SelectionDAGISel.cpp revision 789cb5df9ca61f8a3794a4fbde7cc020fd00a02a
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/TargetTransformInfo.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/FunctionLoweringInfo.h" 25#include "llvm/CodeGen/GCMetadata.h" 26#include "llvm/CodeGen/GCStrategy.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/Constants.h" 37#include "llvm/IR/Function.h" 38#include "llvm/IR/InlineAsm.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/IntrinsicInst.h" 41#include "llvm/IR/Intrinsics.h" 42#include "llvm/IR/LLVMContext.h" 43#include "llvm/IR/Module.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLibraryInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "llvm/Target/TargetOptions.h" 55#include "llvm/Target/TargetRegisterInfo.h" 56#include "llvm/Target/TargetSubtargetInfo.h" 57#include "llvm/Transforms/Utils/BasicBlockUtils.h" 58#include <algorithm> 59using namespace llvm; 60 61STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 62STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 63STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 64STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 65STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66 67#ifndef NDEBUG 68static cl::opt<bool> 69EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 70 cl::desc("Enable extra verbose messages in the \"fast\" " 71 "instruction selector")); 72 // Terminators 73STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 74STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 75STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 76STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 77STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 78STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 79STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 80 81 // Standard binary operators... 82STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 83STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 84STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 85STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 86STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 87STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 88STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 89STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 90STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 91STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 92STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 93STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 94 95 // Logical operators... 96STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 97STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 98STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 99 100 // Memory instructions... 101STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 102STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 103STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 104STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 105STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 106STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 107STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 108 109 // Convert instructions... 110STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 111STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 112STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 113STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 114STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 115STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 116STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 117STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 118STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 119STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 120STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 121STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 122 123 // Other instructions... 124STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 125STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 126STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 127STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 128STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 129STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 130STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 131STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 132STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 133STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 134STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 135STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 136STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 137STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 138STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 139#endif 140 141static cl::opt<bool> 142EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 143 cl::desc("Enable verbose messages in the \"fast\" " 144 "instruction selector")); 145static cl::opt<bool> 146EnableFastISelAbort("fast-isel-abort", cl::Hidden, 147 cl::desc("Enable abort calls when \"fast\" instruction fails")); 148 149static cl::opt<bool> 150UseMBPI("use-mbpi", 151 cl::desc("use Machine Branch Probability Info"), 152 cl::init(true), cl::Hidden); 153 154#ifndef NDEBUG 155static cl::opt<bool> 156ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 157 cl::desc("Pop up a window to show dags before the first " 158 "dag combine pass")); 159static cl::opt<bool> 160ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 161 cl::desc("Pop up a window to show dags before legalize types")); 162static cl::opt<bool> 163ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 164 cl::desc("Pop up a window to show dags before legalize")); 165static cl::opt<bool> 166ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the second " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before the post legalize types" 172 " dag combine pass")); 173static cl::opt<bool> 174ViewISelDAGs("view-isel-dags", cl::Hidden, 175 cl::desc("Pop up a window to show isel dags as they are selected")); 176static cl::opt<bool> 177ViewSchedDAGs("view-sched-dags", cl::Hidden, 178 cl::desc("Pop up a window to show sched dags as they are processed")); 179static cl::opt<bool> 180ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 181 cl::desc("Pop up a window to show SUnit dags after they are processed")); 182#else 183static const bool ViewDAGCombine1 = false, 184 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 185 ViewDAGCombine2 = false, 186 ViewDAGCombineLT = false, 187 ViewISelDAGs = false, ViewSchedDAGs = false, 188 ViewSUnitDAGs = false; 189#endif 190 191//===---------------------------------------------------------------------===// 192/// 193/// RegisterScheduler class - Track the registration of instruction schedulers. 194/// 195//===---------------------------------------------------------------------===// 196MachinePassRegistry RegisterScheduler::Registry; 197 198//===---------------------------------------------------------------------===// 199/// 200/// ISHeuristic command line option for instruction schedulers. 201/// 202//===---------------------------------------------------------------------===// 203static cl::opt<RegisterScheduler::FunctionPassCtor, false, 204 RegisterPassParser<RegisterScheduler> > 205ISHeuristic("pre-RA-sched", 206 cl::init(&createDefaultScheduler), 207 cl::desc("Instruction schedulers available (before register" 208 " allocation):")); 209 210static RegisterScheduler 211defaultListDAGScheduler("default", "Best scheduler for the target", 212 createDefaultScheduler); 213 214namespace llvm { 215 //===--------------------------------------------------------------------===// 216 /// createDefaultScheduler - This creates an instruction scheduler appropriate 217 /// for the target. 218 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 219 CodeGenOpt::Level OptLevel) { 220 const TargetLowering &TLI = IS->getTargetLowering(); 221 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 222 223 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 224 TLI.getSchedulingPreference() == Sched::Source) 225 return createSourceListDAGScheduler(IS, OptLevel); 226 if (TLI.getSchedulingPreference() == Sched::RegPressure) 227 return createBURRListDAGScheduler(IS, OptLevel); 228 if (TLI.getSchedulingPreference() == Sched::Hybrid) 229 return createHybridListDAGScheduler(IS, OptLevel); 230 if (TLI.getSchedulingPreference() == Sched::VLIW) 231 return createVLIWDAGScheduler(IS, OptLevel); 232 assert(TLI.getSchedulingPreference() == Sched::ILP && 233 "Unknown sched type!"); 234 return createILPListDAGScheduler(IS, OptLevel); 235 } 236} 237 238// EmitInstrWithCustomInserter - This method should be implemented by targets 239// that mark instructions with the 'usesCustomInserter' flag. These 240// instructions are special in various ways, which require special support to 241// insert. The specified MachineInstr is created but not inserted into any 242// basic blocks, and this method is called to expand it into a sequence of 243// instructions, potentially also creating new basic blocks and control flow. 244// When new basic blocks are inserted and the edges from MBB to its successors 245// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 246// DenseMap. 247MachineBasicBlock * 248TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 249 MachineBasicBlock *MBB) const { 250#ifndef NDEBUG 251 dbgs() << "If a target marks an instruction with " 252 "'usesCustomInserter', it must implement " 253 "TargetLowering::EmitInstrWithCustomInserter!"; 254#endif 255 llvm_unreachable(0); 256} 257 258void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 259 SDNode *Node) const { 260 assert(!MI->hasPostISelHook() && 261 "If a target marks an instruction with 'hasPostISelHook', " 262 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 263} 264 265//===----------------------------------------------------------------------===// 266// SelectionDAGISel code 267//===----------------------------------------------------------------------===// 268 269SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 270 CodeGenOpt::Level OL) : 271 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 272 FuncInfo(new FunctionLoweringInfo(TLI)), 273 CurDAG(new SelectionDAG(tm, OL)), 274 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 275 GFI(), 276 OptLevel(OL), 277 DAGSize(0) { 278 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 279 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 280 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 281 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 282 } 283 284SelectionDAGISel::~SelectionDAGISel() { 285 delete SDB; 286 delete CurDAG; 287 delete FuncInfo; 288} 289 290void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 291 AU.addRequired<AliasAnalysis>(); 292 AU.addPreserved<AliasAnalysis>(); 293 AU.addRequired<GCModuleInfo>(); 294 AU.addPreserved<GCModuleInfo>(); 295 AU.addRequired<TargetLibraryInfo>(); 296 if (UseMBPI && OptLevel != CodeGenOpt::None) 297 AU.addRequired<BranchProbabilityInfo>(); 298 MachineFunctionPass::getAnalysisUsage(AU); 299} 300 301/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 302/// may trap on it. In this case we have to split the edge so that the path 303/// through the predecessor block that doesn't go to the phi block doesn't 304/// execute the possibly trapping instruction. 305/// 306/// This is required for correctness, so it must be done at -O0. 307/// 308static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 309 // Loop for blocks with phi nodes. 310 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 311 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 312 if (PN == 0) continue; 313 314 ReprocessBlock: 315 // For each block with a PHI node, check to see if any of the input values 316 // are potentially trapping constant expressions. Constant expressions are 317 // the only potentially trapping value that can occur as the argument to a 318 // PHI. 319 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 320 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 321 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 322 if (CE == 0 || !CE->canTrap()) continue; 323 324 // The only case we have to worry about is when the edge is critical. 325 // Since this block has a PHI Node, we assume it has multiple input 326 // edges: check to see if the pred has multiple successors. 327 BasicBlock *Pred = PN->getIncomingBlock(i); 328 if (Pred->getTerminator()->getNumSuccessors() == 1) 329 continue; 330 331 // Okay, we have to split this edge. 332 SplitCriticalEdge(Pred->getTerminator(), 333 GetSuccessorNumber(Pred, BB), SDISel, true); 334 goto ReprocessBlock; 335 } 336 } 337} 338 339bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 340 // Do some sanity-checking on the command-line options. 341 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 342 "-fast-isel-verbose requires -fast-isel"); 343 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 344 "-fast-isel-abort requires -fast-isel"); 345 346 const Function &Fn = *mf.getFunction(); 347 const TargetInstrInfo &TII = *TM.getInstrInfo(); 348 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 349 350 MF = &mf; 351 RegInfo = &MF->getRegInfo(); 352 AA = &getAnalysis<AliasAnalysis>(); 353 LibInfo = &getAnalysis<TargetLibraryInfo>(); 354 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 355 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 356 357 TargetSubtargetInfo &ST = 358 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 359 ST.resetSubtargetFeatures(MF); 360 361 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 362 363 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 364 365 CurDAG->init(*MF, TTI); 366 FuncInfo->set(Fn, *MF); 367 368 if (UseMBPI && OptLevel != CodeGenOpt::None) 369 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 370 else 371 FuncInfo->BPI = 0; 372 373 SDB->init(GFI, *AA, LibInfo); 374 375 SelectAllBasicBlocks(Fn); 376 377 // If the first basic block in the function has live ins that need to be 378 // copied into vregs, emit the copies into the top of the block before 379 // emitting the code for the block. 380 MachineBasicBlock *EntryMBB = MF->begin(); 381 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 382 383 DenseMap<unsigned, unsigned> LiveInMap; 384 if (!FuncInfo->ArgDbgValues.empty()) 385 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 386 E = RegInfo->livein_end(); LI != E; ++LI) 387 if (LI->second) 388 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 389 390 // Insert DBG_VALUE instructions for function arguments to the entry block. 391 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 392 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 393 unsigned Reg = MI->getOperand(0).getReg(); 394 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 395 EntryMBB->insert(EntryMBB->begin(), MI); 396 else { 397 MachineInstr *Def = RegInfo->getVRegDef(Reg); 398 MachineBasicBlock::iterator InsertPos = Def; 399 // FIXME: VR def may not be in entry block. 400 Def->getParent()->insert(llvm::next(InsertPos), MI); 401 } 402 403 // If Reg is live-in then update debug info to track its copy in a vreg. 404 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 405 if (LDI != LiveInMap.end()) { 406 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 407 MachineBasicBlock::iterator InsertPos = Def; 408 const MDNode *Variable = 409 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 410 unsigned Offset = MI->getOperand(1).getImm(); 411 // Def is never a terminator here, so it is ok to increment InsertPos. 412 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 413 TII.get(TargetOpcode::DBG_VALUE)) 414 .addReg(LDI->second, RegState::Debug) 415 .addImm(Offset).addMetadata(Variable); 416 417 // If this vreg is directly copied into an exported register then 418 // that COPY instructions also need DBG_VALUE, if it is the only 419 // user of LDI->second. 420 MachineInstr *CopyUseMI = NULL; 421 for (MachineRegisterInfo::use_iterator 422 UI = RegInfo->use_begin(LDI->second); 423 MachineInstr *UseMI = UI.skipInstruction();) { 424 if (UseMI->isDebugValue()) continue; 425 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 426 CopyUseMI = UseMI; continue; 427 } 428 // Otherwise this is another use or second copy use. 429 CopyUseMI = NULL; break; 430 } 431 if (CopyUseMI) { 432 MachineInstr *NewMI = 433 BuildMI(*MF, CopyUseMI->getDebugLoc(), 434 TII.get(TargetOpcode::DBG_VALUE)) 435 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 436 .addImm(Offset).addMetadata(Variable); 437 MachineBasicBlock::iterator Pos = CopyUseMI; 438 EntryMBB->insertAfter(Pos, NewMI); 439 } 440 } 441 } 442 443 // Determine if there are any calls in this machine function. 444 MachineFrameInfo *MFI = MF->getFrameInfo(); 445 if (!MFI->hasCalls()) { 446 for (MachineFunction::const_iterator 447 I = MF->begin(), E = MF->end(); I != E; ++I) { 448 const MachineBasicBlock *MBB = I; 449 for (MachineBasicBlock::const_iterator 450 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 451 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 452 453 if ((MCID.isCall() && !MCID.isReturn()) || 454 II->isStackAligningInlineAsm()) { 455 MFI->setHasCalls(true); 456 goto done; 457 } 458 } 459 } 460 } 461 462 done: 463 // Determine if there is a call to setjmp in the machine function. 464 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 465 466 // Replace forward-declared registers with the registers containing 467 // the desired value. 468 MachineRegisterInfo &MRI = MF->getRegInfo(); 469 for (DenseMap<unsigned, unsigned>::iterator 470 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 471 I != E; ++I) { 472 unsigned From = I->first; 473 unsigned To = I->second; 474 // If To is also scheduled to be replaced, find what its ultimate 475 // replacement is. 476 for (;;) { 477 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 478 if (J == E) break; 479 To = J->second; 480 } 481 // Replace it. 482 MRI.replaceRegWith(From, To); 483 } 484 485 // Freeze the set of reserved registers now that MachineFrameInfo has been 486 // set up. All the information required by getReservedRegs() should be 487 // available now. 488 MRI.freezeReservedRegs(*MF); 489 490 // Release function-specific state. SDB and CurDAG are already cleared 491 // at this point. 492 FuncInfo->clear(); 493 494 return true; 495} 496 497void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 498 BasicBlock::const_iterator End, 499 bool &HadTailCall) { 500 // Lower all of the non-terminator instructions. If a call is emitted 501 // as a tail call, cease emitting nodes for this block. Terminators 502 // are handled below. 503 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 504 SDB->visit(*I); 505 506 // Make sure the root of the DAG is up-to-date. 507 CurDAG->setRoot(SDB->getControlRoot()); 508 HadTailCall = SDB->HasTailCall; 509 SDB->clear(); 510 511 // Final step, emit the lowered DAG as machine code. 512 CodeGenAndEmitDAG(); 513} 514 515void SelectionDAGISel::ComputeLiveOutVRegInfo() { 516 SmallPtrSet<SDNode*, 128> VisitedNodes; 517 SmallVector<SDNode*, 128> Worklist; 518 519 Worklist.push_back(CurDAG->getRoot().getNode()); 520 521 APInt KnownZero; 522 APInt KnownOne; 523 524 do { 525 SDNode *N = Worklist.pop_back_val(); 526 527 // If we've already seen this node, ignore it. 528 if (!VisitedNodes.insert(N)) 529 continue; 530 531 // Otherwise, add all chain operands to the worklist. 532 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 533 if (N->getOperand(i).getValueType() == MVT::Other) 534 Worklist.push_back(N->getOperand(i).getNode()); 535 536 // If this is a CopyToReg with a vreg dest, process it. 537 if (N->getOpcode() != ISD::CopyToReg) 538 continue; 539 540 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 541 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 542 continue; 543 544 // Ignore non-scalar or non-integer values. 545 SDValue Src = N->getOperand(2); 546 EVT SrcVT = Src.getValueType(); 547 if (!SrcVT.isInteger() || SrcVT.isVector()) 548 continue; 549 550 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 551 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 552 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 553 } while (!Worklist.empty()); 554} 555 556void SelectionDAGISel::CodeGenAndEmitDAG() { 557 std::string GroupName; 558 if (TimePassesIsEnabled) 559 GroupName = "Instruction Selection and Scheduling"; 560 std::string BlockName; 561 int BlockNumber = -1; 562 (void)BlockNumber; 563#ifdef NDEBUG 564 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 565 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 566 ViewSUnitDAGs) 567#endif 568 { 569 BlockNumber = FuncInfo->MBB->getNumber(); 570 BlockName = MF->getName().str() + ":" + 571 FuncInfo->MBB->getBasicBlock()->getName().str(); 572 } 573 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 574 << " '" << BlockName << "'\n"; CurDAG->dump()); 575 576 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 577 578 // Run the DAG combiner in pre-legalize mode. 579 { 580 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 581 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 582 } 583 584 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 585 << " '" << BlockName << "'\n"; CurDAG->dump()); 586 587 // Second step, hack on the DAG until it only uses operations and types that 588 // the target supports. 589 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 590 BlockName); 591 592 bool Changed; 593 { 594 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 595 Changed = CurDAG->LegalizeTypes(); 596 } 597 598 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 599 << " '" << BlockName << "'\n"; CurDAG->dump()); 600 601 if (Changed) { 602 if (ViewDAGCombineLT) 603 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 604 605 // Run the DAG combiner in post-type-legalize mode. 606 { 607 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 608 TimePassesIsEnabled); 609 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 610 } 611 612 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 613 << " '" << BlockName << "'\n"; CurDAG->dump()); 614 } 615 616 { 617 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 618 Changed = CurDAG->LegalizeVectors(); 619 } 620 621 if (Changed) { 622 { 623 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 624 CurDAG->LegalizeTypes(); 625 } 626 627 if (ViewDAGCombineLT) 628 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 629 630 // Run the DAG combiner in post-type-legalize mode. 631 { 632 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 633 TimePassesIsEnabled); 634 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 635 } 636 637 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 638 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 639 } 640 641 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 642 643 { 644 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 645 CurDAG->Legalize(); 646 } 647 648 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 649 << " '" << BlockName << "'\n"; CurDAG->dump()); 650 651 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 652 653 // Run the DAG combiner in post-legalize mode. 654 { 655 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 656 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 657 } 658 659 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 660 << " '" << BlockName << "'\n"; CurDAG->dump()); 661 662 if (OptLevel != CodeGenOpt::None) 663 ComputeLiveOutVRegInfo(); 664 665 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 666 667 // Third, instruction select all of the operations to machine code, adding the 668 // code to the MachineBasicBlock. 669 { 670 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 671 DoInstructionSelection(); 672 } 673 674 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 675 << " '" << BlockName << "'\n"; CurDAG->dump()); 676 677 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 678 679 // Schedule machine code. 680 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 681 { 682 NamedRegionTimer T("Instruction Scheduling", GroupName, 683 TimePassesIsEnabled); 684 Scheduler->Run(CurDAG, FuncInfo->MBB); 685 } 686 687 if (ViewSUnitDAGs) Scheduler->viewGraph(); 688 689 // Emit machine code to BB. This can change 'BB' to the last block being 690 // inserted into. 691 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 692 { 693 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 694 695 // FuncInfo->InsertPt is passed by reference and set to the end of the 696 // scheduled instructions. 697 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 698 } 699 700 // If the block was split, make sure we update any references that are used to 701 // update PHI nodes later on. 702 if (FirstMBB != LastMBB) 703 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 704 705 // Free the scheduler state. 706 { 707 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 708 TimePassesIsEnabled); 709 delete Scheduler; 710 } 711 712 // Free the SelectionDAG state, now that we're finished with it. 713 CurDAG->clear(); 714} 715 716namespace { 717/// ISelUpdater - helper class to handle updates of the instruction selection 718/// graph. 719class ISelUpdater : public SelectionDAG::DAGUpdateListener { 720 SelectionDAG::allnodes_iterator &ISelPosition; 721public: 722 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 723 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 724 725 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 726 /// deleted is the current ISelPosition node, update ISelPosition. 727 /// 728 virtual void NodeDeleted(SDNode *N, SDNode *E) { 729 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 730 ++ISelPosition; 731 } 732}; 733} // end anonymous namespace 734 735void SelectionDAGISel::DoInstructionSelection() { 736 DEBUG(errs() << "===== Instruction selection begins: BB#" 737 << FuncInfo->MBB->getNumber() 738 << " '" << FuncInfo->MBB->getName() << "'\n"); 739 740 PreprocessISelDAG(); 741 742 // Select target instructions for the DAG. 743 { 744 // Number all nodes with a topological order and set DAGSize. 745 DAGSize = CurDAG->AssignTopologicalOrder(); 746 747 // Create a dummy node (which is not added to allnodes), that adds 748 // a reference to the root node, preventing it from being deleted, 749 // and tracking any changes of the root. 750 HandleSDNode Dummy(CurDAG->getRoot()); 751 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 752 ++ISelPosition; 753 754 // Make sure that ISelPosition gets properly updated when nodes are deleted 755 // in calls made from this function. 756 ISelUpdater ISU(*CurDAG, ISelPosition); 757 758 // The AllNodes list is now topological-sorted. Visit the 759 // nodes by starting at the end of the list (the root of the 760 // graph) and preceding back toward the beginning (the entry 761 // node). 762 while (ISelPosition != CurDAG->allnodes_begin()) { 763 SDNode *Node = --ISelPosition; 764 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 765 // but there are currently some corner cases that it misses. Also, this 766 // makes it theoretically possible to disable the DAGCombiner. 767 if (Node->use_empty()) 768 continue; 769 770 SDNode *ResNode = Select(Node); 771 772 // FIXME: This is pretty gross. 'Select' should be changed to not return 773 // anything at all and this code should be nuked with a tactical strike. 774 775 // If node should not be replaced, continue with the next one. 776 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 777 continue; 778 // Replace node. 779 if (ResNode) 780 ReplaceUses(Node, ResNode); 781 782 // If after the replacement this node is not used any more, 783 // remove this dead node. 784 if (Node->use_empty()) // Don't delete EntryToken, etc. 785 CurDAG->RemoveDeadNode(Node); 786 } 787 788 CurDAG->setRoot(Dummy.getValue()); 789 } 790 791 DEBUG(errs() << "===== Instruction selection ends:\n"); 792 793 PostprocessISelDAG(); 794} 795 796/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 797/// do other setup for EH landing-pad blocks. 798void SelectionDAGISel::PrepareEHLandingPad() { 799 MachineBasicBlock *MBB = FuncInfo->MBB; 800 801 // Add a label to mark the beginning of the landing pad. Deletion of the 802 // landing pad can thus be detected via the MachineModuleInfo. 803 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 804 805 // Assign the call site to the landing pad's begin label. 806 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 807 808 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 809 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 810 .addSym(Label); 811 812 // Mark exception register as live in. 813 unsigned Reg = TLI.getExceptionPointerRegister(); 814 if (Reg) MBB->addLiveIn(Reg); 815 816 // Mark exception selector register as live in. 817 Reg = TLI.getExceptionSelectorRegister(); 818 if (Reg) MBB->addLiveIn(Reg); 819} 820 821/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 822/// load into the specified FoldInst. Note that we could have a sequence where 823/// multiple LLVM IR instructions are folded into the same machineinstr. For 824/// example we could have: 825/// A: x = load i32 *P 826/// B: y = icmp A, 42 827/// C: br y, ... 828/// 829/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 830/// any other folded instructions) because it is between A and C. 831/// 832/// If we succeed in folding the load into the operation, return true. 833/// 834bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 835 const Instruction *FoldInst, 836 FastISel *FastIS) { 837 // We know that the load has a single use, but don't know what it is. If it 838 // isn't one of the folded instructions, then we can't succeed here. Handle 839 // this by scanning the single-use users of the load until we get to FoldInst. 840 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 841 842 const Instruction *TheUser = LI->use_back(); 843 while (TheUser != FoldInst && // Scan up until we find FoldInst. 844 // Stay in the right block. 845 TheUser->getParent() == FoldInst->getParent() && 846 --MaxUsers) { // Don't scan too far. 847 // If there are multiple or no uses of this instruction, then bail out. 848 if (!TheUser->hasOneUse()) 849 return false; 850 851 TheUser = TheUser->use_back(); 852 } 853 854 // If we didn't find the fold instruction, then we failed to collapse the 855 // sequence. 856 if (TheUser != FoldInst) 857 return false; 858 859 // Don't try to fold volatile loads. Target has to deal with alignment 860 // constraints. 861 if (LI->isVolatile()) return false; 862 863 // Figure out which vreg this is going into. If there is no assigned vreg yet 864 // then there actually was no reference to it. Perhaps the load is referenced 865 // by a dead instruction. 866 unsigned LoadReg = FastIS->getRegForValue(LI); 867 if (LoadReg == 0) 868 return false; 869 870 // Check to see what the uses of this vreg are. If it has no uses, or more 871 // than one use (at the machine instr level) then we can't fold it. 872 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 873 if (RI == RegInfo->reg_end()) 874 return false; 875 876 // See if there is exactly one use of the vreg. If there are multiple uses, 877 // then the instruction got lowered to multiple machine instructions or the 878 // use of the loaded value ended up being multiple operands of the result, in 879 // either case, we can't fold this. 880 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 881 if (PostRI != RegInfo->reg_end()) 882 return false; 883 884 assert(RI.getOperand().isUse() && 885 "The only use of the vreg must be a use, we haven't emitted the def!"); 886 887 MachineInstr *User = &*RI; 888 889 // Set the insertion point properly. Folding the load can cause generation of 890 // other random instructions (like sign extends) for addressing modes, make 891 // sure they get inserted in a logical place before the new instruction. 892 FuncInfo->InsertPt = User; 893 FuncInfo->MBB = User->getParent(); 894 895 // Ask the target to try folding the load. 896 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 897} 898 899/// isFoldedOrDeadInstruction - Return true if the specified instruction is 900/// side-effect free and is either dead or folded into a generated instruction. 901/// Return false if it needs to be emitted. 902static bool isFoldedOrDeadInstruction(const Instruction *I, 903 FunctionLoweringInfo *FuncInfo) { 904 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 905 !isa<TerminatorInst>(I) && // Terminators aren't folded. 906 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 907 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 908 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 909} 910 911#ifndef NDEBUG 912// Collect per Instruction statistics for fast-isel misses. Only those 913// instructions that cause the bail are accounted for. It does not account for 914// instructions higher in the block. Thus, summing the per instructions stats 915// will not add up to what is reported by NumFastIselFailures. 916static void collectFailStats(const Instruction *I) { 917 switch (I->getOpcode()) { 918 default: assert (0 && "<Invalid operator> "); 919 920 // Terminators 921 case Instruction::Ret: NumFastIselFailRet++; return; 922 case Instruction::Br: NumFastIselFailBr++; return; 923 case Instruction::Switch: NumFastIselFailSwitch++; return; 924 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 925 case Instruction::Invoke: NumFastIselFailInvoke++; return; 926 case Instruction::Resume: NumFastIselFailResume++; return; 927 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 928 929 // Standard binary operators... 930 case Instruction::Add: NumFastIselFailAdd++; return; 931 case Instruction::FAdd: NumFastIselFailFAdd++; return; 932 case Instruction::Sub: NumFastIselFailSub++; return; 933 case Instruction::FSub: NumFastIselFailFSub++; return; 934 case Instruction::Mul: NumFastIselFailMul++; return; 935 case Instruction::FMul: NumFastIselFailFMul++; return; 936 case Instruction::UDiv: NumFastIselFailUDiv++; return; 937 case Instruction::SDiv: NumFastIselFailSDiv++; return; 938 case Instruction::FDiv: NumFastIselFailFDiv++; return; 939 case Instruction::URem: NumFastIselFailURem++; return; 940 case Instruction::SRem: NumFastIselFailSRem++; return; 941 case Instruction::FRem: NumFastIselFailFRem++; return; 942 943 // Logical operators... 944 case Instruction::And: NumFastIselFailAnd++; return; 945 case Instruction::Or: NumFastIselFailOr++; return; 946 case Instruction::Xor: NumFastIselFailXor++; return; 947 948 // Memory instructions... 949 case Instruction::Alloca: NumFastIselFailAlloca++; return; 950 case Instruction::Load: NumFastIselFailLoad++; return; 951 case Instruction::Store: NumFastIselFailStore++; return; 952 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 953 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 954 case Instruction::Fence: NumFastIselFailFence++; return; 955 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 956 957 // Convert instructions... 958 case Instruction::Trunc: NumFastIselFailTrunc++; return; 959 case Instruction::ZExt: NumFastIselFailZExt++; return; 960 case Instruction::SExt: NumFastIselFailSExt++; return; 961 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 962 case Instruction::FPExt: NumFastIselFailFPExt++; return; 963 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 964 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 965 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 966 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 967 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 968 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 969 case Instruction::BitCast: NumFastIselFailBitCast++; return; 970 971 // Other instructions... 972 case Instruction::ICmp: NumFastIselFailICmp++; return; 973 case Instruction::FCmp: NumFastIselFailFCmp++; return; 974 case Instruction::PHI: NumFastIselFailPHI++; return; 975 case Instruction::Select: NumFastIselFailSelect++; return; 976 case Instruction::Call: NumFastIselFailCall++; return; 977 case Instruction::Shl: NumFastIselFailShl++; return; 978 case Instruction::LShr: NumFastIselFailLShr++; return; 979 case Instruction::AShr: NumFastIselFailAShr++; return; 980 case Instruction::VAArg: NumFastIselFailVAArg++; return; 981 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 982 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 983 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 984 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 985 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 986 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 987 } 988} 989#endif 990 991void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 992 // Initialize the Fast-ISel state, if needed. 993 FastISel *FastIS = 0; 994 if (TM.Options.EnableFastISel) 995 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 996 997 // Iterate over all basic blocks in the function. 998 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 999 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1000 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1001 const BasicBlock *LLVMBB = *I; 1002 1003 if (OptLevel != CodeGenOpt::None) { 1004 bool AllPredsVisited = true; 1005 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1006 PI != PE; ++PI) { 1007 if (!FuncInfo->VisitedBBs.count(*PI)) { 1008 AllPredsVisited = false; 1009 break; 1010 } 1011 } 1012 1013 if (AllPredsVisited) { 1014 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1015 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1016 FuncInfo->ComputePHILiveOutRegInfo(PN); 1017 } else { 1018 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1019 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1020 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1021 } 1022 1023 FuncInfo->VisitedBBs.insert(LLVMBB); 1024 } 1025 1026 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1027 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1028 1029 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1030 BasicBlock::const_iterator const End = LLVMBB->end(); 1031 BasicBlock::const_iterator BI = End; 1032 1033 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1034 1035 // Setup an EH landing-pad block. 1036 if (FuncInfo->MBB->isLandingPad()) 1037 PrepareEHLandingPad(); 1038 1039 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1040 if (FastIS) { 1041 FastIS->startNewBlock(); 1042 1043 // Emit code for any incoming arguments. This must happen before 1044 // beginning FastISel on the entry block. 1045 if (LLVMBB == &Fn.getEntryBlock()) { 1046 // Lower any arguments needed in this block if this is the entry block. 1047 if (!FastIS->LowerArguments()) { 1048 // Call target indepedent SDISel argument lowering code if the target 1049 // specific routine is not successful. 1050 LowerArguments(LLVMBB); 1051 CurDAG->setRoot(SDB->getControlRoot()); 1052 SDB->clear(); 1053 CodeGenAndEmitDAG(); 1054 } 1055 1056 // If we inserted any instructions at the beginning, make a note of 1057 // where they are, so we can be sure to emit subsequent instructions 1058 // after them. 1059 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1060 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1061 else 1062 FastIS->setLastLocalValue(0); 1063 } 1064 1065 unsigned NumFastIselRemaining = std::distance(Begin, End); 1066 // Do FastISel on as many instructions as possible. 1067 for (; BI != Begin; --BI) { 1068 const Instruction *Inst = llvm::prior(BI); 1069 1070 // If we no longer require this instruction, skip it. 1071 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1072 --NumFastIselRemaining; 1073 continue; 1074 } 1075 1076 // Bottom-up: reset the insert pos at the top, after any local-value 1077 // instructions. 1078 FastIS->recomputeInsertPt(); 1079 1080 // Try to select the instruction with FastISel. 1081 if (FastIS->SelectInstruction(Inst)) { 1082 --NumFastIselRemaining; 1083 ++NumFastIselSuccess; 1084 // If fast isel succeeded, skip over all the folded instructions, and 1085 // then see if there is a load right before the selected instructions. 1086 // Try to fold the load if so. 1087 const Instruction *BeforeInst = Inst; 1088 while (BeforeInst != Begin) { 1089 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1090 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1091 break; 1092 } 1093 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1094 BeforeInst->hasOneUse() && 1095 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) { 1096 // If we succeeded, don't re-select the load. 1097 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1098 --NumFastIselRemaining; 1099 ++NumFastIselSuccess; 1100 } 1101 continue; 1102 } 1103 1104#ifndef NDEBUG 1105 if (EnableFastISelVerbose2) 1106 collectFailStats(Inst); 1107#endif 1108 1109 // Then handle certain instructions as single-LLVM-Instruction blocks. 1110 if (isa<CallInst>(Inst)) { 1111 1112 if (EnableFastISelVerbose || EnableFastISelAbort) { 1113 dbgs() << "FastISel missed call: "; 1114 Inst->dump(); 1115 } 1116 1117 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1118 unsigned &R = FuncInfo->ValueMap[Inst]; 1119 if (!R) 1120 R = FuncInfo->CreateRegs(Inst->getType()); 1121 } 1122 1123 bool HadTailCall = false; 1124 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1125 SelectBasicBlock(Inst, BI, HadTailCall); 1126 1127 // If the call was emitted as a tail call, we're done with the block. 1128 // We also need to delete any previously emitted instructions. 1129 if (HadTailCall) { 1130 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1131 --BI; 1132 break; 1133 } 1134 1135 // Recompute NumFastIselRemaining as Selection DAG instruction 1136 // selection may have handled the call, input args, etc. 1137 unsigned RemainingNow = std::distance(Begin, BI); 1138 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1139 NumFastIselRemaining = RemainingNow; 1140 continue; 1141 } 1142 1143 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1144 // Don't abort, and use a different message for terminator misses. 1145 NumFastIselFailures += NumFastIselRemaining; 1146 if (EnableFastISelVerbose || EnableFastISelAbort) { 1147 dbgs() << "FastISel missed terminator: "; 1148 Inst->dump(); 1149 } 1150 } else { 1151 NumFastIselFailures += NumFastIselRemaining; 1152 if (EnableFastISelVerbose || EnableFastISelAbort) { 1153 dbgs() << "FastISel miss: "; 1154 Inst->dump(); 1155 } 1156 if (EnableFastISelAbort) 1157 // The "fast" selector couldn't handle something and bailed. 1158 // For the purpose of debugging, just abort. 1159 llvm_unreachable("FastISel didn't select the entire block"); 1160 } 1161 break; 1162 } 1163 1164 FastIS->recomputeInsertPt(); 1165 } else { 1166 // Lower any arguments needed in this block if this is the entry block. 1167 if (LLVMBB == &Fn.getEntryBlock()) 1168 LowerArguments(LLVMBB); 1169 } 1170 1171 if (Begin != BI) 1172 ++NumDAGBlocks; 1173 else 1174 ++NumFastIselBlocks; 1175 1176 if (Begin != BI) { 1177 // Run SelectionDAG instruction selection on the remainder of the block 1178 // not handled by FastISel. If FastISel is not run, this is the entire 1179 // block. 1180 bool HadTailCall; 1181 SelectBasicBlock(Begin, BI, HadTailCall); 1182 } 1183 1184 FinishBasicBlock(); 1185 FuncInfo->PHINodesToUpdate.clear(); 1186 } 1187 1188 delete FastIS; 1189 SDB->clearDanglingDebugInfo(); 1190} 1191 1192void 1193SelectionDAGISel::FinishBasicBlock() { 1194 1195 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1196 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1197 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1198 dbgs() << "Node " << i << " : (" 1199 << FuncInfo->PHINodesToUpdate[i].first 1200 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1201 1202 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1203 // PHI nodes in successors. 1204 if (SDB->SwitchCases.empty() && 1205 SDB->JTCases.empty() && 1206 SDB->BitTestCases.empty()) { 1207 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1208 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1209 assert(PHI->isPHI() && 1210 "This is not a machine PHI node that we are updating!"); 1211 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1212 continue; 1213 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1214 } 1215 return; 1216 } 1217 1218 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1219 // Lower header first, if it wasn't already lowered 1220 if (!SDB->BitTestCases[i].Emitted) { 1221 // Set the current basic block to the mbb we wish to insert the code into 1222 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1223 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1224 // Emit the code 1225 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1226 CurDAG->setRoot(SDB->getRoot()); 1227 SDB->clear(); 1228 CodeGenAndEmitDAG(); 1229 } 1230 1231 uint32_t UnhandledWeight = 0; 1232 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1233 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1234 1235 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1236 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1237 // Set the current basic block to the mbb we wish to insert the code into 1238 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1239 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1240 // Emit the code 1241 if (j+1 != ej) 1242 SDB->visitBitTestCase(SDB->BitTestCases[i], 1243 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1244 UnhandledWeight, 1245 SDB->BitTestCases[i].Reg, 1246 SDB->BitTestCases[i].Cases[j], 1247 FuncInfo->MBB); 1248 else 1249 SDB->visitBitTestCase(SDB->BitTestCases[i], 1250 SDB->BitTestCases[i].Default, 1251 UnhandledWeight, 1252 SDB->BitTestCases[i].Reg, 1253 SDB->BitTestCases[i].Cases[j], 1254 FuncInfo->MBB); 1255 1256 1257 CurDAG->setRoot(SDB->getRoot()); 1258 SDB->clear(); 1259 CodeGenAndEmitDAG(); 1260 } 1261 1262 // Update PHI Nodes 1263 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1264 pi != pe; ++pi) { 1265 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1266 MachineBasicBlock *PHIBB = PHI->getParent(); 1267 assert(PHI->isPHI() && 1268 "This is not a machine PHI node that we are updating!"); 1269 // This is "default" BB. We have two jumps to it. From "header" BB and 1270 // from last "case" BB. 1271 if (PHIBB == SDB->BitTestCases[i].Default) 1272 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1273 .addMBB(SDB->BitTestCases[i].Parent) 1274 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1275 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1276 // One of "cases" BB. 1277 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1278 j != ej; ++j) { 1279 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1280 if (cBB->isSuccessor(PHIBB)) 1281 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1282 } 1283 } 1284 } 1285 SDB->BitTestCases.clear(); 1286 1287 // If the JumpTable record is filled in, then we need to emit a jump table. 1288 // Updating the PHI nodes is tricky in this case, since we need to determine 1289 // whether the PHI is a successor of the range check MBB or the jump table MBB 1290 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1291 // Lower header first, if it wasn't already lowered 1292 if (!SDB->JTCases[i].first.Emitted) { 1293 // Set the current basic block to the mbb we wish to insert the code into 1294 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1295 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1296 // Emit the code 1297 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1298 FuncInfo->MBB); 1299 CurDAG->setRoot(SDB->getRoot()); 1300 SDB->clear(); 1301 CodeGenAndEmitDAG(); 1302 } 1303 1304 // Set the current basic block to the mbb we wish to insert the code into 1305 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1306 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1307 // Emit the code 1308 SDB->visitJumpTable(SDB->JTCases[i].second); 1309 CurDAG->setRoot(SDB->getRoot()); 1310 SDB->clear(); 1311 CodeGenAndEmitDAG(); 1312 1313 // Update PHI Nodes 1314 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1315 pi != pe; ++pi) { 1316 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1317 MachineBasicBlock *PHIBB = PHI->getParent(); 1318 assert(PHI->isPHI() && 1319 "This is not a machine PHI node that we are updating!"); 1320 // "default" BB. We can go there only from header BB. 1321 if (PHIBB == SDB->JTCases[i].second.Default) 1322 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1323 .addMBB(SDB->JTCases[i].first.HeaderBB); 1324 // JT BB. Just iterate over successors here 1325 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1326 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1327 } 1328 } 1329 SDB->JTCases.clear(); 1330 1331 // If the switch block involved a branch to one of the actual successors, we 1332 // need to update PHI nodes in that block. 1333 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1334 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1335 assert(PHI->isPHI() && 1336 "This is not a machine PHI node that we are updating!"); 1337 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1338 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1339 } 1340 1341 // If we generated any switch lowering information, build and codegen any 1342 // additional DAGs necessary. 1343 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1344 // Set the current basic block to the mbb we wish to insert the code into 1345 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1346 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1347 1348 // Determine the unique successors. 1349 SmallVector<MachineBasicBlock *, 2> Succs; 1350 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1351 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1352 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1353 1354 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1355 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1356 CurDAG->setRoot(SDB->getRoot()); 1357 SDB->clear(); 1358 CodeGenAndEmitDAG(); 1359 1360 // Remember the last block, now that any splitting is done, for use in 1361 // populating PHI nodes in successors. 1362 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1363 1364 // Handle any PHI nodes in successors of this chunk, as if we were coming 1365 // from the original BB before switch expansion. Note that PHI nodes can 1366 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1367 // handle them the right number of times. 1368 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1369 FuncInfo->MBB = Succs[i]; 1370 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1371 // FuncInfo->MBB may have been removed from the CFG if a branch was 1372 // constant folded. 1373 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1374 for (MachineBasicBlock::iterator 1375 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1376 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1377 MachineInstrBuilder PHI(*MF, MBBI); 1378 // This value for this PHI node is recorded in PHINodesToUpdate. 1379 for (unsigned pn = 0; ; ++pn) { 1380 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1381 "Didn't find PHI entry!"); 1382 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1383 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1384 break; 1385 } 1386 } 1387 } 1388 } 1389 } 1390 } 1391 SDB->SwitchCases.clear(); 1392} 1393 1394 1395/// Create the scheduler. If a specific scheduler was specified 1396/// via the SchedulerRegistry, use it, otherwise select the 1397/// one preferred by the target. 1398/// 1399ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1400 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1401 1402 if (!Ctor) { 1403 Ctor = ISHeuristic; 1404 RegisterScheduler::setDefault(Ctor); 1405 } 1406 1407 return Ctor(this, OptLevel); 1408} 1409 1410//===----------------------------------------------------------------------===// 1411// Helper functions used by the generated instruction selector. 1412//===----------------------------------------------------------------------===// 1413// Calls to these methods are generated by tblgen. 1414 1415/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1416/// the dag combiner simplified the 255, we still want to match. RHS is the 1417/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1418/// specified in the .td file (e.g. 255). 1419bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1420 int64_t DesiredMaskS) const { 1421 const APInt &ActualMask = RHS->getAPIntValue(); 1422 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1423 1424 // If the actual mask exactly matches, success! 1425 if (ActualMask == DesiredMask) 1426 return true; 1427 1428 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1429 if (ActualMask.intersects(~DesiredMask)) 1430 return false; 1431 1432 // Otherwise, the DAG Combiner may have proven that the value coming in is 1433 // either already zero or is not demanded. Check for known zero input bits. 1434 APInt NeededMask = DesiredMask & ~ActualMask; 1435 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1436 return true; 1437 1438 // TODO: check to see if missing bits are just not demanded. 1439 1440 // Otherwise, this pattern doesn't match. 1441 return false; 1442} 1443 1444/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1445/// the dag combiner simplified the 255, we still want to match. RHS is the 1446/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1447/// specified in the .td file (e.g. 255). 1448bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1449 int64_t DesiredMaskS) const { 1450 const APInt &ActualMask = RHS->getAPIntValue(); 1451 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1452 1453 // If the actual mask exactly matches, success! 1454 if (ActualMask == DesiredMask) 1455 return true; 1456 1457 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1458 if (ActualMask.intersects(~DesiredMask)) 1459 return false; 1460 1461 // Otherwise, the DAG Combiner may have proven that the value coming in is 1462 // either already zero or is not demanded. Check for known zero input bits. 1463 APInt NeededMask = DesiredMask & ~ActualMask; 1464 1465 APInt KnownZero, KnownOne; 1466 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1467 1468 // If all the missing bits in the or are already known to be set, match! 1469 if ((NeededMask & KnownOne) == NeededMask) 1470 return true; 1471 1472 // TODO: check to see if missing bits are just not demanded. 1473 1474 // Otherwise, this pattern doesn't match. 1475 return false; 1476} 1477 1478 1479/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1480/// by tblgen. Others should not call it. 1481void SelectionDAGISel:: 1482SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1483 std::vector<SDValue> InOps; 1484 std::swap(InOps, Ops); 1485 1486 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1487 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1488 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1489 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1490 1491 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1492 if (InOps[e-1].getValueType() == MVT::Glue) 1493 --e; // Don't process a glue operand if it is here. 1494 1495 while (i != e) { 1496 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1497 if (!InlineAsm::isMemKind(Flags)) { 1498 // Just skip over this operand, copying the operands verbatim. 1499 Ops.insert(Ops.end(), InOps.begin()+i, 1500 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1501 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1502 } else { 1503 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1504 "Memory operand with multiple values?"); 1505 // Otherwise, this is a memory operand. Ask the target to select it. 1506 std::vector<SDValue> SelOps; 1507 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1508 report_fatal_error("Could not match memory address. Inline asm" 1509 " failure!"); 1510 1511 // Add this to the output node. 1512 unsigned NewFlags = 1513 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1514 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1515 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1516 i += 2; 1517 } 1518 } 1519 1520 // Add the glue input back if present. 1521 if (e != InOps.size()) 1522 Ops.push_back(InOps.back()); 1523} 1524 1525/// findGlueUse - Return use of MVT::Glue value produced by the specified 1526/// SDNode. 1527/// 1528static SDNode *findGlueUse(SDNode *N) { 1529 unsigned FlagResNo = N->getNumValues()-1; 1530 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1531 SDUse &Use = I.getUse(); 1532 if (Use.getResNo() == FlagResNo) 1533 return Use.getUser(); 1534 } 1535 return NULL; 1536} 1537 1538/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1539/// This function recursively traverses up the operand chain, ignoring 1540/// certain nodes. 1541static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1542 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1543 bool IgnoreChains) { 1544 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1545 // greater than all of its (recursive) operands. If we scan to a point where 1546 // 'use' is smaller than the node we're scanning for, then we know we will 1547 // never find it. 1548 // 1549 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1550 // happen because we scan down to newly selected nodes in the case of glue 1551 // uses. 1552 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1553 return false; 1554 1555 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1556 // won't fail if we scan it again. 1557 if (!Visited.insert(Use)) 1558 return false; 1559 1560 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1561 // Ignore chain uses, they are validated by HandleMergeInputChains. 1562 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1563 continue; 1564 1565 SDNode *N = Use->getOperand(i).getNode(); 1566 if (N == Def) { 1567 if (Use == ImmedUse || Use == Root) 1568 continue; // We are not looking for immediate use. 1569 assert(N != Root); 1570 return true; 1571 } 1572 1573 // Traverse up the operand chain. 1574 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1575 return true; 1576 } 1577 return false; 1578} 1579 1580/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1581/// operand node N of U during instruction selection that starts at Root. 1582bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1583 SDNode *Root) const { 1584 if (OptLevel == CodeGenOpt::None) return false; 1585 return N.hasOneUse(); 1586} 1587 1588/// IsLegalToFold - Returns true if the specific operand node N of 1589/// U can be folded during instruction selection that starts at Root. 1590bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1591 CodeGenOpt::Level OptLevel, 1592 bool IgnoreChains) { 1593 if (OptLevel == CodeGenOpt::None) return false; 1594 1595 // If Root use can somehow reach N through a path that that doesn't contain 1596 // U then folding N would create a cycle. e.g. In the following 1597 // diagram, Root can reach N through X. If N is folded into into Root, then 1598 // X is both a predecessor and a successor of U. 1599 // 1600 // [N*] // 1601 // ^ ^ // 1602 // / \ // 1603 // [U*] [X]? // 1604 // ^ ^ // 1605 // \ / // 1606 // \ / // 1607 // [Root*] // 1608 // 1609 // * indicates nodes to be folded together. 1610 // 1611 // If Root produces glue, then it gets (even more) interesting. Since it 1612 // will be "glued" together with its glue use in the scheduler, we need to 1613 // check if it might reach N. 1614 // 1615 // [N*] // 1616 // ^ ^ // 1617 // / \ // 1618 // [U*] [X]? // 1619 // ^ ^ // 1620 // \ \ // 1621 // \ | // 1622 // [Root*] | // 1623 // ^ | // 1624 // f | // 1625 // | / // 1626 // [Y] / // 1627 // ^ / // 1628 // f / // 1629 // | / // 1630 // [GU] // 1631 // 1632 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1633 // (call it Fold), then X is a predecessor of GU and a successor of 1634 // Fold. But since Fold and GU are glued together, this will create 1635 // a cycle in the scheduling graph. 1636 1637 // If the node has glue, walk down the graph to the "lowest" node in the 1638 // glueged set. 1639 EVT VT = Root->getValueType(Root->getNumValues()-1); 1640 while (VT == MVT::Glue) { 1641 SDNode *GU = findGlueUse(Root); 1642 if (GU == NULL) 1643 break; 1644 Root = GU; 1645 VT = Root->getValueType(Root->getNumValues()-1); 1646 1647 // If our query node has a glue result with a use, we've walked up it. If 1648 // the user (which has already been selected) has a chain or indirectly uses 1649 // the chain, our WalkChainUsers predicate will not consider it. Because of 1650 // this, we cannot ignore chains in this predicate. 1651 IgnoreChains = false; 1652 } 1653 1654 1655 SmallPtrSet<SDNode*, 16> Visited; 1656 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1657} 1658 1659SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1660 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1661 SelectInlineAsmMemoryOperands(Ops); 1662 1663 std::vector<EVT> VTs; 1664 VTs.push_back(MVT::Other); 1665 VTs.push_back(MVT::Glue); 1666 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1667 VTs, &Ops[0], Ops.size()); 1668 New->setNodeId(-1); 1669 return New.getNode(); 1670} 1671 1672SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1673 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1674} 1675 1676/// GetVBR - decode a vbr encoding whose top bit is set. 1677LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1678GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1679 assert(Val >= 128 && "Not a VBR"); 1680 Val &= 127; // Remove first vbr bit. 1681 1682 unsigned Shift = 7; 1683 uint64_t NextBits; 1684 do { 1685 NextBits = MatcherTable[Idx++]; 1686 Val |= (NextBits&127) << Shift; 1687 Shift += 7; 1688 } while (NextBits & 128); 1689 1690 return Val; 1691} 1692 1693 1694/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1695/// interior glue and chain results to use the new glue and chain results. 1696void SelectionDAGISel:: 1697UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1698 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1699 SDValue InputGlue, 1700 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1701 bool isMorphNodeTo) { 1702 SmallVector<SDNode*, 4> NowDeadNodes; 1703 1704 // Now that all the normal results are replaced, we replace the chain and 1705 // glue results if present. 1706 if (!ChainNodesMatched.empty()) { 1707 assert(InputChain.getNode() != 0 && 1708 "Matched input chains but didn't produce a chain"); 1709 // Loop over all of the nodes we matched that produced a chain result. 1710 // Replace all the chain results with the final chain we ended up with. 1711 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1712 SDNode *ChainNode = ChainNodesMatched[i]; 1713 1714 // If this node was already deleted, don't look at it. 1715 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1716 continue; 1717 1718 // Don't replace the results of the root node if we're doing a 1719 // MorphNodeTo. 1720 if (ChainNode == NodeToMatch && isMorphNodeTo) 1721 continue; 1722 1723 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1724 if (ChainVal.getValueType() == MVT::Glue) 1725 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1726 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1727 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1728 1729 // If the node became dead and we haven't already seen it, delete it. 1730 if (ChainNode->use_empty() && 1731 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1732 NowDeadNodes.push_back(ChainNode); 1733 } 1734 } 1735 1736 // If the result produces glue, update any glue results in the matched 1737 // pattern with the glue result. 1738 if (InputGlue.getNode() != 0) { 1739 // Handle any interior nodes explicitly marked. 1740 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1741 SDNode *FRN = GlueResultNodesMatched[i]; 1742 1743 // If this node was already deleted, don't look at it. 1744 if (FRN->getOpcode() == ISD::DELETED_NODE) 1745 continue; 1746 1747 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1748 "Doesn't have a glue result"); 1749 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1750 InputGlue); 1751 1752 // If the node became dead and we haven't already seen it, delete it. 1753 if (FRN->use_empty() && 1754 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1755 NowDeadNodes.push_back(FRN); 1756 } 1757 } 1758 1759 if (!NowDeadNodes.empty()) 1760 CurDAG->RemoveDeadNodes(NowDeadNodes); 1761 1762 DEBUG(errs() << "ISEL: Match complete!\n"); 1763} 1764 1765enum ChainResult { 1766 CR_Simple, 1767 CR_InducesCycle, 1768 CR_LeadsToInteriorNode 1769}; 1770 1771/// WalkChainUsers - Walk down the users of the specified chained node that is 1772/// part of the pattern we're matching, looking at all of the users we find. 1773/// This determines whether something is an interior node, whether we have a 1774/// non-pattern node in between two pattern nodes (which prevent folding because 1775/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1776/// between pattern nodes (in which case the TF becomes part of the pattern). 1777/// 1778/// The walk we do here is guaranteed to be small because we quickly get down to 1779/// already selected nodes "below" us. 1780static ChainResult 1781WalkChainUsers(const SDNode *ChainedNode, 1782 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1783 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1784 ChainResult Result = CR_Simple; 1785 1786 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1787 E = ChainedNode->use_end(); UI != E; ++UI) { 1788 // Make sure the use is of the chain, not some other value we produce. 1789 if (UI.getUse().getValueType() != MVT::Other) continue; 1790 1791 SDNode *User = *UI; 1792 1793 // If we see an already-selected machine node, then we've gone beyond the 1794 // pattern that we're selecting down into the already selected chunk of the 1795 // DAG. 1796 if (User->isMachineOpcode() || 1797 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1798 continue; 1799 1800 unsigned UserOpcode = User->getOpcode(); 1801 if (UserOpcode == ISD::CopyToReg || 1802 UserOpcode == ISD::CopyFromReg || 1803 UserOpcode == ISD::INLINEASM || 1804 UserOpcode == ISD::EH_LABEL || 1805 UserOpcode == ISD::LIFETIME_START || 1806 UserOpcode == ISD::LIFETIME_END) { 1807 // If their node ID got reset to -1 then they've already been selected. 1808 // Treat them like a MachineOpcode. 1809 if (User->getNodeId() == -1) 1810 continue; 1811 } 1812 1813 // If we have a TokenFactor, we handle it specially. 1814 if (User->getOpcode() != ISD::TokenFactor) { 1815 // If the node isn't a token factor and isn't part of our pattern, then it 1816 // must be a random chained node in between two nodes we're selecting. 1817 // This happens when we have something like: 1818 // x = load ptr 1819 // call 1820 // y = x+4 1821 // store y -> ptr 1822 // Because we structurally match the load/store as a read/modify/write, 1823 // but the call is chained between them. We cannot fold in this case 1824 // because it would induce a cycle in the graph. 1825 if (!std::count(ChainedNodesInPattern.begin(), 1826 ChainedNodesInPattern.end(), User)) 1827 return CR_InducesCycle; 1828 1829 // Otherwise we found a node that is part of our pattern. For example in: 1830 // x = load ptr 1831 // y = x+4 1832 // store y -> ptr 1833 // This would happen when we're scanning down from the load and see the 1834 // store as a user. Record that there is a use of ChainedNode that is 1835 // part of the pattern and keep scanning uses. 1836 Result = CR_LeadsToInteriorNode; 1837 InteriorChainedNodes.push_back(User); 1838 continue; 1839 } 1840 1841 // If we found a TokenFactor, there are two cases to consider: first if the 1842 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1843 // uses of the TF are in our pattern) we just want to ignore it. Second, 1844 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1845 // [Load chain] 1846 // ^ 1847 // | 1848 // [Load] 1849 // ^ ^ 1850 // | \ DAG's like cheese 1851 // / \ do you? 1852 // / | 1853 // [TokenFactor] [Op] 1854 // ^ ^ 1855 // | | 1856 // \ / 1857 // \ / 1858 // [Store] 1859 // 1860 // In this case, the TokenFactor becomes part of our match and we rewrite it 1861 // as a new TokenFactor. 1862 // 1863 // To distinguish these two cases, do a recursive walk down the uses. 1864 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1865 case CR_Simple: 1866 // If the uses of the TokenFactor are just already-selected nodes, ignore 1867 // it, it is "below" our pattern. 1868 continue; 1869 case CR_InducesCycle: 1870 // If the uses of the TokenFactor lead to nodes that are not part of our 1871 // pattern that are not selected, folding would turn this into a cycle, 1872 // bail out now. 1873 return CR_InducesCycle; 1874 case CR_LeadsToInteriorNode: 1875 break; // Otherwise, keep processing. 1876 } 1877 1878 // Okay, we know we're in the interesting interior case. The TokenFactor 1879 // is now going to be considered part of the pattern so that we rewrite its 1880 // uses (it may have uses that are not part of the pattern) with the 1881 // ultimate chain result of the generated code. We will also add its chain 1882 // inputs as inputs to the ultimate TokenFactor we create. 1883 Result = CR_LeadsToInteriorNode; 1884 ChainedNodesInPattern.push_back(User); 1885 InteriorChainedNodes.push_back(User); 1886 continue; 1887 } 1888 1889 return Result; 1890} 1891 1892/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1893/// operation for when the pattern matched at least one node with a chains. The 1894/// input vector contains a list of all of the chained nodes that we match. We 1895/// must determine if this is a valid thing to cover (i.e. matching it won't 1896/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1897/// be used as the input node chain for the generated nodes. 1898static SDValue 1899HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1900 SelectionDAG *CurDAG) { 1901 // Walk all of the chained nodes we've matched, recursively scanning down the 1902 // users of the chain result. This adds any TokenFactor nodes that are caught 1903 // in between chained nodes to the chained and interior nodes list. 1904 SmallVector<SDNode*, 3> InteriorChainedNodes; 1905 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1906 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1907 InteriorChainedNodes) == CR_InducesCycle) 1908 return SDValue(); // Would induce a cycle. 1909 } 1910 1911 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1912 // that we are interested in. Form our input TokenFactor node. 1913 SmallVector<SDValue, 3> InputChains; 1914 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1915 // Add the input chain of this node to the InputChains list (which will be 1916 // the operands of the generated TokenFactor) if it's not an interior node. 1917 SDNode *N = ChainNodesMatched[i]; 1918 if (N->getOpcode() != ISD::TokenFactor) { 1919 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1920 continue; 1921 1922 // Otherwise, add the input chain. 1923 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1924 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1925 InputChains.push_back(InChain); 1926 continue; 1927 } 1928 1929 // If we have a token factor, we want to add all inputs of the token factor 1930 // that are not part of the pattern we're matching. 1931 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1932 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1933 N->getOperand(op).getNode())) 1934 InputChains.push_back(N->getOperand(op)); 1935 } 1936 } 1937 1938 SDValue Res; 1939 if (InputChains.size() == 1) 1940 return InputChains[0]; 1941 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1942 MVT::Other, &InputChains[0], InputChains.size()); 1943} 1944 1945/// MorphNode - Handle morphing a node in place for the selector. 1946SDNode *SelectionDAGISel:: 1947MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1948 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1949 // It is possible we're using MorphNodeTo to replace a node with no 1950 // normal results with one that has a normal result (or we could be 1951 // adding a chain) and the input could have glue and chains as well. 1952 // In this case we need to shift the operands down. 1953 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1954 // than the old isel though. 1955 int OldGlueResultNo = -1, OldChainResultNo = -1; 1956 1957 unsigned NTMNumResults = Node->getNumValues(); 1958 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1959 OldGlueResultNo = NTMNumResults-1; 1960 if (NTMNumResults != 1 && 1961 Node->getValueType(NTMNumResults-2) == MVT::Other) 1962 OldChainResultNo = NTMNumResults-2; 1963 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1964 OldChainResultNo = NTMNumResults-1; 1965 1966 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1967 // that this deletes operands of the old node that become dead. 1968 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1969 1970 // MorphNodeTo can operate in two ways: if an existing node with the 1971 // specified operands exists, it can just return it. Otherwise, it 1972 // updates the node in place to have the requested operands. 1973 if (Res == Node) { 1974 // If we updated the node in place, reset the node ID. To the isel, 1975 // this should be just like a newly allocated machine node. 1976 Res->setNodeId(-1); 1977 } 1978 1979 unsigned ResNumResults = Res->getNumValues(); 1980 // Move the glue if needed. 1981 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1982 (unsigned)OldGlueResultNo != ResNumResults-1) 1983 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1984 SDValue(Res, ResNumResults-1)); 1985 1986 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1987 --ResNumResults; 1988 1989 // Move the chain reference if needed. 1990 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1991 (unsigned)OldChainResultNo != ResNumResults-1) 1992 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1993 SDValue(Res, ResNumResults-1)); 1994 1995 // Otherwise, no replacement happened because the node already exists. Replace 1996 // Uses of the old node with the new one. 1997 if (Res != Node) 1998 CurDAG->ReplaceAllUsesWith(Node, Res); 1999 2000 return Res; 2001} 2002 2003/// CheckSame - Implements OP_CheckSame. 2004LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2005CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2006 SDValue N, 2007 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2008 // Accept if it is exactly the same as a previously recorded node. 2009 unsigned RecNo = MatcherTable[MatcherIndex++]; 2010 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2011 return N == RecordedNodes[RecNo].first; 2012} 2013 2014/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2015LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2016CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2017 const SelectionDAGISel &SDISel) { 2018 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2019} 2020 2021/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2022LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2023CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2024 const SelectionDAGISel &SDISel, SDNode *N) { 2025 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2026} 2027 2028LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2029CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2030 SDNode *N) { 2031 uint16_t Opc = MatcherTable[MatcherIndex++]; 2032 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2033 return N->getOpcode() == Opc; 2034} 2035 2036LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2037CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2038 SDValue N, const TargetLowering &TLI) { 2039 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2040 if (N.getValueType() == VT) return true; 2041 2042 // Handle the case when VT is iPTR. 2043 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 2044} 2045 2046LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2047CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2048 SDValue N, const TargetLowering &TLI, 2049 unsigned ChildNo) { 2050 if (ChildNo >= N.getNumOperands()) 2051 return false; // Match fails if out of range child #. 2052 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2053} 2054 2055 2056LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2057CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2058 SDValue N) { 2059 return cast<CondCodeSDNode>(N)->get() == 2060 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2061} 2062 2063LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2064CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2065 SDValue N, const TargetLowering &TLI) { 2066 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2067 if (cast<VTSDNode>(N)->getVT() == VT) 2068 return true; 2069 2070 // Handle the case when VT is iPTR. 2071 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2072} 2073 2074LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2075CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2076 SDValue N) { 2077 int64_t Val = MatcherTable[MatcherIndex++]; 2078 if (Val & 128) 2079 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2080 2081 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2082 return C != 0 && C->getSExtValue() == Val; 2083} 2084 2085LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2086CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2087 SDValue N, const SelectionDAGISel &SDISel) { 2088 int64_t Val = MatcherTable[MatcherIndex++]; 2089 if (Val & 128) 2090 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2091 2092 if (N->getOpcode() != ISD::AND) return false; 2093 2094 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2095 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2096} 2097 2098LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2099CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2100 SDValue N, const SelectionDAGISel &SDISel) { 2101 int64_t Val = MatcherTable[MatcherIndex++]; 2102 if (Val & 128) 2103 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2104 2105 if (N->getOpcode() != ISD::OR) return false; 2106 2107 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2108 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2109} 2110 2111/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2112/// scope, evaluate the current node. If the current predicate is known to 2113/// fail, set Result=true and return anything. If the current predicate is 2114/// known to pass, set Result=false and return the MatcherIndex to continue 2115/// with. If the current predicate is unknown, set Result=false and return the 2116/// MatcherIndex to continue with. 2117static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2118 unsigned Index, SDValue N, 2119 bool &Result, 2120 const SelectionDAGISel &SDISel, 2121 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2122 switch (Table[Index++]) { 2123 default: 2124 Result = false; 2125 return Index-1; // Could not evaluate this predicate. 2126 case SelectionDAGISel::OPC_CheckSame: 2127 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2128 return Index; 2129 case SelectionDAGISel::OPC_CheckPatternPredicate: 2130 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2131 return Index; 2132 case SelectionDAGISel::OPC_CheckPredicate: 2133 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2134 return Index; 2135 case SelectionDAGISel::OPC_CheckOpcode: 2136 Result = !::CheckOpcode(Table, Index, N.getNode()); 2137 return Index; 2138 case SelectionDAGISel::OPC_CheckType: 2139 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2140 return Index; 2141 case SelectionDAGISel::OPC_CheckChild0Type: 2142 case SelectionDAGISel::OPC_CheckChild1Type: 2143 case SelectionDAGISel::OPC_CheckChild2Type: 2144 case SelectionDAGISel::OPC_CheckChild3Type: 2145 case SelectionDAGISel::OPC_CheckChild4Type: 2146 case SelectionDAGISel::OPC_CheckChild5Type: 2147 case SelectionDAGISel::OPC_CheckChild6Type: 2148 case SelectionDAGISel::OPC_CheckChild7Type: 2149 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2150 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2151 return Index; 2152 case SelectionDAGISel::OPC_CheckCondCode: 2153 Result = !::CheckCondCode(Table, Index, N); 2154 return Index; 2155 case SelectionDAGISel::OPC_CheckValueType: 2156 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2157 return Index; 2158 case SelectionDAGISel::OPC_CheckInteger: 2159 Result = !::CheckInteger(Table, Index, N); 2160 return Index; 2161 case SelectionDAGISel::OPC_CheckAndImm: 2162 Result = !::CheckAndImm(Table, Index, N, SDISel); 2163 return Index; 2164 case SelectionDAGISel::OPC_CheckOrImm: 2165 Result = !::CheckOrImm(Table, Index, N, SDISel); 2166 return Index; 2167 } 2168} 2169 2170namespace { 2171 2172struct MatchScope { 2173 /// FailIndex - If this match fails, this is the index to continue with. 2174 unsigned FailIndex; 2175 2176 /// NodeStack - The node stack when the scope was formed. 2177 SmallVector<SDValue, 4> NodeStack; 2178 2179 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2180 unsigned NumRecordedNodes; 2181 2182 /// NumMatchedMemRefs - The number of matched memref entries. 2183 unsigned NumMatchedMemRefs; 2184 2185 /// InputChain/InputGlue - The current chain/glue 2186 SDValue InputChain, InputGlue; 2187 2188 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2189 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2190}; 2191 2192} 2193 2194SDNode *SelectionDAGISel:: 2195SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2196 unsigned TableSize) { 2197 // FIXME: Should these even be selected? Handle these cases in the caller? 2198 switch (NodeToMatch->getOpcode()) { 2199 default: 2200 break; 2201 case ISD::EntryToken: // These nodes remain the same. 2202 case ISD::BasicBlock: 2203 case ISD::Register: 2204 case ISD::RegisterMask: 2205 //case ISD::VALUETYPE: 2206 //case ISD::CONDCODE: 2207 case ISD::HANDLENODE: 2208 case ISD::MDNODE_SDNODE: 2209 case ISD::TargetConstant: 2210 case ISD::TargetConstantFP: 2211 case ISD::TargetConstantPool: 2212 case ISD::TargetFrameIndex: 2213 case ISD::TargetExternalSymbol: 2214 case ISD::TargetBlockAddress: 2215 case ISD::TargetJumpTable: 2216 case ISD::TargetGlobalTLSAddress: 2217 case ISD::TargetGlobalAddress: 2218 case ISD::TokenFactor: 2219 case ISD::CopyFromReg: 2220 case ISD::CopyToReg: 2221 case ISD::EH_LABEL: 2222 case ISD::LIFETIME_START: 2223 case ISD::LIFETIME_END: 2224 NodeToMatch->setNodeId(-1); // Mark selected. 2225 return 0; 2226 case ISD::AssertSext: 2227 case ISD::AssertZext: 2228 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2229 NodeToMatch->getOperand(0)); 2230 return 0; 2231 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2232 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2233 } 2234 2235 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2236 2237 // Set up the node stack with NodeToMatch as the only node on the stack. 2238 SmallVector<SDValue, 8> NodeStack; 2239 SDValue N = SDValue(NodeToMatch, 0); 2240 NodeStack.push_back(N); 2241 2242 // MatchScopes - Scopes used when matching, if a match failure happens, this 2243 // indicates where to continue checking. 2244 SmallVector<MatchScope, 8> MatchScopes; 2245 2246 // RecordedNodes - This is the set of nodes that have been recorded by the 2247 // state machine. The second value is the parent of the node, or null if the 2248 // root is recorded. 2249 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2250 2251 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2252 // pattern. 2253 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2254 2255 // These are the current input chain and glue for use when generating nodes. 2256 // Various Emit operations change these. For example, emitting a copytoreg 2257 // uses and updates these. 2258 SDValue InputChain, InputGlue; 2259 2260 // ChainNodesMatched - If a pattern matches nodes that have input/output 2261 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2262 // which ones they are. The result is captured into this list so that we can 2263 // update the chain results when the pattern is complete. 2264 SmallVector<SDNode*, 3> ChainNodesMatched; 2265 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2266 2267 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2268 NodeToMatch->dump(CurDAG); 2269 errs() << '\n'); 2270 2271 // Determine where to start the interpreter. Normally we start at opcode #0, 2272 // but if the state machine starts with an OPC_SwitchOpcode, then we 2273 // accelerate the first lookup (which is guaranteed to be hot) with the 2274 // OpcodeOffset table. 2275 unsigned MatcherIndex = 0; 2276 2277 if (!OpcodeOffset.empty()) { 2278 // Already computed the OpcodeOffset table, just index into it. 2279 if (N.getOpcode() < OpcodeOffset.size()) 2280 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2281 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2282 2283 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2284 // Otherwise, the table isn't computed, but the state machine does start 2285 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2286 // is the first time we're selecting an instruction. 2287 unsigned Idx = 1; 2288 while (1) { 2289 // Get the size of this case. 2290 unsigned CaseSize = MatcherTable[Idx++]; 2291 if (CaseSize & 128) 2292 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2293 if (CaseSize == 0) break; 2294 2295 // Get the opcode, add the index to the table. 2296 uint16_t Opc = MatcherTable[Idx++]; 2297 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2298 if (Opc >= OpcodeOffset.size()) 2299 OpcodeOffset.resize((Opc+1)*2); 2300 OpcodeOffset[Opc] = Idx; 2301 Idx += CaseSize; 2302 } 2303 2304 // Okay, do the lookup for the first opcode. 2305 if (N.getOpcode() < OpcodeOffset.size()) 2306 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2307 } 2308 2309 while (1) { 2310 assert(MatcherIndex < TableSize && "Invalid index"); 2311#ifndef NDEBUG 2312 unsigned CurrentOpcodeIndex = MatcherIndex; 2313#endif 2314 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2315 switch (Opcode) { 2316 case OPC_Scope: { 2317 // Okay, the semantics of this operation are that we should push a scope 2318 // then evaluate the first child. However, pushing a scope only to have 2319 // the first check fail (which then pops it) is inefficient. If we can 2320 // determine immediately that the first check (or first several) will 2321 // immediately fail, don't even bother pushing a scope for them. 2322 unsigned FailIndex; 2323 2324 while (1) { 2325 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2326 if (NumToSkip & 128) 2327 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2328 // Found the end of the scope with no match. 2329 if (NumToSkip == 0) { 2330 FailIndex = 0; 2331 break; 2332 } 2333 2334 FailIndex = MatcherIndex+NumToSkip; 2335 2336 unsigned MatcherIndexOfPredicate = MatcherIndex; 2337 (void)MatcherIndexOfPredicate; // silence warning. 2338 2339 // If we can't evaluate this predicate without pushing a scope (e.g. if 2340 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2341 // push the scope and evaluate the full predicate chain. 2342 bool Result; 2343 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2344 Result, *this, RecordedNodes); 2345 if (!Result) 2346 break; 2347 2348 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2349 << "index " << MatcherIndexOfPredicate 2350 << ", continuing at " << FailIndex << "\n"); 2351 ++NumDAGIselRetries; 2352 2353 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2354 // move to the next case. 2355 MatcherIndex = FailIndex; 2356 } 2357 2358 // If the whole scope failed to match, bail. 2359 if (FailIndex == 0) break; 2360 2361 // Push a MatchScope which indicates where to go if the first child fails 2362 // to match. 2363 MatchScope NewEntry; 2364 NewEntry.FailIndex = FailIndex; 2365 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2366 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2367 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2368 NewEntry.InputChain = InputChain; 2369 NewEntry.InputGlue = InputGlue; 2370 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2371 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2372 MatchScopes.push_back(NewEntry); 2373 continue; 2374 } 2375 case OPC_RecordNode: { 2376 // Remember this node, it may end up being an operand in the pattern. 2377 SDNode *Parent = 0; 2378 if (NodeStack.size() > 1) 2379 Parent = NodeStack[NodeStack.size()-2].getNode(); 2380 RecordedNodes.push_back(std::make_pair(N, Parent)); 2381 continue; 2382 } 2383 2384 case OPC_RecordChild0: case OPC_RecordChild1: 2385 case OPC_RecordChild2: case OPC_RecordChild3: 2386 case OPC_RecordChild4: case OPC_RecordChild5: 2387 case OPC_RecordChild6: case OPC_RecordChild7: { 2388 unsigned ChildNo = Opcode-OPC_RecordChild0; 2389 if (ChildNo >= N.getNumOperands()) 2390 break; // Match fails if out of range child #. 2391 2392 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2393 N.getNode())); 2394 continue; 2395 } 2396 case OPC_RecordMemRef: 2397 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2398 continue; 2399 2400 case OPC_CaptureGlueInput: 2401 // If the current node has an input glue, capture it in InputGlue. 2402 if (N->getNumOperands() != 0 && 2403 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2404 InputGlue = N->getOperand(N->getNumOperands()-1); 2405 continue; 2406 2407 case OPC_MoveChild: { 2408 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2409 if (ChildNo >= N.getNumOperands()) 2410 break; // Match fails if out of range child #. 2411 N = N.getOperand(ChildNo); 2412 NodeStack.push_back(N); 2413 continue; 2414 } 2415 2416 case OPC_MoveParent: 2417 // Pop the current node off the NodeStack. 2418 NodeStack.pop_back(); 2419 assert(!NodeStack.empty() && "Node stack imbalance!"); 2420 N = NodeStack.back(); 2421 continue; 2422 2423 case OPC_CheckSame: 2424 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2425 continue; 2426 case OPC_CheckPatternPredicate: 2427 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2428 continue; 2429 case OPC_CheckPredicate: 2430 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2431 N.getNode())) 2432 break; 2433 continue; 2434 case OPC_CheckComplexPat: { 2435 unsigned CPNum = MatcherTable[MatcherIndex++]; 2436 unsigned RecNo = MatcherTable[MatcherIndex++]; 2437 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2438 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2439 RecordedNodes[RecNo].first, CPNum, 2440 RecordedNodes)) 2441 break; 2442 continue; 2443 } 2444 case OPC_CheckOpcode: 2445 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2446 continue; 2447 2448 case OPC_CheckType: 2449 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2450 continue; 2451 2452 case OPC_SwitchOpcode: { 2453 unsigned CurNodeOpcode = N.getOpcode(); 2454 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2455 unsigned CaseSize; 2456 while (1) { 2457 // Get the size of this case. 2458 CaseSize = MatcherTable[MatcherIndex++]; 2459 if (CaseSize & 128) 2460 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2461 if (CaseSize == 0) break; 2462 2463 uint16_t Opc = MatcherTable[MatcherIndex++]; 2464 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2465 2466 // If the opcode matches, then we will execute this case. 2467 if (CurNodeOpcode == Opc) 2468 break; 2469 2470 // Otherwise, skip over this case. 2471 MatcherIndex += CaseSize; 2472 } 2473 2474 // If no cases matched, bail out. 2475 if (CaseSize == 0) break; 2476 2477 // Otherwise, execute the case we found. 2478 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2479 << " to " << MatcherIndex << "\n"); 2480 continue; 2481 } 2482 2483 case OPC_SwitchType: { 2484 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2485 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2486 unsigned CaseSize; 2487 while (1) { 2488 // Get the size of this case. 2489 CaseSize = MatcherTable[MatcherIndex++]; 2490 if (CaseSize & 128) 2491 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2492 if (CaseSize == 0) break; 2493 2494 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2495 if (CaseVT == MVT::iPTR) 2496 CaseVT = TLI.getPointerTy(); 2497 2498 // If the VT matches, then we will execute this case. 2499 if (CurNodeVT == CaseVT) 2500 break; 2501 2502 // Otherwise, skip over this case. 2503 MatcherIndex += CaseSize; 2504 } 2505 2506 // If no cases matched, bail out. 2507 if (CaseSize == 0) break; 2508 2509 // Otherwise, execute the case we found. 2510 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2511 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2512 continue; 2513 } 2514 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2515 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2516 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2517 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2518 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2519 Opcode-OPC_CheckChild0Type)) 2520 break; 2521 continue; 2522 case OPC_CheckCondCode: 2523 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2524 continue; 2525 case OPC_CheckValueType: 2526 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2527 continue; 2528 case OPC_CheckInteger: 2529 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2530 continue; 2531 case OPC_CheckAndImm: 2532 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2533 continue; 2534 case OPC_CheckOrImm: 2535 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2536 continue; 2537 2538 case OPC_CheckFoldableChainNode: { 2539 assert(NodeStack.size() != 1 && "No parent node"); 2540 // Verify that all intermediate nodes between the root and this one have 2541 // a single use. 2542 bool HasMultipleUses = false; 2543 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2544 if (!NodeStack[i].hasOneUse()) { 2545 HasMultipleUses = true; 2546 break; 2547 } 2548 if (HasMultipleUses) break; 2549 2550 // Check to see that the target thinks this is profitable to fold and that 2551 // we can fold it without inducing cycles in the graph. 2552 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2553 NodeToMatch) || 2554 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2555 NodeToMatch, OptLevel, 2556 true/*We validate our own chains*/)) 2557 break; 2558 2559 continue; 2560 } 2561 case OPC_EmitInteger: { 2562 MVT::SimpleValueType VT = 2563 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2564 int64_t Val = MatcherTable[MatcherIndex++]; 2565 if (Val & 128) 2566 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2567 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2568 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2569 continue; 2570 } 2571 case OPC_EmitRegister: { 2572 MVT::SimpleValueType VT = 2573 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2574 unsigned RegNo = MatcherTable[MatcherIndex++]; 2575 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2576 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2577 continue; 2578 } 2579 case OPC_EmitRegister2: { 2580 // For targets w/ more than 256 register names, the register enum 2581 // values are stored in two bytes in the matcher table (just like 2582 // opcodes). 2583 MVT::SimpleValueType VT = 2584 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2585 unsigned RegNo = MatcherTable[MatcherIndex++]; 2586 RegNo |= MatcherTable[MatcherIndex++] << 8; 2587 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2588 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2589 continue; 2590 } 2591 2592 case OPC_EmitConvertToTarget: { 2593 // Convert from IMM/FPIMM to target version. 2594 unsigned RecNo = MatcherTable[MatcherIndex++]; 2595 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2596 SDValue Imm = RecordedNodes[RecNo].first; 2597 2598 if (Imm->getOpcode() == ISD::Constant) { 2599 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2600 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2601 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2602 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2603 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2604 } 2605 2606 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2607 continue; 2608 } 2609 2610 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2611 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2612 // These are space-optimized forms of OPC_EmitMergeInputChains. 2613 assert(InputChain.getNode() == 0 && 2614 "EmitMergeInputChains should be the first chain producing node"); 2615 assert(ChainNodesMatched.empty() && 2616 "Should only have one EmitMergeInputChains per match"); 2617 2618 // Read all of the chained nodes. 2619 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2620 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2621 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2622 2623 // FIXME: What if other value results of the node have uses not matched 2624 // by this pattern? 2625 if (ChainNodesMatched.back() != NodeToMatch && 2626 !RecordedNodes[RecNo].first.hasOneUse()) { 2627 ChainNodesMatched.clear(); 2628 break; 2629 } 2630 2631 // Merge the input chains if they are not intra-pattern references. 2632 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2633 2634 if (InputChain.getNode() == 0) 2635 break; // Failed to merge. 2636 continue; 2637 } 2638 2639 case OPC_EmitMergeInputChains: { 2640 assert(InputChain.getNode() == 0 && 2641 "EmitMergeInputChains should be the first chain producing node"); 2642 // This node gets a list of nodes we matched in the input that have 2643 // chains. We want to token factor all of the input chains to these nodes 2644 // together. However, if any of the input chains is actually one of the 2645 // nodes matched in this pattern, then we have an intra-match reference. 2646 // Ignore these because the newly token factored chain should not refer to 2647 // the old nodes. 2648 unsigned NumChains = MatcherTable[MatcherIndex++]; 2649 assert(NumChains != 0 && "Can't TF zero chains"); 2650 2651 assert(ChainNodesMatched.empty() && 2652 "Should only have one EmitMergeInputChains per match"); 2653 2654 // Read all of the chained nodes. 2655 for (unsigned i = 0; i != NumChains; ++i) { 2656 unsigned RecNo = MatcherTable[MatcherIndex++]; 2657 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2658 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2659 2660 // FIXME: What if other value results of the node have uses not matched 2661 // by this pattern? 2662 if (ChainNodesMatched.back() != NodeToMatch && 2663 !RecordedNodes[RecNo].first.hasOneUse()) { 2664 ChainNodesMatched.clear(); 2665 break; 2666 } 2667 } 2668 2669 // If the inner loop broke out, the match fails. 2670 if (ChainNodesMatched.empty()) 2671 break; 2672 2673 // Merge the input chains if they are not intra-pattern references. 2674 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2675 2676 if (InputChain.getNode() == 0) 2677 break; // Failed to merge. 2678 2679 continue; 2680 } 2681 2682 case OPC_EmitCopyToReg: { 2683 unsigned RecNo = MatcherTable[MatcherIndex++]; 2684 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2685 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2686 2687 if (InputChain.getNode() == 0) 2688 InputChain = CurDAG->getEntryNode(); 2689 2690 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2691 DestPhysReg, RecordedNodes[RecNo].first, 2692 InputGlue); 2693 2694 InputGlue = InputChain.getValue(1); 2695 continue; 2696 } 2697 2698 case OPC_EmitNodeXForm: { 2699 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2700 unsigned RecNo = MatcherTable[MatcherIndex++]; 2701 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2702 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2703 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2704 continue; 2705 } 2706 2707 case OPC_EmitNode: 2708 case OPC_MorphNodeTo: { 2709 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2710 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2711 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2712 // Get the result VT list. 2713 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2714 SmallVector<EVT, 4> VTs; 2715 for (unsigned i = 0; i != NumVTs; ++i) { 2716 MVT::SimpleValueType VT = 2717 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2718 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2719 VTs.push_back(VT); 2720 } 2721 2722 if (EmitNodeInfo & OPFL_Chain) 2723 VTs.push_back(MVT::Other); 2724 if (EmitNodeInfo & OPFL_GlueOutput) 2725 VTs.push_back(MVT::Glue); 2726 2727 // This is hot code, so optimize the two most common cases of 1 and 2 2728 // results. 2729 SDVTList VTList; 2730 if (VTs.size() == 1) 2731 VTList = CurDAG->getVTList(VTs[0]); 2732 else if (VTs.size() == 2) 2733 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2734 else 2735 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2736 2737 // Get the operand list. 2738 unsigned NumOps = MatcherTable[MatcherIndex++]; 2739 SmallVector<SDValue, 8> Ops; 2740 for (unsigned i = 0; i != NumOps; ++i) { 2741 unsigned RecNo = MatcherTable[MatcherIndex++]; 2742 if (RecNo & 128) 2743 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2744 2745 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2746 Ops.push_back(RecordedNodes[RecNo].first); 2747 } 2748 2749 // If there are variadic operands to add, handle them now. 2750 if (EmitNodeInfo & OPFL_VariadicInfo) { 2751 // Determine the start index to copy from. 2752 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2753 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2754 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2755 "Invalid variadic node"); 2756 // Copy all of the variadic operands, not including a potential glue 2757 // input. 2758 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2759 i != e; ++i) { 2760 SDValue V = NodeToMatch->getOperand(i); 2761 if (V.getValueType() == MVT::Glue) break; 2762 Ops.push_back(V); 2763 } 2764 } 2765 2766 // If this has chain/glue inputs, add them. 2767 if (EmitNodeInfo & OPFL_Chain) 2768 Ops.push_back(InputChain); 2769 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2770 Ops.push_back(InputGlue); 2771 2772 // Create the node. 2773 SDNode *Res = 0; 2774 if (Opcode != OPC_MorphNodeTo) { 2775 // If this is a normal EmitNode command, just create the new node and 2776 // add the results to the RecordedNodes list. 2777 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2778 VTList, Ops.data(), Ops.size()); 2779 2780 // Add all the non-glue/non-chain results to the RecordedNodes list. 2781 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2782 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2783 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2784 (SDNode*) 0)); 2785 } 2786 2787 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2788 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2789 EmitNodeInfo); 2790 } else { 2791 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2792 // We will visit the equivalent node later. 2793 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2794 return 0; 2795 } 2796 2797 // If the node had chain/glue results, update our notion of the current 2798 // chain and glue. 2799 if (EmitNodeInfo & OPFL_GlueOutput) { 2800 InputGlue = SDValue(Res, VTs.size()-1); 2801 if (EmitNodeInfo & OPFL_Chain) 2802 InputChain = SDValue(Res, VTs.size()-2); 2803 } else if (EmitNodeInfo & OPFL_Chain) 2804 InputChain = SDValue(Res, VTs.size()-1); 2805 2806 // If the OPFL_MemRefs glue is set on this node, slap all of the 2807 // accumulated memrefs onto it. 2808 // 2809 // FIXME: This is vastly incorrect for patterns with multiple outputs 2810 // instructions that access memory and for ComplexPatterns that match 2811 // loads. 2812 if (EmitNodeInfo & OPFL_MemRefs) { 2813 // Only attach load or store memory operands if the generated 2814 // instruction may load or store. 2815 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2816 bool mayLoad = MCID.mayLoad(); 2817 bool mayStore = MCID.mayStore(); 2818 2819 unsigned NumMemRefs = 0; 2820 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2821 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2822 if ((*I)->isLoad()) { 2823 if (mayLoad) 2824 ++NumMemRefs; 2825 } else if ((*I)->isStore()) { 2826 if (mayStore) 2827 ++NumMemRefs; 2828 } else { 2829 ++NumMemRefs; 2830 } 2831 } 2832 2833 MachineSDNode::mmo_iterator MemRefs = 2834 MF->allocateMemRefsArray(NumMemRefs); 2835 2836 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2837 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2838 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2839 if ((*I)->isLoad()) { 2840 if (mayLoad) 2841 *MemRefsPos++ = *I; 2842 } else if ((*I)->isStore()) { 2843 if (mayStore) 2844 *MemRefsPos++ = *I; 2845 } else { 2846 *MemRefsPos++ = *I; 2847 } 2848 } 2849 2850 cast<MachineSDNode>(Res) 2851 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2852 } 2853 2854 DEBUG(errs() << " " 2855 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2856 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2857 2858 // If this was a MorphNodeTo then we're completely done! 2859 if (Opcode == OPC_MorphNodeTo) { 2860 // Update chain and glue uses. 2861 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2862 InputGlue, GlueResultNodesMatched, true); 2863 return Res; 2864 } 2865 2866 continue; 2867 } 2868 2869 case OPC_MarkGlueResults: { 2870 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2871 2872 // Read and remember all the glue-result nodes. 2873 for (unsigned i = 0; i != NumNodes; ++i) { 2874 unsigned RecNo = MatcherTable[MatcherIndex++]; 2875 if (RecNo & 128) 2876 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2877 2878 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2879 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2880 } 2881 continue; 2882 } 2883 2884 case OPC_CompleteMatch: { 2885 // The match has been completed, and any new nodes (if any) have been 2886 // created. Patch up references to the matched dag to use the newly 2887 // created nodes. 2888 unsigned NumResults = MatcherTable[MatcherIndex++]; 2889 2890 for (unsigned i = 0; i != NumResults; ++i) { 2891 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2892 if (ResSlot & 128) 2893 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2894 2895 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2896 SDValue Res = RecordedNodes[ResSlot].first; 2897 2898 assert(i < NodeToMatch->getNumValues() && 2899 NodeToMatch->getValueType(i) != MVT::Other && 2900 NodeToMatch->getValueType(i) != MVT::Glue && 2901 "Invalid number of results to complete!"); 2902 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2903 NodeToMatch->getValueType(i) == MVT::iPTR || 2904 Res.getValueType() == MVT::iPTR || 2905 NodeToMatch->getValueType(i).getSizeInBits() == 2906 Res.getValueType().getSizeInBits()) && 2907 "invalid replacement"); 2908 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2909 } 2910 2911 // If the root node defines glue, add it to the glue nodes to update list. 2912 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2913 GlueResultNodesMatched.push_back(NodeToMatch); 2914 2915 // Update chain and glue uses. 2916 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2917 InputGlue, GlueResultNodesMatched, false); 2918 2919 assert(NodeToMatch->use_empty() && 2920 "Didn't replace all uses of the node?"); 2921 2922 // FIXME: We just return here, which interacts correctly with SelectRoot 2923 // above. We should fix this to not return an SDNode* anymore. 2924 return 0; 2925 } 2926 } 2927 2928 // If the code reached this point, then the match failed. See if there is 2929 // another child to try in the current 'Scope', otherwise pop it until we 2930 // find a case to check. 2931 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2932 ++NumDAGIselRetries; 2933 while (1) { 2934 if (MatchScopes.empty()) { 2935 CannotYetSelect(NodeToMatch); 2936 return 0; 2937 } 2938 2939 // Restore the interpreter state back to the point where the scope was 2940 // formed. 2941 MatchScope &LastScope = MatchScopes.back(); 2942 RecordedNodes.resize(LastScope.NumRecordedNodes); 2943 NodeStack.clear(); 2944 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2945 N = NodeStack.back(); 2946 2947 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2948 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2949 MatcherIndex = LastScope.FailIndex; 2950 2951 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2952 2953 InputChain = LastScope.InputChain; 2954 InputGlue = LastScope.InputGlue; 2955 if (!LastScope.HasChainNodesMatched) 2956 ChainNodesMatched.clear(); 2957 if (!LastScope.HasGlueResultNodesMatched) 2958 GlueResultNodesMatched.clear(); 2959 2960 // Check to see what the offset is at the new MatcherIndex. If it is zero 2961 // we have reached the end of this scope, otherwise we have another child 2962 // in the current scope to try. 2963 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2964 if (NumToSkip & 128) 2965 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2966 2967 // If we have another child in this scope to match, update FailIndex and 2968 // try it. 2969 if (NumToSkip != 0) { 2970 LastScope.FailIndex = MatcherIndex+NumToSkip; 2971 break; 2972 } 2973 2974 // End of this scope, pop it and try the next child in the containing 2975 // scope. 2976 MatchScopes.pop_back(); 2977 } 2978 } 2979} 2980 2981 2982 2983void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2984 std::string msg; 2985 raw_string_ostream Msg(msg); 2986 Msg << "Cannot select: "; 2987 2988 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2989 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2990 N->getOpcode() != ISD::INTRINSIC_VOID) { 2991 N->printrFull(Msg, CurDAG); 2992 Msg << "\nIn function: " << MF->getName(); 2993 } else { 2994 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2995 unsigned iid = 2996 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2997 if (iid < Intrinsic::num_intrinsics) 2998 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2999 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3000 Msg << "target intrinsic %" << TII->getName(iid); 3001 else 3002 Msg << "unknown intrinsic #" << iid; 3003 } 3004 report_fatal_error(Msg.str()); 3005} 3006 3007char SelectionDAGISel::ID = 0; 3008