SelectionDAGISel.cpp revision 78ae76d54c1a523366be7e1c3cde16287e94de5f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineJumpTableInfo.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleDAG.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetData.h" 42#include "llvm/Target/TargetFrameInfo.h" 43#include "llvm/Target/TargetInstrInfo.h" 44#include "llvm/Target/TargetLowering.h" 45#include "llvm/Target/TargetMachine.h" 46#include "llvm/Target/TargetOptions.h" 47#include "llvm/Support/Compiler.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Support/Timer.h" 51#include <algorithm> 52using namespace llvm; 53 54static cl::opt<bool> 55EnableValueProp("enable-value-prop", cl::Hidden); 56static cl::opt<bool> 57EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the experimental \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65static cl::opt<bool> 66SchedLiveInCopies("schedule-livein-copies", 67 cl::desc("Schedule copies of livein registers"), 68 cl::init(false)); 69 70#ifndef NDEBUG 71static cl::opt<bool> 72ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before the first " 74 "dag combine pass")); 75static cl::opt<bool> 76ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before legalize types")); 78static cl::opt<bool> 79ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before legalize")); 81static cl::opt<bool> 82ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the second " 84 "dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewISelDAGs = false, ViewSchedDAGs = false, 99 ViewSUnitDAGs = false; 100#endif 101 102//===---------------------------------------------------------------------===// 103/// 104/// RegisterScheduler class - Track the registration of instruction schedulers. 105/// 106//===---------------------------------------------------------------------===// 107MachinePassRegistry RegisterScheduler::Registry; 108 109//===---------------------------------------------------------------------===// 110/// 111/// ISHeuristic command line option for instruction schedulers. 112/// 113//===---------------------------------------------------------------------===// 114static cl::opt<RegisterScheduler::FunctionPassCtor, false, 115 RegisterPassParser<RegisterScheduler> > 116ISHeuristic("pre-RA-sched", 117 cl::init(&createDefaultScheduler), 118 cl::desc("Instruction schedulers available (before register" 119 " allocation):")); 120 121static RegisterScheduler 122defaultListDAGScheduler("default", " Best scheduler for the target", 123 createDefaultScheduler); 124 125namespace llvm { 126 //===--------------------------------------------------------------------===// 127 /// createDefaultScheduler - This creates an instruction scheduler appropriate 128 /// for the target. 129 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 130 SelectionDAG *DAG, 131 MachineBasicBlock *BB, 132 bool Fast) { 133 TargetLowering &TLI = IS->getTargetLowering(); 134 135 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 136 return createTDListDAGScheduler(IS, DAG, BB, Fast); 137 } else { 138 assert(TLI.getSchedulingPreference() == 139 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 140 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 141 } 142 } 143} 144 145// EmitInstrWithCustomInserter - This method should be implemented by targets 146// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 147// instructions are special in various ways, which require special support to 148// insert. The specified MachineInstr is created but not inserted into any 149// basic blocks, and the scheduler passes ownership of it to this method. 150MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 151 MachineBasicBlock *MBB) { 152 cerr << "If a target marks an instruction with " 153 << "'usesCustomDAGSchedInserter', it must implement " 154 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 155 abort(); 156 return 0; 157} 158 159/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 160/// physical register has only a single copy use, then coalesced the copy 161/// if possible. 162static void EmitLiveInCopy(MachineBasicBlock *MBB, 163 MachineBasicBlock::iterator &InsertPos, 164 unsigned VirtReg, unsigned PhysReg, 165 const TargetRegisterClass *RC, 166 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 167 const MachineRegisterInfo &MRI, 168 const TargetRegisterInfo &TRI, 169 const TargetInstrInfo &TII) { 170 unsigned NumUses = 0; 171 MachineInstr *UseMI = NULL; 172 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 173 UE = MRI.use_end(); UI != UE; ++UI) { 174 UseMI = &*UI; 175 if (++NumUses > 1) 176 break; 177 } 178 179 // If the number of uses is not one, or the use is not a move instruction, 180 // don't coalesce. Also, only coalesce away a virtual register to virtual 181 // register copy. 182 bool Coalesced = false; 183 unsigned SrcReg, DstReg; 184 if (NumUses == 1 && 185 TII.isMoveInstr(*UseMI, SrcReg, DstReg) && 186 TargetRegisterInfo::isVirtualRegister(DstReg)) { 187 VirtReg = DstReg; 188 Coalesced = true; 189 } 190 191 // Now find an ideal location to insert the copy. 192 MachineBasicBlock::iterator Pos = InsertPos; 193 while (Pos != MBB->begin()) { 194 MachineInstr *PrevMI = prior(Pos); 195 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 196 // copyRegToReg might emit multiple instructions to do a copy. 197 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 198 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 199 // This is what the BB looks like right now: 200 // r1024 = mov r0 201 // ... 202 // r1 = mov r1024 203 // 204 // We want to insert "r1025 = mov r1". Inserting this copy below the 205 // move to r1024 makes it impossible for that move to be coalesced. 206 // 207 // r1025 = mov r1 208 // r1024 = mov r0 209 // ... 210 // r1 = mov 1024 211 // r2 = mov 1025 212 break; // Woot! Found a good location. 213 --Pos; 214 } 215 216 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 217 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 218 if (Coalesced) { 219 if (&*InsertPos == UseMI) ++InsertPos; 220 MBB->erase(UseMI); 221 } 222} 223 224/// EmitLiveInCopies - If this is the first basic block in the function, 225/// and if it has live ins that need to be copied into vregs, emit the 226/// copies into the block. 227static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 228 const MachineRegisterInfo &MRI, 229 const TargetRegisterInfo &TRI, 230 const TargetInstrInfo &TII) { 231 if (SchedLiveInCopies) { 232 // Emit the copies at a heuristically-determined location in the block. 233 DenseMap<MachineInstr*, unsigned> CopyRegMap; 234 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 235 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 236 E = MRI.livein_end(); LI != E; ++LI) 237 if (LI->second) { 238 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 239 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 240 RC, CopyRegMap, MRI, TRI, TII); 241 } 242 } else { 243 // Emit the copies into the top of the block. 244 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 245 E = MRI.livein_end(); LI != E; ++LI) 246 if (LI->second) { 247 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 248 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 249 LI->second, LI->first, RC, RC); 250 } 251 } 252} 253 254//===----------------------------------------------------------------------===// 255// SelectionDAGISel code 256//===----------------------------------------------------------------------===// 257 258SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) : 259 FunctionPass(&ID), TLI(tli), 260 FuncInfo(new FunctionLoweringInfo(TLI)), 261 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 262 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)), 263 GFI(), 264 Fast(fast), 265 DAGSize(0) 266{} 267 268SelectionDAGISel::~SelectionDAGISel() { 269 delete SDL; 270 delete CurDAG; 271 delete FuncInfo; 272} 273 274unsigned SelectionDAGISel::MakeReg(MVT VT) { 275 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 276} 277 278void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 279 AU.addRequired<AliasAnalysis>(); 280 AU.addRequired<GCModuleInfo>(); 281 AU.setPreservesAll(); 282} 283 284bool SelectionDAGISel::runOnFunction(Function &Fn) { 285 // Do some sanity-checking on the command-line options. 286 assert((!EnableFastISelVerbose || EnableFastISel) && 287 "-fast-isel-verbose requires -fast-isel"); 288 assert((!EnableFastISelAbort || EnableFastISel) && 289 "-fast-isel-abort requires -fast-isel"); 290 291 // Get alias analysis for load/store combining. 292 AA = &getAnalysis<AliasAnalysis>(); 293 294 TargetMachine &TM = TLI.getTargetMachine(); 295 MachineFunction &MF = MachineFunction::construct(&Fn, TM); 296 const MachineRegisterInfo &MRI = MF.getRegInfo(); 297 const TargetInstrInfo &TII = *TM.getInstrInfo(); 298 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 299 300 if (MF.getFunction()->hasGC()) 301 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction()); 302 else 303 GFI = 0; 304 RegInfo = &MF.getRegInfo(); 305 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 306 307 FuncInfo->set(Fn, MF, EnableFastISel); 308 MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>(); 309 CurDAG->init(MF, MMI); 310 SDL->init(GFI, *AA); 311 312 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 313 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 314 // Mark landing pad. 315 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 316 317 SelectAllBasicBlocks(Fn, MF, MMI); 318 319 // If the first basic block in the function has live ins that need to be 320 // copied into vregs, emit the copies into the top of the block before 321 // emitting the code for the block. 322 EmitLiveInCopies(MF.begin(), MRI, TRI, TII); 323 324 // Add function live-ins to entry block live-in set. 325 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 326 E = RegInfo->livein_end(); I != E; ++I) 327 MF.begin()->addLiveIn(I->first); 328 329#ifndef NDEBUG 330 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 331 "Not all catch info was assigned to a landing pad!"); 332#endif 333 334 FuncInfo->clear(); 335 336 return true; 337} 338 339static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 340 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 341 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 342 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 343 // Apply the catch info to DestBB. 344 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 345#ifndef NDEBUG 346 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 347 FLI.CatchInfoFound.insert(EHSel); 348#endif 349 } 350} 351 352/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 353/// whether object offset >= 0. 354static bool 355IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 356 if (!isa<FrameIndexSDNode>(Op)) return false; 357 358 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 359 int FrameIdx = FrameIdxNode->getIndex(); 360 return MFI->isFixedObjectIndex(FrameIdx) && 361 MFI->getObjectOffset(FrameIdx) >= 0; 362} 363 364/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 365/// possibly be overwritten when lowering the outgoing arguments in a tail 366/// call. Currently the implementation of this call is very conservative and 367/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 368/// virtual registers would be overwritten by direct lowering. 369static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 370 MachineFrameInfo * MFI) { 371 RegisterSDNode * OpReg = NULL; 372 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 373 (Op.getOpcode()== ISD::CopyFromReg && 374 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 375 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 376 (Op.getOpcode() == ISD::LOAD && 377 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 378 (Op.getOpcode() == ISD::MERGE_VALUES && 379 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD && 380 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()). 381 getOperand(1)))) 382 return true; 383 return false; 384} 385 386/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 387/// DAG and fixes their tailcall attribute operand. 388static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 389 TargetLowering& TLI) { 390 SDNode * Ret = NULL; 391 SDValue Terminator = DAG.getRoot(); 392 393 // Find RET node. 394 if (Terminator.getOpcode() == ISD::RET) { 395 Ret = Terminator.getNode(); 396 } 397 398 // Fix tail call attribute of CALL nodes. 399 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 400 BI = DAG.allnodes_end(); BI != BE; ) { 401 --BI; 402 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) { 403 SDValue OpRet(Ret, 0); 404 SDValue OpCall(BI, 0); 405 bool isMarkedTailCall = TheCall->isTailCall(); 406 // If CALL node has tail call attribute set to true and the call is not 407 // eligible (no RET or the target rejects) the attribute is fixed to 408 // false. The TargetLowering::IsEligibleForTailCallOptimization function 409 // must correctly identify tail call optimizable calls. 410 if (!isMarkedTailCall) continue; 411 if (Ret==NULL || 412 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) { 413 // Not eligible. Mark CALL node as non tail call. Note that we 414 // can modify the call node in place since calls are not CSE'd. 415 TheCall->setNotTailCall(); 416 } else { 417 // Look for tail call clobbered arguments. Emit a series of 418 // copyto/copyfrom virtual register nodes to protect them. 419 SmallVector<SDValue, 32> Ops; 420 SDValue Chain = TheCall->getChain(), InFlag; 421 Ops.push_back(Chain); 422 Ops.push_back(TheCall->getCallee()); 423 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 424 SDValue Arg = TheCall->getArg(i); 425 bool isByVal = TheCall->getArgFlags(i).isByVal(); 426 MachineFunction &MF = DAG.getMachineFunction(); 427 MachineFrameInfo *MFI = MF.getFrameInfo(); 428 if (!isByVal && 429 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 430 MVT VT = Arg.getValueType(); 431 unsigned VReg = MF.getRegInfo(). 432 createVirtualRegister(TLI.getRegClassFor(VT)); 433 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 434 InFlag = Chain.getValue(1); 435 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 436 Chain = Arg.getValue(1); 437 InFlag = Arg.getValue(2); 438 } 439 Ops.push_back(Arg); 440 Ops.push_back(TheCall->getArgFlagsVal(i)); 441 } 442 // Link in chain of CopyTo/CopyFromReg. 443 Ops[0] = Chain; 444 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 445 } 446 } 447 } 448} 449 450void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 451 BasicBlock::iterator Begin, 452 BasicBlock::iterator End) { 453 SDL->setCurrentBasicBlock(BB); 454 455 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo(); 456 457 if (MMI && BB->isLandingPad()) { 458 // Add a label to mark the beginning of the landing pad. Deletion of the 459 // landing pad can thus be detected via the MachineModuleInfo. 460 unsigned LabelID = MMI->addLandingPad(BB); 461 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL, 462 CurDAG->getEntryNode(), LabelID)); 463 464 // Mark exception register as live in. 465 unsigned Reg = TLI.getExceptionAddressRegister(); 466 if (Reg) BB->addLiveIn(Reg); 467 468 // Mark exception selector register as live in. 469 Reg = TLI.getExceptionSelectorRegister(); 470 if (Reg) BB->addLiveIn(Reg); 471 472 // FIXME: Hack around an exception handling flaw (PR1508): the personality 473 // function and list of typeids logically belong to the invoke (or, if you 474 // like, the basic block containing the invoke), and need to be associated 475 // with it in the dwarf exception handling tables. Currently however the 476 // information is provided by an intrinsic (eh.selector) that can be moved 477 // to unexpected places by the optimizers: if the unwind edge is critical, 478 // then breaking it can result in the intrinsics being in the successor of 479 // the landing pad, not the landing pad itself. This results in exceptions 480 // not being caught because no typeids are associated with the invoke. 481 // This may not be the only way things can go wrong, but it is the only way 482 // we try to work around for the moment. 483 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 484 485 if (Br && Br->isUnconditional()) { // Critical edge? 486 BasicBlock::iterator I, E; 487 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 488 if (isa<EHSelectorInst>(I)) 489 break; 490 491 if (I == E) 492 // No catch info found - try to extract some from the successor. 493 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 494 } 495 } 496 497 // Lower all of the non-terminator instructions. 498 for (BasicBlock::iterator I = Begin; I != End; ++I) 499 if (!isa<TerminatorInst>(I)) 500 SDL->visit(*I); 501 502 // Ensure that all instructions which are used outside of their defining 503 // blocks are available as virtual registers. Invoke is handled elsewhere. 504 for (BasicBlock::iterator I = Begin; I != End; ++I) 505 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 506 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I); 507 if (VMI != FuncInfo->ValueMap.end()) 508 SDL->CopyValueToVirtualRegister(I, VMI->second); 509 } 510 511 // Handle PHI nodes in successor blocks. 512 if (End == LLVMBB->end()) { 513 HandlePHINodesInSuccessorBlocks(LLVMBB); 514 515 // Lower the terminator after the copies are emitted. 516 SDL->visit(*LLVMBB->getTerminator()); 517 } 518 519 // Make sure the root of the DAG is up-to-date. 520 CurDAG->setRoot(SDL->getControlRoot()); 521 522 // Check whether calls in this block are real tail calls. Fix up CALL nodes 523 // with correct tailcall attribute so that the target can rely on the tailcall 524 // attribute indicating whether the call is really eligible for tail call 525 // optimization. 526 if (PerformTailCallOpt) 527 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI); 528 529 // Final step, emit the lowered DAG as machine code. 530 CodeGenAndEmitDAG(); 531 SDL->clear(); 532} 533 534void SelectionDAGISel::ComputeLiveOutVRegInfo() { 535 SmallPtrSet<SDNode*, 128> VisitedNodes; 536 SmallVector<SDNode*, 128> Worklist; 537 538 Worklist.push_back(CurDAG->getRoot().getNode()); 539 540 APInt Mask; 541 APInt KnownZero; 542 APInt KnownOne; 543 544 while (!Worklist.empty()) { 545 SDNode *N = Worklist.back(); 546 Worklist.pop_back(); 547 548 // If we've already seen this node, ignore it. 549 if (!VisitedNodes.insert(N)) 550 continue; 551 552 // Otherwise, add all chain operands to the worklist. 553 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 554 if (N->getOperand(i).getValueType() == MVT::Other) 555 Worklist.push_back(N->getOperand(i).getNode()); 556 557 // If this is a CopyToReg with a vreg dest, process it. 558 if (N->getOpcode() != ISD::CopyToReg) 559 continue; 560 561 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 562 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 563 continue; 564 565 // Ignore non-scalar or non-integer values. 566 SDValue Src = N->getOperand(2); 567 MVT SrcVT = Src.getValueType(); 568 if (!SrcVT.isInteger() || SrcVT.isVector()) 569 continue; 570 571 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 572 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 573 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 574 575 // Only install this information if it tells us something. 576 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 577 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 578 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo(); 579 if (DestReg >= FLI.LiveOutRegInfo.size()) 580 FLI.LiveOutRegInfo.resize(DestReg+1); 581 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 582 LOI.NumSignBits = NumSignBits; 583 LOI.KnownOne = NumSignBits; 584 LOI.KnownZero = NumSignBits; 585 } 586 } 587} 588 589void SelectionDAGISel::CodeGenAndEmitDAG() { 590 std::string GroupName; 591 if (TimePassesIsEnabled) 592 GroupName = "Instruction Selection and Scheduling"; 593 std::string BlockName; 594 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 595 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 596 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' + 597 BB->getBasicBlock()->getName(); 598 599 DOUT << "Initial selection DAG:\n"; 600 DEBUG(CurDAG->dump()); 601 602 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 603 604 // Run the DAG combiner in pre-legalize mode. 605 if (TimePassesIsEnabled) { 606 NamedRegionTimer T("DAG Combining 1", GroupName); 607 CurDAG->Combine(false, *AA, Fast); 608 } else { 609 CurDAG->Combine(false, *AA, Fast); 610 } 611 612 DOUT << "Optimized lowered selection DAG:\n"; 613 DEBUG(CurDAG->dump()); 614 615 // Second step, hack on the DAG until it only uses operations and types that 616 // the target supports. 617 if (EnableLegalizeTypes) {// Enable this some day. 618 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 619 BlockName); 620 621 if (TimePassesIsEnabled) { 622 NamedRegionTimer T("Type Legalization", GroupName); 623 CurDAG->LegalizeTypes(); 624 } else { 625 CurDAG->LegalizeTypes(); 626 } 627 628 DOUT << "Type-legalized selection DAG:\n"; 629 DEBUG(CurDAG->dump()); 630 631 // TODO: enable a dag combine pass here. 632 } 633 634 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 635 636 if (TimePassesIsEnabled) { 637 NamedRegionTimer T("DAG Legalization", GroupName); 638 CurDAG->Legalize(); 639 } else { 640 CurDAG->Legalize(); 641 } 642 643 DOUT << "Legalized selection DAG:\n"; 644 DEBUG(CurDAG->dump()); 645 646 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 647 648 // Run the DAG combiner in post-legalize mode. 649 if (TimePassesIsEnabled) { 650 NamedRegionTimer T("DAG Combining 2", GroupName); 651 CurDAG->Combine(true, *AA, Fast); 652 } else { 653 CurDAG->Combine(true, *AA, Fast); 654 } 655 656 DOUT << "Optimized legalized selection DAG:\n"; 657 DEBUG(CurDAG->dump()); 658 659 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 660 661 if (!Fast && EnableValueProp) 662 ComputeLiveOutVRegInfo(); 663 664 // Third, instruction select all of the operations to machine code, adding the 665 // code to the MachineBasicBlock. 666 if (TimePassesIsEnabled) { 667 NamedRegionTimer T("Instruction Selection", GroupName); 668 InstructionSelect(); 669 } else { 670 InstructionSelect(); 671 } 672 673 DOUT << "Selected selection DAG:\n"; 674 DEBUG(CurDAG->dump()); 675 676 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 677 678 // Schedule machine code. 679 ScheduleDAG *Scheduler; 680 if (TimePassesIsEnabled) { 681 NamedRegionTimer T("Instruction Scheduling", GroupName); 682 Scheduler = Schedule(); 683 } else { 684 Scheduler = Schedule(); 685 } 686 687 if (ViewSUnitDAGs) Scheduler->viewGraph(); 688 689 // Emit machine code to BB. This can change 'BB' to the last block being 690 // inserted into. 691 if (TimePassesIsEnabled) { 692 NamedRegionTimer T("Instruction Creation", GroupName); 693 BB = Scheduler->EmitSchedule(); 694 } else { 695 BB = Scheduler->EmitSchedule(); 696 } 697 698 // Free the scheduler state. 699 if (TimePassesIsEnabled) { 700 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 701 delete Scheduler; 702 } else { 703 delete Scheduler; 704 } 705 706 DOUT << "Selected machine code:\n"; 707 DEBUG(BB->dump()); 708} 709 710void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 711 MachineModuleInfo *MMI) { 712 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 713 BasicBlock *LLVMBB = &*I; 714 BB = FuncInfo->MBBMap[LLVMBB]; 715 716 BasicBlock::iterator const Begin = LLVMBB->begin(); 717 BasicBlock::iterator const End = LLVMBB->end(); 718 BasicBlock::iterator BI = Begin; 719 720 // Lower any arguments needed in this block if this is the entry block. 721 bool SuppressFastISel = false; 722 if (LLVMBB == &Fn.getEntryBlock()) { 723 LowerArguments(LLVMBB); 724 725 // If any of the arguments has the byval attribute, forgo 726 // fast-isel in the entry block. 727 if (EnableFastISel) { 728 unsigned j = 1; 729 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 730 I != E; ++I, ++j) 731 if (Fn.paramHasAttr(j, ParamAttr::ByVal)) { 732 cerr << "FastISel skips entry block due to byval argument"; 733 SuppressFastISel = true; 734 break; 735 } 736 } 737 } 738 739 // Before doing SelectionDAG ISel, see if FastISel has been requested. 740 // FastISel doesn't support EH landing pads, which require special handling. 741 if (EnableFastISel && !SuppressFastISel && !BB->isLandingPad()) { 742 if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, MMI, 743 FuncInfo->ValueMap, 744 FuncInfo->MBBMap, 745 FuncInfo->StaticAllocaMap)) { 746 // Emit code for any incoming arguments. This must happen before 747 // beginning FastISel on the entry block. 748 if (LLVMBB == &Fn.getEntryBlock()) { 749 CurDAG->setRoot(SDL->getControlRoot()); 750 CodeGenAndEmitDAG(); 751 SDL->clear(); 752 } 753 F->setCurrentBlock(BB); 754 // Do FastISel on as many instructions as possible. 755 for (; BI != End; ++BI) { 756 // Just before the terminator instruction, insert instructions to 757 // feed PHI nodes in successor blocks. 758 if (isa<TerminatorInst>(BI)) 759 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, F)) { 760 if (EnableFastISelVerbose || EnableFastISelAbort) { 761 cerr << "FastISel miss: "; 762 BI->dump(); 763 } 764 if (EnableFastISelAbort) 765 assert(0 && "FastISel didn't handle a PHI in a successor"); 766 break; 767 } 768 769 // First try normal tablegen-generated "fast" selection. 770 if (F->SelectInstruction(BI)) 771 continue; 772 773 // Next, try calling the target to attempt to handle the instruction. 774 if (F->TargetSelectInstruction(BI)) 775 continue; 776 777 // Then handle certain instructions as single-LLVM-Instruction blocks. 778 if (isa<CallInst>(BI)) { 779 cerr << "FastISel missed call: "; 780 BI->dump(); 781 782 if (BI->getType() != Type::VoidTy) { 783 unsigned &R = FuncInfo->ValueMap[BI]; 784 if (!R) 785 R = FuncInfo->CreateRegForValue(BI); 786 } 787 788 SelectBasicBlock(LLVMBB, BI, next(BI)); 789 continue; 790 } 791 792 // Otherwise, give up on FastISel for the rest of the block. 793 // For now, be a little lenient about non-branch terminators. 794 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 795 if (EnableFastISelVerbose || EnableFastISelAbort) { 796 cerr << "FastISel miss: "; 797 BI->dump(); 798 } 799 if (EnableFastISelAbort) 800 // The "fast" selector couldn't handle something and bailed. 801 // For the purpose of debugging, just abort. 802 assert(0 && "FastISel didn't select the entire block"); 803 } 804 break; 805 } 806 delete F; 807 } 808 } 809 810 // Run SelectionDAG instruction selection on the remainder of the block 811 // not handled by FastISel. If FastISel is not run, this is the entire 812 // block. 813 if (BI != End) 814 SelectBasicBlock(LLVMBB, BI, End); 815 816 FinishBasicBlock(); 817 } 818} 819 820void 821SelectionDAGISel::FinishBasicBlock() { 822 823 // Perform target specific isel post processing. 824 InstructionSelectPostProcessing(); 825 826 DOUT << "Target-post-processed machine code:\n"; 827 DEBUG(BB->dump()); 828 829 DOUT << "Total amount of phi nodes to update: " 830 << SDL->PHINodesToUpdate.size() << "\n"; 831 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 832 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 833 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 834 835 // Next, now that we know what the last MBB the LLVM BB expanded is, update 836 // PHI nodes in successors. 837 if (SDL->SwitchCases.empty() && 838 SDL->JTCases.empty() && 839 SDL->BitTestCases.empty()) { 840 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 841 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 842 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 843 "This is not a machine PHI node that we are updating!"); 844 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 845 false)); 846 PHI->addOperand(MachineOperand::CreateMBB(BB)); 847 } 848 SDL->PHINodesToUpdate.clear(); 849 return; 850 } 851 852 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 853 // Lower header first, if it wasn't already lowered 854 if (!SDL->BitTestCases[i].Emitted) { 855 // Set the current basic block to the mbb we wish to insert the code into 856 BB = SDL->BitTestCases[i].Parent; 857 SDL->setCurrentBasicBlock(BB); 858 // Emit the code 859 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 860 CurDAG->setRoot(SDL->getRoot()); 861 CodeGenAndEmitDAG(); 862 SDL->clear(); 863 } 864 865 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 866 // Set the current basic block to the mbb we wish to insert the code into 867 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 868 SDL->setCurrentBasicBlock(BB); 869 // Emit the code 870 if (j+1 != ej) 871 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 872 SDL->BitTestCases[i].Reg, 873 SDL->BitTestCases[i].Cases[j]); 874 else 875 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 876 SDL->BitTestCases[i].Reg, 877 SDL->BitTestCases[i].Cases[j]); 878 879 880 CurDAG->setRoot(SDL->getRoot()); 881 CodeGenAndEmitDAG(); 882 SDL->clear(); 883 } 884 885 // Update PHI Nodes 886 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 887 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 888 MachineBasicBlock *PHIBB = PHI->getParent(); 889 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 890 "This is not a machine PHI node that we are updating!"); 891 // This is "default" BB. We have two jumps to it. From "header" BB and 892 // from last "case" BB. 893 if (PHIBB == SDL->BitTestCases[i].Default) { 894 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 895 false)); 896 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 897 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 898 false)); 899 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 900 back().ThisBB)); 901 } 902 // One of "cases" BB. 903 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 904 j != ej; ++j) { 905 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 906 if (cBB->succ_end() != 907 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 908 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 909 false)); 910 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 911 } 912 } 913 } 914 } 915 SDL->BitTestCases.clear(); 916 917 // If the JumpTable record is filled in, then we need to emit a jump table. 918 // Updating the PHI nodes is tricky in this case, since we need to determine 919 // whether the PHI is a successor of the range check MBB or the jump table MBB 920 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 921 // Lower header first, if it wasn't already lowered 922 if (!SDL->JTCases[i].first.Emitted) { 923 // Set the current basic block to the mbb we wish to insert the code into 924 BB = SDL->JTCases[i].first.HeaderBB; 925 SDL->setCurrentBasicBlock(BB); 926 // Emit the code 927 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 928 CurDAG->setRoot(SDL->getRoot()); 929 CodeGenAndEmitDAG(); 930 SDL->clear(); 931 } 932 933 // Set the current basic block to the mbb we wish to insert the code into 934 BB = SDL->JTCases[i].second.MBB; 935 SDL->setCurrentBasicBlock(BB); 936 // Emit the code 937 SDL->visitJumpTable(SDL->JTCases[i].second); 938 CurDAG->setRoot(SDL->getRoot()); 939 CodeGenAndEmitDAG(); 940 SDL->clear(); 941 942 // Update PHI Nodes 943 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 944 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 945 MachineBasicBlock *PHIBB = PHI->getParent(); 946 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 947 "This is not a machine PHI node that we are updating!"); 948 // "default" BB. We can go there only from header BB. 949 if (PHIBB == SDL->JTCases[i].second.Default) { 950 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 951 false)); 952 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 953 } 954 // JT BB. Just iterate over successors here 955 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 956 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 957 false)); 958 PHI->addOperand(MachineOperand::CreateMBB(BB)); 959 } 960 } 961 } 962 SDL->JTCases.clear(); 963 964 // If the switch block involved a branch to one of the actual successors, we 965 // need to update PHI nodes in that block. 966 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 967 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 968 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 969 "This is not a machine PHI node that we are updating!"); 970 if (BB->isSuccessor(PHI->getParent())) { 971 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 972 false)); 973 PHI->addOperand(MachineOperand::CreateMBB(BB)); 974 } 975 } 976 977 // If we generated any switch lowering information, build and codegen any 978 // additional DAGs necessary. 979 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 980 // Set the current basic block to the mbb we wish to insert the code into 981 BB = SDL->SwitchCases[i].ThisBB; 982 SDL->setCurrentBasicBlock(BB); 983 984 // Emit the code 985 SDL->visitSwitchCase(SDL->SwitchCases[i]); 986 CurDAG->setRoot(SDL->getRoot()); 987 CodeGenAndEmitDAG(); 988 SDL->clear(); 989 990 // Handle any PHI nodes in successors of this chunk, as if we were coming 991 // from the original BB before switch expansion. Note that PHI nodes can 992 // occur multiple times in PHINodesToUpdate. We have to be very careful to 993 // handle them the right number of times. 994 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 995 for (MachineBasicBlock::iterator Phi = BB->begin(); 996 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 997 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 998 for (unsigned pn = 0; ; ++pn) { 999 assert(pn != SDL->PHINodesToUpdate.size() && 1000 "Didn't find PHI entry!"); 1001 if (SDL->PHINodesToUpdate[pn].first == Phi) { 1002 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 1003 second, false)); 1004 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 1005 break; 1006 } 1007 } 1008 } 1009 1010 // Don't process RHS if same block as LHS. 1011 if (BB == SDL->SwitchCases[i].FalseBB) 1012 SDL->SwitchCases[i].FalseBB = 0; 1013 1014 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1015 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 1016 SDL->SwitchCases[i].FalseBB = 0; 1017 } 1018 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 1019 } 1020 SDL->SwitchCases.clear(); 1021 1022 SDL->PHINodesToUpdate.clear(); 1023} 1024 1025 1026/// Schedule - Pick a safe ordering for instructions for each 1027/// target node in the graph. 1028/// 1029ScheduleDAG *SelectionDAGISel::Schedule() { 1030 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1031 1032 if (!Ctor) { 1033 Ctor = ISHeuristic; 1034 RegisterScheduler::setDefault(Ctor); 1035 } 1036 1037 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast); 1038 Scheduler->Run(); 1039 1040 return Scheduler; 1041} 1042 1043 1044HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1045 return new HazardRecognizer(); 1046} 1047 1048//===----------------------------------------------------------------------===// 1049// Helper functions used by the generated instruction selector. 1050//===----------------------------------------------------------------------===// 1051// Calls to these methods are generated by tblgen. 1052 1053/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1054/// the dag combiner simplified the 255, we still want to match. RHS is the 1055/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1056/// specified in the .td file (e.g. 255). 1057bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1058 int64_t DesiredMaskS) const { 1059 const APInt &ActualMask = RHS->getAPIntValue(); 1060 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1061 1062 // If the actual mask exactly matches, success! 1063 if (ActualMask == DesiredMask) 1064 return true; 1065 1066 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1067 if (ActualMask.intersects(~DesiredMask)) 1068 return false; 1069 1070 // Otherwise, the DAG Combiner may have proven that the value coming in is 1071 // either already zero or is not demanded. Check for known zero input bits. 1072 APInt NeededMask = DesiredMask & ~ActualMask; 1073 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1074 return true; 1075 1076 // TODO: check to see if missing bits are just not demanded. 1077 1078 // Otherwise, this pattern doesn't match. 1079 return false; 1080} 1081 1082/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1083/// the dag combiner simplified the 255, we still want to match. RHS is the 1084/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1085/// specified in the .td file (e.g. 255). 1086bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1087 int64_t DesiredMaskS) const { 1088 const APInt &ActualMask = RHS->getAPIntValue(); 1089 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1090 1091 // If the actual mask exactly matches, success! 1092 if (ActualMask == DesiredMask) 1093 return true; 1094 1095 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1096 if (ActualMask.intersects(~DesiredMask)) 1097 return false; 1098 1099 // Otherwise, the DAG Combiner may have proven that the value coming in is 1100 // either already zero or is not demanded. Check for known zero input bits. 1101 APInt NeededMask = DesiredMask & ~ActualMask; 1102 1103 APInt KnownZero, KnownOne; 1104 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1105 1106 // If all the missing bits in the or are already known to be set, match! 1107 if ((NeededMask & KnownOne) == NeededMask) 1108 return true; 1109 1110 // TODO: check to see if missing bits are just not demanded. 1111 1112 // Otherwise, this pattern doesn't match. 1113 return false; 1114} 1115 1116 1117/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1118/// by tblgen. Others should not call it. 1119void SelectionDAGISel:: 1120SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1121 std::vector<SDValue> InOps; 1122 std::swap(InOps, Ops); 1123 1124 Ops.push_back(InOps[0]); // input chain. 1125 Ops.push_back(InOps[1]); // input asm string. 1126 1127 unsigned i = 2, e = InOps.size(); 1128 if (InOps[e-1].getValueType() == MVT::Flag) 1129 --e; // Don't process a flag operand if it is here. 1130 1131 while (i != e) { 1132 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1133 if ((Flags & 7) != 4 /*MEM*/) { 1134 // Just skip over this operand, copying the operands verbatim. 1135 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 1136 i += (Flags >> 3) + 1; 1137 } else { 1138 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 1139 // Otherwise, this is a memory operand. Ask the target to select it. 1140 std::vector<SDValue> SelOps; 1141 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1142 cerr << "Could not match memory address. Inline asm failure!\n"; 1143 exit(1); 1144 } 1145 1146 // Add this to the output node. 1147 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy(); 1148 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1149 IntPtrTy)); 1150 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1151 i += 2; 1152 } 1153 } 1154 1155 // Add the flag input back if present. 1156 if (e != InOps.size()) 1157 Ops.push_back(InOps.back()); 1158} 1159 1160char SelectionDAGISel::ID = 0; 1161