SelectionDAGISel.cpp revision 7d3b3e40e16069bbc07c2acb20594cfffe406572
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63DisableLegalizeTypes("disable-legalize-types", cl::Hidden); 64static cl::opt<bool> 65EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 66 cl::desc("Enable verbose messages in the \"fast\" " 67 "instruction selector")); 68static cl::opt<bool> 69EnableFastISelAbort("fast-isel-abort", cl::Hidden, 70 cl::desc("Enable abort calls when \"fast\" instruction fails")); 71static cl::opt<bool> 72SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 73 cl::desc("Schedule copies of livein registers"), 74 cl::init(false)); 75 76#ifndef NDEBUG 77static cl::opt<bool> 78ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the first " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before legalize types")); 84static cl::opt<bool> 85ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 86 cl::desc("Pop up a window to show dags before legalize")); 87static cl::opt<bool> 88ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 89 cl::desc("Pop up a window to show dags before the second " 90 "dag combine pass")); 91static cl::opt<bool> 92ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 93 cl::desc("Pop up a window to show dags before the post legalize types" 94 " dag combine pass")); 95static cl::opt<bool> 96ViewISelDAGs("view-isel-dags", cl::Hidden, 97 cl::desc("Pop up a window to show isel dags as they are selected")); 98static cl::opt<bool> 99ViewSchedDAGs("view-sched-dags", cl::Hidden, 100 cl::desc("Pop up a window to show sched dags as they are processed")); 101static cl::opt<bool> 102ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 103 cl::desc("Pop up a window to show SUnit dags after they are processed")); 104#else 105static const bool ViewDAGCombine1 = false, 106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 107 ViewDAGCombine2 = false, 108 ViewDAGCombineLT = false, 109 ViewISelDAGs = false, ViewSchedDAGs = false, 110 ViewSUnitDAGs = false; 111#endif 112 113//===---------------------------------------------------------------------===// 114/// 115/// RegisterScheduler class - Track the registration of instruction schedulers. 116/// 117//===---------------------------------------------------------------------===// 118MachinePassRegistry RegisterScheduler::Registry; 119 120//===---------------------------------------------------------------------===// 121/// 122/// ISHeuristic command line option for instruction schedulers. 123/// 124//===---------------------------------------------------------------------===// 125static cl::opt<RegisterScheduler::FunctionPassCtor, false, 126 RegisterPassParser<RegisterScheduler> > 127ISHeuristic("pre-RA-sched", 128 cl::init(&createDefaultScheduler), 129 cl::desc("Instruction schedulers available (before register" 130 " allocation):")); 131 132static RegisterScheduler 133defaultListDAGScheduler("default", "Best scheduler for the target", 134 createDefaultScheduler); 135 136namespace llvm { 137 //===--------------------------------------------------------------------===// 138 /// createDefaultScheduler - This creates an instruction scheduler appropriate 139 /// for the target. 140 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 141 CodeGenOpt::Level OptLevel) { 142 const TargetLowering &TLI = IS->getTargetLowering(); 143 144 if (OptLevel == CodeGenOpt::None) 145 return createFastDAGScheduler(IS, OptLevel); 146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 147 return createTDListDAGScheduler(IS, OptLevel); 148 assert(TLI.getSchedulingPreference() == 149 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 150 return createBURRListDAGScheduler(IS, OptLevel); 151 } 152} 153 154// EmitInstrWithCustomInserter - This method should be implemented by targets 155// that mark instructions with the 'usesCustomInserter' flag. These 156// instructions are special in various ways, which require special support to 157// insert. The specified MachineInstr is created but not inserted into any 158// basic blocks, and this method is called to expand it into a sequence of 159// instructions, potentially also creating new basic blocks and control flow. 160// When new basic blocks are inserted and the edges from MBB to its successors 161// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 162// DenseMap. 163MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 164 MachineBasicBlock *MBB, 165 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 166#ifndef NDEBUG 167 errs() << "If a target marks an instruction with " 168 "'usesCustomInserter', it must implement " 169 "TargetLowering::EmitInstrWithCustomInserter!"; 170#endif 171 llvm_unreachable(0); 172 return 0; 173} 174 175/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 176/// physical register has only a single copy use, then coalesced the copy 177/// if possible. 178static void EmitLiveInCopy(MachineBasicBlock *MBB, 179 MachineBasicBlock::iterator &InsertPos, 180 unsigned VirtReg, unsigned PhysReg, 181 const TargetRegisterClass *RC, 182 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 183 const MachineRegisterInfo &MRI, 184 const TargetRegisterInfo &TRI, 185 const TargetInstrInfo &TII) { 186 unsigned NumUses = 0; 187 MachineInstr *UseMI = NULL; 188 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 189 UE = MRI.use_end(); UI != UE; ++UI) { 190 UseMI = &*UI; 191 if (++NumUses > 1) 192 break; 193 } 194 195 // If the number of uses is not one, or the use is not a move instruction, 196 // don't coalesce. Also, only coalesce away a virtual register to virtual 197 // register copy. 198 bool Coalesced = false; 199 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 200 if (NumUses == 1 && 201 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 202 TargetRegisterInfo::isVirtualRegister(DstReg)) { 203 VirtReg = DstReg; 204 Coalesced = true; 205 } 206 207 // Now find an ideal location to insert the copy. 208 MachineBasicBlock::iterator Pos = InsertPos; 209 while (Pos != MBB->begin()) { 210 MachineInstr *PrevMI = prior(Pos); 211 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 212 // copyRegToReg might emit multiple instructions to do a copy. 213 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 214 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 215 // This is what the BB looks like right now: 216 // r1024 = mov r0 217 // ... 218 // r1 = mov r1024 219 // 220 // We want to insert "r1025 = mov r1". Inserting this copy below the 221 // move to r1024 makes it impossible for that move to be coalesced. 222 // 223 // r1025 = mov r1 224 // r1024 = mov r0 225 // ... 226 // r1 = mov 1024 227 // r2 = mov 1025 228 break; // Woot! Found a good location. 229 --Pos; 230 } 231 232 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 233 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 234 (void) Emitted; 235 236 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 237 if (Coalesced) { 238 if (&*InsertPos == UseMI) ++InsertPos; 239 MBB->erase(UseMI); 240 } 241} 242 243/// EmitLiveInCopies - If this is the first basic block in the function, 244/// and if it has live ins that need to be copied into vregs, emit the 245/// copies into the block. 246static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 247 const MachineRegisterInfo &MRI, 248 const TargetRegisterInfo &TRI, 249 const TargetInstrInfo &TII) { 250 if (SchedLiveInCopies) { 251 // Emit the copies at a heuristically-determined location in the block. 252 DenseMap<MachineInstr*, unsigned> CopyRegMap; 253 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 254 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 255 E = MRI.livein_end(); LI != E; ++LI) 256 if (LI->second) { 257 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 258 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 259 RC, CopyRegMap, MRI, TRI, TII); 260 } 261 } else { 262 // Emit the copies into the top of the block. 263 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 264 E = MRI.livein_end(); LI != E; ++LI) 265 if (LI->second) { 266 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 267 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 268 LI->second, LI->first, RC, RC); 269 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 270 (void) Emitted; 271 } 272 } 273} 274 275//===----------------------------------------------------------------------===// 276// SelectionDAGISel code 277//===----------------------------------------------------------------------===// 278 279SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 280 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 281 FuncInfo(new FunctionLoweringInfo(TLI)), 282 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 283 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 284 GFI(), 285 OptLevel(OL), 286 DAGSize(0) 287{} 288 289SelectionDAGISel::~SelectionDAGISel() { 290 delete SDB; 291 delete CurDAG; 292 delete FuncInfo; 293} 294 295unsigned SelectionDAGISel::MakeReg(EVT VT) { 296 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 297} 298 299void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 300 AU.addRequired<AliasAnalysis>(); 301 AU.addPreserved<AliasAnalysis>(); 302 AU.addRequired<GCModuleInfo>(); 303 AU.addPreserved<GCModuleInfo>(); 304 AU.addRequired<DwarfWriter>(); 305 AU.addPreserved<DwarfWriter>(); 306 MachineFunctionPass::getAnalysisUsage(AU); 307} 308 309bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 310 Function &Fn = *mf.getFunction(); 311 312 // Do some sanity-checking on the command-line options. 313 assert((!EnableFastISelVerbose || EnableFastISel) && 314 "-fast-isel-verbose requires -fast-isel"); 315 assert((!EnableFastISelAbort || EnableFastISel) && 316 "-fast-isel-abort requires -fast-isel"); 317 318 // Get alias analysis for load/store combining. 319 AA = &getAnalysis<AliasAnalysis>(); 320 321 MF = &mf; 322 const TargetInstrInfo &TII = *TM.getInstrInfo(); 323 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 324 325 if (Fn.hasGC()) 326 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 327 else 328 GFI = 0; 329 RegInfo = &MF->getRegInfo(); 330 DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n"); 331 332 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 333 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 334 CurDAG->init(*MF, MMI, DW); 335 FuncInfo->set(Fn, *MF, EnableFastISel); 336 SDB->init(GFI, *AA); 337 338 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 339 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 340 // Mark landing pad. 341 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 342 343 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 344 345 // If the first basic block in the function has live ins that need to be 346 // copied into vregs, emit the copies into the top of the block before 347 // emitting the code for the block. 348 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 349 350 // Add function live-ins to entry block live-in set. 351 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 352 E = RegInfo->livein_end(); I != E; ++I) 353 MF->begin()->addLiveIn(I->first); 354 355#ifndef NDEBUG 356 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 357 "Not all catch info was assigned to a landing pad!"); 358#endif 359 360 FuncInfo->clear(); 361 362 return true; 363} 364 365void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 366 BasicBlock::iterator Begin, 367 BasicBlock::iterator End, 368 bool &HadTailCall) { 369 SDB->setCurrentBasicBlock(BB); 370 MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); 371 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 372 373 // Lower all of the non-terminator instructions. If a call is emitted 374 // as a tail call, cease emitting nodes for this block. 375 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 376 if (MDDbgKind) { 377 // Update DebugLoc if debug information is attached with this 378 // instruction. 379 if (!isa<DbgInfoIntrinsic>(I)) 380 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) { 381 DILocation DILoc(Dbg); 382 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 383 SDB->setCurDebugLoc(Loc); 384 if (MF->getDefaultDebugLoc().isUnknown()) 385 MF->setDefaultDebugLoc(Loc); 386 } 387 } 388 if (!isa<TerminatorInst>(I)) 389 SDB->visit(*I); 390 } 391 392 if (!SDB->HasTailCall) { 393 // Ensure that all instructions which are used outside of their defining 394 // blocks are available as virtual registers. Invoke is handled elsewhere. 395 for (BasicBlock::iterator I = Begin; I != End; ++I) 396 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 397 SDB->CopyToExportRegsIfNeeded(I); 398 399 // Handle PHI nodes in successor blocks. 400 if (End == LLVMBB->end()) { 401 HandlePHINodesInSuccessorBlocks(LLVMBB); 402 403 // Lower the terminator after the copies are emitted. 404 SDB->visit(*LLVMBB->getTerminator()); 405 } 406 } 407 408 // Make sure the root of the DAG is up-to-date. 409 CurDAG->setRoot(SDB->getControlRoot()); 410 411 // Final step, emit the lowered DAG as machine code. 412 CodeGenAndEmitDAG(); 413 HadTailCall = SDB->HasTailCall; 414 SDB->clear(); 415} 416 417void SelectionDAGISel::ComputeLiveOutVRegInfo() { 418 SmallPtrSet<SDNode*, 128> VisitedNodes; 419 SmallVector<SDNode*, 128> Worklist; 420 421 Worklist.push_back(CurDAG->getRoot().getNode()); 422 423 APInt Mask; 424 APInt KnownZero; 425 APInt KnownOne; 426 427 while (!Worklist.empty()) { 428 SDNode *N = Worklist.back(); 429 Worklist.pop_back(); 430 431 // If we've already seen this node, ignore it. 432 if (!VisitedNodes.insert(N)) 433 continue; 434 435 // Otherwise, add all chain operands to the worklist. 436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 437 if (N->getOperand(i).getValueType() == MVT::Other) 438 Worklist.push_back(N->getOperand(i).getNode()); 439 440 // If this is a CopyToReg with a vreg dest, process it. 441 if (N->getOpcode() != ISD::CopyToReg) 442 continue; 443 444 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 445 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 446 continue; 447 448 // Ignore non-scalar or non-integer values. 449 SDValue Src = N->getOperand(2); 450 EVT SrcVT = Src.getValueType(); 451 if (!SrcVT.isInteger() || SrcVT.isVector()) 452 continue; 453 454 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 455 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 456 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 457 458 // Only install this information if it tells us something. 459 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 460 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 461 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 462 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 463 FunctionLoweringInfo::LiveOutInfo &LOI = 464 FuncInfo->LiveOutRegInfo[DestReg]; 465 LOI.NumSignBits = NumSignBits; 466 LOI.KnownOne = KnownOne; 467 LOI.KnownZero = KnownZero; 468 } 469 } 470} 471 472void SelectionDAGISel::CodeGenAndEmitDAG() { 473 std::string GroupName; 474 if (TimePassesIsEnabled) 475 GroupName = "Instruction Selection and Scheduling"; 476 std::string BlockName; 477 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 478 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 479 ViewSUnitDAGs) 480 BlockName = MF->getFunction()->getNameStr() + ":" + 481 BB->getBasicBlock()->getNameStr(); 482 483 DEBUG(errs() << "Initial selection DAG:\n"); 484 DEBUG(CurDAG->dump()); 485 486 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 487 488 // Run the DAG combiner in pre-legalize mode. 489 if (TimePassesIsEnabled) { 490 NamedRegionTimer T("DAG Combining 1", GroupName); 491 CurDAG->Combine(Unrestricted, *AA, OptLevel); 492 } else { 493 CurDAG->Combine(Unrestricted, *AA, OptLevel); 494 } 495 496 DEBUG(errs() << "Optimized lowered selection DAG:\n"); 497 DEBUG(CurDAG->dump()); 498 499 // Second step, hack on the DAG until it only uses operations and types that 500 // the target supports. 501 if (!DisableLegalizeTypes) { 502 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 503 BlockName); 504 505 bool Changed; 506 if (TimePassesIsEnabled) { 507 NamedRegionTimer T("Type Legalization", GroupName); 508 Changed = CurDAG->LegalizeTypes(); 509 } else { 510 Changed = CurDAG->LegalizeTypes(); 511 } 512 513 DEBUG(errs() << "Type-legalized selection DAG:\n"); 514 DEBUG(CurDAG->dump()); 515 516 if (Changed) { 517 if (ViewDAGCombineLT) 518 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 519 520 // Run the DAG combiner in post-type-legalize mode. 521 if (TimePassesIsEnabled) { 522 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 523 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 524 } else { 525 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 526 } 527 528 DEBUG(errs() << "Optimized type-legalized selection DAG:\n"); 529 DEBUG(CurDAG->dump()); 530 } 531 532 if (TimePassesIsEnabled) { 533 NamedRegionTimer T("Vector Legalization", GroupName); 534 Changed = CurDAG->LegalizeVectors(); 535 } else { 536 Changed = CurDAG->LegalizeVectors(); 537 } 538 539 if (Changed) { 540 if (TimePassesIsEnabled) { 541 NamedRegionTimer T("Type Legalization 2", GroupName); 542 Changed = CurDAG->LegalizeTypes(); 543 } else { 544 Changed = CurDAG->LegalizeTypes(); 545 } 546 547 if (ViewDAGCombineLT) 548 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 549 550 // Run the DAG combiner in post-type-legalize mode. 551 if (TimePassesIsEnabled) { 552 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 553 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 554 } else { 555 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 556 } 557 558 DEBUG(errs() << "Optimized vector-legalized selection DAG:\n"); 559 DEBUG(CurDAG->dump()); 560 } 561 } 562 563 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 564 565 if (TimePassesIsEnabled) { 566 NamedRegionTimer T("DAG Legalization", GroupName); 567 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 568 } else { 569 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 570 } 571 572 DEBUG(errs() << "Legalized selection DAG:\n"); 573 DEBUG(CurDAG->dump()); 574 575 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 576 577 // Run the DAG combiner in post-legalize mode. 578 if (TimePassesIsEnabled) { 579 NamedRegionTimer T("DAG Combining 2", GroupName); 580 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 581 } else { 582 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 583 } 584 585 DEBUG(errs() << "Optimized legalized selection DAG:\n"); 586 DEBUG(CurDAG->dump()); 587 588 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 589 590 if (OptLevel != CodeGenOpt::None) 591 ComputeLiveOutVRegInfo(); 592 593 // Third, instruction select all of the operations to machine code, adding the 594 // code to the MachineBasicBlock. 595 if (TimePassesIsEnabled) { 596 NamedRegionTimer T("Instruction Selection", GroupName); 597 InstructionSelect(); 598 } else { 599 InstructionSelect(); 600 } 601 602 DEBUG(errs() << "Selected selection DAG:\n"); 603 DEBUG(CurDAG->dump()); 604 605 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 606 607 // Schedule machine code. 608 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 609 if (TimePassesIsEnabled) { 610 NamedRegionTimer T("Instruction Scheduling", GroupName); 611 Scheduler->Run(CurDAG, BB, BB->end()); 612 } else { 613 Scheduler->Run(CurDAG, BB, BB->end()); 614 } 615 616 if (ViewSUnitDAGs) Scheduler->viewGraph(); 617 618 // Emit machine code to BB. This can change 'BB' to the last block being 619 // inserted into. 620 if (TimePassesIsEnabled) { 621 NamedRegionTimer T("Instruction Creation", GroupName); 622 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 623 } else { 624 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 625 } 626 627 // Free the scheduler state. 628 if (TimePassesIsEnabled) { 629 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 630 delete Scheduler; 631 } else { 632 delete Scheduler; 633 } 634 635 DEBUG(errs() << "Selected machine code:\n"); 636 DEBUG(BB->dump()); 637} 638 639void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 640 MachineFunction &MF, 641 MachineModuleInfo *MMI, 642 DwarfWriter *DW, 643 const TargetInstrInfo &TII) { 644 // Initialize the Fast-ISel state, if needed. 645 FastISel *FastIS = 0; 646 if (EnableFastISel) 647 FastIS = TLI.createFastISel(MF, MMI, DW, 648 FuncInfo->ValueMap, 649 FuncInfo->MBBMap, 650 FuncInfo->StaticAllocaMap 651#ifndef NDEBUG 652 , FuncInfo->CatchInfoLost 653#endif 654 ); 655 656 MetadataContext &TheMetadata = Fn.getContext().getMetadata(); 657 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 658 659 // Iterate over all basic blocks in the function. 660 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 661 BasicBlock *LLVMBB = &*I; 662 BB = FuncInfo->MBBMap[LLVMBB]; 663 664 BasicBlock::iterator const Begin = LLVMBB->begin(); 665 BasicBlock::iterator const End = LLVMBB->end(); 666 BasicBlock::iterator BI = Begin; 667 668 // Lower any arguments needed in this block if this is the entry block. 669 bool SuppressFastISel = false; 670 if (LLVMBB == &Fn.getEntryBlock()) { 671 LowerArguments(LLVMBB); 672 673 // If any of the arguments has the byval attribute, forgo 674 // fast-isel in the entry block. 675 if (FastIS) { 676 unsigned j = 1; 677 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 678 I != E; ++I, ++j) 679 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 680 if (EnableFastISelVerbose || EnableFastISelAbort) 681 errs() << "FastISel skips entry block due to byval argument\n"; 682 SuppressFastISel = true; 683 break; 684 } 685 } 686 } 687 688 if (MMI && BB->isLandingPad()) { 689 // Add a label to mark the beginning of the landing pad. Deletion of the 690 // landing pad can thus be detected via the MachineModuleInfo. 691 unsigned LabelID = MMI->addLandingPad(BB); 692 693 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 694 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 695 696 // Mark exception register as live in. 697 unsigned Reg = TLI.getExceptionAddressRegister(); 698 if (Reg) BB->addLiveIn(Reg); 699 700 // Mark exception selector register as live in. 701 Reg = TLI.getExceptionSelectorRegister(); 702 if (Reg) BB->addLiveIn(Reg); 703 704 // FIXME: Hack around an exception handling flaw (PR1508): the personality 705 // function and list of typeids logically belong to the invoke (or, if you 706 // like, the basic block containing the invoke), and need to be associated 707 // with it in the dwarf exception handling tables. Currently however the 708 // information is provided by an intrinsic (eh.selector) that can be moved 709 // to unexpected places by the optimizers: if the unwind edge is critical, 710 // then breaking it can result in the intrinsics being in the successor of 711 // the landing pad, not the landing pad itself. This results in exceptions 712 // not being caught because no typeids are associated with the invoke. 713 // This may not be the only way things can go wrong, but it is the only way 714 // we try to work around for the moment. 715 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 716 717 if (Br && Br->isUnconditional()) { // Critical edge? 718 BasicBlock::iterator I, E; 719 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 720 if (isa<EHSelectorInst>(I)) 721 break; 722 723 if (I == E) 724 // No catch info found - try to extract some from the successor. 725 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 726 } 727 } 728 729 // Before doing SelectionDAG ISel, see if FastISel has been requested. 730 if (FastIS && !SuppressFastISel) { 731 // Emit code for any incoming arguments. This must happen before 732 // beginning FastISel on the entry block. 733 if (LLVMBB == &Fn.getEntryBlock()) { 734 CurDAG->setRoot(SDB->getControlRoot()); 735 CodeGenAndEmitDAG(); 736 SDB->clear(); 737 } 738 FastIS->startNewBlock(BB); 739 // Do FastISel on as many instructions as possible. 740 for (; BI != End; ++BI) { 741 if (MDDbgKind) { 742 // Update DebugLoc if debug information is attached with this 743 // instruction. 744 if (!isa<DbgInfoIntrinsic>(BI)) 745 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, BI)) { 746 DILocation DILoc(Dbg); 747 DebugLoc Loc = ExtractDebugLocation(DILoc, 748 MF.getDebugLocInfo()); 749 FastIS->setCurDebugLoc(Loc); 750 if (MF.getDefaultDebugLoc().isUnknown()) 751 MF.setDefaultDebugLoc(Loc); 752 } 753 } 754 755 // Just before the terminator instruction, insert instructions to 756 // feed PHI nodes in successor blocks. 757 if (isa<TerminatorInst>(BI)) 758 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 759 if (EnableFastISelVerbose || EnableFastISelAbort) { 760 errs() << "FastISel miss: "; 761 BI->dump(); 762 } 763 assert(!EnableFastISelAbort && 764 "FastISel didn't handle a PHI in a successor"); 765 break; 766 } 767 768 // First try normal tablegen-generated "fast" selection. 769 if (FastIS->SelectInstruction(BI)) 770 continue; 771 772 // Next, try calling the target to attempt to handle the instruction. 773 if (FastIS->TargetSelectInstruction(BI)) 774 continue; 775 776 // Then handle certain instructions as single-LLVM-Instruction blocks. 777 if (isa<CallInst>(BI)) { 778 if (EnableFastISelVerbose || EnableFastISelAbort) { 779 errs() << "FastISel missed call: "; 780 BI->dump(); 781 } 782 783 if (BI->getType() != Type::getVoidTy(*CurDAG->getContext())) { 784 unsigned &R = FuncInfo->ValueMap[BI]; 785 if (!R) 786 R = FuncInfo->CreateRegForValue(BI); 787 } 788 789 SDB->setCurDebugLoc(FastIS->getCurDebugLoc()); 790 791 bool HadTailCall = false; 792 SelectBasicBlock(LLVMBB, BI, next(BI), HadTailCall); 793 794 // If the call was emitted as a tail call, we're done with the block. 795 if (HadTailCall) { 796 BI = End; 797 break; 798 } 799 800 // If the instruction was codegen'd with multiple blocks, 801 // inform the FastISel object where to resume inserting. 802 FastIS->setCurrentBlock(BB); 803 continue; 804 } 805 806 // Otherwise, give up on FastISel for the rest of the block. 807 // For now, be a little lenient about non-branch terminators. 808 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 809 if (EnableFastISelVerbose || EnableFastISelAbort) { 810 errs() << "FastISel miss: "; 811 BI->dump(); 812 } 813 if (EnableFastISelAbort) 814 // The "fast" selector couldn't handle something and bailed. 815 // For the purpose of debugging, just abort. 816 llvm_unreachable("FastISel didn't select the entire block"); 817 } 818 break; 819 } 820 } 821 822 // Run SelectionDAG instruction selection on the remainder of the block 823 // not handled by FastISel. If FastISel is not run, this is the entire 824 // block. 825 if (BI != End) { 826 // If FastISel is run and it has known DebugLoc then use it. 827 if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) 828 SDB->setCurDebugLoc(FastIS->getCurDebugLoc()); 829 bool HadTailCall; 830 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 831 } 832 833 FinishBasicBlock(); 834 } 835 836 delete FastIS; 837} 838 839void 840SelectionDAGISel::FinishBasicBlock() { 841 842 DEBUG(errs() << "Target-post-processed machine code:\n"); 843 DEBUG(BB->dump()); 844 845 DEBUG(errs() << "Total amount of phi nodes to update: " 846 << SDB->PHINodesToUpdate.size() << "\n"); 847 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 848 errs() << "Node " << i << " : (" 849 << SDB->PHINodesToUpdate[i].first 850 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 851 852 // Next, now that we know what the last MBB the LLVM BB expanded is, update 853 // PHI nodes in successors. 854 if (SDB->SwitchCases.empty() && 855 SDB->JTCases.empty() && 856 SDB->BitTestCases.empty()) { 857 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 858 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 859 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 860 "This is not a machine PHI node that we are updating!"); 861 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 862 false)); 863 PHI->addOperand(MachineOperand::CreateMBB(BB)); 864 } 865 SDB->PHINodesToUpdate.clear(); 866 return; 867 } 868 869 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 870 // Lower header first, if it wasn't already lowered 871 if (!SDB->BitTestCases[i].Emitted) { 872 // Set the current basic block to the mbb we wish to insert the code into 873 BB = SDB->BitTestCases[i].Parent; 874 SDB->setCurrentBasicBlock(BB); 875 // Emit the code 876 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 877 CurDAG->setRoot(SDB->getRoot()); 878 CodeGenAndEmitDAG(); 879 SDB->clear(); 880 } 881 882 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 883 // Set the current basic block to the mbb we wish to insert the code into 884 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 885 SDB->setCurrentBasicBlock(BB); 886 // Emit the code 887 if (j+1 != ej) 888 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 889 SDB->BitTestCases[i].Reg, 890 SDB->BitTestCases[i].Cases[j]); 891 else 892 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 893 SDB->BitTestCases[i].Reg, 894 SDB->BitTestCases[i].Cases[j]); 895 896 897 CurDAG->setRoot(SDB->getRoot()); 898 CodeGenAndEmitDAG(); 899 SDB->clear(); 900 } 901 902 // Update PHI Nodes 903 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 904 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 905 MachineBasicBlock *PHIBB = PHI->getParent(); 906 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 907 "This is not a machine PHI node that we are updating!"); 908 // This is "default" BB. We have two jumps to it. From "header" BB and 909 // from last "case" BB. 910 if (PHIBB == SDB->BitTestCases[i].Default) { 911 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 912 false)); 913 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 914 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 915 false)); 916 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 917 back().ThisBB)); 918 } 919 // One of "cases" BB. 920 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 921 j != ej; ++j) { 922 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 923 if (cBB->succ_end() != 924 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 925 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 926 false)); 927 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 928 } 929 } 930 } 931 } 932 SDB->BitTestCases.clear(); 933 934 // If the JumpTable record is filled in, then we need to emit a jump table. 935 // Updating the PHI nodes is tricky in this case, since we need to determine 936 // whether the PHI is a successor of the range check MBB or the jump table MBB 937 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 938 // Lower header first, if it wasn't already lowered 939 if (!SDB->JTCases[i].first.Emitted) { 940 // Set the current basic block to the mbb we wish to insert the code into 941 BB = SDB->JTCases[i].first.HeaderBB; 942 SDB->setCurrentBasicBlock(BB); 943 // Emit the code 944 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 945 CurDAG->setRoot(SDB->getRoot()); 946 CodeGenAndEmitDAG(); 947 SDB->clear(); 948 } 949 950 // Set the current basic block to the mbb we wish to insert the code into 951 BB = SDB->JTCases[i].second.MBB; 952 SDB->setCurrentBasicBlock(BB); 953 // Emit the code 954 SDB->visitJumpTable(SDB->JTCases[i].second); 955 CurDAG->setRoot(SDB->getRoot()); 956 CodeGenAndEmitDAG(); 957 SDB->clear(); 958 959 // Update PHI Nodes 960 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 961 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 962 MachineBasicBlock *PHIBB = PHI->getParent(); 963 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 964 "This is not a machine PHI node that we are updating!"); 965 // "default" BB. We can go there only from header BB. 966 if (PHIBB == SDB->JTCases[i].second.Default) { 967 PHI->addOperand 968 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 969 PHI->addOperand 970 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 971 } 972 // JT BB. Just iterate over successors here 973 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 974 PHI->addOperand 975 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 976 PHI->addOperand(MachineOperand::CreateMBB(BB)); 977 } 978 } 979 } 980 SDB->JTCases.clear(); 981 982 // If the switch block involved a branch to one of the actual successors, we 983 // need to update PHI nodes in that block. 984 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 985 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 986 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 987 "This is not a machine PHI node that we are updating!"); 988 if (BB->isSuccessor(PHI->getParent())) { 989 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 990 false)); 991 PHI->addOperand(MachineOperand::CreateMBB(BB)); 992 } 993 } 994 995 // If we generated any switch lowering information, build and codegen any 996 // additional DAGs necessary. 997 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 998 // Set the current basic block to the mbb we wish to insert the code into 999 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1000 SDB->setCurrentBasicBlock(BB); 1001 1002 // Emit the code 1003 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1004 CurDAG->setRoot(SDB->getRoot()); 1005 CodeGenAndEmitDAG(); 1006 1007 // Handle any PHI nodes in successors of this chunk, as if we were coming 1008 // from the original BB before switch expansion. Note that PHI nodes can 1009 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1010 // handle them the right number of times. 1011 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1012 // If new BB's are created during scheduling, the edges may have been 1013 // updated. That is, the edge from ThisBB to BB may have been split and 1014 // BB's predecessor is now another block. 1015 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1016 SDB->EdgeMapping.find(BB); 1017 if (EI != SDB->EdgeMapping.end()) 1018 ThisBB = EI->second; 1019 for (MachineBasicBlock::iterator Phi = BB->begin(); 1020 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 1021 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 1022 for (unsigned pn = 0; ; ++pn) { 1023 assert(pn != SDB->PHINodesToUpdate.size() && 1024 "Didn't find PHI entry!"); 1025 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1026 Phi->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pn]. 1027 second, false)); 1028 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1029 break; 1030 } 1031 } 1032 } 1033 1034 // Don't process RHS if same block as LHS. 1035 if (BB == SDB->SwitchCases[i].FalseBB) 1036 SDB->SwitchCases[i].FalseBB = 0; 1037 1038 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1039 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1040 SDB->SwitchCases[i].FalseBB = 0; 1041 } 1042 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1043 SDB->clear(); 1044 } 1045 SDB->SwitchCases.clear(); 1046 1047 SDB->PHINodesToUpdate.clear(); 1048} 1049 1050 1051/// Create the scheduler. If a specific scheduler was specified 1052/// via the SchedulerRegistry, use it, otherwise select the 1053/// one preferred by the target. 1054/// 1055ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1056 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1057 1058 if (!Ctor) { 1059 Ctor = ISHeuristic; 1060 RegisterScheduler::setDefault(Ctor); 1061 } 1062 1063 return Ctor(this, OptLevel); 1064} 1065 1066ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1067 return new ScheduleHazardRecognizer(); 1068} 1069 1070//===----------------------------------------------------------------------===// 1071// Helper functions used by the generated instruction selector. 1072//===----------------------------------------------------------------------===// 1073// Calls to these methods are generated by tblgen. 1074 1075/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1076/// the dag combiner simplified the 255, we still want to match. RHS is the 1077/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1078/// specified in the .td file (e.g. 255). 1079bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1080 int64_t DesiredMaskS) const { 1081 const APInt &ActualMask = RHS->getAPIntValue(); 1082 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1083 1084 // If the actual mask exactly matches, success! 1085 if (ActualMask == DesiredMask) 1086 return true; 1087 1088 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1089 if (ActualMask.intersects(~DesiredMask)) 1090 return false; 1091 1092 // Otherwise, the DAG Combiner may have proven that the value coming in is 1093 // either already zero or is not demanded. Check for known zero input bits. 1094 APInt NeededMask = DesiredMask & ~ActualMask; 1095 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1096 return true; 1097 1098 // TODO: check to see if missing bits are just not demanded. 1099 1100 // Otherwise, this pattern doesn't match. 1101 return false; 1102} 1103 1104/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1105/// the dag combiner simplified the 255, we still want to match. RHS is the 1106/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1107/// specified in the .td file (e.g. 255). 1108bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1109 int64_t DesiredMaskS) const { 1110 const APInt &ActualMask = RHS->getAPIntValue(); 1111 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1112 1113 // If the actual mask exactly matches, success! 1114 if (ActualMask == DesiredMask) 1115 return true; 1116 1117 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1118 if (ActualMask.intersects(~DesiredMask)) 1119 return false; 1120 1121 // Otherwise, the DAG Combiner may have proven that the value coming in is 1122 // either already zero or is not demanded. Check for known zero input bits. 1123 APInt NeededMask = DesiredMask & ~ActualMask; 1124 1125 APInt KnownZero, KnownOne; 1126 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1127 1128 // If all the missing bits in the or are already known to be set, match! 1129 if ((NeededMask & KnownOne) == NeededMask) 1130 return true; 1131 1132 // TODO: check to see if missing bits are just not demanded. 1133 1134 // Otherwise, this pattern doesn't match. 1135 return false; 1136} 1137 1138 1139/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1140/// by tblgen. Others should not call it. 1141void SelectionDAGISel:: 1142SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1143 std::vector<SDValue> InOps; 1144 std::swap(InOps, Ops); 1145 1146 Ops.push_back(InOps[0]); // input chain. 1147 Ops.push_back(InOps[1]); // input asm string. 1148 1149 unsigned i = 2, e = InOps.size(); 1150 if (InOps[e-1].getValueType() == MVT::Flag) 1151 --e; // Don't process a flag operand if it is here. 1152 1153 while (i != e) { 1154 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1155 if ((Flags & 7) != 4 /*MEM*/) { 1156 // Just skip over this operand, copying the operands verbatim. 1157 Ops.insert(Ops.end(), InOps.begin()+i, 1158 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1159 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1160 } else { 1161 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1162 "Memory operand with multiple values?"); 1163 // Otherwise, this is a memory operand. Ask the target to select it. 1164 std::vector<SDValue> SelOps; 1165 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1166 llvm_report_error("Could not match memory address. Inline asm" 1167 " failure!"); 1168 } 1169 1170 // Add this to the output node. 1171 EVT IntPtrTy = TLI.getPointerTy(); 1172 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1173 IntPtrTy)); 1174 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1175 i += 2; 1176 } 1177 } 1178 1179 // Add the flag input back if present. 1180 if (e != InOps.size()) 1181 Ops.push_back(InOps.back()); 1182} 1183 1184/// findFlagUse - Return use of EVT::Flag value produced by the specified 1185/// SDNode. 1186/// 1187static SDNode *findFlagUse(SDNode *N) { 1188 unsigned FlagResNo = N->getNumValues()-1; 1189 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1190 SDUse &Use = I.getUse(); 1191 if (Use.getResNo() == FlagResNo) 1192 return Use.getUser(); 1193 } 1194 return NULL; 1195} 1196 1197/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1198/// This function recursively traverses up the operand chain, ignoring 1199/// certain nodes. 1200static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1201 SDNode *Root, 1202 SmallPtrSet<SDNode*, 16> &Visited) { 1203 if (Use->getNodeId() < Def->getNodeId() || 1204 !Visited.insert(Use)) 1205 return false; 1206 1207 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1208 SDNode *N = Use->getOperand(i).getNode(); 1209 if (N == Def) { 1210 if (Use == ImmedUse || Use == Root) 1211 continue; // We are not looking for immediate use. 1212 assert(N != Root); 1213 return true; 1214 } 1215 1216 // Traverse up the operand chain. 1217 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1218 return true; 1219 } 1220 return false; 1221} 1222 1223/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1224/// be reached. Return true if that's the case. However, ignore direct uses 1225/// by ImmedUse (which would be U in the example illustrated in 1226/// IsLegalAndProfitableToFold) and by Root (which can happen in the store 1227/// case). 1228/// FIXME: to be really generic, we should allow direct use by any node 1229/// that is being folded. But realisticly since we only fold loads which 1230/// have one non-chain use, we only need to watch out for load/op/store 1231/// and load/op/cmp case where the root (store / cmp) may reach the load via 1232/// its chain operand. 1233static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1234 SmallPtrSet<SDNode*, 16> Visited; 1235 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1236} 1237 1238/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 1239/// U can be folded during instruction selection that starts at Root and 1240/// folding N is profitable. 1241bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 1242 SDNode *Root) const { 1243 if (OptLevel == CodeGenOpt::None) return false; 1244 1245 // If Root use can somehow reach N through a path that that doesn't contain 1246 // U then folding N would create a cycle. e.g. In the following 1247 // diagram, Root can reach N through X. If N is folded into into Root, then 1248 // X is both a predecessor and a successor of U. 1249 // 1250 // [N*] // 1251 // ^ ^ // 1252 // / \ // 1253 // [U*] [X]? // 1254 // ^ ^ // 1255 // \ / // 1256 // \ / // 1257 // [Root*] // 1258 // 1259 // * indicates nodes to be folded together. 1260 // 1261 // If Root produces a flag, then it gets (even more) interesting. Since it 1262 // will be "glued" together with its flag use in the scheduler, we need to 1263 // check if it might reach N. 1264 // 1265 // [N*] // 1266 // ^ ^ // 1267 // / \ // 1268 // [U*] [X]? // 1269 // ^ ^ // 1270 // \ \ // 1271 // \ | // 1272 // [Root*] | // 1273 // ^ | // 1274 // f | // 1275 // | / // 1276 // [Y] / // 1277 // ^ / // 1278 // f / // 1279 // | / // 1280 // [FU] // 1281 // 1282 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1283 // (call it Fold), then X is a predecessor of FU and a successor of 1284 // Fold. But since Fold and FU are flagged together, this will create 1285 // a cycle in the scheduling graph. 1286 1287 EVT VT = Root->getValueType(Root->getNumValues()-1); 1288 while (VT == MVT::Flag) { 1289 SDNode *FU = findFlagUse(Root); 1290 if (FU == NULL) 1291 break; 1292 Root = FU; 1293 VT = Root->getValueType(Root->getNumValues()-1); 1294 } 1295 1296 return !isNonImmUse(Root, N, U); 1297} 1298 1299SDNode *SelectionDAGISel::Select_INLINEASM(SDValue N) { 1300 std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end()); 1301 SelectInlineAsmMemoryOperands(Ops); 1302 1303 std::vector<EVT> VTs; 1304 VTs.push_back(MVT::Other); 1305 VTs.push_back(MVT::Flag); 1306 SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(), 1307 VTs, &Ops[0], Ops.size()); 1308 return New.getNode(); 1309} 1310 1311SDNode *SelectionDAGISel::Select_UNDEF(const SDValue &N) { 1312 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF, 1313 N.getValueType()); 1314} 1315 1316SDNode *SelectionDAGISel::Select_DBG_LABEL(const SDValue &N) { 1317 SDValue Chain = N.getOperand(0); 1318 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1319 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1320 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DBG_LABEL, 1321 MVT::Other, Tmp, Chain); 1322} 1323 1324SDNode *SelectionDAGISel::Select_EH_LABEL(const SDValue &N) { 1325 SDValue Chain = N.getOperand(0); 1326 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1327 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1328 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL, 1329 MVT::Other, Tmp, Chain); 1330} 1331 1332void SelectionDAGISel::CannotYetSelect(SDValue N) { 1333 std::string msg; 1334 raw_string_ostream Msg(msg); 1335 Msg << "Cannot yet select: "; 1336 N.getNode()->print(Msg, CurDAG); 1337 llvm_report_error(Msg.str()); 1338} 1339 1340void SelectionDAGISel::CannotYetSelectIntrinsic(SDValue N) { 1341 errs() << "Cannot yet select: "; 1342 unsigned iid = 1343 cast<ConstantSDNode>(N.getOperand(N.getOperand(0).getValueType() == MVT::Other))->getZExtValue(); 1344 if (iid < Intrinsic::num_intrinsics) 1345 llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid)); 1346 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 1347 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 1348 tii->getName(iid)); 1349} 1350 1351char SelectionDAGISel::ID = 0; 1352