SelectionDAGISel.cpp revision 8181bd1f95ae9994edb390dd9acd0b7b12375219
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/Timer.h" 49#include <algorithm> 50using namespace llvm; 51 52static cl::opt<bool> 53EnableValueProp("enable-value-prop", cl::Hidden); 54static cl::opt<bool> 55EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 56 57 58#ifndef NDEBUG 59static cl::opt<bool> 60ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 61 cl::desc("Pop up a window to show dags before the first " 62 "dag combine pass")); 63static cl::opt<bool> 64ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 65 cl::desc("Pop up a window to show dags before legalize types")); 66static cl::opt<bool> 67ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 68 cl::desc("Pop up a window to show dags before legalize")); 69static cl::opt<bool> 70ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before the second " 72 "dag combine pass")); 73static cl::opt<bool> 74ViewISelDAGs("view-isel-dags", cl::Hidden, 75 cl::desc("Pop up a window to show isel dags as they are selected")); 76static cl::opt<bool> 77ViewSchedDAGs("view-sched-dags", cl::Hidden, 78 cl::desc("Pop up a window to show sched dags as they are processed")); 79static cl::opt<bool> 80ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 81 cl::desc("Pop up a window to show SUnit dags after they are processed")); 82#else 83static const bool ViewDAGCombine1 = false, 84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 85 ViewDAGCombine2 = false, 86 ViewISelDAGs = false, ViewSchedDAGs = false, 87 ViewSUnitDAGs = false; 88#endif 89 90//===---------------------------------------------------------------------===// 91/// 92/// RegisterScheduler class - Track the registration of instruction schedulers. 93/// 94//===---------------------------------------------------------------------===// 95MachinePassRegistry RegisterScheduler::Registry; 96 97//===---------------------------------------------------------------------===// 98/// 99/// ISHeuristic command line option for instruction schedulers. 100/// 101//===---------------------------------------------------------------------===// 102static cl::opt<RegisterScheduler::FunctionPassCtor, false, 103 RegisterPassParser<RegisterScheduler> > 104ISHeuristic("pre-RA-sched", 105 cl::init(&createDefaultScheduler), 106 cl::desc("Instruction schedulers available (before register" 107 " allocation):")); 108 109static RegisterScheduler 110defaultListDAGScheduler("default", " Best scheduler for the target", 111 createDefaultScheduler); 112 113namespace { struct SDISelAsmOperandInfo; } 114 115/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence 116/// insertvalue or extractvalue indices that identify a member, return 117/// the linearized index of the start of the member. 118/// 119static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, 120 const unsigned *Indices, 121 const unsigned *IndicesEnd, 122 unsigned CurIndex = 0) { 123 // Base case: We're done. 124 if (Indices && Indices == IndicesEnd) 125 return CurIndex; 126 127 // Given a struct type, recursively traverse the elements. 128 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 129 for (StructType::element_iterator EB = STy->element_begin(), 130 EI = EB, 131 EE = STy->element_end(); 132 EI != EE; ++EI) { 133 if (Indices && *Indices == unsigned(EI - EB)) 134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex); 135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex); 136 } 137 } 138 // Given an array type, recursively traverse the elements. 139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 140 const Type *EltTy = ATy->getElementType(); 141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) { 142 if (Indices && *Indices == i) 143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex); 144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex); 145 } 146 } 147 // We haven't found the type we're looking for, so keep searching. 148 return CurIndex + 1; 149} 150 151/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of 152/// MVTs that represent all the individual underlying 153/// non-aggregate types that comprise it. 154/// 155/// If Offsets is non-null, it points to a vector to be filled in 156/// with the in-memory offsets of each of the individual values. 157/// 158static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, 159 SmallVectorImpl<MVT> &ValueVTs, 160 SmallVectorImpl<uint64_t> *Offsets = 0, 161 uint64_t StartingOffset = 0) { 162 // Given a struct type, recursively traverse the elements. 163 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); 165 for (StructType::element_iterator EB = STy->element_begin(), 166 EI = EB, 167 EE = STy->element_end(); 168 EI != EE; ++EI) 169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, 170 StartingOffset + SL->getElementOffset(EI - EB)); 171 return; 172 } 173 // Given an array type, recursively traverse the elements. 174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 175 const Type *EltTy = ATy->getElementType(); 176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy); 177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) 178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, 179 StartingOffset + i * EltSize); 180 return; 181 } 182 // Base case: we can get an MVT for this LLVM IR type. 183 ValueVTs.push_back(TLI.getValueType(Ty)); 184 if (Offsets) 185 Offsets->push_back(StartingOffset); 186} 187 188namespace { 189 /// RegsForValue - This struct represents the registers (physical or virtual) 190 /// that a particular set of values is assigned, and the type information about 191 /// the value. The most common situation is to represent one value at a time, 192 /// but struct or array values are handled element-wise as multiple values. 193 /// The splitting of aggregates is performed recursively, so that we never 194 /// have aggregate-typed registers. The values at this point do not necessarily 195 /// have legal types, so each value may require one or more registers of some 196 /// legal type. 197 /// 198 struct VISIBILITY_HIDDEN RegsForValue { 199 /// TLI - The TargetLowering object. 200 /// 201 const TargetLowering *TLI; 202 203 /// ValueVTs - The value types of the values, which may not be legal, and 204 /// may need be promoted or synthesized from one or more registers. 205 /// 206 SmallVector<MVT, 4> ValueVTs; 207 208 /// RegVTs - The value types of the registers. This is the same size as 209 /// ValueVTs and it records, for each value, what the type of the assigned 210 /// register or registers are. (Individual values are never synthesized 211 /// from more than one type of register.) 212 /// 213 /// With virtual registers, the contents of RegVTs is redundant with TLI's 214 /// getRegisterType member function, however when with physical registers 215 /// it is necessary to have a separate record of the types. 216 /// 217 SmallVector<MVT, 4> RegVTs; 218 219 /// Regs - This list holds the registers assigned to the values. 220 /// Each legal or promoted value requires one register, and each 221 /// expanded value requires multiple registers. 222 /// 223 SmallVector<unsigned, 4> Regs; 224 225 RegsForValue() : TLI(0) {} 226 227 RegsForValue(const TargetLowering &tli, 228 const SmallVector<unsigned, 4> ®s, 229 MVT regvt, MVT valuevt) 230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 231 RegsForValue(const TargetLowering &tli, 232 const SmallVector<unsigned, 4> ®s, 233 const SmallVector<MVT, 4> ®vts, 234 const SmallVector<MVT, 4> &valuevts) 235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 236 RegsForValue(const TargetLowering &tli, 237 unsigned Reg, const Type *Ty) : TLI(&tli) { 238 ComputeValueVTs(tli, Ty, ValueVTs); 239 240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 241 MVT ValueVT = ValueVTs[Value]; 242 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 243 MVT RegisterVT = TLI->getRegisterType(ValueVT); 244 for (unsigned i = 0; i != NumRegs; ++i) 245 Regs.push_back(Reg + i); 246 RegVTs.push_back(RegisterVT); 247 Reg += NumRegs; 248 } 249 } 250 251 /// append - Add the specified values to this one. 252 void append(const RegsForValue &RHS) { 253 TLI = RHS.TLI; 254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 256 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 257 } 258 259 260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 261 /// this value and returns the result as a ValueVTs value. This uses 262 /// Chain/Flag as the input and updates them for the output Chain/Flag. 263 /// If the Flag pointer is NULL, no flag is used. 264 SDValue getCopyFromRegs(SelectionDAG &DAG, 265 SDValue &Chain, SDValue *Flag) const; 266 267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 268 /// specified value into the registers specified by this object. This uses 269 /// Chain/Flag as the input and updates them for the output Chain/Flag. 270 /// If the Flag pointer is NULL, no flag is used. 271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, 272 SDValue &Chain, SDValue *Flag) const; 273 274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 275 /// operand list. This adds the code marker and includes the number of 276 /// values added into it. 277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 278 std::vector<SDValue> &Ops) const; 279 }; 280} 281 282namespace llvm { 283 //===--------------------------------------------------------------------===// 284 /// createDefaultScheduler - This creates an instruction scheduler appropriate 285 /// for the target. 286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 287 SelectionDAG *DAG, 288 MachineBasicBlock *BB, 289 bool Fast) { 290 TargetLowering &TLI = IS->getTargetLowering(); 291 292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 293 return createTDListDAGScheduler(IS, DAG, BB, Fast); 294 } else { 295 assert(TLI.getSchedulingPreference() == 296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 297 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 298 } 299 } 300 301 302 //===--------------------------------------------------------------------===// 303 /// FunctionLoweringInfo - This contains information that is global to a 304 /// function that is used when lowering a region of the function. 305 class FunctionLoweringInfo { 306 public: 307 TargetLowering &TLI; 308 Function &Fn; 309 MachineFunction &MF; 310 MachineRegisterInfo &RegInfo; 311 312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 313 314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 316 317 /// ValueMap - Since we emit code for the function a basic block at a time, 318 /// we must remember which virtual registers hold the values for 319 /// cross-basic-block values. 320 DenseMap<const Value*, unsigned> ValueMap; 321 322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 323 /// the entry block. This allows the allocas to be efficiently referenced 324 /// anywhere in the function. 325 std::map<const AllocaInst*, int> StaticAllocaMap; 326 327#ifndef NDEBUG 328 SmallSet<Instruction*, 8> CatchInfoLost; 329 SmallSet<Instruction*, 8> CatchInfoFound; 330#endif 331 332 unsigned MakeReg(MVT VT) { 333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 334 } 335 336 /// isExportedInst - Return true if the specified value is an instruction 337 /// exported from its block. 338 bool isExportedInst(const Value *V) { 339 return ValueMap.count(V); 340 } 341 342 unsigned CreateRegForValue(const Value *V); 343 344 unsigned InitializeRegForValue(const Value *V) { 345 unsigned &R = ValueMap[V]; 346 assert(R == 0 && "Already initialized this value register!"); 347 return R = CreateRegForValue(V); 348 } 349 350 struct LiveOutInfo { 351 unsigned NumSignBits; 352 APInt KnownOne, KnownZero; 353 LiveOutInfo() : NumSignBits(0) {} 354 }; 355 356 /// LiveOutRegInfo - Information about live out vregs, indexed by their 357 /// register number offset by 'FirstVirtualRegister'. 358 std::vector<LiveOutInfo> LiveOutRegInfo; 359 }; 360} 361 362/// isSelector - Return true if this instruction is a call to the 363/// eh.selector intrinsic. 364static bool isSelector(Instruction *I) { 365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 367 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 368 return false; 369} 370 371/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 372/// PHI nodes or outside of the basic block that defines it, or used by a 373/// switch or atomic instruction, which may expand to multiple basic blocks. 374static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 375 if (isa<PHINode>(I)) return true; 376 BasicBlock *BB = I->getParent(); 377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 379 // FIXME: Remove switchinst special case. 380 isa<SwitchInst>(*UI)) 381 return true; 382 return false; 383} 384 385/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 386/// entry block, return true. This includes arguments used by switches, since 387/// the switch may expand into multiple basic blocks. 388static bool isOnlyUsedInEntryBlock(Argument *A) { 389 BasicBlock *Entry = A->getParent()->begin(); 390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 392 return false; // Use not in entry block. 393 return true; 394} 395 396FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 397 Function &fn, MachineFunction &mf) 398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 399 400 // Create a vreg for each argument register that is not dead and is used 401 // outside of the entry block for the function. 402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 403 AI != E; ++AI) 404 if (!isOnlyUsedInEntryBlock(AI)) 405 InitializeRegForValue(AI); 406 407 // Initialize the mapping of values to registers. This is only set up for 408 // instruction values that are used outside of the block that defines 409 // them. 410 Function::iterator BB = Fn.begin(), EB = Fn.end(); 411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 414 const Type *Ty = AI->getAllocatedType(); 415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 416 unsigned Align = 417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 418 AI->getAlignment()); 419 420 TySize *= CUI->getZExtValue(); // Get total allocated size. 421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 422 StaticAllocaMap[AI] = 423 MF.getFrameInfo()->CreateStackObject(TySize, Align); 424 } 425 426 for (; BB != EB; ++BB) 427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 429 if (!isa<AllocaInst>(I) || 430 !StaticAllocaMap.count(cast<AllocaInst>(I))) 431 InitializeRegForValue(I); 432 433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 434 // also creates the initial PHI MachineInstrs, though none of the input 435 // operands are populated. 436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); 438 MBBMap[BB] = MBB; 439 MF.push_back(MBB); 440 441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 442 // appropriate. 443 PHINode *PN; 444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 445 if (PN->use_empty()) continue; 446 447 MVT VT = TLI.getValueType(PN->getType()); 448 unsigned NumRegisters = TLI.getNumRegisters(VT); 449 unsigned PHIReg = ValueMap[PN]; 450 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 451 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 452 for (unsigned i = 0; i != NumRegisters; ++i) 453 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 454 } 455 } 456} 457 458/// CreateRegForValue - Allocate the appropriate number of virtual registers of 459/// the correctly promoted or expanded types. Assign these registers 460/// consecutive vreg numbers and return the first assigned number. 461/// 462/// In the case that the given value has struct or array type, this function 463/// will assign registers for each member or element. 464/// 465unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 466 SmallVector<MVT, 4> ValueVTs; 467 ComputeValueVTs(TLI, V->getType(), ValueVTs); 468 469 unsigned FirstReg = 0; 470 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 471 MVT ValueVT = ValueVTs[Value]; 472 MVT RegisterVT = TLI.getRegisterType(ValueVT); 473 474 unsigned NumRegs = TLI.getNumRegisters(ValueVT); 475 for (unsigned i = 0; i != NumRegs; ++i) { 476 unsigned R = MakeReg(RegisterVT); 477 if (!FirstReg) FirstReg = R; 478 } 479 } 480 return FirstReg; 481} 482 483//===----------------------------------------------------------------------===// 484/// SelectionDAGLowering - This is the common target-independent lowering 485/// implementation that is parameterized by a TargetLowering object. 486/// Also, targets can overload any lowering method. 487/// 488namespace llvm { 489class SelectionDAGLowering { 490 MachineBasicBlock *CurMBB; 491 492 DenseMap<const Value*, SDValue> NodeMap; 493 494 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 495 /// them up and then emit token factor nodes when possible. This allows us to 496 /// get simple disambiguation between loads without worrying about alias 497 /// analysis. 498 SmallVector<SDValue, 8> PendingLoads; 499 500 /// PendingExports - CopyToReg nodes that copy values to virtual registers 501 /// for export to other blocks need to be emitted before any terminator 502 /// instruction, but they have no other ordering requirements. We bunch them 503 /// up and the emit a single tokenfactor for them just before terminator 504 /// instructions. 505 std::vector<SDValue> PendingExports; 506 507 /// Case - A struct to record the Value for a switch case, and the 508 /// case's target basic block. 509 struct Case { 510 Constant* Low; 511 Constant* High; 512 MachineBasicBlock* BB; 513 514 Case() : Low(0), High(0), BB(0) { } 515 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 516 Low(low), High(high), BB(bb) { } 517 uint64_t size() const { 518 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 519 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 520 return (rHigh - rLow + 1ULL); 521 } 522 }; 523 524 struct CaseBits { 525 uint64_t Mask; 526 MachineBasicBlock* BB; 527 unsigned Bits; 528 529 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 530 Mask(mask), BB(bb), Bits(bits) { } 531 }; 532 533 typedef std::vector<Case> CaseVector; 534 typedef std::vector<CaseBits> CaseBitsVector; 535 typedef CaseVector::iterator CaseItr; 536 typedef std::pair<CaseItr, CaseItr> CaseRange; 537 538 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 539 /// of conditional branches. 540 struct CaseRec { 541 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 542 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 543 544 /// CaseBB - The MBB in which to emit the compare and branch 545 MachineBasicBlock *CaseBB; 546 /// LT, GE - If nonzero, we know the current case value must be less-than or 547 /// greater-than-or-equal-to these Constants. 548 Constant *LT; 549 Constant *GE; 550 /// Range - A pair of iterators representing the range of case values to be 551 /// processed at this point in the binary search tree. 552 CaseRange Range; 553 }; 554 555 typedef std::vector<CaseRec> CaseRecVector; 556 557 /// The comparison function for sorting the switch case values in the vector. 558 /// WARNING: Case ranges should be disjoint! 559 struct CaseCmp { 560 bool operator () (const Case& C1, const Case& C2) { 561 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 562 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 563 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 564 return CI1->getValue().slt(CI2->getValue()); 565 } 566 }; 567 568 struct CaseBitsCmp { 569 bool operator () (const CaseBits& C1, const CaseBits& C2) { 570 return C1.Bits > C2.Bits; 571 } 572 }; 573 574 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 575 576public: 577 // TLI - This is information that describes the available target features we 578 // need for lowering. This indicates when operations are unavailable, 579 // implemented with a libcall, etc. 580 TargetLowering &TLI; 581 SelectionDAG &DAG; 582 const TargetData *TD; 583 AliasAnalysis &AA; 584 585 /// SwitchCases - Vector of CaseBlock structures used to communicate 586 /// SwitchInst code generation information. 587 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 588 /// JTCases - Vector of JumpTable structures used to communicate 589 /// SwitchInst code generation information. 590 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 591 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 592 593 /// FuncInfo - Information about the function as a whole. 594 /// 595 FunctionLoweringInfo &FuncInfo; 596 597 /// GCI - Garbage collection metadata for the function. 598 CollectorMetadata *GCI; 599 600 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 601 AliasAnalysis &aa, 602 FunctionLoweringInfo &funcinfo, 603 CollectorMetadata *gci) 604 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 605 FuncInfo(funcinfo), GCI(gci) { 606 } 607 608 /// getRoot - Return the current virtual root of the Selection DAG, 609 /// flushing any PendingLoad items. This must be done before emitting 610 /// a store or any other node that may need to be ordered after any 611 /// prior load instructions. 612 /// 613 SDValue getRoot() { 614 if (PendingLoads.empty()) 615 return DAG.getRoot(); 616 617 if (PendingLoads.size() == 1) { 618 SDValue Root = PendingLoads[0]; 619 DAG.setRoot(Root); 620 PendingLoads.clear(); 621 return Root; 622 } 623 624 // Otherwise, we have to make a token factor node. 625 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 626 &PendingLoads[0], PendingLoads.size()); 627 PendingLoads.clear(); 628 DAG.setRoot(Root); 629 return Root; 630 } 631 632 /// getControlRoot - Similar to getRoot, but instead of flushing all the 633 /// PendingLoad items, flush all the PendingExports items. It is necessary 634 /// to do this before emitting a terminator instruction. 635 /// 636 SDValue getControlRoot() { 637 SDValue Root = DAG.getRoot(); 638 639 if (PendingExports.empty()) 640 return Root; 641 642 // Turn all of the CopyToReg chains into one factored node. 643 if (Root.getOpcode() != ISD::EntryToken) { 644 unsigned i = 0, e = PendingExports.size(); 645 for (; i != e; ++i) { 646 assert(PendingExports[i].Val->getNumOperands() > 1); 647 if (PendingExports[i].Val->getOperand(0) == Root) 648 break; // Don't add the root if we already indirectly depend on it. 649 } 650 651 if (i == e) 652 PendingExports.push_back(Root); 653 } 654 655 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 656 &PendingExports[0], 657 PendingExports.size()); 658 PendingExports.clear(); 659 DAG.setRoot(Root); 660 return Root; 661 } 662 663 void CopyValueToVirtualRegister(Value *V, unsigned Reg); 664 665 void visit(Instruction &I) { visit(I.getOpcode(), I); } 666 667 void visit(unsigned Opcode, User &I) { 668 // Note: this doesn't use InstVisitor, because it has to work with 669 // ConstantExpr's in addition to instructions. 670 switch (Opcode) { 671 default: assert(0 && "Unknown instruction type encountered!"); 672 abort(); 673 // Build the switch statement using the Instruction.def file. 674#define HANDLE_INST(NUM, OPCODE, CLASS) \ 675 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 676#include "llvm/Instruction.def" 677 } 678 } 679 680 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 681 682 SDValue getValue(const Value *V); 683 684 void setValue(const Value *V, SDValue NewN) { 685 SDValue &N = NodeMap[V]; 686 assert(N.Val == 0 && "Already set a value for this node!"); 687 N = NewN; 688 } 689 690 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 691 std::set<unsigned> &OutputRegs, 692 std::set<unsigned> &InputRegs); 693 694 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 696 unsigned Opc); 697 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 698 void ExportFromCurrentBlock(Value *V); 699 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall, 700 MachineBasicBlock *LandingPad = NULL); 701 702 // Terminator instructions. 703 void visitRet(ReturnInst &I); 704 void visitBr(BranchInst &I); 705 void visitSwitch(SwitchInst &I); 706 void visitUnreachable(UnreachableInst &I) { /* noop */ } 707 708 // Helpers for visitSwitch 709 bool handleSmallSwitchRange(CaseRec& CR, 710 CaseRecVector& WorkList, 711 Value* SV, 712 MachineBasicBlock* Default); 713 bool handleJTSwitchCase(CaseRec& CR, 714 CaseRecVector& WorkList, 715 Value* SV, 716 MachineBasicBlock* Default); 717 bool handleBTSplitSwitchCase(CaseRec& CR, 718 CaseRecVector& WorkList, 719 Value* SV, 720 MachineBasicBlock* Default); 721 bool handleBitTestsSwitchCase(CaseRec& CR, 722 CaseRecVector& WorkList, 723 Value* SV, 724 MachineBasicBlock* Default); 725 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 726 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 727 void visitBitTestCase(MachineBasicBlock* NextMBB, 728 unsigned Reg, 729 SelectionDAGISel::BitTestCase &B); 730 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 731 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 732 SelectionDAGISel::JumpTableHeader &JTH); 733 734 // These all get lowered before this pass. 735 void visitInvoke(InvokeInst &I); 736 void visitUnwind(UnwindInst &I); 737 738 void visitBinary(User &I, unsigned OpCode); 739 void visitShift(User &I, unsigned Opcode); 740 void visitAdd(User &I) { 741 if (I.getType()->isFPOrFPVector()) 742 visitBinary(I, ISD::FADD); 743 else 744 visitBinary(I, ISD::ADD); 745 } 746 void visitSub(User &I); 747 void visitMul(User &I) { 748 if (I.getType()->isFPOrFPVector()) 749 visitBinary(I, ISD::FMUL); 750 else 751 visitBinary(I, ISD::MUL); 752 } 753 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 754 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 755 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 756 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 757 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 758 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 759 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 760 void visitOr (User &I) { visitBinary(I, ISD::OR); } 761 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 762 void visitShl (User &I) { visitShift(I, ISD::SHL); } 763 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 764 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 765 void visitICmp(User &I); 766 void visitFCmp(User &I); 767 void visitVICmp(User &I); 768 void visitVFCmp(User &I); 769 // Visit the conversion instructions 770 void visitTrunc(User &I); 771 void visitZExt(User &I); 772 void visitSExt(User &I); 773 void visitFPTrunc(User &I); 774 void visitFPExt(User &I); 775 void visitFPToUI(User &I); 776 void visitFPToSI(User &I); 777 void visitUIToFP(User &I); 778 void visitSIToFP(User &I); 779 void visitPtrToInt(User &I); 780 void visitIntToPtr(User &I); 781 void visitBitCast(User &I); 782 783 void visitExtractElement(User &I); 784 void visitInsertElement(User &I); 785 void visitShuffleVector(User &I); 786 787 void visitExtractValue(ExtractValueInst &I); 788 void visitInsertValue(InsertValueInst &I); 789 790 void visitGetElementPtr(User &I); 791 void visitSelect(User &I); 792 793 void visitMalloc(MallocInst &I); 794 void visitFree(FreeInst &I); 795 void visitAlloca(AllocaInst &I); 796 void visitLoad(LoadInst &I); 797 void visitStore(StoreInst &I); 798 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 799 void visitCall(CallInst &I); 800 void visitInlineAsm(CallSite CS); 801 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 802 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 803 804 void visitVAStart(CallInst &I); 805 void visitVAArg(VAArgInst &I); 806 void visitVAEnd(CallInst &I); 807 void visitVACopy(CallInst &I); 808 809 void visitUserOp1(Instruction &I) { 810 assert(0 && "UserOp1 should not exist at instruction selection time!"); 811 abort(); 812 } 813 void visitUserOp2(Instruction &I) { 814 assert(0 && "UserOp2 should not exist at instruction selection time!"); 815 abort(); 816 } 817 818private: 819 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); 820 821}; 822} // end namespace llvm 823 824 825/// getCopyFromParts - Create a value that contains the specified legal parts 826/// combined into the value they represent. If the parts combine to a type 827/// larger then ValueVT then AssertOp can be used to specify whether the extra 828/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 829/// (ISD::AssertSext). 830static SDValue getCopyFromParts(SelectionDAG &DAG, 831 const SDValue *Parts, 832 unsigned NumParts, 833 MVT PartVT, 834 MVT ValueVT, 835 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 836 assert(NumParts > 0 && "No parts to assemble!"); 837 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 838 SDValue Val = Parts[0]; 839 840 if (NumParts > 1) { 841 // Assemble the value from multiple parts. 842 if (!ValueVT.isVector()) { 843 unsigned PartBits = PartVT.getSizeInBits(); 844 unsigned ValueBits = ValueVT.getSizeInBits(); 845 846 // Assemble the power of 2 part. 847 unsigned RoundParts = NumParts & (NumParts - 1) ? 848 1 << Log2_32(NumParts) : NumParts; 849 unsigned RoundBits = PartBits * RoundParts; 850 MVT RoundVT = RoundBits == ValueBits ? 851 ValueVT : MVT::getIntegerVT(RoundBits); 852 SDValue Lo, Hi; 853 854 if (RoundParts > 2) { 855 MVT HalfVT = MVT::getIntegerVT(RoundBits/2); 856 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 857 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 858 PartVT, HalfVT); 859 } else { 860 Lo = Parts[0]; 861 Hi = Parts[1]; 862 } 863 if (TLI.isBigEndian()) 864 std::swap(Lo, Hi); 865 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 866 867 if (RoundParts < NumParts) { 868 // Assemble the trailing non-power-of-2 part. 869 unsigned OddParts = NumParts - RoundParts; 870 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); 871 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 872 873 // Combine the round and odd parts. 874 Lo = Val; 875 if (TLI.isBigEndian()) 876 std::swap(Lo, Hi); 877 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); 878 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 879 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 880 DAG.getConstant(Lo.getValueType().getSizeInBits(), 881 TLI.getShiftAmountTy())); 882 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 883 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 884 } 885 } else { 886 // Handle a multi-element vector. 887 MVT IntermediateVT, RegisterVT; 888 unsigned NumIntermediates; 889 unsigned NumRegs = 890 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 891 RegisterVT); 892 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 893 NumParts = NumRegs; // Silence a compiler warning. 894 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 895 assert(RegisterVT == Parts[0].getValueType() && 896 "Part type doesn't match part!"); 897 898 // Assemble the parts into intermediate operands. 899 SmallVector<SDValue, 8> Ops(NumIntermediates); 900 if (NumIntermediates == NumParts) { 901 // If the register was not expanded, truncate or copy the value, 902 // as appropriate. 903 for (unsigned i = 0; i != NumParts; ++i) 904 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 905 PartVT, IntermediateVT); 906 } else if (NumParts > 0) { 907 // If the intermediate type was expanded, build the intermediate operands 908 // from the parts. 909 assert(NumParts % NumIntermediates == 0 && 910 "Must expand into a divisible number of parts!"); 911 unsigned Factor = NumParts / NumIntermediates; 912 for (unsigned i = 0; i != NumIntermediates; ++i) 913 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 914 PartVT, IntermediateVT); 915 } 916 917 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 918 // operands. 919 Val = DAG.getNode(IntermediateVT.isVector() ? 920 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 921 ValueVT, &Ops[0], NumIntermediates); 922 } 923 } 924 925 // There is now one part, held in Val. Correct it to match ValueVT. 926 PartVT = Val.getValueType(); 927 928 if (PartVT == ValueVT) 929 return Val; 930 931 if (PartVT.isVector()) { 932 assert(ValueVT.isVector() && "Unknown vector conversion!"); 933 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 934 } 935 936 if (ValueVT.isVector()) { 937 assert(ValueVT.getVectorElementType() == PartVT && 938 ValueVT.getVectorNumElements() == 1 && 939 "Only trivial scalar-to-vector conversions should get here!"); 940 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 941 } 942 943 if (PartVT.isInteger() && 944 ValueVT.isInteger()) { 945 if (ValueVT.bitsLT(PartVT)) { 946 // For a truncate, see if we have any information to 947 // indicate whether the truncated bits will always be 948 // zero or sign-extension. 949 if (AssertOp != ISD::DELETED_NODE) 950 Val = DAG.getNode(AssertOp, PartVT, Val, 951 DAG.getValueType(ValueVT)); 952 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 953 } else { 954 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 955 } 956 } 957 958 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 959 if (ValueVT.bitsLT(Val.getValueType())) 960 // FP_ROUND's are always exact here. 961 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 962 DAG.getIntPtrConstant(1)); 963 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); 964 } 965 966 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 967 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 968 969 assert(0 && "Unknown mismatch!"); 970 return SDValue(); 971} 972 973/// getCopyToParts - Create a series of nodes that contain the specified value 974/// split into legal parts. If the parts contain more bits than Val, then, for 975/// integers, ExtendKind can be used to specify how to generate the extra bits. 976static void getCopyToParts(SelectionDAG &DAG, 977 SDValue Val, 978 SDValue *Parts, 979 unsigned NumParts, 980 MVT PartVT, 981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 982 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 983 MVT PtrVT = TLI.getPointerTy(); 984 MVT ValueVT = Val.getValueType(); 985 unsigned PartBits = PartVT.getSizeInBits(); 986 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 987 988 if (!NumParts) 989 return; 990 991 if (!ValueVT.isVector()) { 992 if (PartVT == ValueVT) { 993 assert(NumParts == 1 && "No-op copy with multiple parts!"); 994 Parts[0] = Val; 995 return; 996 } 997 998 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 999 // If the parts cover more bits than the value has, promote the value. 1000 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 1001 assert(NumParts == 1 && "Do not know what to promote to!"); 1002 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 1003 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 1004 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1005 Val = DAG.getNode(ExtendKind, ValueVT, Val); 1006 } else { 1007 assert(0 && "Unknown mismatch!"); 1008 } 1009 } else if (PartBits == ValueVT.getSizeInBits()) { 1010 // Different types of the same size. 1011 assert(NumParts == 1 && PartVT != ValueVT); 1012 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1013 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 1014 // If the parts cover less bits than value has, truncate the value. 1015 if (PartVT.isInteger() && ValueVT.isInteger()) { 1016 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1017 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1018 } else { 1019 assert(0 && "Unknown mismatch!"); 1020 } 1021 } 1022 1023 // The value may have changed - recompute ValueVT. 1024 ValueVT = Val.getValueType(); 1025 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 1026 "Failed to tile the value with PartVT!"); 1027 1028 if (NumParts == 1) { 1029 assert(PartVT == ValueVT && "Type conversion failed!"); 1030 Parts[0] = Val; 1031 return; 1032 } 1033 1034 // Expand the value into multiple parts. 1035 if (NumParts & (NumParts - 1)) { 1036 // The number of parts is not a power of 2. Split off and copy the tail. 1037 assert(PartVT.isInteger() && ValueVT.isInteger() && 1038 "Do not know what to expand to!"); 1039 unsigned RoundParts = 1 << Log2_32(NumParts); 1040 unsigned RoundBits = RoundParts * PartBits; 1041 unsigned OddParts = NumParts - RoundParts; 1042 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 1043 DAG.getConstant(RoundBits, 1044 TLI.getShiftAmountTy())); 1045 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 1046 if (TLI.isBigEndian()) 1047 // The odd parts were reversed by getCopyToParts - unreverse them. 1048 std::reverse(Parts + RoundParts, Parts + NumParts); 1049 NumParts = RoundParts; 1050 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1051 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1052 } 1053 1054 // The number of parts is a power of 2. Repeatedly bisect the value using 1055 // EXTRACT_ELEMENT. 1056 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, 1057 MVT::getIntegerVT(ValueVT.getSizeInBits()), 1058 Val); 1059 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 1060 for (unsigned i = 0; i < NumParts; i += StepSize) { 1061 unsigned ThisBits = StepSize * PartBits / 2; 1062 MVT ThisVT = MVT::getIntegerVT (ThisBits); 1063 SDValue &Part0 = Parts[i]; 1064 SDValue &Part1 = Parts[i+StepSize/2]; 1065 1066 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1067 DAG.getConstant(1, PtrVT)); 1068 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1069 DAG.getConstant(0, PtrVT)); 1070 1071 if (ThisBits == PartBits && ThisVT != PartVT) { 1072 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0); 1073 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1); 1074 } 1075 } 1076 } 1077 1078 if (TLI.isBigEndian()) 1079 std::reverse(Parts, Parts + NumParts); 1080 1081 return; 1082 } 1083 1084 // Vector ValueVT. 1085 if (NumParts == 1) { 1086 if (PartVT != ValueVT) { 1087 if (PartVT.isVector()) { 1088 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1089 } else { 1090 assert(ValueVT.getVectorElementType() == PartVT && 1091 ValueVT.getVectorNumElements() == 1 && 1092 "Only trivial vector-to-scalar conversions should get here!"); 1093 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 1094 DAG.getConstant(0, PtrVT)); 1095 } 1096 } 1097 1098 Parts[0] = Val; 1099 return; 1100 } 1101 1102 // Handle a multi-element vector. 1103 MVT IntermediateVT, RegisterVT; 1104 unsigned NumIntermediates; 1105 unsigned NumRegs = 1106 DAG.getTargetLoweringInfo() 1107 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 1108 RegisterVT); 1109 unsigned NumElements = ValueVT.getVectorNumElements(); 1110 1111 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 1112 NumParts = NumRegs; // Silence a compiler warning. 1113 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 1114 1115 // Split the vector into intermediate operands. 1116 SmallVector<SDValue, 8> Ops(NumIntermediates); 1117 for (unsigned i = 0; i != NumIntermediates; ++i) 1118 if (IntermediateVT.isVector()) 1119 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 1120 IntermediateVT, Val, 1121 DAG.getConstant(i * (NumElements / NumIntermediates), 1122 PtrVT)); 1123 else 1124 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 1125 IntermediateVT, Val, 1126 DAG.getConstant(i, PtrVT)); 1127 1128 // Split the intermediate operands into legal parts. 1129 if (NumParts == NumIntermediates) { 1130 // If the register was not expanded, promote or copy the value, 1131 // as appropriate. 1132 for (unsigned i = 0; i != NumParts; ++i) 1133 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 1134 } else if (NumParts > 0) { 1135 // If the intermediate type was expanded, split each the value into 1136 // legal parts. 1137 assert(NumParts % NumIntermediates == 0 && 1138 "Must expand into a divisible number of parts!"); 1139 unsigned Factor = NumParts / NumIntermediates; 1140 for (unsigned i = 0; i != NumIntermediates; ++i) 1141 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 1142 } 1143} 1144 1145 1146SDValue SelectionDAGLowering::getValue(const Value *V) { 1147 SDValue &N = NodeMap[V]; 1148 if (N.Val) return N; 1149 1150 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 1151 MVT VT = TLI.getValueType(V->getType(), true); 1152 1153 if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1154 return N = DAG.getConstant(CI->getValue(), VT); 1155 1156 if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1157 return N = DAG.getGlobalAddress(GV, VT); 1158 1159 if (isa<ConstantPointerNull>(C)) 1160 return N = DAG.getConstant(0, TLI.getPointerTy()); 1161 1162 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1163 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 1164 1165 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) && 1166 !V->getType()->isAggregateType()) 1167 return N = DAG.getNode(ISD::UNDEF, VT); 1168 1169 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1170 visit(CE->getOpcode(), *CE); 1171 SDValue N1 = NodeMap[V]; 1172 assert(N1.Val && "visit didn't populate the ValueMap!"); 1173 return N1; 1174 } 1175 1176 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1177 SmallVector<SDValue, 4> Constants; 1178 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1179 OI != OE; ++OI) { 1180 SDNode *Val = getValue(*OI).Val; 1181 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1182 Constants.push_back(SDValue(Val, i)); 1183 } 1184 return DAG.getMergeValues(&Constants[0], Constants.size()); 1185 } 1186 1187 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) { 1188 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1189 "Unknown array constant!"); 1190 unsigned NumElts = ATy->getNumElements(); 1191 if (NumElts == 0) 1192 return SDValue(); // empty array 1193 MVT EltVT = TLI.getValueType(ATy->getElementType()); 1194 SmallVector<SDValue, 4> Constants(NumElts); 1195 for (unsigned i = 0, e = NumElts; i != e; ++i) { 1196 if (isa<UndefValue>(C)) 1197 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); 1198 else if (EltVT.isFloatingPoint()) 1199 Constants[i] = DAG.getConstantFP(0, EltVT); 1200 else 1201 Constants[i] = DAG.getConstant(0, EltVT); 1202 } 1203 return DAG.getMergeValues(&Constants[0], Constants.size()); 1204 } 1205 1206 if (const StructType *STy = dyn_cast<StructType>(C->getType())) { 1207 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1208 "Unknown struct constant!"); 1209 unsigned NumElts = STy->getNumElements(); 1210 if (NumElts == 0) 1211 return SDValue(); // empty struct 1212 SmallVector<SDValue, 4> Constants(NumElts); 1213 for (unsigned i = 0, e = NumElts; i != e; ++i) { 1214 MVT EltVT = TLI.getValueType(STy->getElementType(i)); 1215 if (isa<UndefValue>(C)) 1216 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); 1217 else if (EltVT.isFloatingPoint()) 1218 Constants[i] = DAG.getConstantFP(0, EltVT); 1219 else 1220 Constants[i] = DAG.getConstant(0, EltVT); 1221 } 1222 return DAG.getMergeValues(&Constants[0], Constants.size()); 1223 } 1224 1225 const VectorType *VecTy = cast<VectorType>(V->getType()); 1226 unsigned NumElements = VecTy->getNumElements(); 1227 1228 // Now that we know the number and type of the elements, get that number of 1229 // elements into the Ops array based on what kind of constant it is. 1230 SmallVector<SDValue, 16> Ops; 1231 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1232 for (unsigned i = 0; i != NumElements; ++i) 1233 Ops.push_back(getValue(CP->getOperand(i))); 1234 } else { 1235 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1236 "Unknown vector constant!"); 1237 MVT EltVT = TLI.getValueType(VecTy->getElementType()); 1238 1239 SDValue Op; 1240 if (isa<UndefValue>(C)) 1241 Op = DAG.getNode(ISD::UNDEF, EltVT); 1242 else if (EltVT.isFloatingPoint()) 1243 Op = DAG.getConstantFP(0, EltVT); 1244 else 1245 Op = DAG.getConstant(0, EltVT); 1246 Ops.assign(NumElements, Op); 1247 } 1248 1249 // Create a BUILD_VECTOR node. 1250 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1251 } 1252 1253 // If this is a static alloca, generate it as the frameindex instead of 1254 // computation. 1255 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1256 std::map<const AllocaInst*, int>::iterator SI = 1257 FuncInfo.StaticAllocaMap.find(AI); 1258 if (SI != FuncInfo.StaticAllocaMap.end()) 1259 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1260 } 1261 1262 unsigned InReg = FuncInfo.ValueMap[V]; 1263 assert(InReg && "Value not in map!"); 1264 1265 RegsForValue RFV(TLI, InReg, V->getType()); 1266 SDValue Chain = DAG.getEntryNode(); 1267 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1268} 1269 1270 1271void SelectionDAGLowering::visitRet(ReturnInst &I) { 1272 if (I.getNumOperands() == 0) { 1273 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot())); 1274 return; 1275 } 1276 1277 SmallVector<SDValue, 8> NewValues; 1278 NewValues.push_back(getControlRoot()); 1279 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1280 SDValue RetOp = getValue(I.getOperand(i)); 1281 1282 SmallVector<MVT, 4> ValueVTs; 1283 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs); 1284 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) { 1285 MVT VT = ValueVTs[j]; 1286 1287 // FIXME: C calling convention requires the return type to be promoted to 1288 // at least 32-bit. But this is not necessary for non-C calling conventions. 1289 if (VT.isInteger()) { 1290 MVT MinVT = TLI.getRegisterType(MVT::i32); 1291 if (VT.bitsLT(MinVT)) 1292 VT = MinVT; 1293 } 1294 1295 unsigned NumParts = TLI.getNumRegisters(VT); 1296 MVT PartVT = TLI.getRegisterType(VT); 1297 SmallVector<SDValue, 4> Parts(NumParts); 1298 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1299 1300 const Function *F = I.getParent()->getParent(); 1301 if (F->paramHasAttr(0, ParamAttr::SExt)) 1302 ExtendKind = ISD::SIGN_EXTEND; 1303 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1304 ExtendKind = ISD::ZERO_EXTEND; 1305 1306 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j), 1307 &Parts[0], NumParts, PartVT, ExtendKind); 1308 1309 for (unsigned i = 0; i < NumParts; ++i) { 1310 NewValues.push_back(Parts[i]); 1311 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy())); 1312 } 1313 } 1314 } 1315 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1316 &NewValues[0], NewValues.size())); 1317} 1318 1319/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1320/// the current basic block, add it to ValueMap now so that we'll get a 1321/// CopyTo/FromReg. 1322void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1323 // No need to export constants. 1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1325 1326 // Already exported? 1327 if (FuncInfo.isExportedInst(V)) return; 1328 1329 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1330 CopyValueToVirtualRegister(V, Reg); 1331} 1332 1333bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1334 const BasicBlock *FromBB) { 1335 // The operands of the setcc have to be in this block. We don't know 1336 // how to export them from some other block. 1337 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1338 // Can export from current BB. 1339 if (VI->getParent() == FromBB) 1340 return true; 1341 1342 // Is already exported, noop. 1343 return FuncInfo.isExportedInst(V); 1344 } 1345 1346 // If this is an argument, we can export it if the BB is the entry block or 1347 // if it is already exported. 1348 if (isa<Argument>(V)) { 1349 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1350 return true; 1351 1352 // Otherwise, can only export this if it is already exported. 1353 return FuncInfo.isExportedInst(V); 1354 } 1355 1356 // Otherwise, constants can always be exported. 1357 return true; 1358} 1359 1360static bool InBlock(const Value *V, const BasicBlock *BB) { 1361 if (const Instruction *I = dyn_cast<Instruction>(V)) 1362 return I->getParent() == BB; 1363 return true; 1364} 1365 1366/// FindMergedConditions - If Cond is an expression like 1367void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1368 MachineBasicBlock *TBB, 1369 MachineBasicBlock *FBB, 1370 MachineBasicBlock *CurBB, 1371 unsigned Opc) { 1372 // If this node is not part of the or/and tree, emit it as a branch. 1373 Instruction *BOp = dyn_cast<Instruction>(Cond); 1374 1375 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1376 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1377 BOp->getParent() != CurBB->getBasicBlock() || 1378 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1379 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1380 const BasicBlock *BB = CurBB->getBasicBlock(); 1381 1382 // If the leaf of the tree is a comparison, merge the condition into 1383 // the caseblock. 1384 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1385 // The operands of the cmp have to be in this block. We don't know 1386 // how to export them from some other block. If this is the first block 1387 // of the sequence, no exporting is needed. 1388 (CurBB == CurMBB || 1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1391 BOp = cast<Instruction>(Cond); 1392 ISD::CondCode Condition; 1393 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1394 switch (IC->getPredicate()) { 1395 default: assert(0 && "Unknown icmp predicate opcode!"); 1396 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1397 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1398 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1399 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1400 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1401 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1402 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1403 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1404 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1405 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1406 } 1407 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1408 ISD::CondCode FPC, FOC; 1409 switch (FC->getPredicate()) { 1410 default: assert(0 && "Unknown fcmp predicate opcode!"); 1411 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1412 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1413 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1414 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1415 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1416 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1417 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1418 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 1419 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 1420 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1421 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1422 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1423 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1424 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1425 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1426 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1427 } 1428 if (FiniteOnlyFPMath()) 1429 Condition = FOC; 1430 else 1431 Condition = FPC; 1432 } else { 1433 Condition = ISD::SETEQ; // silence warning. 1434 assert(0 && "Unknown compare instruction"); 1435 } 1436 1437 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1438 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1439 SwitchCases.push_back(CB); 1440 return; 1441 } 1442 1443 // Create a CaseBlock record representing this branch. 1444 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1445 NULL, TBB, FBB, CurBB); 1446 SwitchCases.push_back(CB); 1447 return; 1448 } 1449 1450 1451 // Create TmpBB after CurBB. 1452 MachineFunction::iterator BBI = CurBB; 1453 MachineFunction &MF = DAG.getMachineFunction(); 1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1455 CurBB->getParent()->insert(++BBI, TmpBB); 1456 1457 if (Opc == Instruction::Or) { 1458 // Codegen X | Y as: 1459 // jmp_if_X TBB 1460 // jmp TmpBB 1461 // TmpBB: 1462 // jmp_if_Y TBB 1463 // jmp FBB 1464 // 1465 1466 // Emit the LHS condition. 1467 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1468 1469 // Emit the RHS condition into TmpBB. 1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1471 } else { 1472 assert(Opc == Instruction::And && "Unknown merge op!"); 1473 // Codegen X & Y as: 1474 // jmp_if_X TmpBB 1475 // jmp FBB 1476 // TmpBB: 1477 // jmp_if_Y TBB 1478 // jmp FBB 1479 // 1480 // This requires creation of TmpBB after CurBB. 1481 1482 // Emit the LHS condition. 1483 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1484 1485 // Emit the RHS condition into TmpBB. 1486 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1487 } 1488} 1489 1490/// If the set of cases should be emitted as a series of branches, return true. 1491/// If we should emit this as a bunch of and/or'd together conditions, return 1492/// false. 1493static bool 1494ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1495 if (Cases.size() != 2) return true; 1496 1497 // If this is two comparisons of the same values or'd or and'd together, they 1498 // will get folded into a single comparison, so don't emit two blocks. 1499 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1500 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1501 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1502 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1503 return false; 1504 } 1505 1506 return true; 1507} 1508 1509void SelectionDAGLowering::visitBr(BranchInst &I) { 1510 // Update machine-CFG edges. 1511 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1512 1513 // Figure out which block is immediately after the current one. 1514 MachineBasicBlock *NextBlock = 0; 1515 MachineFunction::iterator BBI = CurMBB; 1516 if (++BBI != CurMBB->getParent()->end()) 1517 NextBlock = BBI; 1518 1519 if (I.isUnconditional()) { 1520 // Update machine-CFG edges. 1521 CurMBB->addSuccessor(Succ0MBB); 1522 1523 // If this is not a fall-through branch, emit the branch. 1524 if (Succ0MBB != NextBlock) 1525 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1526 DAG.getBasicBlock(Succ0MBB))); 1527 return; 1528 } 1529 1530 // If this condition is one of the special cases we handle, do special stuff 1531 // now. 1532 Value *CondVal = I.getCondition(); 1533 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1534 1535 // If this is a series of conditions that are or'd or and'd together, emit 1536 // this as a sequence of branches instead of setcc's with and/or operations. 1537 // For example, instead of something like: 1538 // cmp A, B 1539 // C = seteq 1540 // cmp D, E 1541 // F = setle 1542 // or C, F 1543 // jnz foo 1544 // Emit: 1545 // cmp A, B 1546 // je foo 1547 // cmp D, E 1548 // jle foo 1549 // 1550 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1551 if (BOp->hasOneUse() && 1552 (BOp->getOpcode() == Instruction::And || 1553 BOp->getOpcode() == Instruction::Or)) { 1554 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1555 // If the compares in later blocks need to use values not currently 1556 // exported from this block, export them now. This block should always 1557 // be the first entry. 1558 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1559 1560 // Allow some cases to be rejected. 1561 if (ShouldEmitAsBranches(SwitchCases)) { 1562 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1563 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1564 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1565 } 1566 1567 // Emit the branch for this block. 1568 visitSwitchCase(SwitchCases[0]); 1569 SwitchCases.erase(SwitchCases.begin()); 1570 return; 1571 } 1572 1573 // Okay, we decided not to do this, remove any inserted MBB's and clear 1574 // SwitchCases. 1575 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1576 CurMBB->getParent()->erase(SwitchCases[i].ThisBB); 1577 1578 SwitchCases.clear(); 1579 } 1580 } 1581 1582 // Create a CaseBlock record representing this branch. 1583 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1584 NULL, Succ0MBB, Succ1MBB, CurMBB); 1585 // Use visitSwitchCase to actually insert the fast branch sequence for this 1586 // cond branch. 1587 visitSwitchCase(CB); 1588} 1589 1590/// visitSwitchCase - Emits the necessary code to represent a single node in 1591/// the binary search tree resulting from lowering a switch instruction. 1592void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1593 SDValue Cond; 1594 SDValue CondLHS = getValue(CB.CmpLHS); 1595 1596 // Build the setcc now. 1597 if (CB.CmpMHS == NULL) { 1598 // Fold "(X == true)" to X and "(X == false)" to !X to 1599 // handle common cases produced by branch lowering. 1600 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1601 Cond = CondLHS; 1602 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1603 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1604 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1605 } else 1606 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1607 } else { 1608 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1609 1610 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1611 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1612 1613 SDValue CmpOp = getValue(CB.CmpMHS); 1614 MVT VT = CmpOp.getValueType(); 1615 1616 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1617 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1618 } else { 1619 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1620 Cond = DAG.getSetCC(MVT::i1, SUB, 1621 DAG.getConstant(High-Low, VT), ISD::SETULE); 1622 } 1623 } 1624 1625 // Update successor info 1626 CurMBB->addSuccessor(CB.TrueBB); 1627 CurMBB->addSuccessor(CB.FalseBB); 1628 1629 // Set NextBlock to be the MBB immediately after the current one, if any. 1630 // This is used to avoid emitting unnecessary branches to the next block. 1631 MachineBasicBlock *NextBlock = 0; 1632 MachineFunction::iterator BBI = CurMBB; 1633 if (++BBI != CurMBB->getParent()->end()) 1634 NextBlock = BBI; 1635 1636 // If the lhs block is the next block, invert the condition so that we can 1637 // fall through to the lhs instead of the rhs block. 1638 if (CB.TrueBB == NextBlock) { 1639 std::swap(CB.TrueBB, CB.FalseBB); 1640 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1641 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1642 } 1643 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond, 1644 DAG.getBasicBlock(CB.TrueBB)); 1645 if (CB.FalseBB == NextBlock) 1646 DAG.setRoot(BrCond); 1647 else 1648 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1649 DAG.getBasicBlock(CB.FalseBB))); 1650} 1651 1652/// visitJumpTable - Emit JumpTable node in the current MBB 1653void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1654 // Emit the code for the jump table 1655 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1656 MVT PTy = TLI.getPointerTy(); 1657 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); 1658 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1659 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1660 Table, Index)); 1661 return; 1662} 1663 1664/// visitJumpTableHeader - This function emits necessary code to produce index 1665/// in the JumpTable from switch case. 1666void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1667 SelectionDAGISel::JumpTableHeader &JTH) { 1668 // Subtract the lowest switch case value from the value being switched on 1669 // and conditional branch to default mbb if the result is greater than the 1670 // difference between smallest and largest cases. 1671 SDValue SwitchOp = getValue(JTH.SValue); 1672 MVT VT = SwitchOp.getValueType(); 1673 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1674 DAG.getConstant(JTH.First, VT)); 1675 1676 // The SDNode we just created, which holds the value being switched on 1677 // minus the the smallest case value, needs to be copied to a virtual 1678 // register so it can be used as an index into the jump table in a 1679 // subsequent basic block. This value may be smaller or larger than the 1680 // target's pointer type, and therefore require extension or truncating. 1681 if (VT.bitsGT(TLI.getPointerTy())) 1682 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1683 else 1684 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1685 1686 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1687 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); 1688 JT.Reg = JumpTableReg; 1689 1690 // Emit the range check for the jump table, and branch to the default 1691 // block for the switch statement if the value being switched on exceeds 1692 // the largest case in the switch. 1693 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1694 DAG.getConstant(JTH.Last-JTH.First,VT), 1695 ISD::SETUGT); 1696 1697 // Set NextBlock to be the MBB immediately after the current one, if any. 1698 // This is used to avoid emitting unnecessary branches to the next block. 1699 MachineBasicBlock *NextBlock = 0; 1700 MachineFunction::iterator BBI = CurMBB; 1701 if (++BBI != CurMBB->getParent()->end()) 1702 NextBlock = BBI; 1703 1704 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1705 DAG.getBasicBlock(JT.Default)); 1706 1707 if (JT.MBB == NextBlock) 1708 DAG.setRoot(BrCond); 1709 else 1710 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1711 DAG.getBasicBlock(JT.MBB))); 1712 1713 return; 1714} 1715 1716/// visitBitTestHeader - This function emits necessary code to produce value 1717/// suitable for "bit tests" 1718void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1719 // Subtract the minimum value 1720 SDValue SwitchOp = getValue(B.SValue); 1721 MVT VT = SwitchOp.getValueType(); 1722 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1723 DAG.getConstant(B.First, VT)); 1724 1725 // Check range 1726 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1727 DAG.getConstant(B.Range, VT), 1728 ISD::SETUGT); 1729 1730 SDValue ShiftOp; 1731 if (VT.bitsGT(TLI.getShiftAmountTy())) 1732 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1733 else 1734 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1735 1736 // Make desired shift 1737 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1738 DAG.getConstant(1, TLI.getPointerTy()), 1739 ShiftOp); 1740 1741 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1742 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); 1743 B.Reg = SwitchReg; 1744 1745 // Set NextBlock to be the MBB immediately after the current one, if any. 1746 // This is used to avoid emitting unnecessary branches to the next block. 1747 MachineBasicBlock *NextBlock = 0; 1748 MachineFunction::iterator BBI = CurMBB; 1749 if (++BBI != CurMBB->getParent()->end()) 1750 NextBlock = BBI; 1751 1752 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1753 1754 CurMBB->addSuccessor(B.Default); 1755 CurMBB->addSuccessor(MBB); 1756 1757 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1758 DAG.getBasicBlock(B.Default)); 1759 1760 if (MBB == NextBlock) 1761 DAG.setRoot(BrRange); 1762 else 1763 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1764 DAG.getBasicBlock(MBB))); 1765 1766 return; 1767} 1768 1769/// visitBitTestCase - this function produces one "bit test" 1770void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1771 unsigned Reg, 1772 SelectionDAGISel::BitTestCase &B) { 1773 // Emit bit tests and jumps 1774 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, 1775 TLI.getPointerTy()); 1776 1777 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, 1778 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1779 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, 1780 DAG.getConstant(0, TLI.getPointerTy()), 1781 ISD::SETNE); 1782 1783 CurMBB->addSuccessor(B.TargetBB); 1784 CurMBB->addSuccessor(NextMBB); 1785 1786 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), 1787 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1788 1789 // Set NextBlock to be the MBB immediately after the current one, if any. 1790 // This is used to avoid emitting unnecessary branches to the next block. 1791 MachineBasicBlock *NextBlock = 0; 1792 MachineFunction::iterator BBI = CurMBB; 1793 if (++BBI != CurMBB->getParent()->end()) 1794 NextBlock = BBI; 1795 1796 if (NextMBB == NextBlock) 1797 DAG.setRoot(BrAnd); 1798 else 1799 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1800 DAG.getBasicBlock(NextMBB))); 1801 1802 return; 1803} 1804 1805void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1806 // Retrieve successors. 1807 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1808 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1809 1810 if (isa<InlineAsm>(I.getCalledValue())) 1811 visitInlineAsm(&I); 1812 else 1813 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1814 1815 // If the value of the invoke is used outside of its defining block, make it 1816 // available as a virtual register. 1817 if (!I.use_empty()) { 1818 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1819 if (VMI != FuncInfo.ValueMap.end()) 1820 CopyValueToVirtualRegister(&I, VMI->second); 1821 } 1822 1823 // Update successor info 1824 CurMBB->addSuccessor(Return); 1825 CurMBB->addSuccessor(LandingPad); 1826 1827 // Drop into normal successor. 1828 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1829 DAG.getBasicBlock(Return))); 1830} 1831 1832void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1833} 1834 1835/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1836/// small case ranges). 1837bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1838 CaseRecVector& WorkList, 1839 Value* SV, 1840 MachineBasicBlock* Default) { 1841 Case& BackCase = *(CR.Range.second-1); 1842 1843 // Size is the number of Cases represented by this range. 1844 unsigned Size = CR.Range.second - CR.Range.first; 1845 if (Size > 3) 1846 return false; 1847 1848 // Get the MachineFunction which holds the current MBB. This is used when 1849 // inserting any additional MBBs necessary to represent the switch. 1850 MachineFunction *CurMF = CurMBB->getParent(); 1851 1852 // Figure out which block is immediately after the current one. 1853 MachineBasicBlock *NextBlock = 0; 1854 MachineFunction::iterator BBI = CR.CaseBB; 1855 1856 if (++BBI != CurMBB->getParent()->end()) 1857 NextBlock = BBI; 1858 1859 // TODO: If any two of the cases has the same destination, and if one value 1860 // is the same as the other, but has one bit unset that the other has set, 1861 // use bit manipulation to do two compares at once. For example: 1862 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1863 1864 // Rearrange the case blocks so that the last one falls through if possible. 1865 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1866 // The last case block won't fall through into 'NextBlock' if we emit the 1867 // branches in this order. See if rearranging a case value would help. 1868 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1869 if (I->BB == NextBlock) { 1870 std::swap(*I, BackCase); 1871 break; 1872 } 1873 } 1874 } 1875 1876 // Create a CaseBlock record representing a conditional branch to 1877 // the Case's target mbb if the value being switched on SV is equal 1878 // to C. 1879 MachineBasicBlock *CurBlock = CR.CaseBB; 1880 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1881 MachineBasicBlock *FallThrough; 1882 if (I != E-1) { 1883 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1884 CurMF->insert(BBI, FallThrough); 1885 } else { 1886 // If the last case doesn't match, go to the default block. 1887 FallThrough = Default; 1888 } 1889 1890 Value *RHS, *LHS, *MHS; 1891 ISD::CondCode CC; 1892 if (I->High == I->Low) { 1893 // This is just small small case range :) containing exactly 1 case 1894 CC = ISD::SETEQ; 1895 LHS = SV; RHS = I->High; MHS = NULL; 1896 } else { 1897 CC = ISD::SETLE; 1898 LHS = I->Low; MHS = SV; RHS = I->High; 1899 } 1900 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1901 I->BB, FallThrough, CurBlock); 1902 1903 // If emitting the first comparison, just call visitSwitchCase to emit the 1904 // code into the current block. Otherwise, push the CaseBlock onto the 1905 // vector to be later processed by SDISel, and insert the node's MBB 1906 // before the next MBB. 1907 if (CurBlock == CurMBB) 1908 visitSwitchCase(CB); 1909 else 1910 SwitchCases.push_back(CB); 1911 1912 CurBlock = FallThrough; 1913 } 1914 1915 return true; 1916} 1917 1918static inline bool areJTsAllowed(const TargetLowering &TLI) { 1919 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1920 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1921} 1922 1923/// handleJTSwitchCase - Emit jumptable for current switch case range 1924bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1925 CaseRecVector& WorkList, 1926 Value* SV, 1927 MachineBasicBlock* Default) { 1928 Case& FrontCase = *CR.Range.first; 1929 Case& BackCase = *(CR.Range.second-1); 1930 1931 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1932 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1933 1934 uint64_t TSize = 0; 1935 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1936 I!=E; ++I) 1937 TSize += I->size(); 1938 1939 if (!areJTsAllowed(TLI) || TSize <= 3) 1940 return false; 1941 1942 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1943 if (Density < 0.4) 1944 return false; 1945 1946 DOUT << "Lowering jump table\n" 1947 << "First entry: " << First << ". Last entry: " << Last << "\n" 1948 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1949 1950 // Get the MachineFunction which holds the current MBB. This is used when 1951 // inserting any additional MBBs necessary to represent the switch. 1952 MachineFunction *CurMF = CurMBB->getParent(); 1953 1954 // Figure out which block is immediately after the current one. 1955 MachineBasicBlock *NextBlock = 0; 1956 MachineFunction::iterator BBI = CR.CaseBB; 1957 1958 if (++BBI != CurMBB->getParent()->end()) 1959 NextBlock = BBI; 1960 1961 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1962 1963 // Create a new basic block to hold the code for loading the address 1964 // of the jump table, and jumping to it. Update successor information; 1965 // we will either branch to the default case for the switch, or the jump 1966 // table. 1967 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1968 CurMF->insert(BBI, JumpTableBB); 1969 CR.CaseBB->addSuccessor(Default); 1970 CR.CaseBB->addSuccessor(JumpTableBB); 1971 1972 // Build a vector of destination BBs, corresponding to each target 1973 // of the jump table. If the value of the jump table slot corresponds to 1974 // a case statement, push the case's BB onto the vector, otherwise, push 1975 // the default BB. 1976 std::vector<MachineBasicBlock*> DestBBs; 1977 int64_t TEI = First; 1978 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1979 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1980 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1981 1982 if ((Low <= TEI) && (TEI <= High)) { 1983 DestBBs.push_back(I->BB); 1984 if (TEI==High) 1985 ++I; 1986 } else { 1987 DestBBs.push_back(Default); 1988 } 1989 } 1990 1991 // Update successor info. Add one edge to each unique successor. 1992 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1993 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1994 E = DestBBs.end(); I != E; ++I) { 1995 if (!SuccsHandled[(*I)->getNumber()]) { 1996 SuccsHandled[(*I)->getNumber()] = true; 1997 JumpTableBB->addSuccessor(*I); 1998 } 1999 } 2000 2001 // Create a jump table index for this jump table, or return an existing 2002 // one. 2003 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 2004 2005 // Set the jump table information so that we can codegen it as a second 2006 // MachineBasicBlock 2007 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 2008 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 2009 (CR.CaseBB == CurMBB)); 2010 if (CR.CaseBB == CurMBB) 2011 visitJumpTableHeader(JT, JTH); 2012 2013 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 2014 2015 return true; 2016} 2017 2018/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2019/// 2 subtrees. 2020bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 2021 CaseRecVector& WorkList, 2022 Value* SV, 2023 MachineBasicBlock* Default) { 2024 // Get the MachineFunction which holds the current MBB. This is used when 2025 // inserting any additional MBBs necessary to represent the switch. 2026 MachineFunction *CurMF = CurMBB->getParent(); 2027 2028 // Figure out which block is immediately after the current one. 2029 MachineBasicBlock *NextBlock = 0; 2030 MachineFunction::iterator BBI = CR.CaseBB; 2031 2032 if (++BBI != CurMBB->getParent()->end()) 2033 NextBlock = BBI; 2034 2035 Case& FrontCase = *CR.Range.first; 2036 Case& BackCase = *(CR.Range.second-1); 2037 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2038 2039 // Size is the number of Cases represented by this range. 2040 unsigned Size = CR.Range.second - CR.Range.first; 2041 2042 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 2043 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 2044 double FMetric = 0; 2045 CaseItr Pivot = CR.Range.first + Size/2; 2046 2047 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2048 // (heuristically) allow us to emit JumpTable's later. 2049 uint64_t TSize = 0; 2050 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2051 I!=E; ++I) 2052 TSize += I->size(); 2053 2054 uint64_t LSize = FrontCase.size(); 2055 uint64_t RSize = TSize-LSize; 2056 DOUT << "Selecting best pivot: \n" 2057 << "First: " << First << ", Last: " << Last <<"\n" 2058 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 2059 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2060 J!=E; ++I, ++J) { 2061 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 2062 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 2063 assert((RBegin-LEnd>=1) && "Invalid case distance"); 2064 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 2065 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 2066 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 2067 // Should always split in some non-trivial place 2068 DOUT <<"=>Step\n" 2069 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 2070 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 2071 << "Metric: " << Metric << "\n"; 2072 if (FMetric < Metric) { 2073 Pivot = J; 2074 FMetric = Metric; 2075 DOUT << "Current metric set to: " << FMetric << "\n"; 2076 } 2077 2078 LSize += J->size(); 2079 RSize -= J->size(); 2080 } 2081 if (areJTsAllowed(TLI)) { 2082 // If our case is dense we *really* should handle it earlier! 2083 assert((FMetric > 0) && "Should handle dense range earlier!"); 2084 } else { 2085 Pivot = CR.Range.first + Size/2; 2086 } 2087 2088 CaseRange LHSR(CR.Range.first, Pivot); 2089 CaseRange RHSR(Pivot, CR.Range.second); 2090 Constant *C = Pivot->Low; 2091 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2092 2093 // We know that we branch to the LHS if the Value being switched on is 2094 // less than the Pivot value, C. We use this to optimize our binary 2095 // tree a bit, by recognizing that if SV is greater than or equal to the 2096 // LHS's Case Value, and that Case Value is exactly one less than the 2097 // Pivot's Value, then we can branch directly to the LHS's Target, 2098 // rather than creating a leaf node for it. 2099 if ((LHSR.second - LHSR.first) == 1 && 2100 LHSR.first->High == CR.GE && 2101 cast<ConstantInt>(C)->getSExtValue() == 2102 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 2103 TrueBB = LHSR.first->BB; 2104 } else { 2105 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2106 CurMF->insert(BBI, TrueBB); 2107 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2108 } 2109 2110 // Similar to the optimization above, if the Value being switched on is 2111 // known to be less than the Constant CR.LT, and the current Case Value 2112 // is CR.LT - 1, then we can branch directly to the target block for 2113 // the current Case Value, rather than emitting a RHS leaf node for it. 2114 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2115 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 2116 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 2117 FalseBB = RHSR.first->BB; 2118 } else { 2119 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2120 CurMF->insert(BBI, FalseBB); 2121 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2122 } 2123 2124 // Create a CaseBlock record representing a conditional branch to 2125 // the LHS node if the value being switched on SV is less than C. 2126 // Otherwise, branch to LHS. 2127 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 2128 TrueBB, FalseBB, CR.CaseBB); 2129 2130 if (CR.CaseBB == CurMBB) 2131 visitSwitchCase(CB); 2132 else 2133 SwitchCases.push_back(CB); 2134 2135 return true; 2136} 2137 2138/// handleBitTestsSwitchCase - if current case range has few destination and 2139/// range span less, than machine word bitwidth, encode case range into series 2140/// of masks and emit bit tests with these masks. 2141bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 2142 CaseRecVector& WorkList, 2143 Value* SV, 2144 MachineBasicBlock* Default){ 2145 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits(); 2146 2147 Case& FrontCase = *CR.Range.first; 2148 Case& BackCase = *(CR.Range.second-1); 2149 2150 // Get the MachineFunction which holds the current MBB. This is used when 2151 // inserting any additional MBBs necessary to represent the switch. 2152 MachineFunction *CurMF = CurMBB->getParent(); 2153 2154 unsigned numCmps = 0; 2155 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2156 I!=E; ++I) { 2157 // Single case counts one, case range - two. 2158 if (I->Low == I->High) 2159 numCmps +=1; 2160 else 2161 numCmps +=2; 2162 } 2163 2164 // Count unique destinations 2165 SmallSet<MachineBasicBlock*, 4> Dests; 2166 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2167 Dests.insert(I->BB); 2168 if (Dests.size() > 3) 2169 // Don't bother the code below, if there are too much unique destinations 2170 return false; 2171 } 2172 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 2173 << "Total number of comparisons: " << numCmps << "\n"; 2174 2175 // Compute span of values. 2176 Constant* minValue = FrontCase.Low; 2177 Constant* maxValue = BackCase.High; 2178 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 2179 cast<ConstantInt>(minValue)->getSExtValue(); 2180 DOUT << "Compare range: " << range << "\n" 2181 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 2182 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 2183 2184 if (range>=IntPtrBits || 2185 (!(Dests.size() == 1 && numCmps >= 3) && 2186 !(Dests.size() == 2 && numCmps >= 5) && 2187 !(Dests.size() >= 3 && numCmps >= 6))) 2188 return false; 2189 2190 DOUT << "Emitting bit tests\n"; 2191 int64_t lowBound = 0; 2192 2193 // Optimize the case where all the case values fit in a 2194 // word without having to subtract minValue. In this case, 2195 // we can optimize away the subtraction. 2196 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 2197 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 2198 range = cast<ConstantInt>(maxValue)->getSExtValue(); 2199 } else { 2200 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 2201 } 2202 2203 CaseBitsVector CasesBits; 2204 unsigned i, count = 0; 2205 2206 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2207 MachineBasicBlock* Dest = I->BB; 2208 for (i = 0; i < count; ++i) 2209 if (Dest == CasesBits[i].BB) 2210 break; 2211 2212 if (i == count) { 2213 assert((count < 3) && "Too much destinations to test!"); 2214 CasesBits.push_back(CaseBits(0, Dest, 0)); 2215 count++; 2216 } 2217 2218 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 2219 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 2220 2221 for (uint64_t j = lo; j <= hi; j++) { 2222 CasesBits[i].Mask |= 1ULL << j; 2223 CasesBits[i].Bits++; 2224 } 2225 2226 } 2227 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2228 2229 SelectionDAGISel::BitTestInfo BTC; 2230 2231 // Figure out which block is immediately after the current one. 2232 MachineFunction::iterator BBI = CR.CaseBB; 2233 ++BBI; 2234 2235 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2236 2237 DOUT << "Cases:\n"; 2238 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2239 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 2240 << ", BB: " << CasesBits[i].BB << "\n"; 2241 2242 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2243 CurMF->insert(BBI, CaseBB); 2244 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 2245 CaseBB, 2246 CasesBits[i].BB)); 2247 } 2248 2249 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 2250 -1U, (CR.CaseBB == CurMBB), 2251 CR.CaseBB, Default, BTC); 2252 2253 if (CR.CaseBB == CurMBB) 2254 visitBitTestHeader(BTB); 2255 2256 BitTestCases.push_back(BTB); 2257 2258 return true; 2259} 2260 2261 2262/// Clusterify - Transform simple list of Cases into list of CaseRange's 2263unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2264 const SwitchInst& SI) { 2265 unsigned numCmps = 0; 2266 2267 // Start with "simple" cases 2268 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2269 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2270 Cases.push_back(Case(SI.getSuccessorValue(i), 2271 SI.getSuccessorValue(i), 2272 SMBB)); 2273 } 2274 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2275 2276 // Merge case into clusters 2277 if (Cases.size()>=2) 2278 // Must recompute end() each iteration because it may be 2279 // invalidated by erase if we hold on to it 2280 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2281 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2282 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2283 MachineBasicBlock* nextBB = J->BB; 2284 MachineBasicBlock* currentBB = I->BB; 2285 2286 // If the two neighboring cases go to the same destination, merge them 2287 // into a single case. 2288 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2289 I->High = J->High; 2290 J = Cases.erase(J); 2291 } else { 2292 I = J++; 2293 } 2294 } 2295 2296 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2297 if (I->Low != I->High) 2298 // A range counts double, since it requires two compares. 2299 ++numCmps; 2300 } 2301 2302 return numCmps; 2303} 2304 2305void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2306 // Figure out which block is immediately after the current one. 2307 MachineBasicBlock *NextBlock = 0; 2308 MachineFunction::iterator BBI = CurMBB; 2309 2310 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2311 2312 // If there is only the default destination, branch to it if it is not the 2313 // next basic block. Otherwise, just fall through. 2314 if (SI.getNumOperands() == 2) { 2315 // Update machine-CFG edges. 2316 2317 // If this is not a fall-through branch, emit the branch. 2318 CurMBB->addSuccessor(Default); 2319 if (Default != NextBlock) 2320 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 2321 DAG.getBasicBlock(Default))); 2322 2323 return; 2324 } 2325 2326 // If there are any non-default case statements, create a vector of Cases 2327 // representing each one, and sort the vector so that we can efficiently 2328 // create a binary search tree from them. 2329 CaseVector Cases; 2330 unsigned numCmps = Clusterify(Cases, SI); 2331 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2332 << ". Total compares: " << numCmps << "\n"; 2333 2334 // Get the Value to be switched on and default basic blocks, which will be 2335 // inserted into CaseBlock records, representing basic blocks in the binary 2336 // search tree. 2337 Value *SV = SI.getOperand(0); 2338 2339 // Push the initial CaseRec onto the worklist 2340 CaseRecVector WorkList; 2341 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2342 2343 while (!WorkList.empty()) { 2344 // Grab a record representing a case range to process off the worklist 2345 CaseRec CR = WorkList.back(); 2346 WorkList.pop_back(); 2347 2348 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2349 continue; 2350 2351 // If the range has few cases (two or less) emit a series of specific 2352 // tests. 2353 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2354 continue; 2355 2356 // If the switch has more than 5 blocks, and at least 40% dense, and the 2357 // target supports indirect branches, then emit a jump table rather than 2358 // lowering the switch to a binary tree of conditional branches. 2359 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2360 continue; 2361 2362 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2363 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2364 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2365 } 2366} 2367 2368 2369void SelectionDAGLowering::visitSub(User &I) { 2370 // -0.0 - X --> fneg 2371 const Type *Ty = I.getType(); 2372 if (isa<VectorType>(Ty)) { 2373 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2374 const VectorType *DestTy = cast<VectorType>(I.getType()); 2375 const Type *ElTy = DestTy->getElementType(); 2376 if (ElTy->isFloatingPoint()) { 2377 unsigned VL = DestTy->getNumElements(); 2378 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2379 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2380 if (CV == CNZ) { 2381 SDValue Op2 = getValue(I.getOperand(1)); 2382 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2383 return; 2384 } 2385 } 2386 } 2387 } 2388 if (Ty->isFloatingPoint()) { 2389 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2390 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2391 SDValue Op2 = getValue(I.getOperand(1)); 2392 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2393 return; 2394 } 2395 } 2396 2397 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2398} 2399 2400void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2401 SDValue Op1 = getValue(I.getOperand(0)); 2402 SDValue Op2 = getValue(I.getOperand(1)); 2403 2404 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2405} 2406 2407void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2408 SDValue Op1 = getValue(I.getOperand(0)); 2409 SDValue Op2 = getValue(I.getOperand(1)); 2410 2411 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) 2412 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2413 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) 2414 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2415 2416 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2417} 2418 2419void SelectionDAGLowering::visitICmp(User &I) { 2420 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2421 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2422 predicate = IC->getPredicate(); 2423 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2424 predicate = ICmpInst::Predicate(IC->getPredicate()); 2425 SDValue Op1 = getValue(I.getOperand(0)); 2426 SDValue Op2 = getValue(I.getOperand(1)); 2427 ISD::CondCode Opcode; 2428 switch (predicate) { 2429 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2430 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2431 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2432 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2433 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2434 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2435 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2436 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2437 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2438 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2439 default: 2440 assert(!"Invalid ICmp predicate value"); 2441 Opcode = ISD::SETEQ; 2442 break; 2443 } 2444 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2445} 2446 2447void SelectionDAGLowering::visitFCmp(User &I) { 2448 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2449 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2450 predicate = FC->getPredicate(); 2451 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2452 predicate = FCmpInst::Predicate(FC->getPredicate()); 2453 SDValue Op1 = getValue(I.getOperand(0)); 2454 SDValue Op2 = getValue(I.getOperand(1)); 2455 ISD::CondCode Condition, FOC, FPC; 2456 switch (predicate) { 2457 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2458 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2459 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2460 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2461 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2462 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2463 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2464 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2465 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2466 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2467 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2468 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2469 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2470 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2471 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2472 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2473 default: 2474 assert(!"Invalid FCmp predicate value"); 2475 FOC = FPC = ISD::SETFALSE; 2476 break; 2477 } 2478 if (FiniteOnlyFPMath()) 2479 Condition = FOC; 2480 else 2481 Condition = FPC; 2482 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2483} 2484 2485void SelectionDAGLowering::visitVICmp(User &I) { 2486 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2487 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I)) 2488 predicate = IC->getPredicate(); 2489 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2490 predicate = ICmpInst::Predicate(IC->getPredicate()); 2491 SDValue Op1 = getValue(I.getOperand(0)); 2492 SDValue Op2 = getValue(I.getOperand(1)); 2493 ISD::CondCode Opcode; 2494 switch (predicate) { 2495 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2496 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2497 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2498 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2499 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2500 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2501 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2502 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2503 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2504 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2505 default: 2506 assert(!"Invalid ICmp predicate value"); 2507 Opcode = ISD::SETEQ; 2508 break; 2509 } 2510 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); 2511} 2512 2513void SelectionDAGLowering::visitVFCmp(User &I) { 2514 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2515 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I)) 2516 predicate = FC->getPredicate(); 2517 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2518 predicate = FCmpInst::Predicate(FC->getPredicate()); 2519 SDValue Op1 = getValue(I.getOperand(0)); 2520 SDValue Op2 = getValue(I.getOperand(1)); 2521 ISD::CondCode Condition, FOC, FPC; 2522 switch (predicate) { 2523 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2524 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2525 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2526 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2527 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2528 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2529 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2530 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2531 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2532 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2533 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2534 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2535 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2536 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2537 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2538 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2539 default: 2540 assert(!"Invalid VFCmp predicate value"); 2541 FOC = FPC = ISD::SETFALSE; 2542 break; 2543 } 2544 if (FiniteOnlyFPMath()) 2545 Condition = FOC; 2546 else 2547 Condition = FPC; 2548 2549 MVT DestVT = TLI.getValueType(I.getType()); 2550 2551 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); 2552} 2553 2554void SelectionDAGLowering::visitSelect(User &I) { 2555 SDValue Cond = getValue(I.getOperand(0)); 2556 SDValue TrueVal = getValue(I.getOperand(1)); 2557 SDValue FalseVal = getValue(I.getOperand(2)); 2558 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2559 TrueVal, FalseVal)); 2560} 2561 2562 2563void SelectionDAGLowering::visitTrunc(User &I) { 2564 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2565 SDValue N = getValue(I.getOperand(0)); 2566 MVT DestVT = TLI.getValueType(I.getType()); 2567 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2568} 2569 2570void SelectionDAGLowering::visitZExt(User &I) { 2571 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2572 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2573 SDValue N = getValue(I.getOperand(0)); 2574 MVT DestVT = TLI.getValueType(I.getType()); 2575 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2576} 2577 2578void SelectionDAGLowering::visitSExt(User &I) { 2579 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2580 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2581 SDValue N = getValue(I.getOperand(0)); 2582 MVT DestVT = TLI.getValueType(I.getType()); 2583 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2584} 2585 2586void SelectionDAGLowering::visitFPTrunc(User &I) { 2587 // FPTrunc is never a no-op cast, no need to check 2588 SDValue N = getValue(I.getOperand(0)); 2589 MVT DestVT = TLI.getValueType(I.getType()); 2590 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2591} 2592 2593void SelectionDAGLowering::visitFPExt(User &I){ 2594 // FPTrunc is never a no-op cast, no need to check 2595 SDValue N = getValue(I.getOperand(0)); 2596 MVT DestVT = TLI.getValueType(I.getType()); 2597 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2598} 2599 2600void SelectionDAGLowering::visitFPToUI(User &I) { 2601 // FPToUI is never a no-op cast, no need to check 2602 SDValue N = getValue(I.getOperand(0)); 2603 MVT DestVT = TLI.getValueType(I.getType()); 2604 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2605} 2606 2607void SelectionDAGLowering::visitFPToSI(User &I) { 2608 // FPToSI is never a no-op cast, no need to check 2609 SDValue N = getValue(I.getOperand(0)); 2610 MVT DestVT = TLI.getValueType(I.getType()); 2611 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2612} 2613 2614void SelectionDAGLowering::visitUIToFP(User &I) { 2615 // UIToFP is never a no-op cast, no need to check 2616 SDValue N = getValue(I.getOperand(0)); 2617 MVT DestVT = TLI.getValueType(I.getType()); 2618 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2619} 2620 2621void SelectionDAGLowering::visitSIToFP(User &I){ 2622 // UIToFP is never a no-op cast, no need to check 2623 SDValue N = getValue(I.getOperand(0)); 2624 MVT DestVT = TLI.getValueType(I.getType()); 2625 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2626} 2627 2628void SelectionDAGLowering::visitPtrToInt(User &I) { 2629 // What to do depends on the size of the integer and the size of the pointer. 2630 // We can either truncate, zero extend, or no-op, accordingly. 2631 SDValue N = getValue(I.getOperand(0)); 2632 MVT SrcVT = N.getValueType(); 2633 MVT DestVT = TLI.getValueType(I.getType()); 2634 SDValue Result; 2635 if (DestVT.bitsLT(SrcVT)) 2636 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2637 else 2638 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2639 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2640 setValue(&I, Result); 2641} 2642 2643void SelectionDAGLowering::visitIntToPtr(User &I) { 2644 // What to do depends on the size of the integer and the size of the pointer. 2645 // We can either truncate, zero extend, or no-op, accordingly. 2646 SDValue N = getValue(I.getOperand(0)); 2647 MVT SrcVT = N.getValueType(); 2648 MVT DestVT = TLI.getValueType(I.getType()); 2649 if (DestVT.bitsLT(SrcVT)) 2650 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2651 else 2652 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2653 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2654} 2655 2656void SelectionDAGLowering::visitBitCast(User &I) { 2657 SDValue N = getValue(I.getOperand(0)); 2658 MVT DestVT = TLI.getValueType(I.getType()); 2659 2660 // BitCast assures us that source and destination are the same size so this 2661 // is either a BIT_CONVERT or a no-op. 2662 if (DestVT != N.getValueType()) 2663 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2664 else 2665 setValue(&I, N); // noop cast. 2666} 2667 2668void SelectionDAGLowering::visitInsertElement(User &I) { 2669 SDValue InVec = getValue(I.getOperand(0)); 2670 SDValue InVal = getValue(I.getOperand(1)); 2671 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2672 getValue(I.getOperand(2))); 2673 2674 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2675 TLI.getValueType(I.getType()), 2676 InVec, InVal, InIdx)); 2677} 2678 2679void SelectionDAGLowering::visitExtractElement(User &I) { 2680 SDValue InVec = getValue(I.getOperand(0)); 2681 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2682 getValue(I.getOperand(1))); 2683 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2684 TLI.getValueType(I.getType()), InVec, InIdx)); 2685} 2686 2687void SelectionDAGLowering::visitShuffleVector(User &I) { 2688 SDValue V1 = getValue(I.getOperand(0)); 2689 SDValue V2 = getValue(I.getOperand(1)); 2690 SDValue Mask = getValue(I.getOperand(2)); 2691 2692 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2693 TLI.getValueType(I.getType()), 2694 V1, V2, Mask)); 2695} 2696 2697void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { 2698 const Value *Op0 = I.getOperand(0); 2699 const Value *Op1 = I.getOperand(1); 2700 const Type *AggTy = I.getType(); 2701 const Type *ValTy = Op1->getType(); 2702 bool IntoUndef = isa<UndefValue>(Op0); 2703 bool FromUndef = isa<UndefValue>(Op1); 2704 2705 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2706 I.idx_begin(), I.idx_end()); 2707 2708 SmallVector<MVT, 4> AggValueVTs; 2709 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2710 SmallVector<MVT, 4> ValValueVTs; 2711 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2712 2713 unsigned NumAggValues = AggValueVTs.size(); 2714 unsigned NumValValues = ValValueVTs.size(); 2715 SmallVector<SDValue, 4> Values(NumAggValues); 2716 2717 SDValue Agg = getValue(Op0); 2718 SDValue Val = getValue(Op1); 2719 unsigned i = 0; 2720 // Copy the beginning value(s) from the original aggregate. 2721 for (; i != LinearIndex; ++i) 2722 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2723 SDValue(Agg.Val, Agg.ResNo + i); 2724 // Copy values from the inserted value(s). 2725 for (; i != LinearIndex + NumValValues; ++i) 2726 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2727 SDValue(Val.Val, Val.ResNo + i - LinearIndex); 2728 // Copy remaining value(s) from the original aggregate. 2729 for (; i != NumAggValues; ++i) 2730 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2731 SDValue(Agg.Val, Agg.ResNo + i); 2732 2733 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues), 2734 &Values[0], NumAggValues)); 2735} 2736 2737void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { 2738 const Value *Op0 = I.getOperand(0); 2739 const Type *AggTy = Op0->getType(); 2740 const Type *ValTy = I.getType(); 2741 bool OutOfUndef = isa<UndefValue>(Op0); 2742 2743 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2744 I.idx_begin(), I.idx_end()); 2745 2746 SmallVector<MVT, 4> ValValueVTs; 2747 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2748 2749 unsigned NumValValues = ValValueVTs.size(); 2750 SmallVector<SDValue, 4> Values(NumValValues); 2751 2752 SDValue Agg = getValue(Op0); 2753 // Copy out the selected value(s). 2754 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2755 Values[i - LinearIndex] = 2756 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) : 2757 SDValue(Agg.Val, Agg.ResNo + i); 2758 2759 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues), 2760 &Values[0], NumValValues)); 2761} 2762 2763 2764void SelectionDAGLowering::visitGetElementPtr(User &I) { 2765 SDValue N = getValue(I.getOperand(0)); 2766 const Type *Ty = I.getOperand(0)->getType(); 2767 2768 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2769 OI != E; ++OI) { 2770 Value *Idx = *OI; 2771 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2772 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2773 if (Field) { 2774 // N = N + Offset 2775 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2776 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2777 DAG.getIntPtrConstant(Offset)); 2778 } 2779 Ty = StTy->getElementType(Field); 2780 } else { 2781 Ty = cast<SequentialType>(Ty)->getElementType(); 2782 2783 // If this is a constant subscript, handle it quickly. 2784 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2785 if (CI->getZExtValue() == 0) continue; 2786 uint64_t Offs = 2787 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2788 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2789 DAG.getIntPtrConstant(Offs)); 2790 continue; 2791 } 2792 2793 // N = N + Idx * ElementSize; 2794 uint64_t ElementSize = TD->getABITypeSize(Ty); 2795 SDValue IdxN = getValue(Idx); 2796 2797 // If the index is smaller or larger than intptr_t, truncate or extend 2798 // it. 2799 if (IdxN.getValueType().bitsLT(N.getValueType())) { 2800 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2801 } else if (IdxN.getValueType().bitsGT(N.getValueType())) 2802 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2803 2804 // If this is a multiply by a power of two, turn it into a shl 2805 // immediately. This is a very common case. 2806 if (isPowerOf2_64(ElementSize)) { 2807 unsigned Amt = Log2_64(ElementSize); 2808 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2809 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2810 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2811 continue; 2812 } 2813 2814 SDValue Scale = DAG.getIntPtrConstant(ElementSize); 2815 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2816 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2817 } 2818 } 2819 setValue(&I, N); 2820} 2821 2822void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2823 // If this is a fixed sized alloca in the entry block of the function, 2824 // allocate it statically on the stack. 2825 if (FuncInfo.StaticAllocaMap.count(&I)) 2826 return; // getValue will auto-populate this. 2827 2828 const Type *Ty = I.getAllocatedType(); 2829 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2830 unsigned Align = 2831 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2832 I.getAlignment()); 2833 2834 SDValue AllocSize = getValue(I.getArraySize()); 2835 MVT IntPtr = TLI.getPointerTy(); 2836 if (IntPtr.bitsLT(AllocSize.getValueType())) 2837 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2838 else if (IntPtr.bitsGT(AllocSize.getValueType())) 2839 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2840 2841 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2842 DAG.getIntPtrConstant(TySize)); 2843 2844 // Handle alignment. If the requested alignment is less than or equal to 2845 // the stack alignment, ignore it. If the size is greater than or equal to 2846 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2847 unsigned StackAlign = 2848 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2849 if (Align <= StackAlign) 2850 Align = 0; 2851 2852 // Round the size of the allocation up to the stack alignment size 2853 // by add SA-1 to the size. 2854 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2855 DAG.getIntPtrConstant(StackAlign-1)); 2856 // Mask out the low bits for alignment purposes. 2857 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2858 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2859 2860 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2861 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2862 MVT::Other); 2863 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2864 setValue(&I, DSA); 2865 DAG.setRoot(DSA.getValue(1)); 2866 2867 // Inform the Frame Information that we have just allocated a variable-sized 2868 // object. 2869 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2870} 2871 2872void SelectionDAGLowering::visitLoad(LoadInst &I) { 2873 const Value *SV = I.getOperand(0); 2874 SDValue Ptr = getValue(SV); 2875 2876 const Type *Ty = I.getType(); 2877 bool isVolatile = I.isVolatile(); 2878 unsigned Alignment = I.getAlignment(); 2879 2880 SmallVector<MVT, 4> ValueVTs; 2881 SmallVector<uint64_t, 4> Offsets; 2882 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2883 unsigned NumValues = ValueVTs.size(); 2884 if (NumValues == 0) 2885 return; 2886 2887 SDValue Root; 2888 bool ConstantMemory = false; 2889 if (I.isVolatile()) 2890 // Serialize volatile loads with other side effects. 2891 Root = getRoot(); 2892 else if (AA.pointsToConstantMemory(SV)) { 2893 // Do not serialize (non-volatile) loads of constant memory with anything. 2894 Root = DAG.getEntryNode(); 2895 ConstantMemory = true; 2896 } else { 2897 // Do not serialize non-volatile loads against each other. 2898 Root = DAG.getRoot(); 2899 } 2900 2901 SmallVector<SDValue, 4> Values(NumValues); 2902 SmallVector<SDValue, 4> Chains(NumValues); 2903 MVT PtrVT = Ptr.getValueType(); 2904 for (unsigned i = 0; i != NumValues; ++i) { 2905 SDValue L = DAG.getLoad(ValueVTs[i], Root, 2906 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2907 DAG.getConstant(Offsets[i], PtrVT)), 2908 SV, Offsets[i], 2909 isVolatile, Alignment); 2910 Values[i] = L; 2911 Chains[i] = L.getValue(1); 2912 } 2913 2914 if (!ConstantMemory) { 2915 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2916 &Chains[0], NumValues); 2917 if (isVolatile) 2918 DAG.setRoot(Chain); 2919 else 2920 PendingLoads.push_back(Chain); 2921 } 2922 2923 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), 2924 &Values[0], NumValues)); 2925} 2926 2927 2928void SelectionDAGLowering::visitStore(StoreInst &I) { 2929 Value *SrcV = I.getOperand(0); 2930 SDValue Src = getValue(SrcV); 2931 Value *PtrV = I.getOperand(1); 2932 SDValue Ptr = getValue(PtrV); 2933 2934 SmallVector<MVT, 4> ValueVTs; 2935 SmallVector<uint64_t, 4> Offsets; 2936 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2937 unsigned NumValues = ValueVTs.size(); 2938 if (NumValues == 0) 2939 return; 2940 2941 SDValue Root = getRoot(); 2942 SmallVector<SDValue, 4> Chains(NumValues); 2943 MVT PtrVT = Ptr.getValueType(); 2944 bool isVolatile = I.isVolatile(); 2945 unsigned Alignment = I.getAlignment(); 2946 for (unsigned i = 0; i != NumValues; ++i) 2947 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i), 2948 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2949 DAG.getConstant(Offsets[i], PtrVT)), 2950 PtrV, Offsets[i], 2951 isVolatile, Alignment); 2952 2953 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues)); 2954} 2955 2956/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2957/// node. 2958void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2959 unsigned Intrinsic) { 2960 bool HasChain = !I.doesNotAccessMemory(); 2961 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2962 2963 // Build the operand list. 2964 SmallVector<SDValue, 8> Ops; 2965 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2966 if (OnlyLoad) { 2967 // We don't need to serialize loads against other loads. 2968 Ops.push_back(DAG.getRoot()); 2969 } else { 2970 Ops.push_back(getRoot()); 2971 } 2972 } 2973 2974 // Add the intrinsic ID as an integer operand. 2975 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2976 2977 // Add all operands of the call to the operand list. 2978 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2979 SDValue Op = getValue(I.getOperand(i)); 2980 assert(TLI.isTypeLegal(Op.getValueType()) && 2981 "Intrinsic uses a non-legal type?"); 2982 Ops.push_back(Op); 2983 } 2984 2985 std::vector<MVT> VTs; 2986 if (I.getType() != Type::VoidTy) { 2987 MVT VT = TLI.getValueType(I.getType()); 2988 if (VT.isVector()) { 2989 const VectorType *DestTy = cast<VectorType>(I.getType()); 2990 MVT EltVT = TLI.getValueType(DestTy->getElementType()); 2991 2992 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); 2993 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2994 } 2995 2996 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2997 VTs.push_back(VT); 2998 } 2999 if (HasChain) 3000 VTs.push_back(MVT::Other); 3001 3002 const MVT *VTList = DAG.getNodeValueTypes(VTs); 3003 3004 // Create the node. 3005 SDValue Result; 3006 if (!HasChain) 3007 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 3008 &Ops[0], Ops.size()); 3009 else if (I.getType() != Type::VoidTy) 3010 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 3011 &Ops[0], Ops.size()); 3012 else 3013 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 3014 &Ops[0], Ops.size()); 3015 3016 if (HasChain) { 3017 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1); 3018 if (OnlyLoad) 3019 PendingLoads.push_back(Chain); 3020 else 3021 DAG.setRoot(Chain); 3022 } 3023 if (I.getType() != Type::VoidTy) { 3024 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3025 MVT VT = TLI.getValueType(PTy); 3026 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 3027 } 3028 setValue(&I, Result); 3029 } 3030} 3031 3032/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 3033static GlobalVariable *ExtractTypeInfo (Value *V) { 3034 V = V->stripPointerCasts(); 3035 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 3036 assert ((GV || isa<ConstantPointerNull>(V)) && 3037 "TypeInfo must be a global variable or NULL"); 3038 return GV; 3039} 3040 3041/// addCatchInfo - Extract the personality and type infos from an eh.selector 3042/// call, and add them to the specified machine basic block. 3043static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 3044 MachineBasicBlock *MBB) { 3045 // Inform the MachineModuleInfo of the personality for this landing pad. 3046 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 3047 assert(CE->getOpcode() == Instruction::BitCast && 3048 isa<Function>(CE->getOperand(0)) && 3049 "Personality should be a function"); 3050 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 3051 3052 // Gather all the type infos for this landing pad and pass them along to 3053 // MachineModuleInfo. 3054 std::vector<GlobalVariable *> TyInfo; 3055 unsigned N = I.getNumOperands(); 3056 3057 for (unsigned i = N - 1; i > 2; --i) { 3058 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 3059 unsigned FilterLength = CI->getZExtValue(); 3060 unsigned FirstCatch = i + FilterLength + !FilterLength; 3061 assert (FirstCatch <= N && "Invalid filter length"); 3062 3063 if (FirstCatch < N) { 3064 TyInfo.reserve(N - FirstCatch); 3065 for (unsigned j = FirstCatch; j < N; ++j) 3066 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3067 MMI->addCatchTypeInfo(MBB, TyInfo); 3068 TyInfo.clear(); 3069 } 3070 3071 if (!FilterLength) { 3072 // Cleanup. 3073 MMI->addCleanup(MBB); 3074 } else { 3075 // Filter. 3076 TyInfo.reserve(FilterLength - 1); 3077 for (unsigned j = i + 1; j < FirstCatch; ++j) 3078 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3079 MMI->addFilterTypeInfo(MBB, TyInfo); 3080 TyInfo.clear(); 3081 } 3082 3083 N = i; 3084 } 3085 } 3086 3087 if (N > 3) { 3088 TyInfo.reserve(N - 3); 3089 for (unsigned j = 3; j < N; ++j) 3090 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3091 MMI->addCatchTypeInfo(MBB, TyInfo); 3092 } 3093} 3094 3095 3096/// Inlined utility function to implement binary input atomic intrinsics for 3097// visitIntrinsicCall: I is a call instruction 3098// Op is the associated NodeType for I 3099const char * 3100SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { 3101 SDValue Root = getRoot(); 3102 SDValue L = DAG.getAtomic(Op, Root, 3103 getValue(I.getOperand(1)), 3104 getValue(I.getOperand(2)), 3105 I.getOperand(1)); 3106 setValue(&I, L); 3107 DAG.setRoot(L.getValue(1)); 3108 return 0; 3109} 3110 3111/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3112/// we want to emit this as a call to a named external function, return the name 3113/// otherwise lower it and return null. 3114const char * 3115SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 3116 switch (Intrinsic) { 3117 default: 3118 // By default, turn this into a target intrinsic node. 3119 visitTargetIntrinsic(I, Intrinsic); 3120 return 0; 3121 case Intrinsic::vastart: visitVAStart(I); return 0; 3122 case Intrinsic::vaend: visitVAEnd(I); return 0; 3123 case Intrinsic::vacopy: visitVACopy(I); return 0; 3124 case Intrinsic::returnaddress: 3125 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 3126 getValue(I.getOperand(1)))); 3127 return 0; 3128 case Intrinsic::frameaddress: 3129 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 3130 getValue(I.getOperand(1)))); 3131 return 0; 3132 case Intrinsic::setjmp: 3133 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3134 break; 3135 case Intrinsic::longjmp: 3136 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3137 break; 3138 case Intrinsic::memcpy_i32: 3139 case Intrinsic::memcpy_i64: { 3140 SDValue Op1 = getValue(I.getOperand(1)); 3141 SDValue Op2 = getValue(I.getOperand(2)); 3142 SDValue Op3 = getValue(I.getOperand(3)); 3143 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3144 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3145 I.getOperand(1), 0, I.getOperand(2), 0)); 3146 return 0; 3147 } 3148 case Intrinsic::memset_i32: 3149 case Intrinsic::memset_i64: { 3150 SDValue Op1 = getValue(I.getOperand(1)); 3151 SDValue Op2 = getValue(I.getOperand(2)); 3152 SDValue Op3 = getValue(I.getOperand(3)); 3153 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3154 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, 3155 I.getOperand(1), 0)); 3156 return 0; 3157 } 3158 case Intrinsic::memmove_i32: 3159 case Intrinsic::memmove_i64: { 3160 SDValue Op1 = getValue(I.getOperand(1)); 3161 SDValue Op2 = getValue(I.getOperand(2)); 3162 SDValue Op3 = getValue(I.getOperand(3)); 3163 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3164 3165 // If the source and destination are known to not be aliases, we can 3166 // lower memmove as memcpy. 3167 uint64_t Size = -1ULL; 3168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3169 Size = C->getValue(); 3170 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3171 AliasAnalysis::NoAlias) { 3172 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3173 I.getOperand(1), 0, I.getOperand(2), 0)); 3174 return 0; 3175 } 3176 3177 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, 3178 I.getOperand(1), 0, I.getOperand(2), 0)); 3179 return 0; 3180 } 3181 case Intrinsic::dbg_stoppoint: { 3182 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3183 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 3184 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 3185 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 3186 assert(DD && "Not a debug information descriptor"); 3187 DAG.setRoot(DAG.getDbgStopPoint(getRoot(), 3188 SPI.getLine(), 3189 SPI.getColumn(), 3190 cast<CompileUnitDesc>(DD))); 3191 } 3192 3193 return 0; 3194 } 3195 case Intrinsic::dbg_region_start: { 3196 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3197 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 3198 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 3199 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 3200 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3201 } 3202 3203 return 0; 3204 } 3205 case Intrinsic::dbg_region_end: { 3206 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3207 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 3208 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 3209 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 3210 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3211 } 3212 3213 return 0; 3214 } 3215 case Intrinsic::dbg_func_start: { 3216 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3217 if (!MMI) return 0; 3218 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 3219 Value *SP = FSI.getSubprogram(); 3220 if (SP && MMI->Verify(SP)) { 3221 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 3222 // what (most?) gdb expects. 3223 DebugInfoDesc *DD = MMI->getDescFor(SP); 3224 assert(DD && "Not a debug information descriptor"); 3225 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 3226 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 3227 unsigned SrcFile = MMI->RecordSource(CompileUnit); 3228 // Record the source line but does create a label. It will be emitted 3229 // at asm emission time. 3230 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 3231 } 3232 3233 return 0; 3234 } 3235 case Intrinsic::dbg_declare: { 3236 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3237 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3238 Value *Variable = DI.getVariable(); 3239 if (MMI && Variable && MMI->Verify(Variable)) 3240 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 3241 getValue(DI.getAddress()), getValue(Variable))); 3242 return 0; 3243 } 3244 3245 case Intrinsic::eh_exception: { 3246 if (!CurMBB->isLandingPad()) { 3247 // FIXME: Mark exception register as live in. Hack for PR1508. 3248 unsigned Reg = TLI.getExceptionAddressRegister(); 3249 if (Reg) CurMBB->addLiveIn(Reg); 3250 } 3251 // Insert the EXCEPTIONADDR instruction. 3252 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3253 SDValue Ops[1]; 3254 Ops[0] = DAG.getRoot(); 3255 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 3256 setValue(&I, Op); 3257 DAG.setRoot(Op.getValue(1)); 3258 return 0; 3259 } 3260 3261 case Intrinsic::eh_selector_i32: 3262 case Intrinsic::eh_selector_i64: { 3263 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3264 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 3265 MVT::i32 : MVT::i64); 3266 3267 if (MMI) { 3268 if (CurMBB->isLandingPad()) 3269 addCatchInfo(I, MMI, CurMBB); 3270 else { 3271#ifndef NDEBUG 3272 FuncInfo.CatchInfoLost.insert(&I); 3273#endif 3274 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3275 unsigned Reg = TLI.getExceptionSelectorRegister(); 3276 if (Reg) CurMBB->addLiveIn(Reg); 3277 } 3278 3279 // Insert the EHSELECTION instruction. 3280 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 3281 SDValue Ops[2]; 3282 Ops[0] = getValue(I.getOperand(1)); 3283 Ops[1] = getRoot(); 3284 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 3285 setValue(&I, Op); 3286 DAG.setRoot(Op.getValue(1)); 3287 } else { 3288 setValue(&I, DAG.getConstant(0, VT)); 3289 } 3290 3291 return 0; 3292 } 3293 3294 case Intrinsic::eh_typeid_for_i32: 3295 case Intrinsic::eh_typeid_for_i64: { 3296 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3297 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 3298 MVT::i32 : MVT::i64); 3299 3300 if (MMI) { 3301 // Find the type id for the given typeinfo. 3302 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3303 3304 unsigned TypeID = MMI->getTypeIDFor(GV); 3305 setValue(&I, DAG.getConstant(TypeID, VT)); 3306 } else { 3307 // Return something different to eh_selector. 3308 setValue(&I, DAG.getConstant(1, VT)); 3309 } 3310 3311 return 0; 3312 } 3313 3314 case Intrinsic::eh_return: { 3315 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3316 3317 if (MMI) { 3318 MMI->setCallsEHReturn(true); 3319 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 3320 MVT::Other, 3321 getControlRoot(), 3322 getValue(I.getOperand(1)), 3323 getValue(I.getOperand(2)))); 3324 } else { 3325 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 3326 } 3327 3328 return 0; 3329 } 3330 3331 case Intrinsic::eh_unwind_init: { 3332 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3333 MMI->setCallsUnwindInit(true); 3334 } 3335 3336 return 0; 3337 } 3338 3339 case Intrinsic::eh_dwarf_cfa: { 3340 MVT VT = getValue(I.getOperand(1)).getValueType(); 3341 SDValue CfaArg; 3342 if (VT.bitsGT(TLI.getPointerTy())) 3343 CfaArg = DAG.getNode(ISD::TRUNCATE, 3344 TLI.getPointerTy(), getValue(I.getOperand(1))); 3345 else 3346 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 3347 TLI.getPointerTy(), getValue(I.getOperand(1))); 3348 3349 SDValue Offset = DAG.getNode(ISD::ADD, 3350 TLI.getPointerTy(), 3351 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 3352 TLI.getPointerTy()), 3353 CfaArg); 3354 setValue(&I, DAG.getNode(ISD::ADD, 3355 TLI.getPointerTy(), 3356 DAG.getNode(ISD::FRAMEADDR, 3357 TLI.getPointerTy(), 3358 DAG.getConstant(0, 3359 TLI.getPointerTy())), 3360 Offset)); 3361 return 0; 3362 } 3363 3364 case Intrinsic::sqrt: 3365 setValue(&I, DAG.getNode(ISD::FSQRT, 3366 getValue(I.getOperand(1)).getValueType(), 3367 getValue(I.getOperand(1)))); 3368 return 0; 3369 case Intrinsic::powi: 3370 setValue(&I, DAG.getNode(ISD::FPOWI, 3371 getValue(I.getOperand(1)).getValueType(), 3372 getValue(I.getOperand(1)), 3373 getValue(I.getOperand(2)))); 3374 return 0; 3375 case Intrinsic::sin: 3376 setValue(&I, DAG.getNode(ISD::FSIN, 3377 getValue(I.getOperand(1)).getValueType(), 3378 getValue(I.getOperand(1)))); 3379 return 0; 3380 case Intrinsic::cos: 3381 setValue(&I, DAG.getNode(ISD::FCOS, 3382 getValue(I.getOperand(1)).getValueType(), 3383 getValue(I.getOperand(1)))); 3384 return 0; 3385 case Intrinsic::pow: 3386 setValue(&I, DAG.getNode(ISD::FPOW, 3387 getValue(I.getOperand(1)).getValueType(), 3388 getValue(I.getOperand(1)), 3389 getValue(I.getOperand(2)))); 3390 return 0; 3391 case Intrinsic::pcmarker: { 3392 SDValue Tmp = getValue(I.getOperand(1)); 3393 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 3394 return 0; 3395 } 3396 case Intrinsic::readcyclecounter: { 3397 SDValue Op = getRoot(); 3398 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 3399 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 3400 &Op, 1); 3401 setValue(&I, Tmp); 3402 DAG.setRoot(Tmp.getValue(1)); 3403 return 0; 3404 } 3405 case Intrinsic::part_select: { 3406 // Currently not implemented: just abort 3407 assert(0 && "part_select intrinsic not implemented"); 3408 abort(); 3409 } 3410 case Intrinsic::part_set: { 3411 // Currently not implemented: just abort 3412 assert(0 && "part_set intrinsic not implemented"); 3413 abort(); 3414 } 3415 case Intrinsic::bswap: 3416 setValue(&I, DAG.getNode(ISD::BSWAP, 3417 getValue(I.getOperand(1)).getValueType(), 3418 getValue(I.getOperand(1)))); 3419 return 0; 3420 case Intrinsic::cttz: { 3421 SDValue Arg = getValue(I.getOperand(1)); 3422 MVT Ty = Arg.getValueType(); 3423 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg); 3424 setValue(&I, result); 3425 return 0; 3426 } 3427 case Intrinsic::ctlz: { 3428 SDValue Arg = getValue(I.getOperand(1)); 3429 MVT Ty = Arg.getValueType(); 3430 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg); 3431 setValue(&I, result); 3432 return 0; 3433 } 3434 case Intrinsic::ctpop: { 3435 SDValue Arg = getValue(I.getOperand(1)); 3436 MVT Ty = Arg.getValueType(); 3437 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg); 3438 setValue(&I, result); 3439 return 0; 3440 } 3441 case Intrinsic::stacksave: { 3442 SDValue Op = getRoot(); 3443 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, 3444 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 3445 setValue(&I, Tmp); 3446 DAG.setRoot(Tmp.getValue(1)); 3447 return 0; 3448 } 3449 case Intrinsic::stackrestore: { 3450 SDValue Tmp = getValue(I.getOperand(1)); 3451 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 3452 return 0; 3453 } 3454 case Intrinsic::var_annotation: 3455 // Discard annotate attributes 3456 return 0; 3457 3458 case Intrinsic::init_trampoline: { 3459 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 3460 3461 SDValue Ops[6]; 3462 Ops[0] = getRoot(); 3463 Ops[1] = getValue(I.getOperand(1)); 3464 Ops[2] = getValue(I.getOperand(2)); 3465 Ops[3] = getValue(I.getOperand(3)); 3466 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3467 Ops[5] = DAG.getSrcValue(F); 3468 3469 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, 3470 DAG.getNodeValueTypes(TLI.getPointerTy(), 3471 MVT::Other), 2, 3472 Ops, 6); 3473 3474 setValue(&I, Tmp); 3475 DAG.setRoot(Tmp.getValue(1)); 3476 return 0; 3477 } 3478 3479 case Intrinsic::gcroot: 3480 if (GCI) { 3481 Value *Alloca = I.getOperand(1); 3482 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3483 3484 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3485 GCI->addStackRoot(FI->getIndex(), TypeMap); 3486 } 3487 return 0; 3488 3489 case Intrinsic::gcread: 3490 case Intrinsic::gcwrite: 3491 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3492 return 0; 3493 3494 case Intrinsic::flt_rounds: { 3495 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3496 return 0; 3497 } 3498 3499 case Intrinsic::trap: { 3500 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3501 return 0; 3502 } 3503 case Intrinsic::prefetch: { 3504 SDValue Ops[4]; 3505 Ops[0] = getRoot(); 3506 Ops[1] = getValue(I.getOperand(1)); 3507 Ops[2] = getValue(I.getOperand(2)); 3508 Ops[3] = getValue(I.getOperand(3)); 3509 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4)); 3510 return 0; 3511 } 3512 3513 case Intrinsic::memory_barrier: { 3514 SDValue Ops[6]; 3515 Ops[0] = getRoot(); 3516 for (int x = 1; x < 6; ++x) 3517 Ops[x] = getValue(I.getOperand(x)); 3518 3519 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); 3520 return 0; 3521 } 3522 case Intrinsic::atomic_cmp_swap: { 3523 SDValue Root = getRoot(); 3524 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root, 3525 getValue(I.getOperand(1)), 3526 getValue(I.getOperand(2)), 3527 getValue(I.getOperand(3)), 3528 I.getOperand(1)); 3529 setValue(&I, L); 3530 DAG.setRoot(L.getValue(1)); 3531 return 0; 3532 } 3533 case Intrinsic::atomic_load_add: 3534 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 3535 case Intrinsic::atomic_load_sub: 3536 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 3537 case Intrinsic::atomic_load_and: 3538 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 3539 case Intrinsic::atomic_load_or: 3540 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 3541 case Intrinsic::atomic_load_xor: 3542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 3543 case Intrinsic::atomic_load_nand: 3544 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 3545 case Intrinsic::atomic_load_min: 3546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 3547 case Intrinsic::atomic_load_max: 3548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 3549 case Intrinsic::atomic_load_umin: 3550 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 3551 case Intrinsic::atomic_load_umax: 3552 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 3553 case Intrinsic::atomic_swap: 3554 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 3555 } 3556} 3557 3558 3559void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, 3560 bool IsTailCall, 3561 MachineBasicBlock *LandingPad) { 3562 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3563 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3564 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3565 unsigned BeginLabel = 0, EndLabel = 0; 3566 3567 TargetLowering::ArgListTy Args; 3568 TargetLowering::ArgListEntry Entry; 3569 Args.reserve(CS.arg_size()); 3570 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3571 i != e; ++i) { 3572 SDValue ArgNode = getValue(*i); 3573 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3574 3575 unsigned attrInd = i - CS.arg_begin() + 1; 3576 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3577 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3578 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3579 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3580 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3581 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3582 Entry.Alignment = CS.getParamAlignment(attrInd); 3583 Args.push_back(Entry); 3584 } 3585 3586 if (LandingPad && MMI) { 3587 // Insert a label before the invoke call to mark the try range. This can be 3588 // used to detect deletion of the invoke via the MachineModuleInfo. 3589 BeginLabel = MMI->NextLabelID(); 3590 // Both PendingLoads and PendingExports must be flushed here; 3591 // this call might not return. 3592 (void)getRoot(); 3593 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); 3594 } 3595 3596 std::pair<SDValue,SDValue> Result = 3597 TLI.LowerCallTo(getRoot(), CS.getType(), 3598 CS.paramHasAttr(0, ParamAttr::SExt), 3599 CS.paramHasAttr(0, ParamAttr::ZExt), 3600 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3601 Callee, Args, DAG); 3602 if (CS.getType() != Type::VoidTy) 3603 setValue(CS.getInstruction(), Result.first); 3604 DAG.setRoot(Result.second); 3605 3606 if (LandingPad && MMI) { 3607 // Insert a label at the end of the invoke call to mark the try range. This 3608 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3609 EndLabel = MMI->NextLabelID(); 3610 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); 3611 3612 // Inform MachineModuleInfo of range. 3613 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3614 } 3615} 3616 3617 3618void SelectionDAGLowering::visitCall(CallInst &I) { 3619 const char *RenameFn = 0; 3620 if (Function *F = I.getCalledFunction()) { 3621 if (F->isDeclaration()) { 3622 if (unsigned IID = F->getIntrinsicID()) { 3623 RenameFn = visitIntrinsicCall(I, IID); 3624 if (!RenameFn) 3625 return; 3626 } 3627 } 3628 3629 // Check for well-known libc/libm calls. If the function is internal, it 3630 // can't be a library call. 3631 unsigned NameLen = F->getNameLen(); 3632 if (!F->hasInternalLinkage() && NameLen) { 3633 const char *NameStr = F->getNameStart(); 3634 if (NameStr[0] == 'c' && 3635 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3636 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3637 if (I.getNumOperands() == 3 && // Basic sanity checks. 3638 I.getOperand(1)->getType()->isFloatingPoint() && 3639 I.getType() == I.getOperand(1)->getType() && 3640 I.getType() == I.getOperand(2)->getType()) { 3641 SDValue LHS = getValue(I.getOperand(1)); 3642 SDValue RHS = getValue(I.getOperand(2)); 3643 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3644 LHS, RHS)); 3645 return; 3646 } 3647 } else if (NameStr[0] == 'f' && 3648 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3649 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3650 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3651 if (I.getNumOperands() == 2 && // Basic sanity checks. 3652 I.getOperand(1)->getType()->isFloatingPoint() && 3653 I.getType() == I.getOperand(1)->getType()) { 3654 SDValue Tmp = getValue(I.getOperand(1)); 3655 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3656 return; 3657 } 3658 } else if (NameStr[0] == 's' && 3659 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3660 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3661 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3662 if (I.getNumOperands() == 2 && // Basic sanity checks. 3663 I.getOperand(1)->getType()->isFloatingPoint() && 3664 I.getType() == I.getOperand(1)->getType()) { 3665 SDValue Tmp = getValue(I.getOperand(1)); 3666 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3667 return; 3668 } 3669 } else if (NameStr[0] == 'c' && 3670 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3671 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3672 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3673 if (I.getNumOperands() == 2 && // Basic sanity checks. 3674 I.getOperand(1)->getType()->isFloatingPoint() && 3675 I.getType() == I.getOperand(1)->getType()) { 3676 SDValue Tmp = getValue(I.getOperand(1)); 3677 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3678 return; 3679 } 3680 } 3681 } 3682 } else if (isa<InlineAsm>(I.getOperand(0))) { 3683 visitInlineAsm(&I); 3684 return; 3685 } 3686 3687 SDValue Callee; 3688 if (!RenameFn) 3689 Callee = getValue(I.getOperand(0)); 3690 else 3691 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3692 3693 LowerCallTo(&I, Callee, I.isTailCall()); 3694} 3695 3696 3697/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3698/// this value and returns the result as a ValueVT value. This uses 3699/// Chain/Flag as the input and updates them for the output Chain/Flag. 3700/// If the Flag pointer is NULL, no flag is used. 3701SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3702 SDValue &Chain, 3703 SDValue *Flag) const { 3704 // Assemble the legal parts into the final values. 3705 SmallVector<SDValue, 4> Values(ValueVTs.size()); 3706 SmallVector<SDValue, 8> Parts; 3707 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3708 // Copy the legal parts from the registers. 3709 MVT ValueVT = ValueVTs[Value]; 3710 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 3711 MVT RegisterVT = RegVTs[Value]; 3712 3713 Parts.resize(NumRegs); 3714 for (unsigned i = 0; i != NumRegs; ++i) { 3715 SDValue P; 3716 if (Flag == 0) 3717 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); 3718 else { 3719 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); 3720 *Flag = P.getValue(2); 3721 } 3722 Chain = P.getValue(1); 3723 3724 // If the source register was virtual and if we know something about it, 3725 // add an assert node. 3726 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 3727 RegisterVT.isInteger() && !RegisterVT.isVector()) { 3728 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 3729 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 3730 if (FLI.LiveOutRegInfo.size() > SlotNo) { 3731 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 3732 3733 unsigned RegSize = RegisterVT.getSizeInBits(); 3734 unsigned NumSignBits = LOI.NumSignBits; 3735 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 3736 3737 // FIXME: We capture more information than the dag can represent. For 3738 // now, just use the tightest assertzext/assertsext possible. 3739 bool isSExt = true; 3740 MVT FromVT(MVT::Other); 3741 if (NumSignBits == RegSize) 3742 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 3743 else if (NumZeroBits >= RegSize-1) 3744 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 3745 else if (NumSignBits > RegSize-8) 3746 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 3747 else if (NumZeroBits >= RegSize-9) 3748 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 3749 else if (NumSignBits > RegSize-16) 3750 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 3751 else if (NumZeroBits >= RegSize-17) 3752 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 3753 else if (NumSignBits > RegSize-32) 3754 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 3755 else if (NumZeroBits >= RegSize-33) 3756 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 3757 3758 if (FromVT != MVT::Other) { 3759 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, 3760 RegisterVT, P, DAG.getValueType(FromVT)); 3761 3762 } 3763 } 3764 } 3765 3766 Parts[Part+i] = P; 3767 } 3768 3769 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT, 3770 ValueVT); 3771 Part += NumRegs; 3772 } 3773 3774 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 3775 &Values[0], ValueVTs.size()); 3776} 3777 3778/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3779/// specified value into the registers specified by this object. This uses 3780/// Chain/Flag as the input and updates them for the output Chain/Flag. 3781/// If the Flag pointer is NULL, no flag is used. 3782void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, 3783 SDValue &Chain, SDValue *Flag) const { 3784 // Get the list of the values's legal parts. 3785 unsigned NumRegs = Regs.size(); 3786 SmallVector<SDValue, 8> Parts(NumRegs); 3787 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3788 MVT ValueVT = ValueVTs[Value]; 3789 unsigned NumParts = TLI->getNumRegisters(ValueVT); 3790 MVT RegisterVT = RegVTs[Value]; 3791 3792 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value), 3793 &Parts[Part], NumParts, RegisterVT); 3794 Part += NumParts; 3795 } 3796 3797 // Copy the parts into the registers. 3798 SmallVector<SDValue, 8> Chains(NumRegs); 3799 for (unsigned i = 0; i != NumRegs; ++i) { 3800 SDValue Part; 3801 if (Flag == 0) 3802 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3803 else { 3804 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); 3805 *Flag = Part.getValue(1); 3806 } 3807 Chains[i] = Part.getValue(0); 3808 } 3809 3810 if (NumRegs == 1 || Flag) 3811 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 3812 // flagged to it. That is the CopyToReg nodes and the user are considered 3813 // a single scheduling unit. If we create a TokenFactor and return it as 3814 // chain, then the TokenFactor is both a predecessor (operand) of the 3815 // user as well as a successor (the TF operands are flagged to the user). 3816 // c1, f1 = CopyToReg 3817 // c2, f2 = CopyToReg 3818 // c3 = TokenFactor c1, c2 3819 // ... 3820 // = op c3, ..., f2 3821 Chain = Chains[NumRegs-1]; 3822 else 3823 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 3824} 3825 3826/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3827/// operand list. This adds the code marker and includes the number of 3828/// values added into it. 3829void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3830 std::vector<SDValue> &Ops) const { 3831 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3832 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3833 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 3834 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); 3835 MVT RegisterVT = RegVTs[Value]; 3836 for (unsigned i = 0; i != NumRegs; ++i) 3837 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 3838 } 3839} 3840 3841/// isAllocatableRegister - If the specified register is safe to allocate, 3842/// i.e. it isn't a stack pointer or some other special register, return the 3843/// register class for the register. Otherwise, return null. 3844static const TargetRegisterClass * 3845isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3846 const TargetLowering &TLI, 3847 const TargetRegisterInfo *TRI) { 3848 MVT FoundVT = MVT::Other; 3849 const TargetRegisterClass *FoundRC = 0; 3850 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3851 E = TRI->regclass_end(); RCI != E; ++RCI) { 3852 MVT ThisVT = MVT::Other; 3853 3854 const TargetRegisterClass *RC = *RCI; 3855 // If none of the the value types for this register class are valid, we 3856 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3857 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3858 I != E; ++I) { 3859 if (TLI.isTypeLegal(*I)) { 3860 // If we have already found this register in a different register class, 3861 // choose the one with the largest VT specified. For example, on 3862 // PowerPC, we favor f64 register classes over f32. 3863 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 3864 ThisVT = *I; 3865 break; 3866 } 3867 } 3868 } 3869 3870 if (ThisVT == MVT::Other) continue; 3871 3872 // NOTE: This isn't ideal. In particular, this might allocate the 3873 // frame pointer in functions that need it (due to them not being taken 3874 // out of allocation, because a variable sized allocation hasn't been seen 3875 // yet). This is a slight code pessimization, but should still work. 3876 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3877 E = RC->allocation_order_end(MF); I != E; ++I) 3878 if (*I == Reg) { 3879 // We found a matching register class. Keep looking at others in case 3880 // we find one with larger registers that this physreg is also in. 3881 FoundRC = RC; 3882 FoundVT = ThisVT; 3883 break; 3884 } 3885 } 3886 return FoundRC; 3887} 3888 3889 3890namespace { 3891/// AsmOperandInfo - This contains information for each constraint that we are 3892/// lowering. 3893struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 3894 /// CallOperand - If this is the result output operand or a clobber 3895 /// this is null, otherwise it is the incoming operand to the CallInst. 3896 /// This gets modified as the asm is processed. 3897 SDValue CallOperand; 3898 3899 /// AssignedRegs - If this is a register or register class operand, this 3900 /// contains the set of register corresponding to the operand. 3901 RegsForValue AssignedRegs; 3902 3903 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3904 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 3905 } 3906 3907 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3908 /// busy in OutputRegs/InputRegs. 3909 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3910 std::set<unsigned> &OutputRegs, 3911 std::set<unsigned> &InputRegs, 3912 const TargetRegisterInfo &TRI) const { 3913 if (isOutReg) { 3914 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3915 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 3916 } 3917 if (isInReg) { 3918 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3919 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 3920 } 3921 } 3922 3923private: 3924 /// MarkRegAndAliases - Mark the specified register and all aliases in the 3925 /// specified set. 3926 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 3927 const TargetRegisterInfo &TRI) { 3928 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 3929 Regs.insert(Reg); 3930 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 3931 for (; *Aliases; ++Aliases) 3932 Regs.insert(*Aliases); 3933 } 3934}; 3935} // end anon namespace. 3936 3937 3938/// GetRegistersForValue - Assign registers (virtual or physical) for the 3939/// specified operand. We prefer to assign virtual registers, to allow the 3940/// register allocator handle the assignment process. However, if the asm uses 3941/// features that we can't model on machineinstrs, we have SDISel do the 3942/// allocation. This produces generally horrible, but correct, code. 3943/// 3944/// OpInfo describes the operand. 3945/// HasEarlyClobber is true if there are any early clobber constraints (=&r) 3946/// or any explicitly clobbered registers. 3947/// Input and OutputRegs are the set of already allocated physical registers. 3948/// 3949void SelectionDAGLowering:: 3950GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 3951 std::set<unsigned> &OutputRegs, 3952 std::set<unsigned> &InputRegs) { 3953 // Compute whether this value requires an input register, an output register, 3954 // or both. 3955 bool isOutReg = false; 3956 bool isInReg = false; 3957 switch (OpInfo.Type) { 3958 case InlineAsm::isOutput: 3959 isOutReg = true; 3960 3961 // If this is an early-clobber output, or if there is an input 3962 // constraint that matches this, we need to reserve the input register 3963 // so no other inputs allocate to it. 3964 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3965 break; 3966 case InlineAsm::isInput: 3967 isInReg = true; 3968 isOutReg = false; 3969 break; 3970 case InlineAsm::isClobber: 3971 isOutReg = true; 3972 isInReg = true; 3973 break; 3974 } 3975 3976 3977 MachineFunction &MF = DAG.getMachineFunction(); 3978 SmallVector<unsigned, 4> Regs; 3979 3980 // If this is a constraint for a single physreg, or a constraint for a 3981 // register class, find it. 3982 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3983 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3984 OpInfo.ConstraintVT); 3985 3986 unsigned NumRegs = 1; 3987 if (OpInfo.ConstraintVT != MVT::Other) 3988 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3989 MVT RegVT; 3990 MVT ValueVT = OpInfo.ConstraintVT; 3991 3992 3993 // If this is a constraint for a specific physical register, like {r17}, 3994 // assign it now. 3995 if (PhysReg.first) { 3996 if (OpInfo.ConstraintVT == MVT::Other) 3997 ValueVT = *PhysReg.second->vt_begin(); 3998 3999 // Get the actual register value type. This is important, because the user 4000 // may have asked for (e.g.) the AX register in i32 type. We need to 4001 // remember that AX is actually i16 to get the right extension. 4002 RegVT = *PhysReg.second->vt_begin(); 4003 4004 // This is a explicit reference to a physical register. 4005 Regs.push_back(PhysReg.first); 4006 4007 // If this is an expanded reference, add the rest of the regs to Regs. 4008 if (NumRegs != 1) { 4009 TargetRegisterClass::iterator I = PhysReg.second->begin(); 4010 for (; *I != PhysReg.first; ++I) 4011 assert(I != PhysReg.second->end() && "Didn't find reg!"); 4012 4013 // Already added the first reg. 4014 --NumRegs; ++I; 4015 for (; NumRegs; --NumRegs, ++I) { 4016 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); 4017 Regs.push_back(*I); 4018 } 4019 } 4020 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4021 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4022 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4023 return; 4024 } 4025 4026 // Otherwise, if this was a reference to an LLVM register class, create vregs 4027 // for this reference. 4028 std::vector<unsigned> RegClassRegs; 4029 const TargetRegisterClass *RC = PhysReg.second; 4030 if (RC) { 4031 // If this is an early clobber or tied register, our regalloc doesn't know 4032 // how to maintain the constraint. If it isn't, go ahead and create vreg 4033 // and let the regalloc do the right thing. 4034 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 4035 // If there is some other early clobber and this is an input register, 4036 // then we are forced to pre-allocate the input reg so it doesn't 4037 // conflict with the earlyclobber. 4038 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 4039 RegVT = *PhysReg.second->vt_begin(); 4040 4041 if (OpInfo.ConstraintVT == MVT::Other) 4042 ValueVT = RegVT; 4043 4044 // Create the appropriate number of virtual registers. 4045 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4046 for (; NumRegs; --NumRegs) 4047 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 4048 4049 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4050 return; 4051 } 4052 4053 // Otherwise, we can't allocate it. Let the code below figure out how to 4054 // maintain these constraints. 4055 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 4056 4057 } else { 4058 // This is a reference to a register class that doesn't directly correspond 4059 // to an LLVM register class. Allocate NumRegs consecutive, available, 4060 // registers from the class. 4061 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 4062 OpInfo.ConstraintVT); 4063 } 4064 4065 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4066 unsigned NumAllocated = 0; 4067 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 4068 unsigned Reg = RegClassRegs[i]; 4069 // See if this register is available. 4070 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 4071 (isInReg && InputRegs.count(Reg))) { // Already used. 4072 // Make sure we find consecutive registers. 4073 NumAllocated = 0; 4074 continue; 4075 } 4076 4077 // Check to see if this register is allocatable (i.e. don't give out the 4078 // stack pointer). 4079 if (RC == 0) { 4080 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 4081 if (!RC) { // Couldn't allocate this register. 4082 // Reset NumAllocated to make sure we return consecutive registers. 4083 NumAllocated = 0; 4084 continue; 4085 } 4086 } 4087 4088 // Okay, this register is good, we can use it. 4089 ++NumAllocated; 4090 4091 // If we allocated enough consecutive registers, succeed. 4092 if (NumAllocated == NumRegs) { 4093 unsigned RegStart = (i-NumAllocated)+1; 4094 unsigned RegEnd = i+1; 4095 // Mark all of the allocated registers used. 4096 for (unsigned i = RegStart; i != RegEnd; ++i) 4097 Regs.push_back(RegClassRegs[i]); 4098 4099 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 4100 OpInfo.ConstraintVT); 4101 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4102 return; 4103 } 4104 } 4105 4106 // Otherwise, we couldn't allocate enough registers for this. 4107} 4108 4109 4110/// visitInlineAsm - Handle a call to an InlineAsm object. 4111/// 4112void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 4113 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 4114 4115 /// ConstraintOperands - Information about all of the constraints. 4116 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 4117 4118 SDValue Chain = getRoot(); 4119 SDValue Flag; 4120 4121 std::set<unsigned> OutputRegs, InputRegs; 4122 4123 // Do a prepass over the constraints, canonicalizing them, and building up the 4124 // ConstraintOperands list. 4125 std::vector<InlineAsm::ConstraintInfo> 4126 ConstraintInfos = IA->ParseConstraints(); 4127 4128 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 4129 // constraint. If so, we can't let the register allocator allocate any input 4130 // registers, because it will not know to avoid the earlyclobbered output reg. 4131 bool SawEarlyClobber = false; 4132 4133 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 4134 unsigned ResNo = 0; // ResNo - The result number of the next output. 4135 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 4136 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 4137 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 4138 4139 MVT OpVT = MVT::Other; 4140 4141 // Compute the value type for each operand. 4142 switch (OpInfo.Type) { 4143 case InlineAsm::isOutput: 4144 // Indirect outputs just consume an argument. 4145 if (OpInfo.isIndirect) { 4146 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4147 break; 4148 } 4149 // The return value of the call is this value. As such, there is no 4150 // corresponding argument. 4151 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4152 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 4153 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 4154 } else { 4155 assert(ResNo == 0 && "Asm only has one result!"); 4156 OpVT = TLI.getValueType(CS.getType()); 4157 } 4158 ++ResNo; 4159 break; 4160 case InlineAsm::isInput: 4161 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4162 break; 4163 case InlineAsm::isClobber: 4164 // Nothing to do. 4165 break; 4166 } 4167 4168 // If this is an input or an indirect output, process the call argument. 4169 // BasicBlocks are labels, currently appearing only in asm's. 4170 if (OpInfo.CallOperandVal) { 4171 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) 4172 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 4173 else { 4174 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 4175 const Type *OpTy = OpInfo.CallOperandVal->getType(); 4176 // If this is an indirect operand, the operand is a pointer to the 4177 // accessed type. 4178 if (OpInfo.isIndirect) 4179 OpTy = cast<PointerType>(OpTy)->getElementType(); 4180 4181 // If OpTy is not a single value, it may be a struct/union that we 4182 // can tile with integers. 4183 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4184 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4185 switch (BitSize) { 4186 default: break; 4187 case 1: 4188 case 8: 4189 case 16: 4190 case 32: 4191 case 64: 4192 OpTy = IntegerType::get(BitSize); 4193 break; 4194 } 4195 } 4196 4197 OpVT = TLI.getValueType(OpTy, true); 4198 } 4199 } 4200 4201 OpInfo.ConstraintVT = OpVT; 4202 4203 // Compute the constraint code and ConstraintType to use. 4204 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 4205 4206 // Keep track of whether we see an earlyclobber. 4207 SawEarlyClobber |= OpInfo.isEarlyClobber; 4208 4209 // If we see a clobber of a register, it is an early clobber. 4210 if (!SawEarlyClobber && 4211 OpInfo.Type == InlineAsm::isClobber && 4212 OpInfo.ConstraintType == TargetLowering::C_Register) { 4213 // Note that we want to ignore things that we don't trick here, like 4214 // dirflag, fpsr, flags, etc. 4215 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 4216 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 4217 OpInfo.ConstraintVT); 4218 if (PhysReg.first || PhysReg.second) { 4219 // This is a register we know of. 4220 SawEarlyClobber = true; 4221 } 4222 } 4223 4224 // If this is a memory input, and if the operand is not indirect, do what we 4225 // need to to provide an address for the memory input. 4226 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 4227 !OpInfo.isIndirect) { 4228 assert(OpInfo.Type == InlineAsm::isInput && 4229 "Can only indirectify direct input operands!"); 4230 4231 // Memory operands really want the address of the value. If we don't have 4232 // an indirect input, put it in the constpool if we can, otherwise spill 4233 // it to a stack slot. 4234 4235 // If the operand is a float, integer, or vector constant, spill to a 4236 // constant pool entry to get its address. 4237 Value *OpVal = OpInfo.CallOperandVal; 4238 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 4239 isa<ConstantVector>(OpVal)) { 4240 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 4241 TLI.getPointerTy()); 4242 } else { 4243 // Otherwise, create a stack slot and emit a store to it before the 4244 // asm. 4245 const Type *Ty = OpVal->getType(); 4246 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 4247 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 4248 MachineFunction &MF = DAG.getMachineFunction(); 4249 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 4250 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4251 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 4252 OpInfo.CallOperand = StackSlot; 4253 } 4254 4255 // There is no longer a Value* corresponding to this operand. 4256 OpInfo.CallOperandVal = 0; 4257 // It is now an indirect operand. 4258 OpInfo.isIndirect = true; 4259 } 4260 4261 // If this constraint is for a specific register, allocate it before 4262 // anything else. 4263 if (OpInfo.ConstraintType == TargetLowering::C_Register) 4264 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4265 } 4266 ConstraintInfos.clear(); 4267 4268 4269 // Second pass - Loop over all of the operands, assigning virtual or physregs 4270 // to registerclass operands. 4271 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4272 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4273 4274 // C_Register operands have already been allocated, Other/Memory don't need 4275 // to be. 4276 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 4277 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4278 } 4279 4280 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 4281 std::vector<SDValue> AsmNodeOperands; 4282 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 4283 AsmNodeOperands.push_back( 4284 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 4285 4286 4287 // Loop over all of the inputs, copying the operand values into the 4288 // appropriate registers and processing the output regs. 4289 RegsForValue RetValRegs; 4290 4291 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 4292 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 4293 4294 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4295 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4296 4297 switch (OpInfo.Type) { 4298 case InlineAsm::isOutput: { 4299 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 4300 OpInfo.ConstraintType != TargetLowering::C_Register) { 4301 // Memory output, or 'other' output (e.g. 'X' constraint). 4302 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 4303 4304 // Add information to the INLINEASM node to know about this output. 4305 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4306 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4307 TLI.getPointerTy())); 4308 AsmNodeOperands.push_back(OpInfo.CallOperand); 4309 break; 4310 } 4311 4312 // Otherwise, this is a register or register class output. 4313 4314 // Copy the output from the appropriate register. Find a register that 4315 // we can use. 4316 if (OpInfo.AssignedRegs.Regs.empty()) { 4317 cerr << "Couldn't allocate output reg for constraint '" 4318 << OpInfo.ConstraintCode << "'!\n"; 4319 exit(1); 4320 } 4321 4322 // If this is an indirect operand, store through the pointer after the 4323 // asm. 4324 if (OpInfo.isIndirect) { 4325 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 4326 OpInfo.CallOperandVal)); 4327 } else { 4328 // This is the result value of the call. 4329 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4330 // Concatenate this output onto the outputs list. 4331 RetValRegs.append(OpInfo.AssignedRegs); 4332 } 4333 4334 // Add information to the INLINEASM node to know that this register is 4335 // set. 4336 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 4337 AsmNodeOperands); 4338 break; 4339 } 4340 case InlineAsm::isInput: { 4341 SDValue InOperandVal = OpInfo.CallOperand; 4342 4343 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 4344 // If this is required to match an output register we have already set, 4345 // just use its register. 4346 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 4347 4348 // Scan until we find the definition we already emitted of this operand. 4349 // When we find it, create a RegsForValue operand. 4350 unsigned CurOp = 2; // The first operand. 4351 for (; OperandNo; --OperandNo) { 4352 // Advance to the next operand. 4353 unsigned NumOps = 4354 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4355 assert(((NumOps & 7) == 2 /*REGDEF*/ || 4356 (NumOps & 7) == 4 /*MEM*/) && 4357 "Skipped past definitions?"); 4358 CurOp += (NumOps>>3)+1; 4359 } 4360 4361 unsigned NumOps = 4362 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4363 if ((NumOps & 7) == 2 /*REGDEF*/) { 4364 // Add NumOps>>3 registers to MatchedRegs. 4365 RegsForValue MatchedRegs; 4366 MatchedRegs.TLI = &TLI; 4367 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 4368 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType()); 4369 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 4370 unsigned Reg = 4371 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 4372 MatchedRegs.Regs.push_back(Reg); 4373 } 4374 4375 // Use the produced MatchedRegs object to 4376 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4377 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 4378 break; 4379 } else { 4380 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 4381 assert((NumOps >> 3) == 1 && "Unexpected number of operands"); 4382 // Add information to the INLINEASM node to know about this input. 4383 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4384 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4385 TLI.getPointerTy())); 4386 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 4387 break; 4388 } 4389 } 4390 4391 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 4392 assert(!OpInfo.isIndirect && 4393 "Don't know how to handle indirect other inputs yet!"); 4394 4395 std::vector<SDValue> Ops; 4396 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 4397 Ops, DAG); 4398 if (Ops.empty()) { 4399 cerr << "Invalid operand for inline asm constraint '" 4400 << OpInfo.ConstraintCode << "'!\n"; 4401 exit(1); 4402 } 4403 4404 // Add information to the INLINEASM node to know about this input. 4405 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 4406 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4407 TLI.getPointerTy())); 4408 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 4409 break; 4410 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 4411 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 4412 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 4413 "Memory operands expect pointer values"); 4414 4415 // Add information to the INLINEASM node to know about this input. 4416 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4417 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4418 TLI.getPointerTy())); 4419 AsmNodeOperands.push_back(InOperandVal); 4420 break; 4421 } 4422 4423 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 4424 OpInfo.ConstraintType == TargetLowering::C_Register) && 4425 "Unknown constraint type!"); 4426 assert(!OpInfo.isIndirect && 4427 "Don't know how to handle indirect register inputs yet!"); 4428 4429 // Copy the input into the appropriate registers. 4430 assert(!OpInfo.AssignedRegs.Regs.empty() && 4431 "Couldn't allocate input reg!"); 4432 4433 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4434 4435 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 4436 AsmNodeOperands); 4437 break; 4438 } 4439 case InlineAsm::isClobber: { 4440 // Add the clobbered value to the operand list, so that the register 4441 // allocator is aware that the physreg got clobbered. 4442 if (!OpInfo.AssignedRegs.Regs.empty()) 4443 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 4444 AsmNodeOperands); 4445 break; 4446 } 4447 } 4448 } 4449 4450 // Finish up input operands. 4451 AsmNodeOperands[0] = Chain; 4452 if (Flag.Val) AsmNodeOperands.push_back(Flag); 4453 4454 Chain = DAG.getNode(ISD::INLINEASM, 4455 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 4456 &AsmNodeOperands[0], AsmNodeOperands.size()); 4457 Flag = Chain.getValue(1); 4458 4459 // If this asm returns a register value, copy the result from that register 4460 // and set it as the value of the call. 4461 if (!RetValRegs.Regs.empty()) { 4462 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 4463 4464 // If any of the results of the inline asm is a vector, it may have the 4465 // wrong width/num elts. This can happen for register classes that can 4466 // contain multiple different value types. The preg or vreg allocated may 4467 // not have the same VT as was expected. Convert it to the right type with 4468 // bit_convert. 4469 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) { 4470 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) { 4471 if (Val.Val->getValueType(i).isVector()) 4472 Val = DAG.getNode(ISD::BIT_CONVERT, 4473 TLI.getValueType(ResSTy->getElementType(i)), Val); 4474 } 4475 } else { 4476 if (Val.getValueType().isVector()) 4477 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()), 4478 Val); 4479 } 4480 4481 setValue(CS.getInstruction(), Val); 4482 } 4483 4484 std::vector<std::pair<SDValue, Value*> > StoresToEmit; 4485 4486 // Process indirect outputs, first output all of the flagged copies out of 4487 // physregs. 4488 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 4489 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 4490 Value *Ptr = IndirectStoresToEmit[i].second; 4491 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 4492 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 4493 } 4494 4495 // Emit the non-flagged stores from the physregs. 4496 SmallVector<SDValue, 8> OutChains; 4497 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 4498 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 4499 getValue(StoresToEmit[i].second), 4500 StoresToEmit[i].second, 0)); 4501 if (!OutChains.empty()) 4502 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4503 &OutChains[0], OutChains.size()); 4504 DAG.setRoot(Chain); 4505} 4506 4507 4508void SelectionDAGLowering::visitMalloc(MallocInst &I) { 4509 SDValue Src = getValue(I.getOperand(0)); 4510 4511 MVT IntPtr = TLI.getPointerTy(); 4512 4513 if (IntPtr.bitsLT(Src.getValueType())) 4514 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 4515 else if (IntPtr.bitsGT(Src.getValueType())) 4516 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 4517 4518 // Scale the source by the type size. 4519 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 4520 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 4521 Src, DAG.getIntPtrConstant(ElementSize)); 4522 4523 TargetLowering::ArgListTy Args; 4524 TargetLowering::ArgListEntry Entry; 4525 Entry.Node = Src; 4526 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4527 Args.push_back(Entry); 4528 4529 std::pair<SDValue,SDValue> Result = 4530 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C, 4531 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG); 4532 setValue(&I, Result.first); // Pointers always fit in registers 4533 DAG.setRoot(Result.second); 4534} 4535 4536void SelectionDAGLowering::visitFree(FreeInst &I) { 4537 TargetLowering::ArgListTy Args; 4538 TargetLowering::ArgListEntry Entry; 4539 Entry.Node = getValue(I.getOperand(0)); 4540 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4541 Args.push_back(Entry); 4542 MVT IntPtr = TLI.getPointerTy(); 4543 std::pair<SDValue,SDValue> Result = 4544 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, 4545 CallingConv::C, true, 4546 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 4547 DAG.setRoot(Result.second); 4548} 4549 4550// EmitInstrWithCustomInserter - This method should be implemented by targets 4551// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 4552// instructions are special in various ways, which require special support to 4553// insert. The specified MachineInstr is created but not inserted into any 4554// basic blocks, and the scheduler passes ownership of it to this method. 4555MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4556 MachineBasicBlock *MBB) { 4557 cerr << "If a target marks an instruction with " 4558 << "'usesCustomDAGSchedInserter', it must implement " 4559 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 4560 abort(); 4561 return 0; 4562} 4563 4564void SelectionDAGLowering::visitVAStart(CallInst &I) { 4565 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 4566 getValue(I.getOperand(1)), 4567 DAG.getSrcValue(I.getOperand(1)))); 4568} 4569 4570void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 4571 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 4572 getValue(I.getOperand(0)), 4573 DAG.getSrcValue(I.getOperand(0))); 4574 setValue(&I, V); 4575 DAG.setRoot(V.getValue(1)); 4576} 4577 4578void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4579 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4580 getValue(I.getOperand(1)), 4581 DAG.getSrcValue(I.getOperand(1)))); 4582} 4583 4584void SelectionDAGLowering::visitVACopy(CallInst &I) { 4585 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4586 getValue(I.getOperand(1)), 4587 getValue(I.getOperand(2)), 4588 DAG.getSrcValue(I.getOperand(1)), 4589 DAG.getSrcValue(I.getOperand(2)))); 4590} 4591 4592/// TargetLowering::LowerArguments - This is the default LowerArguments 4593/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4594/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4595/// integrated into SDISel. 4596void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, 4597 SmallVectorImpl<SDValue> &ArgValues) { 4598 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4599 SmallVector<SDValue, 3+16> Ops; 4600 Ops.push_back(DAG.getRoot()); 4601 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4602 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4603 4604 // Add one result value for each formal argument. 4605 SmallVector<MVT, 16> RetVals; 4606 unsigned j = 1; 4607 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4608 I != E; ++I, ++j) { 4609 SmallVector<MVT, 4> ValueVTs; 4610 ComputeValueVTs(*this, I->getType(), ValueVTs); 4611 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4612 Value != NumValues; ++Value) { 4613 MVT VT = ValueVTs[Value]; 4614 const Type *ArgTy = VT.getTypeForMVT(); 4615 ISD::ArgFlagsTy Flags; 4616 unsigned OriginalAlignment = 4617 getTargetData()->getABITypeAlignment(ArgTy); 4618 4619 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4620 Flags.setZExt(); 4621 if (F.paramHasAttr(j, ParamAttr::SExt)) 4622 Flags.setSExt(); 4623 if (F.paramHasAttr(j, ParamAttr::InReg)) 4624 Flags.setInReg(); 4625 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4626 Flags.setSRet(); 4627 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4628 Flags.setByVal(); 4629 const PointerType *Ty = cast<PointerType>(I->getType()); 4630 const Type *ElementTy = Ty->getElementType(); 4631 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4632 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4633 // For ByVal, alignment should be passed from FE. BE will guess if 4634 // this info is not there but there are cases it cannot get right. 4635 if (F.getParamAlignment(j)) 4636 FrameAlign = F.getParamAlignment(j); 4637 Flags.setByValAlign(FrameAlign); 4638 Flags.setByValSize(FrameSize); 4639 } 4640 if (F.paramHasAttr(j, ParamAttr::Nest)) 4641 Flags.setNest(); 4642 Flags.setOrigAlign(OriginalAlignment); 4643 4644 MVT RegisterVT = getRegisterType(VT); 4645 unsigned NumRegs = getNumRegisters(VT); 4646 for (unsigned i = 0; i != NumRegs; ++i) { 4647 RetVals.push_back(RegisterVT); 4648 ISD::ArgFlagsTy MyFlags = Flags; 4649 if (NumRegs > 1 && i == 0) 4650 MyFlags.setSplit(); 4651 // if it isn't first piece, alignment must be 1 4652 else if (i > 0) 4653 MyFlags.setOrigAlign(1); 4654 Ops.push_back(DAG.getArgFlags(MyFlags)); 4655 } 4656 } 4657 } 4658 4659 RetVals.push_back(MVT::Other); 4660 4661 // Create the node. 4662 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4663 DAG.getVTList(&RetVals[0], RetVals.size()), 4664 &Ops[0], Ops.size()).Val; 4665 4666 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but 4667 // allows exposing the loads that may be part of the argument access to the 4668 // first DAGCombiner pass. 4669 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG); 4670 4671 // The number of results should match up, except that the lowered one may have 4672 // an extra flag result. 4673 assert((Result->getNumValues() == TmpRes.Val->getNumValues() || 4674 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && 4675 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) 4676 && "Lowering produced unexpected number of results!"); 4677 4678 // The FORMAL_ARGUMENTS node itself is likely no longer needed. 4679 if (Result != TmpRes.Val && Result->use_empty()) { 4680 HandleSDNode Dummy(DAG.getRoot()); 4681 DAG.RemoveDeadNode(Result); 4682 } 4683 4684 Result = TmpRes.Val; 4685 4686 unsigned NumArgRegs = Result->getNumValues() - 1; 4687 DAG.setRoot(SDValue(Result, NumArgRegs)); 4688 4689 // Set up the return result vector. 4690 unsigned i = 0; 4691 unsigned Idx = 1; 4692 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4693 ++I, ++Idx) { 4694 SmallVector<MVT, 4> ValueVTs; 4695 ComputeValueVTs(*this, I->getType(), ValueVTs); 4696 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4697 Value != NumValues; ++Value) { 4698 MVT VT = ValueVTs[Value]; 4699 MVT PartVT = getRegisterType(VT); 4700 4701 unsigned NumParts = getNumRegisters(VT); 4702 SmallVector<SDValue, 4> Parts(NumParts); 4703 for (unsigned j = 0; j != NumParts; ++j) 4704 Parts[j] = SDValue(Result, i++); 4705 4706 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4707 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4708 AssertOp = ISD::AssertSext; 4709 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4710 AssertOp = ISD::AssertZext; 4711 4712 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4713 AssertOp)); 4714 } 4715 } 4716 assert(i == NumArgRegs && "Argument register count mismatch!"); 4717} 4718 4719 4720/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4721/// implementation, which just inserts an ISD::CALL node, which is later custom 4722/// lowered by the target to something concrete. FIXME: When all targets are 4723/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4724std::pair<SDValue, SDValue> 4725TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 4726 bool RetSExt, bool RetZExt, bool isVarArg, 4727 unsigned CallingConv, bool isTailCall, 4728 SDValue Callee, 4729 ArgListTy &Args, SelectionDAG &DAG) { 4730 SmallVector<SDValue, 32> Ops; 4731 Ops.push_back(Chain); // Op#0 - Chain 4732 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4733 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4734 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4735 Ops.push_back(Callee); 4736 4737 // Handle all of the outgoing arguments. 4738 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4739 SmallVector<MVT, 4> ValueVTs; 4740 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 4741 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4742 Value != NumValues; ++Value) { 4743 MVT VT = ValueVTs[Value]; 4744 const Type *ArgTy = VT.getTypeForMVT(); 4745 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value); 4746 ISD::ArgFlagsTy Flags; 4747 unsigned OriginalAlignment = 4748 getTargetData()->getABITypeAlignment(ArgTy); 4749 4750 if (Args[i].isZExt) 4751 Flags.setZExt(); 4752 if (Args[i].isSExt) 4753 Flags.setSExt(); 4754 if (Args[i].isInReg) 4755 Flags.setInReg(); 4756 if (Args[i].isSRet) 4757 Flags.setSRet(); 4758 if (Args[i].isByVal) { 4759 Flags.setByVal(); 4760 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4761 const Type *ElementTy = Ty->getElementType(); 4762 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4763 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4764 // For ByVal, alignment should come from FE. BE will guess if this 4765 // info is not there but there are cases it cannot get right. 4766 if (Args[i].Alignment) 4767 FrameAlign = Args[i].Alignment; 4768 Flags.setByValAlign(FrameAlign); 4769 Flags.setByValSize(FrameSize); 4770 } 4771 if (Args[i].isNest) 4772 Flags.setNest(); 4773 Flags.setOrigAlign(OriginalAlignment); 4774 4775 MVT PartVT = getRegisterType(VT); 4776 unsigned NumParts = getNumRegisters(VT); 4777 SmallVector<SDValue, 4> Parts(NumParts); 4778 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4779 4780 if (Args[i].isSExt) 4781 ExtendKind = ISD::SIGN_EXTEND; 4782 else if (Args[i].isZExt) 4783 ExtendKind = ISD::ZERO_EXTEND; 4784 4785 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4786 4787 for (unsigned i = 0; i != NumParts; ++i) { 4788 // if it isn't first piece, alignment must be 1 4789 ISD::ArgFlagsTy MyFlags = Flags; 4790 if (NumParts > 1 && i == 0) 4791 MyFlags.setSplit(); 4792 else if (i != 0) 4793 MyFlags.setOrigAlign(1); 4794 4795 Ops.push_back(Parts[i]); 4796 Ops.push_back(DAG.getArgFlags(MyFlags)); 4797 } 4798 } 4799 } 4800 4801 // Figure out the result value types. We start by making a list of 4802 // the potentially illegal return value types. 4803 SmallVector<MVT, 4> LoweredRetTys; 4804 SmallVector<MVT, 4> RetTys; 4805 ComputeValueVTs(*this, RetTy, RetTys); 4806 4807 // Then we translate that to a list of legal types. 4808 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4809 MVT VT = RetTys[I]; 4810 MVT RegisterVT = getRegisterType(VT); 4811 unsigned NumRegs = getNumRegisters(VT); 4812 for (unsigned i = 0; i != NumRegs; ++i) 4813 LoweredRetTys.push_back(RegisterVT); 4814 } 4815 4816 LoweredRetTys.push_back(MVT::Other); // Always has a chain. 4817 4818 // Create the CALL node. 4819 SDValue Res = DAG.getNode(ISD::CALL, 4820 DAG.getVTList(&LoweredRetTys[0], 4821 LoweredRetTys.size()), 4822 &Ops[0], Ops.size()); 4823 Chain = Res.getValue(LoweredRetTys.size() - 1); 4824 4825 // Gather up the call result into a single value. 4826 if (RetTy != Type::VoidTy) { 4827 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4828 4829 if (RetSExt) 4830 AssertOp = ISD::AssertSext; 4831 else if (RetZExt) 4832 AssertOp = ISD::AssertZext; 4833 4834 SmallVector<SDValue, 4> ReturnValues; 4835 unsigned RegNo = 0; 4836 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4837 MVT VT = RetTys[I]; 4838 MVT RegisterVT = getRegisterType(VT); 4839 unsigned NumRegs = getNumRegisters(VT); 4840 unsigned RegNoEnd = NumRegs + RegNo; 4841 SmallVector<SDValue, 4> Results; 4842 for (; RegNo != RegNoEnd; ++RegNo) 4843 Results.push_back(Res.getValue(RegNo)); 4844 SDValue ReturnValue = 4845 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, 4846 AssertOp); 4847 ReturnValues.push_back(ReturnValue); 4848 } 4849 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()), 4850 &ReturnValues[0], ReturnValues.size()); 4851 } 4852 4853 return std::make_pair(Res, Chain); 4854} 4855 4856SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 4857 assert(0 && "LowerOperation not implemented for this target!"); 4858 abort(); 4859 return SDValue(); 4860} 4861 4862 4863//===----------------------------------------------------------------------===// 4864// SelectionDAGISel code 4865//===----------------------------------------------------------------------===// 4866 4867unsigned SelectionDAGISel::MakeReg(MVT VT) { 4868 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4869} 4870 4871void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4872 AU.addRequired<AliasAnalysis>(); 4873 AU.addRequired<CollectorModuleMetadata>(); 4874 AU.setPreservesAll(); 4875} 4876 4877bool SelectionDAGISel::runOnFunction(Function &Fn) { 4878 // Get alias analysis for load/store combining. 4879 AA = &getAnalysis<AliasAnalysis>(); 4880 4881 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4882 if (MF.getFunction()->hasCollector()) 4883 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4884 else 4885 GCI = 0; 4886 RegInfo = &MF.getRegInfo(); 4887 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4888 4889 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4890 4891 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4892 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4893 // Mark landing pad. 4894 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4895 4896 SelectAllBasicBlocks(Fn, MF, FuncInfo); 4897 4898 // Add function live-ins to entry block live-in set. 4899 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4900 BB = FuncInfo.MBBMap[EntryBB]; 4901 if (!RegInfo->livein_empty()) 4902 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4903 E = RegInfo->livein_end(); I != E; ++I) 4904 BB->addLiveIn(I->first); 4905 4906#ifndef NDEBUG 4907 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4908 "Not all catch info was assigned to a landing pad!"); 4909#endif 4910 4911 return true; 4912} 4913 4914void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) { 4915 SDValue Op = getValue(V); 4916 assert((Op.getOpcode() != ISD::CopyFromReg || 4917 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4918 "Copy from a reg to the same reg!"); 4919 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 4920 4921 RegsForValue RFV(TLI, Reg, V->getType()); 4922 SDValue Chain = DAG.getEntryNode(); 4923 RFV.getCopyToRegs(Op, DAG, Chain, 0); 4924 PendingExports.push_back(Chain); 4925} 4926 4927void SelectionDAGISel:: 4928LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { 4929 // If this is the entry block, emit arguments. 4930 Function &F = *LLVMBB->getParent(); 4931 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4932 SDValue OldRoot = SDL.DAG.getRoot(); 4933 SmallVector<SDValue, 16> Args; 4934 TLI.LowerArguments(F, SDL.DAG, Args); 4935 4936 unsigned a = 0; 4937 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4938 AI != E; ++AI) { 4939 SmallVector<MVT, 4> ValueVTs; 4940 ComputeValueVTs(TLI, AI->getType(), ValueVTs); 4941 unsigned NumValues = ValueVTs.size(); 4942 if (!AI->use_empty()) { 4943 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues)); 4944 // If this argument is live outside of the entry block, insert a copy from 4945 // whereever we got it to the vreg that other BB's will reference it as. 4946 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4947 if (VMI != FuncInfo.ValueMap.end()) { 4948 SDL.CopyValueToVirtualRegister(AI, VMI->second); 4949 } 4950 } 4951 a += NumValues; 4952 } 4953 4954 // Finally, if the target has anything special to do, allow it to do so. 4955 // FIXME: this should insert code into the DAG! 4956 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4957} 4958 4959static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4960 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4961 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4962 if (isSelector(I)) { 4963 // Apply the catch info to DestBB. 4964 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4965#ifndef NDEBUG 4966 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4967 FLI.CatchInfoFound.insert(I); 4968#endif 4969 } 4970} 4971 4972/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 4973/// whether object offset >= 0. 4974static bool 4975IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 4976 if (!isa<FrameIndexSDNode>(Op)) return false; 4977 4978 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 4979 int FrameIdx = FrameIdxNode->getIndex(); 4980 return MFI->isFixedObjectIndex(FrameIdx) && 4981 MFI->getObjectOffset(FrameIdx) >= 0; 4982} 4983 4984/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 4985/// possibly be overwritten when lowering the outgoing arguments in a tail 4986/// call. Currently the implementation of this call is very conservative and 4987/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 4988/// virtual registers would be overwritten by direct lowering. 4989static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 4990 MachineFrameInfo * MFI) { 4991 RegisterSDNode * OpReg = NULL; 4992 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 4993 (Op.getOpcode()== ISD::CopyFromReg && 4994 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 4995 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 4996 (Op.getOpcode() == ISD::LOAD && 4997 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 4998 (Op.getOpcode() == ISD::MERGE_VALUES && 4999 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD && 5000 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo). 5001 getOperand(1)))) 5002 return true; 5003 return false; 5004} 5005 5006/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 5007/// DAG and fixes their tailcall attribute operand. 5008static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 5009 TargetLowering& TLI) { 5010 SDNode * Ret = NULL; 5011 SDValue Terminator = DAG.getRoot(); 5012 5013 // Find RET node. 5014 if (Terminator.getOpcode() == ISD::RET) { 5015 Ret = Terminator.Val; 5016 } 5017 5018 // Fix tail call attribute of CALL nodes. 5019 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 5020 BI = DAG.allnodes_end(); BI != BE; ) { 5021 --BI; 5022 if (BI->getOpcode() == ISD::CALL) { 5023 SDValue OpRet(Ret, 0); 5024 SDValue OpCall(BI, 0); 5025 bool isMarkedTailCall = 5026 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 5027 // If CALL node has tail call attribute set to true and the call is not 5028 // eligible (no RET or the target rejects) the attribute is fixed to 5029 // false. The TargetLowering::IsEligibleForTailCallOptimization function 5030 // must correctly identify tail call optimizable calls. 5031 if (!isMarkedTailCall) continue; 5032 if (Ret==NULL || 5033 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) { 5034 // Not eligible. Mark CALL node as non tail call. 5035 SmallVector<SDValue, 32> Ops; 5036 unsigned idx=0; 5037 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 5038 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5039 if (idx!=3) 5040 Ops.push_back(*I); 5041 else 5042 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 5043 } 5044 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5045 } else { 5046 // Look for tail call clobbered arguments. Emit a series of 5047 // copyto/copyfrom virtual register nodes to protect them. 5048 SmallVector<SDValue, 32> Ops; 5049 SDValue Chain = OpCall.getOperand(0), InFlag; 5050 unsigned idx=0; 5051 for(SDNode::op_iterator I = OpCall.Val->op_begin(), 5052 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5053 SDValue Arg = *I; 5054 if (idx > 4 && (idx % 2)) { 5055 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))-> 5056 getArgFlags().isByVal(); 5057 MachineFunction &MF = DAG.getMachineFunction(); 5058 MachineFrameInfo *MFI = MF.getFrameInfo(); 5059 if (!isByVal && 5060 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 5061 MVT VT = Arg.getValueType(); 5062 unsigned VReg = MF.getRegInfo(). 5063 createVirtualRegister(TLI.getRegClassFor(VT)); 5064 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 5065 InFlag = Chain.getValue(1); 5066 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 5067 Chain = Arg.getValue(1); 5068 InFlag = Arg.getValue(2); 5069 } 5070 } 5071 Ops.push_back(Arg); 5072 } 5073 // Link in chain of CopyTo/CopyFromReg. 5074 Ops[0] = Chain; 5075 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5076 } 5077 } 5078 } 5079} 5080 5081void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 5082 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 5083 FunctionLoweringInfo &FuncInfo) { 5084 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 5085 5086 // Lower any arguments needed in this block if this is the entry block. 5087 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 5088 LowerArguments(LLVMBB, SDL); 5089 5090 BB = FuncInfo.MBBMap[LLVMBB]; 5091 SDL.setCurrentBasicBlock(BB); 5092 5093 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 5094 5095 if (MMI && BB->isLandingPad()) { 5096 // Add a label to mark the beginning of the landing pad. Deletion of the 5097 // landing pad can thus be detected via the MachineModuleInfo. 5098 unsigned LabelID = MMI->addLandingPad(BB); 5099 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID)); 5100 5101 // Mark exception register as live in. 5102 unsigned Reg = TLI.getExceptionAddressRegister(); 5103 if (Reg) BB->addLiveIn(Reg); 5104 5105 // Mark exception selector register as live in. 5106 Reg = TLI.getExceptionSelectorRegister(); 5107 if (Reg) BB->addLiveIn(Reg); 5108 5109 // FIXME: Hack around an exception handling flaw (PR1508): the personality 5110 // function and list of typeids logically belong to the invoke (or, if you 5111 // like, the basic block containing the invoke), and need to be associated 5112 // with it in the dwarf exception handling tables. Currently however the 5113 // information is provided by an intrinsic (eh.selector) that can be moved 5114 // to unexpected places by the optimizers: if the unwind edge is critical, 5115 // then breaking it can result in the intrinsics being in the successor of 5116 // the landing pad, not the landing pad itself. This results in exceptions 5117 // not being caught because no typeids are associated with the invoke. 5118 // This may not be the only way things can go wrong, but it is the only way 5119 // we try to work around for the moment. 5120 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 5121 5122 if (Br && Br->isUnconditional()) { // Critical edge? 5123 BasicBlock::iterator I, E; 5124 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 5125 if (isSelector(I)) 5126 break; 5127 5128 if (I == E) 5129 // No catch info found - try to extract some from the successor. 5130 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 5131 } 5132 } 5133 5134 // Lower all of the non-terminator instructions. 5135 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 5136 I != E; ++I) 5137 SDL.visit(*I); 5138 5139 // Ensure that all instructions which are used outside of their defining 5140 // blocks are available as virtual registers. Invoke is handled elsewhere. 5141 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 5142 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 5143 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 5144 if (VMI != FuncInfo.ValueMap.end()) 5145 SDL.CopyValueToVirtualRegister(I, VMI->second); 5146 } 5147 5148 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 5149 // ensure constants are generated when needed. Remember the virtual registers 5150 // that need to be added to the Machine PHI nodes as input. We cannot just 5151 // directly add them, because expansion might result in multiple MBB's for one 5152 // BB. As such, the start of the BB might correspond to a different MBB than 5153 // the end. 5154 // 5155 TerminatorInst *TI = LLVMBB->getTerminator(); 5156 5157 // Emit constants only once even if used by multiple PHI nodes. 5158 std::map<Constant*, unsigned> ConstantsOut; 5159 5160 // Vector bool would be better, but vector<bool> is really slow. 5161 std::vector<unsigned char> SuccsHandled; 5162 if (TI->getNumSuccessors()) 5163 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 5164 5165 // Check successor nodes' PHI nodes that expect a constant to be available 5166 // from this block. 5167 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 5168 BasicBlock *SuccBB = TI->getSuccessor(succ); 5169 if (!isa<PHINode>(SuccBB->begin())) continue; 5170 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 5171 5172 // If this terminator has multiple identical successors (common for 5173 // switches), only handle each succ once. 5174 unsigned SuccMBBNo = SuccMBB->getNumber(); 5175 if (SuccsHandled[SuccMBBNo]) continue; 5176 SuccsHandled[SuccMBBNo] = true; 5177 5178 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 5179 PHINode *PN; 5180 5181 // At this point we know that there is a 1-1 correspondence between LLVM PHI 5182 // nodes and Machine PHI nodes, but the incoming operands have not been 5183 // emitted yet. 5184 for (BasicBlock::iterator I = SuccBB->begin(); 5185 (PN = dyn_cast<PHINode>(I)); ++I) { 5186 // Ignore dead phi's. 5187 if (PN->use_empty()) continue; 5188 5189 unsigned Reg; 5190 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 5191 5192 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 5193 unsigned &RegOut = ConstantsOut[C]; 5194 if (RegOut == 0) { 5195 RegOut = FuncInfo.CreateRegForValue(C); 5196 SDL.CopyValueToVirtualRegister(C, RegOut); 5197 } 5198 Reg = RegOut; 5199 } else { 5200 Reg = FuncInfo.ValueMap[PHIOp]; 5201 if (Reg == 0) { 5202 assert(isa<AllocaInst>(PHIOp) && 5203 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 5204 "Didn't codegen value into a register!??"); 5205 Reg = FuncInfo.CreateRegForValue(PHIOp); 5206 SDL.CopyValueToVirtualRegister(PHIOp, Reg); 5207 } 5208 } 5209 5210 // Remember that this register needs to added to the machine PHI node as 5211 // the input for this MBB. 5212 MVT VT = TLI.getValueType(PN->getType()); 5213 unsigned NumRegisters = TLI.getNumRegisters(VT); 5214 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 5215 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 5216 } 5217 } 5218 ConstantsOut.clear(); 5219 5220 // Lower the terminator after the copies are emitted. 5221 SDL.visit(*LLVMBB->getTerminator()); 5222 5223 // Copy over any CaseBlock records that may now exist due to SwitchInst 5224 // lowering, as well as any jump table information. 5225 SwitchCases.clear(); 5226 SwitchCases = SDL.SwitchCases; 5227 JTCases.clear(); 5228 JTCases = SDL.JTCases; 5229 BitTestCases.clear(); 5230 BitTestCases = SDL.BitTestCases; 5231 5232 // Make sure the root of the DAG is up-to-date. 5233 DAG.setRoot(SDL.getControlRoot()); 5234 5235 // Check whether calls in this block are real tail calls. Fix up CALL nodes 5236 // with correct tailcall attribute so that the target can rely on the tailcall 5237 // attribute indicating whether the call is really eligible for tail call 5238 // optimization. 5239 CheckDAGForTailCallsAndFixThem(DAG, TLI); 5240} 5241 5242void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { 5243 SmallPtrSet<SDNode*, 128> VisitedNodes; 5244 SmallVector<SDNode*, 128> Worklist; 5245 5246 Worklist.push_back(DAG.getRoot().Val); 5247 5248 APInt Mask; 5249 APInt KnownZero; 5250 APInt KnownOne; 5251 5252 while (!Worklist.empty()) { 5253 SDNode *N = Worklist.back(); 5254 Worklist.pop_back(); 5255 5256 // If we've already seen this node, ignore it. 5257 if (!VisitedNodes.insert(N)) 5258 continue; 5259 5260 // Otherwise, add all chain operands to the worklist. 5261 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5262 if (N->getOperand(i).getValueType() == MVT::Other) 5263 Worklist.push_back(N->getOperand(i).Val); 5264 5265 // If this is a CopyToReg with a vreg dest, process it. 5266 if (N->getOpcode() != ISD::CopyToReg) 5267 continue; 5268 5269 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 5270 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 5271 continue; 5272 5273 // Ignore non-scalar or non-integer values. 5274 SDValue Src = N->getOperand(2); 5275 MVT SrcVT = Src.getValueType(); 5276 if (!SrcVT.isInteger() || SrcVT.isVector()) 5277 continue; 5278 5279 unsigned NumSignBits = DAG.ComputeNumSignBits(Src); 5280 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 5281 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 5282 5283 // Only install this information if it tells us something. 5284 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 5285 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 5286 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5287 if (DestReg >= FLI.LiveOutRegInfo.size()) 5288 FLI.LiveOutRegInfo.resize(DestReg+1); 5289 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 5290 LOI.NumSignBits = NumSignBits; 5291 LOI.KnownOne = NumSignBits; 5292 LOI.KnownZero = NumSignBits; 5293 } 5294 } 5295} 5296 5297void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 5298 std::string GroupName; 5299 if (TimePassesIsEnabled) 5300 GroupName = "Instruction Selection and Scheduling"; 5301 std::string BlockName; 5302 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 5303 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 5304 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' + 5305 BB->getBasicBlock()->getName(); 5306 5307 DOUT << "Initial selection DAG:\n"; 5308 DEBUG(DAG.dump()); 5309 5310 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName); 5311 5312 // Run the DAG combiner in pre-legalize mode. 5313 if (TimePassesIsEnabled) { 5314 NamedRegionTimer T("DAG Combining 1", GroupName); 5315 DAG.Combine(false, *AA); 5316 } else { 5317 DAG.Combine(false, *AA); 5318 } 5319 5320 DOUT << "Optimized lowered selection DAG:\n"; 5321 DEBUG(DAG.dump()); 5322 5323 // Second step, hack on the DAG until it only uses operations and types that 5324 // the target supports. 5325 if (EnableLegalizeTypes) {// Enable this some day. 5326 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " + 5327 BlockName); 5328 5329 if (TimePassesIsEnabled) { 5330 NamedRegionTimer T("Type Legalization", GroupName); 5331 DAG.LegalizeTypes(); 5332 } else { 5333 DAG.LegalizeTypes(); 5334 } 5335 5336 DOUT << "Type-legalized selection DAG:\n"; 5337 DEBUG(DAG.dump()); 5338 5339 // TODO: enable a dag combine pass here. 5340 } 5341 5342 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName); 5343 5344 if (TimePassesIsEnabled) { 5345 NamedRegionTimer T("DAG Legalization", GroupName); 5346 DAG.Legalize(); 5347 } else { 5348 DAG.Legalize(); 5349 } 5350 5351 DOUT << "Legalized selection DAG:\n"; 5352 DEBUG(DAG.dump()); 5353 5354 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName); 5355 5356 // Run the DAG combiner in post-legalize mode. 5357 if (TimePassesIsEnabled) { 5358 NamedRegionTimer T("DAG Combining 2", GroupName); 5359 DAG.Combine(true, *AA); 5360 } else { 5361 DAG.Combine(true, *AA); 5362 } 5363 5364 DOUT << "Optimized legalized selection DAG:\n"; 5365 DEBUG(DAG.dump()); 5366 5367 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName); 5368 5369 if (!FastISel && EnableValueProp) 5370 ComputeLiveOutVRegInfo(DAG); 5371 5372 // Third, instruction select all of the operations to machine code, adding the 5373 // code to the MachineBasicBlock. 5374 if (TimePassesIsEnabled) { 5375 NamedRegionTimer T("Instruction Selection", GroupName); 5376 InstructionSelect(DAG); 5377 } else { 5378 InstructionSelect(DAG); 5379 } 5380 5381 DOUT << "Selected selection DAG:\n"; 5382 DEBUG(DAG.dump()); 5383 5384 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName); 5385 5386 // Schedule machine code. 5387 ScheduleDAG *Scheduler; 5388 if (TimePassesIsEnabled) { 5389 NamedRegionTimer T("Instruction Scheduling", GroupName); 5390 Scheduler = Schedule(DAG); 5391 } else { 5392 Scheduler = Schedule(DAG); 5393 } 5394 5395 if (ViewSUnitDAGs) Scheduler->viewGraph(); 5396 5397 // Emit machine code to BB. This can change 'BB' to the last block being 5398 // inserted into. 5399 if (TimePassesIsEnabled) { 5400 NamedRegionTimer T("Instruction Creation", GroupName); 5401 BB = Scheduler->EmitSchedule(); 5402 } else { 5403 BB = Scheduler->EmitSchedule(); 5404 } 5405 5406 // Free the scheduler state. 5407 if (TimePassesIsEnabled) { 5408 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 5409 delete Scheduler; 5410 } else { 5411 delete Scheduler; 5412 } 5413 5414 // Perform target specific isel post processing. 5415 if (TimePassesIsEnabled) { 5416 NamedRegionTimer T("Instruction Selection Post Processing", GroupName); 5417 InstructionSelectPostProcessing(); 5418 } else { 5419 InstructionSelectPostProcessing(); 5420 } 5421 5422 DOUT << "Selected machine code:\n"; 5423 DEBUG(BB->dump()); 5424} 5425 5426void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 5427 FunctionLoweringInfo &FuncInfo) { 5428 // Define AllNodes here so that memory allocation is reused for 5429 // each basic block. 5430 alist<SDNode, LargestSDNode> AllNodes; 5431 5432 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 5433 SelectBasicBlock(I, MF, FuncInfo, AllNodes); 5434 AllNodes.clear(); 5435 } 5436} 5437 5438void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 5439 FunctionLoweringInfo &FuncInfo, 5440 alist<SDNode, LargestSDNode> &AllNodes) { 5441 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 5442 { 5443 SelectionDAG DAG(TLI, MF, FuncInfo, 5444 getAnalysisToUpdate<MachineModuleInfo>(), 5445 AllNodes); 5446 CurDAG = &DAG; 5447 5448 // First step, lower LLVM code to some DAG. This DAG may use operations and 5449 // types that are not supported by the target. 5450 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 5451 5452 // Second step, emit the lowered DAG as machine code. 5453 CodeGenAndEmitDAG(DAG); 5454 } 5455 5456 DOUT << "Total amount of phi nodes to update: " 5457 << PHINodesToUpdate.size() << "\n"; 5458 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 5459 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 5460 << ", " << PHINodesToUpdate[i].second << ")\n";); 5461 5462 // Next, now that we know what the last MBB the LLVM BB expanded is, update 5463 // PHI nodes in successors. 5464 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 5465 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5466 MachineInstr *PHI = PHINodesToUpdate[i].first; 5467 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5468 "This is not a machine PHI node that we are updating!"); 5469 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5470 false)); 5471 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5472 } 5473 return; 5474 } 5475 5476 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 5477 // Lower header first, if it wasn't already lowered 5478 if (!BitTestCases[i].Emitted) { 5479 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5480 getAnalysisToUpdate<MachineModuleInfo>(), 5481 AllNodes); 5482 CurDAG = &HSDAG; 5483 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5484 // Set the current basic block to the mbb we wish to insert the code into 5485 BB = BitTestCases[i].Parent; 5486 HSDL.setCurrentBasicBlock(BB); 5487 // Emit the code 5488 HSDL.visitBitTestHeader(BitTestCases[i]); 5489 HSDAG.setRoot(HSDL.getRoot()); 5490 CodeGenAndEmitDAG(HSDAG); 5491 } 5492 5493 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5494 SelectionDAG BSDAG(TLI, MF, FuncInfo, 5495 getAnalysisToUpdate<MachineModuleInfo>(), 5496 AllNodes); 5497 CurDAG = &BSDAG; 5498 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 5499 // Set the current basic block to the mbb we wish to insert the code into 5500 BB = BitTestCases[i].Cases[j].ThisBB; 5501 BSDL.setCurrentBasicBlock(BB); 5502 // Emit the code 5503 if (j+1 != ej) 5504 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 5505 BitTestCases[i].Reg, 5506 BitTestCases[i].Cases[j]); 5507 else 5508 BSDL.visitBitTestCase(BitTestCases[i].Default, 5509 BitTestCases[i].Reg, 5510 BitTestCases[i].Cases[j]); 5511 5512 5513 BSDAG.setRoot(BSDL.getRoot()); 5514 CodeGenAndEmitDAG(BSDAG); 5515 } 5516 5517 // Update PHI Nodes 5518 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5519 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5520 MachineBasicBlock *PHIBB = PHI->getParent(); 5521 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5522 "This is not a machine PHI node that we are updating!"); 5523 // This is "default" BB. We have two jumps to it. From "header" BB and 5524 // from last "case" BB. 5525 if (PHIBB == BitTestCases[i].Default) { 5526 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5527 false)); 5528 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 5529 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5530 false)); 5531 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 5532 back().ThisBB)); 5533 } 5534 // One of "cases" BB. 5535 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5536 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 5537 if (cBB->succ_end() != 5538 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 5539 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5540 false)); 5541 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 5542 } 5543 } 5544 } 5545 } 5546 5547 // If the JumpTable record is filled in, then we need to emit a jump table. 5548 // Updating the PHI nodes is tricky in this case, since we need to determine 5549 // whether the PHI is a successor of the range check MBB or the jump table MBB 5550 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 5551 // Lower header first, if it wasn't already lowered 5552 if (!JTCases[i].first.Emitted) { 5553 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5554 getAnalysisToUpdate<MachineModuleInfo>(), 5555 AllNodes); 5556 CurDAG = &HSDAG; 5557 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5558 // Set the current basic block to the mbb we wish to insert the code into 5559 BB = JTCases[i].first.HeaderBB; 5560 HSDL.setCurrentBasicBlock(BB); 5561 // Emit the code 5562 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 5563 HSDAG.setRoot(HSDL.getRoot()); 5564 CodeGenAndEmitDAG(HSDAG); 5565 } 5566 5567 SelectionDAG JSDAG(TLI, MF, FuncInfo, 5568 getAnalysisToUpdate<MachineModuleInfo>(), 5569 AllNodes); 5570 CurDAG = &JSDAG; 5571 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 5572 // Set the current basic block to the mbb we wish to insert the code into 5573 BB = JTCases[i].second.MBB; 5574 JSDL.setCurrentBasicBlock(BB); 5575 // Emit the code 5576 JSDL.visitJumpTable(JTCases[i].second); 5577 JSDAG.setRoot(JSDL.getRoot()); 5578 CodeGenAndEmitDAG(JSDAG); 5579 5580 // Update PHI Nodes 5581 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5582 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5583 MachineBasicBlock *PHIBB = PHI->getParent(); 5584 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5585 "This is not a machine PHI node that we are updating!"); 5586 // "default" BB. We can go there only from header BB. 5587 if (PHIBB == JTCases[i].second.Default) { 5588 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5589 false)); 5590 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 5591 } 5592 // JT BB. Just iterate over successors here 5593 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 5594 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5595 false)); 5596 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5597 } 5598 } 5599 } 5600 5601 // If the switch block involved a branch to one of the actual successors, we 5602 // need to update PHI nodes in that block. 5603 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5604 MachineInstr *PHI = PHINodesToUpdate[i].first; 5605 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5606 "This is not a machine PHI node that we are updating!"); 5607 if (BB->isSuccessor(PHI->getParent())) { 5608 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5609 false)); 5610 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5611 } 5612 } 5613 5614 // If we generated any switch lowering information, build and codegen any 5615 // additional DAGs necessary. 5616 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5617 SelectionDAG SDAG(TLI, MF, FuncInfo, 5618 getAnalysisToUpdate<MachineModuleInfo>(), 5619 AllNodes); 5620 CurDAG = &SDAG; 5621 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5622 5623 // Set the current basic block to the mbb we wish to insert the code into 5624 BB = SwitchCases[i].ThisBB; 5625 SDL.setCurrentBasicBlock(BB); 5626 5627 // Emit the code 5628 SDL.visitSwitchCase(SwitchCases[i]); 5629 SDAG.setRoot(SDL.getRoot()); 5630 CodeGenAndEmitDAG(SDAG); 5631 5632 // Handle any PHI nodes in successors of this chunk, as if we were coming 5633 // from the original BB before switch expansion. Note that PHI nodes can 5634 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5635 // handle them the right number of times. 5636 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5637 for (MachineBasicBlock::iterator Phi = BB->begin(); 5638 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5639 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5640 for (unsigned pn = 0; ; ++pn) { 5641 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5642 if (PHINodesToUpdate[pn].first == Phi) { 5643 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5644 second, false)); 5645 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5646 break; 5647 } 5648 } 5649 } 5650 5651 // Don't process RHS if same block as LHS. 5652 if (BB == SwitchCases[i].FalseBB) 5653 SwitchCases[i].FalseBB = 0; 5654 5655 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5656 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5657 SwitchCases[i].FalseBB = 0; 5658 } 5659 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5660 } 5661} 5662 5663 5664/// Schedule - Pick a safe ordering for instructions for each 5665/// target node in the graph. 5666/// 5667ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { 5668 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5669 5670 if (!Ctor) { 5671 Ctor = ISHeuristic; 5672 RegisterScheduler::setDefault(Ctor); 5673 } 5674 5675 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); 5676 Scheduler->Run(); 5677 5678 return Scheduler; 5679} 5680 5681 5682HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5683 return new HazardRecognizer(); 5684} 5685 5686//===----------------------------------------------------------------------===// 5687// Helper functions used by the generated instruction selector. 5688//===----------------------------------------------------------------------===// 5689// Calls to these methods are generated by tblgen. 5690 5691/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5692/// the dag combiner simplified the 255, we still want to match. RHS is the 5693/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5694/// specified in the .td file (e.g. 255). 5695bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 5696 int64_t DesiredMaskS) const { 5697 const APInt &ActualMask = RHS->getAPIntValue(); 5698 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5699 5700 // If the actual mask exactly matches, success! 5701 if (ActualMask == DesiredMask) 5702 return true; 5703 5704 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5705 if (ActualMask.intersects(~DesiredMask)) 5706 return false; 5707 5708 // Otherwise, the DAG Combiner may have proven that the value coming in is 5709 // either already zero or is not demanded. Check for known zero input bits. 5710 APInt NeededMask = DesiredMask & ~ActualMask; 5711 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5712 return true; 5713 5714 // TODO: check to see if missing bits are just not demanded. 5715 5716 // Otherwise, this pattern doesn't match. 5717 return false; 5718} 5719 5720/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5721/// the dag combiner simplified the 255, we still want to match. RHS is the 5722/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5723/// specified in the .td file (e.g. 255). 5724bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 5725 int64_t DesiredMaskS) const { 5726 const APInt &ActualMask = RHS->getAPIntValue(); 5727 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5728 5729 // If the actual mask exactly matches, success! 5730 if (ActualMask == DesiredMask) 5731 return true; 5732 5733 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5734 if (ActualMask.intersects(~DesiredMask)) 5735 return false; 5736 5737 // Otherwise, the DAG Combiner may have proven that the value coming in is 5738 // either already zero or is not demanded. Check for known zero input bits. 5739 APInt NeededMask = DesiredMask & ~ActualMask; 5740 5741 APInt KnownZero, KnownOne; 5742 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5743 5744 // If all the missing bits in the or are already known to be set, match! 5745 if ((NeededMask & KnownOne) == NeededMask) 5746 return true; 5747 5748 // TODO: check to see if missing bits are just not demanded. 5749 5750 // Otherwise, this pattern doesn't match. 5751 return false; 5752} 5753 5754 5755/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5756/// by tblgen. Others should not call it. 5757void SelectionDAGISel:: 5758SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) { 5759 std::vector<SDValue> InOps; 5760 std::swap(InOps, Ops); 5761 5762 Ops.push_back(InOps[0]); // input chain. 5763 Ops.push_back(InOps[1]); // input asm string. 5764 5765 unsigned i = 2, e = InOps.size(); 5766 if (InOps[e-1].getValueType() == MVT::Flag) 5767 --e; // Don't process a flag operand if it is here. 5768 5769 while (i != e) { 5770 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5771 if ((Flags & 7) != 4 /*MEM*/) { 5772 // Just skip over this operand, copying the operands verbatim. 5773 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5774 i += (Flags >> 3) + 1; 5775 } else { 5776 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5777 // Otherwise, this is a memory operand. Ask the target to select it. 5778 std::vector<SDValue> SelOps; 5779 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5780 cerr << "Could not match memory address. Inline asm failure!\n"; 5781 exit(1); 5782 } 5783 5784 // Add this to the output node. 5785 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5786 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5787 IntPtrTy)); 5788 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5789 i += 2; 5790 } 5791 } 5792 5793 // Add the flag input back if present. 5794 if (e != InOps.size()) 5795 Ops.push_back(InOps.back()); 5796} 5797 5798char SelectionDAGISel::ID = 0; 5799