SelectionDAGISel.cpp revision 849f214a4e3676e41168b0c5398165c4d4fb99f8
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available:")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { struct AsmOperandInfo; } 86 87namespace { 88 /// RegsForValue - This struct represents the physical registers that a 89 /// particular value is assigned and the type information about the value. 90 /// This is needed because values can be promoted into larger registers and 91 /// expanded into multiple smaller registers than the value. 92 struct VISIBILITY_HIDDEN RegsForValue { 93 /// Regs - This list holds the register (for legal and promoted values) 94 /// or register set (for expanded values) that the value should be assigned 95 /// to. 96 std::vector<unsigned> Regs; 97 98 /// RegVT - The value type of each register. 99 /// 100 MVT::ValueType RegVT; 101 102 /// ValueVT - The value type of the LLVM value, which may be promoted from 103 /// RegVT or made from merging the two expanded parts. 104 MVT::ValueType ValueVT; 105 106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 107 108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 109 : RegVT(regvt), ValueVT(valuevt) { 110 Regs.push_back(Reg); 111 } 112 RegsForValue(const std::vector<unsigned> ®s, 113 MVT::ValueType regvt, MVT::ValueType valuevt) 114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 115 } 116 117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 118 /// this value and returns the result as a ValueVT value. This uses 119 /// Chain/Flag as the input and updates them for the output Chain/Flag. 120 /// If the Flag pointer is NULL, no flag is used. 121 SDOperand getCopyFromRegs(SelectionDAG &DAG, 122 SDOperand &Chain, SDOperand *Flag) const; 123 124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 125 /// specified value into the registers specified by this object. This uses 126 /// Chain/Flag as the input and updates them for the output Chain/Flag. 127 /// If the Flag pointer is NULL, no flag is used. 128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 129 SDOperand &Chain, SDOperand *Flag) const; 130 131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 132 /// operand list. This adds the code marker and includes the number of 133 /// values added into it. 134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 135 std::vector<SDOperand> &Ops) const; 136 }; 137} 138 139namespace llvm { 140 //===--------------------------------------------------------------------===// 141 /// createDefaultScheduler - This creates an instruction scheduler appropriate 142 /// for the target. 143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 144 SelectionDAG *DAG, 145 MachineBasicBlock *BB) { 146 TargetLowering &TLI = IS->getTargetLowering(); 147 148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 149 return createTDListDAGScheduler(IS, DAG, BB); 150 } else { 151 assert(TLI.getSchedulingPreference() == 152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 153 return createBURRListDAGScheduler(IS, DAG, BB); 154 } 155 } 156 157 158 //===--------------------------------------------------------------------===// 159 /// FunctionLoweringInfo - This contains information that is global to a 160 /// function that is used when lowering a region of the function. 161 class FunctionLoweringInfo { 162 public: 163 TargetLowering &TLI; 164 Function &Fn; 165 MachineFunction &MF; 166 SSARegMap *RegMap; 167 168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 169 170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 172 173 /// ValueMap - Since we emit code for the function a basic block at a time, 174 /// we must remember which virtual registers hold the values for 175 /// cross-basic-block values. 176 DenseMap<const Value*, unsigned> ValueMap; 177 178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 179 /// the entry block. This allows the allocas to be efficiently referenced 180 /// anywhere in the function. 181 std::map<const AllocaInst*, int> StaticAllocaMap; 182 183#ifndef NDEBUG 184 SmallSet<Instruction*, 8> CatchInfoLost; 185 SmallSet<Instruction*, 8> CatchInfoFound; 186#endif 187 188 unsigned MakeReg(MVT::ValueType VT) { 189 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 190 } 191 192 /// isExportedInst - Return true if the specified value is an instruction 193 /// exported from its block. 194 bool isExportedInst(const Value *V) { 195 return ValueMap.count(V); 196 } 197 198 unsigned CreateRegForValue(const Value *V); 199 200 unsigned InitializeRegForValue(const Value *V) { 201 unsigned &R = ValueMap[V]; 202 assert(R == 0 && "Already initialized this value register!"); 203 return R = CreateRegForValue(V); 204 } 205 }; 206} 207 208/// isFilterOrSelector - Return true if this instruction is a call to the 209/// eh.filter or the eh.selector intrinsic. 210static bool isFilterOrSelector(Instruction *I) { 211 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 212 return II->getIntrinsicID() == Intrinsic::eh_selector 213 || II->getIntrinsicID() == Intrinsic::eh_filter; 214 return false; 215} 216 217/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 218/// PHI nodes or outside of the basic block that defines it, or used by a 219/// switch instruction, which may expand to multiple basic blocks. 220static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 221 if (isa<PHINode>(I)) return true; 222 BasicBlock *BB = I->getParent(); 223 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 224 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 225 // FIXME: Remove switchinst special case. 226 isa<SwitchInst>(*UI)) 227 return true; 228 return false; 229} 230 231/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 232/// entry block, return true. This includes arguments used by switches, since 233/// the switch may expand into multiple basic blocks. 234static bool isOnlyUsedInEntryBlock(Argument *A) { 235 BasicBlock *Entry = A->getParent()->begin(); 236 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 237 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 238 return false; // Use not in entry block. 239 return true; 240} 241 242FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 243 Function &fn, MachineFunction &mf) 244 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 245 246 // Create a vreg for each argument register that is not dead and is used 247 // outside of the entry block for the function. 248 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 249 AI != E; ++AI) 250 if (!isOnlyUsedInEntryBlock(AI)) 251 InitializeRegForValue(AI); 252 253 // Initialize the mapping of values to registers. This is only set up for 254 // instruction values that are used outside of the block that defines 255 // them. 256 Function::iterator BB = Fn.begin(), EB = Fn.end(); 257 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 258 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 259 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 260 const Type *Ty = AI->getAllocatedType(); 261 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 262 unsigned Align = 263 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 264 AI->getAlignment()); 265 266 TySize *= CUI->getZExtValue(); // Get total allocated size. 267 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 268 StaticAllocaMap[AI] = 269 MF.getFrameInfo()->CreateStackObject(TySize, Align); 270 } 271 272 for (; BB != EB; ++BB) 273 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 274 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 275 if (!isa<AllocaInst>(I) || 276 !StaticAllocaMap.count(cast<AllocaInst>(I))) 277 InitializeRegForValue(I); 278 279 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 280 // also creates the initial PHI MachineInstrs, though none of the input 281 // operands are populated. 282 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 283 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 284 MBBMap[BB] = MBB; 285 MF.getBasicBlockList().push_back(MBB); 286 287 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 288 // appropriate. 289 PHINode *PN; 290 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 291 if (PN->use_empty()) continue; 292 293 MVT::ValueType VT = TLI.getValueType(PN->getType()); 294 unsigned NumRegisters = TLI.getNumRegisters(VT); 295 unsigned PHIReg = ValueMap[PN]; 296 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 297 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 298 for (unsigned i = 0; i != NumRegisters; ++i) 299 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 300 } 301 } 302} 303 304/// CreateRegForValue - Allocate the appropriate number of virtual registers of 305/// the correctly promoted or expanded types. Assign these registers 306/// consecutive vreg numbers and return the first assigned number. 307unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 308 MVT::ValueType VT = TLI.getValueType(V->getType()); 309 310 unsigned NumRegisters = TLI.getNumRegisters(VT); 311 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 312 313 unsigned R = MakeReg(RegisterVT); 314 for (unsigned i = 1; i != NumRegisters; ++i) 315 MakeReg(RegisterVT); 316 317 return R; 318} 319 320//===----------------------------------------------------------------------===// 321/// SelectionDAGLowering - This is the common target-independent lowering 322/// implementation that is parameterized by a TargetLowering object. 323/// Also, targets can overload any lowering method. 324/// 325namespace llvm { 326class SelectionDAGLowering { 327 MachineBasicBlock *CurMBB; 328 329 DenseMap<const Value*, SDOperand> NodeMap; 330 331 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 332 /// them up and then emit token factor nodes when possible. This allows us to 333 /// get simple disambiguation between loads without worrying about alias 334 /// analysis. 335 std::vector<SDOperand> PendingLoads; 336 337 /// Case - A struct to record the Value for a switch case, and the 338 /// case's target basic block. 339 struct Case { 340 Constant* Low; 341 Constant* High; 342 MachineBasicBlock* BB; 343 344 Case() : Low(0), High(0), BB(0) { } 345 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 346 Low(low), High(high), BB(bb) { } 347 uint64_t size() const { 348 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 349 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 350 return (rHigh - rLow + 1ULL); 351 } 352 }; 353 354 struct CaseBits { 355 uint64_t Mask; 356 MachineBasicBlock* BB; 357 unsigned Bits; 358 359 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 360 Mask(mask), BB(bb), Bits(bits) { } 361 }; 362 363 typedef std::vector<Case> CaseVector; 364 typedef std::vector<CaseBits> CaseBitsVector; 365 typedef CaseVector::iterator CaseItr; 366 typedef std::pair<CaseItr, CaseItr> CaseRange; 367 368 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 369 /// of conditional branches. 370 struct CaseRec { 371 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 372 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 373 374 /// CaseBB - The MBB in which to emit the compare and branch 375 MachineBasicBlock *CaseBB; 376 /// LT, GE - If nonzero, we know the current case value must be less-than or 377 /// greater-than-or-equal-to these Constants. 378 Constant *LT; 379 Constant *GE; 380 /// Range - A pair of iterators representing the range of case values to be 381 /// processed at this point in the binary search tree. 382 CaseRange Range; 383 }; 384 385 typedef std::vector<CaseRec> CaseRecVector; 386 387 /// The comparison function for sorting the switch case values in the vector. 388 /// WARNING: Case ranges should be disjoint! 389 struct CaseCmp { 390 bool operator () (const Case& C1, const Case& C2) { 391 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 392 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 393 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 394 return CI1->getValue().slt(CI2->getValue()); 395 } 396 }; 397 398 struct CaseBitsCmp { 399 bool operator () (const CaseBits& C1, const CaseBits& C2) { 400 return C1.Bits > C2.Bits; 401 } 402 }; 403 404 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 405 406public: 407 // TLI - This is information that describes the available target features we 408 // need for lowering. This indicates when operations are unavailable, 409 // implemented with a libcall, etc. 410 TargetLowering &TLI; 411 SelectionDAG &DAG; 412 const TargetData *TD; 413 414 /// SwitchCases - Vector of CaseBlock structures used to communicate 415 /// SwitchInst code generation information. 416 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 417 /// JTCases - Vector of JumpTable structures used to communicate 418 /// SwitchInst code generation information. 419 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 420 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 421 422 /// FuncInfo - Information about the function as a whole. 423 /// 424 FunctionLoweringInfo &FuncInfo; 425 426 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 427 FunctionLoweringInfo &funcinfo) 428 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 429 FuncInfo(funcinfo) { 430 } 431 432 /// getRoot - Return the current virtual root of the Selection DAG. 433 /// 434 SDOperand getRoot() { 435 if (PendingLoads.empty()) 436 return DAG.getRoot(); 437 438 if (PendingLoads.size() == 1) { 439 SDOperand Root = PendingLoads[0]; 440 DAG.setRoot(Root); 441 PendingLoads.clear(); 442 return Root; 443 } 444 445 // Otherwise, we have to make a token factor node. 446 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 447 &PendingLoads[0], PendingLoads.size()); 448 PendingLoads.clear(); 449 DAG.setRoot(Root); 450 return Root; 451 } 452 453 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 454 455 void visit(Instruction &I) { visit(I.getOpcode(), I); } 456 457 void visit(unsigned Opcode, User &I) { 458 // Note: this doesn't use InstVisitor, because it has to work with 459 // ConstantExpr's in addition to instructions. 460 switch (Opcode) { 461 default: assert(0 && "Unknown instruction type encountered!"); 462 abort(); 463 // Build the switch statement using the Instruction.def file. 464#define HANDLE_INST(NUM, OPCODE, CLASS) \ 465 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 466#include "llvm/Instruction.def" 467 } 468 } 469 470 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 471 472 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 473 const Value *SV, SDOperand Root, 474 bool isVolatile, unsigned Alignment); 475 476 SDOperand getIntPtrConstant(uint64_t Val) { 477 return DAG.getConstant(Val, TLI.getPointerTy()); 478 } 479 480 SDOperand getValue(const Value *V); 481 482 void setValue(const Value *V, SDOperand NewN) { 483 SDOperand &N = NodeMap[V]; 484 assert(N.Val == 0 && "Already set a value for this node!"); 485 N = NewN; 486 } 487 488 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 489 std::set<unsigned> &OutputRegs, 490 std::set<unsigned> &InputRegs); 491 492 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 493 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 494 unsigned Opc); 495 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 496 void ExportFromCurrentBlock(Value *V); 497 void LowerCallTo(Instruction &I, 498 const Type *CalledValueTy, unsigned CallingConv, 499 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 500 MachineBasicBlock *LandingPad = NULL); 501 502 // Terminator instructions. 503 void visitRet(ReturnInst &I); 504 void visitBr(BranchInst &I); 505 void visitSwitch(SwitchInst &I); 506 void visitUnreachable(UnreachableInst &I) { /* noop */ } 507 508 // Helpers for visitSwitch 509 bool handleSmallSwitchRange(CaseRec& CR, 510 CaseRecVector& WorkList, 511 Value* SV, 512 MachineBasicBlock* Default); 513 bool handleJTSwitchCase(CaseRec& CR, 514 CaseRecVector& WorkList, 515 Value* SV, 516 MachineBasicBlock* Default); 517 bool handleBTSplitSwitchCase(CaseRec& CR, 518 CaseRecVector& WorkList, 519 Value* SV, 520 MachineBasicBlock* Default); 521 bool handleBitTestsSwitchCase(CaseRec& CR, 522 CaseRecVector& WorkList, 523 Value* SV, 524 MachineBasicBlock* Default); 525 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 526 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 527 void visitBitTestCase(MachineBasicBlock* NextMBB, 528 unsigned Reg, 529 SelectionDAGISel::BitTestCase &B); 530 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 531 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 532 SelectionDAGISel::JumpTableHeader &JTH); 533 534 // These all get lowered before this pass. 535 void visitInvoke(InvokeInst &I); 536 void visitUnwind(UnwindInst &I); 537 538 void visitBinary(User &I, unsigned OpCode); 539 void visitShift(User &I, unsigned Opcode); 540 void visitAdd(User &I) { 541 if (I.getType()->isFPOrFPVector()) 542 visitBinary(I, ISD::FADD); 543 else 544 visitBinary(I, ISD::ADD); 545 } 546 void visitSub(User &I); 547 void visitMul(User &I) { 548 if (I.getType()->isFPOrFPVector()) 549 visitBinary(I, ISD::FMUL); 550 else 551 visitBinary(I, ISD::MUL); 552 } 553 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 554 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 555 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 556 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 557 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 558 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 559 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 560 void visitOr (User &I) { visitBinary(I, ISD::OR); } 561 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 562 void visitShl (User &I) { visitShift(I, ISD::SHL); } 563 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 564 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 565 void visitICmp(User &I); 566 void visitFCmp(User &I); 567 // Visit the conversion instructions 568 void visitTrunc(User &I); 569 void visitZExt(User &I); 570 void visitSExt(User &I); 571 void visitFPTrunc(User &I); 572 void visitFPExt(User &I); 573 void visitFPToUI(User &I); 574 void visitFPToSI(User &I); 575 void visitUIToFP(User &I); 576 void visitSIToFP(User &I); 577 void visitPtrToInt(User &I); 578 void visitIntToPtr(User &I); 579 void visitBitCast(User &I); 580 581 void visitExtractElement(User &I); 582 void visitInsertElement(User &I); 583 void visitShuffleVector(User &I); 584 585 void visitGetElementPtr(User &I); 586 void visitSelect(User &I); 587 588 void visitMalloc(MallocInst &I); 589 void visitFree(FreeInst &I); 590 void visitAlloca(AllocaInst &I); 591 void visitLoad(LoadInst &I); 592 void visitStore(StoreInst &I); 593 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 594 void visitCall(CallInst &I); 595 void visitInlineAsm(CallInst &I); 596 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 597 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 598 599 void visitVAStart(CallInst &I); 600 void visitVAArg(VAArgInst &I); 601 void visitVAEnd(CallInst &I); 602 void visitVACopy(CallInst &I); 603 604 void visitMemIntrinsic(CallInst &I, unsigned Op); 605 606 void visitUserOp1(Instruction &I) { 607 assert(0 && "UserOp1 should not exist at instruction selection time!"); 608 abort(); 609 } 610 void visitUserOp2(Instruction &I) { 611 assert(0 && "UserOp2 should not exist at instruction selection time!"); 612 abort(); 613 } 614}; 615} // end namespace llvm 616 617SDOperand SelectionDAGLowering::getValue(const Value *V) { 618 SDOperand &N = NodeMap[V]; 619 if (N.Val) return N; 620 621 const Type *VTy = V->getType(); 622 MVT::ValueType VT = TLI.getValueType(VTy); 623 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 624 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 625 visit(CE->getOpcode(), *CE); 626 SDOperand N1 = NodeMap[V]; 627 assert(N1.Val && "visit didn't populate the ValueMap!"); 628 return N1; 629 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 630 return N = DAG.getGlobalAddress(GV, VT); 631 } else if (isa<ConstantPointerNull>(C)) { 632 return N = DAG.getConstant(0, TLI.getPointerTy()); 633 } else if (isa<UndefValue>(C)) { 634 if (!isa<VectorType>(VTy)) 635 return N = DAG.getNode(ISD::UNDEF, VT); 636 637 // Create a BUILD_VECTOR of undef nodes. 638 const VectorType *PTy = cast<VectorType>(VTy); 639 unsigned NumElements = PTy->getNumElements(); 640 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 641 642 SmallVector<SDOperand, 8> Ops; 643 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 644 645 // Create a VConstant node with generic Vector type. 646 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 647 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 648 &Ops[0], Ops.size()); 649 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 650 return N = DAG.getConstantFP(CFP->getValue(), VT); 651 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 652 unsigned NumElements = PTy->getNumElements(); 653 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 654 655 // Now that we know the number and type of the elements, push a 656 // Constant or ConstantFP node onto the ops list for each element of 657 // the packed constant. 658 SmallVector<SDOperand, 8> Ops; 659 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 660 for (unsigned i = 0; i != NumElements; ++i) 661 Ops.push_back(getValue(CP->getOperand(i))); 662 } else { 663 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 664 SDOperand Op; 665 if (MVT::isFloatingPoint(PVT)) 666 Op = DAG.getConstantFP(0, PVT); 667 else 668 Op = DAG.getConstant(0, PVT); 669 Ops.assign(NumElements, Op); 670 } 671 672 // Create a BUILD_VECTOR node. 673 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 674 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 675 Ops.size()); 676 } else { 677 // Canonicalize all constant ints to be unsigned. 678 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 679 } 680 } 681 682 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 683 std::map<const AllocaInst*, int>::iterator SI = 684 FuncInfo.StaticAllocaMap.find(AI); 685 if (SI != FuncInfo.StaticAllocaMap.end()) 686 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 687 } 688 689 unsigned InReg = FuncInfo.ValueMap[V]; 690 assert(InReg && "Value not in map!"); 691 692 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 693 unsigned NumRegs = TLI.getNumRegisters(VT); 694 695 std::vector<unsigned> Regs(NumRegs); 696 for (unsigned i = 0; i != NumRegs; ++i) 697 Regs[i] = InReg + i; 698 699 RegsForValue RFV(Regs, RegisterVT, VT); 700 SDOperand Chain = DAG.getEntryNode(); 701 702 return RFV.getCopyFromRegs(DAG, Chain, NULL); 703} 704 705 706void SelectionDAGLowering::visitRet(ReturnInst &I) { 707 if (I.getNumOperands() == 0) { 708 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 709 return; 710 } 711 SmallVector<SDOperand, 8> NewValues; 712 NewValues.push_back(getRoot()); 713 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 714 SDOperand RetOp = getValue(I.getOperand(i)); 715 716 // If this is an integer return value, we need to promote it ourselves to 717 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 718 // than sign/zero. 719 // FIXME: C calling convention requires the return type to be promoted to 720 // at least 32-bit. But this is not necessary for non-C calling conventions. 721 if (MVT::isInteger(RetOp.getValueType()) && 722 RetOp.getValueType() < MVT::i64) { 723 MVT::ValueType TmpVT; 724 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 725 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 726 else 727 TmpVT = MVT::i32; 728 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 729 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 730 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 731 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 732 ExtendKind = ISD::SIGN_EXTEND; 733 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 734 ExtendKind = ISD::ZERO_EXTEND; 735 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 736 } 737 NewValues.push_back(RetOp); 738 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 739 } 740 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 741 &NewValues[0], NewValues.size())); 742} 743 744/// ExportFromCurrentBlock - If this condition isn't known to be exported from 745/// the current basic block, add it to ValueMap now so that we'll get a 746/// CopyTo/FromReg. 747void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 748 // No need to export constants. 749 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 750 751 // Already exported? 752 if (FuncInfo.isExportedInst(V)) return; 753 754 unsigned Reg = FuncInfo.InitializeRegForValue(V); 755 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 756} 757 758bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 759 const BasicBlock *FromBB) { 760 // The operands of the setcc have to be in this block. We don't know 761 // how to export them from some other block. 762 if (Instruction *VI = dyn_cast<Instruction>(V)) { 763 // Can export from current BB. 764 if (VI->getParent() == FromBB) 765 return true; 766 767 // Is already exported, noop. 768 return FuncInfo.isExportedInst(V); 769 } 770 771 // If this is an argument, we can export it if the BB is the entry block or 772 // if it is already exported. 773 if (isa<Argument>(V)) { 774 if (FromBB == &FromBB->getParent()->getEntryBlock()) 775 return true; 776 777 // Otherwise, can only export this if it is already exported. 778 return FuncInfo.isExportedInst(V); 779 } 780 781 // Otherwise, constants can always be exported. 782 return true; 783} 784 785static bool InBlock(const Value *V, const BasicBlock *BB) { 786 if (const Instruction *I = dyn_cast<Instruction>(V)) 787 return I->getParent() == BB; 788 return true; 789} 790 791/// FindMergedConditions - If Cond is an expression like 792void SelectionDAGLowering::FindMergedConditions(Value *Cond, 793 MachineBasicBlock *TBB, 794 MachineBasicBlock *FBB, 795 MachineBasicBlock *CurBB, 796 unsigned Opc) { 797 // If this node is not part of the or/and tree, emit it as a branch. 798 Instruction *BOp = dyn_cast<Instruction>(Cond); 799 800 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 801 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 802 BOp->getParent() != CurBB->getBasicBlock() || 803 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 804 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 805 const BasicBlock *BB = CurBB->getBasicBlock(); 806 807 // If the leaf of the tree is a comparison, merge the condition into 808 // the caseblock. 809 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 810 // The operands of the cmp have to be in this block. We don't know 811 // how to export them from some other block. If this is the first block 812 // of the sequence, no exporting is needed. 813 (CurBB == CurMBB || 814 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 815 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 816 BOp = cast<Instruction>(Cond); 817 ISD::CondCode Condition; 818 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 819 switch (IC->getPredicate()) { 820 default: assert(0 && "Unknown icmp predicate opcode!"); 821 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 822 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 823 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 824 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 825 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 826 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 827 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 828 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 829 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 830 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 831 } 832 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 833 ISD::CondCode FPC, FOC; 834 switch (FC->getPredicate()) { 835 default: assert(0 && "Unknown fcmp predicate opcode!"); 836 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 837 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 838 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 839 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 840 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 841 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 842 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 843 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 844 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 845 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 846 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 847 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 848 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 849 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 850 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 851 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 852 } 853 if (FiniteOnlyFPMath()) 854 Condition = FOC; 855 else 856 Condition = FPC; 857 } else { 858 Condition = ISD::SETEQ; // silence warning. 859 assert(0 && "Unknown compare instruction"); 860 } 861 862 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 863 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 864 SwitchCases.push_back(CB); 865 return; 866 } 867 868 // Create a CaseBlock record representing this branch. 869 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 870 NULL, TBB, FBB, CurBB); 871 SwitchCases.push_back(CB); 872 return; 873 } 874 875 876 // Create TmpBB after CurBB. 877 MachineFunction::iterator BBI = CurBB; 878 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 879 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 880 881 if (Opc == Instruction::Or) { 882 // Codegen X | Y as: 883 // jmp_if_X TBB 884 // jmp TmpBB 885 // TmpBB: 886 // jmp_if_Y TBB 887 // jmp FBB 888 // 889 890 // Emit the LHS condition. 891 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 892 893 // Emit the RHS condition into TmpBB. 894 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 895 } else { 896 assert(Opc == Instruction::And && "Unknown merge op!"); 897 // Codegen X & Y as: 898 // jmp_if_X TmpBB 899 // jmp FBB 900 // TmpBB: 901 // jmp_if_Y TBB 902 // jmp FBB 903 // 904 // This requires creation of TmpBB after CurBB. 905 906 // Emit the LHS condition. 907 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 908 909 // Emit the RHS condition into TmpBB. 910 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 911 } 912} 913 914/// If the set of cases should be emitted as a series of branches, return true. 915/// If we should emit this as a bunch of and/or'd together conditions, return 916/// false. 917static bool 918ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 919 if (Cases.size() != 2) return true; 920 921 // If this is two comparisons of the same values or'd or and'd together, they 922 // will get folded into a single comparison, so don't emit two blocks. 923 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 924 Cases[0].CmpRHS == Cases[1].CmpRHS) || 925 (Cases[0].CmpRHS == Cases[1].CmpLHS && 926 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 927 return false; 928 } 929 930 return true; 931} 932 933void SelectionDAGLowering::visitBr(BranchInst &I) { 934 // Update machine-CFG edges. 935 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 936 937 // Figure out which block is immediately after the current one. 938 MachineBasicBlock *NextBlock = 0; 939 MachineFunction::iterator BBI = CurMBB; 940 if (++BBI != CurMBB->getParent()->end()) 941 NextBlock = BBI; 942 943 if (I.isUnconditional()) { 944 // If this is not a fall-through branch, emit the branch. 945 if (Succ0MBB != NextBlock) 946 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 947 DAG.getBasicBlock(Succ0MBB))); 948 949 // Update machine-CFG edges. 950 CurMBB->addSuccessor(Succ0MBB); 951 952 return; 953 } 954 955 // If this condition is one of the special cases we handle, do special stuff 956 // now. 957 Value *CondVal = I.getCondition(); 958 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 959 960 // If this is a series of conditions that are or'd or and'd together, emit 961 // this as a sequence of branches instead of setcc's with and/or operations. 962 // For example, instead of something like: 963 // cmp A, B 964 // C = seteq 965 // cmp D, E 966 // F = setle 967 // or C, F 968 // jnz foo 969 // Emit: 970 // cmp A, B 971 // je foo 972 // cmp D, E 973 // jle foo 974 // 975 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 976 if (BOp->hasOneUse() && 977 (BOp->getOpcode() == Instruction::And || 978 BOp->getOpcode() == Instruction::Or)) { 979 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 980 // If the compares in later blocks need to use values not currently 981 // exported from this block, export them now. This block should always 982 // be the first entry. 983 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 984 985 // Allow some cases to be rejected. 986 if (ShouldEmitAsBranches(SwitchCases)) { 987 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 988 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 989 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 990 } 991 992 // Emit the branch for this block. 993 visitSwitchCase(SwitchCases[0]); 994 SwitchCases.erase(SwitchCases.begin()); 995 return; 996 } 997 998 // Okay, we decided not to do this, remove any inserted MBB's and clear 999 // SwitchCases. 1000 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1001 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1002 1003 SwitchCases.clear(); 1004 } 1005 } 1006 1007 // Create a CaseBlock record representing this branch. 1008 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1009 NULL, Succ0MBB, Succ1MBB, CurMBB); 1010 // Use visitSwitchCase to actually insert the fast branch sequence for this 1011 // cond branch. 1012 visitSwitchCase(CB); 1013} 1014 1015/// visitSwitchCase - Emits the necessary code to represent a single node in 1016/// the binary search tree resulting from lowering a switch instruction. 1017void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1018 SDOperand Cond; 1019 SDOperand CondLHS = getValue(CB.CmpLHS); 1020 1021 // Build the setcc now. 1022 if (CB.CmpMHS == NULL) { 1023 // Fold "(X == true)" to X and "(X == false)" to !X to 1024 // handle common cases produced by branch lowering. 1025 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1026 Cond = CondLHS; 1027 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1028 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1029 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1030 } else 1031 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1032 } else { 1033 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1034 1035 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1036 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1037 1038 SDOperand CmpOp = getValue(CB.CmpMHS); 1039 MVT::ValueType VT = CmpOp.getValueType(); 1040 1041 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1042 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1043 } else { 1044 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1045 Cond = DAG.getSetCC(MVT::i1, SUB, 1046 DAG.getConstant(High-Low, VT), ISD::SETULE); 1047 } 1048 1049 } 1050 1051 // Set NextBlock to be the MBB immediately after the current one, if any. 1052 // This is used to avoid emitting unnecessary branches to the next block. 1053 MachineBasicBlock *NextBlock = 0; 1054 MachineFunction::iterator BBI = CurMBB; 1055 if (++BBI != CurMBB->getParent()->end()) 1056 NextBlock = BBI; 1057 1058 // If the lhs block is the next block, invert the condition so that we can 1059 // fall through to the lhs instead of the rhs block. 1060 if (CB.TrueBB == NextBlock) { 1061 std::swap(CB.TrueBB, CB.FalseBB); 1062 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1063 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1064 } 1065 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1066 DAG.getBasicBlock(CB.TrueBB)); 1067 if (CB.FalseBB == NextBlock) 1068 DAG.setRoot(BrCond); 1069 else 1070 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1071 DAG.getBasicBlock(CB.FalseBB))); 1072 // Update successor info 1073 CurMBB->addSuccessor(CB.TrueBB); 1074 CurMBB->addSuccessor(CB.FalseBB); 1075} 1076 1077/// visitJumpTable - Emit JumpTable node in the current MBB 1078void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1079 // Emit the code for the jump table 1080 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1081 MVT::ValueType PTy = TLI.getPointerTy(); 1082 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1083 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1084 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1085 Table, Index)); 1086 return; 1087} 1088 1089/// visitJumpTableHeader - This function emits necessary code to produce index 1090/// in the JumpTable from switch case. 1091void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1092 SelectionDAGISel::JumpTableHeader &JTH) { 1093 // Subtract the lowest switch case value from the value being switched on 1094 // and conditional branch to default mbb if the result is greater than the 1095 // difference between smallest and largest cases. 1096 SDOperand SwitchOp = getValue(JTH.SValue); 1097 MVT::ValueType VT = SwitchOp.getValueType(); 1098 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1099 DAG.getConstant(JTH.First, VT)); 1100 1101 // The SDNode we just created, which holds the value being switched on 1102 // minus the the smallest case value, needs to be copied to a virtual 1103 // register so it can be used as an index into the jump table in a 1104 // subsequent basic block. This value may be smaller or larger than the 1105 // target's pointer type, and therefore require extension or truncating. 1106 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1107 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1108 else 1109 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1110 1111 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1112 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1113 JT.Reg = JumpTableReg; 1114 1115 // Emit the range check for the jump table, and branch to the default 1116 // block for the switch statement if the value being switched on exceeds 1117 // the largest case in the switch. 1118 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1119 DAG.getConstant(JTH.Last-JTH.First,VT), 1120 ISD::SETUGT); 1121 1122 // Set NextBlock to be the MBB immediately after the current one, if any. 1123 // This is used to avoid emitting unnecessary branches to the next block. 1124 MachineBasicBlock *NextBlock = 0; 1125 MachineFunction::iterator BBI = CurMBB; 1126 if (++BBI != CurMBB->getParent()->end()) 1127 NextBlock = BBI; 1128 1129 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1130 DAG.getBasicBlock(JT.Default)); 1131 1132 if (JT.MBB == NextBlock) 1133 DAG.setRoot(BrCond); 1134 else 1135 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1136 DAG.getBasicBlock(JT.MBB))); 1137 1138 return; 1139} 1140 1141/// visitBitTestHeader - This function emits necessary code to produce value 1142/// suitable for "bit tests" 1143void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1144 // Subtract the minimum value 1145 SDOperand SwitchOp = getValue(B.SValue); 1146 MVT::ValueType VT = SwitchOp.getValueType(); 1147 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1148 DAG.getConstant(B.First, VT)); 1149 1150 // Check range 1151 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1152 DAG.getConstant(B.Range, VT), 1153 ISD::SETUGT); 1154 1155 SDOperand ShiftOp; 1156 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1157 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1158 else 1159 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1160 1161 // Make desired shift 1162 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1163 DAG.getConstant(1, TLI.getPointerTy()), 1164 ShiftOp); 1165 1166 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1167 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1168 B.Reg = SwitchReg; 1169 1170 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1171 DAG.getBasicBlock(B.Default)); 1172 1173 // Set NextBlock to be the MBB immediately after the current one, if any. 1174 // This is used to avoid emitting unnecessary branches to the next block. 1175 MachineBasicBlock *NextBlock = 0; 1176 MachineFunction::iterator BBI = CurMBB; 1177 if (++BBI != CurMBB->getParent()->end()) 1178 NextBlock = BBI; 1179 1180 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1181 if (MBB == NextBlock) 1182 DAG.setRoot(BrRange); 1183 else 1184 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1185 DAG.getBasicBlock(MBB))); 1186 1187 CurMBB->addSuccessor(B.Default); 1188 CurMBB->addSuccessor(MBB); 1189 1190 return; 1191} 1192 1193/// visitBitTestCase - this function produces one "bit test" 1194void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1195 unsigned Reg, 1196 SelectionDAGISel::BitTestCase &B) { 1197 // Emit bit tests and jumps 1198 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1199 1200 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1201 SwitchVal, 1202 DAG.getConstant(B.Mask, 1203 TLI.getPointerTy())); 1204 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1205 DAG.getConstant(0, TLI.getPointerTy()), 1206 ISD::SETNE); 1207 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1208 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1209 1210 // Set NextBlock to be the MBB immediately after the current one, if any. 1211 // This is used to avoid emitting unnecessary branches to the next block. 1212 MachineBasicBlock *NextBlock = 0; 1213 MachineFunction::iterator BBI = CurMBB; 1214 if (++BBI != CurMBB->getParent()->end()) 1215 NextBlock = BBI; 1216 1217 if (NextMBB == NextBlock) 1218 DAG.setRoot(BrAnd); 1219 else 1220 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1221 DAG.getBasicBlock(NextMBB))); 1222 1223 CurMBB->addSuccessor(B.TargetBB); 1224 CurMBB->addSuccessor(NextMBB); 1225 1226 return; 1227} 1228 1229void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1230 // Retrieve successors. 1231 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1232 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1233 1234 LowerCallTo(I, I.getCalledValue()->getType(), 1235 I.getCallingConv(), 1236 false, 1237 getValue(I.getOperand(0)), 1238 3, LandingPad); 1239 1240 // If the value of the invoke is used outside of its defining block, make it 1241 // available as a virtual register. 1242 if (!I.use_empty()) { 1243 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1244 if (VMI != FuncInfo.ValueMap.end()) 1245 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1246 } 1247 1248 // Drop into normal successor. 1249 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1250 DAG.getBasicBlock(Return))); 1251 1252 // Update successor info 1253 CurMBB->addSuccessor(Return); 1254 CurMBB->addSuccessor(LandingPad); 1255} 1256 1257void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1258} 1259 1260/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1261/// small case ranges). 1262bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1263 CaseRecVector& WorkList, 1264 Value* SV, 1265 MachineBasicBlock* Default) { 1266 Case& BackCase = *(CR.Range.second-1); 1267 1268 // Size is the number of Cases represented by this range. 1269 unsigned Size = CR.Range.second - CR.Range.first; 1270 if (Size > 3) 1271 return false; 1272 1273 // Get the MachineFunction which holds the current MBB. This is used when 1274 // inserting any additional MBBs necessary to represent the switch. 1275 MachineFunction *CurMF = CurMBB->getParent(); 1276 1277 // Figure out which block is immediately after the current one. 1278 MachineBasicBlock *NextBlock = 0; 1279 MachineFunction::iterator BBI = CR.CaseBB; 1280 1281 if (++BBI != CurMBB->getParent()->end()) 1282 NextBlock = BBI; 1283 1284 // TODO: If any two of the cases has the same destination, and if one value 1285 // is the same as the other, but has one bit unset that the other has set, 1286 // use bit manipulation to do two compares at once. For example: 1287 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1288 1289 // Rearrange the case blocks so that the last one falls through if possible. 1290 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1291 // The last case block won't fall through into 'NextBlock' if we emit the 1292 // branches in this order. See if rearranging a case value would help. 1293 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1294 if (I->BB == NextBlock) { 1295 std::swap(*I, BackCase); 1296 break; 1297 } 1298 } 1299 } 1300 1301 // Create a CaseBlock record representing a conditional branch to 1302 // the Case's target mbb if the value being switched on SV is equal 1303 // to C. 1304 MachineBasicBlock *CurBlock = CR.CaseBB; 1305 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1306 MachineBasicBlock *FallThrough; 1307 if (I != E-1) { 1308 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1309 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1310 } else { 1311 // If the last case doesn't match, go to the default block. 1312 FallThrough = Default; 1313 } 1314 1315 Value *RHS, *LHS, *MHS; 1316 ISD::CondCode CC; 1317 if (I->High == I->Low) { 1318 // This is just small small case range :) containing exactly 1 case 1319 CC = ISD::SETEQ; 1320 LHS = SV; RHS = I->High; MHS = NULL; 1321 } else { 1322 CC = ISD::SETLE; 1323 LHS = I->Low; MHS = SV; RHS = I->High; 1324 } 1325 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1326 I->BB, FallThrough, CurBlock); 1327 1328 // If emitting the first comparison, just call visitSwitchCase to emit the 1329 // code into the current block. Otherwise, push the CaseBlock onto the 1330 // vector to be later processed by SDISel, and insert the node's MBB 1331 // before the next MBB. 1332 if (CurBlock == CurMBB) 1333 visitSwitchCase(CB); 1334 else 1335 SwitchCases.push_back(CB); 1336 1337 CurBlock = FallThrough; 1338 } 1339 1340 return true; 1341} 1342 1343static inline bool areJTsAllowed(const TargetLowering &TLI) { 1344 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1345 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1346} 1347 1348/// handleJTSwitchCase - Emit jumptable for current switch case range 1349bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1350 CaseRecVector& WorkList, 1351 Value* SV, 1352 MachineBasicBlock* Default) { 1353 Case& FrontCase = *CR.Range.first; 1354 Case& BackCase = *(CR.Range.second-1); 1355 1356 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1357 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1358 1359 uint64_t TSize = 0; 1360 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1361 I!=E; ++I) 1362 TSize += I->size(); 1363 1364 if (!areJTsAllowed(TLI) || TSize <= 3) 1365 return false; 1366 1367 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1368 if (Density < 0.4) 1369 return false; 1370 1371 DOUT << "Lowering jump table\n" 1372 << "First entry: " << First << ". Last entry: " << Last << "\n" 1373 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1374 1375 // Get the MachineFunction which holds the current MBB. This is used when 1376 // inserting any additional MBBs necessary to represent the switch. 1377 MachineFunction *CurMF = CurMBB->getParent(); 1378 1379 // Figure out which block is immediately after the current one. 1380 MachineBasicBlock *NextBlock = 0; 1381 MachineFunction::iterator BBI = CR.CaseBB; 1382 1383 if (++BBI != CurMBB->getParent()->end()) 1384 NextBlock = BBI; 1385 1386 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1387 1388 // Create a new basic block to hold the code for loading the address 1389 // of the jump table, and jumping to it. Update successor information; 1390 // we will either branch to the default case for the switch, or the jump 1391 // table. 1392 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1393 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1394 CR.CaseBB->addSuccessor(Default); 1395 CR.CaseBB->addSuccessor(JumpTableBB); 1396 1397 // Build a vector of destination BBs, corresponding to each target 1398 // of the jump table. If the value of the jump table slot corresponds to 1399 // a case statement, push the case's BB onto the vector, otherwise, push 1400 // the default BB. 1401 std::vector<MachineBasicBlock*> DestBBs; 1402 int64_t TEI = First; 1403 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1404 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1405 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1406 1407 if ((Low <= TEI) && (TEI <= High)) { 1408 DestBBs.push_back(I->BB); 1409 if (TEI==High) 1410 ++I; 1411 } else { 1412 DestBBs.push_back(Default); 1413 } 1414 } 1415 1416 // Update successor info. Add one edge to each unique successor. 1417 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1418 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1419 E = DestBBs.end(); I != E; ++I) { 1420 if (!SuccsHandled[(*I)->getNumber()]) { 1421 SuccsHandled[(*I)->getNumber()] = true; 1422 JumpTableBB->addSuccessor(*I); 1423 } 1424 } 1425 1426 // Create a jump table index for this jump table, or return an existing 1427 // one. 1428 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1429 1430 // Set the jump table information so that we can codegen it as a second 1431 // MachineBasicBlock 1432 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1433 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1434 (CR.CaseBB == CurMBB)); 1435 if (CR.CaseBB == CurMBB) 1436 visitJumpTableHeader(JT, JTH); 1437 1438 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1439 1440 return true; 1441} 1442 1443/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1444/// 2 subtrees. 1445bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1446 CaseRecVector& WorkList, 1447 Value* SV, 1448 MachineBasicBlock* Default) { 1449 // Get the MachineFunction which holds the current MBB. This is used when 1450 // inserting any additional MBBs necessary to represent the switch. 1451 MachineFunction *CurMF = CurMBB->getParent(); 1452 1453 // Figure out which block is immediately after the current one. 1454 MachineBasicBlock *NextBlock = 0; 1455 MachineFunction::iterator BBI = CR.CaseBB; 1456 1457 if (++BBI != CurMBB->getParent()->end()) 1458 NextBlock = BBI; 1459 1460 Case& FrontCase = *CR.Range.first; 1461 Case& BackCase = *(CR.Range.second-1); 1462 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1463 1464 // Size is the number of Cases represented by this range. 1465 unsigned Size = CR.Range.second - CR.Range.first; 1466 1467 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1468 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1469 double FMetric = 0; 1470 CaseItr Pivot = CR.Range.first + Size/2; 1471 1472 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1473 // (heuristically) allow us to emit JumpTable's later. 1474 uint64_t TSize = 0; 1475 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1476 I!=E; ++I) 1477 TSize += I->size(); 1478 1479 uint64_t LSize = FrontCase.size(); 1480 uint64_t RSize = TSize-LSize; 1481 DOUT << "Selecting best pivot: \n" 1482 << "First: " << First << ", Last: " << Last <<"\n" 1483 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1484 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1485 J!=E; ++I, ++J) { 1486 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1487 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1488 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1489 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1490 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1491 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1492 // Should always split in some non-trivial place 1493 DOUT <<"=>Step\n" 1494 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1495 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1496 << "Metric: " << Metric << "\n"; 1497 if (FMetric < Metric) { 1498 Pivot = J; 1499 FMetric = Metric; 1500 DOUT << "Current metric set to: " << FMetric << "\n"; 1501 } 1502 1503 LSize += J->size(); 1504 RSize -= J->size(); 1505 } 1506 if (areJTsAllowed(TLI)) { 1507 // If our case is dense we *really* should handle it earlier! 1508 assert((FMetric > 0) && "Should handle dense range earlier!"); 1509 } else { 1510 Pivot = CR.Range.first + Size/2; 1511 } 1512 1513 CaseRange LHSR(CR.Range.first, Pivot); 1514 CaseRange RHSR(Pivot, CR.Range.second); 1515 Constant *C = Pivot->Low; 1516 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1517 1518 // We know that we branch to the LHS if the Value being switched on is 1519 // less than the Pivot value, C. We use this to optimize our binary 1520 // tree a bit, by recognizing that if SV is greater than or equal to the 1521 // LHS's Case Value, and that Case Value is exactly one less than the 1522 // Pivot's Value, then we can branch directly to the LHS's Target, 1523 // rather than creating a leaf node for it. 1524 if ((LHSR.second - LHSR.first) == 1 && 1525 LHSR.first->High == CR.GE && 1526 cast<ConstantInt>(C)->getSExtValue() == 1527 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1528 TrueBB = LHSR.first->BB; 1529 } else { 1530 TrueBB = new MachineBasicBlock(LLVMBB); 1531 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1532 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1533 } 1534 1535 // Similar to the optimization above, if the Value being switched on is 1536 // known to be less than the Constant CR.LT, and the current Case Value 1537 // is CR.LT - 1, then we can branch directly to the target block for 1538 // the current Case Value, rather than emitting a RHS leaf node for it. 1539 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1540 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1541 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1542 FalseBB = RHSR.first->BB; 1543 } else { 1544 FalseBB = new MachineBasicBlock(LLVMBB); 1545 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1546 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1547 } 1548 1549 // Create a CaseBlock record representing a conditional branch to 1550 // the LHS node if the value being switched on SV is less than C. 1551 // Otherwise, branch to LHS. 1552 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1553 TrueBB, FalseBB, CR.CaseBB); 1554 1555 if (CR.CaseBB == CurMBB) 1556 visitSwitchCase(CB); 1557 else 1558 SwitchCases.push_back(CB); 1559 1560 return true; 1561} 1562 1563/// handleBitTestsSwitchCase - if current case range has few destination and 1564/// range span less, than machine word bitwidth, encode case range into series 1565/// of masks and emit bit tests with these masks. 1566bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1567 CaseRecVector& WorkList, 1568 Value* SV, 1569 MachineBasicBlock* Default){ 1570 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1571 1572 Case& FrontCase = *CR.Range.first; 1573 Case& BackCase = *(CR.Range.second-1); 1574 1575 // Get the MachineFunction which holds the current MBB. This is used when 1576 // inserting any additional MBBs necessary to represent the switch. 1577 MachineFunction *CurMF = CurMBB->getParent(); 1578 1579 unsigned numCmps = 0; 1580 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1581 I!=E; ++I) { 1582 // Single case counts one, case range - two. 1583 if (I->Low == I->High) 1584 numCmps +=1; 1585 else 1586 numCmps +=2; 1587 } 1588 1589 // Count unique destinations 1590 SmallSet<MachineBasicBlock*, 4> Dests; 1591 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1592 Dests.insert(I->BB); 1593 if (Dests.size() > 3) 1594 // Don't bother the code below, if there are too much unique destinations 1595 return false; 1596 } 1597 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1598 << "Total number of comparisons: " << numCmps << "\n"; 1599 1600 // Compute span of values. 1601 Constant* minValue = FrontCase.Low; 1602 Constant* maxValue = BackCase.High; 1603 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1604 cast<ConstantInt>(minValue)->getSExtValue(); 1605 DOUT << "Compare range: " << range << "\n" 1606 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1607 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1608 1609 if (range>=IntPtrBits || 1610 (!(Dests.size() == 1 && numCmps >= 3) && 1611 !(Dests.size() == 2 && numCmps >= 5) && 1612 !(Dests.size() >= 3 && numCmps >= 6))) 1613 return false; 1614 1615 DOUT << "Emitting bit tests\n"; 1616 int64_t lowBound = 0; 1617 1618 // Optimize the case where all the case values fit in a 1619 // word without having to subtract minValue. In this case, 1620 // we can optimize away the subtraction. 1621 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1622 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1623 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1624 } else { 1625 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1626 } 1627 1628 CaseBitsVector CasesBits; 1629 unsigned i, count = 0; 1630 1631 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1632 MachineBasicBlock* Dest = I->BB; 1633 for (i = 0; i < count; ++i) 1634 if (Dest == CasesBits[i].BB) 1635 break; 1636 1637 if (i == count) { 1638 assert((count < 3) && "Too much destinations to test!"); 1639 CasesBits.push_back(CaseBits(0, Dest, 0)); 1640 count++; 1641 } 1642 1643 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1644 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1645 1646 for (uint64_t j = lo; j <= hi; j++) { 1647 CasesBits[i].Mask |= 1ULL << j; 1648 CasesBits[i].Bits++; 1649 } 1650 1651 } 1652 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1653 1654 SelectionDAGISel::BitTestInfo BTC; 1655 1656 // Figure out which block is immediately after the current one. 1657 MachineFunction::iterator BBI = CR.CaseBB; 1658 ++BBI; 1659 1660 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1661 1662 DOUT << "Cases:\n"; 1663 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1664 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1665 << ", BB: " << CasesBits[i].BB << "\n"; 1666 1667 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1668 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1669 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1670 CaseBB, 1671 CasesBits[i].BB)); 1672 } 1673 1674 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1675 -1U, (CR.CaseBB == CurMBB), 1676 CR.CaseBB, Default, BTC); 1677 1678 if (CR.CaseBB == CurMBB) 1679 visitBitTestHeader(BTB); 1680 1681 BitTestCases.push_back(BTB); 1682 1683 return true; 1684} 1685 1686 1687// Clusterify - Transform simple list of Cases into list of CaseRange's 1688unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1689 const SwitchInst& SI) { 1690 unsigned numCmps = 0; 1691 1692 // Start with "simple" cases 1693 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1694 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1695 Cases.push_back(Case(SI.getSuccessorValue(i), 1696 SI.getSuccessorValue(i), 1697 SMBB)); 1698 } 1699 sort(Cases.begin(), Cases.end(), CaseCmp()); 1700 1701 // Merge case into clusters 1702 if (Cases.size()>=2) 1703 // Must recompute end() each iteration because it may be 1704 // invalidated by erase if we hold on to it 1705 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1706 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1707 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1708 MachineBasicBlock* nextBB = J->BB; 1709 MachineBasicBlock* currentBB = I->BB; 1710 1711 // If the two neighboring cases go to the same destination, merge them 1712 // into a single case. 1713 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1714 I->High = J->High; 1715 J = Cases.erase(J); 1716 } else { 1717 I = J++; 1718 } 1719 } 1720 1721 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1722 if (I->Low != I->High) 1723 // A range counts double, since it requires two compares. 1724 ++numCmps; 1725 } 1726 1727 return numCmps; 1728} 1729 1730void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1731 // Figure out which block is immediately after the current one. 1732 MachineBasicBlock *NextBlock = 0; 1733 MachineFunction::iterator BBI = CurMBB; 1734 1735 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1736 1737 // If there is only the default destination, branch to it if it is not the 1738 // next basic block. Otherwise, just fall through. 1739 if (SI.getNumOperands() == 2) { 1740 // Update machine-CFG edges. 1741 1742 // If this is not a fall-through branch, emit the branch. 1743 if (Default != NextBlock) 1744 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1745 DAG.getBasicBlock(Default))); 1746 1747 CurMBB->addSuccessor(Default); 1748 return; 1749 } 1750 1751 // If there are any non-default case statements, create a vector of Cases 1752 // representing each one, and sort the vector so that we can efficiently 1753 // create a binary search tree from them. 1754 CaseVector Cases; 1755 unsigned numCmps = Clusterify(Cases, SI); 1756 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1757 << ". Total compares: " << numCmps << "\n"; 1758 1759 // Get the Value to be switched on and default basic blocks, which will be 1760 // inserted into CaseBlock records, representing basic blocks in the binary 1761 // search tree. 1762 Value *SV = SI.getOperand(0); 1763 1764 // Push the initial CaseRec onto the worklist 1765 CaseRecVector WorkList; 1766 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1767 1768 while (!WorkList.empty()) { 1769 // Grab a record representing a case range to process off the worklist 1770 CaseRec CR = WorkList.back(); 1771 WorkList.pop_back(); 1772 1773 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1774 continue; 1775 1776 // If the range has few cases (two or less) emit a series of specific 1777 // tests. 1778 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1779 continue; 1780 1781 // If the switch has more than 5 blocks, and at least 40% dense, and the 1782 // target supports indirect branches, then emit a jump table rather than 1783 // lowering the switch to a binary tree of conditional branches. 1784 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1785 continue; 1786 1787 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1788 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1789 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1790 } 1791} 1792 1793 1794void SelectionDAGLowering::visitSub(User &I) { 1795 // -0.0 - X --> fneg 1796 const Type *Ty = I.getType(); 1797 if (isa<VectorType>(Ty)) { 1798 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 1799 const VectorType *DestTy = cast<VectorType>(I.getType()); 1800 const Type *ElTy = DestTy->getElementType(); 1801 if (ElTy->isFloatingPoint()) { 1802 unsigned VL = DestTy->getNumElements(); 1803 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0)); 1804 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 1805 if (CV == CNZ) { 1806 SDOperand Op2 = getValue(I.getOperand(1)); 1807 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1808 return; 1809 } 1810 } 1811 } 1812 } 1813 if (Ty->isFloatingPoint()) { 1814 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1815 if (CFP->isExactlyValue(-0.0)) { 1816 SDOperand Op2 = getValue(I.getOperand(1)); 1817 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1818 return; 1819 } 1820 } 1821 1822 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 1823} 1824 1825void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 1826 SDOperand Op1 = getValue(I.getOperand(0)); 1827 SDOperand Op2 = getValue(I.getOperand(1)); 1828 1829 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 1830} 1831 1832void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1833 SDOperand Op1 = getValue(I.getOperand(0)); 1834 SDOperand Op2 = getValue(I.getOperand(1)); 1835 1836 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 1837 MVT::getSizeInBits(Op2.getValueType())) 1838 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 1839 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 1840 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1841 1842 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1843} 1844 1845void SelectionDAGLowering::visitICmp(User &I) { 1846 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 1847 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 1848 predicate = IC->getPredicate(); 1849 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 1850 predicate = ICmpInst::Predicate(IC->getPredicate()); 1851 SDOperand Op1 = getValue(I.getOperand(0)); 1852 SDOperand Op2 = getValue(I.getOperand(1)); 1853 ISD::CondCode Opcode; 1854 switch (predicate) { 1855 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 1856 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 1857 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 1858 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 1859 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 1860 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 1861 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 1862 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 1863 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 1864 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 1865 default: 1866 assert(!"Invalid ICmp predicate value"); 1867 Opcode = ISD::SETEQ; 1868 break; 1869 } 1870 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1871} 1872 1873void SelectionDAGLowering::visitFCmp(User &I) { 1874 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 1875 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 1876 predicate = FC->getPredicate(); 1877 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 1878 predicate = FCmpInst::Predicate(FC->getPredicate()); 1879 SDOperand Op1 = getValue(I.getOperand(0)); 1880 SDOperand Op2 = getValue(I.getOperand(1)); 1881 ISD::CondCode Condition, FOC, FPC; 1882 switch (predicate) { 1883 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1884 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1885 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1886 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1887 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1888 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1889 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1890 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1891 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1892 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1893 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1894 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1895 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1896 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1897 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1898 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1899 default: 1900 assert(!"Invalid FCmp predicate value"); 1901 FOC = FPC = ISD::SETFALSE; 1902 break; 1903 } 1904 if (FiniteOnlyFPMath()) 1905 Condition = FOC; 1906 else 1907 Condition = FPC; 1908 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 1909} 1910 1911void SelectionDAGLowering::visitSelect(User &I) { 1912 SDOperand Cond = getValue(I.getOperand(0)); 1913 SDOperand TrueVal = getValue(I.getOperand(1)); 1914 SDOperand FalseVal = getValue(I.getOperand(2)); 1915 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 1916 TrueVal, FalseVal)); 1917} 1918 1919 1920void SelectionDAGLowering::visitTrunc(User &I) { 1921 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 1922 SDOperand N = getValue(I.getOperand(0)); 1923 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1924 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 1925} 1926 1927void SelectionDAGLowering::visitZExt(User &I) { 1928 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 1929 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 1930 SDOperand N = getValue(I.getOperand(0)); 1931 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1932 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 1933} 1934 1935void SelectionDAGLowering::visitSExt(User &I) { 1936 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 1937 // SExt also can't be a cast to bool for same reason. So, nothing much to do 1938 SDOperand N = getValue(I.getOperand(0)); 1939 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1940 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 1941} 1942 1943void SelectionDAGLowering::visitFPTrunc(User &I) { 1944 // FPTrunc is never a no-op cast, no need to check 1945 SDOperand N = getValue(I.getOperand(0)); 1946 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1947 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 1948} 1949 1950void SelectionDAGLowering::visitFPExt(User &I){ 1951 // FPTrunc is never a no-op cast, no need to check 1952 SDOperand N = getValue(I.getOperand(0)); 1953 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1954 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 1955} 1956 1957void SelectionDAGLowering::visitFPToUI(User &I) { 1958 // FPToUI is never a no-op cast, no need to check 1959 SDOperand N = getValue(I.getOperand(0)); 1960 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1961 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 1962} 1963 1964void SelectionDAGLowering::visitFPToSI(User &I) { 1965 // FPToSI is never a no-op cast, no need to check 1966 SDOperand N = getValue(I.getOperand(0)); 1967 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1968 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 1969} 1970 1971void SelectionDAGLowering::visitUIToFP(User &I) { 1972 // UIToFP is never a no-op cast, no need to check 1973 SDOperand N = getValue(I.getOperand(0)); 1974 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1975 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 1976} 1977 1978void SelectionDAGLowering::visitSIToFP(User &I){ 1979 // UIToFP is never a no-op cast, no need to check 1980 SDOperand N = getValue(I.getOperand(0)); 1981 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1982 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 1983} 1984 1985void SelectionDAGLowering::visitPtrToInt(User &I) { 1986 // What to do depends on the size of the integer and the size of the pointer. 1987 // We can either truncate, zero extend, or no-op, accordingly. 1988 SDOperand N = getValue(I.getOperand(0)); 1989 MVT::ValueType SrcVT = N.getValueType(); 1990 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1991 SDOperand Result; 1992 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 1993 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 1994 else 1995 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 1996 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 1997 setValue(&I, Result); 1998} 1999 2000void SelectionDAGLowering::visitIntToPtr(User &I) { 2001 // What to do depends on the size of the integer and the size of the pointer. 2002 // We can either truncate, zero extend, or no-op, accordingly. 2003 SDOperand N = getValue(I.getOperand(0)); 2004 MVT::ValueType SrcVT = N.getValueType(); 2005 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2006 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2007 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2008 else 2009 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2010 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2011} 2012 2013void SelectionDAGLowering::visitBitCast(User &I) { 2014 SDOperand N = getValue(I.getOperand(0)); 2015 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2016 2017 // BitCast assures us that source and destination are the same size so this 2018 // is either a BIT_CONVERT or a no-op. 2019 if (DestVT != N.getValueType()) 2020 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2021 else 2022 setValue(&I, N); // noop cast. 2023} 2024 2025void SelectionDAGLowering::visitInsertElement(User &I) { 2026 SDOperand InVec = getValue(I.getOperand(0)); 2027 SDOperand InVal = getValue(I.getOperand(1)); 2028 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2029 getValue(I.getOperand(2))); 2030 2031 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2032 TLI.getValueType(I.getType()), 2033 InVec, InVal, InIdx)); 2034} 2035 2036void SelectionDAGLowering::visitExtractElement(User &I) { 2037 SDOperand InVec = getValue(I.getOperand(0)); 2038 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2039 getValue(I.getOperand(1))); 2040 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2041 TLI.getValueType(I.getType()), InVec, InIdx)); 2042} 2043 2044void SelectionDAGLowering::visitShuffleVector(User &I) { 2045 SDOperand V1 = getValue(I.getOperand(0)); 2046 SDOperand V2 = getValue(I.getOperand(1)); 2047 SDOperand Mask = getValue(I.getOperand(2)); 2048 2049 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2050 TLI.getValueType(I.getType()), 2051 V1, V2, Mask)); 2052} 2053 2054 2055void SelectionDAGLowering::visitGetElementPtr(User &I) { 2056 SDOperand N = getValue(I.getOperand(0)); 2057 const Type *Ty = I.getOperand(0)->getType(); 2058 2059 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2060 OI != E; ++OI) { 2061 Value *Idx = *OI; 2062 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2063 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2064 if (Field) { 2065 // N = N + Offset 2066 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2067 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2068 getIntPtrConstant(Offset)); 2069 } 2070 Ty = StTy->getElementType(Field); 2071 } else { 2072 Ty = cast<SequentialType>(Ty)->getElementType(); 2073 2074 // If this is a constant subscript, handle it quickly. 2075 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2076 if (CI->getZExtValue() == 0) continue; 2077 uint64_t Offs = 2078 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2079 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2080 continue; 2081 } 2082 2083 // N = N + Idx * ElementSize; 2084 uint64_t ElementSize = TD->getTypeSize(Ty); 2085 SDOperand IdxN = getValue(Idx); 2086 2087 // If the index is smaller or larger than intptr_t, truncate or extend 2088 // it. 2089 if (IdxN.getValueType() < N.getValueType()) { 2090 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2091 } else if (IdxN.getValueType() > N.getValueType()) 2092 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2093 2094 // If this is a multiply by a power of two, turn it into a shl 2095 // immediately. This is a very common case. 2096 if (isPowerOf2_64(ElementSize)) { 2097 unsigned Amt = Log2_64(ElementSize); 2098 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2099 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2100 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2101 continue; 2102 } 2103 2104 SDOperand Scale = getIntPtrConstant(ElementSize); 2105 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2106 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2107 } 2108 } 2109 setValue(&I, N); 2110} 2111 2112void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2113 // If this is a fixed sized alloca in the entry block of the function, 2114 // allocate it statically on the stack. 2115 if (FuncInfo.StaticAllocaMap.count(&I)) 2116 return; // getValue will auto-populate this. 2117 2118 const Type *Ty = I.getAllocatedType(); 2119 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2120 unsigned Align = 2121 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2122 I.getAlignment()); 2123 2124 SDOperand AllocSize = getValue(I.getArraySize()); 2125 MVT::ValueType IntPtr = TLI.getPointerTy(); 2126 if (IntPtr < AllocSize.getValueType()) 2127 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2128 else if (IntPtr > AllocSize.getValueType()) 2129 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2130 2131 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2132 getIntPtrConstant(TySize)); 2133 2134 // Handle alignment. If the requested alignment is less than or equal to the 2135 // stack alignment, ignore it and round the size of the allocation up to the 2136 // stack alignment size. If the size is greater than the stack alignment, we 2137 // note this in the DYNAMIC_STACKALLOC node. 2138 unsigned StackAlign = 2139 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2140 if (Align <= StackAlign) { 2141 Align = 0; 2142 // Add SA-1 to the size. 2143 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2144 getIntPtrConstant(StackAlign-1)); 2145 // Mask out the low bits for alignment purposes. 2146 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2147 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2148 } 2149 2150 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2151 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2152 MVT::Other); 2153 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2154 setValue(&I, DSA); 2155 DAG.setRoot(DSA.getValue(1)); 2156 2157 // Inform the Frame Information that we have just allocated a variable-sized 2158 // object. 2159 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2160} 2161 2162void SelectionDAGLowering::visitLoad(LoadInst &I) { 2163 SDOperand Ptr = getValue(I.getOperand(0)); 2164 2165 SDOperand Root; 2166 if (I.isVolatile()) 2167 Root = getRoot(); 2168 else { 2169 // Do not serialize non-volatile loads against each other. 2170 Root = DAG.getRoot(); 2171 } 2172 2173 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2174 Root, I.isVolatile(), I.getAlignment())); 2175} 2176 2177SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2178 const Value *SV, SDOperand Root, 2179 bool isVolatile, 2180 unsigned Alignment) { 2181 SDOperand L = 2182 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2183 isVolatile, Alignment); 2184 2185 if (isVolatile) 2186 DAG.setRoot(L.getValue(1)); 2187 else 2188 PendingLoads.push_back(L.getValue(1)); 2189 2190 return L; 2191} 2192 2193 2194void SelectionDAGLowering::visitStore(StoreInst &I) { 2195 Value *SrcV = I.getOperand(0); 2196 SDOperand Src = getValue(SrcV); 2197 SDOperand Ptr = getValue(I.getOperand(1)); 2198 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2199 I.isVolatile(), I.getAlignment())); 2200} 2201 2202/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2203/// access memory and has no other side effects at all. 2204static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2205#define GET_NO_MEMORY_INTRINSICS 2206#include "llvm/Intrinsics.gen" 2207#undef GET_NO_MEMORY_INTRINSICS 2208 return false; 2209} 2210 2211// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2212// have any side-effects or if it only reads memory. 2213static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2214#define GET_SIDE_EFFECT_INFO 2215#include "llvm/Intrinsics.gen" 2216#undef GET_SIDE_EFFECT_INFO 2217 return false; 2218} 2219 2220/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2221/// node. 2222void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2223 unsigned Intrinsic) { 2224 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2225 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2226 2227 // Build the operand list. 2228 SmallVector<SDOperand, 8> Ops; 2229 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2230 if (OnlyLoad) { 2231 // We don't need to serialize loads against other loads. 2232 Ops.push_back(DAG.getRoot()); 2233 } else { 2234 Ops.push_back(getRoot()); 2235 } 2236 } 2237 2238 // Add the intrinsic ID as an integer operand. 2239 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2240 2241 // Add all operands of the call to the operand list. 2242 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2243 SDOperand Op = getValue(I.getOperand(i)); 2244 assert(TLI.isTypeLegal(Op.getValueType()) && 2245 "Intrinsic uses a non-legal type?"); 2246 Ops.push_back(Op); 2247 } 2248 2249 std::vector<MVT::ValueType> VTs; 2250 if (I.getType() != Type::VoidTy) { 2251 MVT::ValueType VT = TLI.getValueType(I.getType()); 2252 if (MVT::isVector(VT)) { 2253 const VectorType *DestTy = cast<VectorType>(I.getType()); 2254 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2255 2256 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2257 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2258 } 2259 2260 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2261 VTs.push_back(VT); 2262 } 2263 if (HasChain) 2264 VTs.push_back(MVT::Other); 2265 2266 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2267 2268 // Create the node. 2269 SDOperand Result; 2270 if (!HasChain) 2271 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2272 &Ops[0], Ops.size()); 2273 else if (I.getType() != Type::VoidTy) 2274 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2275 &Ops[0], Ops.size()); 2276 else 2277 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2278 &Ops[0], Ops.size()); 2279 2280 if (HasChain) { 2281 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2282 if (OnlyLoad) 2283 PendingLoads.push_back(Chain); 2284 else 2285 DAG.setRoot(Chain); 2286 } 2287 if (I.getType() != Type::VoidTy) { 2288 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2289 MVT::ValueType VT = TLI.getValueType(PTy); 2290 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2291 } 2292 setValue(&I, Result); 2293 } 2294} 2295 2296/// ExtractGlobalVariable - If C is a global variable, or a bitcast of one 2297/// (possibly constant folded), return it. Otherwise return NULL. 2298static GlobalVariable *ExtractGlobalVariable (Constant *C) { 2299 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) 2300 return GV; 2301 else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 2302 if (CE->getOpcode() == Instruction::BitCast) 2303 return dyn_cast<GlobalVariable>(CE->getOperand(0)); 2304 else if (CE->getOpcode() == Instruction::GetElementPtr) { 2305 for (unsigned i = 1, e = CE->getNumOperands(); i != e; ++i) 2306 if (!CE->getOperand(i)->isNullValue()) 2307 return NULL; 2308 return dyn_cast<GlobalVariable>(CE->getOperand(0)); 2309 } 2310 } 2311 return NULL; 2312} 2313 2314/// addCatchInfo - Extract the personality and type infos from an eh.selector 2315/// or eh.filter call, and add them to the specified machine basic block. 2316static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2317 MachineBasicBlock *MBB) { 2318 // Inform the MachineModuleInfo of the personality for this landing pad. 2319 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2320 assert(CE->getOpcode() == Instruction::BitCast && 2321 isa<Function>(CE->getOperand(0)) && 2322 "Personality should be a function"); 2323 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2324 2325 // Gather all the type infos for this landing pad and pass them along to 2326 // MachineModuleInfo. 2327 std::vector<GlobalVariable *> TyInfo; 2328 for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) { 2329 Constant *C = cast<Constant>(I.getOperand(i)); 2330 GlobalVariable *GV = ExtractGlobalVariable(C); 2331 assert (GV || isa<ConstantPointerNull>(C) && 2332 "TypeInfo must be a global variable or NULL"); 2333 TyInfo.push_back(GV); 2334 } 2335 if (I.getCalledFunction()->getIntrinsicID() == Intrinsic::eh_filter) 2336 MMI->addFilterTypeInfo(MBB, TyInfo); 2337 else 2338 MMI->addCatchTypeInfo(MBB, TyInfo); 2339} 2340 2341/// propagateEHRegister - The specified EH register is required in a successor 2342/// of the EH landing pad. Propagate it (by adding it to livein) to all the 2343/// blocks in the paths between the landing pad and the specified block. 2344static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg, 2345 SmallPtrSet<MachineBasicBlock*, 8> Visited) { 2346 if (MBB->isLandingPad() || !Visited.insert(MBB)) 2347 return; 2348 2349 MBB->addLiveIn(EHReg); 2350 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), 2351 E = MBB->pred_end(); PI != E; ++PI) 2352 propagateEHRegister(*PI, EHReg, Visited); 2353} 2354 2355static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg) { 2356 SmallPtrSet<MachineBasicBlock*, 8> Visited; 2357 propagateEHRegister(MBB, EHReg, Visited); 2358} 2359 2360/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2361/// we want to emit this as a call to a named external function, return the name 2362/// otherwise lower it and return null. 2363const char * 2364SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2365 switch (Intrinsic) { 2366 default: 2367 // By default, turn this into a target intrinsic node. 2368 visitTargetIntrinsic(I, Intrinsic); 2369 return 0; 2370 case Intrinsic::vastart: visitVAStart(I); return 0; 2371 case Intrinsic::vaend: visitVAEnd(I); return 0; 2372 case Intrinsic::vacopy: visitVACopy(I); return 0; 2373 case Intrinsic::returnaddress: 2374 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2375 getValue(I.getOperand(1)))); 2376 return 0; 2377 case Intrinsic::frameaddress: 2378 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2379 getValue(I.getOperand(1)))); 2380 return 0; 2381 case Intrinsic::setjmp: 2382 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2383 break; 2384 case Intrinsic::longjmp: 2385 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2386 break; 2387 case Intrinsic::memcpy_i32: 2388 case Intrinsic::memcpy_i64: 2389 visitMemIntrinsic(I, ISD::MEMCPY); 2390 return 0; 2391 case Intrinsic::memset_i32: 2392 case Intrinsic::memset_i64: 2393 visitMemIntrinsic(I, ISD::MEMSET); 2394 return 0; 2395 case Intrinsic::memmove_i32: 2396 case Intrinsic::memmove_i64: 2397 visitMemIntrinsic(I, ISD::MEMMOVE); 2398 return 0; 2399 2400 case Intrinsic::dbg_stoppoint: { 2401 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2402 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2403 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2404 SDOperand Ops[5]; 2405 2406 Ops[0] = getRoot(); 2407 Ops[1] = getValue(SPI.getLineValue()); 2408 Ops[2] = getValue(SPI.getColumnValue()); 2409 2410 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2411 assert(DD && "Not a debug information descriptor"); 2412 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2413 2414 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2415 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2416 2417 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2418 } 2419 2420 return 0; 2421 } 2422 case Intrinsic::dbg_region_start: { 2423 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2424 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2425 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2426 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2427 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2428 DAG.getConstant(LabelID, MVT::i32))); 2429 } 2430 2431 return 0; 2432 } 2433 case Intrinsic::dbg_region_end: { 2434 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2435 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2436 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2437 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2438 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2439 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2440 } 2441 2442 return 0; 2443 } 2444 case Intrinsic::dbg_func_start: { 2445 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2446 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2447 if (MMI && FSI.getSubprogram() && 2448 MMI->Verify(FSI.getSubprogram())) { 2449 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2450 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2451 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2452 } 2453 2454 return 0; 2455 } 2456 case Intrinsic::dbg_declare: { 2457 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2458 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2459 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2460 SDOperand AddressOp = getValue(DI.getAddress()); 2461 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2462 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2463 } 2464 2465 return 0; 2466 } 2467 2468 case Intrinsic::eh_exception: { 2469 if (ExceptionHandling) { 2470 if (!CurMBB->isLandingPad() && TLI.getExceptionAddressRegister()) 2471 propagateEHRegister(CurMBB, TLI.getExceptionAddressRegister()); 2472 2473 // Insert the EXCEPTIONADDR instruction. 2474 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2475 SDOperand Ops[1]; 2476 Ops[0] = DAG.getRoot(); 2477 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2478 setValue(&I, Op); 2479 DAG.setRoot(Op.getValue(1)); 2480 } else { 2481 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2482 } 2483 return 0; 2484 } 2485 2486 case Intrinsic::eh_selector: 2487 case Intrinsic::eh_filter:{ 2488 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2489 2490 if (ExceptionHandling && MMI) { 2491 if (CurMBB->isLandingPad()) 2492 addCatchInfo(I, MMI, CurMBB); 2493 else { 2494#ifndef NDEBUG 2495 FuncInfo.CatchInfoLost.insert(&I); 2496#endif 2497 if (TLI.getExceptionSelectorRegister()) 2498 propagateEHRegister(CurMBB, TLI.getExceptionSelectorRegister()); 2499 } 2500 2501 // Insert the EHSELECTION instruction. 2502 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2503 SDOperand Ops[2]; 2504 Ops[0] = getValue(I.getOperand(1)); 2505 Ops[1] = getRoot(); 2506 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2507 setValue(&I, Op); 2508 DAG.setRoot(Op.getValue(1)); 2509 } else { 2510 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2511 } 2512 2513 return 0; 2514 } 2515 2516 case Intrinsic::eh_typeid_for: { 2517 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2518 2519 if (MMI) { 2520 // Find the type id for the given typeinfo. 2521 Constant *C = cast<Constant>(I.getOperand(1)); 2522 GlobalVariable *GV = ExtractGlobalVariable(C); 2523 assert (GV || isa<ConstantPointerNull>(C) && 2524 "TypeInfo must be a global variable or NULL"); 2525 2526 unsigned TypeID = MMI->getTypeIDFor(GV); 2527 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2528 } else { 2529 setValue(&I, DAG.getConstant(0, MVT::i32)); 2530 } 2531 2532 return 0; 2533 } 2534 2535 case Intrinsic::sqrt_f32: 2536 case Intrinsic::sqrt_f64: 2537 setValue(&I, DAG.getNode(ISD::FSQRT, 2538 getValue(I.getOperand(1)).getValueType(), 2539 getValue(I.getOperand(1)))); 2540 return 0; 2541 case Intrinsic::powi_f32: 2542 case Intrinsic::powi_f64: 2543 setValue(&I, DAG.getNode(ISD::FPOWI, 2544 getValue(I.getOperand(1)).getValueType(), 2545 getValue(I.getOperand(1)), 2546 getValue(I.getOperand(2)))); 2547 return 0; 2548 case Intrinsic::pcmarker: { 2549 SDOperand Tmp = getValue(I.getOperand(1)); 2550 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2551 return 0; 2552 } 2553 case Intrinsic::readcyclecounter: { 2554 SDOperand Op = getRoot(); 2555 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2556 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2557 &Op, 1); 2558 setValue(&I, Tmp); 2559 DAG.setRoot(Tmp.getValue(1)); 2560 return 0; 2561 } 2562 case Intrinsic::part_select: { 2563 // Currently not implemented: just abort 2564 assert(0 && "part_select intrinsic not implemented"); 2565 abort(); 2566 } 2567 case Intrinsic::part_set: { 2568 // Currently not implemented: just abort 2569 assert(0 && "part_set intrinsic not implemented"); 2570 abort(); 2571 } 2572 case Intrinsic::bswap: 2573 setValue(&I, DAG.getNode(ISD::BSWAP, 2574 getValue(I.getOperand(1)).getValueType(), 2575 getValue(I.getOperand(1)))); 2576 return 0; 2577 case Intrinsic::cttz: { 2578 SDOperand Arg = getValue(I.getOperand(1)); 2579 MVT::ValueType Ty = Arg.getValueType(); 2580 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2581 if (Ty < MVT::i32) 2582 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2583 else if (Ty > MVT::i32) 2584 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2585 setValue(&I, result); 2586 return 0; 2587 } 2588 case Intrinsic::ctlz: { 2589 SDOperand Arg = getValue(I.getOperand(1)); 2590 MVT::ValueType Ty = Arg.getValueType(); 2591 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2592 if (Ty < MVT::i32) 2593 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2594 else if (Ty > MVT::i32) 2595 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2596 setValue(&I, result); 2597 return 0; 2598 } 2599 case Intrinsic::ctpop: { 2600 SDOperand Arg = getValue(I.getOperand(1)); 2601 MVT::ValueType Ty = Arg.getValueType(); 2602 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2603 if (Ty < MVT::i32) 2604 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2605 else if (Ty > MVT::i32) 2606 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2607 setValue(&I, result); 2608 return 0; 2609 } 2610 case Intrinsic::stacksave: { 2611 SDOperand Op = getRoot(); 2612 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2613 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2614 setValue(&I, Tmp); 2615 DAG.setRoot(Tmp.getValue(1)); 2616 return 0; 2617 } 2618 case Intrinsic::stackrestore: { 2619 SDOperand Tmp = getValue(I.getOperand(1)); 2620 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2621 return 0; 2622 } 2623 case Intrinsic::prefetch: 2624 // FIXME: Currently discarding prefetches. 2625 return 0; 2626 2627 case Intrinsic::var_annotation: 2628 // Discard annotate attributes 2629 return 0; 2630 } 2631} 2632 2633 2634void SelectionDAGLowering::LowerCallTo(Instruction &I, 2635 const Type *CalledValueTy, 2636 unsigned CallingConv, 2637 bool IsTailCall, 2638 SDOperand Callee, unsigned OpIdx, 2639 MachineBasicBlock *LandingPad) { 2640 const PointerType *PT = cast<PointerType>(CalledValueTy); 2641 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2642 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2643 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2644 unsigned BeginLabel = 0, EndLabel = 0; 2645 2646 TargetLowering::ArgListTy Args; 2647 TargetLowering::ArgListEntry Entry; 2648 Args.reserve(I.getNumOperands()); 2649 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2650 Value *Arg = I.getOperand(i); 2651 SDOperand ArgNode = getValue(Arg); 2652 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2653 2654 unsigned attrInd = i - OpIdx + 1; 2655 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2656 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2657 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2658 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2659 Args.push_back(Entry); 2660 } 2661 2662 if (ExceptionHandling && MMI) { 2663 // Insert a label before the invoke call to mark the try range. This can be 2664 // used to detect deletion of the invoke via the MachineModuleInfo. 2665 BeginLabel = MMI->NextLabelID(); 2666 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2667 DAG.getConstant(BeginLabel, MVT::i32))); 2668 } 2669 2670 std::pair<SDOperand,SDOperand> Result = 2671 TLI.LowerCallTo(getRoot(), I.getType(), 2672 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2673 FTy->isVarArg(), CallingConv, IsTailCall, 2674 Callee, Args, DAG); 2675 if (I.getType() != Type::VoidTy) 2676 setValue(&I, Result.first); 2677 DAG.setRoot(Result.second); 2678 2679 if (ExceptionHandling && MMI) { 2680 // Insert a label at the end of the invoke call to mark the try range. This 2681 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2682 EndLabel = MMI->NextLabelID(); 2683 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2684 DAG.getConstant(EndLabel, MVT::i32))); 2685 2686 // Inform MachineModuleInfo of range. 2687 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2688 } 2689} 2690 2691 2692void SelectionDAGLowering::visitCall(CallInst &I) { 2693 const char *RenameFn = 0; 2694 if (Function *F = I.getCalledFunction()) { 2695 if (F->isDeclaration()) 2696 if (unsigned IID = F->getIntrinsicID()) { 2697 RenameFn = visitIntrinsicCall(I, IID); 2698 if (!RenameFn) 2699 return; 2700 } else { // Not an LLVM intrinsic. 2701 const std::string &Name = F->getName(); 2702 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2703 if (I.getNumOperands() == 3 && // Basic sanity checks. 2704 I.getOperand(1)->getType()->isFloatingPoint() && 2705 I.getType() == I.getOperand(1)->getType() && 2706 I.getType() == I.getOperand(2)->getType()) { 2707 SDOperand LHS = getValue(I.getOperand(1)); 2708 SDOperand RHS = getValue(I.getOperand(2)); 2709 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2710 LHS, RHS)); 2711 return; 2712 } 2713 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2714 if (I.getNumOperands() == 2 && // Basic sanity checks. 2715 I.getOperand(1)->getType()->isFloatingPoint() && 2716 I.getType() == I.getOperand(1)->getType()) { 2717 SDOperand Tmp = getValue(I.getOperand(1)); 2718 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2719 return; 2720 } 2721 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2722 if (I.getNumOperands() == 2 && // Basic sanity checks. 2723 I.getOperand(1)->getType()->isFloatingPoint() && 2724 I.getType() == I.getOperand(1)->getType()) { 2725 SDOperand Tmp = getValue(I.getOperand(1)); 2726 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2727 return; 2728 } 2729 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2730 if (I.getNumOperands() == 2 && // Basic sanity checks. 2731 I.getOperand(1)->getType()->isFloatingPoint() && 2732 I.getType() == I.getOperand(1)->getType()) { 2733 SDOperand Tmp = getValue(I.getOperand(1)); 2734 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2735 return; 2736 } 2737 } 2738 } 2739 } else if (isa<InlineAsm>(I.getOperand(0))) { 2740 visitInlineAsm(I); 2741 return; 2742 } 2743 2744 SDOperand Callee; 2745 if (!RenameFn) 2746 Callee = getValue(I.getOperand(0)); 2747 else 2748 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2749 2750 LowerCallTo(I, I.getCalledValue()->getType(), 2751 I.getCallingConv(), 2752 I.isTailCall(), 2753 Callee, 2754 1); 2755} 2756 2757 2758/// getCopyFromParts - Create a value that contains the 2759/// specified legal parts combined into the value they represent. 2760static SDOperand getCopyFromParts(SelectionDAG &DAG, 2761 const SDOperand *Parts, 2762 unsigned NumParts, 2763 MVT::ValueType PartVT, 2764 MVT::ValueType ValueVT, 2765 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 2766 if (!MVT::isVector(ValueVT) || NumParts == 1) { 2767 SDOperand Val = Parts[0]; 2768 2769 // If the value was expanded, copy from the top part. 2770 if (NumParts > 1) { 2771 assert(NumParts == 2 && 2772 "Cannot expand to more than 2 elts yet!"); 2773 SDOperand Hi = Parts[1]; 2774 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 2775 } 2776 2777 // Otherwise, if the value was promoted or extended, truncate it to the 2778 // appropriate type. 2779 if (PartVT == ValueVT) 2780 return Val; 2781 2782 if (MVT::isVector(PartVT)) { 2783 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 2784 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 2785 } 2786 2787 if (MVT::isInteger(PartVT) && 2788 MVT::isInteger(ValueVT)) { 2789 if (ValueVT < PartVT) { 2790 // For a truncate, see if we have any information to 2791 // indicate whether the truncated bits will always be 2792 // zero or sign-extension. 2793 if (AssertOp != ISD::DELETED_NODE) 2794 Val = DAG.getNode(AssertOp, PartVT, Val, 2795 DAG.getValueType(ValueVT)); 2796 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 2797 } else { 2798 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 2799 } 2800 } 2801 2802 if (MVT::isFloatingPoint(PartVT) && 2803 MVT::isFloatingPoint(ValueVT)) 2804 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 2805 2806 if (MVT::getSizeInBits(PartVT) == 2807 MVT::getSizeInBits(ValueVT)) 2808 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 2809 2810 assert(0 && "Unknown mismatch!"); 2811 } 2812 2813 // Handle a multi-element vector. 2814 MVT::ValueType IntermediateVT, RegisterVT; 2815 unsigned NumIntermediates; 2816 unsigned NumRegs = 2817 DAG.getTargetLoweringInfo() 2818 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 2819 RegisterVT); 2820 2821 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 2822 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 2823 assert(RegisterVT == Parts[0].getValueType() && 2824 "Part type doesn't match part!"); 2825 2826 // Assemble the parts into intermediate operands. 2827 SmallVector<SDOperand, 8> Ops(NumIntermediates); 2828 if (NumIntermediates == NumParts) { 2829 // If the register was not expanded, truncate or copy the value, 2830 // as appropriate. 2831 for (unsigned i = 0; i != NumParts; ++i) 2832 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, PartVT, IntermediateVT); 2833 } else if (NumParts > 0) { 2834 // If the intermediate type was expanded, build the intermediate operands 2835 // from the parts. 2836 assert(NumIntermediates % NumParts == 0 && 2837 "Must expand into a divisible number of parts!"); 2838 unsigned Factor = NumIntermediates / NumParts; 2839 for (unsigned i = 0; i != NumIntermediates; ++i) 2840 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 2841 PartVT, IntermediateVT); 2842 } 2843 2844 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 2845 // operands. 2846 return DAG.getNode(MVT::isVector(IntermediateVT) ? 2847 ISD::CONCAT_VECTORS : 2848 ISD::BUILD_VECTOR, 2849 ValueVT, &Ops[0], NumParts); 2850} 2851 2852/// getCopyToParts - Create a series of nodes that contain the 2853/// specified value split into legal parts. 2854static void getCopyToParts(SelectionDAG &DAG, 2855 SDOperand Val, 2856 SDOperand *Parts, 2857 unsigned NumParts, 2858 MVT::ValueType PartVT) { 2859 MVT::ValueType ValueVT = Val.getValueType(); 2860 2861 if (!MVT::isVector(ValueVT) || NumParts == 1) { 2862 // If the value was expanded, copy from the parts. 2863 if (NumParts > 1) { 2864 for (unsigned i = 0; i != NumParts; ++i) 2865 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 2866 DAG.getConstant(i, MVT::i32)); 2867 return; 2868 } 2869 2870 // If there is a single part and the types differ, this must be 2871 // a promotion. 2872 if (PartVT != ValueVT) { 2873 if (MVT::isVector(PartVT)) { 2874 assert(MVT::isVector(ValueVT) && 2875 "Not a vector-vector cast?"); 2876 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 2877 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 2878 if (PartVT < ValueVT) 2879 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 2880 else 2881 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 2882 } else if (MVT::isFloatingPoint(PartVT) && 2883 MVT::isFloatingPoint(ValueVT)) { 2884 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 2885 } else if (MVT::getSizeInBits(PartVT) == 2886 MVT::getSizeInBits(ValueVT)) { 2887 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 2888 } else { 2889 assert(0 && "Unknown mismatch!"); 2890 } 2891 } 2892 Parts[0] = Val; 2893 return; 2894 } 2895 2896 // Handle a multi-element vector. 2897 MVT::ValueType IntermediateVT, RegisterVT; 2898 unsigned NumIntermediates; 2899 unsigned NumRegs = 2900 DAG.getTargetLoweringInfo() 2901 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 2902 RegisterVT); 2903 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 2904 2905 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 2906 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 2907 2908 // Split the vector into intermediate operands. 2909 SmallVector<SDOperand, 8> Ops(NumIntermediates); 2910 for (unsigned i = 0; i != NumIntermediates; ++i) 2911 if (MVT::isVector(IntermediateVT)) 2912 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 2913 IntermediateVT, Val, 2914 DAG.getConstant(i * (NumElements / NumIntermediates), 2915 MVT::i32)); 2916 else 2917 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2918 IntermediateVT, Val, 2919 DAG.getConstant(i, MVT::i32)); 2920 2921 // Split the intermediate operands into legal parts. 2922 if (NumParts == NumIntermediates) { 2923 // If the register was not expanded, promote or copy the value, 2924 // as appropriate. 2925 for (unsigned i = 0; i != NumParts; ++i) 2926 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 2927 } else if (NumParts > 0) { 2928 // If the intermediate type was expanded, split each the value into 2929 // legal parts. 2930 assert(NumParts % NumIntermediates == 0 && 2931 "Must expand into a divisible number of parts!"); 2932 unsigned Factor = NumParts / NumIntermediates; 2933 for (unsigned i = 0; i != NumIntermediates; ++i) 2934 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 2935 } 2936} 2937 2938 2939/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 2940/// this value and returns the result as a ValueVT value. This uses 2941/// Chain/Flag as the input and updates them for the output Chain/Flag. 2942/// If the Flag pointer is NULL, no flag is used. 2943SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2944 SDOperand &Chain, SDOperand *Flag)const{ 2945 // Get the list of registers, in the appropriate order. 2946 std::vector<unsigned> R(Regs); 2947 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2948 std::reverse(R.begin(), R.end()); 2949 2950 // Copy the legal parts from the registers. 2951 unsigned NumParts = Regs.size(); 2952 SmallVector<SDOperand, 8> Parts(NumParts); 2953 for (unsigned i = 0; i != NumParts; ++i) { 2954 SDOperand Part = Flag ? 2955 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 2956 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 2957 Chain = Part.getValue(1); 2958 if (Flag) 2959 *Flag = Part.getValue(2); 2960 Parts[i] = Part; 2961 } 2962 2963 // Assemble the legal parts into the final value. 2964 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 2965} 2966 2967/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 2968/// specified value into the registers specified by this object. This uses 2969/// Chain/Flag as the input and updates them for the output Chain/Flag. 2970/// If the Flag pointer is NULL, no flag is used. 2971void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 2972 SDOperand &Chain, SDOperand *Flag) const { 2973 // Get the list of registers, in the appropriate order. 2974 std::vector<unsigned> R(Regs); 2975 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2976 std::reverse(R.begin(), R.end()); 2977 2978 // Get the list of the values's legal parts. 2979 unsigned NumParts = Regs.size(); 2980 SmallVector<SDOperand, 8> Parts(NumParts); 2981 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 2982 2983 // Copy the parts into the registers. 2984 for (unsigned i = 0; i != NumParts; ++i) { 2985 SDOperand Part = Flag ? 2986 DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) : 2987 DAG.getCopyToReg(Chain, R[i], Parts[i]); 2988 Chain = Part.getValue(0); 2989 if (Flag) 2990 *Flag = Part.getValue(1); 2991 } 2992} 2993 2994/// AddInlineAsmOperands - Add this value to the specified inlineasm node 2995/// operand list. This adds the code marker and includes the number of 2996/// values added into it. 2997void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 2998 std::vector<SDOperand> &Ops) const { 2999 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3000 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3001 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3002 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3003} 3004 3005/// isAllocatableRegister - If the specified register is safe to allocate, 3006/// i.e. it isn't a stack pointer or some other special register, return the 3007/// register class for the register. Otherwise, return null. 3008static const TargetRegisterClass * 3009isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3010 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3011 MVT::ValueType FoundVT = MVT::Other; 3012 const TargetRegisterClass *FoundRC = 0; 3013 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3014 E = MRI->regclass_end(); RCI != E; ++RCI) { 3015 MVT::ValueType ThisVT = MVT::Other; 3016 3017 const TargetRegisterClass *RC = *RCI; 3018 // If none of the the value types for this register class are valid, we 3019 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3020 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3021 I != E; ++I) { 3022 if (TLI.isTypeLegal(*I)) { 3023 // If we have already found this register in a different register class, 3024 // choose the one with the largest VT specified. For example, on 3025 // PowerPC, we favor f64 register classes over f32. 3026 if (FoundVT == MVT::Other || 3027 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3028 ThisVT = *I; 3029 break; 3030 } 3031 } 3032 } 3033 3034 if (ThisVT == MVT::Other) continue; 3035 3036 // NOTE: This isn't ideal. In particular, this might allocate the 3037 // frame pointer in functions that need it (due to them not being taken 3038 // out of allocation, because a variable sized allocation hasn't been seen 3039 // yet). This is a slight code pessimization, but should still work. 3040 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3041 E = RC->allocation_order_end(MF); I != E; ++I) 3042 if (*I == Reg) { 3043 // We found a matching register class. Keep looking at others in case 3044 // we find one with larger registers that this physreg is also in. 3045 FoundRC = RC; 3046 FoundVT = ThisVT; 3047 break; 3048 } 3049 } 3050 return FoundRC; 3051} 3052 3053 3054namespace { 3055/// AsmOperandInfo - This contains information for each constraint that we are 3056/// lowering. 3057struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3058 /// ConstraintCode - This contains the actual string for the code, like "m". 3059 std::string ConstraintCode; 3060 3061 /// ConstraintType - Information about the constraint code, e.g. Register, 3062 /// RegisterClass, Memory, Other, Unknown. 3063 TargetLowering::ConstraintType ConstraintType; 3064 3065 /// CallOperand/CallOperandval - If this is the result output operand or a 3066 /// clobber, this is null, otherwise it is the incoming operand to the 3067 /// CallInst. This gets modified as the asm is processed. 3068 SDOperand CallOperand; 3069 Value *CallOperandVal; 3070 3071 /// ConstraintVT - The ValueType for the operand value. 3072 MVT::ValueType ConstraintVT; 3073 3074 /// AssignedRegs - If this is a register or register class operand, this 3075 /// contains the set of register corresponding to the operand. 3076 RegsForValue AssignedRegs; 3077 3078 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3079 : InlineAsm::ConstraintInfo(info), 3080 ConstraintType(TargetLowering::C_Unknown), 3081 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3082 } 3083 3084 void ComputeConstraintToUse(const TargetLowering &TLI); 3085 3086 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3087 /// busy in OutputRegs/InputRegs. 3088 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3089 std::set<unsigned> &OutputRegs, 3090 std::set<unsigned> &InputRegs) const { 3091 if (isOutReg) 3092 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3093 if (isInReg) 3094 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3095 } 3096}; 3097} // end anon namespace. 3098 3099/// getConstraintGenerality - Return an integer indicating how general CT is. 3100static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3101 switch (CT) { 3102 default: assert(0 && "Unknown constraint type!"); 3103 case TargetLowering::C_Other: 3104 case TargetLowering::C_Unknown: 3105 return 0; 3106 case TargetLowering::C_Register: 3107 return 1; 3108 case TargetLowering::C_RegisterClass: 3109 return 2; 3110 case TargetLowering::C_Memory: 3111 return 3; 3112 } 3113} 3114 3115void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3116 assert(!Codes.empty() && "Must have at least one constraint"); 3117 3118 std::string *Current = &Codes[0]; 3119 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3120 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3121 ConstraintCode = *Current; 3122 ConstraintType = CurType; 3123 return; 3124 } 3125 3126 unsigned CurGenerality = getConstraintGenerality(CurType); 3127 3128 // If we have multiple constraints, try to pick the most general one ahead 3129 // of time. This isn't a wonderful solution, but handles common cases. 3130 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3131 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3132 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3133 if (ThisGenerality > CurGenerality) { 3134 // This constraint letter is more general than the previous one, 3135 // use it. 3136 CurType = ThisType; 3137 Current = &Codes[j]; 3138 CurGenerality = ThisGenerality; 3139 } 3140 } 3141 3142 ConstraintCode = *Current; 3143 ConstraintType = CurType; 3144} 3145 3146 3147void SelectionDAGLowering:: 3148GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3149 std::set<unsigned> &OutputRegs, 3150 std::set<unsigned> &InputRegs) { 3151 // Compute whether this value requires an input register, an output register, 3152 // or both. 3153 bool isOutReg = false; 3154 bool isInReg = false; 3155 switch (OpInfo.Type) { 3156 case InlineAsm::isOutput: 3157 isOutReg = true; 3158 3159 // If this is an early-clobber output, or if there is an input 3160 // constraint that matches this, we need to reserve the input register 3161 // so no other inputs allocate to it. 3162 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3163 break; 3164 case InlineAsm::isInput: 3165 isInReg = true; 3166 isOutReg = false; 3167 break; 3168 case InlineAsm::isClobber: 3169 isOutReg = true; 3170 isInReg = true; 3171 break; 3172 } 3173 3174 3175 MachineFunction &MF = DAG.getMachineFunction(); 3176 std::vector<unsigned> Regs; 3177 3178 // If this is a constraint for a single physreg, or a constraint for a 3179 // register class, find it. 3180 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3181 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3182 OpInfo.ConstraintVT); 3183 3184 unsigned NumRegs = 1; 3185 if (OpInfo.ConstraintVT != MVT::Other) 3186 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3187 MVT::ValueType RegVT; 3188 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3189 3190 3191 // If this is a constraint for a specific physical register, like {r17}, 3192 // assign it now. 3193 if (PhysReg.first) { 3194 if (OpInfo.ConstraintVT == MVT::Other) 3195 ValueVT = *PhysReg.second->vt_begin(); 3196 3197 // Get the actual register value type. This is important, because the user 3198 // may have asked for (e.g.) the AX register in i32 type. We need to 3199 // remember that AX is actually i16 to get the right extension. 3200 RegVT = *PhysReg.second->vt_begin(); 3201 3202 // This is a explicit reference to a physical register. 3203 Regs.push_back(PhysReg.first); 3204 3205 // If this is an expanded reference, add the rest of the regs to Regs. 3206 if (NumRegs != 1) { 3207 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3208 TargetRegisterClass::iterator E = PhysReg.second->end(); 3209 for (; *I != PhysReg.first; ++I) 3210 assert(I != E && "Didn't find reg!"); 3211 3212 // Already added the first reg. 3213 --NumRegs; ++I; 3214 for (; NumRegs; --NumRegs, ++I) { 3215 assert(I != E && "Ran out of registers to allocate!"); 3216 Regs.push_back(*I); 3217 } 3218 } 3219 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3220 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3221 return; 3222 } 3223 3224 // Otherwise, if this was a reference to an LLVM register class, create vregs 3225 // for this reference. 3226 std::vector<unsigned> RegClassRegs; 3227 const TargetRegisterClass *RC = PhysReg.second; 3228 if (RC) { 3229 // If this is an early clobber or tied register, our regalloc doesn't know 3230 // how to maintain the constraint. If it isn't, go ahead and create vreg 3231 // and let the regalloc do the right thing. 3232 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3233 // If there is some other early clobber and this is an input register, 3234 // then we are forced to pre-allocate the input reg so it doesn't 3235 // conflict with the earlyclobber. 3236 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3237 RegVT = *PhysReg.second->vt_begin(); 3238 3239 if (OpInfo.ConstraintVT == MVT::Other) 3240 ValueVT = RegVT; 3241 3242 // Create the appropriate number of virtual registers. 3243 SSARegMap *RegMap = MF.getSSARegMap(); 3244 for (; NumRegs; --NumRegs) 3245 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3246 3247 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3248 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3249 return; 3250 } 3251 3252 // Otherwise, we can't allocate it. Let the code below figure out how to 3253 // maintain these constraints. 3254 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3255 3256 } else { 3257 // This is a reference to a register class that doesn't directly correspond 3258 // to an LLVM register class. Allocate NumRegs consecutive, available, 3259 // registers from the class. 3260 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3261 OpInfo.ConstraintVT); 3262 } 3263 3264 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3265 unsigned NumAllocated = 0; 3266 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3267 unsigned Reg = RegClassRegs[i]; 3268 // See if this register is available. 3269 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3270 (isInReg && InputRegs.count(Reg))) { // Already used. 3271 // Make sure we find consecutive registers. 3272 NumAllocated = 0; 3273 continue; 3274 } 3275 3276 // Check to see if this register is allocatable (i.e. don't give out the 3277 // stack pointer). 3278 if (RC == 0) { 3279 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3280 if (!RC) { // Couldn't allocate this register. 3281 // Reset NumAllocated to make sure we return consecutive registers. 3282 NumAllocated = 0; 3283 continue; 3284 } 3285 } 3286 3287 // Okay, this register is good, we can use it. 3288 ++NumAllocated; 3289 3290 // If we allocated enough consecutive registers, succeed. 3291 if (NumAllocated == NumRegs) { 3292 unsigned RegStart = (i-NumAllocated)+1; 3293 unsigned RegEnd = i+1; 3294 // Mark all of the allocated registers used. 3295 for (unsigned i = RegStart; i != RegEnd; ++i) 3296 Regs.push_back(RegClassRegs[i]); 3297 3298 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3299 OpInfo.ConstraintVT); 3300 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3301 return; 3302 } 3303 } 3304 3305 // Otherwise, we couldn't allocate enough registers for this. 3306 return; 3307} 3308 3309 3310/// visitInlineAsm - Handle a call to an InlineAsm object. 3311/// 3312void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3313 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3314 3315 /// ConstraintOperands - Information about all of the constraints. 3316 std::vector<AsmOperandInfo> ConstraintOperands; 3317 3318 SDOperand Chain = getRoot(); 3319 SDOperand Flag; 3320 3321 std::set<unsigned> OutputRegs, InputRegs; 3322 3323 // Do a prepass over the constraints, canonicalizing them, and building up the 3324 // ConstraintOperands list. 3325 std::vector<InlineAsm::ConstraintInfo> 3326 ConstraintInfos = IA->ParseConstraints(); 3327 3328 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3329 // constraint. If so, we can't let the register allocator allocate any input 3330 // registers, because it will not know to avoid the earlyclobbered output reg. 3331 bool SawEarlyClobber = false; 3332 3333 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3334 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3335 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3336 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3337 3338 MVT::ValueType OpVT = MVT::Other; 3339 3340 // Compute the value type for each operand. 3341 switch (OpInfo.Type) { 3342 case InlineAsm::isOutput: 3343 if (!OpInfo.isIndirect) { 3344 // The return value of the call is this value. As such, there is no 3345 // corresponding argument. 3346 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3347 OpVT = TLI.getValueType(I.getType()); 3348 } else { 3349 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3350 } 3351 break; 3352 case InlineAsm::isInput: 3353 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3354 break; 3355 case InlineAsm::isClobber: 3356 // Nothing to do. 3357 break; 3358 } 3359 3360 // If this is an input or an indirect output, process the call argument. 3361 if (OpInfo.CallOperandVal) { 3362 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3363 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3364 // If this is an indirect operand, the operand is a pointer to the 3365 // accessed type. 3366 if (OpInfo.isIndirect) 3367 OpTy = cast<PointerType>(OpTy)->getElementType(); 3368 3369 // If OpTy is not a first-class value, it may be a struct/union that we 3370 // can tile with integers. 3371 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3372 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3373 switch (BitSize) { 3374 default: break; 3375 case 1: 3376 case 8: 3377 case 16: 3378 case 32: 3379 case 64: 3380 OpTy = IntegerType::get(BitSize); 3381 break; 3382 } 3383 } 3384 3385 OpVT = TLI.getValueType(OpTy, true); 3386 } 3387 3388 OpInfo.ConstraintVT = OpVT; 3389 3390 // Compute the constraint code and ConstraintType to use. 3391 OpInfo.ComputeConstraintToUse(TLI); 3392 3393 // Keep track of whether we see an earlyclobber. 3394 SawEarlyClobber |= OpInfo.isEarlyClobber; 3395 3396 // If this is a memory input, and if the operand is not indirect, do what we 3397 // need to to provide an address for the memory input. 3398 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3399 !OpInfo.isIndirect) { 3400 assert(OpInfo.Type == InlineAsm::isInput && 3401 "Can only indirectify direct input operands!"); 3402 3403 // Memory operands really want the address of the value. If we don't have 3404 // an indirect input, put it in the constpool if we can, otherwise spill 3405 // it to a stack slot. 3406 3407 // If the operand is a float, integer, or vector constant, spill to a 3408 // constant pool entry to get its address. 3409 Value *OpVal = OpInfo.CallOperandVal; 3410 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3411 isa<ConstantVector>(OpVal)) { 3412 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3413 TLI.getPointerTy()); 3414 } else { 3415 // Otherwise, create a stack slot and emit a store to it before the 3416 // asm. 3417 const Type *Ty = OpVal->getType(); 3418 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3419 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3420 MachineFunction &MF = DAG.getMachineFunction(); 3421 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3422 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3423 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3424 OpInfo.CallOperand = StackSlot; 3425 } 3426 3427 // There is no longer a Value* corresponding to this operand. 3428 OpInfo.CallOperandVal = 0; 3429 // It is now an indirect operand. 3430 OpInfo.isIndirect = true; 3431 } 3432 3433 // If this constraint is for a specific register, allocate it before 3434 // anything else. 3435 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3436 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3437 } 3438 ConstraintInfos.clear(); 3439 3440 3441 // Second pass - Loop over all of the operands, assigning virtual or physregs 3442 // to registerclass operands. 3443 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3444 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3445 3446 // C_Register operands have already been allocated, Other/Memory don't need 3447 // to be. 3448 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3449 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3450 } 3451 3452 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3453 std::vector<SDOperand> AsmNodeOperands; 3454 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3455 AsmNodeOperands.push_back( 3456 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3457 3458 3459 // Loop over all of the inputs, copying the operand values into the 3460 // appropriate registers and processing the output regs. 3461 RegsForValue RetValRegs; 3462 3463 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3464 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3465 3466 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3467 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3468 3469 switch (OpInfo.Type) { 3470 case InlineAsm::isOutput: { 3471 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3472 OpInfo.ConstraintType != TargetLowering::C_Register) { 3473 // Memory output, or 'other' output (e.g. 'X' constraint). 3474 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3475 3476 // Add information to the INLINEASM node to know about this output. 3477 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3478 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3479 TLI.getPointerTy())); 3480 AsmNodeOperands.push_back(OpInfo.CallOperand); 3481 break; 3482 } 3483 3484 // Otherwise, this is a register or register class output. 3485 3486 // Copy the output from the appropriate register. Find a register that 3487 // we can use. 3488 if (OpInfo.AssignedRegs.Regs.empty()) { 3489 cerr << "Couldn't allocate output reg for contraint '" 3490 << OpInfo.ConstraintCode << "'!\n"; 3491 exit(1); 3492 } 3493 3494 if (!OpInfo.isIndirect) { 3495 // This is the result value of the call. 3496 assert(RetValRegs.Regs.empty() && 3497 "Cannot have multiple output constraints yet!"); 3498 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3499 RetValRegs = OpInfo.AssignedRegs; 3500 } else { 3501 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3502 OpInfo.CallOperandVal)); 3503 } 3504 3505 // Add information to the INLINEASM node to know that this register is 3506 // set. 3507 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3508 AsmNodeOperands); 3509 break; 3510 } 3511 case InlineAsm::isInput: { 3512 SDOperand InOperandVal = OpInfo.CallOperand; 3513 3514 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3515 // If this is required to match an output register we have already set, 3516 // just use its register. 3517 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3518 3519 // Scan until we find the definition we already emitted of this operand. 3520 // When we find it, create a RegsForValue operand. 3521 unsigned CurOp = 2; // The first operand. 3522 for (; OperandNo; --OperandNo) { 3523 // Advance to the next operand. 3524 unsigned NumOps = 3525 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3526 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3527 (NumOps & 7) == 4 /*MEM*/) && 3528 "Skipped past definitions?"); 3529 CurOp += (NumOps>>3)+1; 3530 } 3531 3532 unsigned NumOps = 3533 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3534 if ((NumOps & 7) == 2 /*REGDEF*/) { 3535 // Add NumOps>>3 registers to MatchedRegs. 3536 RegsForValue MatchedRegs; 3537 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3538 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3539 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3540 unsigned Reg = 3541 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3542 MatchedRegs.Regs.push_back(Reg); 3543 } 3544 3545 // Use the produced MatchedRegs object to 3546 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3547 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3548 break; 3549 } else { 3550 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3551 assert(0 && "matching constraints for memory operands unimp"); 3552 } 3553 } 3554 3555 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3556 assert(!OpInfo.isIndirect && 3557 "Don't know how to handle indirect other inputs yet!"); 3558 3559 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 3560 OpInfo.ConstraintCode[0], 3561 DAG); 3562 if (!InOperandVal.Val) { 3563 cerr << "Invalid operand for inline asm constraint '" 3564 << OpInfo.ConstraintCode << "'!\n"; 3565 exit(1); 3566 } 3567 3568 // Add information to the INLINEASM node to know about this input. 3569 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 3570 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3571 TLI.getPointerTy())); 3572 AsmNodeOperands.push_back(InOperandVal); 3573 break; 3574 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3575 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3576 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3577 "Memory operands expect pointer values"); 3578 3579 // Add information to the INLINEASM node to know about this input. 3580 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3581 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3582 TLI.getPointerTy())); 3583 AsmNodeOperands.push_back(InOperandVal); 3584 break; 3585 } 3586 3587 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3588 OpInfo.ConstraintType == TargetLowering::C_Register) && 3589 "Unknown constraint type!"); 3590 assert(!OpInfo.isIndirect && 3591 "Don't know how to handle indirect register inputs yet!"); 3592 3593 // Copy the input into the appropriate registers. 3594 assert(!OpInfo.AssignedRegs.Regs.empty() && 3595 "Couldn't allocate input reg!"); 3596 3597 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3598 3599 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3600 AsmNodeOperands); 3601 break; 3602 } 3603 case InlineAsm::isClobber: { 3604 // Add the clobbered value to the operand list, so that the register 3605 // allocator is aware that the physreg got clobbered. 3606 if (!OpInfo.AssignedRegs.Regs.empty()) 3607 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3608 AsmNodeOperands); 3609 break; 3610 } 3611 } 3612 } 3613 3614 // Finish up input operands. 3615 AsmNodeOperands[0] = Chain; 3616 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3617 3618 Chain = DAG.getNode(ISD::INLINEASM, 3619 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3620 &AsmNodeOperands[0], AsmNodeOperands.size()); 3621 Flag = Chain.getValue(1); 3622 3623 // If this asm returns a register value, copy the result from that register 3624 // and set it as the value of the call. 3625 if (!RetValRegs.Regs.empty()) { 3626 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3627 3628 // If the result of the inline asm is a vector, it may have the wrong 3629 // width/num elts. Make sure to convert it to the right type with 3630 // bit_convert. 3631 if (MVT::isVector(Val.getValueType())) { 3632 const VectorType *VTy = cast<VectorType>(I.getType()); 3633 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3634 3635 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3636 } 3637 3638 setValue(&I, Val); 3639 } 3640 3641 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3642 3643 // Process indirect outputs, first output all of the flagged copies out of 3644 // physregs. 3645 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3646 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3647 Value *Ptr = IndirectStoresToEmit[i].second; 3648 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3649 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3650 } 3651 3652 // Emit the non-flagged stores from the physregs. 3653 SmallVector<SDOperand, 8> OutChains; 3654 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3655 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3656 getValue(StoresToEmit[i].second), 3657 StoresToEmit[i].second, 0)); 3658 if (!OutChains.empty()) 3659 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3660 &OutChains[0], OutChains.size()); 3661 DAG.setRoot(Chain); 3662} 3663 3664 3665void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3666 SDOperand Src = getValue(I.getOperand(0)); 3667 3668 MVT::ValueType IntPtr = TLI.getPointerTy(); 3669 3670 if (IntPtr < Src.getValueType()) 3671 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3672 else if (IntPtr > Src.getValueType()) 3673 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3674 3675 // Scale the source by the type size. 3676 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3677 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3678 Src, getIntPtrConstant(ElementSize)); 3679 3680 TargetLowering::ArgListTy Args; 3681 TargetLowering::ArgListEntry Entry; 3682 Entry.Node = Src; 3683 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3684 Args.push_back(Entry); 3685 3686 std::pair<SDOperand,SDOperand> Result = 3687 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3688 DAG.getExternalSymbol("malloc", IntPtr), 3689 Args, DAG); 3690 setValue(&I, Result.first); // Pointers always fit in registers 3691 DAG.setRoot(Result.second); 3692} 3693 3694void SelectionDAGLowering::visitFree(FreeInst &I) { 3695 TargetLowering::ArgListTy Args; 3696 TargetLowering::ArgListEntry Entry; 3697 Entry.Node = getValue(I.getOperand(0)); 3698 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3699 Args.push_back(Entry); 3700 MVT::ValueType IntPtr = TLI.getPointerTy(); 3701 std::pair<SDOperand,SDOperand> Result = 3702 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3703 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3704 DAG.setRoot(Result.second); 3705} 3706 3707// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3708// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3709// instructions are special in various ways, which require special support to 3710// insert. The specified MachineInstr is created but not inserted into any 3711// basic blocks, and the scheduler passes ownership of it to this method. 3712MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3713 MachineBasicBlock *MBB) { 3714 cerr << "If a target marks an instruction with " 3715 << "'usesCustomDAGSchedInserter', it must implement " 3716 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3717 abort(); 3718 return 0; 3719} 3720 3721void SelectionDAGLowering::visitVAStart(CallInst &I) { 3722 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3723 getValue(I.getOperand(1)), 3724 DAG.getSrcValue(I.getOperand(1)))); 3725} 3726 3727void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3728 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3729 getValue(I.getOperand(0)), 3730 DAG.getSrcValue(I.getOperand(0))); 3731 setValue(&I, V); 3732 DAG.setRoot(V.getValue(1)); 3733} 3734 3735void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3736 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3737 getValue(I.getOperand(1)), 3738 DAG.getSrcValue(I.getOperand(1)))); 3739} 3740 3741void SelectionDAGLowering::visitVACopy(CallInst &I) { 3742 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3743 getValue(I.getOperand(1)), 3744 getValue(I.getOperand(2)), 3745 DAG.getSrcValue(I.getOperand(1)), 3746 DAG.getSrcValue(I.getOperand(2)))); 3747} 3748 3749/// TargetLowering::LowerArguments - This is the default LowerArguments 3750/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3751/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3752/// integrated into SDISel. 3753std::vector<SDOperand> 3754TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3755 const FunctionType *FTy = F.getFunctionType(); 3756 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3757 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3758 std::vector<SDOperand> Ops; 3759 Ops.push_back(DAG.getRoot()); 3760 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3761 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3762 3763 // Add one result value for each formal argument. 3764 std::vector<MVT::ValueType> RetVals; 3765 unsigned j = 1; 3766 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3767 I != E; ++I, ++j) { 3768 MVT::ValueType VT = getValueType(I->getType()); 3769 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3770 unsigned OriginalAlignment = 3771 getTargetData()->getABITypeAlignment(I->getType()); 3772 3773 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3774 // that is zero extended! 3775 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3776 Flags &= ~(ISD::ParamFlags::SExt); 3777 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3778 Flags |= ISD::ParamFlags::SExt; 3779 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3780 Flags |= ISD::ParamFlags::InReg; 3781 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3782 Flags |= ISD::ParamFlags::StructReturn; 3783 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3784 3785 switch (getTypeAction(VT)) { 3786 default: assert(0 && "Unknown type action!"); 3787 case Legal: 3788 RetVals.push_back(VT); 3789 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3790 break; 3791 case Promote: 3792 RetVals.push_back(getTypeToTransformTo(VT)); 3793 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3794 break; 3795 case Expand: { 3796 // If this is an illegal type, it needs to be broken up to fit into 3797 // registers. 3798 MVT::ValueType RegisterVT = getRegisterType(VT); 3799 unsigned NumRegs = getNumRegisters(VT); 3800 for (unsigned i = 0; i != NumRegs; ++i) { 3801 RetVals.push_back(RegisterVT); 3802 // if it isn't first piece, alignment must be 1 3803 if (i > 0) 3804 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3805 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3806 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3807 } 3808 break; 3809 } 3810 } 3811 } 3812 3813 RetVals.push_back(MVT::Other); 3814 3815 // Create the node. 3816 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3817 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3818 &Ops[0], Ops.size()).Val; 3819 unsigned NumArgRegs = Result->getNumValues() - 1; 3820 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3821 3822 // Set up the return result vector. 3823 Ops.clear(); 3824 unsigned i = 0; 3825 unsigned Idx = 1; 3826 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3827 ++I, ++Idx) { 3828 MVT::ValueType VT = getValueType(I->getType()); 3829 3830 switch (getTypeAction(VT)) { 3831 default: assert(0 && "Unknown type action!"); 3832 case Legal: 3833 Ops.push_back(SDOperand(Result, i++)); 3834 break; 3835 case Promote: { 3836 SDOperand Op(Result, i++); 3837 if (MVT::isInteger(VT)) { 3838 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3839 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3840 DAG.getValueType(VT)); 3841 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3842 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3843 DAG.getValueType(VT)); 3844 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3845 } else { 3846 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3847 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3848 } 3849 Ops.push_back(Op); 3850 break; 3851 } 3852 case Expand: { 3853 MVT::ValueType PartVT = getRegisterType(VT); 3854 unsigned NumParts = getNumRegisters(VT); 3855 SmallVector<SDOperand, 4> Parts(NumParts); 3856 for (unsigned j = 0; j != NumParts; ++j) 3857 Parts[j] = SDOperand(Result, i++); 3858 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3859 break; 3860 } 3861 } 3862 } 3863 assert(i == NumArgRegs && "Argument register count mismatch!"); 3864 return Ops; 3865} 3866 3867 3868/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3869/// implementation, which just inserts an ISD::CALL node, which is later custom 3870/// lowered by the target to something concrete. FIXME: When all targets are 3871/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3872std::pair<SDOperand, SDOperand> 3873TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3874 bool RetTyIsSigned, bool isVarArg, 3875 unsigned CallingConv, bool isTailCall, 3876 SDOperand Callee, 3877 ArgListTy &Args, SelectionDAG &DAG) { 3878 SmallVector<SDOperand, 32> Ops; 3879 Ops.push_back(Chain); // Op#0 - Chain 3880 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3881 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3882 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3883 Ops.push_back(Callee); 3884 3885 // Handle all of the outgoing arguments. 3886 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3887 MVT::ValueType VT = getValueType(Args[i].Ty); 3888 SDOperand Op = Args[i].Node; 3889 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3890 unsigned OriginalAlignment = 3891 getTargetData()->getABITypeAlignment(Args[i].Ty); 3892 3893 if (Args[i].isSExt) 3894 Flags |= ISD::ParamFlags::SExt; 3895 if (Args[i].isZExt) 3896 Flags |= ISD::ParamFlags::ZExt; 3897 if (Args[i].isInReg) 3898 Flags |= ISD::ParamFlags::InReg; 3899 if (Args[i].isSRet) 3900 Flags |= ISD::ParamFlags::StructReturn; 3901 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3902 3903 switch (getTypeAction(VT)) { 3904 default: assert(0 && "Unknown type action!"); 3905 case Legal: 3906 Ops.push_back(Op); 3907 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3908 break; 3909 case Promote: 3910 if (MVT::isInteger(VT)) { 3911 unsigned ExtOp; 3912 if (Args[i].isSExt) 3913 ExtOp = ISD::SIGN_EXTEND; 3914 else if (Args[i].isZExt) 3915 ExtOp = ISD::ZERO_EXTEND; 3916 else 3917 ExtOp = ISD::ANY_EXTEND; 3918 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3919 } else { 3920 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3921 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 3922 } 3923 Ops.push_back(Op); 3924 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3925 break; 3926 case Expand: { 3927 MVT::ValueType PartVT = getRegisterType(VT); 3928 unsigned NumParts = getNumRegisters(VT); 3929 SmallVector<SDOperand, 4> Parts(NumParts); 3930 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 3931 for (unsigned i = 0; i != NumParts; ++i) { 3932 // if it isn't first piece, alignment must be 1 3933 unsigned MyFlags = Flags; 3934 if (i != 0) 3935 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 3936 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3937 3938 Ops.push_back(Parts[i]); 3939 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 3940 } 3941 break; 3942 } 3943 } 3944 } 3945 3946 // Figure out the result value types. 3947 MVT::ValueType VT = getValueType(RetTy); 3948 MVT::ValueType RegisterVT = getRegisterType(VT); 3949 unsigned NumRegs = getNumRegisters(VT); 3950 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 3951 for (unsigned i = 0; i != NumRegs; ++i) 3952 RetTys[i] = RegisterVT; 3953 3954 RetTys.push_back(MVT::Other); // Always has a chain. 3955 3956 // Create the CALL node. 3957 SDOperand Res = DAG.getNode(ISD::CALL, 3958 DAG.getVTList(&RetTys[0], NumRegs + 1), 3959 &Ops[0], Ops.size()); 3960 SDOperand Chain = Res.getValue(NumRegs); 3961 3962 // Gather up the call result into a single value. 3963 if (RetTy != Type::VoidTy) { 3964 ISD::NodeType AssertOp = ISD::AssertSext; 3965 if (!RetTyIsSigned) 3966 AssertOp = ISD::AssertZext; 3967 SmallVector<SDOperand, 4> Results(NumRegs); 3968 for (unsigned i = 0; i != NumRegs; ++i) 3969 Results[i] = Res.getValue(i); 3970 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 3971 } 3972 3973 return std::make_pair(Res, Chain); 3974} 3975 3976SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3977 assert(0 && "LowerOperation not implemented for this target!"); 3978 abort(); 3979 return SDOperand(); 3980} 3981 3982SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 3983 SelectionDAG &DAG) { 3984 assert(0 && "CustomPromoteOperation not implemented for this target!"); 3985 abort(); 3986 return SDOperand(); 3987} 3988 3989/// getMemsetValue - Vectorized representation of the memset value 3990/// operand. 3991static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 3992 SelectionDAG &DAG) { 3993 MVT::ValueType CurVT = VT; 3994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 3995 uint64_t Val = C->getValue() & 255; 3996 unsigned Shift = 8; 3997 while (CurVT != MVT::i8) { 3998 Val = (Val << Shift) | Val; 3999 Shift <<= 1; 4000 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4001 } 4002 return DAG.getConstant(Val, VT); 4003 } else { 4004 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4005 unsigned Shift = 8; 4006 while (CurVT != MVT::i8) { 4007 Value = 4008 DAG.getNode(ISD::OR, VT, 4009 DAG.getNode(ISD::SHL, VT, Value, 4010 DAG.getConstant(Shift, MVT::i8)), Value); 4011 Shift <<= 1; 4012 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4013 } 4014 4015 return Value; 4016 } 4017} 4018 4019/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4020/// used when a memcpy is turned into a memset when the source is a constant 4021/// string ptr. 4022static SDOperand getMemsetStringVal(MVT::ValueType VT, 4023 SelectionDAG &DAG, TargetLowering &TLI, 4024 std::string &Str, unsigned Offset) { 4025 uint64_t Val = 0; 4026 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4027 if (TLI.isLittleEndian()) 4028 Offset = Offset + MSB - 1; 4029 for (unsigned i = 0; i != MSB; ++i) { 4030 Val = (Val << 8) | (unsigned char)Str[Offset]; 4031 Offset += TLI.isLittleEndian() ? -1 : 1; 4032 } 4033 return DAG.getConstant(Val, VT); 4034} 4035 4036/// getMemBasePlusOffset - Returns base and offset node for the 4037static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4038 SelectionDAG &DAG, TargetLowering &TLI) { 4039 MVT::ValueType VT = Base.getValueType(); 4040 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4041} 4042 4043/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4044/// to replace the memset / memcpy is below the threshold. It also returns the 4045/// types of the sequence of memory ops to perform memset / memcpy. 4046static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4047 unsigned Limit, uint64_t Size, 4048 unsigned Align, TargetLowering &TLI) { 4049 MVT::ValueType VT; 4050 4051 if (TLI.allowsUnalignedMemoryAccesses()) { 4052 VT = MVT::i64; 4053 } else { 4054 switch (Align & 7) { 4055 case 0: 4056 VT = MVT::i64; 4057 break; 4058 case 4: 4059 VT = MVT::i32; 4060 break; 4061 case 2: 4062 VT = MVT::i16; 4063 break; 4064 default: 4065 VT = MVT::i8; 4066 break; 4067 } 4068 } 4069 4070 MVT::ValueType LVT = MVT::i64; 4071 while (!TLI.isTypeLegal(LVT)) 4072 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4073 assert(MVT::isInteger(LVT)); 4074 4075 if (VT > LVT) 4076 VT = LVT; 4077 4078 unsigned NumMemOps = 0; 4079 while (Size != 0) { 4080 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4081 while (VTSize > Size) { 4082 VT = (MVT::ValueType)((unsigned)VT - 1); 4083 VTSize >>= 1; 4084 } 4085 assert(MVT::isInteger(VT)); 4086 4087 if (++NumMemOps > Limit) 4088 return false; 4089 MemOps.push_back(VT); 4090 Size -= VTSize; 4091 } 4092 4093 return true; 4094} 4095 4096void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4097 SDOperand Op1 = getValue(I.getOperand(1)); 4098 SDOperand Op2 = getValue(I.getOperand(2)); 4099 SDOperand Op3 = getValue(I.getOperand(3)); 4100 SDOperand Op4 = getValue(I.getOperand(4)); 4101 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4102 if (Align == 0) Align = 1; 4103 4104 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4105 std::vector<MVT::ValueType> MemOps; 4106 4107 // Expand memset / memcpy to a series of load / store ops 4108 // if the size operand falls below a certain threshold. 4109 SmallVector<SDOperand, 8> OutChains; 4110 switch (Op) { 4111 default: break; // Do nothing for now. 4112 case ISD::MEMSET: { 4113 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4114 Size->getValue(), Align, TLI)) { 4115 unsigned NumMemOps = MemOps.size(); 4116 unsigned Offset = 0; 4117 for (unsigned i = 0; i < NumMemOps; i++) { 4118 MVT::ValueType VT = MemOps[i]; 4119 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4120 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4121 SDOperand Store = DAG.getStore(getRoot(), Value, 4122 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4123 I.getOperand(1), Offset); 4124 OutChains.push_back(Store); 4125 Offset += VTSize; 4126 } 4127 } 4128 break; 4129 } 4130 case ISD::MEMCPY: { 4131 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4132 Size->getValue(), Align, TLI)) { 4133 unsigned NumMemOps = MemOps.size(); 4134 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4135 GlobalAddressSDNode *G = NULL; 4136 std::string Str; 4137 bool CopyFromStr = false; 4138 4139 if (Op2.getOpcode() == ISD::GlobalAddress) 4140 G = cast<GlobalAddressSDNode>(Op2); 4141 else if (Op2.getOpcode() == ISD::ADD && 4142 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4143 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4144 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4145 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4146 } 4147 if (G) { 4148 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4149 if (GV && GV->isConstant()) { 4150 Str = GV->getStringValue(false); 4151 if (!Str.empty()) { 4152 CopyFromStr = true; 4153 SrcOff += SrcDelta; 4154 } 4155 } 4156 } 4157 4158 for (unsigned i = 0; i < NumMemOps; i++) { 4159 MVT::ValueType VT = MemOps[i]; 4160 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4161 SDOperand Value, Chain, Store; 4162 4163 if (CopyFromStr) { 4164 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4165 Chain = getRoot(); 4166 Store = 4167 DAG.getStore(Chain, Value, 4168 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4169 I.getOperand(1), DstOff); 4170 } else { 4171 Value = DAG.getLoad(VT, getRoot(), 4172 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4173 I.getOperand(2), SrcOff); 4174 Chain = Value.getValue(1); 4175 Store = 4176 DAG.getStore(Chain, Value, 4177 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4178 I.getOperand(1), DstOff); 4179 } 4180 OutChains.push_back(Store); 4181 SrcOff += VTSize; 4182 DstOff += VTSize; 4183 } 4184 } 4185 break; 4186 } 4187 } 4188 4189 if (!OutChains.empty()) { 4190 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4191 &OutChains[0], OutChains.size())); 4192 return; 4193 } 4194 } 4195 4196 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4197} 4198 4199//===----------------------------------------------------------------------===// 4200// SelectionDAGISel code 4201//===----------------------------------------------------------------------===// 4202 4203unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4204 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4205} 4206 4207void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4208 AU.addRequired<AliasAnalysis>(); 4209 AU.setPreservesAll(); 4210} 4211 4212 4213 4214bool SelectionDAGISel::runOnFunction(Function &Fn) { 4215 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4216 RegMap = MF.getSSARegMap(); 4217 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4218 4219 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4220 4221 if (ExceptionHandling) 4222 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4223 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4224 // Mark landing pad. 4225 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4226 4227 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4228 SelectBasicBlock(I, MF, FuncInfo); 4229 4230 // Add function live-ins to entry block live-in set. 4231 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4232 BB = FuncInfo.MBBMap[EntryBB]; 4233 if (!MF.livein_empty()) 4234 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4235 E = MF.livein_end(); I != E; ++I) 4236 BB->addLiveIn(I->first); 4237 4238#ifndef NDEBUG 4239 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4240 "Not all catch info was assigned to a landing pad!"); 4241#endif 4242 4243 return true; 4244} 4245 4246SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4247 unsigned Reg) { 4248 SDOperand Op = getValue(V); 4249 assert((Op.getOpcode() != ISD::CopyFromReg || 4250 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4251 "Copy from a reg to the same reg!"); 4252 4253 MVT::ValueType SrcVT = Op.getValueType(); 4254 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4255 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4256 SmallVector<SDOperand, 8> Regs(NumRegs); 4257 SmallVector<SDOperand, 8> Chains(NumRegs); 4258 4259 // Copy the value by legal parts into sequential virtual registers. 4260 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4261 for (unsigned i = 0; i != NumRegs; ++i) 4262 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4263 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4264} 4265 4266void SelectionDAGISel:: 4267LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4268 std::vector<SDOperand> &UnorderedChains) { 4269 // If this is the entry block, emit arguments. 4270 Function &F = *LLVMBB->getParent(); 4271 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4272 SDOperand OldRoot = SDL.DAG.getRoot(); 4273 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4274 4275 unsigned a = 0; 4276 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4277 AI != E; ++AI, ++a) 4278 if (!AI->use_empty()) { 4279 SDL.setValue(AI, Args[a]); 4280 4281 // If this argument is live outside of the entry block, insert a copy from 4282 // whereever we got it to the vreg that other BB's will reference it as. 4283 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4284 if (VMI != FuncInfo.ValueMap.end()) { 4285 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4286 UnorderedChains.push_back(Copy); 4287 } 4288 } 4289 4290 // Finally, if the target has anything special to do, allow it to do so. 4291 // FIXME: this should insert code into the DAG! 4292 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4293} 4294 4295static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4296 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4297 assert(!FLI.MBBMap[SrcBB]->isLandingPad() && 4298 "Copying catch info out of a landing pad!"); 4299 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4300 if (isFilterOrSelector(I)) { 4301 // Apply the catch info to DestBB. 4302 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4303#ifndef NDEBUG 4304 FLI.CatchInfoFound.insert(I); 4305#endif 4306 } 4307} 4308 4309void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4310 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4311 FunctionLoweringInfo &FuncInfo) { 4312 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4313 4314 std::vector<SDOperand> UnorderedChains; 4315 4316 // Lower any arguments needed in this block if this is the entry block. 4317 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4318 LowerArguments(LLVMBB, SDL, UnorderedChains); 4319 4320 BB = FuncInfo.MBBMap[LLVMBB]; 4321 SDL.setCurrentBasicBlock(BB); 4322 4323 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4324 4325 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4326 // Add a label to mark the beginning of the landing pad. Deletion of the 4327 // landing pad can thus be detected via the MachineModuleInfo. 4328 unsigned LabelID = MMI->addLandingPad(BB); 4329 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4330 DAG.getConstant(LabelID, MVT::i32))); 4331 4332 // Mark exception register as live in. 4333 unsigned Reg = TLI.getExceptionAddressRegister(); 4334 if (Reg) BB->addLiveIn(Reg); 4335 4336 // Mark exception selector register as live in. 4337 Reg = TLI.getExceptionSelectorRegister(); 4338 if (Reg) BB->addLiveIn(Reg); 4339 4340 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4341 // function and list of typeids logically belong to the invoke (or, if you 4342 // like, the basic block containing the invoke), and need to be associated 4343 // with it in the dwarf exception handling tables. Currently however the 4344 // information is provided by intrinsics (eh.filter and eh.selector) that 4345 // can be moved to unexpected places by the optimizers: if the unwind edge 4346 // is critical, then breaking it can result in the intrinsics being in the 4347 // successor of the landing pad, not the landing pad itself. This results 4348 // in exceptions not being caught because no typeids are associated with 4349 // the invoke. This may not be the only way things can go wrong, but it 4350 // is the only way we try to work around for the moment. 4351 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4352 4353 if (Br && Br->isUnconditional()) { // Critical edge? 4354 BasicBlock::iterator I, E; 4355 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4356 if (isFilterOrSelector(I)) 4357 break; 4358 4359 if (I == E) 4360 // No catch info found - try to extract some from the successor. 4361 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4362 } 4363 } 4364 4365 // Lower all of the non-terminator instructions. 4366 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4367 I != E; ++I) 4368 SDL.visit(*I); 4369 4370 // Ensure that all instructions which are used outside of their defining 4371 // blocks are available as virtual registers. Invoke is handled elsewhere. 4372 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4373 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4374 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4375 if (VMI != FuncInfo.ValueMap.end()) 4376 UnorderedChains.push_back( 4377 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4378 } 4379 4380 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4381 // ensure constants are generated when needed. Remember the virtual registers 4382 // that need to be added to the Machine PHI nodes as input. We cannot just 4383 // directly add them, because expansion might result in multiple MBB's for one 4384 // BB. As such, the start of the BB might correspond to a different MBB than 4385 // the end. 4386 // 4387 TerminatorInst *TI = LLVMBB->getTerminator(); 4388 4389 // Emit constants only once even if used by multiple PHI nodes. 4390 std::map<Constant*, unsigned> ConstantsOut; 4391 4392 // Vector bool would be better, but vector<bool> is really slow. 4393 std::vector<unsigned char> SuccsHandled; 4394 if (TI->getNumSuccessors()) 4395 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4396 4397 // Check successor nodes PHI nodes that expect a constant to be available from 4398 // this block. 4399 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4400 BasicBlock *SuccBB = TI->getSuccessor(succ); 4401 if (!isa<PHINode>(SuccBB->begin())) continue; 4402 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4403 4404 // If this terminator has multiple identical successors (common for 4405 // switches), only handle each succ once. 4406 unsigned SuccMBBNo = SuccMBB->getNumber(); 4407 if (SuccsHandled[SuccMBBNo]) continue; 4408 SuccsHandled[SuccMBBNo] = true; 4409 4410 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4411 PHINode *PN; 4412 4413 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4414 // nodes and Machine PHI nodes, but the incoming operands have not been 4415 // emitted yet. 4416 for (BasicBlock::iterator I = SuccBB->begin(); 4417 (PN = dyn_cast<PHINode>(I)); ++I) { 4418 // Ignore dead phi's. 4419 if (PN->use_empty()) continue; 4420 4421 unsigned Reg; 4422 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4423 4424 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4425 unsigned &RegOut = ConstantsOut[C]; 4426 if (RegOut == 0) { 4427 RegOut = FuncInfo.CreateRegForValue(C); 4428 UnorderedChains.push_back( 4429 SDL.CopyValueToVirtualRegister(C, RegOut)); 4430 } 4431 Reg = RegOut; 4432 } else { 4433 Reg = FuncInfo.ValueMap[PHIOp]; 4434 if (Reg == 0) { 4435 assert(isa<AllocaInst>(PHIOp) && 4436 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4437 "Didn't codegen value into a register!??"); 4438 Reg = FuncInfo.CreateRegForValue(PHIOp); 4439 UnorderedChains.push_back( 4440 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4441 } 4442 } 4443 4444 // Remember that this register needs to added to the machine PHI node as 4445 // the input for this MBB. 4446 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4447 unsigned NumRegisters = TLI.getNumRegisters(VT); 4448 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4449 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4450 } 4451 } 4452 ConstantsOut.clear(); 4453 4454 // Turn all of the unordered chains into one factored node. 4455 if (!UnorderedChains.empty()) { 4456 SDOperand Root = SDL.getRoot(); 4457 if (Root.getOpcode() != ISD::EntryToken) { 4458 unsigned i = 0, e = UnorderedChains.size(); 4459 for (; i != e; ++i) { 4460 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4461 if (UnorderedChains[i].Val->getOperand(0) == Root) 4462 break; // Don't add the root if we already indirectly depend on it. 4463 } 4464 4465 if (i == e) 4466 UnorderedChains.push_back(Root); 4467 } 4468 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4469 &UnorderedChains[0], UnorderedChains.size())); 4470 } 4471 4472 // Lower the terminator after the copies are emitted. 4473 SDL.visit(*LLVMBB->getTerminator()); 4474 4475 // Copy over any CaseBlock records that may now exist due to SwitchInst 4476 // lowering, as well as any jump table information. 4477 SwitchCases.clear(); 4478 SwitchCases = SDL.SwitchCases; 4479 JTCases.clear(); 4480 JTCases = SDL.JTCases; 4481 BitTestCases.clear(); 4482 BitTestCases = SDL.BitTestCases; 4483 4484 // Make sure the root of the DAG is up-to-date. 4485 DAG.setRoot(SDL.getRoot()); 4486} 4487 4488void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4489 // Get alias analysis for load/store combining. 4490 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4491 4492 // Run the DAG combiner in pre-legalize mode. 4493 DAG.Combine(false, AA); 4494 4495 DOUT << "Lowered selection DAG:\n"; 4496 DEBUG(DAG.dump()); 4497 4498 // Second step, hack on the DAG until it only uses operations and types that 4499 // the target supports. 4500 DAG.Legalize(); 4501 4502 DOUT << "Legalized selection DAG:\n"; 4503 DEBUG(DAG.dump()); 4504 4505 // Run the DAG combiner in post-legalize mode. 4506 DAG.Combine(true, AA); 4507 4508 if (ViewISelDAGs) DAG.viewGraph(); 4509 4510 // Third, instruction select all of the operations to machine code, adding the 4511 // code to the MachineBasicBlock. 4512 InstructionSelectBasicBlock(DAG); 4513 4514 DOUT << "Selected machine code:\n"; 4515 DEBUG(BB->dump()); 4516} 4517 4518void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4519 FunctionLoweringInfo &FuncInfo) { 4520 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4521 { 4522 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4523 CurDAG = &DAG; 4524 4525 // First step, lower LLVM code to some DAG. This DAG may use operations and 4526 // types that are not supported by the target. 4527 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4528 4529 // Second step, emit the lowered DAG as machine code. 4530 CodeGenAndEmitDAG(DAG); 4531 } 4532 4533 DOUT << "Total amount of phi nodes to update: " 4534 << PHINodesToUpdate.size() << "\n"; 4535 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4536 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4537 << ", " << PHINodesToUpdate[i].second << ")\n";); 4538 4539 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4540 // PHI nodes in successors. 4541 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4542 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4543 MachineInstr *PHI = PHINodesToUpdate[i].first; 4544 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4545 "This is not a machine PHI node that we are updating!"); 4546 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4547 PHI->addMachineBasicBlockOperand(BB); 4548 } 4549 return; 4550 } 4551 4552 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4553 // Lower header first, if it wasn't already lowered 4554 if (!BitTestCases[i].Emitted) { 4555 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4556 CurDAG = &HSDAG; 4557 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4558 // Set the current basic block to the mbb we wish to insert the code into 4559 BB = BitTestCases[i].Parent; 4560 HSDL.setCurrentBasicBlock(BB); 4561 // Emit the code 4562 HSDL.visitBitTestHeader(BitTestCases[i]); 4563 HSDAG.setRoot(HSDL.getRoot()); 4564 CodeGenAndEmitDAG(HSDAG); 4565 } 4566 4567 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4568 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4569 CurDAG = &BSDAG; 4570 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4571 // Set the current basic block to the mbb we wish to insert the code into 4572 BB = BitTestCases[i].Cases[j].ThisBB; 4573 BSDL.setCurrentBasicBlock(BB); 4574 // Emit the code 4575 if (j+1 != ej) 4576 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4577 BitTestCases[i].Reg, 4578 BitTestCases[i].Cases[j]); 4579 else 4580 BSDL.visitBitTestCase(BitTestCases[i].Default, 4581 BitTestCases[i].Reg, 4582 BitTestCases[i].Cases[j]); 4583 4584 4585 BSDAG.setRoot(BSDL.getRoot()); 4586 CodeGenAndEmitDAG(BSDAG); 4587 } 4588 4589 // Update PHI Nodes 4590 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4591 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4592 MachineBasicBlock *PHIBB = PHI->getParent(); 4593 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4594 "This is not a machine PHI node that we are updating!"); 4595 // This is "default" BB. We have two jumps to it. From "header" BB and 4596 // from last "case" BB. 4597 if (PHIBB == BitTestCases[i].Default) { 4598 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4599 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4600 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4601 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4602 } 4603 // One of "cases" BB. 4604 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4605 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4606 if (cBB->succ_end() != 4607 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4608 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4609 PHI->addMachineBasicBlockOperand(cBB); 4610 } 4611 } 4612 } 4613 } 4614 4615 // If the JumpTable record is filled in, then we need to emit a jump table. 4616 // Updating the PHI nodes is tricky in this case, since we need to determine 4617 // whether the PHI is a successor of the range check MBB or the jump table MBB 4618 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4619 // Lower header first, if it wasn't already lowered 4620 if (!JTCases[i].first.Emitted) { 4621 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4622 CurDAG = &HSDAG; 4623 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4624 // Set the current basic block to the mbb we wish to insert the code into 4625 BB = JTCases[i].first.HeaderBB; 4626 HSDL.setCurrentBasicBlock(BB); 4627 // Emit the code 4628 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4629 HSDAG.setRoot(HSDL.getRoot()); 4630 CodeGenAndEmitDAG(HSDAG); 4631 } 4632 4633 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4634 CurDAG = &JSDAG; 4635 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4636 // Set the current basic block to the mbb we wish to insert the code into 4637 BB = JTCases[i].second.MBB; 4638 JSDL.setCurrentBasicBlock(BB); 4639 // Emit the code 4640 JSDL.visitJumpTable(JTCases[i].second); 4641 JSDAG.setRoot(JSDL.getRoot()); 4642 CodeGenAndEmitDAG(JSDAG); 4643 4644 // Update PHI Nodes 4645 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4646 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4647 MachineBasicBlock *PHIBB = PHI->getParent(); 4648 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4649 "This is not a machine PHI node that we are updating!"); 4650 // "default" BB. We can go there only from header BB. 4651 if (PHIBB == JTCases[i].second.Default) { 4652 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4653 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4654 } 4655 // JT BB. Just iterate over successors here 4656 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4657 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4658 PHI->addMachineBasicBlockOperand(BB); 4659 } 4660 } 4661 } 4662 4663 // If the switch block involved a branch to one of the actual successors, we 4664 // need to update PHI nodes in that block. 4665 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4666 MachineInstr *PHI = PHINodesToUpdate[i].first; 4667 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4668 "This is not a machine PHI node that we are updating!"); 4669 if (BB->isSuccessor(PHI->getParent())) { 4670 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4671 PHI->addMachineBasicBlockOperand(BB); 4672 } 4673 } 4674 4675 // If we generated any switch lowering information, build and codegen any 4676 // additional DAGs necessary. 4677 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4678 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4679 CurDAG = &SDAG; 4680 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4681 4682 // Set the current basic block to the mbb we wish to insert the code into 4683 BB = SwitchCases[i].ThisBB; 4684 SDL.setCurrentBasicBlock(BB); 4685 4686 // Emit the code 4687 SDL.visitSwitchCase(SwitchCases[i]); 4688 SDAG.setRoot(SDL.getRoot()); 4689 CodeGenAndEmitDAG(SDAG); 4690 4691 // Handle any PHI nodes in successors of this chunk, as if we were coming 4692 // from the original BB before switch expansion. Note that PHI nodes can 4693 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4694 // handle them the right number of times. 4695 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4696 for (MachineBasicBlock::iterator Phi = BB->begin(); 4697 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4698 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4699 for (unsigned pn = 0; ; ++pn) { 4700 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4701 if (PHINodesToUpdate[pn].first == Phi) { 4702 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4703 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4704 break; 4705 } 4706 } 4707 } 4708 4709 // Don't process RHS if same block as LHS. 4710 if (BB == SwitchCases[i].FalseBB) 4711 SwitchCases[i].FalseBB = 0; 4712 4713 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4714 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4715 SwitchCases[i].FalseBB = 0; 4716 } 4717 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4718 } 4719} 4720 4721 4722//===----------------------------------------------------------------------===// 4723/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4724/// target node in the graph. 4725void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4726 if (ViewSchedDAGs) DAG.viewGraph(); 4727 4728 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4729 4730 if (!Ctor) { 4731 Ctor = ISHeuristic; 4732 RegisterScheduler::setDefault(Ctor); 4733 } 4734 4735 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4736 BB = SL->Run(); 4737 delete SL; 4738} 4739 4740 4741HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4742 return new HazardRecognizer(); 4743} 4744 4745//===----------------------------------------------------------------------===// 4746// Helper functions used by the generated instruction selector. 4747//===----------------------------------------------------------------------===// 4748// Calls to these methods are generated by tblgen. 4749 4750/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4751/// the dag combiner simplified the 255, we still want to match. RHS is the 4752/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4753/// specified in the .td file (e.g. 255). 4754bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4755 int64_t DesiredMaskS) { 4756 uint64_t ActualMask = RHS->getValue(); 4757 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4758 4759 // If the actual mask exactly matches, success! 4760 if (ActualMask == DesiredMask) 4761 return true; 4762 4763 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4764 if (ActualMask & ~DesiredMask) 4765 return false; 4766 4767 // Otherwise, the DAG Combiner may have proven that the value coming in is 4768 // either already zero or is not demanded. Check for known zero input bits. 4769 uint64_t NeededMask = DesiredMask & ~ActualMask; 4770 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4771 return true; 4772 4773 // TODO: check to see if missing bits are just not demanded. 4774 4775 // Otherwise, this pattern doesn't match. 4776 return false; 4777} 4778 4779/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4780/// the dag combiner simplified the 255, we still want to match. RHS is the 4781/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4782/// specified in the .td file (e.g. 255). 4783bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4784 int64_t DesiredMaskS) { 4785 uint64_t ActualMask = RHS->getValue(); 4786 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4787 4788 // If the actual mask exactly matches, success! 4789 if (ActualMask == DesiredMask) 4790 return true; 4791 4792 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4793 if (ActualMask & ~DesiredMask) 4794 return false; 4795 4796 // Otherwise, the DAG Combiner may have proven that the value coming in is 4797 // either already zero or is not demanded. Check for known zero input bits. 4798 uint64_t NeededMask = DesiredMask & ~ActualMask; 4799 4800 uint64_t KnownZero, KnownOne; 4801 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4802 4803 // If all the missing bits in the or are already known to be set, match! 4804 if ((NeededMask & KnownOne) == NeededMask) 4805 return true; 4806 4807 // TODO: check to see if missing bits are just not demanded. 4808 4809 // Otherwise, this pattern doesn't match. 4810 return false; 4811} 4812 4813 4814/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4815/// by tblgen. Others should not call it. 4816void SelectionDAGISel:: 4817SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4818 std::vector<SDOperand> InOps; 4819 std::swap(InOps, Ops); 4820 4821 Ops.push_back(InOps[0]); // input chain. 4822 Ops.push_back(InOps[1]); // input asm string. 4823 4824 unsigned i = 2, e = InOps.size(); 4825 if (InOps[e-1].getValueType() == MVT::Flag) 4826 --e; // Don't process a flag operand if it is here. 4827 4828 while (i != e) { 4829 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4830 if ((Flags & 7) != 4 /*MEM*/) { 4831 // Just skip over this operand, copying the operands verbatim. 4832 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4833 i += (Flags >> 3) + 1; 4834 } else { 4835 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4836 // Otherwise, this is a memory operand. Ask the target to select it. 4837 std::vector<SDOperand> SelOps; 4838 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4839 cerr << "Could not match memory address. Inline asm failure!\n"; 4840 exit(1); 4841 } 4842 4843 // Add this to the output node. 4844 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4845 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4846 IntPtrTy)); 4847 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4848 i += 2; 4849 } 4850 } 4851 4852 // Add the flag input back if present. 4853 if (e != InOps.size()) 4854 Ops.push_back(InOps.back()); 4855} 4856 4857char SelectionDAGISel::ID = 0; 4858