SelectionDAGISel.cpp revision 86da6600aec9b8f1c3fbae157414bf1648eb639c
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available:")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { struct AsmOperandInfo; } 86 87namespace { 88 /// RegsForValue - This struct represents the physical registers that a 89 /// particular value is assigned and the type information about the value. 90 /// This is needed because values can be promoted into larger registers and 91 /// expanded into multiple smaller registers than the value. 92 struct VISIBILITY_HIDDEN RegsForValue { 93 /// Regs - This list holds the register (for legal and promoted values) 94 /// or register set (for expanded values) that the value should be assigned 95 /// to. 96 std::vector<unsigned> Regs; 97 98 /// RegVT - The value type of each register. 99 /// 100 MVT::ValueType RegVT; 101 102 /// ValueVT - The value type of the LLVM value, which may be promoted from 103 /// RegVT or made from merging the two expanded parts. 104 MVT::ValueType ValueVT; 105 106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 107 108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 109 : RegVT(regvt), ValueVT(valuevt) { 110 Regs.push_back(Reg); 111 } 112 RegsForValue(const std::vector<unsigned> ®s, 113 MVT::ValueType regvt, MVT::ValueType valuevt) 114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 115 } 116 117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 118 /// this value and returns the result as a ValueVT value. This uses 119 /// Chain/Flag as the input and updates them for the output Chain/Flag. 120 /// If the Flag pointer is NULL, no flag is used. 121 SDOperand getCopyFromRegs(SelectionDAG &DAG, 122 SDOperand &Chain, SDOperand *Flag) const; 123 124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 125 /// specified value into the registers specified by this object. This uses 126 /// Chain/Flag as the input and updates them for the output Chain/Flag. 127 /// If the Flag pointer is NULL, no flag is used. 128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 129 SDOperand &Chain, SDOperand *Flag) const; 130 131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 132 /// operand list. This adds the code marker and includes the number of 133 /// values added into it. 134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 135 std::vector<SDOperand> &Ops) const; 136 }; 137} 138 139namespace llvm { 140 //===--------------------------------------------------------------------===// 141 /// createDefaultScheduler - This creates an instruction scheduler appropriate 142 /// for the target. 143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 144 SelectionDAG *DAG, 145 MachineBasicBlock *BB) { 146 TargetLowering &TLI = IS->getTargetLowering(); 147 148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 149 return createTDListDAGScheduler(IS, DAG, BB); 150 } else { 151 assert(TLI.getSchedulingPreference() == 152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 153 return createBURRListDAGScheduler(IS, DAG, BB); 154 } 155 } 156 157 158 //===--------------------------------------------------------------------===// 159 /// FunctionLoweringInfo - This contains information that is global to a 160 /// function that is used when lowering a region of the function. 161 class FunctionLoweringInfo { 162 public: 163 TargetLowering &TLI; 164 Function &Fn; 165 MachineFunction &MF; 166 SSARegMap *RegMap; 167 168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 169 170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 172 173 /// ValueMap - Since we emit code for the function a basic block at a time, 174 /// we must remember which virtual registers hold the values for 175 /// cross-basic-block values. 176 DenseMap<const Value*, unsigned> ValueMap; 177 178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 179 /// the entry block. This allows the allocas to be efficiently referenced 180 /// anywhere in the function. 181 std::map<const AllocaInst*, int> StaticAllocaMap; 182 183#ifndef NDEBUG 184 SmallSet<Instruction*, 8> CatchInfoLost; 185 SmallSet<Instruction*, 8> CatchInfoFound; 186#endif 187 188 unsigned MakeReg(MVT::ValueType VT) { 189 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 190 } 191 192 /// isExportedInst - Return true if the specified value is an instruction 193 /// exported from its block. 194 bool isExportedInst(const Value *V) { 195 return ValueMap.count(V); 196 } 197 198 unsigned CreateRegForValue(const Value *V); 199 200 unsigned InitializeRegForValue(const Value *V) { 201 unsigned &R = ValueMap[V]; 202 assert(R == 0 && "Already initialized this value register!"); 203 return R = CreateRegForValue(V); 204 } 205 }; 206} 207 208/// isSelector - Return true if this instruction is a call to the 209/// eh.selector intrinsic. 210static bool isSelector(Instruction *I) { 211 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 212 return II->getIntrinsicID() == Intrinsic::eh_selector; 213 return false; 214} 215 216/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 217/// PHI nodes or outside of the basic block that defines it, or used by a 218/// switch instruction, which may expand to multiple basic blocks. 219static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 220 if (isa<PHINode>(I)) return true; 221 BasicBlock *BB = I->getParent(); 222 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 223 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 224 // FIXME: Remove switchinst special case. 225 isa<SwitchInst>(*UI)) 226 return true; 227 return false; 228} 229 230/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 231/// entry block, return true. This includes arguments used by switches, since 232/// the switch may expand into multiple basic blocks. 233static bool isOnlyUsedInEntryBlock(Argument *A) { 234 BasicBlock *Entry = A->getParent()->begin(); 235 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 236 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 237 return false; // Use not in entry block. 238 return true; 239} 240 241FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 242 Function &fn, MachineFunction &mf) 243 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 244 245 // Create a vreg for each argument register that is not dead and is used 246 // outside of the entry block for the function. 247 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 248 AI != E; ++AI) 249 if (!isOnlyUsedInEntryBlock(AI)) 250 InitializeRegForValue(AI); 251 252 // Initialize the mapping of values to registers. This is only set up for 253 // instruction values that are used outside of the block that defines 254 // them. 255 Function::iterator BB = Fn.begin(), EB = Fn.end(); 256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 257 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 258 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 259 const Type *Ty = AI->getAllocatedType(); 260 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 261 unsigned Align = 262 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 263 AI->getAlignment()); 264 265 TySize *= CUI->getZExtValue(); // Get total allocated size. 266 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 267 StaticAllocaMap[AI] = 268 MF.getFrameInfo()->CreateStackObject(TySize, Align); 269 } 270 271 for (; BB != EB; ++BB) 272 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 273 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 274 if (!isa<AllocaInst>(I) || 275 !StaticAllocaMap.count(cast<AllocaInst>(I))) 276 InitializeRegForValue(I); 277 278 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 279 // also creates the initial PHI MachineInstrs, though none of the input 280 // operands are populated. 281 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 282 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 283 MBBMap[BB] = MBB; 284 MF.getBasicBlockList().push_back(MBB); 285 286 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 287 // appropriate. 288 PHINode *PN; 289 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 290 if (PN->use_empty()) continue; 291 292 MVT::ValueType VT = TLI.getValueType(PN->getType()); 293 unsigned NumRegisters = TLI.getNumRegisters(VT); 294 unsigned PHIReg = ValueMap[PN]; 295 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 296 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 297 for (unsigned i = 0; i != NumRegisters; ++i) 298 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 299 } 300 } 301} 302 303/// CreateRegForValue - Allocate the appropriate number of virtual registers of 304/// the correctly promoted or expanded types. Assign these registers 305/// consecutive vreg numbers and return the first assigned number. 306unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 307 MVT::ValueType VT = TLI.getValueType(V->getType()); 308 309 unsigned NumRegisters = TLI.getNumRegisters(VT); 310 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 311 312 unsigned R = MakeReg(RegisterVT); 313 for (unsigned i = 1; i != NumRegisters; ++i) 314 MakeReg(RegisterVT); 315 316 return R; 317} 318 319//===----------------------------------------------------------------------===// 320/// SelectionDAGLowering - This is the common target-independent lowering 321/// implementation that is parameterized by a TargetLowering object. 322/// Also, targets can overload any lowering method. 323/// 324namespace llvm { 325class SelectionDAGLowering { 326 MachineBasicBlock *CurMBB; 327 328 DenseMap<const Value*, SDOperand> NodeMap; 329 330 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 331 /// them up and then emit token factor nodes when possible. This allows us to 332 /// get simple disambiguation between loads without worrying about alias 333 /// analysis. 334 std::vector<SDOperand> PendingLoads; 335 336 /// Case - A struct to record the Value for a switch case, and the 337 /// case's target basic block. 338 struct Case { 339 Constant* Low; 340 Constant* High; 341 MachineBasicBlock* BB; 342 343 Case() : Low(0), High(0), BB(0) { } 344 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 345 Low(low), High(high), BB(bb) { } 346 uint64_t size() const { 347 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 348 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 349 return (rHigh - rLow + 1ULL); 350 } 351 }; 352 353 struct CaseBits { 354 uint64_t Mask; 355 MachineBasicBlock* BB; 356 unsigned Bits; 357 358 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 359 Mask(mask), BB(bb), Bits(bits) { } 360 }; 361 362 typedef std::vector<Case> CaseVector; 363 typedef std::vector<CaseBits> CaseBitsVector; 364 typedef CaseVector::iterator CaseItr; 365 typedef std::pair<CaseItr, CaseItr> CaseRange; 366 367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 368 /// of conditional branches. 369 struct CaseRec { 370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 371 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 372 373 /// CaseBB - The MBB in which to emit the compare and branch 374 MachineBasicBlock *CaseBB; 375 /// LT, GE - If nonzero, we know the current case value must be less-than or 376 /// greater-than-or-equal-to these Constants. 377 Constant *LT; 378 Constant *GE; 379 /// Range - A pair of iterators representing the range of case values to be 380 /// processed at this point in the binary search tree. 381 CaseRange Range; 382 }; 383 384 typedef std::vector<CaseRec> CaseRecVector; 385 386 /// The comparison function for sorting the switch case values in the vector. 387 /// WARNING: Case ranges should be disjoint! 388 struct CaseCmp { 389 bool operator () (const Case& C1, const Case& C2) { 390 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 391 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 392 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 393 return CI1->getValue().slt(CI2->getValue()); 394 } 395 }; 396 397 struct CaseBitsCmp { 398 bool operator () (const CaseBits& C1, const CaseBits& C2) { 399 return C1.Bits > C2.Bits; 400 } 401 }; 402 403 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 404 405public: 406 // TLI - This is information that describes the available target features we 407 // need for lowering. This indicates when operations are unavailable, 408 // implemented with a libcall, etc. 409 TargetLowering &TLI; 410 SelectionDAG &DAG; 411 const TargetData *TD; 412 413 /// SwitchCases - Vector of CaseBlock structures used to communicate 414 /// SwitchInst code generation information. 415 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 416 /// JTCases - Vector of JumpTable structures used to communicate 417 /// SwitchInst code generation information. 418 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 419 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 420 421 /// FuncInfo - Information about the function as a whole. 422 /// 423 FunctionLoweringInfo &FuncInfo; 424 425 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 426 FunctionLoweringInfo &funcinfo) 427 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 428 FuncInfo(funcinfo) { 429 } 430 431 /// getRoot - Return the current virtual root of the Selection DAG. 432 /// 433 SDOperand getRoot() { 434 if (PendingLoads.empty()) 435 return DAG.getRoot(); 436 437 if (PendingLoads.size() == 1) { 438 SDOperand Root = PendingLoads[0]; 439 DAG.setRoot(Root); 440 PendingLoads.clear(); 441 return Root; 442 } 443 444 // Otherwise, we have to make a token factor node. 445 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 446 &PendingLoads[0], PendingLoads.size()); 447 PendingLoads.clear(); 448 DAG.setRoot(Root); 449 return Root; 450 } 451 452 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 453 454 void visit(Instruction &I) { visit(I.getOpcode(), I); } 455 456 void visit(unsigned Opcode, User &I) { 457 // Note: this doesn't use InstVisitor, because it has to work with 458 // ConstantExpr's in addition to instructions. 459 switch (Opcode) { 460 default: assert(0 && "Unknown instruction type encountered!"); 461 abort(); 462 // Build the switch statement using the Instruction.def file. 463#define HANDLE_INST(NUM, OPCODE, CLASS) \ 464 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 465#include "llvm/Instruction.def" 466 } 467 } 468 469 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 470 471 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 472 const Value *SV, SDOperand Root, 473 bool isVolatile, unsigned Alignment); 474 475 SDOperand getIntPtrConstant(uint64_t Val) { 476 return DAG.getConstant(Val, TLI.getPointerTy()); 477 } 478 479 SDOperand getValue(const Value *V); 480 481 void setValue(const Value *V, SDOperand NewN) { 482 SDOperand &N = NodeMap[V]; 483 assert(N.Val == 0 && "Already set a value for this node!"); 484 N = NewN; 485 } 486 487 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 488 std::set<unsigned> &OutputRegs, 489 std::set<unsigned> &InputRegs); 490 491 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 492 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 493 unsigned Opc); 494 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 495 void ExportFromCurrentBlock(Value *V); 496 void LowerCallTo(Instruction &I, 497 const Type *CalledValueTy, unsigned CallingConv, 498 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 499 MachineBasicBlock *LandingPad = NULL); 500 501 // Terminator instructions. 502 void visitRet(ReturnInst &I); 503 void visitBr(BranchInst &I); 504 void visitSwitch(SwitchInst &I); 505 void visitUnreachable(UnreachableInst &I) { /* noop */ } 506 507 // Helpers for visitSwitch 508 bool handleSmallSwitchRange(CaseRec& CR, 509 CaseRecVector& WorkList, 510 Value* SV, 511 MachineBasicBlock* Default); 512 bool handleJTSwitchCase(CaseRec& CR, 513 CaseRecVector& WorkList, 514 Value* SV, 515 MachineBasicBlock* Default); 516 bool handleBTSplitSwitchCase(CaseRec& CR, 517 CaseRecVector& WorkList, 518 Value* SV, 519 MachineBasicBlock* Default); 520 bool handleBitTestsSwitchCase(CaseRec& CR, 521 CaseRecVector& WorkList, 522 Value* SV, 523 MachineBasicBlock* Default); 524 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 525 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 526 void visitBitTestCase(MachineBasicBlock* NextMBB, 527 unsigned Reg, 528 SelectionDAGISel::BitTestCase &B); 529 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 530 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 531 SelectionDAGISel::JumpTableHeader &JTH); 532 533 // These all get lowered before this pass. 534 void visitInvoke(InvokeInst &I); 535 void visitUnwind(UnwindInst &I); 536 537 void visitBinary(User &I, unsigned OpCode); 538 void visitShift(User &I, unsigned Opcode); 539 void visitAdd(User &I) { 540 if (I.getType()->isFPOrFPVector()) 541 visitBinary(I, ISD::FADD); 542 else 543 visitBinary(I, ISD::ADD); 544 } 545 void visitSub(User &I); 546 void visitMul(User &I) { 547 if (I.getType()->isFPOrFPVector()) 548 visitBinary(I, ISD::FMUL); 549 else 550 visitBinary(I, ISD::MUL); 551 } 552 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 553 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 554 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 555 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 556 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 557 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 558 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 559 void visitOr (User &I) { visitBinary(I, ISD::OR); } 560 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 561 void visitShl (User &I) { visitShift(I, ISD::SHL); } 562 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 563 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 564 void visitICmp(User &I); 565 void visitFCmp(User &I); 566 // Visit the conversion instructions 567 void visitTrunc(User &I); 568 void visitZExt(User &I); 569 void visitSExt(User &I); 570 void visitFPTrunc(User &I); 571 void visitFPExt(User &I); 572 void visitFPToUI(User &I); 573 void visitFPToSI(User &I); 574 void visitUIToFP(User &I); 575 void visitSIToFP(User &I); 576 void visitPtrToInt(User &I); 577 void visitIntToPtr(User &I); 578 void visitBitCast(User &I); 579 580 void visitExtractElement(User &I); 581 void visitInsertElement(User &I); 582 void visitShuffleVector(User &I); 583 584 void visitGetElementPtr(User &I); 585 void visitSelect(User &I); 586 587 void visitMalloc(MallocInst &I); 588 void visitFree(FreeInst &I); 589 void visitAlloca(AllocaInst &I); 590 void visitLoad(LoadInst &I); 591 void visitStore(StoreInst &I); 592 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 593 void visitCall(CallInst &I); 594 void visitInlineAsm(CallInst &I); 595 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 596 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 597 598 void visitVAStart(CallInst &I); 599 void visitVAArg(VAArgInst &I); 600 void visitVAEnd(CallInst &I); 601 void visitVACopy(CallInst &I); 602 603 void visitMemIntrinsic(CallInst &I, unsigned Op); 604 605 void visitUserOp1(Instruction &I) { 606 assert(0 && "UserOp1 should not exist at instruction selection time!"); 607 abort(); 608 } 609 void visitUserOp2(Instruction &I) { 610 assert(0 && "UserOp2 should not exist at instruction selection time!"); 611 abort(); 612 } 613}; 614} // end namespace llvm 615 616 617/// getCopyFromParts - Create a value that contains the 618/// specified legal parts combined into the value they represent. 619static SDOperand getCopyFromParts(SelectionDAG &DAG, 620 const SDOperand *Parts, 621 unsigned NumParts, 622 MVT::ValueType PartVT, 623 MVT::ValueType ValueVT, 624 bool EndianOrder, 625 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 626 if (!MVT::isVector(ValueVT) || NumParts == 1) { 627 SDOperand Val = Parts[0]; 628 629 // If the value was expanded, copy from the top part. 630 if (NumParts > 1) { 631 assert(NumParts == 2 && 632 "Cannot expand to more than 2 elts yet!"); 633 SDOperand Hi = Parts[1]; 634 if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian()) 635 std::swap(Val, Hi); 636 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 637 } 638 639 // Otherwise, if the value was promoted or extended, truncate it to the 640 // appropriate type. 641 if (PartVT == ValueVT) 642 return Val; 643 644 if (MVT::isVector(PartVT)) { 645 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 646 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 647 } 648 649 if (MVT::isInteger(PartVT) && 650 MVT::isInteger(ValueVT)) { 651 if (ValueVT < PartVT) { 652 // For a truncate, see if we have any information to 653 // indicate whether the truncated bits will always be 654 // zero or sign-extension. 655 if (AssertOp != ISD::DELETED_NODE) 656 Val = DAG.getNode(AssertOp, PartVT, Val, 657 DAG.getValueType(ValueVT)); 658 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 659 } else { 660 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 661 } 662 } 663 664 if (MVT::isFloatingPoint(PartVT) && 665 MVT::isFloatingPoint(ValueVT)) 666 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 667 668 if (MVT::getSizeInBits(PartVT) == 669 MVT::getSizeInBits(ValueVT)) 670 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 671 672 assert(0 && "Unknown mismatch!"); 673 } 674 675 // Handle a multi-element vector. 676 MVT::ValueType IntermediateVT, RegisterVT; 677 unsigned NumIntermediates; 678 unsigned NumRegs = 679 DAG.getTargetLoweringInfo() 680 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 681 RegisterVT); 682 683 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 684 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 685 assert(RegisterVT == Parts[0].getValueType() && 686 "Part type doesn't match part!"); 687 688 // Assemble the parts into intermediate operands. 689 SmallVector<SDOperand, 8> Ops(NumIntermediates); 690 if (NumIntermediates == NumParts) { 691 // If the register was not expanded, truncate or copy the value, 692 // as appropriate. 693 for (unsigned i = 0; i != NumParts; ++i) 694 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 695 PartVT, IntermediateVT, EndianOrder); 696 } else if (NumParts > 0) { 697 // If the intermediate type was expanded, build the intermediate operands 698 // from the parts. 699 assert(NumIntermediates % NumParts == 0 && 700 "Must expand into a divisible number of parts!"); 701 unsigned Factor = NumIntermediates / NumParts; 702 for (unsigned i = 0; i != NumIntermediates; ++i) 703 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 704 PartVT, IntermediateVT, EndianOrder); 705 } 706 707 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 708 // operands. 709 return DAG.getNode(MVT::isVector(IntermediateVT) ? 710 ISD::CONCAT_VECTORS : 711 ISD::BUILD_VECTOR, 712 ValueVT, &Ops[0], NumParts); 713} 714 715/// getCopyToParts - Create a series of nodes that contain the 716/// specified value split into legal parts. 717static void getCopyToParts(SelectionDAG &DAG, 718 SDOperand Val, 719 SDOperand *Parts, 720 unsigned NumParts, 721 MVT::ValueType PartVT, 722 bool EndianOrder) { 723 MVT::ValueType ValueVT = Val.getValueType(); 724 725 if (!MVT::isVector(ValueVT) || NumParts == 1) { 726 // If the value was expanded, copy from the parts. 727 if (NumParts > 1) { 728 for (unsigned i = 0; i != NumParts; ++i) 729 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 730 DAG.getConstant(i, MVT::i32)); 731 if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian()) 732 std::reverse(Parts, Parts + NumParts); 733 return; 734 } 735 736 // If there is a single part and the types differ, this must be 737 // a promotion. 738 if (PartVT != ValueVT) { 739 if (MVT::isVector(PartVT)) { 740 assert(MVT::isVector(ValueVT) && 741 "Not a vector-vector cast?"); 742 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 743 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 744 if (PartVT < ValueVT) 745 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 746 else 747 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 748 } else if (MVT::isFloatingPoint(PartVT) && 749 MVT::isFloatingPoint(ValueVT)) { 750 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 751 } else if (MVT::getSizeInBits(PartVT) == 752 MVT::getSizeInBits(ValueVT)) { 753 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 754 } else { 755 assert(0 && "Unknown mismatch!"); 756 } 757 } 758 Parts[0] = Val; 759 return; 760 } 761 762 // Handle a multi-element vector. 763 MVT::ValueType IntermediateVT, RegisterVT; 764 unsigned NumIntermediates; 765 unsigned NumRegs = 766 DAG.getTargetLoweringInfo() 767 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 768 RegisterVT); 769 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 770 771 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 772 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 773 774 // Split the vector into intermediate operands. 775 SmallVector<SDOperand, 8> Ops(NumIntermediates); 776 for (unsigned i = 0; i != NumIntermediates; ++i) 777 if (MVT::isVector(IntermediateVT)) 778 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 779 IntermediateVT, Val, 780 DAG.getConstant(i * (NumElements / NumIntermediates), 781 MVT::i32)); 782 else 783 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 784 IntermediateVT, Val, 785 DAG.getConstant(i, MVT::i32)); 786 787 // Split the intermediate operands into legal parts. 788 if (NumParts == NumIntermediates) { 789 // If the register was not expanded, promote or copy the value, 790 // as appropriate. 791 for (unsigned i = 0; i != NumParts; ++i) 792 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT, EndianOrder); 793 } else if (NumParts > 0) { 794 // If the intermediate type was expanded, split each the value into 795 // legal parts. 796 assert(NumParts % NumIntermediates == 0 && 797 "Must expand into a divisible number of parts!"); 798 unsigned Factor = NumParts / NumIntermediates; 799 for (unsigned i = 0; i != NumIntermediates; ++i) 800 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT, EndianOrder); 801 } 802} 803 804 805SDOperand SelectionDAGLowering::getValue(const Value *V) { 806 SDOperand &N = NodeMap[V]; 807 if (N.Val) return N; 808 809 const Type *VTy = V->getType(); 810 MVT::ValueType VT = TLI.getValueType(VTy); 811 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 812 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 813 visit(CE->getOpcode(), *CE); 814 SDOperand N1 = NodeMap[V]; 815 assert(N1.Val && "visit didn't populate the ValueMap!"); 816 return N1; 817 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 818 return N = DAG.getGlobalAddress(GV, VT); 819 } else if (isa<ConstantPointerNull>(C)) { 820 return N = DAG.getConstant(0, TLI.getPointerTy()); 821 } else if (isa<UndefValue>(C)) { 822 if (!isa<VectorType>(VTy)) 823 return N = DAG.getNode(ISD::UNDEF, VT); 824 825 // Create a BUILD_VECTOR of undef nodes. 826 const VectorType *PTy = cast<VectorType>(VTy); 827 unsigned NumElements = PTy->getNumElements(); 828 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 829 830 SmallVector<SDOperand, 8> Ops; 831 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 832 833 // Create a VConstant node with generic Vector type. 834 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 835 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 836 &Ops[0], Ops.size()); 837 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 838 return N = DAG.getConstantFP(CFP->getValue(), VT); 839 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 840 unsigned NumElements = PTy->getNumElements(); 841 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 842 843 // Now that we know the number and type of the elements, push a 844 // Constant or ConstantFP node onto the ops list for each element of 845 // the packed constant. 846 SmallVector<SDOperand, 8> Ops; 847 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 848 for (unsigned i = 0; i != NumElements; ++i) 849 Ops.push_back(getValue(CP->getOperand(i))); 850 } else { 851 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 852 SDOperand Op; 853 if (MVT::isFloatingPoint(PVT)) 854 Op = DAG.getConstantFP(0, PVT); 855 else 856 Op = DAG.getConstant(0, PVT); 857 Ops.assign(NumElements, Op); 858 } 859 860 // Create a BUILD_VECTOR node. 861 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 862 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 863 Ops.size()); 864 } else { 865 // Canonicalize all constant ints to be unsigned. 866 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 867 } 868 } 869 870 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 871 std::map<const AllocaInst*, int>::iterator SI = 872 FuncInfo.StaticAllocaMap.find(AI); 873 if (SI != FuncInfo.StaticAllocaMap.end()) 874 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 875 } 876 877 unsigned InReg = FuncInfo.ValueMap[V]; 878 assert(InReg && "Value not in map!"); 879 880 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 881 unsigned NumRegs = TLI.getNumRegisters(VT); 882 883 std::vector<unsigned> Regs(NumRegs); 884 for (unsigned i = 0; i != NumRegs; ++i) 885 Regs[i] = InReg + i; 886 887 RegsForValue RFV(Regs, RegisterVT, VT); 888 SDOperand Chain = DAG.getEntryNode(); 889 890 return RFV.getCopyFromRegs(DAG, Chain, NULL); 891} 892 893 894void SelectionDAGLowering::visitRet(ReturnInst &I) { 895 if (I.getNumOperands() == 0) { 896 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 897 return; 898 } 899 SmallVector<SDOperand, 8> NewValues; 900 NewValues.push_back(getRoot()); 901 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 902 SDOperand RetOp = getValue(I.getOperand(i)); 903 904 // If this is an integer return value, we need to promote it ourselves to 905 // the full width of a register, since getCopyToParts and Legalize will use 906 // ANY_EXTEND rather than sign/zero. 907 // FIXME: C calling convention requires the return type to be promoted to 908 // at least 32-bit. But this is not necessary for non-C calling conventions. 909 if (MVT::isInteger(RetOp.getValueType()) && 910 RetOp.getValueType() < MVT::i64) { 911 MVT::ValueType TmpVT; 912 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 913 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 914 else 915 TmpVT = MVT::i32; 916 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 917 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 918 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 919 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 920 ExtendKind = ISD::SIGN_EXTEND; 921 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 922 ExtendKind = ISD::ZERO_EXTEND; 923 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 924 NewValues.push_back(RetOp); 925 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 926 } else { 927 MVT::ValueType VT = RetOp.getValueType(); 928 unsigned NumParts = TLI.getNumRegisters(VT); 929 MVT::ValueType PartVT = TLI.getRegisterType(VT); 930 SmallVector<SDOperand, 4> Parts(NumParts); 931 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, true); 932 for (unsigned i = 0; i < NumParts; ++i) { 933 NewValues.push_back(Parts[i]); 934 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 935 } 936 } 937 } 938 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 939 &NewValues[0], NewValues.size())); 940} 941 942/// ExportFromCurrentBlock - If this condition isn't known to be exported from 943/// the current basic block, add it to ValueMap now so that we'll get a 944/// CopyTo/FromReg. 945void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 946 // No need to export constants. 947 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 948 949 // Already exported? 950 if (FuncInfo.isExportedInst(V)) return; 951 952 unsigned Reg = FuncInfo.InitializeRegForValue(V); 953 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 954} 955 956bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 957 const BasicBlock *FromBB) { 958 // The operands of the setcc have to be in this block. We don't know 959 // how to export them from some other block. 960 if (Instruction *VI = dyn_cast<Instruction>(V)) { 961 // Can export from current BB. 962 if (VI->getParent() == FromBB) 963 return true; 964 965 // Is already exported, noop. 966 return FuncInfo.isExportedInst(V); 967 } 968 969 // If this is an argument, we can export it if the BB is the entry block or 970 // if it is already exported. 971 if (isa<Argument>(V)) { 972 if (FromBB == &FromBB->getParent()->getEntryBlock()) 973 return true; 974 975 // Otherwise, can only export this if it is already exported. 976 return FuncInfo.isExportedInst(V); 977 } 978 979 // Otherwise, constants can always be exported. 980 return true; 981} 982 983static bool InBlock(const Value *V, const BasicBlock *BB) { 984 if (const Instruction *I = dyn_cast<Instruction>(V)) 985 return I->getParent() == BB; 986 return true; 987} 988 989/// FindMergedConditions - If Cond is an expression like 990void SelectionDAGLowering::FindMergedConditions(Value *Cond, 991 MachineBasicBlock *TBB, 992 MachineBasicBlock *FBB, 993 MachineBasicBlock *CurBB, 994 unsigned Opc) { 995 // If this node is not part of the or/and tree, emit it as a branch. 996 Instruction *BOp = dyn_cast<Instruction>(Cond); 997 998 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 999 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1000 BOp->getParent() != CurBB->getBasicBlock() || 1001 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1002 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1003 const BasicBlock *BB = CurBB->getBasicBlock(); 1004 1005 // If the leaf of the tree is a comparison, merge the condition into 1006 // the caseblock. 1007 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1008 // The operands of the cmp have to be in this block. We don't know 1009 // how to export them from some other block. If this is the first block 1010 // of the sequence, no exporting is needed. 1011 (CurBB == CurMBB || 1012 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1013 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1014 BOp = cast<Instruction>(Cond); 1015 ISD::CondCode Condition; 1016 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1017 switch (IC->getPredicate()) { 1018 default: assert(0 && "Unknown icmp predicate opcode!"); 1019 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1020 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1021 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1022 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1023 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1024 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1025 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1026 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1027 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1028 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1029 } 1030 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1031 ISD::CondCode FPC, FOC; 1032 switch (FC->getPredicate()) { 1033 default: assert(0 && "Unknown fcmp predicate opcode!"); 1034 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1035 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1036 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1037 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1038 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1039 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1040 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1041 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1042 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1043 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1044 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1045 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1046 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1047 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1048 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1049 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1050 } 1051 if (FiniteOnlyFPMath()) 1052 Condition = FOC; 1053 else 1054 Condition = FPC; 1055 } else { 1056 Condition = ISD::SETEQ; // silence warning. 1057 assert(0 && "Unknown compare instruction"); 1058 } 1059 1060 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1061 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1062 SwitchCases.push_back(CB); 1063 return; 1064 } 1065 1066 // Create a CaseBlock record representing this branch. 1067 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1068 NULL, TBB, FBB, CurBB); 1069 SwitchCases.push_back(CB); 1070 return; 1071 } 1072 1073 1074 // Create TmpBB after CurBB. 1075 MachineFunction::iterator BBI = CurBB; 1076 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1077 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1078 1079 if (Opc == Instruction::Or) { 1080 // Codegen X | Y as: 1081 // jmp_if_X TBB 1082 // jmp TmpBB 1083 // TmpBB: 1084 // jmp_if_Y TBB 1085 // jmp FBB 1086 // 1087 1088 // Emit the LHS condition. 1089 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1090 1091 // Emit the RHS condition into TmpBB. 1092 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1093 } else { 1094 assert(Opc == Instruction::And && "Unknown merge op!"); 1095 // Codegen X & Y as: 1096 // jmp_if_X TmpBB 1097 // jmp FBB 1098 // TmpBB: 1099 // jmp_if_Y TBB 1100 // jmp FBB 1101 // 1102 // This requires creation of TmpBB after CurBB. 1103 1104 // Emit the LHS condition. 1105 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1106 1107 // Emit the RHS condition into TmpBB. 1108 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1109 } 1110} 1111 1112/// If the set of cases should be emitted as a series of branches, return true. 1113/// If we should emit this as a bunch of and/or'd together conditions, return 1114/// false. 1115static bool 1116ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1117 if (Cases.size() != 2) return true; 1118 1119 // If this is two comparisons of the same values or'd or and'd together, they 1120 // will get folded into a single comparison, so don't emit two blocks. 1121 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1122 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1123 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1124 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1125 return false; 1126 } 1127 1128 return true; 1129} 1130 1131void SelectionDAGLowering::visitBr(BranchInst &I) { 1132 // Update machine-CFG edges. 1133 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1134 1135 // Figure out which block is immediately after the current one. 1136 MachineBasicBlock *NextBlock = 0; 1137 MachineFunction::iterator BBI = CurMBB; 1138 if (++BBI != CurMBB->getParent()->end()) 1139 NextBlock = BBI; 1140 1141 if (I.isUnconditional()) { 1142 // If this is not a fall-through branch, emit the branch. 1143 if (Succ0MBB != NextBlock) 1144 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1145 DAG.getBasicBlock(Succ0MBB))); 1146 1147 // Update machine-CFG edges. 1148 CurMBB->addSuccessor(Succ0MBB); 1149 1150 return; 1151 } 1152 1153 // If this condition is one of the special cases we handle, do special stuff 1154 // now. 1155 Value *CondVal = I.getCondition(); 1156 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1157 1158 // If this is a series of conditions that are or'd or and'd together, emit 1159 // this as a sequence of branches instead of setcc's with and/or operations. 1160 // For example, instead of something like: 1161 // cmp A, B 1162 // C = seteq 1163 // cmp D, E 1164 // F = setle 1165 // or C, F 1166 // jnz foo 1167 // Emit: 1168 // cmp A, B 1169 // je foo 1170 // cmp D, E 1171 // jle foo 1172 // 1173 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1174 if (BOp->hasOneUse() && 1175 (BOp->getOpcode() == Instruction::And || 1176 BOp->getOpcode() == Instruction::Or)) { 1177 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1178 // If the compares in later blocks need to use values not currently 1179 // exported from this block, export them now. This block should always 1180 // be the first entry. 1181 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1182 1183 // Allow some cases to be rejected. 1184 if (ShouldEmitAsBranches(SwitchCases)) { 1185 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1186 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1187 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1188 } 1189 1190 // Emit the branch for this block. 1191 visitSwitchCase(SwitchCases[0]); 1192 SwitchCases.erase(SwitchCases.begin()); 1193 return; 1194 } 1195 1196 // Okay, we decided not to do this, remove any inserted MBB's and clear 1197 // SwitchCases. 1198 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1199 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1200 1201 SwitchCases.clear(); 1202 } 1203 } 1204 1205 // Create a CaseBlock record representing this branch. 1206 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1207 NULL, Succ0MBB, Succ1MBB, CurMBB); 1208 // Use visitSwitchCase to actually insert the fast branch sequence for this 1209 // cond branch. 1210 visitSwitchCase(CB); 1211} 1212 1213/// visitSwitchCase - Emits the necessary code to represent a single node in 1214/// the binary search tree resulting from lowering a switch instruction. 1215void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1216 SDOperand Cond; 1217 SDOperand CondLHS = getValue(CB.CmpLHS); 1218 1219 // Build the setcc now. 1220 if (CB.CmpMHS == NULL) { 1221 // Fold "(X == true)" to X and "(X == false)" to !X to 1222 // handle common cases produced by branch lowering. 1223 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1224 Cond = CondLHS; 1225 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1226 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1227 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1228 } else 1229 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1230 } else { 1231 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1232 1233 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1234 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1235 1236 SDOperand CmpOp = getValue(CB.CmpMHS); 1237 MVT::ValueType VT = CmpOp.getValueType(); 1238 1239 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1240 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1241 } else { 1242 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1243 Cond = DAG.getSetCC(MVT::i1, SUB, 1244 DAG.getConstant(High-Low, VT), ISD::SETULE); 1245 } 1246 1247 } 1248 1249 // Set NextBlock to be the MBB immediately after the current one, if any. 1250 // This is used to avoid emitting unnecessary branches to the next block. 1251 MachineBasicBlock *NextBlock = 0; 1252 MachineFunction::iterator BBI = CurMBB; 1253 if (++BBI != CurMBB->getParent()->end()) 1254 NextBlock = BBI; 1255 1256 // If the lhs block is the next block, invert the condition so that we can 1257 // fall through to the lhs instead of the rhs block. 1258 if (CB.TrueBB == NextBlock) { 1259 std::swap(CB.TrueBB, CB.FalseBB); 1260 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1261 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1262 } 1263 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1264 DAG.getBasicBlock(CB.TrueBB)); 1265 if (CB.FalseBB == NextBlock) 1266 DAG.setRoot(BrCond); 1267 else 1268 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1269 DAG.getBasicBlock(CB.FalseBB))); 1270 // Update successor info 1271 CurMBB->addSuccessor(CB.TrueBB); 1272 CurMBB->addSuccessor(CB.FalseBB); 1273} 1274 1275/// visitJumpTable - Emit JumpTable node in the current MBB 1276void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1277 // Emit the code for the jump table 1278 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1279 MVT::ValueType PTy = TLI.getPointerTy(); 1280 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1281 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1282 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1283 Table, Index)); 1284 return; 1285} 1286 1287/// visitJumpTableHeader - This function emits necessary code to produce index 1288/// in the JumpTable from switch case. 1289void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1290 SelectionDAGISel::JumpTableHeader &JTH) { 1291 // Subtract the lowest switch case value from the value being switched on 1292 // and conditional branch to default mbb if the result is greater than the 1293 // difference between smallest and largest cases. 1294 SDOperand SwitchOp = getValue(JTH.SValue); 1295 MVT::ValueType VT = SwitchOp.getValueType(); 1296 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1297 DAG.getConstant(JTH.First, VT)); 1298 1299 // The SDNode we just created, which holds the value being switched on 1300 // minus the the smallest case value, needs to be copied to a virtual 1301 // register so it can be used as an index into the jump table in a 1302 // subsequent basic block. This value may be smaller or larger than the 1303 // target's pointer type, and therefore require extension or truncating. 1304 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1305 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1306 else 1307 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1308 1309 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1310 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1311 JT.Reg = JumpTableReg; 1312 1313 // Emit the range check for the jump table, and branch to the default 1314 // block for the switch statement if the value being switched on exceeds 1315 // the largest case in the switch. 1316 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1317 DAG.getConstant(JTH.Last-JTH.First,VT), 1318 ISD::SETUGT); 1319 1320 // Set NextBlock to be the MBB immediately after the current one, if any. 1321 // This is used to avoid emitting unnecessary branches to the next block. 1322 MachineBasicBlock *NextBlock = 0; 1323 MachineFunction::iterator BBI = CurMBB; 1324 if (++BBI != CurMBB->getParent()->end()) 1325 NextBlock = BBI; 1326 1327 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1328 DAG.getBasicBlock(JT.Default)); 1329 1330 if (JT.MBB == NextBlock) 1331 DAG.setRoot(BrCond); 1332 else 1333 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1334 DAG.getBasicBlock(JT.MBB))); 1335 1336 return; 1337} 1338 1339/// visitBitTestHeader - This function emits necessary code to produce value 1340/// suitable for "bit tests" 1341void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1342 // Subtract the minimum value 1343 SDOperand SwitchOp = getValue(B.SValue); 1344 MVT::ValueType VT = SwitchOp.getValueType(); 1345 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1346 DAG.getConstant(B.First, VT)); 1347 1348 // Check range 1349 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1350 DAG.getConstant(B.Range, VT), 1351 ISD::SETUGT); 1352 1353 SDOperand ShiftOp; 1354 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1355 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1356 else 1357 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1358 1359 // Make desired shift 1360 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1361 DAG.getConstant(1, TLI.getPointerTy()), 1362 ShiftOp); 1363 1364 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1365 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1366 B.Reg = SwitchReg; 1367 1368 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1369 DAG.getBasicBlock(B.Default)); 1370 1371 // Set NextBlock to be the MBB immediately after the current one, if any. 1372 // This is used to avoid emitting unnecessary branches to the next block. 1373 MachineBasicBlock *NextBlock = 0; 1374 MachineFunction::iterator BBI = CurMBB; 1375 if (++BBI != CurMBB->getParent()->end()) 1376 NextBlock = BBI; 1377 1378 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1379 if (MBB == NextBlock) 1380 DAG.setRoot(BrRange); 1381 else 1382 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1383 DAG.getBasicBlock(MBB))); 1384 1385 CurMBB->addSuccessor(B.Default); 1386 CurMBB->addSuccessor(MBB); 1387 1388 return; 1389} 1390 1391/// visitBitTestCase - this function produces one "bit test" 1392void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1393 unsigned Reg, 1394 SelectionDAGISel::BitTestCase &B) { 1395 // Emit bit tests and jumps 1396 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1397 1398 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1399 SwitchVal, 1400 DAG.getConstant(B.Mask, 1401 TLI.getPointerTy())); 1402 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1403 DAG.getConstant(0, TLI.getPointerTy()), 1404 ISD::SETNE); 1405 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1406 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1407 1408 // Set NextBlock to be the MBB immediately after the current one, if any. 1409 // This is used to avoid emitting unnecessary branches to the next block. 1410 MachineBasicBlock *NextBlock = 0; 1411 MachineFunction::iterator BBI = CurMBB; 1412 if (++BBI != CurMBB->getParent()->end()) 1413 NextBlock = BBI; 1414 1415 if (NextMBB == NextBlock) 1416 DAG.setRoot(BrAnd); 1417 else 1418 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1419 DAG.getBasicBlock(NextMBB))); 1420 1421 CurMBB->addSuccessor(B.TargetBB); 1422 CurMBB->addSuccessor(NextMBB); 1423 1424 return; 1425} 1426 1427void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1428 // Retrieve successors. 1429 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1430 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1431 1432 LowerCallTo(I, I.getCalledValue()->getType(), 1433 I.getCallingConv(), 1434 false, 1435 getValue(I.getOperand(0)), 1436 3, LandingPad); 1437 1438 // If the value of the invoke is used outside of its defining block, make it 1439 // available as a virtual register. 1440 if (!I.use_empty()) { 1441 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1442 if (VMI != FuncInfo.ValueMap.end()) 1443 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1444 } 1445 1446 // Drop into normal successor. 1447 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1448 DAG.getBasicBlock(Return))); 1449 1450 // Update successor info 1451 CurMBB->addSuccessor(Return); 1452 CurMBB->addSuccessor(LandingPad); 1453} 1454 1455void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1456} 1457 1458/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1459/// small case ranges). 1460bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1461 CaseRecVector& WorkList, 1462 Value* SV, 1463 MachineBasicBlock* Default) { 1464 Case& BackCase = *(CR.Range.second-1); 1465 1466 // Size is the number of Cases represented by this range. 1467 unsigned Size = CR.Range.second - CR.Range.first; 1468 if (Size > 3) 1469 return false; 1470 1471 // Get the MachineFunction which holds the current MBB. This is used when 1472 // inserting any additional MBBs necessary to represent the switch. 1473 MachineFunction *CurMF = CurMBB->getParent(); 1474 1475 // Figure out which block is immediately after the current one. 1476 MachineBasicBlock *NextBlock = 0; 1477 MachineFunction::iterator BBI = CR.CaseBB; 1478 1479 if (++BBI != CurMBB->getParent()->end()) 1480 NextBlock = BBI; 1481 1482 // TODO: If any two of the cases has the same destination, and if one value 1483 // is the same as the other, but has one bit unset that the other has set, 1484 // use bit manipulation to do two compares at once. For example: 1485 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1486 1487 // Rearrange the case blocks so that the last one falls through if possible. 1488 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1489 // The last case block won't fall through into 'NextBlock' if we emit the 1490 // branches in this order. See if rearranging a case value would help. 1491 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1492 if (I->BB == NextBlock) { 1493 std::swap(*I, BackCase); 1494 break; 1495 } 1496 } 1497 } 1498 1499 // Create a CaseBlock record representing a conditional branch to 1500 // the Case's target mbb if the value being switched on SV is equal 1501 // to C. 1502 MachineBasicBlock *CurBlock = CR.CaseBB; 1503 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1504 MachineBasicBlock *FallThrough; 1505 if (I != E-1) { 1506 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1507 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1508 } else { 1509 // If the last case doesn't match, go to the default block. 1510 FallThrough = Default; 1511 } 1512 1513 Value *RHS, *LHS, *MHS; 1514 ISD::CondCode CC; 1515 if (I->High == I->Low) { 1516 // This is just small small case range :) containing exactly 1 case 1517 CC = ISD::SETEQ; 1518 LHS = SV; RHS = I->High; MHS = NULL; 1519 } else { 1520 CC = ISD::SETLE; 1521 LHS = I->Low; MHS = SV; RHS = I->High; 1522 } 1523 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1524 I->BB, FallThrough, CurBlock); 1525 1526 // If emitting the first comparison, just call visitSwitchCase to emit the 1527 // code into the current block. Otherwise, push the CaseBlock onto the 1528 // vector to be later processed by SDISel, and insert the node's MBB 1529 // before the next MBB. 1530 if (CurBlock == CurMBB) 1531 visitSwitchCase(CB); 1532 else 1533 SwitchCases.push_back(CB); 1534 1535 CurBlock = FallThrough; 1536 } 1537 1538 return true; 1539} 1540 1541static inline bool areJTsAllowed(const TargetLowering &TLI) { 1542 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1543 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1544} 1545 1546/// handleJTSwitchCase - Emit jumptable for current switch case range 1547bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1548 CaseRecVector& WorkList, 1549 Value* SV, 1550 MachineBasicBlock* Default) { 1551 Case& FrontCase = *CR.Range.first; 1552 Case& BackCase = *(CR.Range.second-1); 1553 1554 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1555 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1556 1557 uint64_t TSize = 0; 1558 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1559 I!=E; ++I) 1560 TSize += I->size(); 1561 1562 if (!areJTsAllowed(TLI) || TSize <= 3) 1563 return false; 1564 1565 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1566 if (Density < 0.4) 1567 return false; 1568 1569 DOUT << "Lowering jump table\n" 1570 << "First entry: " << First << ". Last entry: " << Last << "\n" 1571 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1572 1573 // Get the MachineFunction which holds the current MBB. This is used when 1574 // inserting any additional MBBs necessary to represent the switch. 1575 MachineFunction *CurMF = CurMBB->getParent(); 1576 1577 // Figure out which block is immediately after the current one. 1578 MachineBasicBlock *NextBlock = 0; 1579 MachineFunction::iterator BBI = CR.CaseBB; 1580 1581 if (++BBI != CurMBB->getParent()->end()) 1582 NextBlock = BBI; 1583 1584 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1585 1586 // Create a new basic block to hold the code for loading the address 1587 // of the jump table, and jumping to it. Update successor information; 1588 // we will either branch to the default case for the switch, or the jump 1589 // table. 1590 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1591 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1592 CR.CaseBB->addSuccessor(Default); 1593 CR.CaseBB->addSuccessor(JumpTableBB); 1594 1595 // Build a vector of destination BBs, corresponding to each target 1596 // of the jump table. If the value of the jump table slot corresponds to 1597 // a case statement, push the case's BB onto the vector, otherwise, push 1598 // the default BB. 1599 std::vector<MachineBasicBlock*> DestBBs; 1600 int64_t TEI = First; 1601 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1602 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1603 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1604 1605 if ((Low <= TEI) && (TEI <= High)) { 1606 DestBBs.push_back(I->BB); 1607 if (TEI==High) 1608 ++I; 1609 } else { 1610 DestBBs.push_back(Default); 1611 } 1612 } 1613 1614 // Update successor info. Add one edge to each unique successor. 1615 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1616 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1617 E = DestBBs.end(); I != E; ++I) { 1618 if (!SuccsHandled[(*I)->getNumber()]) { 1619 SuccsHandled[(*I)->getNumber()] = true; 1620 JumpTableBB->addSuccessor(*I); 1621 } 1622 } 1623 1624 // Create a jump table index for this jump table, or return an existing 1625 // one. 1626 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1627 1628 // Set the jump table information so that we can codegen it as a second 1629 // MachineBasicBlock 1630 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1631 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1632 (CR.CaseBB == CurMBB)); 1633 if (CR.CaseBB == CurMBB) 1634 visitJumpTableHeader(JT, JTH); 1635 1636 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1637 1638 return true; 1639} 1640 1641/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1642/// 2 subtrees. 1643bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1644 CaseRecVector& WorkList, 1645 Value* SV, 1646 MachineBasicBlock* Default) { 1647 // Get the MachineFunction which holds the current MBB. This is used when 1648 // inserting any additional MBBs necessary to represent the switch. 1649 MachineFunction *CurMF = CurMBB->getParent(); 1650 1651 // Figure out which block is immediately after the current one. 1652 MachineBasicBlock *NextBlock = 0; 1653 MachineFunction::iterator BBI = CR.CaseBB; 1654 1655 if (++BBI != CurMBB->getParent()->end()) 1656 NextBlock = BBI; 1657 1658 Case& FrontCase = *CR.Range.first; 1659 Case& BackCase = *(CR.Range.second-1); 1660 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1661 1662 // Size is the number of Cases represented by this range. 1663 unsigned Size = CR.Range.second - CR.Range.first; 1664 1665 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1666 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1667 double FMetric = 0; 1668 CaseItr Pivot = CR.Range.first + Size/2; 1669 1670 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1671 // (heuristically) allow us to emit JumpTable's later. 1672 uint64_t TSize = 0; 1673 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1674 I!=E; ++I) 1675 TSize += I->size(); 1676 1677 uint64_t LSize = FrontCase.size(); 1678 uint64_t RSize = TSize-LSize; 1679 DOUT << "Selecting best pivot: \n" 1680 << "First: " << First << ", Last: " << Last <<"\n" 1681 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1682 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1683 J!=E; ++I, ++J) { 1684 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1685 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1686 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1687 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1688 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1689 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1690 // Should always split in some non-trivial place 1691 DOUT <<"=>Step\n" 1692 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1693 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1694 << "Metric: " << Metric << "\n"; 1695 if (FMetric < Metric) { 1696 Pivot = J; 1697 FMetric = Metric; 1698 DOUT << "Current metric set to: " << FMetric << "\n"; 1699 } 1700 1701 LSize += J->size(); 1702 RSize -= J->size(); 1703 } 1704 if (areJTsAllowed(TLI)) { 1705 // If our case is dense we *really* should handle it earlier! 1706 assert((FMetric > 0) && "Should handle dense range earlier!"); 1707 } else { 1708 Pivot = CR.Range.first + Size/2; 1709 } 1710 1711 CaseRange LHSR(CR.Range.first, Pivot); 1712 CaseRange RHSR(Pivot, CR.Range.second); 1713 Constant *C = Pivot->Low; 1714 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1715 1716 // We know that we branch to the LHS if the Value being switched on is 1717 // less than the Pivot value, C. We use this to optimize our binary 1718 // tree a bit, by recognizing that if SV is greater than or equal to the 1719 // LHS's Case Value, and that Case Value is exactly one less than the 1720 // Pivot's Value, then we can branch directly to the LHS's Target, 1721 // rather than creating a leaf node for it. 1722 if ((LHSR.second - LHSR.first) == 1 && 1723 LHSR.first->High == CR.GE && 1724 cast<ConstantInt>(C)->getSExtValue() == 1725 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1726 TrueBB = LHSR.first->BB; 1727 } else { 1728 TrueBB = new MachineBasicBlock(LLVMBB); 1729 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1730 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1731 } 1732 1733 // Similar to the optimization above, if the Value being switched on is 1734 // known to be less than the Constant CR.LT, and the current Case Value 1735 // is CR.LT - 1, then we can branch directly to the target block for 1736 // the current Case Value, rather than emitting a RHS leaf node for it. 1737 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1738 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1739 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1740 FalseBB = RHSR.first->BB; 1741 } else { 1742 FalseBB = new MachineBasicBlock(LLVMBB); 1743 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1744 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1745 } 1746 1747 // Create a CaseBlock record representing a conditional branch to 1748 // the LHS node if the value being switched on SV is less than C. 1749 // Otherwise, branch to LHS. 1750 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1751 TrueBB, FalseBB, CR.CaseBB); 1752 1753 if (CR.CaseBB == CurMBB) 1754 visitSwitchCase(CB); 1755 else 1756 SwitchCases.push_back(CB); 1757 1758 return true; 1759} 1760 1761/// handleBitTestsSwitchCase - if current case range has few destination and 1762/// range span less, than machine word bitwidth, encode case range into series 1763/// of masks and emit bit tests with these masks. 1764bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1765 CaseRecVector& WorkList, 1766 Value* SV, 1767 MachineBasicBlock* Default){ 1768 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1769 1770 Case& FrontCase = *CR.Range.first; 1771 Case& BackCase = *(CR.Range.second-1); 1772 1773 // Get the MachineFunction which holds the current MBB. This is used when 1774 // inserting any additional MBBs necessary to represent the switch. 1775 MachineFunction *CurMF = CurMBB->getParent(); 1776 1777 unsigned numCmps = 0; 1778 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1779 I!=E; ++I) { 1780 // Single case counts one, case range - two. 1781 if (I->Low == I->High) 1782 numCmps +=1; 1783 else 1784 numCmps +=2; 1785 } 1786 1787 // Count unique destinations 1788 SmallSet<MachineBasicBlock*, 4> Dests; 1789 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1790 Dests.insert(I->BB); 1791 if (Dests.size() > 3) 1792 // Don't bother the code below, if there are too much unique destinations 1793 return false; 1794 } 1795 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1796 << "Total number of comparisons: " << numCmps << "\n"; 1797 1798 // Compute span of values. 1799 Constant* minValue = FrontCase.Low; 1800 Constant* maxValue = BackCase.High; 1801 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1802 cast<ConstantInt>(minValue)->getSExtValue(); 1803 DOUT << "Compare range: " << range << "\n" 1804 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1805 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1806 1807 if (range>=IntPtrBits || 1808 (!(Dests.size() == 1 && numCmps >= 3) && 1809 !(Dests.size() == 2 && numCmps >= 5) && 1810 !(Dests.size() >= 3 && numCmps >= 6))) 1811 return false; 1812 1813 DOUT << "Emitting bit tests\n"; 1814 int64_t lowBound = 0; 1815 1816 // Optimize the case where all the case values fit in a 1817 // word without having to subtract minValue. In this case, 1818 // we can optimize away the subtraction. 1819 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1820 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1821 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1822 } else { 1823 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1824 } 1825 1826 CaseBitsVector CasesBits; 1827 unsigned i, count = 0; 1828 1829 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1830 MachineBasicBlock* Dest = I->BB; 1831 for (i = 0; i < count; ++i) 1832 if (Dest == CasesBits[i].BB) 1833 break; 1834 1835 if (i == count) { 1836 assert((count < 3) && "Too much destinations to test!"); 1837 CasesBits.push_back(CaseBits(0, Dest, 0)); 1838 count++; 1839 } 1840 1841 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1842 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1843 1844 for (uint64_t j = lo; j <= hi; j++) { 1845 CasesBits[i].Mask |= 1ULL << j; 1846 CasesBits[i].Bits++; 1847 } 1848 1849 } 1850 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1851 1852 SelectionDAGISel::BitTestInfo BTC; 1853 1854 // Figure out which block is immediately after the current one. 1855 MachineFunction::iterator BBI = CR.CaseBB; 1856 ++BBI; 1857 1858 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1859 1860 DOUT << "Cases:\n"; 1861 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1862 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1863 << ", BB: " << CasesBits[i].BB << "\n"; 1864 1865 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1866 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1867 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1868 CaseBB, 1869 CasesBits[i].BB)); 1870 } 1871 1872 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1873 -1U, (CR.CaseBB == CurMBB), 1874 CR.CaseBB, Default, BTC); 1875 1876 if (CR.CaseBB == CurMBB) 1877 visitBitTestHeader(BTB); 1878 1879 BitTestCases.push_back(BTB); 1880 1881 return true; 1882} 1883 1884 1885// Clusterify - Transform simple list of Cases into list of CaseRange's 1886unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1887 const SwitchInst& SI) { 1888 unsigned numCmps = 0; 1889 1890 // Start with "simple" cases 1891 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1892 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1893 Cases.push_back(Case(SI.getSuccessorValue(i), 1894 SI.getSuccessorValue(i), 1895 SMBB)); 1896 } 1897 sort(Cases.begin(), Cases.end(), CaseCmp()); 1898 1899 // Merge case into clusters 1900 if (Cases.size()>=2) 1901 // Must recompute end() each iteration because it may be 1902 // invalidated by erase if we hold on to it 1903 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1904 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1905 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1906 MachineBasicBlock* nextBB = J->BB; 1907 MachineBasicBlock* currentBB = I->BB; 1908 1909 // If the two neighboring cases go to the same destination, merge them 1910 // into a single case. 1911 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1912 I->High = J->High; 1913 J = Cases.erase(J); 1914 } else { 1915 I = J++; 1916 } 1917 } 1918 1919 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1920 if (I->Low != I->High) 1921 // A range counts double, since it requires two compares. 1922 ++numCmps; 1923 } 1924 1925 return numCmps; 1926} 1927 1928void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1929 // Figure out which block is immediately after the current one. 1930 MachineBasicBlock *NextBlock = 0; 1931 MachineFunction::iterator BBI = CurMBB; 1932 1933 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1934 1935 // If there is only the default destination, branch to it if it is not the 1936 // next basic block. Otherwise, just fall through. 1937 if (SI.getNumOperands() == 2) { 1938 // Update machine-CFG edges. 1939 1940 // If this is not a fall-through branch, emit the branch. 1941 if (Default != NextBlock) 1942 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1943 DAG.getBasicBlock(Default))); 1944 1945 CurMBB->addSuccessor(Default); 1946 return; 1947 } 1948 1949 // If there are any non-default case statements, create a vector of Cases 1950 // representing each one, and sort the vector so that we can efficiently 1951 // create a binary search tree from them. 1952 CaseVector Cases; 1953 unsigned numCmps = Clusterify(Cases, SI); 1954 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1955 << ". Total compares: " << numCmps << "\n"; 1956 1957 // Get the Value to be switched on and default basic blocks, which will be 1958 // inserted into CaseBlock records, representing basic blocks in the binary 1959 // search tree. 1960 Value *SV = SI.getOperand(0); 1961 1962 // Push the initial CaseRec onto the worklist 1963 CaseRecVector WorkList; 1964 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1965 1966 while (!WorkList.empty()) { 1967 // Grab a record representing a case range to process off the worklist 1968 CaseRec CR = WorkList.back(); 1969 WorkList.pop_back(); 1970 1971 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1972 continue; 1973 1974 // If the range has few cases (two or less) emit a series of specific 1975 // tests. 1976 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1977 continue; 1978 1979 // If the switch has more than 5 blocks, and at least 40% dense, and the 1980 // target supports indirect branches, then emit a jump table rather than 1981 // lowering the switch to a binary tree of conditional branches. 1982 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1983 continue; 1984 1985 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1986 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1987 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1988 } 1989} 1990 1991 1992void SelectionDAGLowering::visitSub(User &I) { 1993 // -0.0 - X --> fneg 1994 const Type *Ty = I.getType(); 1995 if (isa<VectorType>(Ty)) { 1996 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 1997 const VectorType *DestTy = cast<VectorType>(I.getType()); 1998 const Type *ElTy = DestTy->getElementType(); 1999 if (ElTy->isFloatingPoint()) { 2000 unsigned VL = DestTy->getNumElements(); 2001 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0)); 2002 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2003 if (CV == CNZ) { 2004 SDOperand Op2 = getValue(I.getOperand(1)); 2005 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2006 return; 2007 } 2008 } 2009 } 2010 } 2011 if (Ty->isFloatingPoint()) { 2012 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2013 if (CFP->isExactlyValue(-0.0)) { 2014 SDOperand Op2 = getValue(I.getOperand(1)); 2015 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2016 return; 2017 } 2018 } 2019 2020 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2021} 2022 2023void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2024 SDOperand Op1 = getValue(I.getOperand(0)); 2025 SDOperand Op2 = getValue(I.getOperand(1)); 2026 2027 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2028} 2029 2030void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2031 SDOperand Op1 = getValue(I.getOperand(0)); 2032 SDOperand Op2 = getValue(I.getOperand(1)); 2033 2034 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2035 MVT::getSizeInBits(Op2.getValueType())) 2036 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2037 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2038 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2039 2040 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2041} 2042 2043void SelectionDAGLowering::visitICmp(User &I) { 2044 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2045 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2046 predicate = IC->getPredicate(); 2047 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2048 predicate = ICmpInst::Predicate(IC->getPredicate()); 2049 SDOperand Op1 = getValue(I.getOperand(0)); 2050 SDOperand Op2 = getValue(I.getOperand(1)); 2051 ISD::CondCode Opcode; 2052 switch (predicate) { 2053 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2054 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2055 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2056 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2057 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2058 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2059 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2060 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2061 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2062 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2063 default: 2064 assert(!"Invalid ICmp predicate value"); 2065 Opcode = ISD::SETEQ; 2066 break; 2067 } 2068 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2069} 2070 2071void SelectionDAGLowering::visitFCmp(User &I) { 2072 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2073 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2074 predicate = FC->getPredicate(); 2075 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2076 predicate = FCmpInst::Predicate(FC->getPredicate()); 2077 SDOperand Op1 = getValue(I.getOperand(0)); 2078 SDOperand Op2 = getValue(I.getOperand(1)); 2079 ISD::CondCode Condition, FOC, FPC; 2080 switch (predicate) { 2081 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2082 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2083 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2084 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2085 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2086 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2087 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2088 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2089 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2090 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2091 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2092 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2093 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2094 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2095 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2096 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2097 default: 2098 assert(!"Invalid FCmp predicate value"); 2099 FOC = FPC = ISD::SETFALSE; 2100 break; 2101 } 2102 if (FiniteOnlyFPMath()) 2103 Condition = FOC; 2104 else 2105 Condition = FPC; 2106 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2107} 2108 2109void SelectionDAGLowering::visitSelect(User &I) { 2110 SDOperand Cond = getValue(I.getOperand(0)); 2111 SDOperand TrueVal = getValue(I.getOperand(1)); 2112 SDOperand FalseVal = getValue(I.getOperand(2)); 2113 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2114 TrueVal, FalseVal)); 2115} 2116 2117 2118void SelectionDAGLowering::visitTrunc(User &I) { 2119 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2120 SDOperand N = getValue(I.getOperand(0)); 2121 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2122 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2123} 2124 2125void SelectionDAGLowering::visitZExt(User &I) { 2126 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2127 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2128 SDOperand N = getValue(I.getOperand(0)); 2129 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2130 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2131} 2132 2133void SelectionDAGLowering::visitSExt(User &I) { 2134 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2135 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2136 SDOperand N = getValue(I.getOperand(0)); 2137 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2138 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2139} 2140 2141void SelectionDAGLowering::visitFPTrunc(User &I) { 2142 // FPTrunc is never a no-op cast, no need to check 2143 SDOperand N = getValue(I.getOperand(0)); 2144 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2145 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2146} 2147 2148void SelectionDAGLowering::visitFPExt(User &I){ 2149 // FPTrunc is never a no-op cast, no need to check 2150 SDOperand N = getValue(I.getOperand(0)); 2151 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2152 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2153} 2154 2155void SelectionDAGLowering::visitFPToUI(User &I) { 2156 // FPToUI is never a no-op cast, no need to check 2157 SDOperand N = getValue(I.getOperand(0)); 2158 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2159 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2160} 2161 2162void SelectionDAGLowering::visitFPToSI(User &I) { 2163 // FPToSI is never a no-op cast, no need to check 2164 SDOperand N = getValue(I.getOperand(0)); 2165 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2166 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2167} 2168 2169void SelectionDAGLowering::visitUIToFP(User &I) { 2170 // UIToFP is never a no-op cast, no need to check 2171 SDOperand N = getValue(I.getOperand(0)); 2172 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2173 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2174} 2175 2176void SelectionDAGLowering::visitSIToFP(User &I){ 2177 // UIToFP is never a no-op cast, no need to check 2178 SDOperand N = getValue(I.getOperand(0)); 2179 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2180 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2181} 2182 2183void SelectionDAGLowering::visitPtrToInt(User &I) { 2184 // What to do depends on the size of the integer and the size of the pointer. 2185 // We can either truncate, zero extend, or no-op, accordingly. 2186 SDOperand N = getValue(I.getOperand(0)); 2187 MVT::ValueType SrcVT = N.getValueType(); 2188 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2189 SDOperand Result; 2190 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2191 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2192 else 2193 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2194 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2195 setValue(&I, Result); 2196} 2197 2198void SelectionDAGLowering::visitIntToPtr(User &I) { 2199 // What to do depends on the size of the integer and the size of the pointer. 2200 // We can either truncate, zero extend, or no-op, accordingly. 2201 SDOperand N = getValue(I.getOperand(0)); 2202 MVT::ValueType SrcVT = N.getValueType(); 2203 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2204 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2205 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2206 else 2207 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2208 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2209} 2210 2211void SelectionDAGLowering::visitBitCast(User &I) { 2212 SDOperand N = getValue(I.getOperand(0)); 2213 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2214 2215 // BitCast assures us that source and destination are the same size so this 2216 // is either a BIT_CONVERT or a no-op. 2217 if (DestVT != N.getValueType()) 2218 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2219 else 2220 setValue(&I, N); // noop cast. 2221} 2222 2223void SelectionDAGLowering::visitInsertElement(User &I) { 2224 SDOperand InVec = getValue(I.getOperand(0)); 2225 SDOperand InVal = getValue(I.getOperand(1)); 2226 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2227 getValue(I.getOperand(2))); 2228 2229 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2230 TLI.getValueType(I.getType()), 2231 InVec, InVal, InIdx)); 2232} 2233 2234void SelectionDAGLowering::visitExtractElement(User &I) { 2235 SDOperand InVec = getValue(I.getOperand(0)); 2236 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2237 getValue(I.getOperand(1))); 2238 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2239 TLI.getValueType(I.getType()), InVec, InIdx)); 2240} 2241 2242void SelectionDAGLowering::visitShuffleVector(User &I) { 2243 SDOperand V1 = getValue(I.getOperand(0)); 2244 SDOperand V2 = getValue(I.getOperand(1)); 2245 SDOperand Mask = getValue(I.getOperand(2)); 2246 2247 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2248 TLI.getValueType(I.getType()), 2249 V1, V2, Mask)); 2250} 2251 2252 2253void SelectionDAGLowering::visitGetElementPtr(User &I) { 2254 SDOperand N = getValue(I.getOperand(0)); 2255 const Type *Ty = I.getOperand(0)->getType(); 2256 2257 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2258 OI != E; ++OI) { 2259 Value *Idx = *OI; 2260 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2261 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2262 if (Field) { 2263 // N = N + Offset 2264 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2265 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2266 getIntPtrConstant(Offset)); 2267 } 2268 Ty = StTy->getElementType(Field); 2269 } else { 2270 Ty = cast<SequentialType>(Ty)->getElementType(); 2271 2272 // If this is a constant subscript, handle it quickly. 2273 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2274 if (CI->getZExtValue() == 0) continue; 2275 uint64_t Offs = 2276 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2277 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2278 continue; 2279 } 2280 2281 // N = N + Idx * ElementSize; 2282 uint64_t ElementSize = TD->getTypeSize(Ty); 2283 SDOperand IdxN = getValue(Idx); 2284 2285 // If the index is smaller or larger than intptr_t, truncate or extend 2286 // it. 2287 if (IdxN.getValueType() < N.getValueType()) { 2288 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2289 } else if (IdxN.getValueType() > N.getValueType()) 2290 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2291 2292 // If this is a multiply by a power of two, turn it into a shl 2293 // immediately. This is a very common case. 2294 if (isPowerOf2_64(ElementSize)) { 2295 unsigned Amt = Log2_64(ElementSize); 2296 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2297 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2298 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2299 continue; 2300 } 2301 2302 SDOperand Scale = getIntPtrConstant(ElementSize); 2303 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2304 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2305 } 2306 } 2307 setValue(&I, N); 2308} 2309 2310void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2311 // If this is a fixed sized alloca in the entry block of the function, 2312 // allocate it statically on the stack. 2313 if (FuncInfo.StaticAllocaMap.count(&I)) 2314 return; // getValue will auto-populate this. 2315 2316 const Type *Ty = I.getAllocatedType(); 2317 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2318 unsigned Align = 2319 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2320 I.getAlignment()); 2321 2322 SDOperand AllocSize = getValue(I.getArraySize()); 2323 MVT::ValueType IntPtr = TLI.getPointerTy(); 2324 if (IntPtr < AllocSize.getValueType()) 2325 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2326 else if (IntPtr > AllocSize.getValueType()) 2327 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2328 2329 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2330 getIntPtrConstant(TySize)); 2331 2332 // Handle alignment. If the requested alignment is less than or equal to the 2333 // stack alignment, ignore it and round the size of the allocation up to the 2334 // stack alignment size. If the size is greater than the stack alignment, we 2335 // note this in the DYNAMIC_STACKALLOC node. 2336 unsigned StackAlign = 2337 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2338 if (Align <= StackAlign) { 2339 Align = 0; 2340 // Add SA-1 to the size. 2341 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2342 getIntPtrConstant(StackAlign-1)); 2343 // Mask out the low bits for alignment purposes. 2344 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2345 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2346 } 2347 2348 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2349 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2350 MVT::Other); 2351 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2352 setValue(&I, DSA); 2353 DAG.setRoot(DSA.getValue(1)); 2354 2355 // Inform the Frame Information that we have just allocated a variable-sized 2356 // object. 2357 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2358} 2359 2360void SelectionDAGLowering::visitLoad(LoadInst &I) { 2361 SDOperand Ptr = getValue(I.getOperand(0)); 2362 2363 SDOperand Root; 2364 if (I.isVolatile()) 2365 Root = getRoot(); 2366 else { 2367 // Do not serialize non-volatile loads against each other. 2368 Root = DAG.getRoot(); 2369 } 2370 2371 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2372 Root, I.isVolatile(), I.getAlignment())); 2373} 2374 2375SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2376 const Value *SV, SDOperand Root, 2377 bool isVolatile, 2378 unsigned Alignment) { 2379 SDOperand L = 2380 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2381 isVolatile, Alignment); 2382 2383 if (isVolatile) 2384 DAG.setRoot(L.getValue(1)); 2385 else 2386 PendingLoads.push_back(L.getValue(1)); 2387 2388 return L; 2389} 2390 2391 2392void SelectionDAGLowering::visitStore(StoreInst &I) { 2393 Value *SrcV = I.getOperand(0); 2394 SDOperand Src = getValue(SrcV); 2395 SDOperand Ptr = getValue(I.getOperand(1)); 2396 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2397 I.isVolatile(), I.getAlignment())); 2398} 2399 2400/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2401/// access memory and has no other side effects at all. 2402static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2403#define GET_NO_MEMORY_INTRINSICS 2404#include "llvm/Intrinsics.gen" 2405#undef GET_NO_MEMORY_INTRINSICS 2406 return false; 2407} 2408 2409// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2410// have any side-effects or if it only reads memory. 2411static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2412#define GET_SIDE_EFFECT_INFO 2413#include "llvm/Intrinsics.gen" 2414#undef GET_SIDE_EFFECT_INFO 2415 return false; 2416} 2417 2418/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2419/// node. 2420void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2421 unsigned Intrinsic) { 2422 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2423 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2424 2425 // Build the operand list. 2426 SmallVector<SDOperand, 8> Ops; 2427 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2428 if (OnlyLoad) { 2429 // We don't need to serialize loads against other loads. 2430 Ops.push_back(DAG.getRoot()); 2431 } else { 2432 Ops.push_back(getRoot()); 2433 } 2434 } 2435 2436 // Add the intrinsic ID as an integer operand. 2437 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2438 2439 // Add all operands of the call to the operand list. 2440 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2441 SDOperand Op = getValue(I.getOperand(i)); 2442 assert(TLI.isTypeLegal(Op.getValueType()) && 2443 "Intrinsic uses a non-legal type?"); 2444 Ops.push_back(Op); 2445 } 2446 2447 std::vector<MVT::ValueType> VTs; 2448 if (I.getType() != Type::VoidTy) { 2449 MVT::ValueType VT = TLI.getValueType(I.getType()); 2450 if (MVT::isVector(VT)) { 2451 const VectorType *DestTy = cast<VectorType>(I.getType()); 2452 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2453 2454 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2455 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2456 } 2457 2458 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2459 VTs.push_back(VT); 2460 } 2461 if (HasChain) 2462 VTs.push_back(MVT::Other); 2463 2464 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2465 2466 // Create the node. 2467 SDOperand Result; 2468 if (!HasChain) 2469 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2470 &Ops[0], Ops.size()); 2471 else if (I.getType() != Type::VoidTy) 2472 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2473 &Ops[0], Ops.size()); 2474 else 2475 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2476 &Ops[0], Ops.size()); 2477 2478 if (HasChain) { 2479 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2480 if (OnlyLoad) 2481 PendingLoads.push_back(Chain); 2482 else 2483 DAG.setRoot(Chain); 2484 } 2485 if (I.getType() != Type::VoidTy) { 2486 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2487 MVT::ValueType VT = TLI.getValueType(PTy); 2488 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2489 } 2490 setValue(&I, Result); 2491 } 2492} 2493 2494/// ExtractGlobalVariable - If V is a global variable, or a bitcast of one 2495/// (possibly constant folded), return it. Otherwise return NULL. 2496static GlobalVariable *ExtractGlobalVariable (Value *V) { 2497 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(V)) 2498 return GV; 2499 else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 2500 if (CE->getOpcode() == Instruction::BitCast) 2501 return dyn_cast<GlobalVariable>(CE->getOperand(0)); 2502 else if (CE->getOpcode() == Instruction::GetElementPtr) { 2503 for (unsigned i = 1, e = CE->getNumOperands(); i != e; ++i) 2504 if (!CE->getOperand(i)->isNullValue()) 2505 return NULL; 2506 return dyn_cast<GlobalVariable>(CE->getOperand(0)); 2507 } 2508 } 2509 return NULL; 2510} 2511 2512/// ExtractTypeInfo - Extracts the type info from a value. 2513static GlobalVariable *ExtractTypeInfo (Value *V) { 2514 GlobalVariable *GV = ExtractGlobalVariable(V); 2515 assert (GV || isa<ConstantPointerNull>(V) && 2516 "TypeInfo must be a global variable or NULL"); 2517 return GV; 2518} 2519 2520/// addCatchInfo - Extract the personality and type infos from an eh.selector 2521/// call, and add them to the specified machine basic block. 2522static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2523 MachineBasicBlock *MBB) { 2524 // Inform the MachineModuleInfo of the personality for this landing pad. 2525 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2526 assert(CE->getOpcode() == Instruction::BitCast && 2527 isa<Function>(CE->getOperand(0)) && 2528 "Personality should be a function"); 2529 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2530 2531 // Gather all the type infos for this landing pad and pass them along to 2532 // MachineModuleInfo. 2533 std::vector<GlobalVariable *> TyInfo; 2534 unsigned N = I.getNumOperands(); 2535 2536 for (unsigned i = N - 1; i > 2; --i) { 2537 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2538 unsigned FilterLength = CI->getZExtValue(); 2539 unsigned FirstCatch = i + FilterLength + 1; 2540 assert (FirstCatch <= N && "Invalid filter length"); 2541 2542 if (FirstCatch < N) { 2543 TyInfo.reserve(N - FirstCatch); 2544 for (unsigned j = FirstCatch; j < N; ++j) 2545 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2546 MMI->addCatchTypeInfo(MBB, TyInfo); 2547 TyInfo.clear(); 2548 } 2549 2550 TyInfo.reserve(FilterLength); 2551 for (unsigned j = i + 1; j < FirstCatch; ++j) 2552 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2553 MMI->addFilterTypeInfo(MBB, TyInfo); 2554 TyInfo.clear(); 2555 2556 N = i; 2557 } 2558 } 2559 2560 if (N > 3) { 2561 TyInfo.reserve(N - 3); 2562 for (unsigned j = 3; j < N; ++j) 2563 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2564 MMI->addCatchTypeInfo(MBB, TyInfo); 2565 } 2566} 2567 2568/// propagateEHRegister - The specified EH register is required in a successor 2569/// of the EH landing pad. Propagate it (by adding it to livein) to all the 2570/// blocks in the paths between the landing pad and the specified block. 2571static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg, 2572 SmallPtrSet<MachineBasicBlock*, 8> Visited) { 2573 if (MBB->isLandingPad() || !Visited.insert(MBB)) 2574 return; 2575 2576 MBB->addLiveIn(EHReg); 2577 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), 2578 E = MBB->pred_end(); PI != E; ++PI) 2579 propagateEHRegister(*PI, EHReg, Visited); 2580} 2581 2582static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg) { 2583 SmallPtrSet<MachineBasicBlock*, 8> Visited; 2584 propagateEHRegister(MBB, EHReg, Visited); 2585} 2586 2587/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2588/// we want to emit this as a call to a named external function, return the name 2589/// otherwise lower it and return null. 2590const char * 2591SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2592 switch (Intrinsic) { 2593 default: 2594 // By default, turn this into a target intrinsic node. 2595 visitTargetIntrinsic(I, Intrinsic); 2596 return 0; 2597 case Intrinsic::vastart: visitVAStart(I); return 0; 2598 case Intrinsic::vaend: visitVAEnd(I); return 0; 2599 case Intrinsic::vacopy: visitVACopy(I); return 0; 2600 case Intrinsic::returnaddress: 2601 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2602 getValue(I.getOperand(1)))); 2603 return 0; 2604 case Intrinsic::frameaddress: 2605 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2606 getValue(I.getOperand(1)))); 2607 return 0; 2608 case Intrinsic::setjmp: 2609 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2610 break; 2611 case Intrinsic::longjmp: 2612 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2613 break; 2614 case Intrinsic::memcpy_i32: 2615 case Intrinsic::memcpy_i64: 2616 visitMemIntrinsic(I, ISD::MEMCPY); 2617 return 0; 2618 case Intrinsic::memset_i32: 2619 case Intrinsic::memset_i64: 2620 visitMemIntrinsic(I, ISD::MEMSET); 2621 return 0; 2622 case Intrinsic::memmove_i32: 2623 case Intrinsic::memmove_i64: 2624 visitMemIntrinsic(I, ISD::MEMMOVE); 2625 return 0; 2626 2627 case Intrinsic::dbg_stoppoint: { 2628 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2629 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2630 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2631 SDOperand Ops[5]; 2632 2633 Ops[0] = getRoot(); 2634 Ops[1] = getValue(SPI.getLineValue()); 2635 Ops[2] = getValue(SPI.getColumnValue()); 2636 2637 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2638 assert(DD && "Not a debug information descriptor"); 2639 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2640 2641 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2642 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2643 2644 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2645 } 2646 2647 return 0; 2648 } 2649 case Intrinsic::dbg_region_start: { 2650 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2651 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2652 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2653 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2654 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2655 DAG.getConstant(LabelID, MVT::i32))); 2656 } 2657 2658 return 0; 2659 } 2660 case Intrinsic::dbg_region_end: { 2661 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2662 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2663 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2664 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2665 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2666 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2667 } 2668 2669 return 0; 2670 } 2671 case Intrinsic::dbg_func_start: { 2672 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2673 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2674 if (MMI && FSI.getSubprogram() && 2675 MMI->Verify(FSI.getSubprogram())) { 2676 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2677 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2678 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2679 } 2680 2681 return 0; 2682 } 2683 case Intrinsic::dbg_declare: { 2684 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2685 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2686 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2687 SDOperand AddressOp = getValue(DI.getAddress()); 2688 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2689 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2690 } 2691 2692 return 0; 2693 } 2694 2695 case Intrinsic::eh_exception: { 2696 if (ExceptionHandling) { 2697 if (!CurMBB->isLandingPad() && TLI.getExceptionAddressRegister()) 2698 propagateEHRegister(CurMBB, TLI.getExceptionAddressRegister()); 2699 2700 // Insert the EXCEPTIONADDR instruction. 2701 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2702 SDOperand Ops[1]; 2703 Ops[0] = DAG.getRoot(); 2704 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2705 setValue(&I, Op); 2706 DAG.setRoot(Op.getValue(1)); 2707 } else { 2708 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2709 } 2710 return 0; 2711 } 2712 2713 case Intrinsic::eh_selector:{ 2714 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2715 2716 if (ExceptionHandling && MMI) { 2717 if (CurMBB->isLandingPad()) 2718 addCatchInfo(I, MMI, CurMBB); 2719 else { 2720#ifndef NDEBUG 2721 FuncInfo.CatchInfoLost.insert(&I); 2722#endif 2723 if (TLI.getExceptionSelectorRegister()) 2724 propagateEHRegister(CurMBB, TLI.getExceptionSelectorRegister()); 2725 } 2726 2727 // Insert the EHSELECTION instruction. 2728 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2729 SDOperand Ops[2]; 2730 Ops[0] = getValue(I.getOperand(1)); 2731 Ops[1] = getRoot(); 2732 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2733 setValue(&I, Op); 2734 DAG.setRoot(Op.getValue(1)); 2735 } else { 2736 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2737 } 2738 2739 return 0; 2740 } 2741 2742 case Intrinsic::eh_typeid_for: { 2743 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2744 2745 if (MMI) { 2746 // Find the type id for the given typeinfo. 2747 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2748 2749 unsigned TypeID = MMI->getTypeIDFor(GV); 2750 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2751 } else { 2752 setValue(&I, DAG.getConstant(0, MVT::i32)); 2753 } 2754 2755 return 0; 2756 } 2757 2758 case Intrinsic::sqrt_f32: 2759 case Intrinsic::sqrt_f64: 2760 setValue(&I, DAG.getNode(ISD::FSQRT, 2761 getValue(I.getOperand(1)).getValueType(), 2762 getValue(I.getOperand(1)))); 2763 return 0; 2764 case Intrinsic::powi_f32: 2765 case Intrinsic::powi_f64: 2766 setValue(&I, DAG.getNode(ISD::FPOWI, 2767 getValue(I.getOperand(1)).getValueType(), 2768 getValue(I.getOperand(1)), 2769 getValue(I.getOperand(2)))); 2770 return 0; 2771 case Intrinsic::pcmarker: { 2772 SDOperand Tmp = getValue(I.getOperand(1)); 2773 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2774 return 0; 2775 } 2776 case Intrinsic::readcyclecounter: { 2777 SDOperand Op = getRoot(); 2778 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2779 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2780 &Op, 1); 2781 setValue(&I, Tmp); 2782 DAG.setRoot(Tmp.getValue(1)); 2783 return 0; 2784 } 2785 case Intrinsic::part_select: { 2786 // Currently not implemented: just abort 2787 assert(0 && "part_select intrinsic not implemented"); 2788 abort(); 2789 } 2790 case Intrinsic::part_set: { 2791 // Currently not implemented: just abort 2792 assert(0 && "part_set intrinsic not implemented"); 2793 abort(); 2794 } 2795 case Intrinsic::bswap: 2796 setValue(&I, DAG.getNode(ISD::BSWAP, 2797 getValue(I.getOperand(1)).getValueType(), 2798 getValue(I.getOperand(1)))); 2799 return 0; 2800 case Intrinsic::cttz: { 2801 SDOperand Arg = getValue(I.getOperand(1)); 2802 MVT::ValueType Ty = Arg.getValueType(); 2803 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2804 if (Ty < MVT::i32) 2805 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2806 else if (Ty > MVT::i32) 2807 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2808 setValue(&I, result); 2809 return 0; 2810 } 2811 case Intrinsic::ctlz: { 2812 SDOperand Arg = getValue(I.getOperand(1)); 2813 MVT::ValueType Ty = Arg.getValueType(); 2814 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2815 if (Ty < MVT::i32) 2816 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2817 else if (Ty > MVT::i32) 2818 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2819 setValue(&I, result); 2820 return 0; 2821 } 2822 case Intrinsic::ctpop: { 2823 SDOperand Arg = getValue(I.getOperand(1)); 2824 MVT::ValueType Ty = Arg.getValueType(); 2825 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2826 if (Ty < MVT::i32) 2827 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2828 else if (Ty > MVT::i32) 2829 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2830 setValue(&I, result); 2831 return 0; 2832 } 2833 case Intrinsic::stacksave: { 2834 SDOperand Op = getRoot(); 2835 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2836 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2837 setValue(&I, Tmp); 2838 DAG.setRoot(Tmp.getValue(1)); 2839 return 0; 2840 } 2841 case Intrinsic::stackrestore: { 2842 SDOperand Tmp = getValue(I.getOperand(1)); 2843 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2844 return 0; 2845 } 2846 case Intrinsic::prefetch: 2847 // FIXME: Currently discarding prefetches. 2848 return 0; 2849 2850 case Intrinsic::var_annotation: 2851 // Discard annotate attributes 2852 return 0; 2853 } 2854} 2855 2856 2857void SelectionDAGLowering::LowerCallTo(Instruction &I, 2858 const Type *CalledValueTy, 2859 unsigned CallingConv, 2860 bool IsTailCall, 2861 SDOperand Callee, unsigned OpIdx, 2862 MachineBasicBlock *LandingPad) { 2863 const PointerType *PT = cast<PointerType>(CalledValueTy); 2864 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2865 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2866 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2867 unsigned BeginLabel = 0, EndLabel = 0; 2868 2869 TargetLowering::ArgListTy Args; 2870 TargetLowering::ArgListEntry Entry; 2871 Args.reserve(I.getNumOperands()); 2872 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2873 Value *Arg = I.getOperand(i); 2874 SDOperand ArgNode = getValue(Arg); 2875 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2876 2877 unsigned attrInd = i - OpIdx + 1; 2878 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2879 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2880 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2881 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2882 Args.push_back(Entry); 2883 } 2884 2885 if (ExceptionHandling && MMI) { 2886 // Insert a label before the invoke call to mark the try range. This can be 2887 // used to detect deletion of the invoke via the MachineModuleInfo. 2888 BeginLabel = MMI->NextLabelID(); 2889 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2890 DAG.getConstant(BeginLabel, MVT::i32))); 2891 } 2892 2893 std::pair<SDOperand,SDOperand> Result = 2894 TLI.LowerCallTo(getRoot(), I.getType(), 2895 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2896 FTy->isVarArg(), CallingConv, IsTailCall, 2897 Callee, Args, DAG); 2898 if (I.getType() != Type::VoidTy) 2899 setValue(&I, Result.first); 2900 DAG.setRoot(Result.second); 2901 2902 if (ExceptionHandling && MMI) { 2903 // Insert a label at the end of the invoke call to mark the try range. This 2904 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2905 EndLabel = MMI->NextLabelID(); 2906 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2907 DAG.getConstant(EndLabel, MVT::i32))); 2908 2909 // Inform MachineModuleInfo of range. 2910 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2911 } 2912} 2913 2914 2915void SelectionDAGLowering::visitCall(CallInst &I) { 2916 const char *RenameFn = 0; 2917 if (Function *F = I.getCalledFunction()) { 2918 if (F->isDeclaration()) 2919 if (unsigned IID = F->getIntrinsicID()) { 2920 RenameFn = visitIntrinsicCall(I, IID); 2921 if (!RenameFn) 2922 return; 2923 } else { // Not an LLVM intrinsic. 2924 const std::string &Name = F->getName(); 2925 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2926 if (I.getNumOperands() == 3 && // Basic sanity checks. 2927 I.getOperand(1)->getType()->isFloatingPoint() && 2928 I.getType() == I.getOperand(1)->getType() && 2929 I.getType() == I.getOperand(2)->getType()) { 2930 SDOperand LHS = getValue(I.getOperand(1)); 2931 SDOperand RHS = getValue(I.getOperand(2)); 2932 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2933 LHS, RHS)); 2934 return; 2935 } 2936 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2937 if (I.getNumOperands() == 2 && // Basic sanity checks. 2938 I.getOperand(1)->getType()->isFloatingPoint() && 2939 I.getType() == I.getOperand(1)->getType()) { 2940 SDOperand Tmp = getValue(I.getOperand(1)); 2941 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2942 return; 2943 } 2944 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2945 if (I.getNumOperands() == 2 && // Basic sanity checks. 2946 I.getOperand(1)->getType()->isFloatingPoint() && 2947 I.getType() == I.getOperand(1)->getType()) { 2948 SDOperand Tmp = getValue(I.getOperand(1)); 2949 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2950 return; 2951 } 2952 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2953 if (I.getNumOperands() == 2 && // Basic sanity checks. 2954 I.getOperand(1)->getType()->isFloatingPoint() && 2955 I.getType() == I.getOperand(1)->getType()) { 2956 SDOperand Tmp = getValue(I.getOperand(1)); 2957 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2958 return; 2959 } 2960 } 2961 } 2962 } else if (isa<InlineAsm>(I.getOperand(0))) { 2963 visitInlineAsm(I); 2964 return; 2965 } 2966 2967 SDOperand Callee; 2968 if (!RenameFn) 2969 Callee = getValue(I.getOperand(0)); 2970 else 2971 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2972 2973 LowerCallTo(I, I.getCalledValue()->getType(), 2974 I.getCallingConv(), 2975 I.isTailCall(), 2976 Callee, 2977 1); 2978} 2979 2980 2981/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 2982/// this value and returns the result as a ValueVT value. This uses 2983/// Chain/Flag as the input and updates them for the output Chain/Flag. 2984/// If the Flag pointer is NULL, no flag is used. 2985SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2986 SDOperand &Chain, SDOperand *Flag)const{ 2987 // Get the list of registers, in the appropriate order. 2988 std::vector<unsigned> R(Regs); 2989 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2990 std::reverse(R.begin(), R.end()); 2991 2992 // Copy the legal parts from the registers. 2993 unsigned NumParts = Regs.size(); 2994 SmallVector<SDOperand, 8> Parts(NumParts); 2995 for (unsigned i = 0; i != NumParts; ++i) { 2996 SDOperand Part = Flag ? 2997 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 2998 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 2999 Chain = Part.getValue(1); 3000 if (Flag) 3001 *Flag = Part.getValue(2); 3002 Parts[i] = Part; 3003 } 3004 3005 // Assemble the legal parts into the final value. 3006 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT, false); 3007} 3008 3009/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3010/// specified value into the registers specified by this object. This uses 3011/// Chain/Flag as the input and updates them for the output Chain/Flag. 3012/// If the Flag pointer is NULL, no flag is used. 3013void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3014 SDOperand &Chain, SDOperand *Flag) const { 3015 // Get the list of registers, in the appropriate order. 3016 std::vector<unsigned> R(Regs); 3017 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 3018 std::reverse(R.begin(), R.end()); 3019 3020 // Get the list of the values's legal parts. 3021 unsigned NumParts = Regs.size(); 3022 SmallVector<SDOperand, 8> Parts(NumParts); 3023 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT, false); 3024 3025 // Copy the parts into the registers. 3026 for (unsigned i = 0; i != NumParts; ++i) { 3027 SDOperand Part = Flag ? 3028 DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) : 3029 DAG.getCopyToReg(Chain, R[i], Parts[i]); 3030 Chain = Part.getValue(0); 3031 if (Flag) 3032 *Flag = Part.getValue(1); 3033 } 3034} 3035 3036/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3037/// operand list. This adds the code marker and includes the number of 3038/// values added into it. 3039void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3040 std::vector<SDOperand> &Ops) const { 3041 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3042 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3043 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3044 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3045} 3046 3047/// isAllocatableRegister - If the specified register is safe to allocate, 3048/// i.e. it isn't a stack pointer or some other special register, return the 3049/// register class for the register. Otherwise, return null. 3050static const TargetRegisterClass * 3051isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3052 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3053 MVT::ValueType FoundVT = MVT::Other; 3054 const TargetRegisterClass *FoundRC = 0; 3055 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3056 E = MRI->regclass_end(); RCI != E; ++RCI) { 3057 MVT::ValueType ThisVT = MVT::Other; 3058 3059 const TargetRegisterClass *RC = *RCI; 3060 // If none of the the value types for this register class are valid, we 3061 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3062 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3063 I != E; ++I) { 3064 if (TLI.isTypeLegal(*I)) { 3065 // If we have already found this register in a different register class, 3066 // choose the one with the largest VT specified. For example, on 3067 // PowerPC, we favor f64 register classes over f32. 3068 if (FoundVT == MVT::Other || 3069 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3070 ThisVT = *I; 3071 break; 3072 } 3073 } 3074 } 3075 3076 if (ThisVT == MVT::Other) continue; 3077 3078 // NOTE: This isn't ideal. In particular, this might allocate the 3079 // frame pointer in functions that need it (due to them not being taken 3080 // out of allocation, because a variable sized allocation hasn't been seen 3081 // yet). This is a slight code pessimization, but should still work. 3082 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3083 E = RC->allocation_order_end(MF); I != E; ++I) 3084 if (*I == Reg) { 3085 // We found a matching register class. Keep looking at others in case 3086 // we find one with larger registers that this physreg is also in. 3087 FoundRC = RC; 3088 FoundVT = ThisVT; 3089 break; 3090 } 3091 } 3092 return FoundRC; 3093} 3094 3095 3096namespace { 3097/// AsmOperandInfo - This contains information for each constraint that we are 3098/// lowering. 3099struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3100 /// ConstraintCode - This contains the actual string for the code, like "m". 3101 std::string ConstraintCode; 3102 3103 /// ConstraintType - Information about the constraint code, e.g. Register, 3104 /// RegisterClass, Memory, Other, Unknown. 3105 TargetLowering::ConstraintType ConstraintType; 3106 3107 /// CallOperand/CallOperandval - If this is the result output operand or a 3108 /// clobber, this is null, otherwise it is the incoming operand to the 3109 /// CallInst. This gets modified as the asm is processed. 3110 SDOperand CallOperand; 3111 Value *CallOperandVal; 3112 3113 /// ConstraintVT - The ValueType for the operand value. 3114 MVT::ValueType ConstraintVT; 3115 3116 /// AssignedRegs - If this is a register or register class operand, this 3117 /// contains the set of register corresponding to the operand. 3118 RegsForValue AssignedRegs; 3119 3120 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3121 : InlineAsm::ConstraintInfo(info), 3122 ConstraintType(TargetLowering::C_Unknown), 3123 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3124 } 3125 3126 void ComputeConstraintToUse(const TargetLowering &TLI); 3127 3128 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3129 /// busy in OutputRegs/InputRegs. 3130 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3131 std::set<unsigned> &OutputRegs, 3132 std::set<unsigned> &InputRegs) const { 3133 if (isOutReg) 3134 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3135 if (isInReg) 3136 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3137 } 3138}; 3139} // end anon namespace. 3140 3141/// getConstraintGenerality - Return an integer indicating how general CT is. 3142static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3143 switch (CT) { 3144 default: assert(0 && "Unknown constraint type!"); 3145 case TargetLowering::C_Other: 3146 case TargetLowering::C_Unknown: 3147 return 0; 3148 case TargetLowering::C_Register: 3149 return 1; 3150 case TargetLowering::C_RegisterClass: 3151 return 2; 3152 case TargetLowering::C_Memory: 3153 return 3; 3154 } 3155} 3156 3157void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3158 assert(!Codes.empty() && "Must have at least one constraint"); 3159 3160 std::string *Current = &Codes[0]; 3161 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3162 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3163 ConstraintCode = *Current; 3164 ConstraintType = CurType; 3165 return; 3166 } 3167 3168 unsigned CurGenerality = getConstraintGenerality(CurType); 3169 3170 // If we have multiple constraints, try to pick the most general one ahead 3171 // of time. This isn't a wonderful solution, but handles common cases. 3172 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3173 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3174 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3175 if (ThisGenerality > CurGenerality) { 3176 // This constraint letter is more general than the previous one, 3177 // use it. 3178 CurType = ThisType; 3179 Current = &Codes[j]; 3180 CurGenerality = ThisGenerality; 3181 } 3182 } 3183 3184 ConstraintCode = *Current; 3185 ConstraintType = CurType; 3186} 3187 3188 3189void SelectionDAGLowering:: 3190GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3191 std::set<unsigned> &OutputRegs, 3192 std::set<unsigned> &InputRegs) { 3193 // Compute whether this value requires an input register, an output register, 3194 // or both. 3195 bool isOutReg = false; 3196 bool isInReg = false; 3197 switch (OpInfo.Type) { 3198 case InlineAsm::isOutput: 3199 isOutReg = true; 3200 3201 // If this is an early-clobber output, or if there is an input 3202 // constraint that matches this, we need to reserve the input register 3203 // so no other inputs allocate to it. 3204 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3205 break; 3206 case InlineAsm::isInput: 3207 isInReg = true; 3208 isOutReg = false; 3209 break; 3210 case InlineAsm::isClobber: 3211 isOutReg = true; 3212 isInReg = true; 3213 break; 3214 } 3215 3216 3217 MachineFunction &MF = DAG.getMachineFunction(); 3218 std::vector<unsigned> Regs; 3219 3220 // If this is a constraint for a single physreg, or a constraint for a 3221 // register class, find it. 3222 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3223 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3224 OpInfo.ConstraintVT); 3225 3226 unsigned NumRegs = 1; 3227 if (OpInfo.ConstraintVT != MVT::Other) 3228 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3229 MVT::ValueType RegVT; 3230 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3231 3232 3233 // If this is a constraint for a specific physical register, like {r17}, 3234 // assign it now. 3235 if (PhysReg.first) { 3236 if (OpInfo.ConstraintVT == MVT::Other) 3237 ValueVT = *PhysReg.second->vt_begin(); 3238 3239 // Get the actual register value type. This is important, because the user 3240 // may have asked for (e.g.) the AX register in i32 type. We need to 3241 // remember that AX is actually i16 to get the right extension. 3242 RegVT = *PhysReg.second->vt_begin(); 3243 3244 // This is a explicit reference to a physical register. 3245 Regs.push_back(PhysReg.first); 3246 3247 // If this is an expanded reference, add the rest of the regs to Regs. 3248 if (NumRegs != 1) { 3249 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3250 TargetRegisterClass::iterator E = PhysReg.second->end(); 3251 for (; *I != PhysReg.first; ++I) 3252 assert(I != E && "Didn't find reg!"); 3253 3254 // Already added the first reg. 3255 --NumRegs; ++I; 3256 for (; NumRegs; --NumRegs, ++I) { 3257 assert(I != E && "Ran out of registers to allocate!"); 3258 Regs.push_back(*I); 3259 } 3260 } 3261 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3262 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3263 return; 3264 } 3265 3266 // Otherwise, if this was a reference to an LLVM register class, create vregs 3267 // for this reference. 3268 std::vector<unsigned> RegClassRegs; 3269 const TargetRegisterClass *RC = PhysReg.second; 3270 if (RC) { 3271 // If this is an early clobber or tied register, our regalloc doesn't know 3272 // how to maintain the constraint. If it isn't, go ahead and create vreg 3273 // and let the regalloc do the right thing. 3274 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3275 // If there is some other early clobber and this is an input register, 3276 // then we are forced to pre-allocate the input reg so it doesn't 3277 // conflict with the earlyclobber. 3278 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3279 RegVT = *PhysReg.second->vt_begin(); 3280 3281 if (OpInfo.ConstraintVT == MVT::Other) 3282 ValueVT = RegVT; 3283 3284 // Create the appropriate number of virtual registers. 3285 SSARegMap *RegMap = MF.getSSARegMap(); 3286 for (; NumRegs; --NumRegs) 3287 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3288 3289 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3290 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3291 return; 3292 } 3293 3294 // Otherwise, we can't allocate it. Let the code below figure out how to 3295 // maintain these constraints. 3296 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3297 3298 } else { 3299 // This is a reference to a register class that doesn't directly correspond 3300 // to an LLVM register class. Allocate NumRegs consecutive, available, 3301 // registers from the class. 3302 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3303 OpInfo.ConstraintVT); 3304 } 3305 3306 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3307 unsigned NumAllocated = 0; 3308 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3309 unsigned Reg = RegClassRegs[i]; 3310 // See if this register is available. 3311 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3312 (isInReg && InputRegs.count(Reg))) { // Already used. 3313 // Make sure we find consecutive registers. 3314 NumAllocated = 0; 3315 continue; 3316 } 3317 3318 // Check to see if this register is allocatable (i.e. don't give out the 3319 // stack pointer). 3320 if (RC == 0) { 3321 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3322 if (!RC) { // Couldn't allocate this register. 3323 // Reset NumAllocated to make sure we return consecutive registers. 3324 NumAllocated = 0; 3325 continue; 3326 } 3327 } 3328 3329 // Okay, this register is good, we can use it. 3330 ++NumAllocated; 3331 3332 // If we allocated enough consecutive registers, succeed. 3333 if (NumAllocated == NumRegs) { 3334 unsigned RegStart = (i-NumAllocated)+1; 3335 unsigned RegEnd = i+1; 3336 // Mark all of the allocated registers used. 3337 for (unsigned i = RegStart; i != RegEnd; ++i) 3338 Regs.push_back(RegClassRegs[i]); 3339 3340 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3341 OpInfo.ConstraintVT); 3342 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3343 return; 3344 } 3345 } 3346 3347 // Otherwise, we couldn't allocate enough registers for this. 3348 return; 3349} 3350 3351 3352/// visitInlineAsm - Handle a call to an InlineAsm object. 3353/// 3354void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3355 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3356 3357 /// ConstraintOperands - Information about all of the constraints. 3358 std::vector<AsmOperandInfo> ConstraintOperands; 3359 3360 SDOperand Chain = getRoot(); 3361 SDOperand Flag; 3362 3363 std::set<unsigned> OutputRegs, InputRegs; 3364 3365 // Do a prepass over the constraints, canonicalizing them, and building up the 3366 // ConstraintOperands list. 3367 std::vector<InlineAsm::ConstraintInfo> 3368 ConstraintInfos = IA->ParseConstraints(); 3369 3370 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3371 // constraint. If so, we can't let the register allocator allocate any input 3372 // registers, because it will not know to avoid the earlyclobbered output reg. 3373 bool SawEarlyClobber = false; 3374 3375 unsigned OpNo = 1; // OpNo - The operand of the CallInst. 3376 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3377 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3378 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3379 3380 MVT::ValueType OpVT = MVT::Other; 3381 3382 // Compute the value type for each operand. 3383 switch (OpInfo.Type) { 3384 case InlineAsm::isOutput: 3385 if (!OpInfo.isIndirect) { 3386 // The return value of the call is this value. As such, there is no 3387 // corresponding argument. 3388 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3389 OpVT = TLI.getValueType(I.getType()); 3390 } else { 3391 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3392 } 3393 break; 3394 case InlineAsm::isInput: 3395 OpInfo.CallOperandVal = I.getOperand(OpNo++); 3396 break; 3397 case InlineAsm::isClobber: 3398 // Nothing to do. 3399 break; 3400 } 3401 3402 // If this is an input or an indirect output, process the call argument. 3403 if (OpInfo.CallOperandVal) { 3404 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3405 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3406 // If this is an indirect operand, the operand is a pointer to the 3407 // accessed type. 3408 if (OpInfo.isIndirect) 3409 OpTy = cast<PointerType>(OpTy)->getElementType(); 3410 3411 // If OpTy is not a first-class value, it may be a struct/union that we 3412 // can tile with integers. 3413 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3414 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3415 switch (BitSize) { 3416 default: break; 3417 case 1: 3418 case 8: 3419 case 16: 3420 case 32: 3421 case 64: 3422 OpTy = IntegerType::get(BitSize); 3423 break; 3424 } 3425 } 3426 3427 OpVT = TLI.getValueType(OpTy, true); 3428 } 3429 3430 OpInfo.ConstraintVT = OpVT; 3431 3432 // Compute the constraint code and ConstraintType to use. 3433 OpInfo.ComputeConstraintToUse(TLI); 3434 3435 // Keep track of whether we see an earlyclobber. 3436 SawEarlyClobber |= OpInfo.isEarlyClobber; 3437 3438 // If this is a memory input, and if the operand is not indirect, do what we 3439 // need to to provide an address for the memory input. 3440 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3441 !OpInfo.isIndirect) { 3442 assert(OpInfo.Type == InlineAsm::isInput && 3443 "Can only indirectify direct input operands!"); 3444 3445 // Memory operands really want the address of the value. If we don't have 3446 // an indirect input, put it in the constpool if we can, otherwise spill 3447 // it to a stack slot. 3448 3449 // If the operand is a float, integer, or vector constant, spill to a 3450 // constant pool entry to get its address. 3451 Value *OpVal = OpInfo.CallOperandVal; 3452 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3453 isa<ConstantVector>(OpVal)) { 3454 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3455 TLI.getPointerTy()); 3456 } else { 3457 // Otherwise, create a stack slot and emit a store to it before the 3458 // asm. 3459 const Type *Ty = OpVal->getType(); 3460 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3461 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3462 MachineFunction &MF = DAG.getMachineFunction(); 3463 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3464 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3465 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3466 OpInfo.CallOperand = StackSlot; 3467 } 3468 3469 // There is no longer a Value* corresponding to this operand. 3470 OpInfo.CallOperandVal = 0; 3471 // It is now an indirect operand. 3472 OpInfo.isIndirect = true; 3473 } 3474 3475 // If this constraint is for a specific register, allocate it before 3476 // anything else. 3477 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3478 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3479 } 3480 ConstraintInfos.clear(); 3481 3482 3483 // Second pass - Loop over all of the operands, assigning virtual or physregs 3484 // to registerclass operands. 3485 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3486 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3487 3488 // C_Register operands have already been allocated, Other/Memory don't need 3489 // to be. 3490 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3491 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3492 } 3493 3494 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3495 std::vector<SDOperand> AsmNodeOperands; 3496 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3497 AsmNodeOperands.push_back( 3498 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3499 3500 3501 // Loop over all of the inputs, copying the operand values into the 3502 // appropriate registers and processing the output regs. 3503 RegsForValue RetValRegs; 3504 3505 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3506 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3507 3508 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3509 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3510 3511 switch (OpInfo.Type) { 3512 case InlineAsm::isOutput: { 3513 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3514 OpInfo.ConstraintType != TargetLowering::C_Register) { 3515 // Memory output, or 'other' output (e.g. 'X' constraint). 3516 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3517 3518 // Add information to the INLINEASM node to know about this output. 3519 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3520 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3521 TLI.getPointerTy())); 3522 AsmNodeOperands.push_back(OpInfo.CallOperand); 3523 break; 3524 } 3525 3526 // Otherwise, this is a register or register class output. 3527 3528 // Copy the output from the appropriate register. Find a register that 3529 // we can use. 3530 if (OpInfo.AssignedRegs.Regs.empty()) { 3531 cerr << "Couldn't allocate output reg for contraint '" 3532 << OpInfo.ConstraintCode << "'!\n"; 3533 exit(1); 3534 } 3535 3536 if (!OpInfo.isIndirect) { 3537 // This is the result value of the call. 3538 assert(RetValRegs.Regs.empty() && 3539 "Cannot have multiple output constraints yet!"); 3540 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3541 RetValRegs = OpInfo.AssignedRegs; 3542 } else { 3543 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3544 OpInfo.CallOperandVal)); 3545 } 3546 3547 // Add information to the INLINEASM node to know that this register is 3548 // set. 3549 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3550 AsmNodeOperands); 3551 break; 3552 } 3553 case InlineAsm::isInput: { 3554 SDOperand InOperandVal = OpInfo.CallOperand; 3555 3556 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3557 // If this is required to match an output register we have already set, 3558 // just use its register. 3559 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3560 3561 // Scan until we find the definition we already emitted of this operand. 3562 // When we find it, create a RegsForValue operand. 3563 unsigned CurOp = 2; // The first operand. 3564 for (; OperandNo; --OperandNo) { 3565 // Advance to the next operand. 3566 unsigned NumOps = 3567 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3568 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3569 (NumOps & 7) == 4 /*MEM*/) && 3570 "Skipped past definitions?"); 3571 CurOp += (NumOps>>3)+1; 3572 } 3573 3574 unsigned NumOps = 3575 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3576 if ((NumOps & 7) == 2 /*REGDEF*/) { 3577 // Add NumOps>>3 registers to MatchedRegs. 3578 RegsForValue MatchedRegs; 3579 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3580 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3581 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3582 unsigned Reg = 3583 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3584 MatchedRegs.Regs.push_back(Reg); 3585 } 3586 3587 // Use the produced MatchedRegs object to 3588 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3589 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3590 break; 3591 } else { 3592 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3593 assert(0 && "matching constraints for memory operands unimp"); 3594 } 3595 } 3596 3597 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3598 assert(!OpInfo.isIndirect && 3599 "Don't know how to handle indirect other inputs yet!"); 3600 3601 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 3602 OpInfo.ConstraintCode[0], 3603 DAG); 3604 if (!InOperandVal.Val) { 3605 cerr << "Invalid operand for inline asm constraint '" 3606 << OpInfo.ConstraintCode << "'!\n"; 3607 exit(1); 3608 } 3609 3610 // Add information to the INLINEASM node to know about this input. 3611 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 3612 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3613 TLI.getPointerTy())); 3614 AsmNodeOperands.push_back(InOperandVal); 3615 break; 3616 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3617 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3618 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3619 "Memory operands expect pointer values"); 3620 3621 // Add information to the INLINEASM node to know about this input. 3622 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3623 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3624 TLI.getPointerTy())); 3625 AsmNodeOperands.push_back(InOperandVal); 3626 break; 3627 } 3628 3629 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3630 OpInfo.ConstraintType == TargetLowering::C_Register) && 3631 "Unknown constraint type!"); 3632 assert(!OpInfo.isIndirect && 3633 "Don't know how to handle indirect register inputs yet!"); 3634 3635 // Copy the input into the appropriate registers. 3636 assert(!OpInfo.AssignedRegs.Regs.empty() && 3637 "Couldn't allocate input reg!"); 3638 3639 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3640 3641 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3642 AsmNodeOperands); 3643 break; 3644 } 3645 case InlineAsm::isClobber: { 3646 // Add the clobbered value to the operand list, so that the register 3647 // allocator is aware that the physreg got clobbered. 3648 if (!OpInfo.AssignedRegs.Regs.empty()) 3649 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3650 AsmNodeOperands); 3651 break; 3652 } 3653 } 3654 } 3655 3656 // Finish up input operands. 3657 AsmNodeOperands[0] = Chain; 3658 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3659 3660 Chain = DAG.getNode(ISD::INLINEASM, 3661 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3662 &AsmNodeOperands[0], AsmNodeOperands.size()); 3663 Flag = Chain.getValue(1); 3664 3665 // If this asm returns a register value, copy the result from that register 3666 // and set it as the value of the call. 3667 if (!RetValRegs.Regs.empty()) { 3668 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3669 3670 // If the result of the inline asm is a vector, it may have the wrong 3671 // width/num elts. Make sure to convert it to the right type with 3672 // bit_convert. 3673 if (MVT::isVector(Val.getValueType())) { 3674 const VectorType *VTy = cast<VectorType>(I.getType()); 3675 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3676 3677 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3678 } 3679 3680 setValue(&I, Val); 3681 } 3682 3683 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3684 3685 // Process indirect outputs, first output all of the flagged copies out of 3686 // physregs. 3687 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3688 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3689 Value *Ptr = IndirectStoresToEmit[i].second; 3690 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3691 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3692 } 3693 3694 // Emit the non-flagged stores from the physregs. 3695 SmallVector<SDOperand, 8> OutChains; 3696 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3697 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3698 getValue(StoresToEmit[i].second), 3699 StoresToEmit[i].second, 0)); 3700 if (!OutChains.empty()) 3701 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3702 &OutChains[0], OutChains.size()); 3703 DAG.setRoot(Chain); 3704} 3705 3706 3707void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3708 SDOperand Src = getValue(I.getOperand(0)); 3709 3710 MVT::ValueType IntPtr = TLI.getPointerTy(); 3711 3712 if (IntPtr < Src.getValueType()) 3713 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3714 else if (IntPtr > Src.getValueType()) 3715 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3716 3717 // Scale the source by the type size. 3718 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3719 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3720 Src, getIntPtrConstant(ElementSize)); 3721 3722 TargetLowering::ArgListTy Args; 3723 TargetLowering::ArgListEntry Entry; 3724 Entry.Node = Src; 3725 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3726 Args.push_back(Entry); 3727 3728 std::pair<SDOperand,SDOperand> Result = 3729 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3730 DAG.getExternalSymbol("malloc", IntPtr), 3731 Args, DAG); 3732 setValue(&I, Result.first); // Pointers always fit in registers 3733 DAG.setRoot(Result.second); 3734} 3735 3736void SelectionDAGLowering::visitFree(FreeInst &I) { 3737 TargetLowering::ArgListTy Args; 3738 TargetLowering::ArgListEntry Entry; 3739 Entry.Node = getValue(I.getOperand(0)); 3740 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3741 Args.push_back(Entry); 3742 MVT::ValueType IntPtr = TLI.getPointerTy(); 3743 std::pair<SDOperand,SDOperand> Result = 3744 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3745 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3746 DAG.setRoot(Result.second); 3747} 3748 3749// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3750// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3751// instructions are special in various ways, which require special support to 3752// insert. The specified MachineInstr is created but not inserted into any 3753// basic blocks, and the scheduler passes ownership of it to this method. 3754MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3755 MachineBasicBlock *MBB) { 3756 cerr << "If a target marks an instruction with " 3757 << "'usesCustomDAGSchedInserter', it must implement " 3758 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3759 abort(); 3760 return 0; 3761} 3762 3763void SelectionDAGLowering::visitVAStart(CallInst &I) { 3764 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3765 getValue(I.getOperand(1)), 3766 DAG.getSrcValue(I.getOperand(1)))); 3767} 3768 3769void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3770 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3771 getValue(I.getOperand(0)), 3772 DAG.getSrcValue(I.getOperand(0))); 3773 setValue(&I, V); 3774 DAG.setRoot(V.getValue(1)); 3775} 3776 3777void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3778 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3779 getValue(I.getOperand(1)), 3780 DAG.getSrcValue(I.getOperand(1)))); 3781} 3782 3783void SelectionDAGLowering::visitVACopy(CallInst &I) { 3784 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3785 getValue(I.getOperand(1)), 3786 getValue(I.getOperand(2)), 3787 DAG.getSrcValue(I.getOperand(1)), 3788 DAG.getSrcValue(I.getOperand(2)))); 3789} 3790 3791/// TargetLowering::LowerArguments - This is the default LowerArguments 3792/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3793/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3794/// integrated into SDISel. 3795std::vector<SDOperand> 3796TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3797 const FunctionType *FTy = F.getFunctionType(); 3798 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3799 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3800 std::vector<SDOperand> Ops; 3801 Ops.push_back(DAG.getRoot()); 3802 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3803 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3804 3805 // Add one result value for each formal argument. 3806 std::vector<MVT::ValueType> RetVals; 3807 unsigned j = 1; 3808 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3809 I != E; ++I, ++j) { 3810 MVT::ValueType VT = getValueType(I->getType()); 3811 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3812 unsigned OriginalAlignment = 3813 getTargetData()->getABITypeAlignment(I->getType()); 3814 3815 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3816 // that is zero extended! 3817 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3818 Flags &= ~(ISD::ParamFlags::SExt); 3819 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3820 Flags |= ISD::ParamFlags::SExt; 3821 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3822 Flags |= ISD::ParamFlags::InReg; 3823 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3824 Flags |= ISD::ParamFlags::StructReturn; 3825 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3826 3827 switch (getTypeAction(VT)) { 3828 default: assert(0 && "Unknown type action!"); 3829 case Legal: 3830 RetVals.push_back(VT); 3831 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3832 break; 3833 case Promote: 3834 RetVals.push_back(getTypeToTransformTo(VT)); 3835 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3836 break; 3837 case Expand: { 3838 // If this is an illegal type, it needs to be broken up to fit into 3839 // registers. 3840 MVT::ValueType RegisterVT = getRegisterType(VT); 3841 unsigned NumRegs = getNumRegisters(VT); 3842 for (unsigned i = 0; i != NumRegs; ++i) { 3843 RetVals.push_back(RegisterVT); 3844 // if it isn't first piece, alignment must be 1 3845 if (i > 0) 3846 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3847 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3848 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3849 } 3850 break; 3851 } 3852 } 3853 } 3854 3855 RetVals.push_back(MVT::Other); 3856 3857 // Create the node. 3858 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3859 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3860 &Ops[0], Ops.size()).Val; 3861 unsigned NumArgRegs = Result->getNumValues() - 1; 3862 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3863 3864 // Set up the return result vector. 3865 Ops.clear(); 3866 unsigned i = 0; 3867 unsigned Idx = 1; 3868 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3869 ++I, ++Idx) { 3870 MVT::ValueType VT = getValueType(I->getType()); 3871 3872 switch (getTypeAction(VT)) { 3873 default: assert(0 && "Unknown type action!"); 3874 case Legal: 3875 Ops.push_back(SDOperand(Result, i++)); 3876 break; 3877 case Promote: { 3878 SDOperand Op(Result, i++); 3879 if (MVT::isInteger(VT)) { 3880 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3881 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3882 DAG.getValueType(VT)); 3883 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3884 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3885 DAG.getValueType(VT)); 3886 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3887 } else { 3888 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3889 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3890 } 3891 Ops.push_back(Op); 3892 break; 3893 } 3894 case Expand: { 3895 MVT::ValueType PartVT = getRegisterType(VT); 3896 unsigned NumParts = getNumRegisters(VT); 3897 SmallVector<SDOperand, 4> Parts(NumParts); 3898 for (unsigned j = 0; j != NumParts; ++j) 3899 Parts[j] = SDOperand(Result, i++); 3900 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, true)); 3901 break; 3902 } 3903 } 3904 } 3905 assert(i == NumArgRegs && "Argument register count mismatch!"); 3906 return Ops; 3907} 3908 3909 3910/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3911/// implementation, which just inserts an ISD::CALL node, which is later custom 3912/// lowered by the target to something concrete. FIXME: When all targets are 3913/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3914std::pair<SDOperand, SDOperand> 3915TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3916 bool RetTyIsSigned, bool isVarArg, 3917 unsigned CallingConv, bool isTailCall, 3918 SDOperand Callee, 3919 ArgListTy &Args, SelectionDAG &DAG) { 3920 SmallVector<SDOperand, 32> Ops; 3921 Ops.push_back(Chain); // Op#0 - Chain 3922 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3923 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3924 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3925 Ops.push_back(Callee); 3926 3927 // Handle all of the outgoing arguments. 3928 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3929 MVT::ValueType VT = getValueType(Args[i].Ty); 3930 SDOperand Op = Args[i].Node; 3931 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3932 unsigned OriginalAlignment = 3933 getTargetData()->getABITypeAlignment(Args[i].Ty); 3934 3935 if (Args[i].isSExt) 3936 Flags |= ISD::ParamFlags::SExt; 3937 if (Args[i].isZExt) 3938 Flags |= ISD::ParamFlags::ZExt; 3939 if (Args[i].isInReg) 3940 Flags |= ISD::ParamFlags::InReg; 3941 if (Args[i].isSRet) 3942 Flags |= ISD::ParamFlags::StructReturn; 3943 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3944 3945 switch (getTypeAction(VT)) { 3946 default: assert(0 && "Unknown type action!"); 3947 case Legal: 3948 Ops.push_back(Op); 3949 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3950 break; 3951 case Promote: 3952 if (MVT::isInteger(VT)) { 3953 unsigned ExtOp; 3954 if (Args[i].isSExt) 3955 ExtOp = ISD::SIGN_EXTEND; 3956 else if (Args[i].isZExt) 3957 ExtOp = ISD::ZERO_EXTEND; 3958 else 3959 ExtOp = ISD::ANY_EXTEND; 3960 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3961 } else { 3962 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3963 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 3964 } 3965 Ops.push_back(Op); 3966 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3967 break; 3968 case Expand: { 3969 MVT::ValueType PartVT = getRegisterType(VT); 3970 unsigned NumParts = getNumRegisters(VT); 3971 SmallVector<SDOperand, 4> Parts(NumParts); 3972 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, true); 3973 for (unsigned i = 0; i != NumParts; ++i) { 3974 // if it isn't first piece, alignment must be 1 3975 unsigned MyFlags = Flags; 3976 if (i != 0) 3977 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 3978 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3979 3980 Ops.push_back(Parts[i]); 3981 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 3982 } 3983 break; 3984 } 3985 } 3986 } 3987 3988 // Figure out the result value types. 3989 MVT::ValueType VT = getValueType(RetTy); 3990 MVT::ValueType RegisterVT = getRegisterType(VT); 3991 unsigned NumRegs = getNumRegisters(VT); 3992 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 3993 for (unsigned i = 0; i != NumRegs; ++i) 3994 RetTys[i] = RegisterVT; 3995 3996 RetTys.push_back(MVT::Other); // Always has a chain. 3997 3998 // Create the CALL node. 3999 SDOperand Res = DAG.getNode(ISD::CALL, 4000 DAG.getVTList(&RetTys[0], NumRegs + 1), 4001 &Ops[0], Ops.size()); 4002 SDOperand Chain = Res.getValue(NumRegs); 4003 4004 // Gather up the call result into a single value. 4005 if (RetTy != Type::VoidTy) { 4006 ISD::NodeType AssertOp = ISD::AssertSext; 4007 if (!RetTyIsSigned) 4008 AssertOp = ISD::AssertZext; 4009 SmallVector<SDOperand, 4> Results(NumRegs); 4010 for (unsigned i = 0; i != NumRegs; ++i) 4011 Results[i] = Res.getValue(i); 4012 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, false, AssertOp); 4013 } 4014 4015 return std::make_pair(Res, Chain); 4016} 4017 4018SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4019 assert(0 && "LowerOperation not implemented for this target!"); 4020 abort(); 4021 return SDOperand(); 4022} 4023 4024SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4025 SelectionDAG &DAG) { 4026 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4027 abort(); 4028 return SDOperand(); 4029} 4030 4031/// getMemsetValue - Vectorized representation of the memset value 4032/// operand. 4033static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4034 SelectionDAG &DAG) { 4035 MVT::ValueType CurVT = VT; 4036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4037 uint64_t Val = C->getValue() & 255; 4038 unsigned Shift = 8; 4039 while (CurVT != MVT::i8) { 4040 Val = (Val << Shift) | Val; 4041 Shift <<= 1; 4042 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4043 } 4044 return DAG.getConstant(Val, VT); 4045 } else { 4046 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4047 unsigned Shift = 8; 4048 while (CurVT != MVT::i8) { 4049 Value = 4050 DAG.getNode(ISD::OR, VT, 4051 DAG.getNode(ISD::SHL, VT, Value, 4052 DAG.getConstant(Shift, MVT::i8)), Value); 4053 Shift <<= 1; 4054 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4055 } 4056 4057 return Value; 4058 } 4059} 4060 4061/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4062/// used when a memcpy is turned into a memset when the source is a constant 4063/// string ptr. 4064static SDOperand getMemsetStringVal(MVT::ValueType VT, 4065 SelectionDAG &DAG, TargetLowering &TLI, 4066 std::string &Str, unsigned Offset) { 4067 uint64_t Val = 0; 4068 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4069 if (TLI.isLittleEndian()) 4070 Offset = Offset + MSB - 1; 4071 for (unsigned i = 0; i != MSB; ++i) { 4072 Val = (Val << 8) | (unsigned char)Str[Offset]; 4073 Offset += TLI.isLittleEndian() ? -1 : 1; 4074 } 4075 return DAG.getConstant(Val, VT); 4076} 4077 4078/// getMemBasePlusOffset - Returns base and offset node for the 4079static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4080 SelectionDAG &DAG, TargetLowering &TLI) { 4081 MVT::ValueType VT = Base.getValueType(); 4082 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4083} 4084 4085/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4086/// to replace the memset / memcpy is below the threshold. It also returns the 4087/// types of the sequence of memory ops to perform memset / memcpy. 4088static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4089 unsigned Limit, uint64_t Size, 4090 unsigned Align, TargetLowering &TLI) { 4091 MVT::ValueType VT; 4092 4093 if (TLI.allowsUnalignedMemoryAccesses()) { 4094 VT = MVT::i64; 4095 } else { 4096 switch (Align & 7) { 4097 case 0: 4098 VT = MVT::i64; 4099 break; 4100 case 4: 4101 VT = MVT::i32; 4102 break; 4103 case 2: 4104 VT = MVT::i16; 4105 break; 4106 default: 4107 VT = MVT::i8; 4108 break; 4109 } 4110 } 4111 4112 MVT::ValueType LVT = MVT::i64; 4113 while (!TLI.isTypeLegal(LVT)) 4114 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4115 assert(MVT::isInteger(LVT)); 4116 4117 if (VT > LVT) 4118 VT = LVT; 4119 4120 unsigned NumMemOps = 0; 4121 while (Size != 0) { 4122 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4123 while (VTSize > Size) { 4124 VT = (MVT::ValueType)((unsigned)VT - 1); 4125 VTSize >>= 1; 4126 } 4127 assert(MVT::isInteger(VT)); 4128 4129 if (++NumMemOps > Limit) 4130 return false; 4131 MemOps.push_back(VT); 4132 Size -= VTSize; 4133 } 4134 4135 return true; 4136} 4137 4138void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4139 SDOperand Op1 = getValue(I.getOperand(1)); 4140 SDOperand Op2 = getValue(I.getOperand(2)); 4141 SDOperand Op3 = getValue(I.getOperand(3)); 4142 SDOperand Op4 = getValue(I.getOperand(4)); 4143 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4144 if (Align == 0) Align = 1; 4145 4146 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4147 std::vector<MVT::ValueType> MemOps; 4148 4149 // Expand memset / memcpy to a series of load / store ops 4150 // if the size operand falls below a certain threshold. 4151 SmallVector<SDOperand, 8> OutChains; 4152 switch (Op) { 4153 default: break; // Do nothing for now. 4154 case ISD::MEMSET: { 4155 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4156 Size->getValue(), Align, TLI)) { 4157 unsigned NumMemOps = MemOps.size(); 4158 unsigned Offset = 0; 4159 for (unsigned i = 0; i < NumMemOps; i++) { 4160 MVT::ValueType VT = MemOps[i]; 4161 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4162 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4163 SDOperand Store = DAG.getStore(getRoot(), Value, 4164 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4165 I.getOperand(1), Offset); 4166 OutChains.push_back(Store); 4167 Offset += VTSize; 4168 } 4169 } 4170 break; 4171 } 4172 case ISD::MEMCPY: { 4173 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4174 Size->getValue(), Align, TLI)) { 4175 unsigned NumMemOps = MemOps.size(); 4176 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4177 GlobalAddressSDNode *G = NULL; 4178 std::string Str; 4179 bool CopyFromStr = false; 4180 4181 if (Op2.getOpcode() == ISD::GlobalAddress) 4182 G = cast<GlobalAddressSDNode>(Op2); 4183 else if (Op2.getOpcode() == ISD::ADD && 4184 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4185 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4186 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4187 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4188 } 4189 if (G) { 4190 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4191 if (GV && GV->isConstant()) { 4192 Str = GV->getStringValue(false); 4193 if (!Str.empty()) { 4194 CopyFromStr = true; 4195 SrcOff += SrcDelta; 4196 } 4197 } 4198 } 4199 4200 for (unsigned i = 0; i < NumMemOps; i++) { 4201 MVT::ValueType VT = MemOps[i]; 4202 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4203 SDOperand Value, Chain, Store; 4204 4205 if (CopyFromStr) { 4206 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4207 Chain = getRoot(); 4208 Store = 4209 DAG.getStore(Chain, Value, 4210 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4211 I.getOperand(1), DstOff); 4212 } else { 4213 Value = DAG.getLoad(VT, getRoot(), 4214 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4215 I.getOperand(2), SrcOff); 4216 Chain = Value.getValue(1); 4217 Store = 4218 DAG.getStore(Chain, Value, 4219 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4220 I.getOperand(1), DstOff); 4221 } 4222 OutChains.push_back(Store); 4223 SrcOff += VTSize; 4224 DstOff += VTSize; 4225 } 4226 } 4227 break; 4228 } 4229 } 4230 4231 if (!OutChains.empty()) { 4232 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4233 &OutChains[0], OutChains.size())); 4234 return; 4235 } 4236 } 4237 4238 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4239} 4240 4241//===----------------------------------------------------------------------===// 4242// SelectionDAGISel code 4243//===----------------------------------------------------------------------===// 4244 4245unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4246 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4247} 4248 4249void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4250 AU.addRequired<AliasAnalysis>(); 4251 AU.setPreservesAll(); 4252} 4253 4254 4255 4256bool SelectionDAGISel::runOnFunction(Function &Fn) { 4257 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4258 RegMap = MF.getSSARegMap(); 4259 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4260 4261 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4262 4263 if (ExceptionHandling) 4264 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4265 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4266 // Mark landing pad. 4267 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4268 4269 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4270 SelectBasicBlock(I, MF, FuncInfo); 4271 4272 // Add function live-ins to entry block live-in set. 4273 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4274 BB = FuncInfo.MBBMap[EntryBB]; 4275 if (!MF.livein_empty()) 4276 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4277 E = MF.livein_end(); I != E; ++I) 4278 BB->addLiveIn(I->first); 4279 4280#ifndef NDEBUG 4281 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4282 "Not all catch info was assigned to a landing pad!"); 4283#endif 4284 4285 return true; 4286} 4287 4288SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4289 unsigned Reg) { 4290 SDOperand Op = getValue(V); 4291 assert((Op.getOpcode() != ISD::CopyFromReg || 4292 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4293 "Copy from a reg to the same reg!"); 4294 4295 MVT::ValueType SrcVT = Op.getValueType(); 4296 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4297 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4298 SmallVector<SDOperand, 8> Regs(NumRegs); 4299 SmallVector<SDOperand, 8> Chains(NumRegs); 4300 4301 // Copy the value by legal parts into sequential virtual registers. 4302 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT, false); 4303 for (unsigned i = 0; i != NumRegs; ++i) 4304 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4305 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4306} 4307 4308void SelectionDAGISel:: 4309LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4310 std::vector<SDOperand> &UnorderedChains) { 4311 // If this is the entry block, emit arguments. 4312 Function &F = *LLVMBB->getParent(); 4313 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4314 SDOperand OldRoot = SDL.DAG.getRoot(); 4315 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4316 4317 unsigned a = 0; 4318 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4319 AI != E; ++AI, ++a) 4320 if (!AI->use_empty()) { 4321 SDL.setValue(AI, Args[a]); 4322 4323 // If this argument is live outside of the entry block, insert a copy from 4324 // whereever we got it to the vreg that other BB's will reference it as. 4325 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4326 if (VMI != FuncInfo.ValueMap.end()) { 4327 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4328 UnorderedChains.push_back(Copy); 4329 } 4330 } 4331 4332 // Finally, if the target has anything special to do, allow it to do so. 4333 // FIXME: this should insert code into the DAG! 4334 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4335} 4336 4337static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4338 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4339 assert(!FLI.MBBMap[SrcBB]->isLandingPad() && 4340 "Copying catch info out of a landing pad!"); 4341 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4342 if (isSelector(I)) { 4343 // Apply the catch info to DestBB. 4344 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4345#ifndef NDEBUG 4346 FLI.CatchInfoFound.insert(I); 4347#endif 4348 } 4349} 4350 4351void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4352 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4353 FunctionLoweringInfo &FuncInfo) { 4354 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4355 4356 std::vector<SDOperand> UnorderedChains; 4357 4358 // Lower any arguments needed in this block if this is the entry block. 4359 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4360 LowerArguments(LLVMBB, SDL, UnorderedChains); 4361 4362 BB = FuncInfo.MBBMap[LLVMBB]; 4363 SDL.setCurrentBasicBlock(BB); 4364 4365 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4366 4367 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4368 // Add a label to mark the beginning of the landing pad. Deletion of the 4369 // landing pad can thus be detected via the MachineModuleInfo. 4370 unsigned LabelID = MMI->addLandingPad(BB); 4371 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4372 DAG.getConstant(LabelID, MVT::i32))); 4373 4374 // Mark exception register as live in. 4375 unsigned Reg = TLI.getExceptionAddressRegister(); 4376 if (Reg) BB->addLiveIn(Reg); 4377 4378 // Mark exception selector register as live in. 4379 Reg = TLI.getExceptionSelectorRegister(); 4380 if (Reg) BB->addLiveIn(Reg); 4381 4382 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4383 // function and list of typeids logically belong to the invoke (or, if you 4384 // like, the basic block containing the invoke), and need to be associated 4385 // with it in the dwarf exception handling tables. Currently however the 4386 // information is provided by an intrinsic (eh.selector) that can be moved 4387 // to unexpected places by the optimizers: if the unwind edge is critical, 4388 // then breaking it can result in the intrinsics being in the successor of 4389 // the landing pad, not the landing pad itself. This results in exceptions 4390 // not being caught because no typeids are associated with the invoke. 4391 // This may not be the only way things can go wrong, but it is the only way 4392 // we try to work around for the moment. 4393 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4394 4395 if (Br && Br->isUnconditional()) { // Critical edge? 4396 BasicBlock::iterator I, E; 4397 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4398 if (isSelector(I)) 4399 break; 4400 4401 if (I == E) 4402 // No catch info found - try to extract some from the successor. 4403 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4404 } 4405 } 4406 4407 // Lower all of the non-terminator instructions. 4408 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4409 I != E; ++I) 4410 SDL.visit(*I); 4411 4412 // Ensure that all instructions which are used outside of their defining 4413 // blocks are available as virtual registers. Invoke is handled elsewhere. 4414 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4415 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4416 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4417 if (VMI != FuncInfo.ValueMap.end()) 4418 UnorderedChains.push_back( 4419 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4420 } 4421 4422 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4423 // ensure constants are generated when needed. Remember the virtual registers 4424 // that need to be added to the Machine PHI nodes as input. We cannot just 4425 // directly add them, because expansion might result in multiple MBB's for one 4426 // BB. As such, the start of the BB might correspond to a different MBB than 4427 // the end. 4428 // 4429 TerminatorInst *TI = LLVMBB->getTerminator(); 4430 4431 // Emit constants only once even if used by multiple PHI nodes. 4432 std::map<Constant*, unsigned> ConstantsOut; 4433 4434 // Vector bool would be better, but vector<bool> is really slow. 4435 std::vector<unsigned char> SuccsHandled; 4436 if (TI->getNumSuccessors()) 4437 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4438 4439 // Check successor nodes PHI nodes that expect a constant to be available from 4440 // this block. 4441 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4442 BasicBlock *SuccBB = TI->getSuccessor(succ); 4443 if (!isa<PHINode>(SuccBB->begin())) continue; 4444 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4445 4446 // If this terminator has multiple identical successors (common for 4447 // switches), only handle each succ once. 4448 unsigned SuccMBBNo = SuccMBB->getNumber(); 4449 if (SuccsHandled[SuccMBBNo]) continue; 4450 SuccsHandled[SuccMBBNo] = true; 4451 4452 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4453 PHINode *PN; 4454 4455 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4456 // nodes and Machine PHI nodes, but the incoming operands have not been 4457 // emitted yet. 4458 for (BasicBlock::iterator I = SuccBB->begin(); 4459 (PN = dyn_cast<PHINode>(I)); ++I) { 4460 // Ignore dead phi's. 4461 if (PN->use_empty()) continue; 4462 4463 unsigned Reg; 4464 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4465 4466 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4467 unsigned &RegOut = ConstantsOut[C]; 4468 if (RegOut == 0) { 4469 RegOut = FuncInfo.CreateRegForValue(C); 4470 UnorderedChains.push_back( 4471 SDL.CopyValueToVirtualRegister(C, RegOut)); 4472 } 4473 Reg = RegOut; 4474 } else { 4475 Reg = FuncInfo.ValueMap[PHIOp]; 4476 if (Reg == 0) { 4477 assert(isa<AllocaInst>(PHIOp) && 4478 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4479 "Didn't codegen value into a register!??"); 4480 Reg = FuncInfo.CreateRegForValue(PHIOp); 4481 UnorderedChains.push_back( 4482 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4483 } 4484 } 4485 4486 // Remember that this register needs to added to the machine PHI node as 4487 // the input for this MBB. 4488 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4489 unsigned NumRegisters = TLI.getNumRegisters(VT); 4490 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4491 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4492 } 4493 } 4494 ConstantsOut.clear(); 4495 4496 // Turn all of the unordered chains into one factored node. 4497 if (!UnorderedChains.empty()) { 4498 SDOperand Root = SDL.getRoot(); 4499 if (Root.getOpcode() != ISD::EntryToken) { 4500 unsigned i = 0, e = UnorderedChains.size(); 4501 for (; i != e; ++i) { 4502 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4503 if (UnorderedChains[i].Val->getOperand(0) == Root) 4504 break; // Don't add the root if we already indirectly depend on it. 4505 } 4506 4507 if (i == e) 4508 UnorderedChains.push_back(Root); 4509 } 4510 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4511 &UnorderedChains[0], UnorderedChains.size())); 4512 } 4513 4514 // Lower the terminator after the copies are emitted. 4515 SDL.visit(*LLVMBB->getTerminator()); 4516 4517 // Copy over any CaseBlock records that may now exist due to SwitchInst 4518 // lowering, as well as any jump table information. 4519 SwitchCases.clear(); 4520 SwitchCases = SDL.SwitchCases; 4521 JTCases.clear(); 4522 JTCases = SDL.JTCases; 4523 BitTestCases.clear(); 4524 BitTestCases = SDL.BitTestCases; 4525 4526 // Make sure the root of the DAG is up-to-date. 4527 DAG.setRoot(SDL.getRoot()); 4528} 4529 4530void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4531 // Get alias analysis for load/store combining. 4532 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4533 4534 // Run the DAG combiner in pre-legalize mode. 4535 DAG.Combine(false, AA); 4536 4537 DOUT << "Lowered selection DAG:\n"; 4538 DEBUG(DAG.dump()); 4539 4540 // Second step, hack on the DAG until it only uses operations and types that 4541 // the target supports. 4542 DAG.Legalize(); 4543 4544 DOUT << "Legalized selection DAG:\n"; 4545 DEBUG(DAG.dump()); 4546 4547 // Run the DAG combiner in post-legalize mode. 4548 DAG.Combine(true, AA); 4549 4550 if (ViewISelDAGs) DAG.viewGraph(); 4551 4552 // Third, instruction select all of the operations to machine code, adding the 4553 // code to the MachineBasicBlock. 4554 InstructionSelectBasicBlock(DAG); 4555 4556 DOUT << "Selected machine code:\n"; 4557 DEBUG(BB->dump()); 4558} 4559 4560void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4561 FunctionLoweringInfo &FuncInfo) { 4562 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4563 { 4564 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4565 CurDAG = &DAG; 4566 4567 // First step, lower LLVM code to some DAG. This DAG may use operations and 4568 // types that are not supported by the target. 4569 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4570 4571 // Second step, emit the lowered DAG as machine code. 4572 CodeGenAndEmitDAG(DAG); 4573 } 4574 4575 DOUT << "Total amount of phi nodes to update: " 4576 << PHINodesToUpdate.size() << "\n"; 4577 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4578 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4579 << ", " << PHINodesToUpdate[i].second << ")\n";); 4580 4581 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4582 // PHI nodes in successors. 4583 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4584 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4585 MachineInstr *PHI = PHINodesToUpdate[i].first; 4586 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4587 "This is not a machine PHI node that we are updating!"); 4588 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4589 PHI->addMachineBasicBlockOperand(BB); 4590 } 4591 return; 4592 } 4593 4594 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4595 // Lower header first, if it wasn't already lowered 4596 if (!BitTestCases[i].Emitted) { 4597 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4598 CurDAG = &HSDAG; 4599 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4600 // Set the current basic block to the mbb we wish to insert the code into 4601 BB = BitTestCases[i].Parent; 4602 HSDL.setCurrentBasicBlock(BB); 4603 // Emit the code 4604 HSDL.visitBitTestHeader(BitTestCases[i]); 4605 HSDAG.setRoot(HSDL.getRoot()); 4606 CodeGenAndEmitDAG(HSDAG); 4607 } 4608 4609 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4610 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4611 CurDAG = &BSDAG; 4612 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4613 // Set the current basic block to the mbb we wish to insert the code into 4614 BB = BitTestCases[i].Cases[j].ThisBB; 4615 BSDL.setCurrentBasicBlock(BB); 4616 // Emit the code 4617 if (j+1 != ej) 4618 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4619 BitTestCases[i].Reg, 4620 BitTestCases[i].Cases[j]); 4621 else 4622 BSDL.visitBitTestCase(BitTestCases[i].Default, 4623 BitTestCases[i].Reg, 4624 BitTestCases[i].Cases[j]); 4625 4626 4627 BSDAG.setRoot(BSDL.getRoot()); 4628 CodeGenAndEmitDAG(BSDAG); 4629 } 4630 4631 // Update PHI Nodes 4632 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4633 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4634 MachineBasicBlock *PHIBB = PHI->getParent(); 4635 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4636 "This is not a machine PHI node that we are updating!"); 4637 // This is "default" BB. We have two jumps to it. From "header" BB and 4638 // from last "case" BB. 4639 if (PHIBB == BitTestCases[i].Default) { 4640 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4641 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4642 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4643 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4644 } 4645 // One of "cases" BB. 4646 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4647 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4648 if (cBB->succ_end() != 4649 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4650 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4651 PHI->addMachineBasicBlockOperand(cBB); 4652 } 4653 } 4654 } 4655 } 4656 4657 // If the JumpTable record is filled in, then we need to emit a jump table. 4658 // Updating the PHI nodes is tricky in this case, since we need to determine 4659 // whether the PHI is a successor of the range check MBB or the jump table MBB 4660 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4661 // Lower header first, if it wasn't already lowered 4662 if (!JTCases[i].first.Emitted) { 4663 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4664 CurDAG = &HSDAG; 4665 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4666 // Set the current basic block to the mbb we wish to insert the code into 4667 BB = JTCases[i].first.HeaderBB; 4668 HSDL.setCurrentBasicBlock(BB); 4669 // Emit the code 4670 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4671 HSDAG.setRoot(HSDL.getRoot()); 4672 CodeGenAndEmitDAG(HSDAG); 4673 } 4674 4675 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4676 CurDAG = &JSDAG; 4677 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4678 // Set the current basic block to the mbb we wish to insert the code into 4679 BB = JTCases[i].second.MBB; 4680 JSDL.setCurrentBasicBlock(BB); 4681 // Emit the code 4682 JSDL.visitJumpTable(JTCases[i].second); 4683 JSDAG.setRoot(JSDL.getRoot()); 4684 CodeGenAndEmitDAG(JSDAG); 4685 4686 // Update PHI Nodes 4687 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4688 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4689 MachineBasicBlock *PHIBB = PHI->getParent(); 4690 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4691 "This is not a machine PHI node that we are updating!"); 4692 // "default" BB. We can go there only from header BB. 4693 if (PHIBB == JTCases[i].second.Default) { 4694 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4695 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4696 } 4697 // JT BB. Just iterate over successors here 4698 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4699 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4700 PHI->addMachineBasicBlockOperand(BB); 4701 } 4702 } 4703 } 4704 4705 // If the switch block involved a branch to one of the actual successors, we 4706 // need to update PHI nodes in that block. 4707 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4708 MachineInstr *PHI = PHINodesToUpdate[i].first; 4709 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4710 "This is not a machine PHI node that we are updating!"); 4711 if (BB->isSuccessor(PHI->getParent())) { 4712 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4713 PHI->addMachineBasicBlockOperand(BB); 4714 } 4715 } 4716 4717 // If we generated any switch lowering information, build and codegen any 4718 // additional DAGs necessary. 4719 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4720 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4721 CurDAG = &SDAG; 4722 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4723 4724 // Set the current basic block to the mbb we wish to insert the code into 4725 BB = SwitchCases[i].ThisBB; 4726 SDL.setCurrentBasicBlock(BB); 4727 4728 // Emit the code 4729 SDL.visitSwitchCase(SwitchCases[i]); 4730 SDAG.setRoot(SDL.getRoot()); 4731 CodeGenAndEmitDAG(SDAG); 4732 4733 // Handle any PHI nodes in successors of this chunk, as if we were coming 4734 // from the original BB before switch expansion. Note that PHI nodes can 4735 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4736 // handle them the right number of times. 4737 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4738 for (MachineBasicBlock::iterator Phi = BB->begin(); 4739 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4740 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4741 for (unsigned pn = 0; ; ++pn) { 4742 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4743 if (PHINodesToUpdate[pn].first == Phi) { 4744 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4745 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4746 break; 4747 } 4748 } 4749 } 4750 4751 // Don't process RHS if same block as LHS. 4752 if (BB == SwitchCases[i].FalseBB) 4753 SwitchCases[i].FalseBB = 0; 4754 4755 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4756 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4757 SwitchCases[i].FalseBB = 0; 4758 } 4759 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4760 } 4761} 4762 4763 4764//===----------------------------------------------------------------------===// 4765/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4766/// target node in the graph. 4767void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4768 if (ViewSchedDAGs) DAG.viewGraph(); 4769 4770 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4771 4772 if (!Ctor) { 4773 Ctor = ISHeuristic; 4774 RegisterScheduler::setDefault(Ctor); 4775 } 4776 4777 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4778 BB = SL->Run(); 4779 delete SL; 4780} 4781 4782 4783HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4784 return new HazardRecognizer(); 4785} 4786 4787//===----------------------------------------------------------------------===// 4788// Helper functions used by the generated instruction selector. 4789//===----------------------------------------------------------------------===// 4790// Calls to these methods are generated by tblgen. 4791 4792/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4793/// the dag combiner simplified the 255, we still want to match. RHS is the 4794/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4795/// specified in the .td file (e.g. 255). 4796bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4797 int64_t DesiredMaskS) { 4798 uint64_t ActualMask = RHS->getValue(); 4799 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4800 4801 // If the actual mask exactly matches, success! 4802 if (ActualMask == DesiredMask) 4803 return true; 4804 4805 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4806 if (ActualMask & ~DesiredMask) 4807 return false; 4808 4809 // Otherwise, the DAG Combiner may have proven that the value coming in is 4810 // either already zero or is not demanded. Check for known zero input bits. 4811 uint64_t NeededMask = DesiredMask & ~ActualMask; 4812 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 4813 return true; 4814 4815 // TODO: check to see if missing bits are just not demanded. 4816 4817 // Otherwise, this pattern doesn't match. 4818 return false; 4819} 4820 4821/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4822/// the dag combiner simplified the 255, we still want to match. RHS is the 4823/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4824/// specified in the .td file (e.g. 255). 4825bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4826 int64_t DesiredMaskS) { 4827 uint64_t ActualMask = RHS->getValue(); 4828 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4829 4830 // If the actual mask exactly matches, success! 4831 if (ActualMask == DesiredMask) 4832 return true; 4833 4834 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4835 if (ActualMask & ~DesiredMask) 4836 return false; 4837 4838 // Otherwise, the DAG Combiner may have proven that the value coming in is 4839 // either already zero or is not demanded. Check for known zero input bits. 4840 uint64_t NeededMask = DesiredMask & ~ActualMask; 4841 4842 uint64_t KnownZero, KnownOne; 4843 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4844 4845 // If all the missing bits in the or are already known to be set, match! 4846 if ((NeededMask & KnownOne) == NeededMask) 4847 return true; 4848 4849 // TODO: check to see if missing bits are just not demanded. 4850 4851 // Otherwise, this pattern doesn't match. 4852 return false; 4853} 4854 4855 4856/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4857/// by tblgen. Others should not call it. 4858void SelectionDAGISel:: 4859SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4860 std::vector<SDOperand> InOps; 4861 std::swap(InOps, Ops); 4862 4863 Ops.push_back(InOps[0]); // input chain. 4864 Ops.push_back(InOps[1]); // input asm string. 4865 4866 unsigned i = 2, e = InOps.size(); 4867 if (InOps[e-1].getValueType() == MVT::Flag) 4868 --e; // Don't process a flag operand if it is here. 4869 4870 while (i != e) { 4871 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4872 if ((Flags & 7) != 4 /*MEM*/) { 4873 // Just skip over this operand, copying the operands verbatim. 4874 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4875 i += (Flags >> 3) + 1; 4876 } else { 4877 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4878 // Otherwise, this is a memory operand. Ask the target to select it. 4879 std::vector<SDOperand> SelOps; 4880 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4881 cerr << "Could not match memory address. Inline asm failure!\n"; 4882 exit(1); 4883 } 4884 4885 // Add this to the output node. 4886 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4887 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4888 IntPtrTy)); 4889 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4890 i += 2; 4891 } 4892 } 4893 4894 // Add the flag input back if present. 4895 if (e != InOps.size()) 4896 Ops.push_back(InOps.back()); 4897} 4898 4899char SelectionDAGISel::ID = 0; 4900