SelectionDAGISel.cpp revision 8927a372950be8591f298fb9650b2059e0f0a6e8
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183unsigned SelectionDAGISel::MakeReg(EVT VT) { 184 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 196 // Do some sanity-checking on the command-line options. 197 assert((!EnableFastISelVerbose || EnableFastISel) && 198 "-fast-isel-verbose requires -fast-isel"); 199 assert((!EnableFastISelAbort || EnableFastISel) && 200 "-fast-isel-abort requires -fast-isel"); 201 202 Function &Fn = *mf.getFunction(); 203 const TargetInstrInfo &TII = *TM.getInstrInfo(); 204 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 205 206 MF = &mf; 207 RegInfo = &MF->getRegInfo(); 208 AA = &getAnalysis<AliasAnalysis>(); 209 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 210 211 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 212 213 CurDAG->init(*MF); 214 FuncInfo->set(Fn, *MF, EnableFastISel); 215 SDB->init(GFI, *AA); 216 217 SelectAllBasicBlocks(Fn, *MF, TII); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224 // Add function live-ins to entry block live-in set. 225 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 226 E = RegInfo->livein_end(); I != E; ++I) 227 MF->begin()->addLiveIn(I->first); 228 229#ifndef NDEBUG 230 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 231 "Not all catch info was assigned to a landing pad!"); 232#endif 233 234 FuncInfo->clear(); 235 236 return true; 237} 238 239/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 240/// attached with this instruction. 241static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB, 242 FastISel *FastIS, MachineFunction *MF) { 243 DebugLoc DL = I->getDebugLoc(); 244 if (DL.isUnknown()) return; 245 246 SDB->setCurDebugLoc(DL); 247 248 if (FastIS) 249 FastIS->setCurDebugLoc(DL); 250 251 // If the function doesn't have a default debug location yet, set 252 // it. This is kind of a hack. 253 if (MF->getDefaultDebugLoc().isUnknown()) 254 MF->setDefaultDebugLoc(DL); 255} 256 257/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 258static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 259 SDB->setCurDebugLoc(DebugLoc()); 260 if (FastIS) 261 FastIS->setCurDebugLoc(DebugLoc()); 262} 263 264void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 265 BasicBlock::iterator Begin, 266 BasicBlock::iterator End, 267 bool &HadTailCall) { 268 SDB->setCurrentBasicBlock(BB); 269 270 // Lower all of the non-terminator instructions. If a call is emitted 271 // as a tail call, cease emitting nodes for this block. 272 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 273 SetDebugLoc(I, SDB, 0, MF); 274 275 if (!isa<TerminatorInst>(I)) { 276 SDB->visit(*I); 277 278 // Set the current debug location back to "unknown" so that it doesn't 279 // spuriously apply to subsequent instructions. 280 ResetDebugLoc(SDB, 0); 281 } 282 } 283 284 if (!SDB->HasTailCall) { 285 // Ensure that all instructions which are used outside of their defining 286 // blocks are available as virtual registers. Invoke is handled elsewhere. 287 for (BasicBlock::iterator I = Begin; I != End; ++I) 288 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 289 SDB->CopyToExportRegsIfNeeded(I); 290 291 // Handle PHI nodes in successor blocks. 292 if (End == LLVMBB->end()) { 293 HandlePHINodesInSuccessorBlocks(LLVMBB); 294 295 // Lower the terminator after the copies are emitted. 296 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 297 SDB->visit(*LLVMBB->getTerminator()); 298 ResetDebugLoc(SDB, 0); 299 } 300 } 301 302 // Make sure the root of the DAG is up-to-date. 303 CurDAG->setRoot(SDB->getControlRoot()); 304 305 // Final step, emit the lowered DAG as machine code. 306 CodeGenAndEmitDAG(); 307 HadTailCall = SDB->HasTailCall; 308 SDB->clear(); 309} 310 311namespace { 312/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 313/// nodes from the worklist. 314class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 315 SmallVector<SDNode*, 128> &Worklist; 316 SmallPtrSet<SDNode*, 128> &InWorklist; 317public: 318 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 319 SmallPtrSet<SDNode*, 128> &inwl) 320 : Worklist(wl), InWorklist(inwl) {} 321 322 void RemoveFromWorklist(SDNode *N) { 323 if (!InWorklist.erase(N)) return; 324 325 SmallVector<SDNode*, 128>::iterator I = 326 std::find(Worklist.begin(), Worklist.end(), N); 327 assert(I != Worklist.end() && "Not in worklist"); 328 329 *I = Worklist.back(); 330 Worklist.pop_back(); 331 } 332 333 virtual void NodeDeleted(SDNode *N, SDNode *E) { 334 RemoveFromWorklist(N); 335 } 336 337 virtual void NodeUpdated(SDNode *N) { 338 // Ignore updates. 339 } 340}; 341} 342 343/// TrivialTruncElim - Eliminate some trivial nops that can result from 344/// ShrinkDemandedOps: (trunc (ext n)) -> n. 345static bool TrivialTruncElim(SDValue Op, 346 TargetLowering::TargetLoweringOpt &TLO) { 347 SDValue N0 = Op.getOperand(0); 348 EVT VT = Op.getValueType(); 349 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 350 N0.getOpcode() == ISD::SIGN_EXTEND || 351 N0.getOpcode() == ISD::ANY_EXTEND) && 352 N0.getOperand(0).getValueType() == VT) { 353 return TLO.CombineTo(Op, N0.getOperand(0)); 354 } 355 return false; 356} 357 358/// ShrinkDemandedOps - A late transformation pass that shrink expressions 359/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 360/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 361void SelectionDAGISel::ShrinkDemandedOps() { 362 SmallVector<SDNode*, 128> Worklist; 363 SmallPtrSet<SDNode*, 128> InWorklist; 364 365 // Add all the dag nodes to the worklist. 366 Worklist.reserve(CurDAG->allnodes_size()); 367 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 368 E = CurDAG->allnodes_end(); I != E; ++I) { 369 Worklist.push_back(I); 370 InWorklist.insert(I); 371 } 372 373 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 374 while (!Worklist.empty()) { 375 SDNode *N = Worklist.pop_back_val(); 376 InWorklist.erase(N); 377 378 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 379 // Deleting this node may make its operands dead, add them to the worklist 380 // if they aren't already there. 381 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 382 if (InWorklist.insert(N->getOperand(i).getNode())) 383 Worklist.push_back(N->getOperand(i).getNode()); 384 385 CurDAG->DeleteNode(N); 386 continue; 387 } 388 389 // Run ShrinkDemandedOp on scalar binary operations. 390 if (N->getNumValues() != 1 || 391 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 392 continue; 393 394 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 395 APInt Demanded = APInt::getAllOnesValue(BitWidth); 396 APInt KnownZero, KnownOne; 397 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 398 KnownZero, KnownOne, TLO) && 399 (N->getOpcode() != ISD::TRUNCATE || 400 !TrivialTruncElim(SDValue(N, 0), TLO))) 401 continue; 402 403 // Revisit the node. 404 assert(!InWorklist.count(N) && "Already in worklist"); 405 Worklist.push_back(N); 406 InWorklist.insert(N); 407 408 // Replace the old value with the new one. 409 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 410 TLO.Old.getNode()->dump(CurDAG); 411 errs() << "\nWith: "; 412 TLO.New.getNode()->dump(CurDAG); 413 errs() << '\n'); 414 415 if (InWorklist.insert(TLO.New.getNode())) 416 Worklist.push_back(TLO.New.getNode()); 417 418 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 419 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 420 421 if (!TLO.Old.getNode()->use_empty()) continue; 422 423 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 424 i != e; ++i) { 425 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 426 if (OpNode->hasOneUse()) { 427 // Add OpNode to the end of the list to revisit. 428 DeadNodes.RemoveFromWorklist(OpNode); 429 Worklist.push_back(OpNode); 430 InWorklist.insert(OpNode); 431 } 432 } 433 434 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 435 CurDAG->DeleteNode(TLO.Old.getNode()); 436 } 437} 438 439void SelectionDAGISel::ComputeLiveOutVRegInfo() { 440 SmallPtrSet<SDNode*, 128> VisitedNodes; 441 SmallVector<SDNode*, 128> Worklist; 442 443 Worklist.push_back(CurDAG->getRoot().getNode()); 444 445 APInt Mask; 446 APInt KnownZero; 447 APInt KnownOne; 448 449 do { 450 SDNode *N = Worklist.pop_back_val(); 451 452 // If we've already seen this node, ignore it. 453 if (!VisitedNodes.insert(N)) 454 continue; 455 456 // Otherwise, add all chain operands to the worklist. 457 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 458 if (N->getOperand(i).getValueType() == MVT::Other) 459 Worklist.push_back(N->getOperand(i).getNode()); 460 461 // If this is a CopyToReg with a vreg dest, process it. 462 if (N->getOpcode() != ISD::CopyToReg) 463 continue; 464 465 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 466 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 467 continue; 468 469 // Ignore non-scalar or non-integer values. 470 SDValue Src = N->getOperand(2); 471 EVT SrcVT = Src.getValueType(); 472 if (!SrcVT.isInteger() || SrcVT.isVector()) 473 continue; 474 475 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 476 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 477 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 478 479 // Only install this information if it tells us something. 480 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 481 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 482 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 483 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 484 FunctionLoweringInfo::LiveOutInfo &LOI = 485 FuncInfo->LiveOutRegInfo[DestReg]; 486 LOI.NumSignBits = NumSignBits; 487 LOI.KnownOne = KnownOne; 488 LOI.KnownZero = KnownZero; 489 } 490 } while (!Worklist.empty()); 491} 492 493void SelectionDAGISel::CodeGenAndEmitDAG() { 494 std::string GroupName; 495 if (TimePassesIsEnabled) 496 GroupName = "Instruction Selection and Scheduling"; 497 std::string BlockName; 498 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 499 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 500 ViewSUnitDAGs) 501 BlockName = MF->getFunction()->getNameStr() + ":" + 502 BB->getBasicBlock()->getNameStr(); 503 504 DEBUG(dbgs() << "Initial selection DAG:\n"); 505 DEBUG(CurDAG->dump()); 506 507 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 508 509 // Run the DAG combiner in pre-legalize mode. 510 if (TimePassesIsEnabled) { 511 NamedRegionTimer T("DAG Combining 1", GroupName); 512 CurDAG->Combine(Unrestricted, *AA, OptLevel); 513 } else { 514 CurDAG->Combine(Unrestricted, *AA, OptLevel); 515 } 516 517 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 518 DEBUG(CurDAG->dump()); 519 520 // Second step, hack on the DAG until it only uses operations and types that 521 // the target supports. 522 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 523 BlockName); 524 525 bool Changed; 526 if (TimePassesIsEnabled) { 527 NamedRegionTimer T("Type Legalization", GroupName); 528 Changed = CurDAG->LegalizeTypes(); 529 } else { 530 Changed = CurDAG->LegalizeTypes(); 531 } 532 533 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 534 DEBUG(CurDAG->dump()); 535 536 if (Changed) { 537 if (ViewDAGCombineLT) 538 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 539 540 // Run the DAG combiner in post-type-legalize mode. 541 if (TimePassesIsEnabled) { 542 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 543 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 544 } else { 545 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 546 } 547 548 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 549 DEBUG(CurDAG->dump()); 550 } 551 552 if (TimePassesIsEnabled) { 553 NamedRegionTimer T("Vector Legalization", GroupName); 554 Changed = CurDAG->LegalizeVectors(); 555 } else { 556 Changed = CurDAG->LegalizeVectors(); 557 } 558 559 if (Changed) { 560 if (TimePassesIsEnabled) { 561 NamedRegionTimer T("Type Legalization 2", GroupName); 562 CurDAG->LegalizeTypes(); 563 } else { 564 CurDAG->LegalizeTypes(); 565 } 566 567 if (ViewDAGCombineLT) 568 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 569 570 // Run the DAG combiner in post-type-legalize mode. 571 if (TimePassesIsEnabled) { 572 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 573 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 574 } else { 575 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 576 } 577 578 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 579 DEBUG(CurDAG->dump()); 580 } 581 582 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 583 584 if (TimePassesIsEnabled) { 585 NamedRegionTimer T("DAG Legalization", GroupName); 586 CurDAG->Legalize(OptLevel); 587 } else { 588 CurDAG->Legalize(OptLevel); 589 } 590 591 DEBUG(dbgs() << "Legalized selection DAG:\n"); 592 DEBUG(CurDAG->dump()); 593 594 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 595 596 // Run the DAG combiner in post-legalize mode. 597 if (TimePassesIsEnabled) { 598 NamedRegionTimer T("DAG Combining 2", GroupName); 599 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 600 } else { 601 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 602 } 603 604 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 605 DEBUG(CurDAG->dump()); 606 607 if (OptLevel != CodeGenOpt::None) { 608 ShrinkDemandedOps(); 609 ComputeLiveOutVRegInfo(); 610 } 611 612 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 613 614 // Third, instruction select all of the operations to machine code, adding the 615 // code to the MachineBasicBlock. 616 if (TimePassesIsEnabled) { 617 NamedRegionTimer T("Instruction Selection", GroupName); 618 DoInstructionSelection(); 619 } else { 620 DoInstructionSelection(); 621 } 622 623 DEBUG(dbgs() << "Selected selection DAG:\n"); 624 DEBUG(CurDAG->dump()); 625 626 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 627 628 // Schedule machine code. 629 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 630 if (TimePassesIsEnabled) { 631 NamedRegionTimer T("Instruction Scheduling", GroupName); 632 Scheduler->Run(CurDAG, BB, BB->end()); 633 } else { 634 Scheduler->Run(CurDAG, BB, BB->end()); 635 } 636 637 if (ViewSUnitDAGs) Scheduler->viewGraph(); 638 639 // Emit machine code to BB. This can change 'BB' to the last block being 640 // inserted into. 641 if (TimePassesIsEnabled) { 642 NamedRegionTimer T("Instruction Creation", GroupName); 643 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 644 } else { 645 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 646 } 647 648 // Free the scheduler state. 649 if (TimePassesIsEnabled) { 650 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 651 delete Scheduler; 652 } else { 653 delete Scheduler; 654 } 655 656 DEBUG(dbgs() << "Selected machine code:\n"); 657 DEBUG(BB->dump()); 658} 659 660void SelectionDAGISel::DoInstructionSelection() { 661 DEBUG(errs() << "===== Instruction selection begins:\n"); 662 663 PreprocessISelDAG(); 664 665 // Select target instructions for the DAG. 666 { 667 // Number all nodes with a topological order and set DAGSize. 668 DAGSize = CurDAG->AssignTopologicalOrder(); 669 670 // Create a dummy node (which is not added to allnodes), that adds 671 // a reference to the root node, preventing it from being deleted, 672 // and tracking any changes of the root. 673 HandleSDNode Dummy(CurDAG->getRoot()); 674 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 675 ++ISelPosition; 676 677 // The AllNodes list is now topological-sorted. Visit the 678 // nodes by starting at the end of the list (the root of the 679 // graph) and preceding back toward the beginning (the entry 680 // node). 681 while (ISelPosition != CurDAG->allnodes_begin()) { 682 SDNode *Node = --ISelPosition; 683 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 684 // but there are currently some corner cases that it misses. Also, this 685 // makes it theoretically possible to disable the DAGCombiner. 686 if (Node->use_empty()) 687 continue; 688 689 SDNode *ResNode = Select(Node); 690 691 // FIXME: This is pretty gross. 'Select' should be changed to not return 692 // anything at all and this code should be nuked with a tactical strike. 693 694 // If node should not be replaced, continue with the next one. 695 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 696 continue; 697 // Replace node. 698 if (ResNode) 699 ReplaceUses(Node, ResNode); 700 701 // If after the replacement this node is not used any more, 702 // remove this dead node. 703 if (Node->use_empty()) { // Don't delete EntryToken, etc. 704 ISelUpdater ISU(ISelPosition); 705 CurDAG->RemoveDeadNode(Node, &ISU); 706 } 707 } 708 709 CurDAG->setRoot(Dummy.getValue()); 710 } 711 DEBUG(errs() << "===== Instruction selection ends:\n"); 712 713 PostprocessISelDAG(); 714} 715 716 717void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 718 MachineFunction &MF, 719 const TargetInstrInfo &TII) { 720 // Initialize the Fast-ISel state, if needed. 721 FastISel *FastIS = 0; 722 if (EnableFastISel) 723 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 724 FuncInfo->StaticAllocaMap 725#ifndef NDEBUG 726 , FuncInfo->CatchInfoLost 727#endif 728 ); 729 730 // Iterate over all basic blocks in the function. 731 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 732 BasicBlock *LLVMBB = &*I; 733 BB = FuncInfo->MBBMap[LLVMBB]; 734 735 BasicBlock::iterator const Begin = LLVMBB->begin(); 736 BasicBlock::iterator const End = LLVMBB->end(); 737 BasicBlock::iterator BI = Begin; 738 739 // Lower any arguments needed in this block if this is the entry block. 740 bool SuppressFastISel = false; 741 if (LLVMBB == &Fn.getEntryBlock()) { 742 LowerArguments(LLVMBB); 743 744 // If any of the arguments has the byval attribute, forgo 745 // fast-isel in the entry block. 746 if (FastIS) { 747 unsigned j = 1; 748 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 749 I != E; ++I, ++j) 750 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 751 if (EnableFastISelVerbose || EnableFastISelAbort) 752 dbgs() << "FastISel skips entry block due to byval argument\n"; 753 SuppressFastISel = true; 754 break; 755 } 756 } 757 } 758 759 if (BB->isLandingPad()) { 760 // Add a label to mark the beginning of the landing pad. Deletion of the 761 // landing pad can thus be detected via the MachineModuleInfo. 762 MCSymbol *Label = MF.getMMI().addLandingPad(BB); 763 764 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 765 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 766 767 // Mark exception register as live in. 768 unsigned Reg = TLI.getExceptionAddressRegister(); 769 if (Reg) BB->addLiveIn(Reg); 770 771 // Mark exception selector register as live in. 772 Reg = TLI.getExceptionSelectorRegister(); 773 if (Reg) BB->addLiveIn(Reg); 774 775 // FIXME: Hack around an exception handling flaw (PR1508): the personality 776 // function and list of typeids logically belong to the invoke (or, if you 777 // like, the basic block containing the invoke), and need to be associated 778 // with it in the dwarf exception handling tables. Currently however the 779 // information is provided by an intrinsic (eh.selector) that can be moved 780 // to unexpected places by the optimizers: if the unwind edge is critical, 781 // then breaking it can result in the intrinsics being in the successor of 782 // the landing pad, not the landing pad itself. This results 783 // in exceptions not being caught because no typeids are associated with 784 // the invoke. This may not be the only way things can go wrong, but it 785 // is the only way we try to work around for the moment. 786 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 787 788 if (Br && Br->isUnconditional()) { // Critical edge? 789 BasicBlock::iterator I, E; 790 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 791 if (isa<EHSelectorInst>(I)) 792 break; 793 794 if (I == E) 795 // No catch info found - try to extract some from the successor. 796 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo); 797 } 798 } 799 800 // Before doing SelectionDAG ISel, see if FastISel has been requested. 801 if (FastIS && !SuppressFastISel) { 802 // Emit code for any incoming arguments. This must happen before 803 // beginning FastISel on the entry block. 804 if (LLVMBB == &Fn.getEntryBlock()) { 805 CurDAG->setRoot(SDB->getControlRoot()); 806 CodeGenAndEmitDAG(); 807 SDB->clear(); 808 } 809 FastIS->startNewBlock(BB); 810 // Do FastISel on as many instructions as possible. 811 for (; BI != End; ++BI) { 812 // Just before the terminator instruction, insert instructions to 813 // feed PHI nodes in successor blocks. 814 if (isa<TerminatorInst>(BI)) 815 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 816 ++NumFastIselFailures; 817 ResetDebugLoc(SDB, FastIS); 818 if (EnableFastISelVerbose || EnableFastISelAbort) { 819 dbgs() << "FastISel miss: "; 820 BI->dump(); 821 } 822 assert(!EnableFastISelAbort && 823 "FastISel didn't handle a PHI in a successor"); 824 break; 825 } 826 827 SetDebugLoc(BI, SDB, FastIS, &MF); 828 829 // Try to select the instruction with FastISel. 830 if (FastIS->SelectInstruction(BI)) { 831 ResetDebugLoc(SDB, FastIS); 832 continue; 833 } 834 835 // Clear out the debug location so that it doesn't carry over to 836 // unrelated instructions. 837 ResetDebugLoc(SDB, FastIS); 838 839 // Then handle certain instructions as single-LLVM-Instruction blocks. 840 if (isa<CallInst>(BI)) { 841 ++NumFastIselFailures; 842 if (EnableFastISelVerbose || EnableFastISelAbort) { 843 dbgs() << "FastISel missed call: "; 844 BI->dump(); 845 } 846 847 if (!BI->getType()->isVoidTy()) { 848 unsigned &R = FuncInfo->ValueMap[BI]; 849 if (!R) 850 R = FuncInfo->CreateRegForValue(BI); 851 } 852 853 bool HadTailCall = false; 854 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 855 856 // If the call was emitted as a tail call, we're done with the block. 857 if (HadTailCall) { 858 BI = End; 859 break; 860 } 861 862 // If the instruction was codegen'd with multiple blocks, 863 // inform the FastISel object where to resume inserting. 864 FastIS->setCurrentBlock(BB); 865 continue; 866 } 867 868 // Otherwise, give up on FastISel for the rest of the block. 869 // For now, be a little lenient about non-branch terminators. 870 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 871 ++NumFastIselFailures; 872 if (EnableFastISelVerbose || EnableFastISelAbort) { 873 dbgs() << "FastISel miss: "; 874 BI->dump(); 875 } 876 if (EnableFastISelAbort) 877 // The "fast" selector couldn't handle something and bailed. 878 // For the purpose of debugging, just abort. 879 llvm_unreachable("FastISel didn't select the entire block"); 880 } 881 break; 882 } 883 } 884 885 // Run SelectionDAG instruction selection on the remainder of the block 886 // not handled by FastISel. If FastISel is not run, this is the entire 887 // block. 888 if (BI != End) { 889 bool HadTailCall; 890 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 891 } 892 893 FinishBasicBlock(); 894 } 895 896 delete FastIS; 897} 898 899void 900SelectionDAGISel::FinishBasicBlock() { 901 902 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 903 DEBUG(BB->dump()); 904 905 DEBUG(dbgs() << "Total amount of phi nodes to update: " 906 << SDB->PHINodesToUpdate.size() << "\n"); 907 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 908 dbgs() << "Node " << i << " : (" 909 << SDB->PHINodesToUpdate[i].first 910 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 911 912 // Next, now that we know what the last MBB the LLVM BB expanded is, update 913 // PHI nodes in successors. 914 if (SDB->SwitchCases.empty() && 915 SDB->JTCases.empty() && 916 SDB->BitTestCases.empty()) { 917 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 918 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 919 assert(PHI->isPHI() && 920 "This is not a machine PHI node that we are updating!"); 921 if (!BB->isSuccessor(PHI->getParent())) 922 continue; 923 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 924 false)); 925 PHI->addOperand(MachineOperand::CreateMBB(BB)); 926 } 927 SDB->PHINodesToUpdate.clear(); 928 return; 929 } 930 931 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 932 // Lower header first, if it wasn't already lowered 933 if (!SDB->BitTestCases[i].Emitted) { 934 // Set the current basic block to the mbb we wish to insert the code into 935 BB = SDB->BitTestCases[i].Parent; 936 SDB->setCurrentBasicBlock(BB); 937 // Emit the code 938 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 939 CurDAG->setRoot(SDB->getRoot()); 940 CodeGenAndEmitDAG(); 941 SDB->clear(); 942 } 943 944 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 945 // Set the current basic block to the mbb we wish to insert the code into 946 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 947 SDB->setCurrentBasicBlock(BB); 948 // Emit the code 949 if (j+1 != ej) 950 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 951 SDB->BitTestCases[i].Reg, 952 SDB->BitTestCases[i].Cases[j]); 953 else 954 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 955 SDB->BitTestCases[i].Reg, 956 SDB->BitTestCases[i].Cases[j]); 957 958 959 CurDAG->setRoot(SDB->getRoot()); 960 CodeGenAndEmitDAG(); 961 SDB->clear(); 962 } 963 964 // Update PHI Nodes 965 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 966 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 967 MachineBasicBlock *PHIBB = PHI->getParent(); 968 assert(PHI->isPHI() && 969 "This is not a machine PHI node that we are updating!"); 970 // This is "default" BB. We have two jumps to it. From "header" BB and 971 // from last "case" BB. 972 if (PHIBB == SDB->BitTestCases[i].Default) { 973 PHI->addOperand(MachineOperand:: 974 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 975 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 976 PHI->addOperand(MachineOperand:: 977 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 978 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 979 back().ThisBB)); 980 } 981 // One of "cases" BB. 982 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 983 j != ej; ++j) { 984 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 985 if (cBB->isSuccessor(PHIBB)) { 986 PHI->addOperand(MachineOperand:: 987 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 988 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 989 } 990 } 991 } 992 } 993 SDB->BitTestCases.clear(); 994 995 // If the JumpTable record is filled in, then we need to emit a jump table. 996 // Updating the PHI nodes is tricky in this case, since we need to determine 997 // whether the PHI is a successor of the range check MBB or the jump table MBB 998 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 999 // Lower header first, if it wasn't already lowered 1000 if (!SDB->JTCases[i].first.Emitted) { 1001 // Set the current basic block to the mbb we wish to insert the code into 1002 BB = SDB->JTCases[i].first.HeaderBB; 1003 SDB->setCurrentBasicBlock(BB); 1004 // Emit the code 1005 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1006 CurDAG->setRoot(SDB->getRoot()); 1007 CodeGenAndEmitDAG(); 1008 SDB->clear(); 1009 } 1010 1011 // Set the current basic block to the mbb we wish to insert the code into 1012 BB = SDB->JTCases[i].second.MBB; 1013 SDB->setCurrentBasicBlock(BB); 1014 // Emit the code 1015 SDB->visitJumpTable(SDB->JTCases[i].second); 1016 CurDAG->setRoot(SDB->getRoot()); 1017 CodeGenAndEmitDAG(); 1018 SDB->clear(); 1019 1020 // Update PHI Nodes 1021 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1022 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1023 MachineBasicBlock *PHIBB = PHI->getParent(); 1024 assert(PHI->isPHI() && 1025 "This is not a machine PHI node that we are updating!"); 1026 // "default" BB. We can go there only from header BB. 1027 if (PHIBB == SDB->JTCases[i].second.Default) { 1028 PHI->addOperand 1029 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1030 PHI->addOperand 1031 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1032 } 1033 // JT BB. Just iterate over successors here 1034 if (BB->isSuccessor(PHIBB)) { 1035 PHI->addOperand 1036 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1037 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1038 } 1039 } 1040 } 1041 SDB->JTCases.clear(); 1042 1043 // If the switch block involved a branch to one of the actual successors, we 1044 // need to update PHI nodes in that block. 1045 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1046 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1047 assert(PHI->isPHI() && 1048 "This is not a machine PHI node that we are updating!"); 1049 if (BB->isSuccessor(PHI->getParent())) { 1050 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1051 false)); 1052 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1053 } 1054 } 1055 1056 // If we generated any switch lowering information, build and codegen any 1057 // additional DAGs necessary. 1058 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1059 // Set the current basic block to the mbb we wish to insert the code into 1060 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1061 SDB->setCurrentBasicBlock(BB); 1062 1063 // Emit the code 1064 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1065 CurDAG->setRoot(SDB->getRoot()); 1066 CodeGenAndEmitDAG(); 1067 1068 // Handle any PHI nodes in successors of this chunk, as if we were coming 1069 // from the original BB before switch expansion. Note that PHI nodes can 1070 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1071 // handle them the right number of times. 1072 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1073 // If new BB's are created during scheduling, the edges may have been 1074 // updated. That is, the edge from ThisBB to BB may have been split and 1075 // BB's predecessor is now another block. 1076 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1077 SDB->EdgeMapping.find(BB); 1078 if (EI != SDB->EdgeMapping.end()) 1079 ThisBB = EI->second; 1080 1081 // BB may have been removed from the CFG if a branch was constant folded. 1082 if (ThisBB->isSuccessor(BB)) { 1083 for (MachineBasicBlock::iterator Phi = BB->begin(); 1084 Phi != BB->end() && Phi->isPHI(); 1085 ++Phi) { 1086 // This value for this PHI node is recorded in PHINodesToUpdate. 1087 for (unsigned pn = 0; ; ++pn) { 1088 assert(pn != SDB->PHINodesToUpdate.size() && 1089 "Didn't find PHI entry!"); 1090 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1091 Phi->addOperand(MachineOperand:: 1092 CreateReg(SDB->PHINodesToUpdate[pn].second, 1093 false)); 1094 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1095 break; 1096 } 1097 } 1098 } 1099 } 1100 1101 // Don't process RHS if same block as LHS. 1102 if (BB == SDB->SwitchCases[i].FalseBB) 1103 SDB->SwitchCases[i].FalseBB = 0; 1104 1105 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1106 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1107 SDB->SwitchCases[i].FalseBB = 0; 1108 } 1109 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1110 SDB->clear(); 1111 } 1112 SDB->SwitchCases.clear(); 1113 1114 SDB->PHINodesToUpdate.clear(); 1115} 1116 1117 1118/// Create the scheduler. If a specific scheduler was specified 1119/// via the SchedulerRegistry, use it, otherwise select the 1120/// one preferred by the target. 1121/// 1122ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1123 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1124 1125 if (!Ctor) { 1126 Ctor = ISHeuristic; 1127 RegisterScheduler::setDefault(Ctor); 1128 } 1129 1130 return Ctor(this, OptLevel); 1131} 1132 1133ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1134 return new ScheduleHazardRecognizer(); 1135} 1136 1137//===----------------------------------------------------------------------===// 1138// Helper functions used by the generated instruction selector. 1139//===----------------------------------------------------------------------===// 1140// Calls to these methods are generated by tblgen. 1141 1142/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1143/// the dag combiner simplified the 255, we still want to match. RHS is the 1144/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1145/// specified in the .td file (e.g. 255). 1146bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1147 int64_t DesiredMaskS) const { 1148 const APInt &ActualMask = RHS->getAPIntValue(); 1149 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1150 1151 // If the actual mask exactly matches, success! 1152 if (ActualMask == DesiredMask) 1153 return true; 1154 1155 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1156 if (ActualMask.intersects(~DesiredMask)) 1157 return false; 1158 1159 // Otherwise, the DAG Combiner may have proven that the value coming in is 1160 // either already zero or is not demanded. Check for known zero input bits. 1161 APInt NeededMask = DesiredMask & ~ActualMask; 1162 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1163 return true; 1164 1165 // TODO: check to see if missing bits are just not demanded. 1166 1167 // Otherwise, this pattern doesn't match. 1168 return false; 1169} 1170 1171/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1172/// the dag combiner simplified the 255, we still want to match. RHS is the 1173/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1174/// specified in the .td file (e.g. 255). 1175bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1176 int64_t DesiredMaskS) const { 1177 const APInt &ActualMask = RHS->getAPIntValue(); 1178 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1179 1180 // If the actual mask exactly matches, success! 1181 if (ActualMask == DesiredMask) 1182 return true; 1183 1184 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1185 if (ActualMask.intersects(~DesiredMask)) 1186 return false; 1187 1188 // Otherwise, the DAG Combiner may have proven that the value coming in is 1189 // either already zero or is not demanded. Check for known zero input bits. 1190 APInt NeededMask = DesiredMask & ~ActualMask; 1191 1192 APInt KnownZero, KnownOne; 1193 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1194 1195 // If all the missing bits in the or are already known to be set, match! 1196 if ((NeededMask & KnownOne) == NeededMask) 1197 return true; 1198 1199 // TODO: check to see if missing bits are just not demanded. 1200 1201 // Otherwise, this pattern doesn't match. 1202 return false; 1203} 1204 1205 1206/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1207/// by tblgen. Others should not call it. 1208void SelectionDAGISel:: 1209SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1210 std::vector<SDValue> InOps; 1211 std::swap(InOps, Ops); 1212 1213 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1214 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1215 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1216 1217 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1218 if (InOps[e-1].getValueType() == MVT::Flag) 1219 --e; // Don't process a flag operand if it is here. 1220 1221 while (i != e) { 1222 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1223 if (!InlineAsm::isMemKind(Flags)) { 1224 // Just skip over this operand, copying the operands verbatim. 1225 Ops.insert(Ops.end(), InOps.begin()+i, 1226 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1227 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1228 } else { 1229 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1230 "Memory operand with multiple values?"); 1231 // Otherwise, this is a memory operand. Ask the target to select it. 1232 std::vector<SDValue> SelOps; 1233 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1234 report_fatal_error("Could not match memory address. Inline asm" 1235 " failure!"); 1236 1237 // Add this to the output node. 1238 unsigned NewFlags = 1239 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1240 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1241 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1242 i += 2; 1243 } 1244 } 1245 1246 // Add the flag input back if present. 1247 if (e != InOps.size()) 1248 Ops.push_back(InOps.back()); 1249} 1250 1251/// findFlagUse - Return use of EVT::Flag value produced by the specified 1252/// SDNode. 1253/// 1254static SDNode *findFlagUse(SDNode *N) { 1255 unsigned FlagResNo = N->getNumValues()-1; 1256 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1257 SDUse &Use = I.getUse(); 1258 if (Use.getResNo() == FlagResNo) 1259 return Use.getUser(); 1260 } 1261 return NULL; 1262} 1263 1264/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1265/// This function recursively traverses up the operand chain, ignoring 1266/// certain nodes. 1267static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1268 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1269 bool IgnoreChains) { 1270 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1271 // greater than all of its (recursive) operands. If we scan to a point where 1272 // 'use' is smaller than the node we're scanning for, then we know we will 1273 // never find it. 1274 // 1275 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1276 // happen because we scan down to newly selected nodes in the case of flag 1277 // uses. 1278 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1279 return false; 1280 1281 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1282 // won't fail if we scan it again. 1283 if (!Visited.insert(Use)) 1284 return false; 1285 1286 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1287 // Ignore chain uses, they are validated by HandleMergeInputChains. 1288 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1289 continue; 1290 1291 SDNode *N = Use->getOperand(i).getNode(); 1292 if (N == Def) { 1293 if (Use == ImmedUse || Use == Root) 1294 continue; // We are not looking for immediate use. 1295 assert(N != Root); 1296 return true; 1297 } 1298 1299 // Traverse up the operand chain. 1300 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1301 return true; 1302 } 1303 return false; 1304} 1305 1306/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1307/// operand node N of U during instruction selection that starts at Root. 1308bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1309 SDNode *Root) const { 1310 if (OptLevel == CodeGenOpt::None) return false; 1311 return N.hasOneUse(); 1312} 1313 1314/// IsLegalToFold - Returns true if the specific operand node N of 1315/// U can be folded during instruction selection that starts at Root. 1316bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1317 bool IgnoreChains) const { 1318 if (OptLevel == CodeGenOpt::None) return false; 1319 1320 // If Root use can somehow reach N through a path that that doesn't contain 1321 // U then folding N would create a cycle. e.g. In the following 1322 // diagram, Root can reach N through X. If N is folded into into Root, then 1323 // X is both a predecessor and a successor of U. 1324 // 1325 // [N*] // 1326 // ^ ^ // 1327 // / \ // 1328 // [U*] [X]? // 1329 // ^ ^ // 1330 // \ / // 1331 // \ / // 1332 // [Root*] // 1333 // 1334 // * indicates nodes to be folded together. 1335 // 1336 // If Root produces a flag, then it gets (even more) interesting. Since it 1337 // will be "glued" together with its flag use in the scheduler, we need to 1338 // check if it might reach N. 1339 // 1340 // [N*] // 1341 // ^ ^ // 1342 // / \ // 1343 // [U*] [X]? // 1344 // ^ ^ // 1345 // \ \ // 1346 // \ | // 1347 // [Root*] | // 1348 // ^ | // 1349 // f | // 1350 // | / // 1351 // [Y] / // 1352 // ^ / // 1353 // f / // 1354 // | / // 1355 // [FU] // 1356 // 1357 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1358 // (call it Fold), then X is a predecessor of FU and a successor of 1359 // Fold. But since Fold and FU are flagged together, this will create 1360 // a cycle in the scheduling graph. 1361 1362 // If the node has flags, walk down the graph to the "lowest" node in the 1363 // flagged set. 1364 EVT VT = Root->getValueType(Root->getNumValues()-1); 1365 while (VT == MVT::Flag) { 1366 SDNode *FU = findFlagUse(Root); 1367 if (FU == NULL) 1368 break; 1369 Root = FU; 1370 VT = Root->getValueType(Root->getNumValues()-1); 1371 1372 // If our query node has a flag result with a use, we've walked up it. If 1373 // the user (which has already been selected) has a chain or indirectly uses 1374 // the chain, our WalkChainUsers predicate will not consider it. Because of 1375 // this, we cannot ignore chains in this predicate. 1376 IgnoreChains = false; 1377 } 1378 1379 1380 SmallPtrSet<SDNode*, 16> Visited; 1381 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1382} 1383 1384SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1385 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1386 SelectInlineAsmMemoryOperands(Ops); 1387 1388 std::vector<EVT> VTs; 1389 VTs.push_back(MVT::Other); 1390 VTs.push_back(MVT::Flag); 1391 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1392 VTs, &Ops[0], Ops.size()); 1393 New->setNodeId(-1); 1394 return New.getNode(); 1395} 1396 1397SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1398 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1399} 1400 1401/// GetVBR - decode a vbr encoding whose top bit is set. 1402ALWAYS_INLINE static uint64_t 1403GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1404 assert(Val >= 128 && "Not a VBR"); 1405 Val &= 127; // Remove first vbr bit. 1406 1407 unsigned Shift = 7; 1408 uint64_t NextBits; 1409 do { 1410 NextBits = MatcherTable[Idx++]; 1411 Val |= (NextBits&127) << Shift; 1412 Shift += 7; 1413 } while (NextBits & 128); 1414 1415 return Val; 1416} 1417 1418 1419/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1420/// interior flag and chain results to use the new flag and chain results. 1421void SelectionDAGISel:: 1422UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1423 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1424 SDValue InputFlag, 1425 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1426 bool isMorphNodeTo) { 1427 SmallVector<SDNode*, 4> NowDeadNodes; 1428 1429 ISelUpdater ISU(ISelPosition); 1430 1431 // Now that all the normal results are replaced, we replace the chain and 1432 // flag results if present. 1433 if (!ChainNodesMatched.empty()) { 1434 assert(InputChain.getNode() != 0 && 1435 "Matched input chains but didn't produce a chain"); 1436 // Loop over all of the nodes we matched that produced a chain result. 1437 // Replace all the chain results with the final chain we ended up with. 1438 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1439 SDNode *ChainNode = ChainNodesMatched[i]; 1440 1441 // If this node was already deleted, don't look at it. 1442 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1443 continue; 1444 1445 // Don't replace the results of the root node if we're doing a 1446 // MorphNodeTo. 1447 if (ChainNode == NodeToMatch && isMorphNodeTo) 1448 continue; 1449 1450 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1451 if (ChainVal.getValueType() == MVT::Flag) 1452 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1453 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1454 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1455 1456 // If the node became dead and we haven't already seen it, delete it. 1457 if (ChainNode->use_empty() && 1458 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1459 NowDeadNodes.push_back(ChainNode); 1460 } 1461 } 1462 1463 // If the result produces a flag, update any flag results in the matched 1464 // pattern with the flag result. 1465 if (InputFlag.getNode() != 0) { 1466 // Handle any interior nodes explicitly marked. 1467 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1468 SDNode *FRN = FlagResultNodesMatched[i]; 1469 1470 // If this node was already deleted, don't look at it. 1471 if (FRN->getOpcode() == ISD::DELETED_NODE) 1472 continue; 1473 1474 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1475 "Doesn't have a flag result"); 1476 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1477 InputFlag, &ISU); 1478 1479 // If the node became dead and we haven't already seen it, delete it. 1480 if (FRN->use_empty() && 1481 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1482 NowDeadNodes.push_back(FRN); 1483 } 1484 } 1485 1486 if (!NowDeadNodes.empty()) 1487 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1488 1489 DEBUG(errs() << "ISEL: Match complete!\n"); 1490} 1491 1492enum ChainResult { 1493 CR_Simple, 1494 CR_InducesCycle, 1495 CR_LeadsToInteriorNode 1496}; 1497 1498/// WalkChainUsers - Walk down the users of the specified chained node that is 1499/// part of the pattern we're matching, looking at all of the users we find. 1500/// This determines whether something is an interior node, whether we have a 1501/// non-pattern node in between two pattern nodes (which prevent folding because 1502/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1503/// between pattern nodes (in which case the TF becomes part of the pattern). 1504/// 1505/// The walk we do here is guaranteed to be small because we quickly get down to 1506/// already selected nodes "below" us. 1507static ChainResult 1508WalkChainUsers(SDNode *ChainedNode, 1509 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1510 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1511 ChainResult Result = CR_Simple; 1512 1513 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1514 E = ChainedNode->use_end(); UI != E; ++UI) { 1515 // Make sure the use is of the chain, not some other value we produce. 1516 if (UI.getUse().getValueType() != MVT::Other) continue; 1517 1518 SDNode *User = *UI; 1519 1520 // If we see an already-selected machine node, then we've gone beyond the 1521 // pattern that we're selecting down into the already selected chunk of the 1522 // DAG. 1523 if (User->isMachineOpcode() || 1524 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1525 continue; 1526 1527 if (User->getOpcode() == ISD::CopyToReg || 1528 User->getOpcode() == ISD::CopyFromReg || 1529 User->getOpcode() == ISD::INLINEASM || 1530 User->getOpcode() == ISD::EH_LABEL) { 1531 // If their node ID got reset to -1 then they've already been selected. 1532 // Treat them like a MachineOpcode. 1533 if (User->getNodeId() == -1) 1534 continue; 1535 } 1536 1537 // If we have a TokenFactor, we handle it specially. 1538 if (User->getOpcode() != ISD::TokenFactor) { 1539 // If the node isn't a token factor and isn't part of our pattern, then it 1540 // must be a random chained node in between two nodes we're selecting. 1541 // This happens when we have something like: 1542 // x = load ptr 1543 // call 1544 // y = x+4 1545 // store y -> ptr 1546 // Because we structurally match the load/store as a read/modify/write, 1547 // but the call is chained between them. We cannot fold in this case 1548 // because it would induce a cycle in the graph. 1549 if (!std::count(ChainedNodesInPattern.begin(), 1550 ChainedNodesInPattern.end(), User)) 1551 return CR_InducesCycle; 1552 1553 // Otherwise we found a node that is part of our pattern. For example in: 1554 // x = load ptr 1555 // y = x+4 1556 // store y -> ptr 1557 // This would happen when we're scanning down from the load and see the 1558 // store as a user. Record that there is a use of ChainedNode that is 1559 // part of the pattern and keep scanning uses. 1560 Result = CR_LeadsToInteriorNode; 1561 InteriorChainedNodes.push_back(User); 1562 continue; 1563 } 1564 1565 // If we found a TokenFactor, there are two cases to consider: first if the 1566 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1567 // uses of the TF are in our pattern) we just want to ignore it. Second, 1568 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1569 // [Load chain] 1570 // ^ 1571 // | 1572 // [Load] 1573 // ^ ^ 1574 // | \ DAG's like cheese 1575 // / \ do you? 1576 // / | 1577 // [TokenFactor] [Op] 1578 // ^ ^ 1579 // | | 1580 // \ / 1581 // \ / 1582 // [Store] 1583 // 1584 // In this case, the TokenFactor becomes part of our match and we rewrite it 1585 // as a new TokenFactor. 1586 // 1587 // To distinguish these two cases, do a recursive walk down the uses. 1588 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1589 case CR_Simple: 1590 // If the uses of the TokenFactor are just already-selected nodes, ignore 1591 // it, it is "below" our pattern. 1592 continue; 1593 case CR_InducesCycle: 1594 // If the uses of the TokenFactor lead to nodes that are not part of our 1595 // pattern that are not selected, folding would turn this into a cycle, 1596 // bail out now. 1597 return CR_InducesCycle; 1598 case CR_LeadsToInteriorNode: 1599 break; // Otherwise, keep processing. 1600 } 1601 1602 // Okay, we know we're in the interesting interior case. The TokenFactor 1603 // is now going to be considered part of the pattern so that we rewrite its 1604 // uses (it may have uses that are not part of the pattern) with the 1605 // ultimate chain result of the generated code. We will also add its chain 1606 // inputs as inputs to the ultimate TokenFactor we create. 1607 Result = CR_LeadsToInteriorNode; 1608 ChainedNodesInPattern.push_back(User); 1609 InteriorChainedNodes.push_back(User); 1610 continue; 1611 } 1612 1613 return Result; 1614} 1615 1616/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1617/// operation for when the pattern matched at least one node with a chains. The 1618/// input vector contains a list of all of the chained nodes that we match. We 1619/// must determine if this is a valid thing to cover (i.e. matching it won't 1620/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1621/// be used as the input node chain for the generated nodes. 1622static SDValue 1623HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1624 SelectionDAG *CurDAG) { 1625 // Walk all of the chained nodes we've matched, recursively scanning down the 1626 // users of the chain result. This adds any TokenFactor nodes that are caught 1627 // in between chained nodes to the chained and interior nodes list. 1628 SmallVector<SDNode*, 3> InteriorChainedNodes; 1629 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1630 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1631 InteriorChainedNodes) == CR_InducesCycle) 1632 return SDValue(); // Would induce a cycle. 1633 } 1634 1635 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1636 // that we are interested in. Form our input TokenFactor node. 1637 SmallVector<SDValue, 3> InputChains; 1638 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1639 // Add the input chain of this node to the InputChains list (which will be 1640 // the operands of the generated TokenFactor) if it's not an interior node. 1641 SDNode *N = ChainNodesMatched[i]; 1642 if (N->getOpcode() != ISD::TokenFactor) { 1643 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1644 continue; 1645 1646 // Otherwise, add the input chain. 1647 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1648 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1649 InputChains.push_back(InChain); 1650 continue; 1651 } 1652 1653 // If we have a token factor, we want to add all inputs of the token factor 1654 // that are not part of the pattern we're matching. 1655 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1656 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1657 N->getOperand(op).getNode())) 1658 InputChains.push_back(N->getOperand(op)); 1659 } 1660 } 1661 1662 SDValue Res; 1663 if (InputChains.size() == 1) 1664 return InputChains[0]; 1665 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1666 MVT::Other, &InputChains[0], InputChains.size()); 1667} 1668 1669/// MorphNode - Handle morphing a node in place for the selector. 1670SDNode *SelectionDAGISel:: 1671MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1672 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1673 // It is possible we're using MorphNodeTo to replace a node with no 1674 // normal results with one that has a normal result (or we could be 1675 // adding a chain) and the input could have flags and chains as well. 1676 // In this case we need to shift the operands down. 1677 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1678 // than the old isel though. 1679 int OldFlagResultNo = -1, OldChainResultNo = -1; 1680 1681 unsigned NTMNumResults = Node->getNumValues(); 1682 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1683 OldFlagResultNo = NTMNumResults-1; 1684 if (NTMNumResults != 1 && 1685 Node->getValueType(NTMNumResults-2) == MVT::Other) 1686 OldChainResultNo = NTMNumResults-2; 1687 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1688 OldChainResultNo = NTMNumResults-1; 1689 1690 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1691 // that this deletes operands of the old node that become dead. 1692 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1693 1694 // MorphNodeTo can operate in two ways: if an existing node with the 1695 // specified operands exists, it can just return it. Otherwise, it 1696 // updates the node in place to have the requested operands. 1697 if (Res == Node) { 1698 // If we updated the node in place, reset the node ID. To the isel, 1699 // this should be just like a newly allocated machine node. 1700 Res->setNodeId(-1); 1701 } 1702 1703 unsigned ResNumResults = Res->getNumValues(); 1704 // Move the flag if needed. 1705 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1706 (unsigned)OldFlagResultNo != ResNumResults-1) 1707 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1708 SDValue(Res, ResNumResults-1)); 1709 1710 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1711 --ResNumResults; 1712 1713 // Move the chain reference if needed. 1714 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1715 (unsigned)OldChainResultNo != ResNumResults-1) 1716 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1717 SDValue(Res, ResNumResults-1)); 1718 1719 // Otherwise, no replacement happened because the node already exists. Replace 1720 // Uses of the old node with the new one. 1721 if (Res != Node) 1722 CurDAG->ReplaceAllUsesWith(Node, Res); 1723 1724 return Res; 1725} 1726 1727/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1728ALWAYS_INLINE static bool 1729CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1730 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1731 // Accept if it is exactly the same as a previously recorded node. 1732 unsigned RecNo = MatcherTable[MatcherIndex++]; 1733 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1734 return N == RecordedNodes[RecNo]; 1735} 1736 1737/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1738ALWAYS_INLINE static bool 1739CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1740 SelectionDAGISel &SDISel) { 1741 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1742} 1743 1744/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1745ALWAYS_INLINE static bool 1746CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1747 SelectionDAGISel &SDISel, SDNode *N) { 1748 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1749} 1750 1751ALWAYS_INLINE static bool 1752CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1753 SDNode *N) { 1754 uint16_t Opc = MatcherTable[MatcherIndex++]; 1755 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1756 return N->getOpcode() == Opc; 1757} 1758 1759ALWAYS_INLINE static bool 1760CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1761 SDValue N, const TargetLowering &TLI) { 1762 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1763 if (N.getValueType() == VT) return true; 1764 1765 // Handle the case when VT is iPTR. 1766 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1767} 1768 1769ALWAYS_INLINE static bool 1770CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1771 SDValue N, const TargetLowering &TLI, 1772 unsigned ChildNo) { 1773 if (ChildNo >= N.getNumOperands()) 1774 return false; // Match fails if out of range child #. 1775 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1776} 1777 1778 1779ALWAYS_INLINE static bool 1780CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1781 SDValue N) { 1782 return cast<CondCodeSDNode>(N)->get() == 1783 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1784} 1785 1786ALWAYS_INLINE static bool 1787CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1788 SDValue N, const TargetLowering &TLI) { 1789 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1790 if (cast<VTSDNode>(N)->getVT() == VT) 1791 return true; 1792 1793 // Handle the case when VT is iPTR. 1794 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1795} 1796 1797ALWAYS_INLINE static bool 1798CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1799 SDValue N) { 1800 int64_t Val = MatcherTable[MatcherIndex++]; 1801 if (Val & 128) 1802 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1803 1804 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1805 return C != 0 && C->getSExtValue() == Val; 1806} 1807 1808ALWAYS_INLINE static bool 1809CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1810 SDValue N, SelectionDAGISel &SDISel) { 1811 int64_t Val = MatcherTable[MatcherIndex++]; 1812 if (Val & 128) 1813 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1814 1815 if (N->getOpcode() != ISD::AND) return false; 1816 1817 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1818 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1819} 1820 1821ALWAYS_INLINE static bool 1822CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1823 SDValue N, SelectionDAGISel &SDISel) { 1824 int64_t Val = MatcherTable[MatcherIndex++]; 1825 if (Val & 128) 1826 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1827 1828 if (N->getOpcode() != ISD::OR) return false; 1829 1830 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1831 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1832} 1833 1834/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1835/// scope, evaluate the current node. If the current predicate is known to 1836/// fail, set Result=true and return anything. If the current predicate is 1837/// known to pass, set Result=false and return the MatcherIndex to continue 1838/// with. If the current predicate is unknown, set Result=false and return the 1839/// MatcherIndex to continue with. 1840static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1841 unsigned Index, SDValue N, 1842 bool &Result, SelectionDAGISel &SDISel, 1843 SmallVectorImpl<SDValue> &RecordedNodes){ 1844 switch (Table[Index++]) { 1845 default: 1846 Result = false; 1847 return Index-1; // Could not evaluate this predicate. 1848 case SelectionDAGISel::OPC_CheckSame: 1849 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1850 return Index; 1851 case SelectionDAGISel::OPC_CheckPatternPredicate: 1852 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1853 return Index; 1854 case SelectionDAGISel::OPC_CheckPredicate: 1855 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1856 return Index; 1857 case SelectionDAGISel::OPC_CheckOpcode: 1858 Result = !::CheckOpcode(Table, Index, N.getNode()); 1859 return Index; 1860 case SelectionDAGISel::OPC_CheckType: 1861 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1862 return Index; 1863 case SelectionDAGISel::OPC_CheckChild0Type: 1864 case SelectionDAGISel::OPC_CheckChild1Type: 1865 case SelectionDAGISel::OPC_CheckChild2Type: 1866 case SelectionDAGISel::OPC_CheckChild3Type: 1867 case SelectionDAGISel::OPC_CheckChild4Type: 1868 case SelectionDAGISel::OPC_CheckChild5Type: 1869 case SelectionDAGISel::OPC_CheckChild6Type: 1870 case SelectionDAGISel::OPC_CheckChild7Type: 1871 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1872 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1873 return Index; 1874 case SelectionDAGISel::OPC_CheckCondCode: 1875 Result = !::CheckCondCode(Table, Index, N); 1876 return Index; 1877 case SelectionDAGISel::OPC_CheckValueType: 1878 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1879 return Index; 1880 case SelectionDAGISel::OPC_CheckInteger: 1881 Result = !::CheckInteger(Table, Index, N); 1882 return Index; 1883 case SelectionDAGISel::OPC_CheckAndImm: 1884 Result = !::CheckAndImm(Table, Index, N, SDISel); 1885 return Index; 1886 case SelectionDAGISel::OPC_CheckOrImm: 1887 Result = !::CheckOrImm(Table, Index, N, SDISel); 1888 return Index; 1889 } 1890} 1891 1892 1893struct MatchScope { 1894 /// FailIndex - If this match fails, this is the index to continue with. 1895 unsigned FailIndex; 1896 1897 /// NodeStack - The node stack when the scope was formed. 1898 SmallVector<SDValue, 4> NodeStack; 1899 1900 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1901 unsigned NumRecordedNodes; 1902 1903 /// NumMatchedMemRefs - The number of matched memref entries. 1904 unsigned NumMatchedMemRefs; 1905 1906 /// InputChain/InputFlag - The current chain/flag 1907 SDValue InputChain, InputFlag; 1908 1909 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1910 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1911}; 1912 1913SDNode *SelectionDAGISel:: 1914SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1915 unsigned TableSize) { 1916 // FIXME: Should these even be selected? Handle these cases in the caller? 1917 switch (NodeToMatch->getOpcode()) { 1918 default: 1919 break; 1920 case ISD::EntryToken: // These nodes remain the same. 1921 case ISD::BasicBlock: 1922 case ISD::Register: 1923 //case ISD::VALUETYPE: 1924 //case ISD::CONDCODE: 1925 case ISD::HANDLENODE: 1926 case ISD::MDNODE_SDNODE: 1927 case ISD::TargetConstant: 1928 case ISD::TargetConstantFP: 1929 case ISD::TargetConstantPool: 1930 case ISD::TargetFrameIndex: 1931 case ISD::TargetExternalSymbol: 1932 case ISD::TargetBlockAddress: 1933 case ISD::TargetJumpTable: 1934 case ISD::TargetGlobalTLSAddress: 1935 case ISD::TargetGlobalAddress: 1936 case ISD::TokenFactor: 1937 case ISD::CopyFromReg: 1938 case ISD::CopyToReg: 1939 case ISD::EH_LABEL: 1940 NodeToMatch->setNodeId(-1); // Mark selected. 1941 return 0; 1942 case ISD::AssertSext: 1943 case ISD::AssertZext: 1944 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1945 NodeToMatch->getOperand(0)); 1946 return 0; 1947 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1948 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1949 } 1950 1951 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1952 1953 // Set up the node stack with NodeToMatch as the only node on the stack. 1954 SmallVector<SDValue, 8> NodeStack; 1955 SDValue N = SDValue(NodeToMatch, 0); 1956 NodeStack.push_back(N); 1957 1958 // MatchScopes - Scopes used when matching, if a match failure happens, this 1959 // indicates where to continue checking. 1960 SmallVector<MatchScope, 8> MatchScopes; 1961 1962 // RecordedNodes - This is the set of nodes that have been recorded by the 1963 // state machine. 1964 SmallVector<SDValue, 8> RecordedNodes; 1965 1966 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1967 // pattern. 1968 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1969 1970 // These are the current input chain and flag for use when generating nodes. 1971 // Various Emit operations change these. For example, emitting a copytoreg 1972 // uses and updates these. 1973 SDValue InputChain, InputFlag; 1974 1975 // ChainNodesMatched - If a pattern matches nodes that have input/output 1976 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1977 // which ones they are. The result is captured into this list so that we can 1978 // update the chain results when the pattern is complete. 1979 SmallVector<SDNode*, 3> ChainNodesMatched; 1980 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1981 1982 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1983 NodeToMatch->dump(CurDAG); 1984 errs() << '\n'); 1985 1986 // Determine where to start the interpreter. Normally we start at opcode #0, 1987 // but if the state machine starts with an OPC_SwitchOpcode, then we 1988 // accelerate the first lookup (which is guaranteed to be hot) with the 1989 // OpcodeOffset table. 1990 unsigned MatcherIndex = 0; 1991 1992 if (!OpcodeOffset.empty()) { 1993 // Already computed the OpcodeOffset table, just index into it. 1994 if (N.getOpcode() < OpcodeOffset.size()) 1995 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1996 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1997 1998 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1999 // Otherwise, the table isn't computed, but the state machine does start 2000 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2001 // is the first time we're selecting an instruction. 2002 unsigned Idx = 1; 2003 while (1) { 2004 // Get the size of this case. 2005 unsigned CaseSize = MatcherTable[Idx++]; 2006 if (CaseSize & 128) 2007 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2008 if (CaseSize == 0) break; 2009 2010 // Get the opcode, add the index to the table. 2011 uint16_t Opc = MatcherTable[Idx++]; 2012 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2013 if (Opc >= OpcodeOffset.size()) 2014 OpcodeOffset.resize((Opc+1)*2); 2015 OpcodeOffset[Opc] = Idx; 2016 Idx += CaseSize; 2017 } 2018 2019 // Okay, do the lookup for the first opcode. 2020 if (N.getOpcode() < OpcodeOffset.size()) 2021 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2022 } 2023 2024 while (1) { 2025 assert(MatcherIndex < TableSize && "Invalid index"); 2026#ifndef NDEBUG 2027 unsigned CurrentOpcodeIndex = MatcherIndex; 2028#endif 2029 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2030 switch (Opcode) { 2031 case OPC_Scope: { 2032 // Okay, the semantics of this operation are that we should push a scope 2033 // then evaluate the first child. However, pushing a scope only to have 2034 // the first check fail (which then pops it) is inefficient. If we can 2035 // determine immediately that the first check (or first several) will 2036 // immediately fail, don't even bother pushing a scope for them. 2037 unsigned FailIndex; 2038 2039 while (1) { 2040 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2041 if (NumToSkip & 128) 2042 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2043 // Found the end of the scope with no match. 2044 if (NumToSkip == 0) { 2045 FailIndex = 0; 2046 break; 2047 } 2048 2049 FailIndex = MatcherIndex+NumToSkip; 2050 2051 unsigned MatcherIndexOfPredicate = MatcherIndex; 2052 (void)MatcherIndexOfPredicate; // silence warning. 2053 2054 // If we can't evaluate this predicate without pushing a scope (e.g. if 2055 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2056 // push the scope and evaluate the full predicate chain. 2057 bool Result; 2058 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2059 Result, *this, RecordedNodes); 2060 if (!Result) 2061 break; 2062 2063 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2064 << "index " << MatcherIndexOfPredicate 2065 << ", continuing at " << FailIndex << "\n"); 2066 ++NumDAGIselRetries; 2067 2068 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2069 // move to the next case. 2070 MatcherIndex = FailIndex; 2071 } 2072 2073 // If the whole scope failed to match, bail. 2074 if (FailIndex == 0) break; 2075 2076 // Push a MatchScope which indicates where to go if the first child fails 2077 // to match. 2078 MatchScope NewEntry; 2079 NewEntry.FailIndex = FailIndex; 2080 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2081 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2082 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2083 NewEntry.InputChain = InputChain; 2084 NewEntry.InputFlag = InputFlag; 2085 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2086 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2087 MatchScopes.push_back(NewEntry); 2088 continue; 2089 } 2090 case OPC_RecordNode: 2091 // Remember this node, it may end up being an operand in the pattern. 2092 RecordedNodes.push_back(N); 2093 continue; 2094 2095 case OPC_RecordChild0: case OPC_RecordChild1: 2096 case OPC_RecordChild2: case OPC_RecordChild3: 2097 case OPC_RecordChild4: case OPC_RecordChild5: 2098 case OPC_RecordChild6: case OPC_RecordChild7: { 2099 unsigned ChildNo = Opcode-OPC_RecordChild0; 2100 if (ChildNo >= N.getNumOperands()) 2101 break; // Match fails if out of range child #. 2102 2103 RecordedNodes.push_back(N->getOperand(ChildNo)); 2104 continue; 2105 } 2106 case OPC_RecordMemRef: 2107 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2108 continue; 2109 2110 case OPC_CaptureFlagInput: 2111 // If the current node has an input flag, capture it in InputFlag. 2112 if (N->getNumOperands() != 0 && 2113 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2114 InputFlag = N->getOperand(N->getNumOperands()-1); 2115 continue; 2116 2117 case OPC_MoveChild: { 2118 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2119 if (ChildNo >= N.getNumOperands()) 2120 break; // Match fails if out of range child #. 2121 N = N.getOperand(ChildNo); 2122 NodeStack.push_back(N); 2123 continue; 2124 } 2125 2126 case OPC_MoveParent: 2127 // Pop the current node off the NodeStack. 2128 NodeStack.pop_back(); 2129 assert(!NodeStack.empty() && "Node stack imbalance!"); 2130 N = NodeStack.back(); 2131 continue; 2132 2133 case OPC_CheckSame: 2134 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2135 continue; 2136 case OPC_CheckPatternPredicate: 2137 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2138 continue; 2139 case OPC_CheckPredicate: 2140 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2141 N.getNode())) 2142 break; 2143 continue; 2144 case OPC_CheckComplexPat: { 2145 unsigned CPNum = MatcherTable[MatcherIndex++]; 2146 unsigned RecNo = MatcherTable[MatcherIndex++]; 2147 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2148 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2149 RecordedNodes)) 2150 break; 2151 continue; 2152 } 2153 case OPC_CheckOpcode: 2154 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2155 continue; 2156 2157 case OPC_CheckType: 2158 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2159 continue; 2160 2161 case OPC_SwitchOpcode: { 2162 unsigned CurNodeOpcode = N.getOpcode(); 2163 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2164 unsigned CaseSize; 2165 while (1) { 2166 // Get the size of this case. 2167 CaseSize = MatcherTable[MatcherIndex++]; 2168 if (CaseSize & 128) 2169 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2170 if (CaseSize == 0) break; 2171 2172 uint16_t Opc = MatcherTable[MatcherIndex++]; 2173 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2174 2175 // If the opcode matches, then we will execute this case. 2176 if (CurNodeOpcode == Opc) 2177 break; 2178 2179 // Otherwise, skip over this case. 2180 MatcherIndex += CaseSize; 2181 } 2182 2183 // If no cases matched, bail out. 2184 if (CaseSize == 0) break; 2185 2186 // Otherwise, execute the case we found. 2187 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2188 << " to " << MatcherIndex << "\n"); 2189 continue; 2190 } 2191 2192 case OPC_SwitchType: { 2193 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2194 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2195 unsigned CaseSize; 2196 while (1) { 2197 // Get the size of this case. 2198 CaseSize = MatcherTable[MatcherIndex++]; 2199 if (CaseSize & 128) 2200 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2201 if (CaseSize == 0) break; 2202 2203 MVT::SimpleValueType CaseVT = 2204 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2205 if (CaseVT == MVT::iPTR) 2206 CaseVT = TLI.getPointerTy().SimpleTy; 2207 2208 // If the VT matches, then we will execute this case. 2209 if (CurNodeVT == CaseVT) 2210 break; 2211 2212 // Otherwise, skip over this case. 2213 MatcherIndex += CaseSize; 2214 } 2215 2216 // If no cases matched, bail out. 2217 if (CaseSize == 0) break; 2218 2219 // Otherwise, execute the case we found. 2220 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2221 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2222 continue; 2223 } 2224 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2225 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2226 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2227 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2228 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2229 Opcode-OPC_CheckChild0Type)) 2230 break; 2231 continue; 2232 case OPC_CheckCondCode: 2233 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2234 continue; 2235 case OPC_CheckValueType: 2236 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2237 continue; 2238 case OPC_CheckInteger: 2239 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2240 continue; 2241 case OPC_CheckAndImm: 2242 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2243 continue; 2244 case OPC_CheckOrImm: 2245 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2246 continue; 2247 2248 case OPC_CheckFoldableChainNode: { 2249 assert(NodeStack.size() != 1 && "No parent node"); 2250 // Verify that all intermediate nodes between the root and this one have 2251 // a single use. 2252 bool HasMultipleUses = false; 2253 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2254 if (!NodeStack[i].hasOneUse()) { 2255 HasMultipleUses = true; 2256 break; 2257 } 2258 if (HasMultipleUses) break; 2259 2260 // Check to see that the target thinks this is profitable to fold and that 2261 // we can fold it without inducing cycles in the graph. 2262 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2263 NodeToMatch) || 2264 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2265 NodeToMatch, true/*We validate our own chains*/)) 2266 break; 2267 2268 continue; 2269 } 2270 case OPC_EmitInteger: { 2271 MVT::SimpleValueType VT = 2272 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2273 int64_t Val = MatcherTable[MatcherIndex++]; 2274 if (Val & 128) 2275 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2276 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2277 continue; 2278 } 2279 case OPC_EmitRegister: { 2280 MVT::SimpleValueType VT = 2281 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2282 unsigned RegNo = MatcherTable[MatcherIndex++]; 2283 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2284 continue; 2285 } 2286 2287 case OPC_EmitConvertToTarget: { 2288 // Convert from IMM/FPIMM to target version. 2289 unsigned RecNo = MatcherTable[MatcherIndex++]; 2290 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2291 SDValue Imm = RecordedNodes[RecNo]; 2292 2293 if (Imm->getOpcode() == ISD::Constant) { 2294 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2295 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2296 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2297 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2298 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2299 } 2300 2301 RecordedNodes.push_back(Imm); 2302 continue; 2303 } 2304 2305 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2306 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2307 // These are space-optimized forms of OPC_EmitMergeInputChains. 2308 assert(InputChain.getNode() == 0 && 2309 "EmitMergeInputChains should be the first chain producing node"); 2310 assert(ChainNodesMatched.empty() && 2311 "Should only have one EmitMergeInputChains per match"); 2312 2313 // Read all of the chained nodes. 2314 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2315 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2316 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2317 2318 // FIXME: What if other value results of the node have uses not matched 2319 // by this pattern? 2320 if (ChainNodesMatched.back() != NodeToMatch && 2321 !RecordedNodes[RecNo].hasOneUse()) { 2322 ChainNodesMatched.clear(); 2323 break; 2324 } 2325 2326 // Merge the input chains if they are not intra-pattern references. 2327 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2328 2329 if (InputChain.getNode() == 0) 2330 break; // Failed to merge. 2331 continue; 2332 } 2333 2334 case OPC_EmitMergeInputChains: { 2335 assert(InputChain.getNode() == 0 && 2336 "EmitMergeInputChains should be the first chain producing node"); 2337 // This node gets a list of nodes we matched in the input that have 2338 // chains. We want to token factor all of the input chains to these nodes 2339 // together. However, if any of the input chains is actually one of the 2340 // nodes matched in this pattern, then we have an intra-match reference. 2341 // Ignore these because the newly token factored chain should not refer to 2342 // the old nodes. 2343 unsigned NumChains = MatcherTable[MatcherIndex++]; 2344 assert(NumChains != 0 && "Can't TF zero chains"); 2345 2346 assert(ChainNodesMatched.empty() && 2347 "Should only have one EmitMergeInputChains per match"); 2348 2349 // Read all of the chained nodes. 2350 for (unsigned i = 0; i != NumChains; ++i) { 2351 unsigned RecNo = MatcherTable[MatcherIndex++]; 2352 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2353 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2354 2355 // FIXME: What if other value results of the node have uses not matched 2356 // by this pattern? 2357 if (ChainNodesMatched.back() != NodeToMatch && 2358 !RecordedNodes[RecNo].hasOneUse()) { 2359 ChainNodesMatched.clear(); 2360 break; 2361 } 2362 } 2363 2364 // If the inner loop broke out, the match fails. 2365 if (ChainNodesMatched.empty()) 2366 break; 2367 2368 // Merge the input chains if they are not intra-pattern references. 2369 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2370 2371 if (InputChain.getNode() == 0) 2372 break; // Failed to merge. 2373 2374 continue; 2375 } 2376 2377 case OPC_EmitCopyToReg: { 2378 unsigned RecNo = MatcherTable[MatcherIndex++]; 2379 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2380 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2381 2382 if (InputChain.getNode() == 0) 2383 InputChain = CurDAG->getEntryNode(); 2384 2385 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2386 DestPhysReg, RecordedNodes[RecNo], 2387 InputFlag); 2388 2389 InputFlag = InputChain.getValue(1); 2390 continue; 2391 } 2392 2393 case OPC_EmitNodeXForm: { 2394 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2395 unsigned RecNo = MatcherTable[MatcherIndex++]; 2396 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2397 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2398 continue; 2399 } 2400 2401 case OPC_EmitNode: 2402 case OPC_MorphNodeTo: { 2403 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2404 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2405 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2406 // Get the result VT list. 2407 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2408 SmallVector<EVT, 4> VTs; 2409 for (unsigned i = 0; i != NumVTs; ++i) { 2410 MVT::SimpleValueType VT = 2411 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2412 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2413 VTs.push_back(VT); 2414 } 2415 2416 if (EmitNodeInfo & OPFL_Chain) 2417 VTs.push_back(MVT::Other); 2418 if (EmitNodeInfo & OPFL_FlagOutput) 2419 VTs.push_back(MVT::Flag); 2420 2421 // This is hot code, so optimize the two most common cases of 1 and 2 2422 // results. 2423 SDVTList VTList; 2424 if (VTs.size() == 1) 2425 VTList = CurDAG->getVTList(VTs[0]); 2426 else if (VTs.size() == 2) 2427 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2428 else 2429 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2430 2431 // Get the operand list. 2432 unsigned NumOps = MatcherTable[MatcherIndex++]; 2433 SmallVector<SDValue, 8> Ops; 2434 for (unsigned i = 0; i != NumOps; ++i) { 2435 unsigned RecNo = MatcherTable[MatcherIndex++]; 2436 if (RecNo & 128) 2437 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2438 2439 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2440 Ops.push_back(RecordedNodes[RecNo]); 2441 } 2442 2443 // If there are variadic operands to add, handle them now. 2444 if (EmitNodeInfo & OPFL_VariadicInfo) { 2445 // Determine the start index to copy from. 2446 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2447 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2448 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2449 "Invalid variadic node"); 2450 // Copy all of the variadic operands, not including a potential flag 2451 // input. 2452 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2453 i != e; ++i) { 2454 SDValue V = NodeToMatch->getOperand(i); 2455 if (V.getValueType() == MVT::Flag) break; 2456 Ops.push_back(V); 2457 } 2458 } 2459 2460 // If this has chain/flag inputs, add them. 2461 if (EmitNodeInfo & OPFL_Chain) 2462 Ops.push_back(InputChain); 2463 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2464 Ops.push_back(InputFlag); 2465 2466 // Create the node. 2467 SDNode *Res = 0; 2468 if (Opcode != OPC_MorphNodeTo) { 2469 // If this is a normal EmitNode command, just create the new node and 2470 // add the results to the RecordedNodes list. 2471 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2472 VTList, Ops.data(), Ops.size()); 2473 2474 // Add all the non-flag/non-chain results to the RecordedNodes list. 2475 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2476 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2477 RecordedNodes.push_back(SDValue(Res, i)); 2478 } 2479 2480 } else { 2481 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2482 EmitNodeInfo); 2483 } 2484 2485 // If the node had chain/flag results, update our notion of the current 2486 // chain and flag. 2487 if (EmitNodeInfo & OPFL_FlagOutput) { 2488 InputFlag = SDValue(Res, VTs.size()-1); 2489 if (EmitNodeInfo & OPFL_Chain) 2490 InputChain = SDValue(Res, VTs.size()-2); 2491 } else if (EmitNodeInfo & OPFL_Chain) 2492 InputChain = SDValue(Res, VTs.size()-1); 2493 2494 // If the OPFL_MemRefs flag is set on this node, slap all of the 2495 // accumulated memrefs onto it. 2496 // 2497 // FIXME: This is vastly incorrect for patterns with multiple outputs 2498 // instructions that access memory and for ComplexPatterns that match 2499 // loads. 2500 if (EmitNodeInfo & OPFL_MemRefs) { 2501 MachineSDNode::mmo_iterator MemRefs = 2502 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2503 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2504 cast<MachineSDNode>(Res) 2505 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2506 } 2507 2508 DEBUG(errs() << " " 2509 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2510 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2511 2512 // If this was a MorphNodeTo then we're completely done! 2513 if (Opcode == OPC_MorphNodeTo) { 2514 // Update chain and flag uses. 2515 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2516 InputFlag, FlagResultNodesMatched, true); 2517 return Res; 2518 } 2519 2520 continue; 2521 } 2522 2523 case OPC_MarkFlagResults: { 2524 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2525 2526 // Read and remember all the flag-result nodes. 2527 for (unsigned i = 0; i != NumNodes; ++i) { 2528 unsigned RecNo = MatcherTable[MatcherIndex++]; 2529 if (RecNo & 128) 2530 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2531 2532 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2533 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2534 } 2535 continue; 2536 } 2537 2538 case OPC_CompleteMatch: { 2539 // The match has been completed, and any new nodes (if any) have been 2540 // created. Patch up references to the matched dag to use the newly 2541 // created nodes. 2542 unsigned NumResults = MatcherTable[MatcherIndex++]; 2543 2544 for (unsigned i = 0; i != NumResults; ++i) { 2545 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2546 if (ResSlot & 128) 2547 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2548 2549 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2550 SDValue Res = RecordedNodes[ResSlot]; 2551 2552 assert(i < NodeToMatch->getNumValues() && 2553 NodeToMatch->getValueType(i) != MVT::Other && 2554 NodeToMatch->getValueType(i) != MVT::Flag && 2555 "Invalid number of results to complete!"); 2556 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2557 NodeToMatch->getValueType(i) == MVT::iPTR || 2558 Res.getValueType() == MVT::iPTR || 2559 NodeToMatch->getValueType(i).getSizeInBits() == 2560 Res.getValueType().getSizeInBits()) && 2561 "invalid replacement"); 2562 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2563 } 2564 2565 // If the root node defines a flag, add it to the flag nodes to update 2566 // list. 2567 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2568 FlagResultNodesMatched.push_back(NodeToMatch); 2569 2570 // Update chain and flag uses. 2571 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2572 InputFlag, FlagResultNodesMatched, false); 2573 2574 assert(NodeToMatch->use_empty() && 2575 "Didn't replace all uses of the node?"); 2576 2577 // FIXME: We just return here, which interacts correctly with SelectRoot 2578 // above. We should fix this to not return an SDNode* anymore. 2579 return 0; 2580 } 2581 } 2582 2583 // If the code reached this point, then the match failed. See if there is 2584 // another child to try in the current 'Scope', otherwise pop it until we 2585 // find a case to check. 2586 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2587 ++NumDAGIselRetries; 2588 while (1) { 2589 if (MatchScopes.empty()) { 2590 CannotYetSelect(NodeToMatch); 2591 return 0; 2592 } 2593 2594 // Restore the interpreter state back to the point where the scope was 2595 // formed. 2596 MatchScope &LastScope = MatchScopes.back(); 2597 RecordedNodes.resize(LastScope.NumRecordedNodes); 2598 NodeStack.clear(); 2599 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2600 N = NodeStack.back(); 2601 2602 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2603 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2604 MatcherIndex = LastScope.FailIndex; 2605 2606 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2607 2608 InputChain = LastScope.InputChain; 2609 InputFlag = LastScope.InputFlag; 2610 if (!LastScope.HasChainNodesMatched) 2611 ChainNodesMatched.clear(); 2612 if (!LastScope.HasFlagResultNodesMatched) 2613 FlagResultNodesMatched.clear(); 2614 2615 // Check to see what the offset is at the new MatcherIndex. If it is zero 2616 // we have reached the end of this scope, otherwise we have another child 2617 // in the current scope to try. 2618 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2619 if (NumToSkip & 128) 2620 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2621 2622 // If we have another child in this scope to match, update FailIndex and 2623 // try it. 2624 if (NumToSkip != 0) { 2625 LastScope.FailIndex = MatcherIndex+NumToSkip; 2626 break; 2627 } 2628 2629 // End of this scope, pop it and try the next child in the containing 2630 // scope. 2631 MatchScopes.pop_back(); 2632 } 2633 } 2634} 2635 2636 2637 2638void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2639 std::string msg; 2640 raw_string_ostream Msg(msg); 2641 Msg << "Cannot yet select: "; 2642 2643 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2644 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2645 N->getOpcode() != ISD::INTRINSIC_VOID) { 2646 N->printrFull(Msg, CurDAG); 2647 } else { 2648 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2649 unsigned iid = 2650 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2651 if (iid < Intrinsic::num_intrinsics) 2652 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2653 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2654 Msg << "target intrinsic %" << TII->getName(iid); 2655 else 2656 Msg << "unknown intrinsic #" << iid; 2657 } 2658 report_fatal_error(Msg.str()); 2659} 2660 2661char SelectionDAGISel::ID = 0; 2662