SelectionDAGISel.cpp revision 8a7f7426eeb18fef58c3471db23fc829b67bc350
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322MachineBasicBlock * 323SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 324 const BasicBlock *LLVMBB, 325 BasicBlock::const_iterator Begin, 326 BasicBlock::const_iterator End, 327 bool &HadTailCall) { 328 // Lower all of the non-terminator instructions. If a call is emitted 329 // as a tail call, cease emitting nodes for this block. Terminators 330 // are handled below. 331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 332 SDB->visit(*I); 333 334 // Make sure the root of the DAG is up-to-date. 335 CurDAG->setRoot(SDB->getControlRoot()); 336 HadTailCall = SDB->HasTailCall; 337 SDB->clear(); 338 339 // Final step, emit the lowered DAG as machine code. 340 return CodeGenAndEmitDAG(BB); 341} 342 343namespace { 344/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 345/// nodes from the worklist. 346class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 347 SmallVector<SDNode*, 128> &Worklist; 348 SmallPtrSet<SDNode*, 128> &InWorklist; 349public: 350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 351 SmallPtrSet<SDNode*, 128> &inwl) 352 : Worklist(wl), InWorklist(inwl) {} 353 354 void RemoveFromWorklist(SDNode *N) { 355 if (!InWorklist.erase(N)) return; 356 357 SmallVector<SDNode*, 128>::iterator I = 358 std::find(Worklist.begin(), Worklist.end(), N); 359 assert(I != Worklist.end() && "Not in worklist"); 360 361 *I = Worklist.back(); 362 Worklist.pop_back(); 363 } 364 365 virtual void NodeDeleted(SDNode *N, SDNode *E) { 366 RemoveFromWorklist(N); 367 } 368 369 virtual void NodeUpdated(SDNode *N) { 370 // Ignore updates. 371 } 372}; 373} 374 375void SelectionDAGISel::ComputeLiveOutVRegInfo() { 376 SmallPtrSet<SDNode*, 128> VisitedNodes; 377 SmallVector<SDNode*, 128> Worklist; 378 379 Worklist.push_back(CurDAG->getRoot().getNode()); 380 381 APInt Mask; 382 APInt KnownZero; 383 APInt KnownOne; 384 385 do { 386 SDNode *N = Worklist.pop_back_val(); 387 388 // If we've already seen this node, ignore it. 389 if (!VisitedNodes.insert(N)) 390 continue; 391 392 // Otherwise, add all chain operands to the worklist. 393 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 394 if (N->getOperand(i).getValueType() == MVT::Other) 395 Worklist.push_back(N->getOperand(i).getNode()); 396 397 // If this is a CopyToReg with a vreg dest, process it. 398 if (N->getOpcode() != ISD::CopyToReg) 399 continue; 400 401 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 402 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 403 continue; 404 405 // Ignore non-scalar or non-integer values. 406 SDValue Src = N->getOperand(2); 407 EVT SrcVT = Src.getValueType(); 408 if (!SrcVT.isInteger() || SrcVT.isVector()) 409 continue; 410 411 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 412 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 413 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 414 415 // Only install this information if it tells us something. 416 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 417 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 418 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 419 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 420 FunctionLoweringInfo::LiveOutInfo &LOI = 421 FuncInfo->LiveOutRegInfo[DestReg]; 422 LOI.NumSignBits = NumSignBits; 423 LOI.KnownOne = KnownOne; 424 LOI.KnownZero = KnownZero; 425 } 426 } while (!Worklist.empty()); 427} 428 429MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 430 std::string GroupName; 431 if (TimePassesIsEnabled) 432 GroupName = "Instruction Selection and Scheduling"; 433 std::string BlockName; 434 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 435 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 436 ViewSUnitDAGs) 437 BlockName = MF->getFunction()->getNameStr() + ":" + 438 BB->getBasicBlock()->getNameStr(); 439 440 DEBUG(dbgs() << "Initial selection DAG:\n"); 441 DEBUG(CurDAG->dump()); 442 443 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 444 445 // Run the DAG combiner in pre-legalize mode. 446 if (TimePassesIsEnabled) { 447 NamedRegionTimer T("DAG Combining 1", GroupName); 448 CurDAG->Combine(Unrestricted, *AA, OptLevel); 449 } else { 450 CurDAG->Combine(Unrestricted, *AA, OptLevel); 451 } 452 453 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 454 DEBUG(CurDAG->dump()); 455 456 // Second step, hack on the DAG until it only uses operations and types that 457 // the target supports. 458 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 459 BlockName); 460 461 bool Changed; 462 if (TimePassesIsEnabled) { 463 NamedRegionTimer T("Type Legalization", GroupName); 464 Changed = CurDAG->LegalizeTypes(); 465 } else { 466 Changed = CurDAG->LegalizeTypes(); 467 } 468 469 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 470 DEBUG(CurDAG->dump()); 471 472 if (Changed) { 473 if (ViewDAGCombineLT) 474 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 475 476 // Run the DAG combiner in post-type-legalize mode. 477 if (TimePassesIsEnabled) { 478 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 479 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 480 } else { 481 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 482 } 483 484 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 485 DEBUG(CurDAG->dump()); 486 } 487 488 if (TimePassesIsEnabled) { 489 NamedRegionTimer T("Vector Legalization", GroupName); 490 Changed = CurDAG->LegalizeVectors(); 491 } else { 492 Changed = CurDAG->LegalizeVectors(); 493 } 494 495 if (Changed) { 496 if (TimePassesIsEnabled) { 497 NamedRegionTimer T("Type Legalization 2", GroupName); 498 CurDAG->LegalizeTypes(); 499 } else { 500 CurDAG->LegalizeTypes(); 501 } 502 503 if (ViewDAGCombineLT) 504 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 505 506 // Run the DAG combiner in post-type-legalize mode. 507 if (TimePassesIsEnabled) { 508 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 509 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 510 } else { 511 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 512 } 513 514 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 515 DEBUG(CurDAG->dump()); 516 } 517 518 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 519 520 if (TimePassesIsEnabled) { 521 NamedRegionTimer T("DAG Legalization", GroupName); 522 CurDAG->Legalize(OptLevel); 523 } else { 524 CurDAG->Legalize(OptLevel); 525 } 526 527 DEBUG(dbgs() << "Legalized selection DAG:\n"); 528 DEBUG(CurDAG->dump()); 529 530 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 531 532 // Run the DAG combiner in post-legalize mode. 533 if (TimePassesIsEnabled) { 534 NamedRegionTimer T("DAG Combining 2", GroupName); 535 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 536 } else { 537 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 538 } 539 540 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 541 DEBUG(CurDAG->dump()); 542 543 if (OptLevel != CodeGenOpt::None) 544 ComputeLiveOutVRegInfo(); 545 546 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 547 548 // Third, instruction select all of the operations to machine code, adding the 549 // code to the MachineBasicBlock. 550 if (TimePassesIsEnabled) { 551 NamedRegionTimer T("Instruction Selection", GroupName); 552 DoInstructionSelection(); 553 } else { 554 DoInstructionSelection(); 555 } 556 557 DEBUG(dbgs() << "Selected selection DAG:\n"); 558 DEBUG(CurDAG->dump()); 559 560 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 561 562 // Schedule machine code. 563 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 564 if (TimePassesIsEnabled) { 565 NamedRegionTimer T("Instruction Scheduling", GroupName); 566 Scheduler->Run(CurDAG, BB, BB->end()); 567 } else { 568 Scheduler->Run(CurDAG, BB, BB->end()); 569 } 570 571 if (ViewSUnitDAGs) Scheduler->viewGraph(); 572 573 // Emit machine code to BB. This can change 'BB' to the last block being 574 // inserted into. 575 if (TimePassesIsEnabled) { 576 NamedRegionTimer T("Instruction Creation", GroupName); 577 BB = Scheduler->EmitSchedule(); 578 } else { 579 BB = Scheduler->EmitSchedule(); 580 } 581 582 // Free the scheduler state. 583 if (TimePassesIsEnabled) { 584 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 585 delete Scheduler; 586 } else { 587 delete Scheduler; 588 } 589 590 // Free the SelectionDAG state, now that we're finished with it. 591 CurDAG->clear(); 592 593 return BB; 594} 595 596void SelectionDAGISel::DoInstructionSelection() { 597 DEBUG(errs() << "===== Instruction selection begins:\n"); 598 599 PreprocessISelDAG(); 600 601 // Select target instructions for the DAG. 602 { 603 // Number all nodes with a topological order and set DAGSize. 604 DAGSize = CurDAG->AssignTopologicalOrder(); 605 606 // Create a dummy node (which is not added to allnodes), that adds 607 // a reference to the root node, preventing it from being deleted, 608 // and tracking any changes of the root. 609 HandleSDNode Dummy(CurDAG->getRoot()); 610 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 611 ++ISelPosition; 612 613 // The AllNodes list is now topological-sorted. Visit the 614 // nodes by starting at the end of the list (the root of the 615 // graph) and preceding back toward the beginning (the entry 616 // node). 617 while (ISelPosition != CurDAG->allnodes_begin()) { 618 SDNode *Node = --ISelPosition; 619 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 620 // but there are currently some corner cases that it misses. Also, this 621 // makes it theoretically possible to disable the DAGCombiner. 622 if (Node->use_empty()) 623 continue; 624 625 SDNode *ResNode = Select(Node); 626 627 // FIXME: This is pretty gross. 'Select' should be changed to not return 628 // anything at all and this code should be nuked with a tactical strike. 629 630 // If node should not be replaced, continue with the next one. 631 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 632 continue; 633 // Replace node. 634 if (ResNode) 635 ReplaceUses(Node, ResNode); 636 637 // If after the replacement this node is not used any more, 638 // remove this dead node. 639 if (Node->use_empty()) { // Don't delete EntryToken, etc. 640 ISelUpdater ISU(ISelPosition); 641 CurDAG->RemoveDeadNode(Node, &ISU); 642 } 643 } 644 645 CurDAG->setRoot(Dummy.getValue()); 646 } 647 648 DEBUG(errs() << "===== Instruction selection ends:\n"); 649 650 PostprocessISelDAG(); 651} 652 653/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 654/// do other setup for EH landing-pad blocks. 655void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 656 // Add a label to mark the beginning of the landing pad. Deletion of the 657 // landing pad can thus be detected via the MachineModuleInfo. 658 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 659 660 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 661 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 662 663 // Mark exception register as live in. 664 unsigned Reg = TLI.getExceptionAddressRegister(); 665 if (Reg) BB->addLiveIn(Reg); 666 667 // Mark exception selector register as live in. 668 Reg = TLI.getExceptionSelectorRegister(); 669 if (Reg) BB->addLiveIn(Reg); 670 671 // FIXME: Hack around an exception handling flaw (PR1508): the personality 672 // function and list of typeids logically belong to the invoke (or, if you 673 // like, the basic block containing the invoke), and need to be associated 674 // with it in the dwarf exception handling tables. Currently however the 675 // information is provided by an intrinsic (eh.selector) that can be moved 676 // to unexpected places by the optimizers: if the unwind edge is critical, 677 // then breaking it can result in the intrinsics being in the successor of 678 // the landing pad, not the landing pad itself. This results 679 // in exceptions not being caught because no typeids are associated with 680 // the invoke. This may not be the only way things can go wrong, but it 681 // is the only way we try to work around for the moment. 682 const BasicBlock *LLVMBB = BB->getBasicBlock(); 683 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 684 685 if (Br && Br->isUnconditional()) { // Critical edge? 686 BasicBlock::const_iterator I, E; 687 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 688 if (isa<EHSelectorInst>(I)) 689 break; 690 691 if (I == E) 692 // No catch info found - try to extract some from the successor. 693 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 694 } 695} 696 697void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 698 // Initialize the Fast-ISel state, if needed. 699 FastISel *FastIS = 0; 700 if (EnableFastISel) 701 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 702 FuncInfo->StaticAllocaMap, 703 FuncInfo->PHINodesToUpdate 704#ifndef NDEBUG 705 , FuncInfo->CatchInfoLost 706#endif 707 ); 708 709 // Iterate over all basic blocks in the function. 710 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 711 const BasicBlock *LLVMBB = &*I; 712 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 713 714 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 715 BasicBlock::const_iterator const End = LLVMBB->end(); 716 BasicBlock::const_iterator BI = Begin; 717 718 // Lower any arguments needed in this block if this is the entry block. 719 if (LLVMBB == &Fn.getEntryBlock()) 720 LowerArguments(LLVMBB); 721 722 // Setup an EH landing-pad block. 723 if (BB->isLandingPad()) 724 PrepareEHLandingPad(BB); 725 726 // Before doing SelectionDAG ISel, see if FastISel has been requested. 727 if (FastIS) { 728 // Emit code for any incoming arguments. This must happen before 729 // beginning FastISel on the entry block. 730 if (LLVMBB == &Fn.getEntryBlock()) { 731 CurDAG->setRoot(SDB->getControlRoot()); 732 SDB->clear(); 733 BB = CodeGenAndEmitDAG(BB); 734 } 735 FastIS->startNewBlock(BB); 736 // Do FastISel on as many instructions as possible. 737 for (; BI != End; ++BI) { 738 // Try to select the instruction with FastISel. 739 if (FastIS->SelectInstruction(BI)) 740 continue; 741 742 // Then handle certain instructions as single-LLVM-Instruction blocks. 743 if (isa<CallInst>(BI)) { 744 ++NumFastIselFailures; 745 if (EnableFastISelVerbose || EnableFastISelAbort) { 746 dbgs() << "FastISel missed call: "; 747 BI->dump(); 748 } 749 750 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 751 unsigned &R = FuncInfo->ValueMap[BI]; 752 if (!R) 753 R = FuncInfo->CreateRegForValue(BI); 754 } 755 756 bool HadTailCall = false; 757 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 758 759 // If the call was emitted as a tail call, we're done with the block. 760 if (HadTailCall) { 761 BI = End; 762 break; 763 } 764 765 // If the instruction was codegen'd with multiple blocks, 766 // inform the FastISel object where to resume inserting. 767 FastIS->setCurrentBlock(BB); 768 continue; 769 } 770 771 // Otherwise, give up on FastISel for the rest of the block. 772 // For now, be a little lenient about non-branch terminators. 773 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 774 ++NumFastIselFailures; 775 if (EnableFastISelVerbose || EnableFastISelAbort) { 776 dbgs() << "FastISel miss: "; 777 BI->dump(); 778 } 779 if (EnableFastISelAbort) 780 // The "fast" selector couldn't handle something and bailed. 781 // For the purpose of debugging, just abort. 782 llvm_unreachable("FastISel didn't select the entire block"); 783 } 784 break; 785 } 786 } 787 788 // Run SelectionDAG instruction selection on the remainder of the block 789 // not handled by FastISel. If FastISel is not run, this is the entire 790 // block. 791 if (BI != End) { 792 bool HadTailCall; 793 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 794 } 795 796 FinishBasicBlock(BB); 797 FuncInfo->PHINodesToUpdate.clear(); 798 } 799 800 delete FastIS; 801} 802 803void 804SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 805 806 DEBUG(dbgs() << "Total amount of phi nodes to update: " 807 << FuncInfo->PHINodesToUpdate.size() << "\n"); 808 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 809 dbgs() << "Node " << i << " : (" 810 << FuncInfo->PHINodesToUpdate[i].first 811 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 812 813 // Next, now that we know what the last MBB the LLVM BB expanded is, update 814 // PHI nodes in successors. 815 if (SDB->SwitchCases.empty() && 816 SDB->JTCases.empty() && 817 SDB->BitTestCases.empty()) { 818 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 819 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 820 assert(PHI->isPHI() && 821 "This is not a machine PHI node that we are updating!"); 822 if (!BB->isSuccessor(PHI->getParent())) 823 continue; 824 PHI->addOperand( 825 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 826 PHI->addOperand(MachineOperand::CreateMBB(BB)); 827 } 828 return; 829 } 830 831 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 832 // Lower header first, if it wasn't already lowered 833 if (!SDB->BitTestCases[i].Emitted) { 834 // Set the current basic block to the mbb we wish to insert the code into 835 BB = SDB->BitTestCases[i].Parent; 836 // Emit the code 837 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 838 CurDAG->setRoot(SDB->getRoot()); 839 SDB->clear(); 840 BB = CodeGenAndEmitDAG(BB); 841 } 842 843 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 844 // Set the current basic block to the mbb we wish to insert the code into 845 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 846 // Emit the code 847 if (j+1 != ej) 848 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 849 SDB->BitTestCases[i].Reg, 850 SDB->BitTestCases[i].Cases[j], 851 BB); 852 else 853 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 854 SDB->BitTestCases[i].Reg, 855 SDB->BitTestCases[i].Cases[j], 856 BB); 857 858 859 CurDAG->setRoot(SDB->getRoot()); 860 SDB->clear(); 861 BB = CodeGenAndEmitDAG(BB); 862 } 863 864 // Update PHI Nodes 865 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 866 pi != pe; ++pi) { 867 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 868 MachineBasicBlock *PHIBB = PHI->getParent(); 869 assert(PHI->isPHI() && 870 "This is not a machine PHI node that we are updating!"); 871 // This is "default" BB. We have two jumps to it. From "header" BB and 872 // from last "case" BB. 873 if (PHIBB == SDB->BitTestCases[i].Default) { 874 PHI->addOperand(MachineOperand:: 875 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 876 false)); 877 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 878 PHI->addOperand(MachineOperand:: 879 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 880 false)); 881 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 882 back().ThisBB)); 883 } 884 // One of "cases" BB. 885 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 886 j != ej; ++j) { 887 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 888 if (cBB->isSuccessor(PHIBB)) { 889 PHI->addOperand(MachineOperand:: 890 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 891 false)); 892 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 893 } 894 } 895 } 896 } 897 SDB->BitTestCases.clear(); 898 899 // If the JumpTable record is filled in, then we need to emit a jump table. 900 // Updating the PHI nodes is tricky in this case, since we need to determine 901 // whether the PHI is a successor of the range check MBB or the jump table MBB 902 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 903 // Lower header first, if it wasn't already lowered 904 if (!SDB->JTCases[i].first.Emitted) { 905 // Set the current basic block to the mbb we wish to insert the code into 906 BB = SDB->JTCases[i].first.HeaderBB; 907 // Emit the code 908 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 909 BB); 910 CurDAG->setRoot(SDB->getRoot()); 911 SDB->clear(); 912 BB = CodeGenAndEmitDAG(BB); 913 } 914 915 // Set the current basic block to the mbb we wish to insert the code into 916 BB = SDB->JTCases[i].second.MBB; 917 // Emit the code 918 SDB->visitJumpTable(SDB->JTCases[i].second); 919 CurDAG->setRoot(SDB->getRoot()); 920 SDB->clear(); 921 BB = CodeGenAndEmitDAG(BB); 922 923 // Update PHI Nodes 924 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 925 pi != pe; ++pi) { 926 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 927 MachineBasicBlock *PHIBB = PHI->getParent(); 928 assert(PHI->isPHI() && 929 "This is not a machine PHI node that we are updating!"); 930 // "default" BB. We can go there only from header BB. 931 if (PHIBB == SDB->JTCases[i].second.Default) { 932 PHI->addOperand 933 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 934 false)); 935 PHI->addOperand 936 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 937 } 938 // JT BB. Just iterate over successors here 939 if (BB->isSuccessor(PHIBB)) { 940 PHI->addOperand 941 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 942 false)); 943 PHI->addOperand(MachineOperand::CreateMBB(BB)); 944 } 945 } 946 } 947 SDB->JTCases.clear(); 948 949 // If the switch block involved a branch to one of the actual successors, we 950 // need to update PHI nodes in that block. 951 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 952 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 953 assert(PHI->isPHI() && 954 "This is not a machine PHI node that we are updating!"); 955 if (BB->isSuccessor(PHI->getParent())) { 956 PHI->addOperand( 957 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 958 PHI->addOperand(MachineOperand::CreateMBB(BB)); 959 } 960 } 961 962 // If we generated any switch lowering information, build and codegen any 963 // additional DAGs necessary. 964 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 965 // Set the current basic block to the mbb we wish to insert the code into 966 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 967 968 // Determine the unique successors. 969 SmallVector<MachineBasicBlock *, 2> Succs; 970 Succs.push_back(SDB->SwitchCases[i].TrueBB); 971 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 972 Succs.push_back(SDB->SwitchCases[i].FalseBB); 973 974 // Emit the code. Note that this could result in ThisBB being split, so 975 // we need to check for updates. 976 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 977 CurDAG->setRoot(SDB->getRoot()); 978 SDB->clear(); 979 ThisBB = CodeGenAndEmitDAG(BB); 980 981 // Handle any PHI nodes in successors of this chunk, as if we were coming 982 // from the original BB before switch expansion. Note that PHI nodes can 983 // occur multiple times in PHINodesToUpdate. We have to be very careful to 984 // handle them the right number of times. 985 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 986 BB = Succs[i]; 987 // BB may have been removed from the CFG if a branch was constant folded. 988 if (ThisBB->isSuccessor(BB)) { 989 for (MachineBasicBlock::iterator Phi = BB->begin(); 990 Phi != BB->end() && Phi->isPHI(); 991 ++Phi) { 992 // This value for this PHI node is recorded in PHINodesToUpdate. 993 for (unsigned pn = 0; ; ++pn) { 994 assert(pn != FuncInfo->PHINodesToUpdate.size() && 995 "Didn't find PHI entry!"); 996 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 997 Phi->addOperand(MachineOperand:: 998 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 999 false)); 1000 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1001 break; 1002 } 1003 } 1004 } 1005 } 1006 } 1007 } 1008 SDB->SwitchCases.clear(); 1009} 1010 1011 1012/// Create the scheduler. If a specific scheduler was specified 1013/// via the SchedulerRegistry, use it, otherwise select the 1014/// one preferred by the target. 1015/// 1016ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1017 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1018 1019 if (!Ctor) { 1020 Ctor = ISHeuristic; 1021 RegisterScheduler::setDefault(Ctor); 1022 } 1023 1024 return Ctor(this, OptLevel); 1025} 1026 1027ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1028 return new ScheduleHazardRecognizer(); 1029} 1030 1031//===----------------------------------------------------------------------===// 1032// Helper functions used by the generated instruction selector. 1033//===----------------------------------------------------------------------===// 1034// Calls to these methods are generated by tblgen. 1035 1036/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1037/// the dag combiner simplified the 255, we still want to match. RHS is the 1038/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1039/// specified in the .td file (e.g. 255). 1040bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1041 int64_t DesiredMaskS) const { 1042 const APInt &ActualMask = RHS->getAPIntValue(); 1043 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1044 1045 // If the actual mask exactly matches, success! 1046 if (ActualMask == DesiredMask) 1047 return true; 1048 1049 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1050 if (ActualMask.intersects(~DesiredMask)) 1051 return false; 1052 1053 // Otherwise, the DAG Combiner may have proven that the value coming in is 1054 // either already zero or is not demanded. Check for known zero input bits. 1055 APInt NeededMask = DesiredMask & ~ActualMask; 1056 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1057 return true; 1058 1059 // TODO: check to see if missing bits are just not demanded. 1060 1061 // Otherwise, this pattern doesn't match. 1062 return false; 1063} 1064 1065/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1066/// the dag combiner simplified the 255, we still want to match. RHS is the 1067/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1068/// specified in the .td file (e.g. 255). 1069bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1070 int64_t DesiredMaskS) const { 1071 const APInt &ActualMask = RHS->getAPIntValue(); 1072 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1073 1074 // If the actual mask exactly matches, success! 1075 if (ActualMask == DesiredMask) 1076 return true; 1077 1078 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1079 if (ActualMask.intersects(~DesiredMask)) 1080 return false; 1081 1082 // Otherwise, the DAG Combiner may have proven that the value coming in is 1083 // either already zero or is not demanded. Check for known zero input bits. 1084 APInt NeededMask = DesiredMask & ~ActualMask; 1085 1086 APInt KnownZero, KnownOne; 1087 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1088 1089 // If all the missing bits in the or are already known to be set, match! 1090 if ((NeededMask & KnownOne) == NeededMask) 1091 return true; 1092 1093 // TODO: check to see if missing bits are just not demanded. 1094 1095 // Otherwise, this pattern doesn't match. 1096 return false; 1097} 1098 1099 1100/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1101/// by tblgen. Others should not call it. 1102void SelectionDAGISel:: 1103SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1104 std::vector<SDValue> InOps; 1105 std::swap(InOps, Ops); 1106 1107 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1108 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1109 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1110 1111 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1112 if (InOps[e-1].getValueType() == MVT::Flag) 1113 --e; // Don't process a flag operand if it is here. 1114 1115 while (i != e) { 1116 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1117 if (!InlineAsm::isMemKind(Flags)) { 1118 // Just skip over this operand, copying the operands verbatim. 1119 Ops.insert(Ops.end(), InOps.begin()+i, 1120 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1121 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1122 } else { 1123 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1124 "Memory operand with multiple values?"); 1125 // Otherwise, this is a memory operand. Ask the target to select it. 1126 std::vector<SDValue> SelOps; 1127 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1128 report_fatal_error("Could not match memory address. Inline asm" 1129 " failure!"); 1130 1131 // Add this to the output node. 1132 unsigned NewFlags = 1133 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1134 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1135 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1136 i += 2; 1137 } 1138 } 1139 1140 // Add the flag input back if present. 1141 if (e != InOps.size()) 1142 Ops.push_back(InOps.back()); 1143} 1144 1145/// findFlagUse - Return use of EVT::Flag value produced by the specified 1146/// SDNode. 1147/// 1148static SDNode *findFlagUse(SDNode *N) { 1149 unsigned FlagResNo = N->getNumValues()-1; 1150 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1151 SDUse &Use = I.getUse(); 1152 if (Use.getResNo() == FlagResNo) 1153 return Use.getUser(); 1154 } 1155 return NULL; 1156} 1157 1158/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1159/// This function recursively traverses up the operand chain, ignoring 1160/// certain nodes. 1161static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1162 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1163 bool IgnoreChains) { 1164 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1165 // greater than all of its (recursive) operands. If we scan to a point where 1166 // 'use' is smaller than the node we're scanning for, then we know we will 1167 // never find it. 1168 // 1169 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1170 // happen because we scan down to newly selected nodes in the case of flag 1171 // uses. 1172 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1173 return false; 1174 1175 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1176 // won't fail if we scan it again. 1177 if (!Visited.insert(Use)) 1178 return false; 1179 1180 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1181 // Ignore chain uses, they are validated by HandleMergeInputChains. 1182 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1183 continue; 1184 1185 SDNode *N = Use->getOperand(i).getNode(); 1186 if (N == Def) { 1187 if (Use == ImmedUse || Use == Root) 1188 continue; // We are not looking for immediate use. 1189 assert(N != Root); 1190 return true; 1191 } 1192 1193 // Traverse up the operand chain. 1194 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1195 return true; 1196 } 1197 return false; 1198} 1199 1200/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1201/// operand node N of U during instruction selection that starts at Root. 1202bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1203 SDNode *Root) const { 1204 if (OptLevel == CodeGenOpt::None) return false; 1205 return N.hasOneUse(); 1206} 1207 1208/// IsLegalToFold - Returns true if the specific operand node N of 1209/// U can be folded during instruction selection that starts at Root. 1210bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1211 CodeGenOpt::Level OptLevel, 1212 bool IgnoreChains) { 1213 if (OptLevel == CodeGenOpt::None) return false; 1214 1215 // If Root use can somehow reach N through a path that that doesn't contain 1216 // U then folding N would create a cycle. e.g. In the following 1217 // diagram, Root can reach N through X. If N is folded into into Root, then 1218 // X is both a predecessor and a successor of U. 1219 // 1220 // [N*] // 1221 // ^ ^ // 1222 // / \ // 1223 // [U*] [X]? // 1224 // ^ ^ // 1225 // \ / // 1226 // \ / // 1227 // [Root*] // 1228 // 1229 // * indicates nodes to be folded together. 1230 // 1231 // If Root produces a flag, then it gets (even more) interesting. Since it 1232 // will be "glued" together with its flag use in the scheduler, we need to 1233 // check if it might reach N. 1234 // 1235 // [N*] // 1236 // ^ ^ // 1237 // / \ // 1238 // [U*] [X]? // 1239 // ^ ^ // 1240 // \ \ // 1241 // \ | // 1242 // [Root*] | // 1243 // ^ | // 1244 // f | // 1245 // | / // 1246 // [Y] / // 1247 // ^ / // 1248 // f / // 1249 // | / // 1250 // [FU] // 1251 // 1252 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1253 // (call it Fold), then X is a predecessor of FU and a successor of 1254 // Fold. But since Fold and FU are flagged together, this will create 1255 // a cycle in the scheduling graph. 1256 1257 // If the node has flags, walk down the graph to the "lowest" node in the 1258 // flagged set. 1259 EVT VT = Root->getValueType(Root->getNumValues()-1); 1260 while (VT == MVT::Flag) { 1261 SDNode *FU = findFlagUse(Root); 1262 if (FU == NULL) 1263 break; 1264 Root = FU; 1265 VT = Root->getValueType(Root->getNumValues()-1); 1266 1267 // If our query node has a flag result with a use, we've walked up it. If 1268 // the user (which has already been selected) has a chain or indirectly uses 1269 // the chain, our WalkChainUsers predicate will not consider it. Because of 1270 // this, we cannot ignore chains in this predicate. 1271 IgnoreChains = false; 1272 } 1273 1274 1275 SmallPtrSet<SDNode*, 16> Visited; 1276 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1277} 1278 1279SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1280 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1281 SelectInlineAsmMemoryOperands(Ops); 1282 1283 std::vector<EVT> VTs; 1284 VTs.push_back(MVT::Other); 1285 VTs.push_back(MVT::Flag); 1286 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1287 VTs, &Ops[0], Ops.size()); 1288 New->setNodeId(-1); 1289 return New.getNode(); 1290} 1291 1292SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1293 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1294} 1295 1296/// GetVBR - decode a vbr encoding whose top bit is set. 1297ALWAYS_INLINE static uint64_t 1298GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1299 assert(Val >= 128 && "Not a VBR"); 1300 Val &= 127; // Remove first vbr bit. 1301 1302 unsigned Shift = 7; 1303 uint64_t NextBits; 1304 do { 1305 NextBits = MatcherTable[Idx++]; 1306 Val |= (NextBits&127) << Shift; 1307 Shift += 7; 1308 } while (NextBits & 128); 1309 1310 return Val; 1311} 1312 1313 1314/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1315/// interior flag and chain results to use the new flag and chain results. 1316void SelectionDAGISel:: 1317UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1318 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1319 SDValue InputFlag, 1320 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1321 bool isMorphNodeTo) { 1322 SmallVector<SDNode*, 4> NowDeadNodes; 1323 1324 ISelUpdater ISU(ISelPosition); 1325 1326 // Now that all the normal results are replaced, we replace the chain and 1327 // flag results if present. 1328 if (!ChainNodesMatched.empty()) { 1329 assert(InputChain.getNode() != 0 && 1330 "Matched input chains but didn't produce a chain"); 1331 // Loop over all of the nodes we matched that produced a chain result. 1332 // Replace all the chain results with the final chain we ended up with. 1333 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1334 SDNode *ChainNode = ChainNodesMatched[i]; 1335 1336 // If this node was already deleted, don't look at it. 1337 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1338 continue; 1339 1340 // Don't replace the results of the root node if we're doing a 1341 // MorphNodeTo. 1342 if (ChainNode == NodeToMatch && isMorphNodeTo) 1343 continue; 1344 1345 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1346 if (ChainVal.getValueType() == MVT::Flag) 1347 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1348 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1349 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1350 1351 // If the node became dead and we haven't already seen it, delete it. 1352 if (ChainNode->use_empty() && 1353 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1354 NowDeadNodes.push_back(ChainNode); 1355 } 1356 } 1357 1358 // If the result produces a flag, update any flag results in the matched 1359 // pattern with the flag result. 1360 if (InputFlag.getNode() != 0) { 1361 // Handle any interior nodes explicitly marked. 1362 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1363 SDNode *FRN = FlagResultNodesMatched[i]; 1364 1365 // If this node was already deleted, don't look at it. 1366 if (FRN->getOpcode() == ISD::DELETED_NODE) 1367 continue; 1368 1369 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1370 "Doesn't have a flag result"); 1371 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1372 InputFlag, &ISU); 1373 1374 // If the node became dead and we haven't already seen it, delete it. 1375 if (FRN->use_empty() && 1376 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1377 NowDeadNodes.push_back(FRN); 1378 } 1379 } 1380 1381 if (!NowDeadNodes.empty()) 1382 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1383 1384 DEBUG(errs() << "ISEL: Match complete!\n"); 1385} 1386 1387enum ChainResult { 1388 CR_Simple, 1389 CR_InducesCycle, 1390 CR_LeadsToInteriorNode 1391}; 1392 1393/// WalkChainUsers - Walk down the users of the specified chained node that is 1394/// part of the pattern we're matching, looking at all of the users we find. 1395/// This determines whether something is an interior node, whether we have a 1396/// non-pattern node in between two pattern nodes (which prevent folding because 1397/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1398/// between pattern nodes (in which case the TF becomes part of the pattern). 1399/// 1400/// The walk we do here is guaranteed to be small because we quickly get down to 1401/// already selected nodes "below" us. 1402static ChainResult 1403WalkChainUsers(SDNode *ChainedNode, 1404 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1405 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1406 ChainResult Result = CR_Simple; 1407 1408 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1409 E = ChainedNode->use_end(); UI != E; ++UI) { 1410 // Make sure the use is of the chain, not some other value we produce. 1411 if (UI.getUse().getValueType() != MVT::Other) continue; 1412 1413 SDNode *User = *UI; 1414 1415 // If we see an already-selected machine node, then we've gone beyond the 1416 // pattern that we're selecting down into the already selected chunk of the 1417 // DAG. 1418 if (User->isMachineOpcode() || 1419 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1420 continue; 1421 1422 if (User->getOpcode() == ISD::CopyToReg || 1423 User->getOpcode() == ISD::CopyFromReg || 1424 User->getOpcode() == ISD::INLINEASM || 1425 User->getOpcode() == ISD::EH_LABEL) { 1426 // If their node ID got reset to -1 then they've already been selected. 1427 // Treat them like a MachineOpcode. 1428 if (User->getNodeId() == -1) 1429 continue; 1430 } 1431 1432 // If we have a TokenFactor, we handle it specially. 1433 if (User->getOpcode() != ISD::TokenFactor) { 1434 // If the node isn't a token factor and isn't part of our pattern, then it 1435 // must be a random chained node in between two nodes we're selecting. 1436 // This happens when we have something like: 1437 // x = load ptr 1438 // call 1439 // y = x+4 1440 // store y -> ptr 1441 // Because we structurally match the load/store as a read/modify/write, 1442 // but the call is chained between them. We cannot fold in this case 1443 // because it would induce a cycle in the graph. 1444 if (!std::count(ChainedNodesInPattern.begin(), 1445 ChainedNodesInPattern.end(), User)) 1446 return CR_InducesCycle; 1447 1448 // Otherwise we found a node that is part of our pattern. For example in: 1449 // x = load ptr 1450 // y = x+4 1451 // store y -> ptr 1452 // This would happen when we're scanning down from the load and see the 1453 // store as a user. Record that there is a use of ChainedNode that is 1454 // part of the pattern and keep scanning uses. 1455 Result = CR_LeadsToInteriorNode; 1456 InteriorChainedNodes.push_back(User); 1457 continue; 1458 } 1459 1460 // If we found a TokenFactor, there are two cases to consider: first if the 1461 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1462 // uses of the TF are in our pattern) we just want to ignore it. Second, 1463 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1464 // [Load chain] 1465 // ^ 1466 // | 1467 // [Load] 1468 // ^ ^ 1469 // | \ DAG's like cheese 1470 // / \ do you? 1471 // / | 1472 // [TokenFactor] [Op] 1473 // ^ ^ 1474 // | | 1475 // \ / 1476 // \ / 1477 // [Store] 1478 // 1479 // In this case, the TokenFactor becomes part of our match and we rewrite it 1480 // as a new TokenFactor. 1481 // 1482 // To distinguish these two cases, do a recursive walk down the uses. 1483 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1484 case CR_Simple: 1485 // If the uses of the TokenFactor are just already-selected nodes, ignore 1486 // it, it is "below" our pattern. 1487 continue; 1488 case CR_InducesCycle: 1489 // If the uses of the TokenFactor lead to nodes that are not part of our 1490 // pattern that are not selected, folding would turn this into a cycle, 1491 // bail out now. 1492 return CR_InducesCycle; 1493 case CR_LeadsToInteriorNode: 1494 break; // Otherwise, keep processing. 1495 } 1496 1497 // Okay, we know we're in the interesting interior case. The TokenFactor 1498 // is now going to be considered part of the pattern so that we rewrite its 1499 // uses (it may have uses that are not part of the pattern) with the 1500 // ultimate chain result of the generated code. We will also add its chain 1501 // inputs as inputs to the ultimate TokenFactor we create. 1502 Result = CR_LeadsToInteriorNode; 1503 ChainedNodesInPattern.push_back(User); 1504 InteriorChainedNodes.push_back(User); 1505 continue; 1506 } 1507 1508 return Result; 1509} 1510 1511/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1512/// operation for when the pattern matched at least one node with a chains. The 1513/// input vector contains a list of all of the chained nodes that we match. We 1514/// must determine if this is a valid thing to cover (i.e. matching it won't 1515/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1516/// be used as the input node chain for the generated nodes. 1517static SDValue 1518HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1519 SelectionDAG *CurDAG) { 1520 // Walk all of the chained nodes we've matched, recursively scanning down the 1521 // users of the chain result. This adds any TokenFactor nodes that are caught 1522 // in between chained nodes to the chained and interior nodes list. 1523 SmallVector<SDNode*, 3> InteriorChainedNodes; 1524 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1525 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1526 InteriorChainedNodes) == CR_InducesCycle) 1527 return SDValue(); // Would induce a cycle. 1528 } 1529 1530 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1531 // that we are interested in. Form our input TokenFactor node. 1532 SmallVector<SDValue, 3> InputChains; 1533 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1534 // Add the input chain of this node to the InputChains list (which will be 1535 // the operands of the generated TokenFactor) if it's not an interior node. 1536 SDNode *N = ChainNodesMatched[i]; 1537 if (N->getOpcode() != ISD::TokenFactor) { 1538 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1539 continue; 1540 1541 // Otherwise, add the input chain. 1542 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1543 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1544 InputChains.push_back(InChain); 1545 continue; 1546 } 1547 1548 // If we have a token factor, we want to add all inputs of the token factor 1549 // that are not part of the pattern we're matching. 1550 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1551 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1552 N->getOperand(op).getNode())) 1553 InputChains.push_back(N->getOperand(op)); 1554 } 1555 } 1556 1557 SDValue Res; 1558 if (InputChains.size() == 1) 1559 return InputChains[0]; 1560 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1561 MVT::Other, &InputChains[0], InputChains.size()); 1562} 1563 1564/// MorphNode - Handle morphing a node in place for the selector. 1565SDNode *SelectionDAGISel:: 1566MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1567 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1568 // It is possible we're using MorphNodeTo to replace a node with no 1569 // normal results with one that has a normal result (or we could be 1570 // adding a chain) and the input could have flags and chains as well. 1571 // In this case we need to shift the operands down. 1572 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1573 // than the old isel though. 1574 int OldFlagResultNo = -1, OldChainResultNo = -1; 1575 1576 unsigned NTMNumResults = Node->getNumValues(); 1577 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1578 OldFlagResultNo = NTMNumResults-1; 1579 if (NTMNumResults != 1 && 1580 Node->getValueType(NTMNumResults-2) == MVT::Other) 1581 OldChainResultNo = NTMNumResults-2; 1582 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1583 OldChainResultNo = NTMNumResults-1; 1584 1585 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1586 // that this deletes operands of the old node that become dead. 1587 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1588 1589 // MorphNodeTo can operate in two ways: if an existing node with the 1590 // specified operands exists, it can just return it. Otherwise, it 1591 // updates the node in place to have the requested operands. 1592 if (Res == Node) { 1593 // If we updated the node in place, reset the node ID. To the isel, 1594 // this should be just like a newly allocated machine node. 1595 Res->setNodeId(-1); 1596 } 1597 1598 unsigned ResNumResults = Res->getNumValues(); 1599 // Move the flag if needed. 1600 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1601 (unsigned)OldFlagResultNo != ResNumResults-1) 1602 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1603 SDValue(Res, ResNumResults-1)); 1604 1605 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1606 --ResNumResults; 1607 1608 // Move the chain reference if needed. 1609 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1610 (unsigned)OldChainResultNo != ResNumResults-1) 1611 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1612 SDValue(Res, ResNumResults-1)); 1613 1614 // Otherwise, no replacement happened because the node already exists. Replace 1615 // Uses of the old node with the new one. 1616 if (Res != Node) 1617 CurDAG->ReplaceAllUsesWith(Node, Res); 1618 1619 return Res; 1620} 1621 1622/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1623ALWAYS_INLINE static bool 1624CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1625 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1626 // Accept if it is exactly the same as a previously recorded node. 1627 unsigned RecNo = MatcherTable[MatcherIndex++]; 1628 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1629 return N == RecordedNodes[RecNo]; 1630} 1631 1632/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1633ALWAYS_INLINE static bool 1634CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1635 SelectionDAGISel &SDISel) { 1636 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1637} 1638 1639/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1640ALWAYS_INLINE static bool 1641CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1642 SelectionDAGISel &SDISel, SDNode *N) { 1643 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1644} 1645 1646ALWAYS_INLINE static bool 1647CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1648 SDNode *N) { 1649 uint16_t Opc = MatcherTable[MatcherIndex++]; 1650 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1651 return N->getOpcode() == Opc; 1652} 1653 1654ALWAYS_INLINE static bool 1655CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1656 SDValue N, const TargetLowering &TLI) { 1657 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1658 if (N.getValueType() == VT) return true; 1659 1660 // Handle the case when VT is iPTR. 1661 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1662} 1663 1664ALWAYS_INLINE static bool 1665CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1666 SDValue N, const TargetLowering &TLI, 1667 unsigned ChildNo) { 1668 if (ChildNo >= N.getNumOperands()) 1669 return false; // Match fails if out of range child #. 1670 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1671} 1672 1673 1674ALWAYS_INLINE static bool 1675CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1676 SDValue N) { 1677 return cast<CondCodeSDNode>(N)->get() == 1678 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1679} 1680 1681ALWAYS_INLINE static bool 1682CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1683 SDValue N, const TargetLowering &TLI) { 1684 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1685 if (cast<VTSDNode>(N)->getVT() == VT) 1686 return true; 1687 1688 // Handle the case when VT is iPTR. 1689 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1690} 1691 1692ALWAYS_INLINE static bool 1693CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1694 SDValue N) { 1695 int64_t Val = MatcherTable[MatcherIndex++]; 1696 if (Val & 128) 1697 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1698 1699 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1700 return C != 0 && C->getSExtValue() == Val; 1701} 1702 1703ALWAYS_INLINE static bool 1704CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1705 SDValue N, SelectionDAGISel &SDISel) { 1706 int64_t Val = MatcherTable[MatcherIndex++]; 1707 if (Val & 128) 1708 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1709 1710 if (N->getOpcode() != ISD::AND) return false; 1711 1712 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1713 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1714} 1715 1716ALWAYS_INLINE static bool 1717CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1718 SDValue N, SelectionDAGISel &SDISel) { 1719 int64_t Val = MatcherTable[MatcherIndex++]; 1720 if (Val & 128) 1721 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1722 1723 if (N->getOpcode() != ISD::OR) return false; 1724 1725 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1726 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1727} 1728 1729/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1730/// scope, evaluate the current node. If the current predicate is known to 1731/// fail, set Result=true and return anything. If the current predicate is 1732/// known to pass, set Result=false and return the MatcherIndex to continue 1733/// with. If the current predicate is unknown, set Result=false and return the 1734/// MatcherIndex to continue with. 1735static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1736 unsigned Index, SDValue N, 1737 bool &Result, SelectionDAGISel &SDISel, 1738 SmallVectorImpl<SDValue> &RecordedNodes){ 1739 switch (Table[Index++]) { 1740 default: 1741 Result = false; 1742 return Index-1; // Could not evaluate this predicate. 1743 case SelectionDAGISel::OPC_CheckSame: 1744 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1745 return Index; 1746 case SelectionDAGISel::OPC_CheckPatternPredicate: 1747 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1748 return Index; 1749 case SelectionDAGISel::OPC_CheckPredicate: 1750 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1751 return Index; 1752 case SelectionDAGISel::OPC_CheckOpcode: 1753 Result = !::CheckOpcode(Table, Index, N.getNode()); 1754 return Index; 1755 case SelectionDAGISel::OPC_CheckType: 1756 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1757 return Index; 1758 case SelectionDAGISel::OPC_CheckChild0Type: 1759 case SelectionDAGISel::OPC_CheckChild1Type: 1760 case SelectionDAGISel::OPC_CheckChild2Type: 1761 case SelectionDAGISel::OPC_CheckChild3Type: 1762 case SelectionDAGISel::OPC_CheckChild4Type: 1763 case SelectionDAGISel::OPC_CheckChild5Type: 1764 case SelectionDAGISel::OPC_CheckChild6Type: 1765 case SelectionDAGISel::OPC_CheckChild7Type: 1766 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1767 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1768 return Index; 1769 case SelectionDAGISel::OPC_CheckCondCode: 1770 Result = !::CheckCondCode(Table, Index, N); 1771 return Index; 1772 case SelectionDAGISel::OPC_CheckValueType: 1773 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1774 return Index; 1775 case SelectionDAGISel::OPC_CheckInteger: 1776 Result = !::CheckInteger(Table, Index, N); 1777 return Index; 1778 case SelectionDAGISel::OPC_CheckAndImm: 1779 Result = !::CheckAndImm(Table, Index, N, SDISel); 1780 return Index; 1781 case SelectionDAGISel::OPC_CheckOrImm: 1782 Result = !::CheckOrImm(Table, Index, N, SDISel); 1783 return Index; 1784 } 1785} 1786 1787namespace { 1788 1789struct MatchScope { 1790 /// FailIndex - If this match fails, this is the index to continue with. 1791 unsigned FailIndex; 1792 1793 /// NodeStack - The node stack when the scope was formed. 1794 SmallVector<SDValue, 4> NodeStack; 1795 1796 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1797 unsigned NumRecordedNodes; 1798 1799 /// NumMatchedMemRefs - The number of matched memref entries. 1800 unsigned NumMatchedMemRefs; 1801 1802 /// InputChain/InputFlag - The current chain/flag 1803 SDValue InputChain, InputFlag; 1804 1805 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1806 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1807}; 1808 1809} 1810 1811SDNode *SelectionDAGISel:: 1812SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1813 unsigned TableSize) { 1814 // FIXME: Should these even be selected? Handle these cases in the caller? 1815 switch (NodeToMatch->getOpcode()) { 1816 default: 1817 break; 1818 case ISD::EntryToken: // These nodes remain the same. 1819 case ISD::BasicBlock: 1820 case ISD::Register: 1821 //case ISD::VALUETYPE: 1822 //case ISD::CONDCODE: 1823 case ISD::HANDLENODE: 1824 case ISD::MDNODE_SDNODE: 1825 case ISD::TargetConstant: 1826 case ISD::TargetConstantFP: 1827 case ISD::TargetConstantPool: 1828 case ISD::TargetFrameIndex: 1829 case ISD::TargetExternalSymbol: 1830 case ISD::TargetBlockAddress: 1831 case ISD::TargetJumpTable: 1832 case ISD::TargetGlobalTLSAddress: 1833 case ISD::TargetGlobalAddress: 1834 case ISD::TokenFactor: 1835 case ISD::CopyFromReg: 1836 case ISD::CopyToReg: 1837 case ISD::EH_LABEL: 1838 NodeToMatch->setNodeId(-1); // Mark selected. 1839 return 0; 1840 case ISD::AssertSext: 1841 case ISD::AssertZext: 1842 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1843 NodeToMatch->getOperand(0)); 1844 return 0; 1845 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1846 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1847 } 1848 1849 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1850 1851 // Set up the node stack with NodeToMatch as the only node on the stack. 1852 SmallVector<SDValue, 8> NodeStack; 1853 SDValue N = SDValue(NodeToMatch, 0); 1854 NodeStack.push_back(N); 1855 1856 // MatchScopes - Scopes used when matching, if a match failure happens, this 1857 // indicates where to continue checking. 1858 SmallVector<MatchScope, 8> MatchScopes; 1859 1860 // RecordedNodes - This is the set of nodes that have been recorded by the 1861 // state machine. 1862 SmallVector<SDValue, 8> RecordedNodes; 1863 1864 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1865 // pattern. 1866 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1867 1868 // These are the current input chain and flag for use when generating nodes. 1869 // Various Emit operations change these. For example, emitting a copytoreg 1870 // uses and updates these. 1871 SDValue InputChain, InputFlag; 1872 1873 // ChainNodesMatched - If a pattern matches nodes that have input/output 1874 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1875 // which ones they are. The result is captured into this list so that we can 1876 // update the chain results when the pattern is complete. 1877 SmallVector<SDNode*, 3> ChainNodesMatched; 1878 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1879 1880 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1881 NodeToMatch->dump(CurDAG); 1882 errs() << '\n'); 1883 1884 // Determine where to start the interpreter. Normally we start at opcode #0, 1885 // but if the state machine starts with an OPC_SwitchOpcode, then we 1886 // accelerate the first lookup (which is guaranteed to be hot) with the 1887 // OpcodeOffset table. 1888 unsigned MatcherIndex = 0; 1889 1890 if (!OpcodeOffset.empty()) { 1891 // Already computed the OpcodeOffset table, just index into it. 1892 if (N.getOpcode() < OpcodeOffset.size()) 1893 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1894 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1895 1896 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1897 // Otherwise, the table isn't computed, but the state machine does start 1898 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1899 // is the first time we're selecting an instruction. 1900 unsigned Idx = 1; 1901 while (1) { 1902 // Get the size of this case. 1903 unsigned CaseSize = MatcherTable[Idx++]; 1904 if (CaseSize & 128) 1905 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1906 if (CaseSize == 0) break; 1907 1908 // Get the opcode, add the index to the table. 1909 uint16_t Opc = MatcherTable[Idx++]; 1910 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1911 if (Opc >= OpcodeOffset.size()) 1912 OpcodeOffset.resize((Opc+1)*2); 1913 OpcodeOffset[Opc] = Idx; 1914 Idx += CaseSize; 1915 } 1916 1917 // Okay, do the lookup for the first opcode. 1918 if (N.getOpcode() < OpcodeOffset.size()) 1919 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1920 } 1921 1922 while (1) { 1923 assert(MatcherIndex < TableSize && "Invalid index"); 1924#ifndef NDEBUG 1925 unsigned CurrentOpcodeIndex = MatcherIndex; 1926#endif 1927 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1928 switch (Opcode) { 1929 case OPC_Scope: { 1930 // Okay, the semantics of this operation are that we should push a scope 1931 // then evaluate the first child. However, pushing a scope only to have 1932 // the first check fail (which then pops it) is inefficient. If we can 1933 // determine immediately that the first check (or first several) will 1934 // immediately fail, don't even bother pushing a scope for them. 1935 unsigned FailIndex; 1936 1937 while (1) { 1938 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1939 if (NumToSkip & 128) 1940 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1941 // Found the end of the scope with no match. 1942 if (NumToSkip == 0) { 1943 FailIndex = 0; 1944 break; 1945 } 1946 1947 FailIndex = MatcherIndex+NumToSkip; 1948 1949 unsigned MatcherIndexOfPredicate = MatcherIndex; 1950 (void)MatcherIndexOfPredicate; // silence warning. 1951 1952 // If we can't evaluate this predicate without pushing a scope (e.g. if 1953 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1954 // push the scope and evaluate the full predicate chain. 1955 bool Result; 1956 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1957 Result, *this, RecordedNodes); 1958 if (!Result) 1959 break; 1960 1961 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1962 << "index " << MatcherIndexOfPredicate 1963 << ", continuing at " << FailIndex << "\n"); 1964 ++NumDAGIselRetries; 1965 1966 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1967 // move to the next case. 1968 MatcherIndex = FailIndex; 1969 } 1970 1971 // If the whole scope failed to match, bail. 1972 if (FailIndex == 0) break; 1973 1974 // Push a MatchScope which indicates where to go if the first child fails 1975 // to match. 1976 MatchScope NewEntry; 1977 NewEntry.FailIndex = FailIndex; 1978 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1979 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1980 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1981 NewEntry.InputChain = InputChain; 1982 NewEntry.InputFlag = InputFlag; 1983 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1984 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1985 MatchScopes.push_back(NewEntry); 1986 continue; 1987 } 1988 case OPC_RecordNode: 1989 // Remember this node, it may end up being an operand in the pattern. 1990 RecordedNodes.push_back(N); 1991 continue; 1992 1993 case OPC_RecordChild0: case OPC_RecordChild1: 1994 case OPC_RecordChild2: case OPC_RecordChild3: 1995 case OPC_RecordChild4: case OPC_RecordChild5: 1996 case OPC_RecordChild6: case OPC_RecordChild7: { 1997 unsigned ChildNo = Opcode-OPC_RecordChild0; 1998 if (ChildNo >= N.getNumOperands()) 1999 break; // Match fails if out of range child #. 2000 2001 RecordedNodes.push_back(N->getOperand(ChildNo)); 2002 continue; 2003 } 2004 case OPC_RecordMemRef: 2005 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2006 continue; 2007 2008 case OPC_CaptureFlagInput: 2009 // If the current node has an input flag, capture it in InputFlag. 2010 if (N->getNumOperands() != 0 && 2011 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2012 InputFlag = N->getOperand(N->getNumOperands()-1); 2013 continue; 2014 2015 case OPC_MoveChild: { 2016 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2017 if (ChildNo >= N.getNumOperands()) 2018 break; // Match fails if out of range child #. 2019 N = N.getOperand(ChildNo); 2020 NodeStack.push_back(N); 2021 continue; 2022 } 2023 2024 case OPC_MoveParent: 2025 // Pop the current node off the NodeStack. 2026 NodeStack.pop_back(); 2027 assert(!NodeStack.empty() && "Node stack imbalance!"); 2028 N = NodeStack.back(); 2029 continue; 2030 2031 case OPC_CheckSame: 2032 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2033 continue; 2034 case OPC_CheckPatternPredicate: 2035 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2036 continue; 2037 case OPC_CheckPredicate: 2038 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2039 N.getNode())) 2040 break; 2041 continue; 2042 case OPC_CheckComplexPat: { 2043 unsigned CPNum = MatcherTable[MatcherIndex++]; 2044 unsigned RecNo = MatcherTable[MatcherIndex++]; 2045 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2046 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2047 RecordedNodes)) 2048 break; 2049 continue; 2050 } 2051 case OPC_CheckOpcode: 2052 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2053 continue; 2054 2055 case OPC_CheckType: 2056 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2057 continue; 2058 2059 case OPC_SwitchOpcode: { 2060 unsigned CurNodeOpcode = N.getOpcode(); 2061 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2062 unsigned CaseSize; 2063 while (1) { 2064 // Get the size of this case. 2065 CaseSize = MatcherTable[MatcherIndex++]; 2066 if (CaseSize & 128) 2067 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2068 if (CaseSize == 0) break; 2069 2070 uint16_t Opc = MatcherTable[MatcherIndex++]; 2071 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2072 2073 // If the opcode matches, then we will execute this case. 2074 if (CurNodeOpcode == Opc) 2075 break; 2076 2077 // Otherwise, skip over this case. 2078 MatcherIndex += CaseSize; 2079 } 2080 2081 // If no cases matched, bail out. 2082 if (CaseSize == 0) break; 2083 2084 // Otherwise, execute the case we found. 2085 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2086 << " to " << MatcherIndex << "\n"); 2087 continue; 2088 } 2089 2090 case OPC_SwitchType: { 2091 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2092 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2093 unsigned CaseSize; 2094 while (1) { 2095 // Get the size of this case. 2096 CaseSize = MatcherTable[MatcherIndex++]; 2097 if (CaseSize & 128) 2098 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2099 if (CaseSize == 0) break; 2100 2101 MVT::SimpleValueType CaseVT = 2102 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2103 if (CaseVT == MVT::iPTR) 2104 CaseVT = TLI.getPointerTy().SimpleTy; 2105 2106 // If the VT matches, then we will execute this case. 2107 if (CurNodeVT == CaseVT) 2108 break; 2109 2110 // Otherwise, skip over this case. 2111 MatcherIndex += CaseSize; 2112 } 2113 2114 // If no cases matched, bail out. 2115 if (CaseSize == 0) break; 2116 2117 // Otherwise, execute the case we found. 2118 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2119 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2120 continue; 2121 } 2122 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2123 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2124 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2125 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2126 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2127 Opcode-OPC_CheckChild0Type)) 2128 break; 2129 continue; 2130 case OPC_CheckCondCode: 2131 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2132 continue; 2133 case OPC_CheckValueType: 2134 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2135 continue; 2136 case OPC_CheckInteger: 2137 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2138 continue; 2139 case OPC_CheckAndImm: 2140 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2141 continue; 2142 case OPC_CheckOrImm: 2143 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2144 continue; 2145 2146 case OPC_CheckFoldableChainNode: { 2147 assert(NodeStack.size() != 1 && "No parent node"); 2148 // Verify that all intermediate nodes between the root and this one have 2149 // a single use. 2150 bool HasMultipleUses = false; 2151 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2152 if (!NodeStack[i].hasOneUse()) { 2153 HasMultipleUses = true; 2154 break; 2155 } 2156 if (HasMultipleUses) break; 2157 2158 // Check to see that the target thinks this is profitable to fold and that 2159 // we can fold it without inducing cycles in the graph. 2160 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2161 NodeToMatch) || 2162 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2163 NodeToMatch, OptLevel, 2164 true/*We validate our own chains*/)) 2165 break; 2166 2167 continue; 2168 } 2169 case OPC_EmitInteger: { 2170 MVT::SimpleValueType VT = 2171 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2172 int64_t Val = MatcherTable[MatcherIndex++]; 2173 if (Val & 128) 2174 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2175 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2176 continue; 2177 } 2178 case OPC_EmitRegister: { 2179 MVT::SimpleValueType VT = 2180 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2181 unsigned RegNo = MatcherTable[MatcherIndex++]; 2182 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2183 continue; 2184 } 2185 2186 case OPC_EmitConvertToTarget: { 2187 // Convert from IMM/FPIMM to target version. 2188 unsigned RecNo = MatcherTable[MatcherIndex++]; 2189 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2190 SDValue Imm = RecordedNodes[RecNo]; 2191 2192 if (Imm->getOpcode() == ISD::Constant) { 2193 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2194 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2195 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2196 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2197 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2198 } 2199 2200 RecordedNodes.push_back(Imm); 2201 continue; 2202 } 2203 2204 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2205 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2206 // These are space-optimized forms of OPC_EmitMergeInputChains. 2207 assert(InputChain.getNode() == 0 && 2208 "EmitMergeInputChains should be the first chain producing node"); 2209 assert(ChainNodesMatched.empty() && 2210 "Should only have one EmitMergeInputChains per match"); 2211 2212 // Read all of the chained nodes. 2213 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2214 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2215 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2216 2217 // FIXME: What if other value results of the node have uses not matched 2218 // by this pattern? 2219 if (ChainNodesMatched.back() != NodeToMatch && 2220 !RecordedNodes[RecNo].hasOneUse()) { 2221 ChainNodesMatched.clear(); 2222 break; 2223 } 2224 2225 // Merge the input chains if they are not intra-pattern references. 2226 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2227 2228 if (InputChain.getNode() == 0) 2229 break; // Failed to merge. 2230 continue; 2231 } 2232 2233 case OPC_EmitMergeInputChains: { 2234 assert(InputChain.getNode() == 0 && 2235 "EmitMergeInputChains should be the first chain producing node"); 2236 // This node gets a list of nodes we matched in the input that have 2237 // chains. We want to token factor all of the input chains to these nodes 2238 // together. However, if any of the input chains is actually one of the 2239 // nodes matched in this pattern, then we have an intra-match reference. 2240 // Ignore these because the newly token factored chain should not refer to 2241 // the old nodes. 2242 unsigned NumChains = MatcherTable[MatcherIndex++]; 2243 assert(NumChains != 0 && "Can't TF zero chains"); 2244 2245 assert(ChainNodesMatched.empty() && 2246 "Should only have one EmitMergeInputChains per match"); 2247 2248 // Read all of the chained nodes. 2249 for (unsigned i = 0; i != NumChains; ++i) { 2250 unsigned RecNo = MatcherTable[MatcherIndex++]; 2251 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2252 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2253 2254 // FIXME: What if other value results of the node have uses not matched 2255 // by this pattern? 2256 if (ChainNodesMatched.back() != NodeToMatch && 2257 !RecordedNodes[RecNo].hasOneUse()) { 2258 ChainNodesMatched.clear(); 2259 break; 2260 } 2261 } 2262 2263 // If the inner loop broke out, the match fails. 2264 if (ChainNodesMatched.empty()) 2265 break; 2266 2267 // Merge the input chains if they are not intra-pattern references. 2268 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2269 2270 if (InputChain.getNode() == 0) 2271 break; // Failed to merge. 2272 2273 continue; 2274 } 2275 2276 case OPC_EmitCopyToReg: { 2277 unsigned RecNo = MatcherTable[MatcherIndex++]; 2278 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2279 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2280 2281 if (InputChain.getNode() == 0) 2282 InputChain = CurDAG->getEntryNode(); 2283 2284 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2285 DestPhysReg, RecordedNodes[RecNo], 2286 InputFlag); 2287 2288 InputFlag = InputChain.getValue(1); 2289 continue; 2290 } 2291 2292 case OPC_EmitNodeXForm: { 2293 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2294 unsigned RecNo = MatcherTable[MatcherIndex++]; 2295 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2296 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2297 continue; 2298 } 2299 2300 case OPC_EmitNode: 2301 case OPC_MorphNodeTo: { 2302 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2303 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2304 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2305 // Get the result VT list. 2306 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2307 SmallVector<EVT, 4> VTs; 2308 for (unsigned i = 0; i != NumVTs; ++i) { 2309 MVT::SimpleValueType VT = 2310 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2311 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2312 VTs.push_back(VT); 2313 } 2314 2315 if (EmitNodeInfo & OPFL_Chain) 2316 VTs.push_back(MVT::Other); 2317 if (EmitNodeInfo & OPFL_FlagOutput) 2318 VTs.push_back(MVT::Flag); 2319 2320 // This is hot code, so optimize the two most common cases of 1 and 2 2321 // results. 2322 SDVTList VTList; 2323 if (VTs.size() == 1) 2324 VTList = CurDAG->getVTList(VTs[0]); 2325 else if (VTs.size() == 2) 2326 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2327 else 2328 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2329 2330 // Get the operand list. 2331 unsigned NumOps = MatcherTable[MatcherIndex++]; 2332 SmallVector<SDValue, 8> Ops; 2333 for (unsigned i = 0; i != NumOps; ++i) { 2334 unsigned RecNo = MatcherTable[MatcherIndex++]; 2335 if (RecNo & 128) 2336 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2337 2338 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2339 Ops.push_back(RecordedNodes[RecNo]); 2340 } 2341 2342 // If there are variadic operands to add, handle them now. 2343 if (EmitNodeInfo & OPFL_VariadicInfo) { 2344 // Determine the start index to copy from. 2345 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2346 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2347 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2348 "Invalid variadic node"); 2349 // Copy all of the variadic operands, not including a potential flag 2350 // input. 2351 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2352 i != e; ++i) { 2353 SDValue V = NodeToMatch->getOperand(i); 2354 if (V.getValueType() == MVT::Flag) break; 2355 Ops.push_back(V); 2356 } 2357 } 2358 2359 // If this has chain/flag inputs, add them. 2360 if (EmitNodeInfo & OPFL_Chain) 2361 Ops.push_back(InputChain); 2362 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2363 Ops.push_back(InputFlag); 2364 2365 // Create the node. 2366 SDNode *Res = 0; 2367 if (Opcode != OPC_MorphNodeTo) { 2368 // If this is a normal EmitNode command, just create the new node and 2369 // add the results to the RecordedNodes list. 2370 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2371 VTList, Ops.data(), Ops.size()); 2372 2373 // Add all the non-flag/non-chain results to the RecordedNodes list. 2374 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2375 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2376 RecordedNodes.push_back(SDValue(Res, i)); 2377 } 2378 2379 } else { 2380 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2381 EmitNodeInfo); 2382 } 2383 2384 // If the node had chain/flag results, update our notion of the current 2385 // chain and flag. 2386 if (EmitNodeInfo & OPFL_FlagOutput) { 2387 InputFlag = SDValue(Res, VTs.size()-1); 2388 if (EmitNodeInfo & OPFL_Chain) 2389 InputChain = SDValue(Res, VTs.size()-2); 2390 } else if (EmitNodeInfo & OPFL_Chain) 2391 InputChain = SDValue(Res, VTs.size()-1); 2392 2393 // If the OPFL_MemRefs flag is set on this node, slap all of the 2394 // accumulated memrefs onto it. 2395 // 2396 // FIXME: This is vastly incorrect for patterns with multiple outputs 2397 // instructions that access memory and for ComplexPatterns that match 2398 // loads. 2399 if (EmitNodeInfo & OPFL_MemRefs) { 2400 MachineSDNode::mmo_iterator MemRefs = 2401 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2402 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2403 cast<MachineSDNode>(Res) 2404 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2405 } 2406 2407 DEBUG(errs() << " " 2408 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2409 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2410 2411 // If this was a MorphNodeTo then we're completely done! 2412 if (Opcode == OPC_MorphNodeTo) { 2413 // Update chain and flag uses. 2414 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2415 InputFlag, FlagResultNodesMatched, true); 2416 return Res; 2417 } 2418 2419 continue; 2420 } 2421 2422 case OPC_MarkFlagResults: { 2423 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2424 2425 // Read and remember all the flag-result nodes. 2426 for (unsigned i = 0; i != NumNodes; ++i) { 2427 unsigned RecNo = MatcherTable[MatcherIndex++]; 2428 if (RecNo & 128) 2429 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2430 2431 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2432 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2433 } 2434 continue; 2435 } 2436 2437 case OPC_CompleteMatch: { 2438 // The match has been completed, and any new nodes (if any) have been 2439 // created. Patch up references to the matched dag to use the newly 2440 // created nodes. 2441 unsigned NumResults = MatcherTable[MatcherIndex++]; 2442 2443 for (unsigned i = 0; i != NumResults; ++i) { 2444 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2445 if (ResSlot & 128) 2446 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2447 2448 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2449 SDValue Res = RecordedNodes[ResSlot]; 2450 2451 assert(i < NodeToMatch->getNumValues() && 2452 NodeToMatch->getValueType(i) != MVT::Other && 2453 NodeToMatch->getValueType(i) != MVT::Flag && 2454 "Invalid number of results to complete!"); 2455 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2456 NodeToMatch->getValueType(i) == MVT::iPTR || 2457 Res.getValueType() == MVT::iPTR || 2458 NodeToMatch->getValueType(i).getSizeInBits() == 2459 Res.getValueType().getSizeInBits()) && 2460 "invalid replacement"); 2461 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2462 } 2463 2464 // If the root node defines a flag, add it to the flag nodes to update 2465 // list. 2466 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2467 FlagResultNodesMatched.push_back(NodeToMatch); 2468 2469 // Update chain and flag uses. 2470 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2471 InputFlag, FlagResultNodesMatched, false); 2472 2473 assert(NodeToMatch->use_empty() && 2474 "Didn't replace all uses of the node?"); 2475 2476 // FIXME: We just return here, which interacts correctly with SelectRoot 2477 // above. We should fix this to not return an SDNode* anymore. 2478 return 0; 2479 } 2480 } 2481 2482 // If the code reached this point, then the match failed. See if there is 2483 // another child to try in the current 'Scope', otherwise pop it until we 2484 // find a case to check. 2485 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2486 ++NumDAGIselRetries; 2487 while (1) { 2488 if (MatchScopes.empty()) { 2489 CannotYetSelect(NodeToMatch); 2490 return 0; 2491 } 2492 2493 // Restore the interpreter state back to the point where the scope was 2494 // formed. 2495 MatchScope &LastScope = MatchScopes.back(); 2496 RecordedNodes.resize(LastScope.NumRecordedNodes); 2497 NodeStack.clear(); 2498 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2499 N = NodeStack.back(); 2500 2501 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2502 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2503 MatcherIndex = LastScope.FailIndex; 2504 2505 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2506 2507 InputChain = LastScope.InputChain; 2508 InputFlag = LastScope.InputFlag; 2509 if (!LastScope.HasChainNodesMatched) 2510 ChainNodesMatched.clear(); 2511 if (!LastScope.HasFlagResultNodesMatched) 2512 FlagResultNodesMatched.clear(); 2513 2514 // Check to see what the offset is at the new MatcherIndex. If it is zero 2515 // we have reached the end of this scope, otherwise we have another child 2516 // in the current scope to try. 2517 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2518 if (NumToSkip & 128) 2519 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2520 2521 // If we have another child in this scope to match, update FailIndex and 2522 // try it. 2523 if (NumToSkip != 0) { 2524 LastScope.FailIndex = MatcherIndex+NumToSkip; 2525 break; 2526 } 2527 2528 // End of this scope, pop it and try the next child in the containing 2529 // scope. 2530 MatchScopes.pop_back(); 2531 } 2532 } 2533} 2534 2535 2536 2537void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2538 std::string msg; 2539 raw_string_ostream Msg(msg); 2540 Msg << "Cannot yet select: "; 2541 2542 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2543 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2544 N->getOpcode() != ISD::INTRINSIC_VOID) { 2545 N->printrFull(Msg, CurDAG); 2546 } else { 2547 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2548 unsigned iid = 2549 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2550 if (iid < Intrinsic::num_intrinsics) 2551 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2552 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2553 Msg << "target intrinsic %" << TII->getName(iid); 2554 else 2555 Msg << "unknown intrinsic #" << iid; 2556 } 2557 report_fatal_error(Msg.str()); 2558} 2559 2560char SelectionDAGISel::ID = 0; 2561