SelectionDAGISel.cpp revision 90a0fe3bd6043f897285b967b196f6ab26dfdcae
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/Constants.h" 21#include "llvm/CallingConv.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/InlineAsm.h" 26#include "llvm/Instructions.h" 27#include "llvm/Intrinsics.h" 28#include "llvm/IntrinsicInst.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/FastISel.h" 31#include "llvm/CodeGen/GCStrategy.h" 32#include "llvm/CodeGen/GCMetadata.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineFunctionAnalysis.h" 35#include "llvm/CodeGen/MachineFrameInfo.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineJumpTableInfo.h" 38#include "llvm/CodeGen/MachineModuleInfo.h" 39#include "llvm/CodeGen/MachineRegisterInfo.h" 40#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 41#include "llvm/CodeGen/SchedulerRegistry.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/CodeGen/DwarfWriter.h" 44#include "llvm/Target/TargetRegisterInfo.h" 45#include "llvm/Target/TargetData.h" 46#include "llvm/Target/TargetFrameInfo.h" 47#include "llvm/Target/TargetIntrinsicInfo.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetLowering.h" 50#include "llvm/Target/TargetMachine.h" 51#include "llvm/Target/TargetOptions.h" 52#include "llvm/Support/Compiler.h" 53#include "llvm/Support/Debug.h" 54#include "llvm/Support/ErrorHandling.h" 55#include "llvm/Support/MathExtras.h" 56#include "llvm/Support/Timer.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61static cl::opt<bool> 62DisableLegalizeTypes("disable-legalize-types", cl::Hidden); 63static cl::opt<bool> 64EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 65 cl::desc("Enable verbose messages in the \"fast\" " 66 "instruction selector")); 67static cl::opt<bool> 68EnableFastISelAbort("fast-isel-abort", cl::Hidden, 69 cl::desc("Enable abort calls when \"fast\" instruction fails")); 70static cl::opt<bool> 71SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 72 cl::desc("Schedule copies of livein registers"), 73 cl::init(false)); 74 75#ifndef NDEBUG 76static cl::opt<bool> 77ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 78 cl::desc("Pop up a window to show dags before the first " 79 "dag combine pass")); 80static cl::opt<bool> 81ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 82 cl::desc("Pop up a window to show dags before legalize types")); 83static cl::opt<bool> 84ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 85 cl::desc("Pop up a window to show dags before legalize")); 86static cl::opt<bool> 87ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 88 cl::desc("Pop up a window to show dags before the second " 89 "dag combine pass")); 90static cl::opt<bool> 91ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 92 cl::desc("Pop up a window to show dags before the post legalize types" 93 " dag combine pass")); 94static cl::opt<bool> 95ViewISelDAGs("view-isel-dags", cl::Hidden, 96 cl::desc("Pop up a window to show isel dags as they are selected")); 97static cl::opt<bool> 98ViewSchedDAGs("view-sched-dags", cl::Hidden, 99 cl::desc("Pop up a window to show sched dags as they are processed")); 100static cl::opt<bool> 101ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 102 cl::desc("Pop up a window to show SUnit dags after they are processed")); 103#else 104static const bool ViewDAGCombine1 = false, 105 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 106 ViewDAGCombine2 = false, 107 ViewDAGCombineLT = false, 108 ViewISelDAGs = false, ViewSchedDAGs = false, 109 ViewSUnitDAGs = false; 110#endif 111 112//===---------------------------------------------------------------------===// 113/// 114/// RegisterScheduler class - Track the registration of instruction schedulers. 115/// 116//===---------------------------------------------------------------------===// 117MachinePassRegistry RegisterScheduler::Registry; 118 119//===---------------------------------------------------------------------===// 120/// 121/// ISHeuristic command line option for instruction schedulers. 122/// 123//===---------------------------------------------------------------------===// 124static cl::opt<RegisterScheduler::FunctionPassCtor, false, 125 RegisterPassParser<RegisterScheduler> > 126ISHeuristic("pre-RA-sched", 127 cl::init(&createDefaultScheduler), 128 cl::desc("Instruction schedulers available (before register" 129 " allocation):")); 130 131static RegisterScheduler 132defaultListDAGScheduler("default", "Best scheduler for the target", 133 createDefaultScheduler); 134 135namespace llvm { 136 //===--------------------------------------------------------------------===// 137 /// createDefaultScheduler - This creates an instruction scheduler appropriate 138 /// for the target. 139 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 140 CodeGenOpt::Level OptLevel) { 141 const TargetLowering &TLI = IS->getTargetLowering(); 142 143 if (OptLevel == CodeGenOpt::None) 144 return createFastDAGScheduler(IS, OptLevel); 145 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 146 return createTDListDAGScheduler(IS, OptLevel); 147 assert(TLI.getSchedulingPreference() == 148 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 149 return createBURRListDAGScheduler(IS, OptLevel); 150 } 151} 152 153// EmitInstrWithCustomInserter - This method should be implemented by targets 154// that mark instructions with the 'usesCustomInserter' flag. These 155// instructions are special in various ways, which require special support to 156// insert. The specified MachineInstr is created but not inserted into any 157// basic blocks, and this method is called to expand it into a sequence of 158// instructions, potentially also creating new basic blocks and control flow. 159// When new basic blocks are inserted and the edges from MBB to its successors 160// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 161// DenseMap. 162MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 163 MachineBasicBlock *MBB, 164 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 165#ifndef NDEBUG 166 errs() << "If a target marks an instruction with " 167 "'usesCustomInserter', it must implement " 168 "TargetLowering::EmitInstrWithCustomInserter!"; 169#endif 170 llvm_unreachable(0); 171 return 0; 172} 173 174/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 175/// physical register has only a single copy use, then coalesced the copy 176/// if possible. 177static void EmitLiveInCopy(MachineBasicBlock *MBB, 178 MachineBasicBlock::iterator &InsertPos, 179 unsigned VirtReg, unsigned PhysReg, 180 const TargetRegisterClass *RC, 181 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 182 const MachineRegisterInfo &MRI, 183 const TargetRegisterInfo &TRI, 184 const TargetInstrInfo &TII) { 185 unsigned NumUses = 0; 186 MachineInstr *UseMI = NULL; 187 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 188 UE = MRI.use_end(); UI != UE; ++UI) { 189 UseMI = &*UI; 190 if (++NumUses > 1) 191 break; 192 } 193 194 // If the number of uses is not one, or the use is not a move instruction, 195 // don't coalesce. Also, only coalesce away a virtual register to virtual 196 // register copy. 197 bool Coalesced = false; 198 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 199 if (NumUses == 1 && 200 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 201 TargetRegisterInfo::isVirtualRegister(DstReg)) { 202 VirtReg = DstReg; 203 Coalesced = true; 204 } 205 206 // Now find an ideal location to insert the copy. 207 MachineBasicBlock::iterator Pos = InsertPos; 208 while (Pos != MBB->begin()) { 209 MachineInstr *PrevMI = prior(Pos); 210 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 211 // copyRegToReg might emit multiple instructions to do a copy. 212 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 213 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 214 // This is what the BB looks like right now: 215 // r1024 = mov r0 216 // ... 217 // r1 = mov r1024 218 // 219 // We want to insert "r1025 = mov r1". Inserting this copy below the 220 // move to r1024 makes it impossible for that move to be coalesced. 221 // 222 // r1025 = mov r1 223 // r1024 = mov r0 224 // ... 225 // r1 = mov 1024 226 // r2 = mov 1025 227 break; // Woot! Found a good location. 228 --Pos; 229 } 230 231 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 232 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 233 (void) Emitted; 234 235 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 236 if (Coalesced) { 237 if (&*InsertPos == UseMI) ++InsertPos; 238 MBB->erase(UseMI); 239 } 240} 241 242/// EmitLiveInCopies - If this is the first basic block in the function, 243/// and if it has live ins that need to be copied into vregs, emit the 244/// copies into the block. 245static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 246 const MachineRegisterInfo &MRI, 247 const TargetRegisterInfo &TRI, 248 const TargetInstrInfo &TII) { 249 if (SchedLiveInCopies) { 250 // Emit the copies at a heuristically-determined location in the block. 251 DenseMap<MachineInstr*, unsigned> CopyRegMap; 252 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 253 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 254 E = MRI.livein_end(); LI != E; ++LI) 255 if (LI->second) { 256 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 257 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 258 RC, CopyRegMap, MRI, TRI, TII); 259 } 260 } else { 261 // Emit the copies into the top of the block. 262 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 263 E = MRI.livein_end(); LI != E; ++LI) 264 if (LI->second) { 265 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 266 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 267 LI->second, LI->first, RC, RC); 268 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 269 (void) Emitted; 270 } 271 } 272} 273 274//===----------------------------------------------------------------------===// 275// SelectionDAGISel code 276//===----------------------------------------------------------------------===// 277 278SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 279 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 280 FuncInfo(new FunctionLoweringInfo(TLI)), 281 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 282 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)), 283 GFI(), 284 OptLevel(OL), 285 DAGSize(0) 286{} 287 288SelectionDAGISel::~SelectionDAGISel() { 289 delete SDL; 290 delete CurDAG; 291 delete FuncInfo; 292} 293 294unsigned SelectionDAGISel::MakeReg(EVT VT) { 295 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 296} 297 298void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 299 AU.addRequired<AliasAnalysis>(); 300 AU.addPreserved<AliasAnalysis>(); 301 AU.addRequired<GCModuleInfo>(); 302 AU.addPreserved<GCModuleInfo>(); 303 AU.addRequired<DwarfWriter>(); 304 AU.addPreserved<DwarfWriter>(); 305 MachineFunctionPass::getAnalysisUsage(AU); 306} 307 308bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 309 Function &Fn = *mf.getFunction(); 310 311 // Do some sanity-checking on the command-line options. 312 assert((!EnableFastISelVerbose || EnableFastISel) && 313 "-fast-isel-verbose requires -fast-isel"); 314 assert((!EnableFastISelAbort || EnableFastISel) && 315 "-fast-isel-abort requires -fast-isel"); 316 317 // Get alias analysis for load/store combining. 318 AA = &getAnalysis<AliasAnalysis>(); 319 320 MF = &mf; 321 const TargetInstrInfo &TII = *TM.getInstrInfo(); 322 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 323 324 if (Fn.hasGC()) 325 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 326 else 327 GFI = 0; 328 RegInfo = &MF->getRegInfo(); 329 DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n"); 330 331 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 332 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 333 CurDAG->init(*MF, MMI, DW); 334 FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); 335 SDL->init(GFI, *AA); 336 337 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 338 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 339 // Mark landing pad. 340 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 341 342 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 343 344 // If the first basic block in the function has live ins that need to be 345 // copied into vregs, emit the copies into the top of the block before 346 // emitting the code for the block. 347 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 348 349 // Add function live-ins to entry block live-in set. 350 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 351 E = RegInfo->livein_end(); I != E; ++I) 352 MF->begin()->addLiveIn(I->first); 353 354#ifndef NDEBUG 355 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 356 "Not all catch info was assigned to a landing pad!"); 357#endif 358 359 FuncInfo->clear(); 360 361 return true; 362} 363 364static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 365 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 366 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 367 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 368 // Apply the catch info to DestBB. 369 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 370#ifndef NDEBUG 371 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 372 FLI.CatchInfoFound.insert(EHSel); 373#endif 374 } 375} 376 377void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 378 BasicBlock::iterator Begin, 379 BasicBlock::iterator End) { 380 SDL->setCurrentBasicBlock(BB); 381 MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); 382 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 383 384 // Lower all of the non-terminator instructions. If a call is emitted 385 // as a tail call, cease emitting nodes for this block. 386 for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) { 387 if (MDDbgKind) { 388 // Update DebugLoc if debug information is attached with this 389 // instruction. 390 if (!isa<DbgInfoIntrinsic>(I)) 391 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) { 392 DILocation DILoc(Dbg); 393 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 394 SDL->setCurDebugLoc(Loc); 395 if (MF->getDefaultDebugLoc().isUnknown()) 396 MF->setDefaultDebugLoc(Loc); 397 } 398 } 399 if (!isa<TerminatorInst>(I)) 400 SDL->visit(*I); 401 } 402 403 if (!SDL->HasTailCall) { 404 // Ensure that all instructions which are used outside of their defining 405 // blocks are available as virtual registers. Invoke is handled elsewhere. 406 for (BasicBlock::iterator I = Begin; I != End; ++I) 407 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 408 SDL->CopyToExportRegsIfNeeded(I); 409 410 // Handle PHI nodes in successor blocks. 411 if (End == LLVMBB->end()) { 412 HandlePHINodesInSuccessorBlocks(LLVMBB); 413 414 // Lower the terminator after the copies are emitted. 415 SDL->visit(*LLVMBB->getTerminator()); 416 } 417 } 418 419 // Make sure the root of the DAG is up-to-date. 420 CurDAG->setRoot(SDL->getControlRoot()); 421 422 // Final step, emit the lowered DAG as machine code. 423 CodeGenAndEmitDAG(); 424 SDL->clear(); 425} 426 427void SelectionDAGISel::ComputeLiveOutVRegInfo() { 428 SmallPtrSet<SDNode*, 128> VisitedNodes; 429 SmallVector<SDNode*, 128> Worklist; 430 431 Worklist.push_back(CurDAG->getRoot().getNode()); 432 433 APInt Mask; 434 APInt KnownZero; 435 APInt KnownOne; 436 437 while (!Worklist.empty()) { 438 SDNode *N = Worklist.back(); 439 Worklist.pop_back(); 440 441 // If we've already seen this node, ignore it. 442 if (!VisitedNodes.insert(N)) 443 continue; 444 445 // Otherwise, add all chain operands to the worklist. 446 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 447 if (N->getOperand(i).getValueType() == MVT::Other) 448 Worklist.push_back(N->getOperand(i).getNode()); 449 450 // If this is a CopyToReg with a vreg dest, process it. 451 if (N->getOpcode() != ISD::CopyToReg) 452 continue; 453 454 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 455 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 456 continue; 457 458 // Ignore non-scalar or non-integer values. 459 SDValue Src = N->getOperand(2); 460 EVT SrcVT = Src.getValueType(); 461 if (!SrcVT.isInteger() || SrcVT.isVector()) 462 continue; 463 464 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 465 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 466 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 467 468 // Only install this information if it tells us something. 469 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 470 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 471 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 472 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 473 FunctionLoweringInfo::LiveOutInfo &LOI = 474 FuncInfo->LiveOutRegInfo[DestReg]; 475 LOI.NumSignBits = NumSignBits; 476 LOI.KnownOne = KnownOne; 477 LOI.KnownZero = KnownZero; 478 } 479 } 480} 481 482void SelectionDAGISel::CodeGenAndEmitDAG() { 483 std::string GroupName; 484 if (TimePassesIsEnabled) 485 GroupName = "Instruction Selection and Scheduling"; 486 std::string BlockName; 487 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 488 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 489 ViewSUnitDAGs) 490 BlockName = MF->getFunction()->getNameStr() + ":" + 491 BB->getBasicBlock()->getNameStr(); 492 493 DEBUG(errs() << "Initial selection DAG:\n"); 494 DEBUG(CurDAG->dump()); 495 496 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 497 498 // Run the DAG combiner in pre-legalize mode. 499 if (TimePassesIsEnabled) { 500 NamedRegionTimer T("DAG Combining 1", GroupName); 501 CurDAG->Combine(Unrestricted, *AA, OptLevel); 502 } else { 503 CurDAG->Combine(Unrestricted, *AA, OptLevel); 504 } 505 506 DEBUG(errs() << "Optimized lowered selection DAG:\n"); 507 DEBUG(CurDAG->dump()); 508 509 // Second step, hack on the DAG until it only uses operations and types that 510 // the target supports. 511 if (!DisableLegalizeTypes) { 512 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 513 BlockName); 514 515 bool Changed; 516 if (TimePassesIsEnabled) { 517 NamedRegionTimer T("Type Legalization", GroupName); 518 Changed = CurDAG->LegalizeTypes(); 519 } else { 520 Changed = CurDAG->LegalizeTypes(); 521 } 522 523 DEBUG(errs() << "Type-legalized selection DAG:\n"); 524 DEBUG(CurDAG->dump()); 525 526 if (Changed) { 527 if (ViewDAGCombineLT) 528 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 529 530 // Run the DAG combiner in post-type-legalize mode. 531 if (TimePassesIsEnabled) { 532 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 533 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 534 } else { 535 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 536 } 537 538 DEBUG(errs() << "Optimized type-legalized selection DAG:\n"); 539 DEBUG(CurDAG->dump()); 540 } 541 542 if (TimePassesIsEnabled) { 543 NamedRegionTimer T("Vector Legalization", GroupName); 544 Changed = CurDAG->LegalizeVectors(); 545 } else { 546 Changed = CurDAG->LegalizeVectors(); 547 } 548 549 if (Changed) { 550 if (TimePassesIsEnabled) { 551 NamedRegionTimer T("Type Legalization 2", GroupName); 552 Changed = CurDAG->LegalizeTypes(); 553 } else { 554 Changed = CurDAG->LegalizeTypes(); 555 } 556 557 if (ViewDAGCombineLT) 558 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 559 560 // Run the DAG combiner in post-type-legalize mode. 561 if (TimePassesIsEnabled) { 562 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 563 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 564 } else { 565 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 566 } 567 568 DEBUG(errs() << "Optimized vector-legalized selection DAG:\n"); 569 DEBUG(CurDAG->dump()); 570 } 571 } 572 573 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 574 575 if (TimePassesIsEnabled) { 576 NamedRegionTimer T("DAG Legalization", GroupName); 577 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 578 } else { 579 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 580 } 581 582 DEBUG(errs() << "Legalized selection DAG:\n"); 583 DEBUG(CurDAG->dump()); 584 585 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 586 587 // Run the DAG combiner in post-legalize mode. 588 if (TimePassesIsEnabled) { 589 NamedRegionTimer T("DAG Combining 2", GroupName); 590 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 591 } else { 592 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 593 } 594 595 DEBUG(errs() << "Optimized legalized selection DAG:\n"); 596 DEBUG(CurDAG->dump()); 597 598 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 599 600 if (OptLevel != CodeGenOpt::None) 601 ComputeLiveOutVRegInfo(); 602 603 // Third, instruction select all of the operations to machine code, adding the 604 // code to the MachineBasicBlock. 605 if (TimePassesIsEnabled) { 606 NamedRegionTimer T("Instruction Selection", GroupName); 607 InstructionSelect(); 608 } else { 609 InstructionSelect(); 610 } 611 612 DEBUG(errs() << "Selected selection DAG:\n"); 613 DEBUG(CurDAG->dump()); 614 615 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 616 617 // Schedule machine code. 618 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 619 if (TimePassesIsEnabled) { 620 NamedRegionTimer T("Instruction Scheduling", GroupName); 621 Scheduler->Run(CurDAG, BB, BB->end()); 622 } else { 623 Scheduler->Run(CurDAG, BB, BB->end()); 624 } 625 626 if (ViewSUnitDAGs) Scheduler->viewGraph(); 627 628 // Emit machine code to BB. This can change 'BB' to the last block being 629 // inserted into. 630 if (TimePassesIsEnabled) { 631 NamedRegionTimer T("Instruction Creation", GroupName); 632 BB = Scheduler->EmitSchedule(&SDL->EdgeMapping); 633 } else { 634 BB = Scheduler->EmitSchedule(&SDL->EdgeMapping); 635 } 636 637 // Free the scheduler state. 638 if (TimePassesIsEnabled) { 639 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 640 delete Scheduler; 641 } else { 642 delete Scheduler; 643 } 644 645 DEBUG(errs() << "Selected machine code:\n"); 646 DEBUG(BB->dump()); 647} 648 649void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 650 MachineFunction &MF, 651 MachineModuleInfo *MMI, 652 DwarfWriter *DW, 653 const TargetInstrInfo &TII) { 654 // Initialize the Fast-ISel state, if needed. 655 FastISel *FastIS = 0; 656 if (EnableFastISel) 657 FastIS = TLI.createFastISel(MF, MMI, DW, 658 FuncInfo->ValueMap, 659 FuncInfo->MBBMap, 660 FuncInfo->StaticAllocaMap 661#ifndef NDEBUG 662 , FuncInfo->CatchInfoLost 663#endif 664 ); 665 666 MetadataContext &TheMetadata = Fn.getContext().getMetadata(); 667 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 668 669 // Iterate over all basic blocks in the function. 670 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 671 BasicBlock *LLVMBB = &*I; 672 BB = FuncInfo->MBBMap[LLVMBB]; 673 674 BasicBlock::iterator const Begin = LLVMBB->begin(); 675 BasicBlock::iterator const End = LLVMBB->end(); 676 BasicBlock::iterator BI = Begin; 677 678 // Lower any arguments needed in this block if this is the entry block. 679 bool SuppressFastISel = false; 680 if (LLVMBB == &Fn.getEntryBlock()) { 681 LowerArguments(LLVMBB); 682 683 // If any of the arguments has the byval attribute, forgo 684 // fast-isel in the entry block. 685 if (FastIS) { 686 unsigned j = 1; 687 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 688 I != E; ++I, ++j) 689 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 690 if (EnableFastISelVerbose || EnableFastISelAbort) 691 errs() << "FastISel skips entry block due to byval argument\n"; 692 SuppressFastISel = true; 693 break; 694 } 695 } 696 } 697 698 if (MMI && BB->isLandingPad()) { 699 // Add a label to mark the beginning of the landing pad. Deletion of the 700 // landing pad can thus be detected via the MachineModuleInfo. 701 unsigned LabelID = MMI->addLandingPad(BB); 702 703 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 704 BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID); 705 706 // Mark exception register as live in. 707 unsigned Reg = TLI.getExceptionAddressRegister(); 708 if (Reg) BB->addLiveIn(Reg); 709 710 // Mark exception selector register as live in. 711 Reg = TLI.getExceptionSelectorRegister(); 712 if (Reg) BB->addLiveIn(Reg); 713 714 // FIXME: Hack around an exception handling flaw (PR1508): the personality 715 // function and list of typeids logically belong to the invoke (or, if you 716 // like, the basic block containing the invoke), and need to be associated 717 // with it in the dwarf exception handling tables. Currently however the 718 // information is provided by an intrinsic (eh.selector) that can be moved 719 // to unexpected places by the optimizers: if the unwind edge is critical, 720 // then breaking it can result in the intrinsics being in the successor of 721 // the landing pad, not the landing pad itself. This results in exceptions 722 // not being caught because no typeids are associated with the invoke. 723 // This may not be the only way things can go wrong, but it is the only way 724 // we try to work around for the moment. 725 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 726 727 if (Br && Br->isUnconditional()) { // Critical edge? 728 BasicBlock::iterator I, E; 729 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 730 if (isa<EHSelectorInst>(I)) 731 break; 732 733 if (I == E) 734 // No catch info found - try to extract some from the successor. 735 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 736 } 737 } 738 739 // Before doing SelectionDAG ISel, see if FastISel has been requested. 740 if (FastIS && !SuppressFastISel) { 741 // Emit code for any incoming arguments. This must happen before 742 // beginning FastISel on the entry block. 743 if (LLVMBB == &Fn.getEntryBlock()) { 744 CurDAG->setRoot(SDL->getControlRoot()); 745 CodeGenAndEmitDAG(); 746 SDL->clear(); 747 } 748 FastIS->startNewBlock(BB); 749 // Do FastISel on as many instructions as possible. 750 for (; BI != End; ++BI) { 751 if (MDDbgKind) { 752 // Update DebugLoc if debug information is attached with this 753 // instruction. 754 if (!isa<DbgInfoIntrinsic>(BI)) 755 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, BI)) { 756 DILocation DILoc(Dbg); 757 DebugLoc Loc = ExtractDebugLocation(DILoc, 758 MF.getDebugLocInfo()); 759 FastIS->setCurDebugLoc(Loc); 760 if (MF.getDefaultDebugLoc().isUnknown()) 761 MF.setDefaultDebugLoc(Loc); 762 } 763 } 764 765 // Just before the terminator instruction, insert instructions to 766 // feed PHI nodes in successor blocks. 767 if (isa<TerminatorInst>(BI)) 768 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 769 if (EnableFastISelVerbose || EnableFastISelAbort) { 770 errs() << "FastISel miss: "; 771 BI->dump(); 772 } 773 assert(!EnableFastISelAbort && 774 "FastISel didn't handle a PHI in a successor"); 775 break; 776 } 777 778 // First try normal tablegen-generated "fast" selection. 779 if (FastIS->SelectInstruction(BI)) 780 continue; 781 782 // Next, try calling the target to attempt to handle the instruction. 783 if (FastIS->TargetSelectInstruction(BI)) 784 continue; 785 786 // Then handle certain instructions as single-LLVM-Instruction blocks. 787 if (isa<CallInst>(BI)) { 788 if (EnableFastISelVerbose || EnableFastISelAbort) { 789 errs() << "FastISel missed call: "; 790 BI->dump(); 791 } 792 793 if (BI->getType() != Type::getVoidTy(*CurDAG->getContext())) { 794 unsigned &R = FuncInfo->ValueMap[BI]; 795 if (!R) 796 R = FuncInfo->CreateRegForValue(BI); 797 } 798 799 SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); 800 SelectBasicBlock(LLVMBB, BI, next(BI)); 801 // If the instruction was codegen'd with multiple blocks, 802 // inform the FastISel object where to resume inserting. 803 FastIS->setCurrentBlock(BB); 804 continue; 805 } 806 807 // Otherwise, give up on FastISel for the rest of the block. 808 // For now, be a little lenient about non-branch terminators. 809 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 810 if (EnableFastISelVerbose || EnableFastISelAbort) { 811 errs() << "FastISel miss: "; 812 BI->dump(); 813 } 814 if (EnableFastISelAbort) 815 // The "fast" selector couldn't handle something and bailed. 816 // For the purpose of debugging, just abort. 817 llvm_unreachable("FastISel didn't select the entire block"); 818 } 819 break; 820 } 821 } 822 823 // Run SelectionDAG instruction selection on the remainder of the block 824 // not handled by FastISel. If FastISel is not run, this is the entire 825 // block. 826 if (BI != End) { 827 // If FastISel is run and it has known DebugLoc then use it. 828 if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) 829 SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); 830 SelectBasicBlock(LLVMBB, BI, End); 831 } 832 833 FinishBasicBlock(); 834 } 835 836 delete FastIS; 837} 838 839void 840SelectionDAGISel::FinishBasicBlock() { 841 842 DEBUG(errs() << "Target-post-processed machine code:\n"); 843 DEBUG(BB->dump()); 844 845 DEBUG(errs() << "Total amount of phi nodes to update: " 846 << SDL->PHINodesToUpdate.size() << "\n"); 847 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 848 errs() << "Node " << i << " : (" 849 << SDL->PHINodesToUpdate[i].first 850 << ", " << SDL->PHINodesToUpdate[i].second << ")\n"); 851 852 // Next, now that we know what the last MBB the LLVM BB expanded is, update 853 // PHI nodes in successors. 854 if (SDL->SwitchCases.empty() && 855 SDL->JTCases.empty() && 856 SDL->BitTestCases.empty()) { 857 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 858 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 859 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 860 "This is not a machine PHI node that we are updating!"); 861 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 862 false)); 863 PHI->addOperand(MachineOperand::CreateMBB(BB)); 864 } 865 SDL->PHINodesToUpdate.clear(); 866 return; 867 } 868 869 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 870 // Lower header first, if it wasn't already lowered 871 if (!SDL->BitTestCases[i].Emitted) { 872 // Set the current basic block to the mbb we wish to insert the code into 873 BB = SDL->BitTestCases[i].Parent; 874 SDL->setCurrentBasicBlock(BB); 875 // Emit the code 876 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 877 CurDAG->setRoot(SDL->getRoot()); 878 CodeGenAndEmitDAG(); 879 SDL->clear(); 880 } 881 882 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 883 // Set the current basic block to the mbb we wish to insert the code into 884 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 885 SDL->setCurrentBasicBlock(BB); 886 // Emit the code 887 if (j+1 != ej) 888 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 889 SDL->BitTestCases[i].Reg, 890 SDL->BitTestCases[i].Cases[j]); 891 else 892 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 893 SDL->BitTestCases[i].Reg, 894 SDL->BitTestCases[i].Cases[j]); 895 896 897 CurDAG->setRoot(SDL->getRoot()); 898 CodeGenAndEmitDAG(); 899 SDL->clear(); 900 } 901 902 // Update PHI Nodes 903 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 904 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 905 MachineBasicBlock *PHIBB = PHI->getParent(); 906 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 907 "This is not a machine PHI node that we are updating!"); 908 // This is "default" BB. We have two jumps to it. From "header" BB and 909 // from last "case" BB. 910 if (PHIBB == SDL->BitTestCases[i].Default) { 911 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 912 false)); 913 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 914 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 915 false)); 916 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 917 back().ThisBB)); 918 } 919 // One of "cases" BB. 920 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 921 j != ej; ++j) { 922 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 923 if (cBB->succ_end() != 924 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 925 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 926 false)); 927 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 928 } 929 } 930 } 931 } 932 SDL->BitTestCases.clear(); 933 934 // If the JumpTable record is filled in, then we need to emit a jump table. 935 // Updating the PHI nodes is tricky in this case, since we need to determine 936 // whether the PHI is a successor of the range check MBB or the jump table MBB 937 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 938 // Lower header first, if it wasn't already lowered 939 if (!SDL->JTCases[i].first.Emitted) { 940 // Set the current basic block to the mbb we wish to insert the code into 941 BB = SDL->JTCases[i].first.HeaderBB; 942 SDL->setCurrentBasicBlock(BB); 943 // Emit the code 944 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 945 CurDAG->setRoot(SDL->getRoot()); 946 CodeGenAndEmitDAG(); 947 SDL->clear(); 948 } 949 950 // Set the current basic block to the mbb we wish to insert the code into 951 BB = SDL->JTCases[i].second.MBB; 952 SDL->setCurrentBasicBlock(BB); 953 // Emit the code 954 SDL->visitJumpTable(SDL->JTCases[i].second); 955 CurDAG->setRoot(SDL->getRoot()); 956 CodeGenAndEmitDAG(); 957 SDL->clear(); 958 959 // Update PHI Nodes 960 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 961 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 962 MachineBasicBlock *PHIBB = PHI->getParent(); 963 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 964 "This is not a machine PHI node that we are updating!"); 965 // "default" BB. We can go there only from header BB. 966 if (PHIBB == SDL->JTCases[i].second.Default) { 967 PHI->addOperand 968 (MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false)); 969 PHI->addOperand 970 (MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 971 } 972 // JT BB. Just iterate over successors here 973 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 974 PHI->addOperand 975 (MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false)); 976 PHI->addOperand(MachineOperand::CreateMBB(BB)); 977 } 978 } 979 } 980 SDL->JTCases.clear(); 981 982 // If the switch block involved a branch to one of the actual successors, we 983 // need to update PHI nodes in that block. 984 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 985 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 986 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 987 "This is not a machine PHI node that we are updating!"); 988 if (BB->isSuccessor(PHI->getParent())) { 989 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 990 false)); 991 PHI->addOperand(MachineOperand::CreateMBB(BB)); 992 } 993 } 994 995 // If we generated any switch lowering information, build and codegen any 996 // additional DAGs necessary. 997 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 998 // Set the current basic block to the mbb we wish to insert the code into 999 MachineBasicBlock *ThisBB = BB = SDL->SwitchCases[i].ThisBB; 1000 SDL->setCurrentBasicBlock(BB); 1001 1002 // Emit the code 1003 SDL->visitSwitchCase(SDL->SwitchCases[i]); 1004 CurDAG->setRoot(SDL->getRoot()); 1005 CodeGenAndEmitDAG(); 1006 1007 // Handle any PHI nodes in successors of this chunk, as if we were coming 1008 // from the original BB before switch expansion. Note that PHI nodes can 1009 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1010 // handle them the right number of times. 1011 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1012 // If new BB's are created during scheduling, the edges may have been 1013 // updated. That is, the edge from ThisBB to BB may have been split and 1014 // BB's predecessor is now another block. 1015 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1016 SDL->EdgeMapping.find(BB); 1017 if (EI != SDL->EdgeMapping.end()) 1018 ThisBB = EI->second; 1019 for (MachineBasicBlock::iterator Phi = BB->begin(); 1020 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 1021 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 1022 for (unsigned pn = 0; ; ++pn) { 1023 assert(pn != SDL->PHINodesToUpdate.size() && 1024 "Didn't find PHI entry!"); 1025 if (SDL->PHINodesToUpdate[pn].first == Phi) { 1026 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 1027 second, false)); 1028 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1029 break; 1030 } 1031 } 1032 } 1033 1034 // Don't process RHS if same block as LHS. 1035 if (BB == SDL->SwitchCases[i].FalseBB) 1036 SDL->SwitchCases[i].FalseBB = 0; 1037 1038 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1039 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 1040 SDL->SwitchCases[i].FalseBB = 0; 1041 } 1042 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 1043 SDL->clear(); 1044 } 1045 SDL->SwitchCases.clear(); 1046 1047 SDL->PHINodesToUpdate.clear(); 1048} 1049 1050 1051/// Create the scheduler. If a specific scheduler was specified 1052/// via the SchedulerRegistry, use it, otherwise select the 1053/// one preferred by the target. 1054/// 1055ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1056 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1057 1058 if (!Ctor) { 1059 Ctor = ISHeuristic; 1060 RegisterScheduler::setDefault(Ctor); 1061 } 1062 1063 return Ctor(this, OptLevel); 1064} 1065 1066ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1067 return new ScheduleHazardRecognizer(); 1068} 1069 1070//===----------------------------------------------------------------------===// 1071// Helper functions used by the generated instruction selector. 1072//===----------------------------------------------------------------------===// 1073// Calls to these methods are generated by tblgen. 1074 1075/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1076/// the dag combiner simplified the 255, we still want to match. RHS is the 1077/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1078/// specified in the .td file (e.g. 255). 1079bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1080 int64_t DesiredMaskS) const { 1081 const APInt &ActualMask = RHS->getAPIntValue(); 1082 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1083 1084 // If the actual mask exactly matches, success! 1085 if (ActualMask == DesiredMask) 1086 return true; 1087 1088 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1089 if (ActualMask.intersects(~DesiredMask)) 1090 return false; 1091 1092 // Otherwise, the DAG Combiner may have proven that the value coming in is 1093 // either already zero or is not demanded. Check for known zero input bits. 1094 APInt NeededMask = DesiredMask & ~ActualMask; 1095 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1096 return true; 1097 1098 // TODO: check to see if missing bits are just not demanded. 1099 1100 // Otherwise, this pattern doesn't match. 1101 return false; 1102} 1103 1104/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1105/// the dag combiner simplified the 255, we still want to match. RHS is the 1106/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1107/// specified in the .td file (e.g. 255). 1108bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1109 int64_t DesiredMaskS) const { 1110 const APInt &ActualMask = RHS->getAPIntValue(); 1111 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1112 1113 // If the actual mask exactly matches, success! 1114 if (ActualMask == DesiredMask) 1115 return true; 1116 1117 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1118 if (ActualMask.intersects(~DesiredMask)) 1119 return false; 1120 1121 // Otherwise, the DAG Combiner may have proven that the value coming in is 1122 // either already zero or is not demanded. Check for known zero input bits. 1123 APInt NeededMask = DesiredMask & ~ActualMask; 1124 1125 APInt KnownZero, KnownOne; 1126 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1127 1128 // If all the missing bits in the or are already known to be set, match! 1129 if ((NeededMask & KnownOne) == NeededMask) 1130 return true; 1131 1132 // TODO: check to see if missing bits are just not demanded. 1133 1134 // Otherwise, this pattern doesn't match. 1135 return false; 1136} 1137 1138 1139/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1140/// by tblgen. Others should not call it. 1141void SelectionDAGISel:: 1142SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1143 std::vector<SDValue> InOps; 1144 std::swap(InOps, Ops); 1145 1146 Ops.push_back(InOps[0]); // input chain. 1147 Ops.push_back(InOps[1]); // input asm string. 1148 1149 unsigned i = 2, e = InOps.size(); 1150 if (InOps[e-1].getValueType() == MVT::Flag) 1151 --e; // Don't process a flag operand if it is here. 1152 1153 while (i != e) { 1154 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1155 if ((Flags & 7) != 4 /*MEM*/) { 1156 // Just skip over this operand, copying the operands verbatim. 1157 Ops.insert(Ops.end(), InOps.begin()+i, 1158 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1159 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1160 } else { 1161 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1162 "Memory operand with multiple values?"); 1163 // Otherwise, this is a memory operand. Ask the target to select it. 1164 std::vector<SDValue> SelOps; 1165 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1166 llvm_report_error("Could not match memory address. Inline asm" 1167 " failure!"); 1168 } 1169 1170 // Add this to the output node. 1171 EVT IntPtrTy = TLI.getPointerTy(); 1172 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1173 IntPtrTy)); 1174 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1175 i += 2; 1176 } 1177 } 1178 1179 // Add the flag input back if present. 1180 if (e != InOps.size()) 1181 Ops.push_back(InOps.back()); 1182} 1183 1184/// findFlagUse - Return use of EVT::Flag value produced by the specified 1185/// SDNode. 1186/// 1187static SDNode *findFlagUse(SDNode *N) { 1188 unsigned FlagResNo = N->getNumValues()-1; 1189 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1190 SDUse &Use = I.getUse(); 1191 if (Use.getResNo() == FlagResNo) 1192 return Use.getUser(); 1193 } 1194 return NULL; 1195} 1196 1197/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1198/// This function recursively traverses up the operand chain, ignoring 1199/// certain nodes. 1200static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1201 SDNode *Root, 1202 SmallPtrSet<SDNode*, 16> &Visited) { 1203 if (Use->getNodeId() < Def->getNodeId() || 1204 !Visited.insert(Use)) 1205 return false; 1206 1207 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1208 SDNode *N = Use->getOperand(i).getNode(); 1209 if (N == Def) { 1210 if (Use == ImmedUse || Use == Root) 1211 continue; // We are not looking for immediate use. 1212 assert(N != Root); 1213 return true; 1214 } 1215 1216 // Traverse up the operand chain. 1217 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1218 return true; 1219 } 1220 return false; 1221} 1222 1223/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1224/// be reached. Return true if that's the case. However, ignore direct uses 1225/// by ImmedUse (which would be U in the example illustrated in 1226/// IsLegalAndProfitableToFold) and by Root (which can happen in the store 1227/// case). 1228/// FIXME: to be really generic, we should allow direct use by any node 1229/// that is being folded. But realisticly since we only fold loads which 1230/// have one non-chain use, we only need to watch out for load/op/store 1231/// and load/op/cmp case where the root (store / cmp) may reach the load via 1232/// its chain operand. 1233static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1234 SmallPtrSet<SDNode*, 16> Visited; 1235 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1236} 1237 1238/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 1239/// U can be folded during instruction selection that starts at Root and 1240/// folding N is profitable. 1241bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 1242 SDNode *Root) const { 1243 if (OptLevel == CodeGenOpt::None) return false; 1244 1245 // If Root use can somehow reach N through a path that that doesn't contain 1246 // U then folding N would create a cycle. e.g. In the following 1247 // diagram, Root can reach N through X. If N is folded into into Root, then 1248 // X is both a predecessor and a successor of U. 1249 // 1250 // [N*] // 1251 // ^ ^ // 1252 // / \ // 1253 // [U*] [X]? // 1254 // ^ ^ // 1255 // \ / // 1256 // \ / // 1257 // [Root*] // 1258 // 1259 // * indicates nodes to be folded together. 1260 // 1261 // If Root produces a flag, then it gets (even more) interesting. Since it 1262 // will be "glued" together with its flag use in the scheduler, we need to 1263 // check if it might reach N. 1264 // 1265 // [N*] // 1266 // ^ ^ // 1267 // / \ // 1268 // [U*] [X]? // 1269 // ^ ^ // 1270 // \ \ // 1271 // \ | // 1272 // [Root*] | // 1273 // ^ | // 1274 // f | // 1275 // | / // 1276 // [Y] / // 1277 // ^ / // 1278 // f / // 1279 // | / // 1280 // [FU] // 1281 // 1282 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1283 // (call it Fold), then X is a predecessor of FU and a successor of 1284 // Fold. But since Fold and FU are flagged together, this will create 1285 // a cycle in the scheduling graph. 1286 1287 EVT VT = Root->getValueType(Root->getNumValues()-1); 1288 while (VT == MVT::Flag) { 1289 SDNode *FU = findFlagUse(Root); 1290 if (FU == NULL) 1291 break; 1292 Root = FU; 1293 VT = Root->getValueType(Root->getNumValues()-1); 1294 } 1295 1296 return !isNonImmUse(Root, N, U); 1297} 1298 1299SDNode *SelectionDAGISel::Select_INLINEASM(SDValue N) { 1300 std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end()); 1301 SelectInlineAsmMemoryOperands(Ops); 1302 1303 std::vector<EVT> VTs; 1304 VTs.push_back(MVT::Other); 1305 VTs.push_back(MVT::Flag); 1306 SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(), 1307 VTs, &Ops[0], Ops.size()); 1308 return New.getNode(); 1309} 1310 1311SDNode *SelectionDAGISel::Select_UNDEF(const SDValue &N) { 1312 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF, 1313 N.getValueType()); 1314} 1315 1316SDNode *SelectionDAGISel::Select_DBG_LABEL(const SDValue &N) { 1317 SDValue Chain = N.getOperand(0); 1318 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1319 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1320 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DBG_LABEL, 1321 MVT::Other, Tmp, Chain); 1322} 1323 1324SDNode *SelectionDAGISel::Select_EH_LABEL(const SDValue &N) { 1325 SDValue Chain = N.getOperand(0); 1326 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1327 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1328 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL, 1329 MVT::Other, Tmp, Chain); 1330} 1331 1332void SelectionDAGISel::CannotYetSelect(SDValue N) { 1333 std::string msg; 1334 raw_string_ostream Msg(msg); 1335 Msg << "Cannot yet select: "; 1336 N.getNode()->print(Msg, CurDAG); 1337 llvm_report_error(Msg.str()); 1338} 1339 1340void SelectionDAGISel::CannotYetSelectIntrinsic(SDValue N) { 1341 errs() << "Cannot yet select: "; 1342 unsigned iid = 1343 cast<ConstantSDNode>(N.getOperand(N.getOperand(0).getValueType() == MVT::Other))->getZExtValue(); 1344 if (iid < Intrinsic::num_intrinsics) 1345 llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid)); 1346 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 1347 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 1348 tii->getName(iid)); 1349} 1350 1351char SelectionDAGISel::ID = 0; 1352