SelectionDAGISel.cpp revision 90d33ee746f354030a4144c4ffa028599663615b
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/Timer.h" 49#include <algorithm> 50using namespace llvm; 51 52static cl::opt<bool> 53EnableValueProp("enable-value-prop", cl::Hidden); 54static cl::opt<bool> 55EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 56 57 58#ifndef NDEBUG 59static cl::opt<bool> 60ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 61 cl::desc("Pop up a window to show dags before the first " 62 "dag combine pass")); 63static cl::opt<bool> 64ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 65 cl::desc("Pop up a window to show dags before legalize types")); 66static cl::opt<bool> 67ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 68 cl::desc("Pop up a window to show dags before legalize")); 69static cl::opt<bool> 70ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before the second " 72 "dag combine pass")); 73static cl::opt<bool> 74ViewISelDAGs("view-isel-dags", cl::Hidden, 75 cl::desc("Pop up a window to show isel dags as they are selected")); 76static cl::opt<bool> 77ViewSchedDAGs("view-sched-dags", cl::Hidden, 78 cl::desc("Pop up a window to show sched dags as they are processed")); 79static cl::opt<bool> 80ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 81 cl::desc("Pop up a window to show SUnit dags after they are processed")); 82#else 83static const bool ViewDAGCombine1 = false, 84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 85 ViewDAGCombine2 = false, 86 ViewISelDAGs = false, ViewSchedDAGs = false, 87 ViewSUnitDAGs = false; 88#endif 89 90//===---------------------------------------------------------------------===// 91/// 92/// RegisterScheduler class - Track the registration of instruction schedulers. 93/// 94//===---------------------------------------------------------------------===// 95MachinePassRegistry RegisterScheduler::Registry; 96 97//===---------------------------------------------------------------------===// 98/// 99/// ISHeuristic command line option for instruction schedulers. 100/// 101//===---------------------------------------------------------------------===// 102static cl::opt<RegisterScheduler::FunctionPassCtor, false, 103 RegisterPassParser<RegisterScheduler> > 104ISHeuristic("pre-RA-sched", 105 cl::init(&createDefaultScheduler), 106 cl::desc("Instruction schedulers available (before register" 107 " allocation):")); 108 109static RegisterScheduler 110defaultListDAGScheduler("default", " Best scheduler for the target", 111 createDefaultScheduler); 112 113namespace { struct SDISelAsmOperandInfo; } 114 115/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence 116/// insertvalue or extractvalue indices that identify a member, return 117/// the linearized index of the start of the member. 118/// 119static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, 120 const unsigned *Indices, 121 const unsigned *IndicesEnd, 122 unsigned CurIndex = 0) { 123 // Base case: We're done. 124 if (Indices && Indices == IndicesEnd) 125 return CurIndex; 126 127 // Given a struct type, recursively traverse the elements. 128 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 129 for (StructType::element_iterator EB = STy->element_begin(), 130 EI = EB, 131 EE = STy->element_end(); 132 EI != EE; ++EI) { 133 if (Indices && *Indices == unsigned(EI - EB)) 134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex); 135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex); 136 } 137 } 138 // Given an array type, recursively traverse the elements. 139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 140 const Type *EltTy = ATy->getElementType(); 141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) { 142 if (Indices && *Indices == i) 143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex); 144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex); 145 } 146 } 147 // We haven't found the type we're looking for, so keep searching. 148 return CurIndex + 1; 149} 150 151/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of 152/// MVTs that represent all the individual underlying 153/// non-aggregate types that comprise it. 154/// 155/// If Offsets is non-null, it points to a vector to be filled in 156/// with the in-memory offsets of each of the individual values. 157/// 158static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, 159 SmallVectorImpl<MVT> &ValueVTs, 160 SmallVectorImpl<uint64_t> *Offsets = 0, 161 uint64_t StartingOffset = 0) { 162 // Given a struct type, recursively traverse the elements. 163 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); 165 for (StructType::element_iterator EB = STy->element_begin(), 166 EI = EB, 167 EE = STy->element_end(); 168 EI != EE; ++EI) 169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, 170 StartingOffset + SL->getElementOffset(EI - EB)); 171 return; 172 } 173 // Given an array type, recursively traverse the elements. 174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 175 const Type *EltTy = ATy->getElementType(); 176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy); 177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) 178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, 179 StartingOffset + i * EltSize); 180 return; 181 } 182 // Base case: we can get an MVT for this LLVM IR type. 183 ValueVTs.push_back(TLI.getValueType(Ty)); 184 if (Offsets) 185 Offsets->push_back(StartingOffset); 186} 187 188namespace { 189 /// RegsForValue - This struct represents the registers (physical or virtual) 190 /// that a particular set of values is assigned, and the type information about 191 /// the value. The most common situation is to represent one value at a time, 192 /// but struct or array values are handled element-wise as multiple values. 193 /// The splitting of aggregates is performed recursively, so that we never 194 /// have aggregate-typed registers. The values at this point do not necessarily 195 /// have legal types, so each value may require one or more registers of some 196 /// legal type. 197 /// 198 struct VISIBILITY_HIDDEN RegsForValue { 199 /// TLI - The TargetLowering object. 200 /// 201 const TargetLowering *TLI; 202 203 /// ValueVTs - The value types of the values, which may not be legal, and 204 /// may need be promoted or synthesized from one or more registers. 205 /// 206 SmallVector<MVT, 4> ValueVTs; 207 208 /// RegVTs - The value types of the registers. This is the same size as 209 /// ValueVTs and it records, for each value, what the type of the assigned 210 /// register or registers are. (Individual values are never synthesized 211 /// from more than one type of register.) 212 /// 213 /// With virtual registers, the contents of RegVTs is redundant with TLI's 214 /// getRegisterType member function, however when with physical registers 215 /// it is necessary to have a separate record of the types. 216 /// 217 SmallVector<MVT, 4> RegVTs; 218 219 /// Regs - This list holds the registers assigned to the values. 220 /// Each legal or promoted value requires one register, and each 221 /// expanded value requires multiple registers. 222 /// 223 SmallVector<unsigned, 4> Regs; 224 225 RegsForValue() : TLI(0) {} 226 227 RegsForValue(const TargetLowering &tli, 228 const SmallVector<unsigned, 4> ®s, 229 MVT regvt, MVT valuevt) 230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 231 RegsForValue(const TargetLowering &tli, 232 const SmallVector<unsigned, 4> ®s, 233 const SmallVector<MVT, 4> ®vts, 234 const SmallVector<MVT, 4> &valuevts) 235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 236 RegsForValue(const TargetLowering &tli, 237 unsigned Reg, const Type *Ty) : TLI(&tli) { 238 ComputeValueVTs(tli, Ty, ValueVTs); 239 240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 241 MVT ValueVT = ValueVTs[Value]; 242 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 243 MVT RegisterVT = TLI->getRegisterType(ValueVT); 244 for (unsigned i = 0; i != NumRegs; ++i) 245 Regs.push_back(Reg + i); 246 RegVTs.push_back(RegisterVT); 247 Reg += NumRegs; 248 } 249 } 250 251 /// append - Add the specified values to this one. 252 void append(const RegsForValue &RHS) { 253 TLI = RHS.TLI; 254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 256 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 257 } 258 259 260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 261 /// this value and returns the result as a ValueVTs value. This uses 262 /// Chain/Flag as the input and updates them for the output Chain/Flag. 263 /// If the Flag pointer is NULL, no flag is used. 264 SDValue getCopyFromRegs(SelectionDAG &DAG, 265 SDValue &Chain, SDValue *Flag) const; 266 267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 268 /// specified value into the registers specified by this object. This uses 269 /// Chain/Flag as the input and updates them for the output Chain/Flag. 270 /// If the Flag pointer is NULL, no flag is used. 271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, 272 SDValue &Chain, SDValue *Flag) const; 273 274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 275 /// operand list. This adds the code marker and includes the number of 276 /// values added into it. 277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 278 std::vector<SDValue> &Ops) const; 279 }; 280} 281 282namespace llvm { 283 //===--------------------------------------------------------------------===// 284 /// createDefaultScheduler - This creates an instruction scheduler appropriate 285 /// for the target. 286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 287 SelectionDAG *DAG, 288 MachineBasicBlock *BB, 289 bool Fast) { 290 TargetLowering &TLI = IS->getTargetLowering(); 291 292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 293 return createTDListDAGScheduler(IS, DAG, BB, Fast); 294 } else { 295 assert(TLI.getSchedulingPreference() == 296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 297 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 298 } 299 } 300 301 302 //===--------------------------------------------------------------------===// 303 /// FunctionLoweringInfo - This contains information that is global to a 304 /// function that is used when lowering a region of the function. 305 class FunctionLoweringInfo { 306 public: 307 TargetLowering &TLI; 308 Function &Fn; 309 MachineFunction &MF; 310 MachineRegisterInfo &RegInfo; 311 312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 313 314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 316 317 /// ValueMap - Since we emit code for the function a basic block at a time, 318 /// we must remember which virtual registers hold the values for 319 /// cross-basic-block values. 320 DenseMap<const Value*, unsigned> ValueMap; 321 322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 323 /// the entry block. This allows the allocas to be efficiently referenced 324 /// anywhere in the function. 325 std::map<const AllocaInst*, int> StaticAllocaMap; 326 327#ifndef NDEBUG 328 SmallSet<Instruction*, 8> CatchInfoLost; 329 SmallSet<Instruction*, 8> CatchInfoFound; 330#endif 331 332 unsigned MakeReg(MVT VT) { 333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 334 } 335 336 /// isExportedInst - Return true if the specified value is an instruction 337 /// exported from its block. 338 bool isExportedInst(const Value *V) { 339 return ValueMap.count(V); 340 } 341 342 unsigned CreateRegForValue(const Value *V); 343 344 unsigned InitializeRegForValue(const Value *V) { 345 unsigned &R = ValueMap[V]; 346 assert(R == 0 && "Already initialized this value register!"); 347 return R = CreateRegForValue(V); 348 } 349 350 struct LiveOutInfo { 351 unsigned NumSignBits; 352 APInt KnownOne, KnownZero; 353 LiveOutInfo() : NumSignBits(0) {} 354 }; 355 356 /// LiveOutRegInfo - Information about live out vregs, indexed by their 357 /// register number offset by 'FirstVirtualRegister'. 358 std::vector<LiveOutInfo> LiveOutRegInfo; 359 }; 360} 361 362/// isSelector - Return true if this instruction is a call to the 363/// eh.selector intrinsic. 364static bool isSelector(Instruction *I) { 365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 367 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 368 return false; 369} 370 371/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 372/// PHI nodes or outside of the basic block that defines it, or used by a 373/// switch or atomic instruction, which may expand to multiple basic blocks. 374static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 375 if (isa<PHINode>(I)) return true; 376 BasicBlock *BB = I->getParent(); 377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 379 // FIXME: Remove switchinst special case. 380 isa<SwitchInst>(*UI)) 381 return true; 382 return false; 383} 384 385/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 386/// entry block, return true. This includes arguments used by switches, since 387/// the switch may expand into multiple basic blocks. 388static bool isOnlyUsedInEntryBlock(Argument *A) { 389 BasicBlock *Entry = A->getParent()->begin(); 390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 392 return false; // Use not in entry block. 393 return true; 394} 395 396FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 397 Function &fn, MachineFunction &mf) 398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 399 400 // Create a vreg for each argument register that is not dead and is used 401 // outside of the entry block for the function. 402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 403 AI != E; ++AI) 404 if (!isOnlyUsedInEntryBlock(AI)) 405 InitializeRegForValue(AI); 406 407 // Initialize the mapping of values to registers. This is only set up for 408 // instruction values that are used outside of the block that defines 409 // them. 410 Function::iterator BB = Fn.begin(), EB = Fn.end(); 411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 414 const Type *Ty = AI->getAllocatedType(); 415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 416 unsigned Align = 417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 418 AI->getAlignment()); 419 420 TySize *= CUI->getZExtValue(); // Get total allocated size. 421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 422 StaticAllocaMap[AI] = 423 MF.getFrameInfo()->CreateStackObject(TySize, Align); 424 } 425 426 for (; BB != EB; ++BB) 427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 429 if (!isa<AllocaInst>(I) || 430 !StaticAllocaMap.count(cast<AllocaInst>(I))) 431 InitializeRegForValue(I); 432 433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 434 // also creates the initial PHI MachineInstrs, though none of the input 435 // operands are populated. 436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); 438 MBBMap[BB] = MBB; 439 MF.push_back(MBB); 440 441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 442 // appropriate. 443 PHINode *PN; 444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 445 if (PN->use_empty()) continue; 446 447 MVT VT = TLI.getValueType(PN->getType()); 448 unsigned NumRegisters = TLI.getNumRegisters(VT); 449 unsigned PHIReg = ValueMap[PN]; 450 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 451 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 452 for (unsigned i = 0; i != NumRegisters; ++i) 453 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 454 } 455 } 456} 457 458/// CreateRegForValue - Allocate the appropriate number of virtual registers of 459/// the correctly promoted or expanded types. Assign these registers 460/// consecutive vreg numbers and return the first assigned number. 461/// 462/// In the case that the given value has struct or array type, this function 463/// will assign registers for each member or element. 464/// 465unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 466 SmallVector<MVT, 4> ValueVTs; 467 ComputeValueVTs(TLI, V->getType(), ValueVTs); 468 469 unsigned FirstReg = 0; 470 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 471 MVT ValueVT = ValueVTs[Value]; 472 MVT RegisterVT = TLI.getRegisterType(ValueVT); 473 474 unsigned NumRegs = TLI.getNumRegisters(ValueVT); 475 for (unsigned i = 0; i != NumRegs; ++i) { 476 unsigned R = MakeReg(RegisterVT); 477 if (!FirstReg) FirstReg = R; 478 } 479 } 480 return FirstReg; 481} 482 483//===----------------------------------------------------------------------===// 484/// SelectionDAGLowering - This is the common target-independent lowering 485/// implementation that is parameterized by a TargetLowering object. 486/// Also, targets can overload any lowering method. 487/// 488namespace llvm { 489class SelectionDAGLowering { 490 MachineBasicBlock *CurMBB; 491 492 DenseMap<const Value*, SDValue> NodeMap; 493 494 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 495 /// them up and then emit token factor nodes when possible. This allows us to 496 /// get simple disambiguation between loads without worrying about alias 497 /// analysis. 498 SmallVector<SDValue, 8> PendingLoads; 499 500 /// PendingExports - CopyToReg nodes that copy values to virtual registers 501 /// for export to other blocks need to be emitted before any terminator 502 /// instruction, but they have no other ordering requirements. We bunch them 503 /// up and the emit a single tokenfactor for them just before terminator 504 /// instructions. 505 std::vector<SDValue> PendingExports; 506 507 /// Case - A struct to record the Value for a switch case, and the 508 /// case's target basic block. 509 struct Case { 510 Constant* Low; 511 Constant* High; 512 MachineBasicBlock* BB; 513 514 Case() : Low(0), High(0), BB(0) { } 515 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 516 Low(low), High(high), BB(bb) { } 517 uint64_t size() const { 518 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 519 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 520 return (rHigh - rLow + 1ULL); 521 } 522 }; 523 524 struct CaseBits { 525 uint64_t Mask; 526 MachineBasicBlock* BB; 527 unsigned Bits; 528 529 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 530 Mask(mask), BB(bb), Bits(bits) { } 531 }; 532 533 typedef std::vector<Case> CaseVector; 534 typedef std::vector<CaseBits> CaseBitsVector; 535 typedef CaseVector::iterator CaseItr; 536 typedef std::pair<CaseItr, CaseItr> CaseRange; 537 538 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 539 /// of conditional branches. 540 struct CaseRec { 541 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 542 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 543 544 /// CaseBB - The MBB in which to emit the compare and branch 545 MachineBasicBlock *CaseBB; 546 /// LT, GE - If nonzero, we know the current case value must be less-than or 547 /// greater-than-or-equal-to these Constants. 548 Constant *LT; 549 Constant *GE; 550 /// Range - A pair of iterators representing the range of case values to be 551 /// processed at this point in the binary search tree. 552 CaseRange Range; 553 }; 554 555 typedef std::vector<CaseRec> CaseRecVector; 556 557 /// The comparison function for sorting the switch case values in the vector. 558 /// WARNING: Case ranges should be disjoint! 559 struct CaseCmp { 560 bool operator () (const Case& C1, const Case& C2) { 561 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 562 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 563 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 564 return CI1->getValue().slt(CI2->getValue()); 565 } 566 }; 567 568 struct CaseBitsCmp { 569 bool operator () (const CaseBits& C1, const CaseBits& C2) { 570 return C1.Bits > C2.Bits; 571 } 572 }; 573 574 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 575 576public: 577 // TLI - This is information that describes the available target features we 578 // need for lowering. This indicates when operations are unavailable, 579 // implemented with a libcall, etc. 580 TargetLowering &TLI; 581 SelectionDAG &DAG; 582 const TargetData *TD; 583 AliasAnalysis &AA; 584 585 /// SwitchCases - Vector of CaseBlock structures used to communicate 586 /// SwitchInst code generation information. 587 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 588 /// JTCases - Vector of JumpTable structures used to communicate 589 /// SwitchInst code generation information. 590 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 591 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 592 593 /// FuncInfo - Information about the function as a whole. 594 /// 595 FunctionLoweringInfo &FuncInfo; 596 597 /// GCI - Garbage collection metadata for the function. 598 CollectorMetadata *GCI; 599 600 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 601 AliasAnalysis &aa, 602 FunctionLoweringInfo &funcinfo, 603 CollectorMetadata *gci) 604 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 605 FuncInfo(funcinfo), GCI(gci) { 606 } 607 608 /// getRoot - Return the current virtual root of the Selection DAG, 609 /// flushing any PendingLoad items. This must be done before emitting 610 /// a store or any other node that may need to be ordered after any 611 /// prior load instructions. 612 /// 613 SDValue getRoot() { 614 if (PendingLoads.empty()) 615 return DAG.getRoot(); 616 617 if (PendingLoads.size() == 1) { 618 SDValue Root = PendingLoads[0]; 619 DAG.setRoot(Root); 620 PendingLoads.clear(); 621 return Root; 622 } 623 624 // Otherwise, we have to make a token factor node. 625 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 626 &PendingLoads[0], PendingLoads.size()); 627 PendingLoads.clear(); 628 DAG.setRoot(Root); 629 return Root; 630 } 631 632 /// getControlRoot - Similar to getRoot, but instead of flushing all the 633 /// PendingLoad items, flush all the PendingExports items. It is necessary 634 /// to do this before emitting a terminator instruction. 635 /// 636 SDValue getControlRoot() { 637 SDValue Root = DAG.getRoot(); 638 639 if (PendingExports.empty()) 640 return Root; 641 642 // Turn all of the CopyToReg chains into one factored node. 643 if (Root.getOpcode() != ISD::EntryToken) { 644 unsigned i = 0, e = PendingExports.size(); 645 for (; i != e; ++i) { 646 assert(PendingExports[i].Val->getNumOperands() > 1); 647 if (PendingExports[i].Val->getOperand(0) == Root) 648 break; // Don't add the root if we already indirectly depend on it. 649 } 650 651 if (i == e) 652 PendingExports.push_back(Root); 653 } 654 655 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 656 &PendingExports[0], 657 PendingExports.size()); 658 PendingExports.clear(); 659 DAG.setRoot(Root); 660 return Root; 661 } 662 663 void CopyValueToVirtualRegister(Value *V, unsigned Reg); 664 665 void visit(Instruction &I) { visit(I.getOpcode(), I); } 666 667 void visit(unsigned Opcode, User &I) { 668 // Note: this doesn't use InstVisitor, because it has to work with 669 // ConstantExpr's in addition to instructions. 670 switch (Opcode) { 671 default: assert(0 && "Unknown instruction type encountered!"); 672 abort(); 673 // Build the switch statement using the Instruction.def file. 674#define HANDLE_INST(NUM, OPCODE, CLASS) \ 675 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 676#include "llvm/Instruction.def" 677 } 678 } 679 680 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 681 682 SDValue getValue(const Value *V); 683 684 void setValue(const Value *V, SDValue NewN) { 685 SDValue &N = NodeMap[V]; 686 assert(N.Val == 0 && "Already set a value for this node!"); 687 N = NewN; 688 } 689 690 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 691 std::set<unsigned> &OutputRegs, 692 std::set<unsigned> &InputRegs); 693 694 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 696 unsigned Opc); 697 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 698 void ExportFromCurrentBlock(Value *V); 699 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall, 700 MachineBasicBlock *LandingPad = NULL); 701 702 // Terminator instructions. 703 void visitRet(ReturnInst &I); 704 void visitBr(BranchInst &I); 705 void visitSwitch(SwitchInst &I); 706 void visitUnreachable(UnreachableInst &I) { /* noop */ } 707 708 // Helpers for visitSwitch 709 bool handleSmallSwitchRange(CaseRec& CR, 710 CaseRecVector& WorkList, 711 Value* SV, 712 MachineBasicBlock* Default); 713 bool handleJTSwitchCase(CaseRec& CR, 714 CaseRecVector& WorkList, 715 Value* SV, 716 MachineBasicBlock* Default); 717 bool handleBTSplitSwitchCase(CaseRec& CR, 718 CaseRecVector& WorkList, 719 Value* SV, 720 MachineBasicBlock* Default); 721 bool handleBitTestsSwitchCase(CaseRec& CR, 722 CaseRecVector& WorkList, 723 Value* SV, 724 MachineBasicBlock* Default); 725 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 726 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 727 void visitBitTestCase(MachineBasicBlock* NextMBB, 728 unsigned Reg, 729 SelectionDAGISel::BitTestCase &B); 730 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 731 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 732 SelectionDAGISel::JumpTableHeader &JTH); 733 734 // These all get lowered before this pass. 735 void visitInvoke(InvokeInst &I); 736 void visitUnwind(UnwindInst &I); 737 738 void visitBinary(User &I, unsigned OpCode); 739 void visitShift(User &I, unsigned Opcode); 740 void visitAdd(User &I) { 741 if (I.getType()->isFPOrFPVector()) 742 visitBinary(I, ISD::FADD); 743 else 744 visitBinary(I, ISD::ADD); 745 } 746 void visitSub(User &I); 747 void visitMul(User &I) { 748 if (I.getType()->isFPOrFPVector()) 749 visitBinary(I, ISD::FMUL); 750 else 751 visitBinary(I, ISD::MUL); 752 } 753 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 754 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 755 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 756 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 757 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 758 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 759 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 760 void visitOr (User &I) { visitBinary(I, ISD::OR); } 761 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 762 void visitShl (User &I) { visitShift(I, ISD::SHL); } 763 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 764 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 765 void visitICmp(User &I); 766 void visitFCmp(User &I); 767 void visitVICmp(User &I); 768 void visitVFCmp(User &I); 769 // Visit the conversion instructions 770 void visitTrunc(User &I); 771 void visitZExt(User &I); 772 void visitSExt(User &I); 773 void visitFPTrunc(User &I); 774 void visitFPExt(User &I); 775 void visitFPToUI(User &I); 776 void visitFPToSI(User &I); 777 void visitUIToFP(User &I); 778 void visitSIToFP(User &I); 779 void visitPtrToInt(User &I); 780 void visitIntToPtr(User &I); 781 void visitBitCast(User &I); 782 783 void visitExtractElement(User &I); 784 void visitInsertElement(User &I); 785 void visitShuffleVector(User &I); 786 787 void visitExtractValue(ExtractValueInst &I); 788 void visitInsertValue(InsertValueInst &I); 789 790 void visitGetElementPtr(User &I); 791 void visitSelect(User &I); 792 793 void visitMalloc(MallocInst &I); 794 void visitFree(FreeInst &I); 795 void visitAlloca(AllocaInst &I); 796 void visitLoad(LoadInst &I); 797 void visitStore(StoreInst &I); 798 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 799 void visitCall(CallInst &I); 800 void visitInlineAsm(CallSite CS); 801 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 802 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 803 804 void visitVAStart(CallInst &I); 805 void visitVAArg(VAArgInst &I); 806 void visitVAEnd(CallInst &I); 807 void visitVACopy(CallInst &I); 808 809 void visitUserOp1(Instruction &I) { 810 assert(0 && "UserOp1 should not exist at instruction selection time!"); 811 abort(); 812 } 813 void visitUserOp2(Instruction &I) { 814 assert(0 && "UserOp2 should not exist at instruction selection time!"); 815 abort(); 816 } 817 818private: 819 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); 820 821}; 822} // end namespace llvm 823 824 825/// getCopyFromParts - Create a value that contains the specified legal parts 826/// combined into the value they represent. If the parts combine to a type 827/// larger then ValueVT then AssertOp can be used to specify whether the extra 828/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 829/// (ISD::AssertSext). 830static SDValue getCopyFromParts(SelectionDAG &DAG, 831 const SDValue *Parts, 832 unsigned NumParts, 833 MVT PartVT, 834 MVT ValueVT, 835 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 836 assert(NumParts > 0 && "No parts to assemble!"); 837 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 838 SDValue Val = Parts[0]; 839 840 if (NumParts > 1) { 841 // Assemble the value from multiple parts. 842 if (!ValueVT.isVector()) { 843 unsigned PartBits = PartVT.getSizeInBits(); 844 unsigned ValueBits = ValueVT.getSizeInBits(); 845 846 // Assemble the power of 2 part. 847 unsigned RoundParts = NumParts & (NumParts - 1) ? 848 1 << Log2_32(NumParts) : NumParts; 849 unsigned RoundBits = PartBits * RoundParts; 850 MVT RoundVT = RoundBits == ValueBits ? 851 ValueVT : MVT::getIntegerVT(RoundBits); 852 SDValue Lo, Hi; 853 854 if (RoundParts > 2) { 855 MVT HalfVT = MVT::getIntegerVT(RoundBits/2); 856 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 857 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 858 PartVT, HalfVT); 859 } else { 860 Lo = Parts[0]; 861 Hi = Parts[1]; 862 } 863 if (TLI.isBigEndian()) 864 std::swap(Lo, Hi); 865 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 866 867 if (RoundParts < NumParts) { 868 // Assemble the trailing non-power-of-2 part. 869 unsigned OddParts = NumParts - RoundParts; 870 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); 871 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 872 873 // Combine the round and odd parts. 874 Lo = Val; 875 if (TLI.isBigEndian()) 876 std::swap(Lo, Hi); 877 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); 878 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 879 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 880 DAG.getConstant(Lo.getValueType().getSizeInBits(), 881 TLI.getShiftAmountTy())); 882 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 883 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 884 } 885 } else { 886 // Handle a multi-element vector. 887 MVT IntermediateVT, RegisterVT; 888 unsigned NumIntermediates; 889 unsigned NumRegs = 890 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 891 RegisterVT); 892 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 893 NumParts = NumRegs; // Silence a compiler warning. 894 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 895 assert(RegisterVT == Parts[0].getValueType() && 896 "Part type doesn't match part!"); 897 898 // Assemble the parts into intermediate operands. 899 SmallVector<SDValue, 8> Ops(NumIntermediates); 900 if (NumIntermediates == NumParts) { 901 // If the register was not expanded, truncate or copy the value, 902 // as appropriate. 903 for (unsigned i = 0; i != NumParts; ++i) 904 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 905 PartVT, IntermediateVT); 906 } else if (NumParts > 0) { 907 // If the intermediate type was expanded, build the intermediate operands 908 // from the parts. 909 assert(NumParts % NumIntermediates == 0 && 910 "Must expand into a divisible number of parts!"); 911 unsigned Factor = NumParts / NumIntermediates; 912 for (unsigned i = 0; i != NumIntermediates; ++i) 913 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 914 PartVT, IntermediateVT); 915 } 916 917 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 918 // operands. 919 Val = DAG.getNode(IntermediateVT.isVector() ? 920 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 921 ValueVT, &Ops[0], NumIntermediates); 922 } 923 } 924 925 // There is now one part, held in Val. Correct it to match ValueVT. 926 PartVT = Val.getValueType(); 927 928 if (PartVT == ValueVT) 929 return Val; 930 931 if (PartVT.isVector()) { 932 assert(ValueVT.isVector() && "Unknown vector conversion!"); 933 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 934 } 935 936 if (ValueVT.isVector()) { 937 assert(ValueVT.getVectorElementType() == PartVT && 938 ValueVT.getVectorNumElements() == 1 && 939 "Only trivial scalar-to-vector conversions should get here!"); 940 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 941 } 942 943 if (PartVT.isInteger() && 944 ValueVT.isInteger()) { 945 if (ValueVT.bitsLT(PartVT)) { 946 // For a truncate, see if we have any information to 947 // indicate whether the truncated bits will always be 948 // zero or sign-extension. 949 if (AssertOp != ISD::DELETED_NODE) 950 Val = DAG.getNode(AssertOp, PartVT, Val, 951 DAG.getValueType(ValueVT)); 952 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 953 } else { 954 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 955 } 956 } 957 958 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 959 if (ValueVT.bitsLT(Val.getValueType())) 960 // FP_ROUND's are always exact here. 961 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 962 DAG.getIntPtrConstant(1)); 963 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); 964 } 965 966 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 967 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 968 969 assert(0 && "Unknown mismatch!"); 970 return SDValue(); 971} 972 973/// getCopyToParts - Create a series of nodes that contain the specified value 974/// split into legal parts. If the parts contain more bits than Val, then, for 975/// integers, ExtendKind can be used to specify how to generate the extra bits. 976static void getCopyToParts(SelectionDAG &DAG, 977 SDValue Val, 978 SDValue *Parts, 979 unsigned NumParts, 980 MVT PartVT, 981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 982 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 983 MVT PtrVT = TLI.getPointerTy(); 984 MVT ValueVT = Val.getValueType(); 985 unsigned PartBits = PartVT.getSizeInBits(); 986 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 987 988 if (!NumParts) 989 return; 990 991 if (!ValueVT.isVector()) { 992 if (PartVT == ValueVT) { 993 assert(NumParts == 1 && "No-op copy with multiple parts!"); 994 Parts[0] = Val; 995 return; 996 } 997 998 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 999 // If the parts cover more bits than the value has, promote the value. 1000 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 1001 assert(NumParts == 1 && "Do not know what to promote to!"); 1002 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 1003 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 1004 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1005 Val = DAG.getNode(ExtendKind, ValueVT, Val); 1006 } else { 1007 assert(0 && "Unknown mismatch!"); 1008 } 1009 } else if (PartBits == ValueVT.getSizeInBits()) { 1010 // Different types of the same size. 1011 assert(NumParts == 1 && PartVT != ValueVT); 1012 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1013 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 1014 // If the parts cover less bits than value has, truncate the value. 1015 if (PartVT.isInteger() && ValueVT.isInteger()) { 1016 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1017 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1018 } else { 1019 assert(0 && "Unknown mismatch!"); 1020 } 1021 } 1022 1023 // The value may have changed - recompute ValueVT. 1024 ValueVT = Val.getValueType(); 1025 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 1026 "Failed to tile the value with PartVT!"); 1027 1028 if (NumParts == 1) { 1029 assert(PartVT == ValueVT && "Type conversion failed!"); 1030 Parts[0] = Val; 1031 return; 1032 } 1033 1034 // Expand the value into multiple parts. 1035 if (NumParts & (NumParts - 1)) { 1036 // The number of parts is not a power of 2. Split off and copy the tail. 1037 assert(PartVT.isInteger() && ValueVT.isInteger() && 1038 "Do not know what to expand to!"); 1039 unsigned RoundParts = 1 << Log2_32(NumParts); 1040 unsigned RoundBits = RoundParts * PartBits; 1041 unsigned OddParts = NumParts - RoundParts; 1042 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 1043 DAG.getConstant(RoundBits, 1044 TLI.getShiftAmountTy())); 1045 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 1046 if (TLI.isBigEndian()) 1047 // The odd parts were reversed by getCopyToParts - unreverse them. 1048 std::reverse(Parts + RoundParts, Parts + NumParts); 1049 NumParts = RoundParts; 1050 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1051 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1052 } 1053 1054 // The number of parts is a power of 2. Repeatedly bisect the value using 1055 // EXTRACT_ELEMENT. 1056 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, 1057 MVT::getIntegerVT(ValueVT.getSizeInBits()), 1058 Val); 1059 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 1060 for (unsigned i = 0; i < NumParts; i += StepSize) { 1061 unsigned ThisBits = StepSize * PartBits / 2; 1062 MVT ThisVT = MVT::getIntegerVT (ThisBits); 1063 SDValue &Part0 = Parts[i]; 1064 SDValue &Part1 = Parts[i+StepSize/2]; 1065 1066 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1067 DAG.getConstant(1, PtrVT)); 1068 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1069 DAG.getConstant(0, PtrVT)); 1070 1071 if (ThisBits == PartBits && ThisVT != PartVT) { 1072 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0); 1073 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1); 1074 } 1075 } 1076 } 1077 1078 if (TLI.isBigEndian()) 1079 std::reverse(Parts, Parts + NumParts); 1080 1081 return; 1082 } 1083 1084 // Vector ValueVT. 1085 if (NumParts == 1) { 1086 if (PartVT != ValueVT) { 1087 if (PartVT.isVector()) { 1088 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1089 } else { 1090 assert(ValueVT.getVectorElementType() == PartVT && 1091 ValueVT.getVectorNumElements() == 1 && 1092 "Only trivial vector-to-scalar conversions should get here!"); 1093 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 1094 DAG.getConstant(0, PtrVT)); 1095 } 1096 } 1097 1098 Parts[0] = Val; 1099 return; 1100 } 1101 1102 // Handle a multi-element vector. 1103 MVT IntermediateVT, RegisterVT; 1104 unsigned NumIntermediates; 1105 unsigned NumRegs = 1106 DAG.getTargetLoweringInfo() 1107 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 1108 RegisterVT); 1109 unsigned NumElements = ValueVT.getVectorNumElements(); 1110 1111 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 1112 NumParts = NumRegs; // Silence a compiler warning. 1113 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 1114 1115 // Split the vector into intermediate operands. 1116 SmallVector<SDValue, 8> Ops(NumIntermediates); 1117 for (unsigned i = 0; i != NumIntermediates; ++i) 1118 if (IntermediateVT.isVector()) 1119 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 1120 IntermediateVT, Val, 1121 DAG.getConstant(i * (NumElements / NumIntermediates), 1122 PtrVT)); 1123 else 1124 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 1125 IntermediateVT, Val, 1126 DAG.getConstant(i, PtrVT)); 1127 1128 // Split the intermediate operands into legal parts. 1129 if (NumParts == NumIntermediates) { 1130 // If the register was not expanded, promote or copy the value, 1131 // as appropriate. 1132 for (unsigned i = 0; i != NumParts; ++i) 1133 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 1134 } else if (NumParts > 0) { 1135 // If the intermediate type was expanded, split each the value into 1136 // legal parts. 1137 assert(NumParts % NumIntermediates == 0 && 1138 "Must expand into a divisible number of parts!"); 1139 unsigned Factor = NumParts / NumIntermediates; 1140 for (unsigned i = 0; i != NumIntermediates; ++i) 1141 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 1142 } 1143} 1144 1145 1146SDValue SelectionDAGLowering::getValue(const Value *V) { 1147 SDValue &N = NodeMap[V]; 1148 if (N.Val) return N; 1149 1150 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 1151 MVT VT = TLI.getValueType(V->getType(), true); 1152 1153 if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1154 return N = DAG.getConstant(CI->getValue(), VT); 1155 1156 if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1157 return N = DAG.getGlobalAddress(GV, VT); 1158 1159 if (isa<ConstantPointerNull>(C)) 1160 return N = DAG.getConstant(0, TLI.getPointerTy()); 1161 1162 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1163 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 1164 1165 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) && 1166 !V->getType()->isAggregateType()) 1167 return N = DAG.getNode(ISD::UNDEF, VT); 1168 1169 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1170 visit(CE->getOpcode(), *CE); 1171 SDValue N1 = NodeMap[V]; 1172 assert(N1.Val && "visit didn't populate the ValueMap!"); 1173 return N1; 1174 } 1175 1176 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1177 SmallVector<SDValue, 4> Constants; 1178 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1179 OI != OE; ++OI) { 1180 SDNode *Val = getValue(*OI).Val; 1181 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1182 Constants.push_back(SDValue(Val, i)); 1183 } 1184 return DAG.getMergeValues(&Constants[0], Constants.size()); 1185 } 1186 1187 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) { 1188 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1189 "Unknown array constant!"); 1190 unsigned NumElts = ATy->getNumElements(); 1191 if (NumElts == 0) 1192 return SDValue(); // empty array 1193 MVT EltVT = TLI.getValueType(ATy->getElementType()); 1194 SmallVector<SDValue, 4> Constants(NumElts); 1195 for (unsigned i = 0, e = NumElts; i != e; ++i) { 1196 if (isa<UndefValue>(C)) 1197 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); 1198 else if (EltVT.isFloatingPoint()) 1199 Constants[i] = DAG.getConstantFP(0, EltVT); 1200 else 1201 Constants[i] = DAG.getConstant(0, EltVT); 1202 } 1203 return DAG.getMergeValues(&Constants[0], Constants.size()); 1204 } 1205 1206 if (const StructType *STy = dyn_cast<StructType>(C->getType())) { 1207 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1208 "Unknown struct constant!"); 1209 unsigned NumElts = STy->getNumElements(); 1210 if (NumElts == 0) 1211 return SDValue(); // empty struct 1212 SmallVector<SDValue, 4> Constants(NumElts); 1213 for (unsigned i = 0, e = NumElts; i != e; ++i) { 1214 MVT EltVT = TLI.getValueType(STy->getElementType(i)); 1215 if (isa<UndefValue>(C)) 1216 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); 1217 else if (EltVT.isFloatingPoint()) 1218 Constants[i] = DAG.getConstantFP(0, EltVT); 1219 else 1220 Constants[i] = DAG.getConstant(0, EltVT); 1221 } 1222 return DAG.getMergeValues(&Constants[0], Constants.size()); 1223 } 1224 1225 const VectorType *VecTy = cast<VectorType>(V->getType()); 1226 unsigned NumElements = VecTy->getNumElements(); 1227 1228 // Now that we know the number and type of the elements, get that number of 1229 // elements into the Ops array based on what kind of constant it is. 1230 SmallVector<SDValue, 16> Ops; 1231 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1232 for (unsigned i = 0; i != NumElements; ++i) 1233 Ops.push_back(getValue(CP->getOperand(i))); 1234 } else { 1235 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1236 "Unknown vector constant!"); 1237 MVT EltVT = TLI.getValueType(VecTy->getElementType()); 1238 1239 SDValue Op; 1240 if (isa<UndefValue>(C)) 1241 Op = DAG.getNode(ISD::UNDEF, EltVT); 1242 else if (EltVT.isFloatingPoint()) 1243 Op = DAG.getConstantFP(0, EltVT); 1244 else 1245 Op = DAG.getConstant(0, EltVT); 1246 Ops.assign(NumElements, Op); 1247 } 1248 1249 // Create a BUILD_VECTOR node. 1250 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1251 } 1252 1253 // If this is a static alloca, generate it as the frameindex instead of 1254 // computation. 1255 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1256 std::map<const AllocaInst*, int>::iterator SI = 1257 FuncInfo.StaticAllocaMap.find(AI); 1258 if (SI != FuncInfo.StaticAllocaMap.end()) 1259 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1260 } 1261 1262 unsigned InReg = FuncInfo.ValueMap[V]; 1263 assert(InReg && "Value not in map!"); 1264 1265 RegsForValue RFV(TLI, InReg, V->getType()); 1266 SDValue Chain = DAG.getEntryNode(); 1267 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1268} 1269 1270 1271void SelectionDAGLowering::visitRet(ReturnInst &I) { 1272 if (I.getNumOperands() == 0) { 1273 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot())); 1274 return; 1275 } 1276 1277 SmallVector<SDValue, 8> NewValues; 1278 NewValues.push_back(getControlRoot()); 1279 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1280 SDValue RetOp = getValue(I.getOperand(i)); 1281 1282 SmallVector<MVT, 4> ValueVTs; 1283 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs); 1284 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) { 1285 MVT VT = ValueVTs[j]; 1286 1287 // FIXME: C calling convention requires the return type to be promoted to 1288 // at least 32-bit. But this is not necessary for non-C calling conventions. 1289 if (VT.isInteger()) { 1290 MVT MinVT = TLI.getRegisterType(MVT::i32); 1291 if (VT.bitsLT(MinVT)) 1292 VT = MinVT; 1293 } 1294 1295 unsigned NumParts = TLI.getNumRegisters(VT); 1296 MVT PartVT = TLI.getRegisterType(VT); 1297 SmallVector<SDValue, 4> Parts(NumParts); 1298 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1299 1300 const Function *F = I.getParent()->getParent(); 1301 if (F->paramHasAttr(0, ParamAttr::SExt)) 1302 ExtendKind = ISD::SIGN_EXTEND; 1303 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1304 ExtendKind = ISD::ZERO_EXTEND; 1305 1306 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j), 1307 &Parts[0], NumParts, PartVT, ExtendKind); 1308 1309 for (unsigned i = 0; i < NumParts; ++i) { 1310 NewValues.push_back(Parts[i]); 1311 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy())); 1312 } 1313 } 1314 } 1315 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1316 &NewValues[0], NewValues.size())); 1317} 1318 1319/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1320/// the current basic block, add it to ValueMap now so that we'll get a 1321/// CopyTo/FromReg. 1322void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1323 // No need to export constants. 1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1325 1326 // Already exported? 1327 if (FuncInfo.isExportedInst(V)) return; 1328 1329 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1330 CopyValueToVirtualRegister(V, Reg); 1331} 1332 1333bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1334 const BasicBlock *FromBB) { 1335 // The operands of the setcc have to be in this block. We don't know 1336 // how to export them from some other block. 1337 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1338 // Can export from current BB. 1339 if (VI->getParent() == FromBB) 1340 return true; 1341 1342 // Is already exported, noop. 1343 return FuncInfo.isExportedInst(V); 1344 } 1345 1346 // If this is an argument, we can export it if the BB is the entry block or 1347 // if it is already exported. 1348 if (isa<Argument>(V)) { 1349 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1350 return true; 1351 1352 // Otherwise, can only export this if it is already exported. 1353 return FuncInfo.isExportedInst(V); 1354 } 1355 1356 // Otherwise, constants can always be exported. 1357 return true; 1358} 1359 1360static bool InBlock(const Value *V, const BasicBlock *BB) { 1361 if (const Instruction *I = dyn_cast<Instruction>(V)) 1362 return I->getParent() == BB; 1363 return true; 1364} 1365 1366/// FindMergedConditions - If Cond is an expression like 1367void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1368 MachineBasicBlock *TBB, 1369 MachineBasicBlock *FBB, 1370 MachineBasicBlock *CurBB, 1371 unsigned Opc) { 1372 // If this node is not part of the or/and tree, emit it as a branch. 1373 Instruction *BOp = dyn_cast<Instruction>(Cond); 1374 1375 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1376 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1377 BOp->getParent() != CurBB->getBasicBlock() || 1378 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1379 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1380 const BasicBlock *BB = CurBB->getBasicBlock(); 1381 1382 // If the leaf of the tree is a comparison, merge the condition into 1383 // the caseblock. 1384 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1385 // The operands of the cmp have to be in this block. We don't know 1386 // how to export them from some other block. If this is the first block 1387 // of the sequence, no exporting is needed. 1388 (CurBB == CurMBB || 1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1391 BOp = cast<Instruction>(Cond); 1392 ISD::CondCode Condition; 1393 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1394 switch (IC->getPredicate()) { 1395 default: assert(0 && "Unknown icmp predicate opcode!"); 1396 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1397 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1398 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1399 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1400 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1401 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1402 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1403 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1404 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1405 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1406 } 1407 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1408 ISD::CondCode FPC, FOC; 1409 switch (FC->getPredicate()) { 1410 default: assert(0 && "Unknown fcmp predicate opcode!"); 1411 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1412 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1413 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1414 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1415 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1416 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1417 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1418 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 1419 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 1420 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1421 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1422 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1423 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1424 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1425 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1426 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1427 } 1428 if (FiniteOnlyFPMath()) 1429 Condition = FOC; 1430 else 1431 Condition = FPC; 1432 } else { 1433 Condition = ISD::SETEQ; // silence warning. 1434 assert(0 && "Unknown compare instruction"); 1435 } 1436 1437 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1438 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1439 SwitchCases.push_back(CB); 1440 return; 1441 } 1442 1443 // Create a CaseBlock record representing this branch. 1444 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1445 NULL, TBB, FBB, CurBB); 1446 SwitchCases.push_back(CB); 1447 return; 1448 } 1449 1450 1451 // Create TmpBB after CurBB. 1452 MachineFunction::iterator BBI = CurBB; 1453 MachineFunction &MF = DAG.getMachineFunction(); 1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1455 CurBB->getParent()->insert(++BBI, TmpBB); 1456 1457 if (Opc == Instruction::Or) { 1458 // Codegen X | Y as: 1459 // jmp_if_X TBB 1460 // jmp TmpBB 1461 // TmpBB: 1462 // jmp_if_Y TBB 1463 // jmp FBB 1464 // 1465 1466 // Emit the LHS condition. 1467 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1468 1469 // Emit the RHS condition into TmpBB. 1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1471 } else { 1472 assert(Opc == Instruction::And && "Unknown merge op!"); 1473 // Codegen X & Y as: 1474 // jmp_if_X TmpBB 1475 // jmp FBB 1476 // TmpBB: 1477 // jmp_if_Y TBB 1478 // jmp FBB 1479 // 1480 // This requires creation of TmpBB after CurBB. 1481 1482 // Emit the LHS condition. 1483 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1484 1485 // Emit the RHS condition into TmpBB. 1486 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1487 } 1488} 1489 1490/// If the set of cases should be emitted as a series of branches, return true. 1491/// If we should emit this as a bunch of and/or'd together conditions, return 1492/// false. 1493static bool 1494ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1495 if (Cases.size() != 2) return true; 1496 1497 // If this is two comparisons of the same values or'd or and'd together, they 1498 // will get folded into a single comparison, so don't emit two blocks. 1499 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1500 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1501 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1502 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1503 return false; 1504 } 1505 1506 return true; 1507} 1508 1509void SelectionDAGLowering::visitBr(BranchInst &I) { 1510 // Update machine-CFG edges. 1511 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1512 1513 // Figure out which block is immediately after the current one. 1514 MachineBasicBlock *NextBlock = 0; 1515 MachineFunction::iterator BBI = CurMBB; 1516 if (++BBI != CurMBB->getParent()->end()) 1517 NextBlock = BBI; 1518 1519 if (I.isUnconditional()) { 1520 // Update machine-CFG edges. 1521 CurMBB->addSuccessor(Succ0MBB); 1522 1523 // If this is not a fall-through branch, emit the branch. 1524 if (Succ0MBB != NextBlock) 1525 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1526 DAG.getBasicBlock(Succ0MBB))); 1527 return; 1528 } 1529 1530 // If this condition is one of the special cases we handle, do special stuff 1531 // now. 1532 Value *CondVal = I.getCondition(); 1533 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1534 1535 // If this is a series of conditions that are or'd or and'd together, emit 1536 // this as a sequence of branches instead of setcc's with and/or operations. 1537 // For example, instead of something like: 1538 // cmp A, B 1539 // C = seteq 1540 // cmp D, E 1541 // F = setle 1542 // or C, F 1543 // jnz foo 1544 // Emit: 1545 // cmp A, B 1546 // je foo 1547 // cmp D, E 1548 // jle foo 1549 // 1550 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1551 if (BOp->hasOneUse() && 1552 (BOp->getOpcode() == Instruction::And || 1553 BOp->getOpcode() == Instruction::Or)) { 1554 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1555 // If the compares in later blocks need to use values not currently 1556 // exported from this block, export them now. This block should always 1557 // be the first entry. 1558 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1559 1560 // Allow some cases to be rejected. 1561 if (ShouldEmitAsBranches(SwitchCases)) { 1562 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1563 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1564 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1565 } 1566 1567 // Emit the branch for this block. 1568 visitSwitchCase(SwitchCases[0]); 1569 SwitchCases.erase(SwitchCases.begin()); 1570 return; 1571 } 1572 1573 // Okay, we decided not to do this, remove any inserted MBB's and clear 1574 // SwitchCases. 1575 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1576 CurMBB->getParent()->erase(SwitchCases[i].ThisBB); 1577 1578 SwitchCases.clear(); 1579 } 1580 } 1581 1582 // Create a CaseBlock record representing this branch. 1583 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1584 NULL, Succ0MBB, Succ1MBB, CurMBB); 1585 // Use visitSwitchCase to actually insert the fast branch sequence for this 1586 // cond branch. 1587 visitSwitchCase(CB); 1588} 1589 1590/// visitSwitchCase - Emits the necessary code to represent a single node in 1591/// the binary search tree resulting from lowering a switch instruction. 1592void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1593 SDValue Cond; 1594 SDValue CondLHS = getValue(CB.CmpLHS); 1595 1596 // Build the setcc now. 1597 if (CB.CmpMHS == NULL) { 1598 // Fold "(X == true)" to X and "(X == false)" to !X to 1599 // handle common cases produced by branch lowering. 1600 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1601 Cond = CondLHS; 1602 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1603 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1604 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1605 } else 1606 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1607 } else { 1608 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1609 1610 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1611 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1612 1613 SDValue CmpOp = getValue(CB.CmpMHS); 1614 MVT VT = CmpOp.getValueType(); 1615 1616 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1617 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1618 } else { 1619 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1620 Cond = DAG.getSetCC(MVT::i1, SUB, 1621 DAG.getConstant(High-Low, VT), ISD::SETULE); 1622 } 1623 } 1624 1625 // Update successor info 1626 CurMBB->addSuccessor(CB.TrueBB); 1627 CurMBB->addSuccessor(CB.FalseBB); 1628 1629 // Set NextBlock to be the MBB immediately after the current one, if any. 1630 // This is used to avoid emitting unnecessary branches to the next block. 1631 MachineBasicBlock *NextBlock = 0; 1632 MachineFunction::iterator BBI = CurMBB; 1633 if (++BBI != CurMBB->getParent()->end()) 1634 NextBlock = BBI; 1635 1636 // If the lhs block is the next block, invert the condition so that we can 1637 // fall through to the lhs instead of the rhs block. 1638 if (CB.TrueBB == NextBlock) { 1639 std::swap(CB.TrueBB, CB.FalseBB); 1640 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1641 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1642 } 1643 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond, 1644 DAG.getBasicBlock(CB.TrueBB)); 1645 if (CB.FalseBB == NextBlock) 1646 DAG.setRoot(BrCond); 1647 else 1648 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1649 DAG.getBasicBlock(CB.FalseBB))); 1650} 1651 1652/// visitJumpTable - Emit JumpTable node in the current MBB 1653void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1654 // Emit the code for the jump table 1655 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1656 MVT PTy = TLI.getPointerTy(); 1657 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); 1658 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1659 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1660 Table, Index)); 1661 return; 1662} 1663 1664/// visitJumpTableHeader - This function emits necessary code to produce index 1665/// in the JumpTable from switch case. 1666void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1667 SelectionDAGISel::JumpTableHeader &JTH) { 1668 // Subtract the lowest switch case value from the value being switched on 1669 // and conditional branch to default mbb if the result is greater than the 1670 // difference between smallest and largest cases. 1671 SDValue SwitchOp = getValue(JTH.SValue); 1672 MVT VT = SwitchOp.getValueType(); 1673 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1674 DAG.getConstant(JTH.First, VT)); 1675 1676 // The SDNode we just created, which holds the value being switched on 1677 // minus the the smallest case value, needs to be copied to a virtual 1678 // register so it can be used as an index into the jump table in a 1679 // subsequent basic block. This value may be smaller or larger than the 1680 // target's pointer type, and therefore require extension or truncating. 1681 if (VT.bitsGT(TLI.getPointerTy())) 1682 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1683 else 1684 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1685 1686 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1687 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); 1688 JT.Reg = JumpTableReg; 1689 1690 // Emit the range check for the jump table, and branch to the default 1691 // block for the switch statement if the value being switched on exceeds 1692 // the largest case in the switch. 1693 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1694 DAG.getConstant(JTH.Last-JTH.First,VT), 1695 ISD::SETUGT); 1696 1697 // Set NextBlock to be the MBB immediately after the current one, if any. 1698 // This is used to avoid emitting unnecessary branches to the next block. 1699 MachineBasicBlock *NextBlock = 0; 1700 MachineFunction::iterator BBI = CurMBB; 1701 if (++BBI != CurMBB->getParent()->end()) 1702 NextBlock = BBI; 1703 1704 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1705 DAG.getBasicBlock(JT.Default)); 1706 1707 if (JT.MBB == NextBlock) 1708 DAG.setRoot(BrCond); 1709 else 1710 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1711 DAG.getBasicBlock(JT.MBB))); 1712 1713 return; 1714} 1715 1716/// visitBitTestHeader - This function emits necessary code to produce value 1717/// suitable for "bit tests" 1718void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1719 // Subtract the minimum value 1720 SDValue SwitchOp = getValue(B.SValue); 1721 MVT VT = SwitchOp.getValueType(); 1722 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1723 DAG.getConstant(B.First, VT)); 1724 1725 // Check range 1726 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1727 DAG.getConstant(B.Range, VT), 1728 ISD::SETUGT); 1729 1730 SDValue ShiftOp; 1731 if (VT.bitsGT(TLI.getShiftAmountTy())) 1732 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1733 else 1734 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1735 1736 // Make desired shift 1737 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1738 DAG.getConstant(1, TLI.getPointerTy()), 1739 ShiftOp); 1740 1741 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1742 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); 1743 B.Reg = SwitchReg; 1744 1745 // Set NextBlock to be the MBB immediately after the current one, if any. 1746 // This is used to avoid emitting unnecessary branches to the next block. 1747 MachineBasicBlock *NextBlock = 0; 1748 MachineFunction::iterator BBI = CurMBB; 1749 if (++BBI != CurMBB->getParent()->end()) 1750 NextBlock = BBI; 1751 1752 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1753 1754 CurMBB->addSuccessor(B.Default); 1755 CurMBB->addSuccessor(MBB); 1756 1757 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1758 DAG.getBasicBlock(B.Default)); 1759 1760 if (MBB == NextBlock) 1761 DAG.setRoot(BrRange); 1762 else 1763 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1764 DAG.getBasicBlock(MBB))); 1765 1766 return; 1767} 1768 1769/// visitBitTestCase - this function produces one "bit test" 1770void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1771 unsigned Reg, 1772 SelectionDAGISel::BitTestCase &B) { 1773 // Emit bit tests and jumps 1774 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, 1775 TLI.getPointerTy()); 1776 1777 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, 1778 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1779 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, 1780 DAG.getConstant(0, TLI.getPointerTy()), 1781 ISD::SETNE); 1782 1783 CurMBB->addSuccessor(B.TargetBB); 1784 CurMBB->addSuccessor(NextMBB); 1785 1786 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), 1787 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1788 1789 // Set NextBlock to be the MBB immediately after the current one, if any. 1790 // This is used to avoid emitting unnecessary branches to the next block. 1791 MachineBasicBlock *NextBlock = 0; 1792 MachineFunction::iterator BBI = CurMBB; 1793 if (++BBI != CurMBB->getParent()->end()) 1794 NextBlock = BBI; 1795 1796 if (NextMBB == NextBlock) 1797 DAG.setRoot(BrAnd); 1798 else 1799 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1800 DAG.getBasicBlock(NextMBB))); 1801 1802 return; 1803} 1804 1805void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1806 // Retrieve successors. 1807 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1808 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1809 1810 if (isa<InlineAsm>(I.getCalledValue())) 1811 visitInlineAsm(&I); 1812 else 1813 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1814 1815 // If the value of the invoke is used outside of its defining block, make it 1816 // available as a virtual register. 1817 if (!I.use_empty()) { 1818 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1819 if (VMI != FuncInfo.ValueMap.end()) 1820 CopyValueToVirtualRegister(&I, VMI->second); 1821 } 1822 1823 // Update successor info 1824 CurMBB->addSuccessor(Return); 1825 CurMBB->addSuccessor(LandingPad); 1826 1827 // Drop into normal successor. 1828 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1829 DAG.getBasicBlock(Return))); 1830} 1831 1832void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1833} 1834 1835/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1836/// small case ranges). 1837bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1838 CaseRecVector& WorkList, 1839 Value* SV, 1840 MachineBasicBlock* Default) { 1841 Case& BackCase = *(CR.Range.second-1); 1842 1843 // Size is the number of Cases represented by this range. 1844 unsigned Size = CR.Range.second - CR.Range.first; 1845 if (Size > 3) 1846 return false; 1847 1848 // Get the MachineFunction which holds the current MBB. This is used when 1849 // inserting any additional MBBs necessary to represent the switch. 1850 MachineFunction *CurMF = CurMBB->getParent(); 1851 1852 // Figure out which block is immediately after the current one. 1853 MachineBasicBlock *NextBlock = 0; 1854 MachineFunction::iterator BBI = CR.CaseBB; 1855 1856 if (++BBI != CurMBB->getParent()->end()) 1857 NextBlock = BBI; 1858 1859 // TODO: If any two of the cases has the same destination, and if one value 1860 // is the same as the other, but has one bit unset that the other has set, 1861 // use bit manipulation to do two compares at once. For example: 1862 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1863 1864 // Rearrange the case blocks so that the last one falls through if possible. 1865 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1866 // The last case block won't fall through into 'NextBlock' if we emit the 1867 // branches in this order. See if rearranging a case value would help. 1868 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1869 if (I->BB == NextBlock) { 1870 std::swap(*I, BackCase); 1871 break; 1872 } 1873 } 1874 } 1875 1876 // Create a CaseBlock record representing a conditional branch to 1877 // the Case's target mbb if the value being switched on SV is equal 1878 // to C. 1879 MachineBasicBlock *CurBlock = CR.CaseBB; 1880 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1881 MachineBasicBlock *FallThrough; 1882 if (I != E-1) { 1883 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1884 CurMF->insert(BBI, FallThrough); 1885 } else { 1886 // If the last case doesn't match, go to the default block. 1887 FallThrough = Default; 1888 } 1889 1890 Value *RHS, *LHS, *MHS; 1891 ISD::CondCode CC; 1892 if (I->High == I->Low) { 1893 // This is just small small case range :) containing exactly 1 case 1894 CC = ISD::SETEQ; 1895 LHS = SV; RHS = I->High; MHS = NULL; 1896 } else { 1897 CC = ISD::SETLE; 1898 LHS = I->Low; MHS = SV; RHS = I->High; 1899 } 1900 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1901 I->BB, FallThrough, CurBlock); 1902 1903 // If emitting the first comparison, just call visitSwitchCase to emit the 1904 // code into the current block. Otherwise, push the CaseBlock onto the 1905 // vector to be later processed by SDISel, and insert the node's MBB 1906 // before the next MBB. 1907 if (CurBlock == CurMBB) 1908 visitSwitchCase(CB); 1909 else 1910 SwitchCases.push_back(CB); 1911 1912 CurBlock = FallThrough; 1913 } 1914 1915 return true; 1916} 1917 1918static inline bool areJTsAllowed(const TargetLowering &TLI) { 1919 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1920 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1921} 1922 1923/// handleJTSwitchCase - Emit jumptable for current switch case range 1924bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1925 CaseRecVector& WorkList, 1926 Value* SV, 1927 MachineBasicBlock* Default) { 1928 Case& FrontCase = *CR.Range.first; 1929 Case& BackCase = *(CR.Range.second-1); 1930 1931 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1932 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1933 1934 uint64_t TSize = 0; 1935 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1936 I!=E; ++I) 1937 TSize += I->size(); 1938 1939 if (!areJTsAllowed(TLI) || TSize <= 3) 1940 return false; 1941 1942 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1943 if (Density < 0.4) 1944 return false; 1945 1946 DOUT << "Lowering jump table\n" 1947 << "First entry: " << First << ". Last entry: " << Last << "\n" 1948 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1949 1950 // Get the MachineFunction which holds the current MBB. This is used when 1951 // inserting any additional MBBs necessary to represent the switch. 1952 MachineFunction *CurMF = CurMBB->getParent(); 1953 1954 // Figure out which block is immediately after the current one. 1955 MachineBasicBlock *NextBlock = 0; 1956 MachineFunction::iterator BBI = CR.CaseBB; 1957 1958 if (++BBI != CurMBB->getParent()->end()) 1959 NextBlock = BBI; 1960 1961 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1962 1963 // Create a new basic block to hold the code for loading the address 1964 // of the jump table, and jumping to it. Update successor information; 1965 // we will either branch to the default case for the switch, or the jump 1966 // table. 1967 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1968 CurMF->insert(BBI, JumpTableBB); 1969 CR.CaseBB->addSuccessor(Default); 1970 CR.CaseBB->addSuccessor(JumpTableBB); 1971 1972 // Build a vector of destination BBs, corresponding to each target 1973 // of the jump table. If the value of the jump table slot corresponds to 1974 // a case statement, push the case's BB onto the vector, otherwise, push 1975 // the default BB. 1976 std::vector<MachineBasicBlock*> DestBBs; 1977 int64_t TEI = First; 1978 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1979 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1980 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1981 1982 if ((Low <= TEI) && (TEI <= High)) { 1983 DestBBs.push_back(I->BB); 1984 if (TEI==High) 1985 ++I; 1986 } else { 1987 DestBBs.push_back(Default); 1988 } 1989 } 1990 1991 // Update successor info. Add one edge to each unique successor. 1992 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1993 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1994 E = DestBBs.end(); I != E; ++I) { 1995 if (!SuccsHandled[(*I)->getNumber()]) { 1996 SuccsHandled[(*I)->getNumber()] = true; 1997 JumpTableBB->addSuccessor(*I); 1998 } 1999 } 2000 2001 // Create a jump table index for this jump table, or return an existing 2002 // one. 2003 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 2004 2005 // Set the jump table information so that we can codegen it as a second 2006 // MachineBasicBlock 2007 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 2008 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 2009 (CR.CaseBB == CurMBB)); 2010 if (CR.CaseBB == CurMBB) 2011 visitJumpTableHeader(JT, JTH); 2012 2013 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 2014 2015 return true; 2016} 2017 2018/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2019/// 2 subtrees. 2020bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 2021 CaseRecVector& WorkList, 2022 Value* SV, 2023 MachineBasicBlock* Default) { 2024 // Get the MachineFunction which holds the current MBB. This is used when 2025 // inserting any additional MBBs necessary to represent the switch. 2026 MachineFunction *CurMF = CurMBB->getParent(); 2027 2028 // Figure out which block is immediately after the current one. 2029 MachineBasicBlock *NextBlock = 0; 2030 MachineFunction::iterator BBI = CR.CaseBB; 2031 2032 if (++BBI != CurMBB->getParent()->end()) 2033 NextBlock = BBI; 2034 2035 Case& FrontCase = *CR.Range.first; 2036 Case& BackCase = *(CR.Range.second-1); 2037 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2038 2039 // Size is the number of Cases represented by this range. 2040 unsigned Size = CR.Range.second - CR.Range.first; 2041 2042 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 2043 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 2044 double FMetric = 0; 2045 CaseItr Pivot = CR.Range.first + Size/2; 2046 2047 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2048 // (heuristically) allow us to emit JumpTable's later. 2049 uint64_t TSize = 0; 2050 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2051 I!=E; ++I) 2052 TSize += I->size(); 2053 2054 uint64_t LSize = FrontCase.size(); 2055 uint64_t RSize = TSize-LSize; 2056 DOUT << "Selecting best pivot: \n" 2057 << "First: " << First << ", Last: " << Last <<"\n" 2058 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 2059 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2060 J!=E; ++I, ++J) { 2061 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 2062 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 2063 assert((RBegin-LEnd>=1) && "Invalid case distance"); 2064 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 2065 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 2066 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 2067 // Should always split in some non-trivial place 2068 DOUT <<"=>Step\n" 2069 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 2070 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 2071 << "Metric: " << Metric << "\n"; 2072 if (FMetric < Metric) { 2073 Pivot = J; 2074 FMetric = Metric; 2075 DOUT << "Current metric set to: " << FMetric << "\n"; 2076 } 2077 2078 LSize += J->size(); 2079 RSize -= J->size(); 2080 } 2081 if (areJTsAllowed(TLI)) { 2082 // If our case is dense we *really* should handle it earlier! 2083 assert((FMetric > 0) && "Should handle dense range earlier!"); 2084 } else { 2085 Pivot = CR.Range.first + Size/2; 2086 } 2087 2088 CaseRange LHSR(CR.Range.first, Pivot); 2089 CaseRange RHSR(Pivot, CR.Range.second); 2090 Constant *C = Pivot->Low; 2091 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2092 2093 // We know that we branch to the LHS if the Value being switched on is 2094 // less than the Pivot value, C. We use this to optimize our binary 2095 // tree a bit, by recognizing that if SV is greater than or equal to the 2096 // LHS's Case Value, and that Case Value is exactly one less than the 2097 // Pivot's Value, then we can branch directly to the LHS's Target, 2098 // rather than creating a leaf node for it. 2099 if ((LHSR.second - LHSR.first) == 1 && 2100 LHSR.first->High == CR.GE && 2101 cast<ConstantInt>(C)->getSExtValue() == 2102 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 2103 TrueBB = LHSR.first->BB; 2104 } else { 2105 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2106 CurMF->insert(BBI, TrueBB); 2107 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2108 } 2109 2110 // Similar to the optimization above, if the Value being switched on is 2111 // known to be less than the Constant CR.LT, and the current Case Value 2112 // is CR.LT - 1, then we can branch directly to the target block for 2113 // the current Case Value, rather than emitting a RHS leaf node for it. 2114 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2115 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 2116 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 2117 FalseBB = RHSR.first->BB; 2118 } else { 2119 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2120 CurMF->insert(BBI, FalseBB); 2121 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2122 } 2123 2124 // Create a CaseBlock record representing a conditional branch to 2125 // the LHS node if the value being switched on SV is less than C. 2126 // Otherwise, branch to LHS. 2127 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 2128 TrueBB, FalseBB, CR.CaseBB); 2129 2130 if (CR.CaseBB == CurMBB) 2131 visitSwitchCase(CB); 2132 else 2133 SwitchCases.push_back(CB); 2134 2135 return true; 2136} 2137 2138/// handleBitTestsSwitchCase - if current case range has few destination and 2139/// range span less, than machine word bitwidth, encode case range into series 2140/// of masks and emit bit tests with these masks. 2141bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 2142 CaseRecVector& WorkList, 2143 Value* SV, 2144 MachineBasicBlock* Default){ 2145 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits(); 2146 2147 Case& FrontCase = *CR.Range.first; 2148 Case& BackCase = *(CR.Range.second-1); 2149 2150 // Get the MachineFunction which holds the current MBB. This is used when 2151 // inserting any additional MBBs necessary to represent the switch. 2152 MachineFunction *CurMF = CurMBB->getParent(); 2153 2154 unsigned numCmps = 0; 2155 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2156 I!=E; ++I) { 2157 // Single case counts one, case range - two. 2158 if (I->Low == I->High) 2159 numCmps +=1; 2160 else 2161 numCmps +=2; 2162 } 2163 2164 // Count unique destinations 2165 SmallSet<MachineBasicBlock*, 4> Dests; 2166 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2167 Dests.insert(I->BB); 2168 if (Dests.size() > 3) 2169 // Don't bother the code below, if there are too much unique destinations 2170 return false; 2171 } 2172 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 2173 << "Total number of comparisons: " << numCmps << "\n"; 2174 2175 // Compute span of values. 2176 Constant* minValue = FrontCase.Low; 2177 Constant* maxValue = BackCase.High; 2178 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 2179 cast<ConstantInt>(minValue)->getSExtValue(); 2180 DOUT << "Compare range: " << range << "\n" 2181 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 2182 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 2183 2184 if (range>=IntPtrBits || 2185 (!(Dests.size() == 1 && numCmps >= 3) && 2186 !(Dests.size() == 2 && numCmps >= 5) && 2187 !(Dests.size() >= 3 && numCmps >= 6))) 2188 return false; 2189 2190 DOUT << "Emitting bit tests\n"; 2191 int64_t lowBound = 0; 2192 2193 // Optimize the case where all the case values fit in a 2194 // word without having to subtract minValue. In this case, 2195 // we can optimize away the subtraction. 2196 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 2197 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 2198 range = cast<ConstantInt>(maxValue)->getSExtValue(); 2199 } else { 2200 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 2201 } 2202 2203 CaseBitsVector CasesBits; 2204 unsigned i, count = 0; 2205 2206 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2207 MachineBasicBlock* Dest = I->BB; 2208 for (i = 0; i < count; ++i) 2209 if (Dest == CasesBits[i].BB) 2210 break; 2211 2212 if (i == count) { 2213 assert((count < 3) && "Too much destinations to test!"); 2214 CasesBits.push_back(CaseBits(0, Dest, 0)); 2215 count++; 2216 } 2217 2218 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 2219 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 2220 2221 for (uint64_t j = lo; j <= hi; j++) { 2222 CasesBits[i].Mask |= 1ULL << j; 2223 CasesBits[i].Bits++; 2224 } 2225 2226 } 2227 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2228 2229 SelectionDAGISel::BitTestInfo BTC; 2230 2231 // Figure out which block is immediately after the current one. 2232 MachineFunction::iterator BBI = CR.CaseBB; 2233 ++BBI; 2234 2235 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2236 2237 DOUT << "Cases:\n"; 2238 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2239 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 2240 << ", BB: " << CasesBits[i].BB << "\n"; 2241 2242 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2243 CurMF->insert(BBI, CaseBB); 2244 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 2245 CaseBB, 2246 CasesBits[i].BB)); 2247 } 2248 2249 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 2250 -1U, (CR.CaseBB == CurMBB), 2251 CR.CaseBB, Default, BTC); 2252 2253 if (CR.CaseBB == CurMBB) 2254 visitBitTestHeader(BTB); 2255 2256 BitTestCases.push_back(BTB); 2257 2258 return true; 2259} 2260 2261 2262/// Clusterify - Transform simple list of Cases into list of CaseRange's 2263unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2264 const SwitchInst& SI) { 2265 unsigned numCmps = 0; 2266 2267 // Start with "simple" cases 2268 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2269 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2270 Cases.push_back(Case(SI.getSuccessorValue(i), 2271 SI.getSuccessorValue(i), 2272 SMBB)); 2273 } 2274 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2275 2276 // Merge case into clusters 2277 if (Cases.size()>=2) 2278 // Must recompute end() each iteration because it may be 2279 // invalidated by erase if we hold on to it 2280 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2281 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2282 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2283 MachineBasicBlock* nextBB = J->BB; 2284 MachineBasicBlock* currentBB = I->BB; 2285 2286 // If the two neighboring cases go to the same destination, merge them 2287 // into a single case. 2288 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2289 I->High = J->High; 2290 J = Cases.erase(J); 2291 } else { 2292 I = J++; 2293 } 2294 } 2295 2296 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2297 if (I->Low != I->High) 2298 // A range counts double, since it requires two compares. 2299 ++numCmps; 2300 } 2301 2302 return numCmps; 2303} 2304 2305void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2306 // Figure out which block is immediately after the current one. 2307 MachineBasicBlock *NextBlock = 0; 2308 MachineFunction::iterator BBI = CurMBB; 2309 2310 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2311 2312 // If there is only the default destination, branch to it if it is not the 2313 // next basic block. Otherwise, just fall through. 2314 if (SI.getNumOperands() == 2) { 2315 // Update machine-CFG edges. 2316 2317 // If this is not a fall-through branch, emit the branch. 2318 CurMBB->addSuccessor(Default); 2319 if (Default != NextBlock) 2320 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 2321 DAG.getBasicBlock(Default))); 2322 2323 return; 2324 } 2325 2326 // If there are any non-default case statements, create a vector of Cases 2327 // representing each one, and sort the vector so that we can efficiently 2328 // create a binary search tree from them. 2329 CaseVector Cases; 2330 unsigned numCmps = Clusterify(Cases, SI); 2331 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2332 << ". Total compares: " << numCmps << "\n"; 2333 2334 // Get the Value to be switched on and default basic blocks, which will be 2335 // inserted into CaseBlock records, representing basic blocks in the binary 2336 // search tree. 2337 Value *SV = SI.getOperand(0); 2338 2339 // Push the initial CaseRec onto the worklist 2340 CaseRecVector WorkList; 2341 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2342 2343 while (!WorkList.empty()) { 2344 // Grab a record representing a case range to process off the worklist 2345 CaseRec CR = WorkList.back(); 2346 WorkList.pop_back(); 2347 2348 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2349 continue; 2350 2351 // If the range has few cases (two or less) emit a series of specific 2352 // tests. 2353 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2354 continue; 2355 2356 // If the switch has more than 5 blocks, and at least 40% dense, and the 2357 // target supports indirect branches, then emit a jump table rather than 2358 // lowering the switch to a binary tree of conditional branches. 2359 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2360 continue; 2361 2362 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2363 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2364 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2365 } 2366} 2367 2368 2369void SelectionDAGLowering::visitSub(User &I) { 2370 // -0.0 - X --> fneg 2371 const Type *Ty = I.getType(); 2372 if (isa<VectorType>(Ty)) { 2373 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2374 const VectorType *DestTy = cast<VectorType>(I.getType()); 2375 const Type *ElTy = DestTy->getElementType(); 2376 if (ElTy->isFloatingPoint()) { 2377 unsigned VL = DestTy->getNumElements(); 2378 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2379 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2380 if (CV == CNZ) { 2381 SDValue Op2 = getValue(I.getOperand(1)); 2382 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2383 return; 2384 } 2385 } 2386 } 2387 } 2388 if (Ty->isFloatingPoint()) { 2389 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2390 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2391 SDValue Op2 = getValue(I.getOperand(1)); 2392 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2393 return; 2394 } 2395 } 2396 2397 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2398} 2399 2400void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2401 SDValue Op1 = getValue(I.getOperand(0)); 2402 SDValue Op2 = getValue(I.getOperand(1)); 2403 2404 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2405} 2406 2407void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2408 SDValue Op1 = getValue(I.getOperand(0)); 2409 SDValue Op2 = getValue(I.getOperand(1)); 2410 if (!isa<VectorType>(I.getType())) { 2411 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) 2412 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2413 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) 2414 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2415 } 2416 2417 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2418} 2419 2420void SelectionDAGLowering::visitICmp(User &I) { 2421 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2422 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2423 predicate = IC->getPredicate(); 2424 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2425 predicate = ICmpInst::Predicate(IC->getPredicate()); 2426 SDValue Op1 = getValue(I.getOperand(0)); 2427 SDValue Op2 = getValue(I.getOperand(1)); 2428 ISD::CondCode Opcode; 2429 switch (predicate) { 2430 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2431 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2432 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2433 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2434 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2435 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2436 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2437 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2438 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2439 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2440 default: 2441 assert(!"Invalid ICmp predicate value"); 2442 Opcode = ISD::SETEQ; 2443 break; 2444 } 2445 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2446} 2447 2448void SelectionDAGLowering::visitFCmp(User &I) { 2449 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2450 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2451 predicate = FC->getPredicate(); 2452 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2453 predicate = FCmpInst::Predicate(FC->getPredicate()); 2454 SDValue Op1 = getValue(I.getOperand(0)); 2455 SDValue Op2 = getValue(I.getOperand(1)); 2456 ISD::CondCode Condition, FOC, FPC; 2457 switch (predicate) { 2458 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2459 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2460 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2461 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2462 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2463 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2464 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2465 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2466 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2467 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2468 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2469 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2470 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2471 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2472 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2473 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2474 default: 2475 assert(!"Invalid FCmp predicate value"); 2476 FOC = FPC = ISD::SETFALSE; 2477 break; 2478 } 2479 if (FiniteOnlyFPMath()) 2480 Condition = FOC; 2481 else 2482 Condition = FPC; 2483 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2484} 2485 2486void SelectionDAGLowering::visitVICmp(User &I) { 2487 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2488 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I)) 2489 predicate = IC->getPredicate(); 2490 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2491 predicate = ICmpInst::Predicate(IC->getPredicate()); 2492 SDValue Op1 = getValue(I.getOperand(0)); 2493 SDValue Op2 = getValue(I.getOperand(1)); 2494 ISD::CondCode Opcode; 2495 switch (predicate) { 2496 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2497 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2498 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2499 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2500 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2501 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2502 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2503 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2504 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2505 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2506 default: 2507 assert(!"Invalid ICmp predicate value"); 2508 Opcode = ISD::SETEQ; 2509 break; 2510 } 2511 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); 2512} 2513 2514void SelectionDAGLowering::visitVFCmp(User &I) { 2515 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2516 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I)) 2517 predicate = FC->getPredicate(); 2518 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2519 predicate = FCmpInst::Predicate(FC->getPredicate()); 2520 SDValue Op1 = getValue(I.getOperand(0)); 2521 SDValue Op2 = getValue(I.getOperand(1)); 2522 ISD::CondCode Condition, FOC, FPC; 2523 switch (predicate) { 2524 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2525 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2526 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2527 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2528 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2529 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2530 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2531 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2532 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2533 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2534 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2535 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2536 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2537 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2538 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2539 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2540 default: 2541 assert(!"Invalid VFCmp predicate value"); 2542 FOC = FPC = ISD::SETFALSE; 2543 break; 2544 } 2545 if (FiniteOnlyFPMath()) 2546 Condition = FOC; 2547 else 2548 Condition = FPC; 2549 2550 MVT DestVT = TLI.getValueType(I.getType()); 2551 2552 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); 2553} 2554 2555void SelectionDAGLowering::visitSelect(User &I) { 2556 SDValue Cond = getValue(I.getOperand(0)); 2557 SDValue TrueVal = getValue(I.getOperand(1)); 2558 SDValue FalseVal = getValue(I.getOperand(2)); 2559 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2560 TrueVal, FalseVal)); 2561} 2562 2563 2564void SelectionDAGLowering::visitTrunc(User &I) { 2565 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2566 SDValue N = getValue(I.getOperand(0)); 2567 MVT DestVT = TLI.getValueType(I.getType()); 2568 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2569} 2570 2571void SelectionDAGLowering::visitZExt(User &I) { 2572 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2573 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2574 SDValue N = getValue(I.getOperand(0)); 2575 MVT DestVT = TLI.getValueType(I.getType()); 2576 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2577} 2578 2579void SelectionDAGLowering::visitSExt(User &I) { 2580 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2581 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2582 SDValue N = getValue(I.getOperand(0)); 2583 MVT DestVT = TLI.getValueType(I.getType()); 2584 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2585} 2586 2587void SelectionDAGLowering::visitFPTrunc(User &I) { 2588 // FPTrunc is never a no-op cast, no need to check 2589 SDValue N = getValue(I.getOperand(0)); 2590 MVT DestVT = TLI.getValueType(I.getType()); 2591 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2592} 2593 2594void SelectionDAGLowering::visitFPExt(User &I){ 2595 // FPTrunc is never a no-op cast, no need to check 2596 SDValue N = getValue(I.getOperand(0)); 2597 MVT DestVT = TLI.getValueType(I.getType()); 2598 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2599} 2600 2601void SelectionDAGLowering::visitFPToUI(User &I) { 2602 // FPToUI is never a no-op cast, no need to check 2603 SDValue N = getValue(I.getOperand(0)); 2604 MVT DestVT = TLI.getValueType(I.getType()); 2605 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2606} 2607 2608void SelectionDAGLowering::visitFPToSI(User &I) { 2609 // FPToSI is never a no-op cast, no need to check 2610 SDValue N = getValue(I.getOperand(0)); 2611 MVT DestVT = TLI.getValueType(I.getType()); 2612 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2613} 2614 2615void SelectionDAGLowering::visitUIToFP(User &I) { 2616 // UIToFP is never a no-op cast, no need to check 2617 SDValue N = getValue(I.getOperand(0)); 2618 MVT DestVT = TLI.getValueType(I.getType()); 2619 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2620} 2621 2622void SelectionDAGLowering::visitSIToFP(User &I){ 2623 // UIToFP is never a no-op cast, no need to check 2624 SDValue N = getValue(I.getOperand(0)); 2625 MVT DestVT = TLI.getValueType(I.getType()); 2626 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2627} 2628 2629void SelectionDAGLowering::visitPtrToInt(User &I) { 2630 // What to do depends on the size of the integer and the size of the pointer. 2631 // We can either truncate, zero extend, or no-op, accordingly. 2632 SDValue N = getValue(I.getOperand(0)); 2633 MVT SrcVT = N.getValueType(); 2634 MVT DestVT = TLI.getValueType(I.getType()); 2635 SDValue Result; 2636 if (DestVT.bitsLT(SrcVT)) 2637 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2638 else 2639 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2640 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2641 setValue(&I, Result); 2642} 2643 2644void SelectionDAGLowering::visitIntToPtr(User &I) { 2645 // What to do depends on the size of the integer and the size of the pointer. 2646 // We can either truncate, zero extend, or no-op, accordingly. 2647 SDValue N = getValue(I.getOperand(0)); 2648 MVT SrcVT = N.getValueType(); 2649 MVT DestVT = TLI.getValueType(I.getType()); 2650 if (DestVT.bitsLT(SrcVT)) 2651 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2652 else 2653 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2654 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2655} 2656 2657void SelectionDAGLowering::visitBitCast(User &I) { 2658 SDValue N = getValue(I.getOperand(0)); 2659 MVT DestVT = TLI.getValueType(I.getType()); 2660 2661 // BitCast assures us that source and destination are the same size so this 2662 // is either a BIT_CONVERT or a no-op. 2663 if (DestVT != N.getValueType()) 2664 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2665 else 2666 setValue(&I, N); // noop cast. 2667} 2668 2669void SelectionDAGLowering::visitInsertElement(User &I) { 2670 SDValue InVec = getValue(I.getOperand(0)); 2671 SDValue InVal = getValue(I.getOperand(1)); 2672 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2673 getValue(I.getOperand(2))); 2674 2675 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2676 TLI.getValueType(I.getType()), 2677 InVec, InVal, InIdx)); 2678} 2679 2680void SelectionDAGLowering::visitExtractElement(User &I) { 2681 SDValue InVec = getValue(I.getOperand(0)); 2682 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2683 getValue(I.getOperand(1))); 2684 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2685 TLI.getValueType(I.getType()), InVec, InIdx)); 2686} 2687 2688void SelectionDAGLowering::visitShuffleVector(User &I) { 2689 SDValue V1 = getValue(I.getOperand(0)); 2690 SDValue V2 = getValue(I.getOperand(1)); 2691 SDValue Mask = getValue(I.getOperand(2)); 2692 2693 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2694 TLI.getValueType(I.getType()), 2695 V1, V2, Mask)); 2696} 2697 2698void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { 2699 const Value *Op0 = I.getOperand(0); 2700 const Value *Op1 = I.getOperand(1); 2701 const Type *AggTy = I.getType(); 2702 const Type *ValTy = Op1->getType(); 2703 bool IntoUndef = isa<UndefValue>(Op0); 2704 bool FromUndef = isa<UndefValue>(Op1); 2705 2706 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2707 I.idx_begin(), I.idx_end()); 2708 2709 SmallVector<MVT, 4> AggValueVTs; 2710 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2711 SmallVector<MVT, 4> ValValueVTs; 2712 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2713 2714 unsigned NumAggValues = AggValueVTs.size(); 2715 unsigned NumValValues = ValValueVTs.size(); 2716 SmallVector<SDValue, 4> Values(NumAggValues); 2717 2718 SDValue Agg = getValue(Op0); 2719 SDValue Val = getValue(Op1); 2720 unsigned i = 0; 2721 // Copy the beginning value(s) from the original aggregate. 2722 for (; i != LinearIndex; ++i) 2723 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2724 SDValue(Agg.Val, Agg.ResNo + i); 2725 // Copy values from the inserted value(s). 2726 for (; i != LinearIndex + NumValValues; ++i) 2727 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2728 SDValue(Val.Val, Val.ResNo + i - LinearIndex); 2729 // Copy remaining value(s) from the original aggregate. 2730 for (; i != NumAggValues; ++i) 2731 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2732 SDValue(Agg.Val, Agg.ResNo + i); 2733 2734 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues), 2735 &Values[0], NumAggValues)); 2736} 2737 2738void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { 2739 const Value *Op0 = I.getOperand(0); 2740 const Type *AggTy = Op0->getType(); 2741 const Type *ValTy = I.getType(); 2742 bool OutOfUndef = isa<UndefValue>(Op0); 2743 2744 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2745 I.idx_begin(), I.idx_end()); 2746 2747 SmallVector<MVT, 4> ValValueVTs; 2748 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2749 2750 unsigned NumValValues = ValValueVTs.size(); 2751 SmallVector<SDValue, 4> Values(NumValValues); 2752 2753 SDValue Agg = getValue(Op0); 2754 // Copy out the selected value(s). 2755 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2756 Values[i - LinearIndex] = 2757 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) : 2758 SDValue(Agg.Val, Agg.ResNo + i); 2759 2760 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues), 2761 &Values[0], NumValValues)); 2762} 2763 2764 2765void SelectionDAGLowering::visitGetElementPtr(User &I) { 2766 SDValue N = getValue(I.getOperand(0)); 2767 const Type *Ty = I.getOperand(0)->getType(); 2768 2769 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2770 OI != E; ++OI) { 2771 Value *Idx = *OI; 2772 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2773 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2774 if (Field) { 2775 // N = N + Offset 2776 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2777 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2778 DAG.getIntPtrConstant(Offset)); 2779 } 2780 Ty = StTy->getElementType(Field); 2781 } else { 2782 Ty = cast<SequentialType>(Ty)->getElementType(); 2783 2784 // If this is a constant subscript, handle it quickly. 2785 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2786 if (CI->getZExtValue() == 0) continue; 2787 uint64_t Offs = 2788 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2789 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2790 DAG.getIntPtrConstant(Offs)); 2791 continue; 2792 } 2793 2794 // N = N + Idx * ElementSize; 2795 uint64_t ElementSize = TD->getABITypeSize(Ty); 2796 SDValue IdxN = getValue(Idx); 2797 2798 // If the index is smaller or larger than intptr_t, truncate or extend 2799 // it. 2800 if (IdxN.getValueType().bitsLT(N.getValueType())) { 2801 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2802 } else if (IdxN.getValueType().bitsGT(N.getValueType())) 2803 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2804 2805 // If this is a multiply by a power of two, turn it into a shl 2806 // immediately. This is a very common case. 2807 if (isPowerOf2_64(ElementSize)) { 2808 unsigned Amt = Log2_64(ElementSize); 2809 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2810 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2811 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2812 continue; 2813 } 2814 2815 SDValue Scale = DAG.getIntPtrConstant(ElementSize); 2816 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2817 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2818 } 2819 } 2820 setValue(&I, N); 2821} 2822 2823void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2824 // If this is a fixed sized alloca in the entry block of the function, 2825 // allocate it statically on the stack. 2826 if (FuncInfo.StaticAllocaMap.count(&I)) 2827 return; // getValue will auto-populate this. 2828 2829 const Type *Ty = I.getAllocatedType(); 2830 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2831 unsigned Align = 2832 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2833 I.getAlignment()); 2834 2835 SDValue AllocSize = getValue(I.getArraySize()); 2836 MVT IntPtr = TLI.getPointerTy(); 2837 if (IntPtr.bitsLT(AllocSize.getValueType())) 2838 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2839 else if (IntPtr.bitsGT(AllocSize.getValueType())) 2840 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2841 2842 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2843 DAG.getIntPtrConstant(TySize)); 2844 2845 // Handle alignment. If the requested alignment is less than or equal to 2846 // the stack alignment, ignore it. If the size is greater than or equal to 2847 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2848 unsigned StackAlign = 2849 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2850 if (Align <= StackAlign) 2851 Align = 0; 2852 2853 // Round the size of the allocation up to the stack alignment size 2854 // by add SA-1 to the size. 2855 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2856 DAG.getIntPtrConstant(StackAlign-1)); 2857 // Mask out the low bits for alignment purposes. 2858 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2859 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2860 2861 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2862 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2863 MVT::Other); 2864 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2865 setValue(&I, DSA); 2866 DAG.setRoot(DSA.getValue(1)); 2867 2868 // Inform the Frame Information that we have just allocated a variable-sized 2869 // object. 2870 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2871} 2872 2873void SelectionDAGLowering::visitLoad(LoadInst &I) { 2874 const Value *SV = I.getOperand(0); 2875 SDValue Ptr = getValue(SV); 2876 2877 const Type *Ty = I.getType(); 2878 bool isVolatile = I.isVolatile(); 2879 unsigned Alignment = I.getAlignment(); 2880 2881 SmallVector<MVT, 4> ValueVTs; 2882 SmallVector<uint64_t, 4> Offsets; 2883 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2884 unsigned NumValues = ValueVTs.size(); 2885 if (NumValues == 0) 2886 return; 2887 2888 SDValue Root; 2889 bool ConstantMemory = false; 2890 if (I.isVolatile()) 2891 // Serialize volatile loads with other side effects. 2892 Root = getRoot(); 2893 else if (AA.pointsToConstantMemory(SV)) { 2894 // Do not serialize (non-volatile) loads of constant memory with anything. 2895 Root = DAG.getEntryNode(); 2896 ConstantMemory = true; 2897 } else { 2898 // Do not serialize non-volatile loads against each other. 2899 Root = DAG.getRoot(); 2900 } 2901 2902 SmallVector<SDValue, 4> Values(NumValues); 2903 SmallVector<SDValue, 4> Chains(NumValues); 2904 MVT PtrVT = Ptr.getValueType(); 2905 for (unsigned i = 0; i != NumValues; ++i) { 2906 SDValue L = DAG.getLoad(ValueVTs[i], Root, 2907 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2908 DAG.getConstant(Offsets[i], PtrVT)), 2909 SV, Offsets[i], 2910 isVolatile, Alignment); 2911 Values[i] = L; 2912 Chains[i] = L.getValue(1); 2913 } 2914 2915 if (!ConstantMemory) { 2916 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2917 &Chains[0], NumValues); 2918 if (isVolatile) 2919 DAG.setRoot(Chain); 2920 else 2921 PendingLoads.push_back(Chain); 2922 } 2923 2924 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), 2925 &Values[0], NumValues)); 2926} 2927 2928 2929void SelectionDAGLowering::visitStore(StoreInst &I) { 2930 Value *SrcV = I.getOperand(0); 2931 Value *PtrV = I.getOperand(1); 2932 2933 SmallVector<MVT, 4> ValueVTs; 2934 SmallVector<uint64_t, 4> Offsets; 2935 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2936 unsigned NumValues = ValueVTs.size(); 2937 if (NumValues == 0) 2938 return; 2939 2940 // Get the lowered operands. Note that we do this after 2941 // checking if NumResults is zero, because with zero results 2942 // the operands won't have values in the map. 2943 SDValue Src = getValue(SrcV); 2944 SDValue Ptr = getValue(PtrV); 2945 2946 SDValue Root = getRoot(); 2947 SmallVector<SDValue, 4> Chains(NumValues); 2948 MVT PtrVT = Ptr.getValueType(); 2949 bool isVolatile = I.isVolatile(); 2950 unsigned Alignment = I.getAlignment(); 2951 for (unsigned i = 0; i != NumValues; ++i) 2952 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i), 2953 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2954 DAG.getConstant(Offsets[i], PtrVT)), 2955 PtrV, Offsets[i], 2956 isVolatile, Alignment); 2957 2958 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues)); 2959} 2960 2961/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2962/// node. 2963void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2964 unsigned Intrinsic) { 2965 bool HasChain = !I.doesNotAccessMemory(); 2966 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2967 2968 // Build the operand list. 2969 SmallVector<SDValue, 8> Ops; 2970 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2971 if (OnlyLoad) { 2972 // We don't need to serialize loads against other loads. 2973 Ops.push_back(DAG.getRoot()); 2974 } else { 2975 Ops.push_back(getRoot()); 2976 } 2977 } 2978 2979 // Add the intrinsic ID as an integer operand. 2980 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2981 2982 // Add all operands of the call to the operand list. 2983 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2984 SDValue Op = getValue(I.getOperand(i)); 2985 assert(TLI.isTypeLegal(Op.getValueType()) && 2986 "Intrinsic uses a non-legal type?"); 2987 Ops.push_back(Op); 2988 } 2989 2990 std::vector<MVT> VTs; 2991 if (I.getType() != Type::VoidTy) { 2992 MVT VT = TLI.getValueType(I.getType()); 2993 if (VT.isVector()) { 2994 const VectorType *DestTy = cast<VectorType>(I.getType()); 2995 MVT EltVT = TLI.getValueType(DestTy->getElementType()); 2996 2997 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); 2998 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2999 } 3000 3001 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 3002 VTs.push_back(VT); 3003 } 3004 if (HasChain) 3005 VTs.push_back(MVT::Other); 3006 3007 const MVT *VTList = DAG.getNodeValueTypes(VTs); 3008 3009 // Create the node. 3010 SDValue Result; 3011 if (!HasChain) 3012 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 3013 &Ops[0], Ops.size()); 3014 else if (I.getType() != Type::VoidTy) 3015 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 3016 &Ops[0], Ops.size()); 3017 else 3018 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 3019 &Ops[0], Ops.size()); 3020 3021 if (HasChain) { 3022 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1); 3023 if (OnlyLoad) 3024 PendingLoads.push_back(Chain); 3025 else 3026 DAG.setRoot(Chain); 3027 } 3028 if (I.getType() != Type::VoidTy) { 3029 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3030 MVT VT = TLI.getValueType(PTy); 3031 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 3032 } 3033 setValue(&I, Result); 3034 } 3035} 3036 3037/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 3038static GlobalVariable *ExtractTypeInfo (Value *V) { 3039 V = V->stripPointerCasts(); 3040 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 3041 assert ((GV || isa<ConstantPointerNull>(V)) && 3042 "TypeInfo must be a global variable or NULL"); 3043 return GV; 3044} 3045 3046/// addCatchInfo - Extract the personality and type infos from an eh.selector 3047/// call, and add them to the specified machine basic block. 3048static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 3049 MachineBasicBlock *MBB) { 3050 // Inform the MachineModuleInfo of the personality for this landing pad. 3051 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 3052 assert(CE->getOpcode() == Instruction::BitCast && 3053 isa<Function>(CE->getOperand(0)) && 3054 "Personality should be a function"); 3055 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 3056 3057 // Gather all the type infos for this landing pad and pass them along to 3058 // MachineModuleInfo. 3059 std::vector<GlobalVariable *> TyInfo; 3060 unsigned N = I.getNumOperands(); 3061 3062 for (unsigned i = N - 1; i > 2; --i) { 3063 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 3064 unsigned FilterLength = CI->getZExtValue(); 3065 unsigned FirstCatch = i + FilterLength + !FilterLength; 3066 assert (FirstCatch <= N && "Invalid filter length"); 3067 3068 if (FirstCatch < N) { 3069 TyInfo.reserve(N - FirstCatch); 3070 for (unsigned j = FirstCatch; j < N; ++j) 3071 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3072 MMI->addCatchTypeInfo(MBB, TyInfo); 3073 TyInfo.clear(); 3074 } 3075 3076 if (!FilterLength) { 3077 // Cleanup. 3078 MMI->addCleanup(MBB); 3079 } else { 3080 // Filter. 3081 TyInfo.reserve(FilterLength - 1); 3082 for (unsigned j = i + 1; j < FirstCatch; ++j) 3083 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3084 MMI->addFilterTypeInfo(MBB, TyInfo); 3085 TyInfo.clear(); 3086 } 3087 3088 N = i; 3089 } 3090 } 3091 3092 if (N > 3) { 3093 TyInfo.reserve(N - 3); 3094 for (unsigned j = 3; j < N; ++j) 3095 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3096 MMI->addCatchTypeInfo(MBB, TyInfo); 3097 } 3098} 3099 3100 3101/// Inlined utility function to implement binary input atomic intrinsics for 3102// visitIntrinsicCall: I is a call instruction 3103// Op is the associated NodeType for I 3104const char * 3105SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { 3106 SDValue Root = getRoot(); 3107 SDValue L = DAG.getAtomic(Op, Root, 3108 getValue(I.getOperand(1)), 3109 getValue(I.getOperand(2)), 3110 I.getOperand(1)); 3111 setValue(&I, L); 3112 DAG.setRoot(L.getValue(1)); 3113 return 0; 3114} 3115 3116/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3117/// we want to emit this as a call to a named external function, return the name 3118/// otherwise lower it and return null. 3119const char * 3120SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 3121 switch (Intrinsic) { 3122 default: 3123 // By default, turn this into a target intrinsic node. 3124 visitTargetIntrinsic(I, Intrinsic); 3125 return 0; 3126 case Intrinsic::vastart: visitVAStart(I); return 0; 3127 case Intrinsic::vaend: visitVAEnd(I); return 0; 3128 case Intrinsic::vacopy: visitVACopy(I); return 0; 3129 case Intrinsic::returnaddress: 3130 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 3131 getValue(I.getOperand(1)))); 3132 return 0; 3133 case Intrinsic::frameaddress: 3134 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 3135 getValue(I.getOperand(1)))); 3136 return 0; 3137 case Intrinsic::setjmp: 3138 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3139 break; 3140 case Intrinsic::longjmp: 3141 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3142 break; 3143 case Intrinsic::memcpy_i32: 3144 case Intrinsic::memcpy_i64: { 3145 SDValue Op1 = getValue(I.getOperand(1)); 3146 SDValue Op2 = getValue(I.getOperand(2)); 3147 SDValue Op3 = getValue(I.getOperand(3)); 3148 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3149 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3150 I.getOperand(1), 0, I.getOperand(2), 0)); 3151 return 0; 3152 } 3153 case Intrinsic::memset_i32: 3154 case Intrinsic::memset_i64: { 3155 SDValue Op1 = getValue(I.getOperand(1)); 3156 SDValue Op2 = getValue(I.getOperand(2)); 3157 SDValue Op3 = getValue(I.getOperand(3)); 3158 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3159 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, 3160 I.getOperand(1), 0)); 3161 return 0; 3162 } 3163 case Intrinsic::memmove_i32: 3164 case Intrinsic::memmove_i64: { 3165 SDValue Op1 = getValue(I.getOperand(1)); 3166 SDValue Op2 = getValue(I.getOperand(2)); 3167 SDValue Op3 = getValue(I.getOperand(3)); 3168 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3169 3170 // If the source and destination are known to not be aliases, we can 3171 // lower memmove as memcpy. 3172 uint64_t Size = -1ULL; 3173 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3174 Size = C->getValue(); 3175 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3176 AliasAnalysis::NoAlias) { 3177 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3178 I.getOperand(1), 0, I.getOperand(2), 0)); 3179 return 0; 3180 } 3181 3182 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, 3183 I.getOperand(1), 0, I.getOperand(2), 0)); 3184 return 0; 3185 } 3186 case Intrinsic::dbg_stoppoint: { 3187 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3188 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 3189 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 3190 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 3191 assert(DD && "Not a debug information descriptor"); 3192 DAG.setRoot(DAG.getDbgStopPoint(getRoot(), 3193 SPI.getLine(), 3194 SPI.getColumn(), 3195 cast<CompileUnitDesc>(DD))); 3196 } 3197 3198 return 0; 3199 } 3200 case Intrinsic::dbg_region_start: { 3201 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3202 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 3203 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 3204 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 3205 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3206 } 3207 3208 return 0; 3209 } 3210 case Intrinsic::dbg_region_end: { 3211 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3212 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 3213 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 3214 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 3215 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3216 } 3217 3218 return 0; 3219 } 3220 case Intrinsic::dbg_func_start: { 3221 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3222 if (!MMI) return 0; 3223 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 3224 Value *SP = FSI.getSubprogram(); 3225 if (SP && MMI->Verify(SP)) { 3226 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 3227 // what (most?) gdb expects. 3228 DebugInfoDesc *DD = MMI->getDescFor(SP); 3229 assert(DD && "Not a debug information descriptor"); 3230 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 3231 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 3232 unsigned SrcFile = MMI->RecordSource(CompileUnit); 3233 // Record the source line but does create a label. It will be emitted 3234 // at asm emission time. 3235 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 3236 } 3237 3238 return 0; 3239 } 3240 case Intrinsic::dbg_declare: { 3241 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3242 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3243 Value *Variable = DI.getVariable(); 3244 if (MMI && Variable && MMI->Verify(Variable)) 3245 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 3246 getValue(DI.getAddress()), getValue(Variable))); 3247 return 0; 3248 } 3249 3250 case Intrinsic::eh_exception: { 3251 if (!CurMBB->isLandingPad()) { 3252 // FIXME: Mark exception register as live in. Hack for PR1508. 3253 unsigned Reg = TLI.getExceptionAddressRegister(); 3254 if (Reg) CurMBB->addLiveIn(Reg); 3255 } 3256 // Insert the EXCEPTIONADDR instruction. 3257 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3258 SDValue Ops[1]; 3259 Ops[0] = DAG.getRoot(); 3260 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 3261 setValue(&I, Op); 3262 DAG.setRoot(Op.getValue(1)); 3263 return 0; 3264 } 3265 3266 case Intrinsic::eh_selector_i32: 3267 case Intrinsic::eh_selector_i64: { 3268 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3269 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 3270 MVT::i32 : MVT::i64); 3271 3272 if (MMI) { 3273 if (CurMBB->isLandingPad()) 3274 addCatchInfo(I, MMI, CurMBB); 3275 else { 3276#ifndef NDEBUG 3277 FuncInfo.CatchInfoLost.insert(&I); 3278#endif 3279 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3280 unsigned Reg = TLI.getExceptionSelectorRegister(); 3281 if (Reg) CurMBB->addLiveIn(Reg); 3282 } 3283 3284 // Insert the EHSELECTION instruction. 3285 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 3286 SDValue Ops[2]; 3287 Ops[0] = getValue(I.getOperand(1)); 3288 Ops[1] = getRoot(); 3289 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 3290 setValue(&I, Op); 3291 DAG.setRoot(Op.getValue(1)); 3292 } else { 3293 setValue(&I, DAG.getConstant(0, VT)); 3294 } 3295 3296 return 0; 3297 } 3298 3299 case Intrinsic::eh_typeid_for_i32: 3300 case Intrinsic::eh_typeid_for_i64: { 3301 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3302 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 3303 MVT::i32 : MVT::i64); 3304 3305 if (MMI) { 3306 // Find the type id for the given typeinfo. 3307 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3308 3309 unsigned TypeID = MMI->getTypeIDFor(GV); 3310 setValue(&I, DAG.getConstant(TypeID, VT)); 3311 } else { 3312 // Return something different to eh_selector. 3313 setValue(&I, DAG.getConstant(1, VT)); 3314 } 3315 3316 return 0; 3317 } 3318 3319 case Intrinsic::eh_return: { 3320 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3321 3322 if (MMI) { 3323 MMI->setCallsEHReturn(true); 3324 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 3325 MVT::Other, 3326 getControlRoot(), 3327 getValue(I.getOperand(1)), 3328 getValue(I.getOperand(2)))); 3329 } else { 3330 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 3331 } 3332 3333 return 0; 3334 } 3335 3336 case Intrinsic::eh_unwind_init: { 3337 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3338 MMI->setCallsUnwindInit(true); 3339 } 3340 3341 return 0; 3342 } 3343 3344 case Intrinsic::eh_dwarf_cfa: { 3345 MVT VT = getValue(I.getOperand(1)).getValueType(); 3346 SDValue CfaArg; 3347 if (VT.bitsGT(TLI.getPointerTy())) 3348 CfaArg = DAG.getNode(ISD::TRUNCATE, 3349 TLI.getPointerTy(), getValue(I.getOperand(1))); 3350 else 3351 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 3352 TLI.getPointerTy(), getValue(I.getOperand(1))); 3353 3354 SDValue Offset = DAG.getNode(ISD::ADD, 3355 TLI.getPointerTy(), 3356 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 3357 TLI.getPointerTy()), 3358 CfaArg); 3359 setValue(&I, DAG.getNode(ISD::ADD, 3360 TLI.getPointerTy(), 3361 DAG.getNode(ISD::FRAMEADDR, 3362 TLI.getPointerTy(), 3363 DAG.getConstant(0, 3364 TLI.getPointerTy())), 3365 Offset)); 3366 return 0; 3367 } 3368 3369 case Intrinsic::sqrt: 3370 setValue(&I, DAG.getNode(ISD::FSQRT, 3371 getValue(I.getOperand(1)).getValueType(), 3372 getValue(I.getOperand(1)))); 3373 return 0; 3374 case Intrinsic::powi: 3375 setValue(&I, DAG.getNode(ISD::FPOWI, 3376 getValue(I.getOperand(1)).getValueType(), 3377 getValue(I.getOperand(1)), 3378 getValue(I.getOperand(2)))); 3379 return 0; 3380 case Intrinsic::sin: 3381 setValue(&I, DAG.getNode(ISD::FSIN, 3382 getValue(I.getOperand(1)).getValueType(), 3383 getValue(I.getOperand(1)))); 3384 return 0; 3385 case Intrinsic::cos: 3386 setValue(&I, DAG.getNode(ISD::FCOS, 3387 getValue(I.getOperand(1)).getValueType(), 3388 getValue(I.getOperand(1)))); 3389 return 0; 3390 case Intrinsic::pow: 3391 setValue(&I, DAG.getNode(ISD::FPOW, 3392 getValue(I.getOperand(1)).getValueType(), 3393 getValue(I.getOperand(1)), 3394 getValue(I.getOperand(2)))); 3395 return 0; 3396 case Intrinsic::pcmarker: { 3397 SDValue Tmp = getValue(I.getOperand(1)); 3398 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 3399 return 0; 3400 } 3401 case Intrinsic::readcyclecounter: { 3402 SDValue Op = getRoot(); 3403 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 3404 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 3405 &Op, 1); 3406 setValue(&I, Tmp); 3407 DAG.setRoot(Tmp.getValue(1)); 3408 return 0; 3409 } 3410 case Intrinsic::part_select: { 3411 // Currently not implemented: just abort 3412 assert(0 && "part_select intrinsic not implemented"); 3413 abort(); 3414 } 3415 case Intrinsic::part_set: { 3416 // Currently not implemented: just abort 3417 assert(0 && "part_set intrinsic not implemented"); 3418 abort(); 3419 } 3420 case Intrinsic::bswap: 3421 setValue(&I, DAG.getNode(ISD::BSWAP, 3422 getValue(I.getOperand(1)).getValueType(), 3423 getValue(I.getOperand(1)))); 3424 return 0; 3425 case Intrinsic::cttz: { 3426 SDValue Arg = getValue(I.getOperand(1)); 3427 MVT Ty = Arg.getValueType(); 3428 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg); 3429 setValue(&I, result); 3430 return 0; 3431 } 3432 case Intrinsic::ctlz: { 3433 SDValue Arg = getValue(I.getOperand(1)); 3434 MVT Ty = Arg.getValueType(); 3435 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg); 3436 setValue(&I, result); 3437 return 0; 3438 } 3439 case Intrinsic::ctpop: { 3440 SDValue Arg = getValue(I.getOperand(1)); 3441 MVT Ty = Arg.getValueType(); 3442 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg); 3443 setValue(&I, result); 3444 return 0; 3445 } 3446 case Intrinsic::stacksave: { 3447 SDValue Op = getRoot(); 3448 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, 3449 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 3450 setValue(&I, Tmp); 3451 DAG.setRoot(Tmp.getValue(1)); 3452 return 0; 3453 } 3454 case Intrinsic::stackrestore: { 3455 SDValue Tmp = getValue(I.getOperand(1)); 3456 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 3457 return 0; 3458 } 3459 case Intrinsic::var_annotation: 3460 // Discard annotate attributes 3461 return 0; 3462 3463 case Intrinsic::init_trampoline: { 3464 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 3465 3466 SDValue Ops[6]; 3467 Ops[0] = getRoot(); 3468 Ops[1] = getValue(I.getOperand(1)); 3469 Ops[2] = getValue(I.getOperand(2)); 3470 Ops[3] = getValue(I.getOperand(3)); 3471 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3472 Ops[5] = DAG.getSrcValue(F); 3473 3474 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, 3475 DAG.getNodeValueTypes(TLI.getPointerTy(), 3476 MVT::Other), 2, 3477 Ops, 6); 3478 3479 setValue(&I, Tmp); 3480 DAG.setRoot(Tmp.getValue(1)); 3481 return 0; 3482 } 3483 3484 case Intrinsic::gcroot: 3485 if (GCI) { 3486 Value *Alloca = I.getOperand(1); 3487 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3488 3489 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3490 GCI->addStackRoot(FI->getIndex(), TypeMap); 3491 } 3492 return 0; 3493 3494 case Intrinsic::gcread: 3495 case Intrinsic::gcwrite: 3496 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3497 return 0; 3498 3499 case Intrinsic::flt_rounds: { 3500 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3501 return 0; 3502 } 3503 3504 case Intrinsic::trap: { 3505 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3506 return 0; 3507 } 3508 case Intrinsic::prefetch: { 3509 SDValue Ops[4]; 3510 Ops[0] = getRoot(); 3511 Ops[1] = getValue(I.getOperand(1)); 3512 Ops[2] = getValue(I.getOperand(2)); 3513 Ops[3] = getValue(I.getOperand(3)); 3514 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4)); 3515 return 0; 3516 } 3517 3518 case Intrinsic::memory_barrier: { 3519 SDValue Ops[6]; 3520 Ops[0] = getRoot(); 3521 for (int x = 1; x < 6; ++x) 3522 Ops[x] = getValue(I.getOperand(x)); 3523 3524 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); 3525 return 0; 3526 } 3527 case Intrinsic::atomic_cmp_swap: { 3528 SDValue Root = getRoot(); 3529 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root, 3530 getValue(I.getOperand(1)), 3531 getValue(I.getOperand(2)), 3532 getValue(I.getOperand(3)), 3533 I.getOperand(1)); 3534 setValue(&I, L); 3535 DAG.setRoot(L.getValue(1)); 3536 return 0; 3537 } 3538 case Intrinsic::atomic_load_add: 3539 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 3540 case Intrinsic::atomic_load_sub: 3541 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 3542 case Intrinsic::atomic_load_and: 3543 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 3544 case Intrinsic::atomic_load_or: 3545 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 3546 case Intrinsic::atomic_load_xor: 3547 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 3548 case Intrinsic::atomic_load_nand: 3549 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 3550 case Intrinsic::atomic_load_min: 3551 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 3552 case Intrinsic::atomic_load_max: 3553 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 3554 case Intrinsic::atomic_load_umin: 3555 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 3556 case Intrinsic::atomic_load_umax: 3557 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 3558 case Intrinsic::atomic_swap: 3559 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 3560 } 3561} 3562 3563 3564void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, 3565 bool IsTailCall, 3566 MachineBasicBlock *LandingPad) { 3567 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3568 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3569 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3570 unsigned BeginLabel = 0, EndLabel = 0; 3571 3572 TargetLowering::ArgListTy Args; 3573 TargetLowering::ArgListEntry Entry; 3574 Args.reserve(CS.arg_size()); 3575 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3576 i != e; ++i) { 3577 SDValue ArgNode = getValue(*i); 3578 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3579 3580 unsigned attrInd = i - CS.arg_begin() + 1; 3581 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3582 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3583 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3584 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3585 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3586 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3587 Entry.Alignment = CS.getParamAlignment(attrInd); 3588 Args.push_back(Entry); 3589 } 3590 3591 if (LandingPad && MMI) { 3592 // Insert a label before the invoke call to mark the try range. This can be 3593 // used to detect deletion of the invoke via the MachineModuleInfo. 3594 BeginLabel = MMI->NextLabelID(); 3595 // Both PendingLoads and PendingExports must be flushed here; 3596 // this call might not return. 3597 (void)getRoot(); 3598 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); 3599 } 3600 3601 std::pair<SDValue,SDValue> Result = 3602 TLI.LowerCallTo(getRoot(), CS.getType(), 3603 CS.paramHasAttr(0, ParamAttr::SExt), 3604 CS.paramHasAttr(0, ParamAttr::ZExt), 3605 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3606 Callee, Args, DAG); 3607 if (CS.getType() != Type::VoidTy) 3608 setValue(CS.getInstruction(), Result.first); 3609 DAG.setRoot(Result.second); 3610 3611 if (LandingPad && MMI) { 3612 // Insert a label at the end of the invoke call to mark the try range. This 3613 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3614 EndLabel = MMI->NextLabelID(); 3615 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); 3616 3617 // Inform MachineModuleInfo of range. 3618 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3619 } 3620} 3621 3622 3623void SelectionDAGLowering::visitCall(CallInst &I) { 3624 const char *RenameFn = 0; 3625 if (Function *F = I.getCalledFunction()) { 3626 if (F->isDeclaration()) { 3627 if (unsigned IID = F->getIntrinsicID()) { 3628 RenameFn = visitIntrinsicCall(I, IID); 3629 if (!RenameFn) 3630 return; 3631 } 3632 } 3633 3634 // Check for well-known libc/libm calls. If the function is internal, it 3635 // can't be a library call. 3636 unsigned NameLen = F->getNameLen(); 3637 if (!F->hasInternalLinkage() && NameLen) { 3638 const char *NameStr = F->getNameStart(); 3639 if (NameStr[0] == 'c' && 3640 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3641 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3642 if (I.getNumOperands() == 3 && // Basic sanity checks. 3643 I.getOperand(1)->getType()->isFloatingPoint() && 3644 I.getType() == I.getOperand(1)->getType() && 3645 I.getType() == I.getOperand(2)->getType()) { 3646 SDValue LHS = getValue(I.getOperand(1)); 3647 SDValue RHS = getValue(I.getOperand(2)); 3648 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3649 LHS, RHS)); 3650 return; 3651 } 3652 } else if (NameStr[0] == 'f' && 3653 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3654 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3655 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3656 if (I.getNumOperands() == 2 && // Basic sanity checks. 3657 I.getOperand(1)->getType()->isFloatingPoint() && 3658 I.getType() == I.getOperand(1)->getType()) { 3659 SDValue Tmp = getValue(I.getOperand(1)); 3660 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3661 return; 3662 } 3663 } else if (NameStr[0] == 's' && 3664 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3665 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3666 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3667 if (I.getNumOperands() == 2 && // Basic sanity checks. 3668 I.getOperand(1)->getType()->isFloatingPoint() && 3669 I.getType() == I.getOperand(1)->getType()) { 3670 SDValue Tmp = getValue(I.getOperand(1)); 3671 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3672 return; 3673 } 3674 } else if (NameStr[0] == 'c' && 3675 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3676 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3677 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3678 if (I.getNumOperands() == 2 && // Basic sanity checks. 3679 I.getOperand(1)->getType()->isFloatingPoint() && 3680 I.getType() == I.getOperand(1)->getType()) { 3681 SDValue Tmp = getValue(I.getOperand(1)); 3682 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3683 return; 3684 } 3685 } 3686 } 3687 } else if (isa<InlineAsm>(I.getOperand(0))) { 3688 visitInlineAsm(&I); 3689 return; 3690 } 3691 3692 SDValue Callee; 3693 if (!RenameFn) 3694 Callee = getValue(I.getOperand(0)); 3695 else 3696 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3697 3698 LowerCallTo(&I, Callee, I.isTailCall()); 3699} 3700 3701 3702/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3703/// this value and returns the result as a ValueVT value. This uses 3704/// Chain/Flag as the input and updates them for the output Chain/Flag. 3705/// If the Flag pointer is NULL, no flag is used. 3706SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3707 SDValue &Chain, 3708 SDValue *Flag) const { 3709 // Assemble the legal parts into the final values. 3710 SmallVector<SDValue, 4> Values(ValueVTs.size()); 3711 SmallVector<SDValue, 8> Parts; 3712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3713 // Copy the legal parts from the registers. 3714 MVT ValueVT = ValueVTs[Value]; 3715 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 3716 MVT RegisterVT = RegVTs[Value]; 3717 3718 Parts.resize(NumRegs); 3719 for (unsigned i = 0; i != NumRegs; ++i) { 3720 SDValue P; 3721 if (Flag == 0) 3722 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); 3723 else { 3724 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); 3725 *Flag = P.getValue(2); 3726 } 3727 Chain = P.getValue(1); 3728 3729 // If the source register was virtual and if we know something about it, 3730 // add an assert node. 3731 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 3732 RegisterVT.isInteger() && !RegisterVT.isVector()) { 3733 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 3734 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 3735 if (FLI.LiveOutRegInfo.size() > SlotNo) { 3736 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 3737 3738 unsigned RegSize = RegisterVT.getSizeInBits(); 3739 unsigned NumSignBits = LOI.NumSignBits; 3740 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 3741 3742 // FIXME: We capture more information than the dag can represent. For 3743 // now, just use the tightest assertzext/assertsext possible. 3744 bool isSExt = true; 3745 MVT FromVT(MVT::Other); 3746 if (NumSignBits == RegSize) 3747 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 3748 else if (NumZeroBits >= RegSize-1) 3749 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 3750 else if (NumSignBits > RegSize-8) 3751 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 3752 else if (NumZeroBits >= RegSize-9) 3753 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 3754 else if (NumSignBits > RegSize-16) 3755 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 3756 else if (NumZeroBits >= RegSize-17) 3757 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 3758 else if (NumSignBits > RegSize-32) 3759 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 3760 else if (NumZeroBits >= RegSize-33) 3761 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 3762 3763 if (FromVT != MVT::Other) { 3764 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, 3765 RegisterVT, P, DAG.getValueType(FromVT)); 3766 3767 } 3768 } 3769 } 3770 3771 Parts[Part+i] = P; 3772 } 3773 3774 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT, 3775 ValueVT); 3776 Part += NumRegs; 3777 } 3778 3779 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 3780 &Values[0], ValueVTs.size()); 3781} 3782 3783/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3784/// specified value into the registers specified by this object. This uses 3785/// Chain/Flag as the input and updates them for the output Chain/Flag. 3786/// If the Flag pointer is NULL, no flag is used. 3787void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, 3788 SDValue &Chain, SDValue *Flag) const { 3789 // Get the list of the values's legal parts. 3790 unsigned NumRegs = Regs.size(); 3791 SmallVector<SDValue, 8> Parts(NumRegs); 3792 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3793 MVT ValueVT = ValueVTs[Value]; 3794 unsigned NumParts = TLI->getNumRegisters(ValueVT); 3795 MVT RegisterVT = RegVTs[Value]; 3796 3797 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value), 3798 &Parts[Part], NumParts, RegisterVT); 3799 Part += NumParts; 3800 } 3801 3802 // Copy the parts into the registers. 3803 SmallVector<SDValue, 8> Chains(NumRegs); 3804 for (unsigned i = 0; i != NumRegs; ++i) { 3805 SDValue Part; 3806 if (Flag == 0) 3807 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3808 else { 3809 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); 3810 *Flag = Part.getValue(1); 3811 } 3812 Chains[i] = Part.getValue(0); 3813 } 3814 3815 if (NumRegs == 1 || Flag) 3816 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 3817 // flagged to it. That is the CopyToReg nodes and the user are considered 3818 // a single scheduling unit. If we create a TokenFactor and return it as 3819 // chain, then the TokenFactor is both a predecessor (operand) of the 3820 // user as well as a successor (the TF operands are flagged to the user). 3821 // c1, f1 = CopyToReg 3822 // c2, f2 = CopyToReg 3823 // c3 = TokenFactor c1, c2 3824 // ... 3825 // = op c3, ..., f2 3826 Chain = Chains[NumRegs-1]; 3827 else 3828 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 3829} 3830 3831/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3832/// operand list. This adds the code marker and includes the number of 3833/// values added into it. 3834void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3835 std::vector<SDValue> &Ops) const { 3836 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3837 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3838 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 3839 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); 3840 MVT RegisterVT = RegVTs[Value]; 3841 for (unsigned i = 0; i != NumRegs; ++i) 3842 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 3843 } 3844} 3845 3846/// isAllocatableRegister - If the specified register is safe to allocate, 3847/// i.e. it isn't a stack pointer or some other special register, return the 3848/// register class for the register. Otherwise, return null. 3849static const TargetRegisterClass * 3850isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3851 const TargetLowering &TLI, 3852 const TargetRegisterInfo *TRI) { 3853 MVT FoundVT = MVT::Other; 3854 const TargetRegisterClass *FoundRC = 0; 3855 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3856 E = TRI->regclass_end(); RCI != E; ++RCI) { 3857 MVT ThisVT = MVT::Other; 3858 3859 const TargetRegisterClass *RC = *RCI; 3860 // If none of the the value types for this register class are valid, we 3861 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3862 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3863 I != E; ++I) { 3864 if (TLI.isTypeLegal(*I)) { 3865 // If we have already found this register in a different register class, 3866 // choose the one with the largest VT specified. For example, on 3867 // PowerPC, we favor f64 register classes over f32. 3868 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 3869 ThisVT = *I; 3870 break; 3871 } 3872 } 3873 } 3874 3875 if (ThisVT == MVT::Other) continue; 3876 3877 // NOTE: This isn't ideal. In particular, this might allocate the 3878 // frame pointer in functions that need it (due to them not being taken 3879 // out of allocation, because a variable sized allocation hasn't been seen 3880 // yet). This is a slight code pessimization, but should still work. 3881 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3882 E = RC->allocation_order_end(MF); I != E; ++I) 3883 if (*I == Reg) { 3884 // We found a matching register class. Keep looking at others in case 3885 // we find one with larger registers that this physreg is also in. 3886 FoundRC = RC; 3887 FoundVT = ThisVT; 3888 break; 3889 } 3890 } 3891 return FoundRC; 3892} 3893 3894 3895namespace { 3896/// AsmOperandInfo - This contains information for each constraint that we are 3897/// lowering. 3898struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 3899 /// CallOperand - If this is the result output operand or a clobber 3900 /// this is null, otherwise it is the incoming operand to the CallInst. 3901 /// This gets modified as the asm is processed. 3902 SDValue CallOperand; 3903 3904 /// AssignedRegs - If this is a register or register class operand, this 3905 /// contains the set of register corresponding to the operand. 3906 RegsForValue AssignedRegs; 3907 3908 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3909 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 3910 } 3911 3912 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3913 /// busy in OutputRegs/InputRegs. 3914 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3915 std::set<unsigned> &OutputRegs, 3916 std::set<unsigned> &InputRegs, 3917 const TargetRegisterInfo &TRI) const { 3918 if (isOutReg) { 3919 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3920 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 3921 } 3922 if (isInReg) { 3923 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3924 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 3925 } 3926 } 3927 3928private: 3929 /// MarkRegAndAliases - Mark the specified register and all aliases in the 3930 /// specified set. 3931 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 3932 const TargetRegisterInfo &TRI) { 3933 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 3934 Regs.insert(Reg); 3935 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 3936 for (; *Aliases; ++Aliases) 3937 Regs.insert(*Aliases); 3938 } 3939}; 3940} // end anon namespace. 3941 3942 3943/// GetRegistersForValue - Assign registers (virtual or physical) for the 3944/// specified operand. We prefer to assign virtual registers, to allow the 3945/// register allocator handle the assignment process. However, if the asm uses 3946/// features that we can't model on machineinstrs, we have SDISel do the 3947/// allocation. This produces generally horrible, but correct, code. 3948/// 3949/// OpInfo describes the operand. 3950/// HasEarlyClobber is true if there are any early clobber constraints (=&r) 3951/// or any explicitly clobbered registers. 3952/// Input and OutputRegs are the set of already allocated physical registers. 3953/// 3954void SelectionDAGLowering:: 3955GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 3956 std::set<unsigned> &OutputRegs, 3957 std::set<unsigned> &InputRegs) { 3958 // Compute whether this value requires an input register, an output register, 3959 // or both. 3960 bool isOutReg = false; 3961 bool isInReg = false; 3962 switch (OpInfo.Type) { 3963 case InlineAsm::isOutput: 3964 isOutReg = true; 3965 3966 // If this is an early-clobber output, or if there is an input 3967 // constraint that matches this, we need to reserve the input register 3968 // so no other inputs allocate to it. 3969 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3970 break; 3971 case InlineAsm::isInput: 3972 isInReg = true; 3973 isOutReg = false; 3974 break; 3975 case InlineAsm::isClobber: 3976 isOutReg = true; 3977 isInReg = true; 3978 break; 3979 } 3980 3981 3982 MachineFunction &MF = DAG.getMachineFunction(); 3983 SmallVector<unsigned, 4> Regs; 3984 3985 // If this is a constraint for a single physreg, or a constraint for a 3986 // register class, find it. 3987 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3988 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3989 OpInfo.ConstraintVT); 3990 3991 unsigned NumRegs = 1; 3992 if (OpInfo.ConstraintVT != MVT::Other) 3993 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3994 MVT RegVT; 3995 MVT ValueVT = OpInfo.ConstraintVT; 3996 3997 3998 // If this is a constraint for a specific physical register, like {r17}, 3999 // assign it now. 4000 if (PhysReg.first) { 4001 if (OpInfo.ConstraintVT == MVT::Other) 4002 ValueVT = *PhysReg.second->vt_begin(); 4003 4004 // Get the actual register value type. This is important, because the user 4005 // may have asked for (e.g.) the AX register in i32 type. We need to 4006 // remember that AX is actually i16 to get the right extension. 4007 RegVT = *PhysReg.second->vt_begin(); 4008 4009 // This is a explicit reference to a physical register. 4010 Regs.push_back(PhysReg.first); 4011 4012 // If this is an expanded reference, add the rest of the regs to Regs. 4013 if (NumRegs != 1) { 4014 TargetRegisterClass::iterator I = PhysReg.second->begin(); 4015 for (; *I != PhysReg.first; ++I) 4016 assert(I != PhysReg.second->end() && "Didn't find reg!"); 4017 4018 // Already added the first reg. 4019 --NumRegs; ++I; 4020 for (; NumRegs; --NumRegs, ++I) { 4021 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); 4022 Regs.push_back(*I); 4023 } 4024 } 4025 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4026 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4027 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4028 return; 4029 } 4030 4031 // Otherwise, if this was a reference to an LLVM register class, create vregs 4032 // for this reference. 4033 std::vector<unsigned> RegClassRegs; 4034 const TargetRegisterClass *RC = PhysReg.second; 4035 if (RC) { 4036 // If this is an early clobber or tied register, our regalloc doesn't know 4037 // how to maintain the constraint. If it isn't, go ahead and create vreg 4038 // and let the regalloc do the right thing. 4039 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 4040 // If there is some other early clobber and this is an input register, 4041 // then we are forced to pre-allocate the input reg so it doesn't 4042 // conflict with the earlyclobber. 4043 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 4044 RegVT = *PhysReg.second->vt_begin(); 4045 4046 if (OpInfo.ConstraintVT == MVT::Other) 4047 ValueVT = RegVT; 4048 4049 // Create the appropriate number of virtual registers. 4050 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4051 for (; NumRegs; --NumRegs) 4052 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 4053 4054 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4055 return; 4056 } 4057 4058 // Otherwise, we can't allocate it. Let the code below figure out how to 4059 // maintain these constraints. 4060 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 4061 4062 } else { 4063 // This is a reference to a register class that doesn't directly correspond 4064 // to an LLVM register class. Allocate NumRegs consecutive, available, 4065 // registers from the class. 4066 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 4067 OpInfo.ConstraintVT); 4068 } 4069 4070 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4071 unsigned NumAllocated = 0; 4072 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 4073 unsigned Reg = RegClassRegs[i]; 4074 // See if this register is available. 4075 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 4076 (isInReg && InputRegs.count(Reg))) { // Already used. 4077 // Make sure we find consecutive registers. 4078 NumAllocated = 0; 4079 continue; 4080 } 4081 4082 // Check to see if this register is allocatable (i.e. don't give out the 4083 // stack pointer). 4084 if (RC == 0) { 4085 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 4086 if (!RC) { // Couldn't allocate this register. 4087 // Reset NumAllocated to make sure we return consecutive registers. 4088 NumAllocated = 0; 4089 continue; 4090 } 4091 } 4092 4093 // Okay, this register is good, we can use it. 4094 ++NumAllocated; 4095 4096 // If we allocated enough consecutive registers, succeed. 4097 if (NumAllocated == NumRegs) { 4098 unsigned RegStart = (i-NumAllocated)+1; 4099 unsigned RegEnd = i+1; 4100 // Mark all of the allocated registers used. 4101 for (unsigned i = RegStart; i != RegEnd; ++i) 4102 Regs.push_back(RegClassRegs[i]); 4103 4104 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 4105 OpInfo.ConstraintVT); 4106 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4107 return; 4108 } 4109 } 4110 4111 // Otherwise, we couldn't allocate enough registers for this. 4112} 4113 4114 4115/// visitInlineAsm - Handle a call to an InlineAsm object. 4116/// 4117void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 4118 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 4119 4120 /// ConstraintOperands - Information about all of the constraints. 4121 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 4122 4123 SDValue Chain = getRoot(); 4124 SDValue Flag; 4125 4126 std::set<unsigned> OutputRegs, InputRegs; 4127 4128 // Do a prepass over the constraints, canonicalizing them, and building up the 4129 // ConstraintOperands list. 4130 std::vector<InlineAsm::ConstraintInfo> 4131 ConstraintInfos = IA->ParseConstraints(); 4132 4133 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 4134 // constraint. If so, we can't let the register allocator allocate any input 4135 // registers, because it will not know to avoid the earlyclobbered output reg. 4136 bool SawEarlyClobber = false; 4137 4138 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 4139 unsigned ResNo = 0; // ResNo - The result number of the next output. 4140 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 4141 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 4142 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 4143 4144 MVT OpVT = MVT::Other; 4145 4146 // Compute the value type for each operand. 4147 switch (OpInfo.Type) { 4148 case InlineAsm::isOutput: 4149 // Indirect outputs just consume an argument. 4150 if (OpInfo.isIndirect) { 4151 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4152 break; 4153 } 4154 // The return value of the call is this value. As such, there is no 4155 // corresponding argument. 4156 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4157 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 4158 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 4159 } else { 4160 assert(ResNo == 0 && "Asm only has one result!"); 4161 OpVT = TLI.getValueType(CS.getType()); 4162 } 4163 ++ResNo; 4164 break; 4165 case InlineAsm::isInput: 4166 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4167 break; 4168 case InlineAsm::isClobber: 4169 // Nothing to do. 4170 break; 4171 } 4172 4173 // If this is an input or an indirect output, process the call argument. 4174 // BasicBlocks are labels, currently appearing only in asm's. 4175 if (OpInfo.CallOperandVal) { 4176 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) 4177 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 4178 else { 4179 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 4180 const Type *OpTy = OpInfo.CallOperandVal->getType(); 4181 // If this is an indirect operand, the operand is a pointer to the 4182 // accessed type. 4183 if (OpInfo.isIndirect) 4184 OpTy = cast<PointerType>(OpTy)->getElementType(); 4185 4186 // If OpTy is not a single value, it may be a struct/union that we 4187 // can tile with integers. 4188 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4189 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4190 switch (BitSize) { 4191 default: break; 4192 case 1: 4193 case 8: 4194 case 16: 4195 case 32: 4196 case 64: 4197 OpTy = IntegerType::get(BitSize); 4198 break; 4199 } 4200 } 4201 4202 OpVT = TLI.getValueType(OpTy, true); 4203 } 4204 } 4205 4206 OpInfo.ConstraintVT = OpVT; 4207 4208 // Compute the constraint code and ConstraintType to use. 4209 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 4210 4211 // Keep track of whether we see an earlyclobber. 4212 SawEarlyClobber |= OpInfo.isEarlyClobber; 4213 4214 // If we see a clobber of a register, it is an early clobber. 4215 if (!SawEarlyClobber && 4216 OpInfo.Type == InlineAsm::isClobber && 4217 OpInfo.ConstraintType == TargetLowering::C_Register) { 4218 // Note that we want to ignore things that we don't trick here, like 4219 // dirflag, fpsr, flags, etc. 4220 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 4221 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 4222 OpInfo.ConstraintVT); 4223 if (PhysReg.first || PhysReg.second) { 4224 // This is a register we know of. 4225 SawEarlyClobber = true; 4226 } 4227 } 4228 4229 // If this is a memory input, and if the operand is not indirect, do what we 4230 // need to to provide an address for the memory input. 4231 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 4232 !OpInfo.isIndirect) { 4233 assert(OpInfo.Type == InlineAsm::isInput && 4234 "Can only indirectify direct input operands!"); 4235 4236 // Memory operands really want the address of the value. If we don't have 4237 // an indirect input, put it in the constpool if we can, otherwise spill 4238 // it to a stack slot. 4239 4240 // If the operand is a float, integer, or vector constant, spill to a 4241 // constant pool entry to get its address. 4242 Value *OpVal = OpInfo.CallOperandVal; 4243 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 4244 isa<ConstantVector>(OpVal)) { 4245 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 4246 TLI.getPointerTy()); 4247 } else { 4248 // Otherwise, create a stack slot and emit a store to it before the 4249 // asm. 4250 const Type *Ty = OpVal->getType(); 4251 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 4252 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 4253 MachineFunction &MF = DAG.getMachineFunction(); 4254 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 4255 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4256 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 4257 OpInfo.CallOperand = StackSlot; 4258 } 4259 4260 // There is no longer a Value* corresponding to this operand. 4261 OpInfo.CallOperandVal = 0; 4262 // It is now an indirect operand. 4263 OpInfo.isIndirect = true; 4264 } 4265 4266 // If this constraint is for a specific register, allocate it before 4267 // anything else. 4268 if (OpInfo.ConstraintType == TargetLowering::C_Register) 4269 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4270 } 4271 ConstraintInfos.clear(); 4272 4273 4274 // Second pass - Loop over all of the operands, assigning virtual or physregs 4275 // to registerclass operands. 4276 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4277 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4278 4279 // C_Register operands have already been allocated, Other/Memory don't need 4280 // to be. 4281 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 4282 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4283 } 4284 4285 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 4286 std::vector<SDValue> AsmNodeOperands; 4287 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 4288 AsmNodeOperands.push_back( 4289 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 4290 4291 4292 // Loop over all of the inputs, copying the operand values into the 4293 // appropriate registers and processing the output regs. 4294 RegsForValue RetValRegs; 4295 4296 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 4297 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 4298 4299 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4300 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4301 4302 switch (OpInfo.Type) { 4303 case InlineAsm::isOutput: { 4304 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 4305 OpInfo.ConstraintType != TargetLowering::C_Register) { 4306 // Memory output, or 'other' output (e.g. 'X' constraint). 4307 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 4308 4309 // Add information to the INLINEASM node to know about this output. 4310 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4311 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4312 TLI.getPointerTy())); 4313 AsmNodeOperands.push_back(OpInfo.CallOperand); 4314 break; 4315 } 4316 4317 // Otherwise, this is a register or register class output. 4318 4319 // Copy the output from the appropriate register. Find a register that 4320 // we can use. 4321 if (OpInfo.AssignedRegs.Regs.empty()) { 4322 cerr << "Couldn't allocate output reg for constraint '" 4323 << OpInfo.ConstraintCode << "'!\n"; 4324 exit(1); 4325 } 4326 4327 // If this is an indirect operand, store through the pointer after the 4328 // asm. 4329 if (OpInfo.isIndirect) { 4330 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 4331 OpInfo.CallOperandVal)); 4332 } else { 4333 // This is the result value of the call. 4334 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4335 // Concatenate this output onto the outputs list. 4336 RetValRegs.append(OpInfo.AssignedRegs); 4337 } 4338 4339 // Add information to the INLINEASM node to know that this register is 4340 // set. 4341 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 4342 AsmNodeOperands); 4343 break; 4344 } 4345 case InlineAsm::isInput: { 4346 SDValue InOperandVal = OpInfo.CallOperand; 4347 4348 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 4349 // If this is required to match an output register we have already set, 4350 // just use its register. 4351 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 4352 4353 // Scan until we find the definition we already emitted of this operand. 4354 // When we find it, create a RegsForValue operand. 4355 unsigned CurOp = 2; // The first operand. 4356 for (; OperandNo; --OperandNo) { 4357 // Advance to the next operand. 4358 unsigned NumOps = 4359 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4360 assert(((NumOps & 7) == 2 /*REGDEF*/ || 4361 (NumOps & 7) == 4 /*MEM*/) && 4362 "Skipped past definitions?"); 4363 CurOp += (NumOps>>3)+1; 4364 } 4365 4366 unsigned NumOps = 4367 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4368 if ((NumOps & 7) == 2 /*REGDEF*/) { 4369 // Add NumOps>>3 registers to MatchedRegs. 4370 RegsForValue MatchedRegs; 4371 MatchedRegs.TLI = &TLI; 4372 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 4373 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType()); 4374 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 4375 unsigned Reg = 4376 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 4377 MatchedRegs.Regs.push_back(Reg); 4378 } 4379 4380 // Use the produced MatchedRegs object to 4381 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4382 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 4383 break; 4384 } else { 4385 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 4386 assert((NumOps >> 3) == 1 && "Unexpected number of operands"); 4387 // Add information to the INLINEASM node to know about this input. 4388 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4389 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4390 TLI.getPointerTy())); 4391 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 4392 break; 4393 } 4394 } 4395 4396 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 4397 assert(!OpInfo.isIndirect && 4398 "Don't know how to handle indirect other inputs yet!"); 4399 4400 std::vector<SDValue> Ops; 4401 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 4402 Ops, DAG); 4403 if (Ops.empty()) { 4404 cerr << "Invalid operand for inline asm constraint '" 4405 << OpInfo.ConstraintCode << "'!\n"; 4406 exit(1); 4407 } 4408 4409 // Add information to the INLINEASM node to know about this input. 4410 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 4411 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4412 TLI.getPointerTy())); 4413 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 4414 break; 4415 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 4416 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 4417 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 4418 "Memory operands expect pointer values"); 4419 4420 // Add information to the INLINEASM node to know about this input. 4421 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4422 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4423 TLI.getPointerTy())); 4424 AsmNodeOperands.push_back(InOperandVal); 4425 break; 4426 } 4427 4428 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 4429 OpInfo.ConstraintType == TargetLowering::C_Register) && 4430 "Unknown constraint type!"); 4431 assert(!OpInfo.isIndirect && 4432 "Don't know how to handle indirect register inputs yet!"); 4433 4434 // Copy the input into the appropriate registers. 4435 assert(!OpInfo.AssignedRegs.Regs.empty() && 4436 "Couldn't allocate input reg!"); 4437 4438 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4439 4440 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 4441 AsmNodeOperands); 4442 break; 4443 } 4444 case InlineAsm::isClobber: { 4445 // Add the clobbered value to the operand list, so that the register 4446 // allocator is aware that the physreg got clobbered. 4447 if (!OpInfo.AssignedRegs.Regs.empty()) 4448 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 4449 AsmNodeOperands); 4450 break; 4451 } 4452 } 4453 } 4454 4455 // Finish up input operands. 4456 AsmNodeOperands[0] = Chain; 4457 if (Flag.Val) AsmNodeOperands.push_back(Flag); 4458 4459 Chain = DAG.getNode(ISD::INLINEASM, 4460 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 4461 &AsmNodeOperands[0], AsmNodeOperands.size()); 4462 Flag = Chain.getValue(1); 4463 4464 // If this asm returns a register value, copy the result from that register 4465 // and set it as the value of the call. 4466 if (!RetValRegs.Regs.empty()) { 4467 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 4468 4469 // If any of the results of the inline asm is a vector, it may have the 4470 // wrong width/num elts. This can happen for register classes that can 4471 // contain multiple different value types. The preg or vreg allocated may 4472 // not have the same VT as was expected. Convert it to the right type with 4473 // bit_convert. 4474 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) { 4475 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) { 4476 if (Val.Val->getValueType(i).isVector()) 4477 Val = DAG.getNode(ISD::BIT_CONVERT, 4478 TLI.getValueType(ResSTy->getElementType(i)), Val); 4479 } 4480 } else { 4481 if (Val.getValueType().isVector()) 4482 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()), 4483 Val); 4484 } 4485 4486 setValue(CS.getInstruction(), Val); 4487 } 4488 4489 std::vector<std::pair<SDValue, Value*> > StoresToEmit; 4490 4491 // Process indirect outputs, first output all of the flagged copies out of 4492 // physregs. 4493 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 4494 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 4495 Value *Ptr = IndirectStoresToEmit[i].second; 4496 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 4497 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 4498 } 4499 4500 // Emit the non-flagged stores from the physregs. 4501 SmallVector<SDValue, 8> OutChains; 4502 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 4503 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 4504 getValue(StoresToEmit[i].second), 4505 StoresToEmit[i].second, 0)); 4506 if (!OutChains.empty()) 4507 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4508 &OutChains[0], OutChains.size()); 4509 DAG.setRoot(Chain); 4510} 4511 4512 4513void SelectionDAGLowering::visitMalloc(MallocInst &I) { 4514 SDValue Src = getValue(I.getOperand(0)); 4515 4516 MVT IntPtr = TLI.getPointerTy(); 4517 4518 if (IntPtr.bitsLT(Src.getValueType())) 4519 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 4520 else if (IntPtr.bitsGT(Src.getValueType())) 4521 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 4522 4523 // Scale the source by the type size. 4524 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 4525 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 4526 Src, DAG.getIntPtrConstant(ElementSize)); 4527 4528 TargetLowering::ArgListTy Args; 4529 TargetLowering::ArgListEntry Entry; 4530 Entry.Node = Src; 4531 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4532 Args.push_back(Entry); 4533 4534 std::pair<SDValue,SDValue> Result = 4535 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C, 4536 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG); 4537 setValue(&I, Result.first); // Pointers always fit in registers 4538 DAG.setRoot(Result.second); 4539} 4540 4541void SelectionDAGLowering::visitFree(FreeInst &I) { 4542 TargetLowering::ArgListTy Args; 4543 TargetLowering::ArgListEntry Entry; 4544 Entry.Node = getValue(I.getOperand(0)); 4545 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4546 Args.push_back(Entry); 4547 MVT IntPtr = TLI.getPointerTy(); 4548 std::pair<SDValue,SDValue> Result = 4549 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, 4550 CallingConv::C, true, 4551 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 4552 DAG.setRoot(Result.second); 4553} 4554 4555// EmitInstrWithCustomInserter - This method should be implemented by targets 4556// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 4557// instructions are special in various ways, which require special support to 4558// insert. The specified MachineInstr is created but not inserted into any 4559// basic blocks, and the scheduler passes ownership of it to this method. 4560MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4561 MachineBasicBlock *MBB) { 4562 cerr << "If a target marks an instruction with " 4563 << "'usesCustomDAGSchedInserter', it must implement " 4564 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 4565 abort(); 4566 return 0; 4567} 4568 4569void SelectionDAGLowering::visitVAStart(CallInst &I) { 4570 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 4571 getValue(I.getOperand(1)), 4572 DAG.getSrcValue(I.getOperand(1)))); 4573} 4574 4575void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 4576 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 4577 getValue(I.getOperand(0)), 4578 DAG.getSrcValue(I.getOperand(0))); 4579 setValue(&I, V); 4580 DAG.setRoot(V.getValue(1)); 4581} 4582 4583void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4584 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4585 getValue(I.getOperand(1)), 4586 DAG.getSrcValue(I.getOperand(1)))); 4587} 4588 4589void SelectionDAGLowering::visitVACopy(CallInst &I) { 4590 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4591 getValue(I.getOperand(1)), 4592 getValue(I.getOperand(2)), 4593 DAG.getSrcValue(I.getOperand(1)), 4594 DAG.getSrcValue(I.getOperand(2)))); 4595} 4596 4597/// TargetLowering::LowerArguments - This is the default LowerArguments 4598/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4599/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4600/// integrated into SDISel. 4601void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, 4602 SmallVectorImpl<SDValue> &ArgValues) { 4603 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4604 SmallVector<SDValue, 3+16> Ops; 4605 Ops.push_back(DAG.getRoot()); 4606 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4607 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4608 4609 // Add one result value for each formal argument. 4610 SmallVector<MVT, 16> RetVals; 4611 unsigned j = 1; 4612 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4613 I != E; ++I, ++j) { 4614 SmallVector<MVT, 4> ValueVTs; 4615 ComputeValueVTs(*this, I->getType(), ValueVTs); 4616 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4617 Value != NumValues; ++Value) { 4618 MVT VT = ValueVTs[Value]; 4619 const Type *ArgTy = VT.getTypeForMVT(); 4620 ISD::ArgFlagsTy Flags; 4621 unsigned OriginalAlignment = 4622 getTargetData()->getABITypeAlignment(ArgTy); 4623 4624 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4625 Flags.setZExt(); 4626 if (F.paramHasAttr(j, ParamAttr::SExt)) 4627 Flags.setSExt(); 4628 if (F.paramHasAttr(j, ParamAttr::InReg)) 4629 Flags.setInReg(); 4630 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4631 Flags.setSRet(); 4632 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4633 Flags.setByVal(); 4634 const PointerType *Ty = cast<PointerType>(I->getType()); 4635 const Type *ElementTy = Ty->getElementType(); 4636 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4637 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4638 // For ByVal, alignment should be passed from FE. BE will guess if 4639 // this info is not there but there are cases it cannot get right. 4640 if (F.getParamAlignment(j)) 4641 FrameAlign = F.getParamAlignment(j); 4642 Flags.setByValAlign(FrameAlign); 4643 Flags.setByValSize(FrameSize); 4644 } 4645 if (F.paramHasAttr(j, ParamAttr::Nest)) 4646 Flags.setNest(); 4647 Flags.setOrigAlign(OriginalAlignment); 4648 4649 MVT RegisterVT = getRegisterType(VT); 4650 unsigned NumRegs = getNumRegisters(VT); 4651 for (unsigned i = 0; i != NumRegs; ++i) { 4652 RetVals.push_back(RegisterVT); 4653 ISD::ArgFlagsTy MyFlags = Flags; 4654 if (NumRegs > 1 && i == 0) 4655 MyFlags.setSplit(); 4656 // if it isn't first piece, alignment must be 1 4657 else if (i > 0) 4658 MyFlags.setOrigAlign(1); 4659 Ops.push_back(DAG.getArgFlags(MyFlags)); 4660 } 4661 } 4662 } 4663 4664 RetVals.push_back(MVT::Other); 4665 4666 // Create the node. 4667 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4668 DAG.getVTList(&RetVals[0], RetVals.size()), 4669 &Ops[0], Ops.size()).Val; 4670 4671 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but 4672 // allows exposing the loads that may be part of the argument access to the 4673 // first DAGCombiner pass. 4674 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG); 4675 4676 // The number of results should match up, except that the lowered one may have 4677 // an extra flag result. 4678 assert((Result->getNumValues() == TmpRes.Val->getNumValues() || 4679 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && 4680 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) 4681 && "Lowering produced unexpected number of results!"); 4682 4683 // The FORMAL_ARGUMENTS node itself is likely no longer needed. 4684 if (Result != TmpRes.Val && Result->use_empty()) { 4685 HandleSDNode Dummy(DAG.getRoot()); 4686 DAG.RemoveDeadNode(Result); 4687 } 4688 4689 Result = TmpRes.Val; 4690 4691 unsigned NumArgRegs = Result->getNumValues() - 1; 4692 DAG.setRoot(SDValue(Result, NumArgRegs)); 4693 4694 // Set up the return result vector. 4695 unsigned i = 0; 4696 unsigned Idx = 1; 4697 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4698 ++I, ++Idx) { 4699 SmallVector<MVT, 4> ValueVTs; 4700 ComputeValueVTs(*this, I->getType(), ValueVTs); 4701 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4702 Value != NumValues; ++Value) { 4703 MVT VT = ValueVTs[Value]; 4704 MVT PartVT = getRegisterType(VT); 4705 4706 unsigned NumParts = getNumRegisters(VT); 4707 SmallVector<SDValue, 4> Parts(NumParts); 4708 for (unsigned j = 0; j != NumParts; ++j) 4709 Parts[j] = SDValue(Result, i++); 4710 4711 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4712 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4713 AssertOp = ISD::AssertSext; 4714 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4715 AssertOp = ISD::AssertZext; 4716 4717 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4718 AssertOp)); 4719 } 4720 } 4721 assert(i == NumArgRegs && "Argument register count mismatch!"); 4722} 4723 4724 4725/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4726/// implementation, which just inserts an ISD::CALL node, which is later custom 4727/// lowered by the target to something concrete. FIXME: When all targets are 4728/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4729std::pair<SDValue, SDValue> 4730TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 4731 bool RetSExt, bool RetZExt, bool isVarArg, 4732 unsigned CallingConv, bool isTailCall, 4733 SDValue Callee, 4734 ArgListTy &Args, SelectionDAG &DAG) { 4735 SmallVector<SDValue, 32> Ops; 4736 Ops.push_back(Chain); // Op#0 - Chain 4737 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4738 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4739 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4740 Ops.push_back(Callee); 4741 4742 // Handle all of the outgoing arguments. 4743 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4744 SmallVector<MVT, 4> ValueVTs; 4745 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 4746 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4747 Value != NumValues; ++Value) { 4748 MVT VT = ValueVTs[Value]; 4749 const Type *ArgTy = VT.getTypeForMVT(); 4750 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value); 4751 ISD::ArgFlagsTy Flags; 4752 unsigned OriginalAlignment = 4753 getTargetData()->getABITypeAlignment(ArgTy); 4754 4755 if (Args[i].isZExt) 4756 Flags.setZExt(); 4757 if (Args[i].isSExt) 4758 Flags.setSExt(); 4759 if (Args[i].isInReg) 4760 Flags.setInReg(); 4761 if (Args[i].isSRet) 4762 Flags.setSRet(); 4763 if (Args[i].isByVal) { 4764 Flags.setByVal(); 4765 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4766 const Type *ElementTy = Ty->getElementType(); 4767 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4768 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4769 // For ByVal, alignment should come from FE. BE will guess if this 4770 // info is not there but there are cases it cannot get right. 4771 if (Args[i].Alignment) 4772 FrameAlign = Args[i].Alignment; 4773 Flags.setByValAlign(FrameAlign); 4774 Flags.setByValSize(FrameSize); 4775 } 4776 if (Args[i].isNest) 4777 Flags.setNest(); 4778 Flags.setOrigAlign(OriginalAlignment); 4779 4780 MVT PartVT = getRegisterType(VT); 4781 unsigned NumParts = getNumRegisters(VT); 4782 SmallVector<SDValue, 4> Parts(NumParts); 4783 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4784 4785 if (Args[i].isSExt) 4786 ExtendKind = ISD::SIGN_EXTEND; 4787 else if (Args[i].isZExt) 4788 ExtendKind = ISD::ZERO_EXTEND; 4789 4790 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4791 4792 for (unsigned i = 0; i != NumParts; ++i) { 4793 // if it isn't first piece, alignment must be 1 4794 ISD::ArgFlagsTy MyFlags = Flags; 4795 if (NumParts > 1 && i == 0) 4796 MyFlags.setSplit(); 4797 else if (i != 0) 4798 MyFlags.setOrigAlign(1); 4799 4800 Ops.push_back(Parts[i]); 4801 Ops.push_back(DAG.getArgFlags(MyFlags)); 4802 } 4803 } 4804 } 4805 4806 // Figure out the result value types. We start by making a list of 4807 // the potentially illegal return value types. 4808 SmallVector<MVT, 4> LoweredRetTys; 4809 SmallVector<MVT, 4> RetTys; 4810 ComputeValueVTs(*this, RetTy, RetTys); 4811 4812 // Then we translate that to a list of legal types. 4813 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4814 MVT VT = RetTys[I]; 4815 MVT RegisterVT = getRegisterType(VT); 4816 unsigned NumRegs = getNumRegisters(VT); 4817 for (unsigned i = 0; i != NumRegs; ++i) 4818 LoweredRetTys.push_back(RegisterVT); 4819 } 4820 4821 LoweredRetTys.push_back(MVT::Other); // Always has a chain. 4822 4823 // Create the CALL node. 4824 SDValue Res = DAG.getNode(ISD::CALL, 4825 DAG.getVTList(&LoweredRetTys[0], 4826 LoweredRetTys.size()), 4827 &Ops[0], Ops.size()); 4828 Chain = Res.getValue(LoweredRetTys.size() - 1); 4829 4830 // Gather up the call result into a single value. 4831 if (RetTy != Type::VoidTy) { 4832 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4833 4834 if (RetSExt) 4835 AssertOp = ISD::AssertSext; 4836 else if (RetZExt) 4837 AssertOp = ISD::AssertZext; 4838 4839 SmallVector<SDValue, 4> ReturnValues; 4840 unsigned RegNo = 0; 4841 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4842 MVT VT = RetTys[I]; 4843 MVT RegisterVT = getRegisterType(VT); 4844 unsigned NumRegs = getNumRegisters(VT); 4845 unsigned RegNoEnd = NumRegs + RegNo; 4846 SmallVector<SDValue, 4> Results; 4847 for (; RegNo != RegNoEnd; ++RegNo) 4848 Results.push_back(Res.getValue(RegNo)); 4849 SDValue ReturnValue = 4850 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, 4851 AssertOp); 4852 ReturnValues.push_back(ReturnValue); 4853 } 4854 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()), 4855 &ReturnValues[0], ReturnValues.size()); 4856 } 4857 4858 return std::make_pair(Res, Chain); 4859} 4860 4861SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 4862 assert(0 && "LowerOperation not implemented for this target!"); 4863 abort(); 4864 return SDValue(); 4865} 4866 4867 4868//===----------------------------------------------------------------------===// 4869// SelectionDAGISel code 4870//===----------------------------------------------------------------------===// 4871 4872unsigned SelectionDAGISel::MakeReg(MVT VT) { 4873 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4874} 4875 4876void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4877 AU.addRequired<AliasAnalysis>(); 4878 AU.addRequired<CollectorModuleMetadata>(); 4879 AU.setPreservesAll(); 4880} 4881 4882bool SelectionDAGISel::runOnFunction(Function &Fn) { 4883 // Get alias analysis for load/store combining. 4884 AA = &getAnalysis<AliasAnalysis>(); 4885 4886 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4887 if (MF.getFunction()->hasCollector()) 4888 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4889 else 4890 GCI = 0; 4891 RegInfo = &MF.getRegInfo(); 4892 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4893 4894 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4895 4896 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4897 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4898 // Mark landing pad. 4899 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4900 4901 SelectAllBasicBlocks(Fn, MF, FuncInfo); 4902 4903 // Add function live-ins to entry block live-in set. 4904 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4905 BB = FuncInfo.MBBMap[EntryBB]; 4906 if (!RegInfo->livein_empty()) 4907 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4908 E = RegInfo->livein_end(); I != E; ++I) 4909 BB->addLiveIn(I->first); 4910 4911#ifndef NDEBUG 4912 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4913 "Not all catch info was assigned to a landing pad!"); 4914#endif 4915 4916 return true; 4917} 4918 4919void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) { 4920 SDValue Op = getValue(V); 4921 assert((Op.getOpcode() != ISD::CopyFromReg || 4922 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4923 "Copy from a reg to the same reg!"); 4924 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 4925 4926 RegsForValue RFV(TLI, Reg, V->getType()); 4927 SDValue Chain = DAG.getEntryNode(); 4928 RFV.getCopyToRegs(Op, DAG, Chain, 0); 4929 PendingExports.push_back(Chain); 4930} 4931 4932void SelectionDAGISel:: 4933LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { 4934 // If this is the entry block, emit arguments. 4935 Function &F = *LLVMBB->getParent(); 4936 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4937 SDValue OldRoot = SDL.DAG.getRoot(); 4938 SmallVector<SDValue, 16> Args; 4939 TLI.LowerArguments(F, SDL.DAG, Args); 4940 4941 unsigned a = 0; 4942 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4943 AI != E; ++AI) { 4944 SmallVector<MVT, 4> ValueVTs; 4945 ComputeValueVTs(TLI, AI->getType(), ValueVTs); 4946 unsigned NumValues = ValueVTs.size(); 4947 if (!AI->use_empty()) { 4948 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues)); 4949 // If this argument is live outside of the entry block, insert a copy from 4950 // whereever we got it to the vreg that other BB's will reference it as. 4951 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4952 if (VMI != FuncInfo.ValueMap.end()) { 4953 SDL.CopyValueToVirtualRegister(AI, VMI->second); 4954 } 4955 } 4956 a += NumValues; 4957 } 4958 4959 // Finally, if the target has anything special to do, allow it to do so. 4960 // FIXME: this should insert code into the DAG! 4961 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4962} 4963 4964static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4965 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4966 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4967 if (isSelector(I)) { 4968 // Apply the catch info to DestBB. 4969 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4970#ifndef NDEBUG 4971 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4972 FLI.CatchInfoFound.insert(I); 4973#endif 4974 } 4975} 4976 4977/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 4978/// whether object offset >= 0. 4979static bool 4980IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 4981 if (!isa<FrameIndexSDNode>(Op)) return false; 4982 4983 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 4984 int FrameIdx = FrameIdxNode->getIndex(); 4985 return MFI->isFixedObjectIndex(FrameIdx) && 4986 MFI->getObjectOffset(FrameIdx) >= 0; 4987} 4988 4989/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 4990/// possibly be overwritten when lowering the outgoing arguments in a tail 4991/// call. Currently the implementation of this call is very conservative and 4992/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 4993/// virtual registers would be overwritten by direct lowering. 4994static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 4995 MachineFrameInfo * MFI) { 4996 RegisterSDNode * OpReg = NULL; 4997 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 4998 (Op.getOpcode()== ISD::CopyFromReg && 4999 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 5000 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 5001 (Op.getOpcode() == ISD::LOAD && 5002 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 5003 (Op.getOpcode() == ISD::MERGE_VALUES && 5004 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD && 5005 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo). 5006 getOperand(1)))) 5007 return true; 5008 return false; 5009} 5010 5011/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 5012/// DAG and fixes their tailcall attribute operand. 5013static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 5014 TargetLowering& TLI) { 5015 SDNode * Ret = NULL; 5016 SDValue Terminator = DAG.getRoot(); 5017 5018 // Find RET node. 5019 if (Terminator.getOpcode() == ISD::RET) { 5020 Ret = Terminator.Val; 5021 } 5022 5023 // Fix tail call attribute of CALL nodes. 5024 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 5025 BI = DAG.allnodes_end(); BI != BE; ) { 5026 --BI; 5027 if (BI->getOpcode() == ISD::CALL) { 5028 SDValue OpRet(Ret, 0); 5029 SDValue OpCall(BI, 0); 5030 bool isMarkedTailCall = 5031 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 5032 // If CALL node has tail call attribute set to true and the call is not 5033 // eligible (no RET or the target rejects) the attribute is fixed to 5034 // false. The TargetLowering::IsEligibleForTailCallOptimization function 5035 // must correctly identify tail call optimizable calls. 5036 if (!isMarkedTailCall) continue; 5037 if (Ret==NULL || 5038 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) { 5039 // Not eligible. Mark CALL node as non tail call. 5040 SmallVector<SDValue, 32> Ops; 5041 unsigned idx=0; 5042 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 5043 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5044 if (idx!=3) 5045 Ops.push_back(*I); 5046 else 5047 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 5048 } 5049 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5050 } else { 5051 // Look for tail call clobbered arguments. Emit a series of 5052 // copyto/copyfrom virtual register nodes to protect them. 5053 SmallVector<SDValue, 32> Ops; 5054 SDValue Chain = OpCall.getOperand(0), InFlag; 5055 unsigned idx=0; 5056 for(SDNode::op_iterator I = OpCall.Val->op_begin(), 5057 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5058 SDValue Arg = *I; 5059 if (idx > 4 && (idx % 2)) { 5060 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))-> 5061 getArgFlags().isByVal(); 5062 MachineFunction &MF = DAG.getMachineFunction(); 5063 MachineFrameInfo *MFI = MF.getFrameInfo(); 5064 if (!isByVal && 5065 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 5066 MVT VT = Arg.getValueType(); 5067 unsigned VReg = MF.getRegInfo(). 5068 createVirtualRegister(TLI.getRegClassFor(VT)); 5069 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 5070 InFlag = Chain.getValue(1); 5071 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 5072 Chain = Arg.getValue(1); 5073 InFlag = Arg.getValue(2); 5074 } 5075 } 5076 Ops.push_back(Arg); 5077 } 5078 // Link in chain of CopyTo/CopyFromReg. 5079 Ops[0] = Chain; 5080 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5081 } 5082 } 5083 } 5084} 5085 5086void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 5087 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 5088 FunctionLoweringInfo &FuncInfo) { 5089 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 5090 5091 // Lower any arguments needed in this block if this is the entry block. 5092 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 5093 LowerArguments(LLVMBB, SDL); 5094 5095 BB = FuncInfo.MBBMap[LLVMBB]; 5096 SDL.setCurrentBasicBlock(BB); 5097 5098 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 5099 5100 if (MMI && BB->isLandingPad()) { 5101 // Add a label to mark the beginning of the landing pad. Deletion of the 5102 // landing pad can thus be detected via the MachineModuleInfo. 5103 unsigned LabelID = MMI->addLandingPad(BB); 5104 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID)); 5105 5106 // Mark exception register as live in. 5107 unsigned Reg = TLI.getExceptionAddressRegister(); 5108 if (Reg) BB->addLiveIn(Reg); 5109 5110 // Mark exception selector register as live in. 5111 Reg = TLI.getExceptionSelectorRegister(); 5112 if (Reg) BB->addLiveIn(Reg); 5113 5114 // FIXME: Hack around an exception handling flaw (PR1508): the personality 5115 // function and list of typeids logically belong to the invoke (or, if you 5116 // like, the basic block containing the invoke), and need to be associated 5117 // with it in the dwarf exception handling tables. Currently however the 5118 // information is provided by an intrinsic (eh.selector) that can be moved 5119 // to unexpected places by the optimizers: if the unwind edge is critical, 5120 // then breaking it can result in the intrinsics being in the successor of 5121 // the landing pad, not the landing pad itself. This results in exceptions 5122 // not being caught because no typeids are associated with the invoke. 5123 // This may not be the only way things can go wrong, but it is the only way 5124 // we try to work around for the moment. 5125 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 5126 5127 if (Br && Br->isUnconditional()) { // Critical edge? 5128 BasicBlock::iterator I, E; 5129 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 5130 if (isSelector(I)) 5131 break; 5132 5133 if (I == E) 5134 // No catch info found - try to extract some from the successor. 5135 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 5136 } 5137 } 5138 5139 // Lower all of the non-terminator instructions. 5140 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 5141 I != E; ++I) 5142 SDL.visit(*I); 5143 5144 // Ensure that all instructions which are used outside of their defining 5145 // blocks are available as virtual registers. Invoke is handled elsewhere. 5146 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 5147 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 5148 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 5149 if (VMI != FuncInfo.ValueMap.end()) 5150 SDL.CopyValueToVirtualRegister(I, VMI->second); 5151 } 5152 5153 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 5154 // ensure constants are generated when needed. Remember the virtual registers 5155 // that need to be added to the Machine PHI nodes as input. We cannot just 5156 // directly add them, because expansion might result in multiple MBB's for one 5157 // BB. As such, the start of the BB might correspond to a different MBB than 5158 // the end. 5159 // 5160 TerminatorInst *TI = LLVMBB->getTerminator(); 5161 5162 // Emit constants only once even if used by multiple PHI nodes. 5163 std::map<Constant*, unsigned> ConstantsOut; 5164 5165 // Vector bool would be better, but vector<bool> is really slow. 5166 std::vector<unsigned char> SuccsHandled; 5167 if (TI->getNumSuccessors()) 5168 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 5169 5170 // Check successor nodes' PHI nodes that expect a constant to be available 5171 // from this block. 5172 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 5173 BasicBlock *SuccBB = TI->getSuccessor(succ); 5174 if (!isa<PHINode>(SuccBB->begin())) continue; 5175 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 5176 5177 // If this terminator has multiple identical successors (common for 5178 // switches), only handle each succ once. 5179 unsigned SuccMBBNo = SuccMBB->getNumber(); 5180 if (SuccsHandled[SuccMBBNo]) continue; 5181 SuccsHandled[SuccMBBNo] = true; 5182 5183 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 5184 PHINode *PN; 5185 5186 // At this point we know that there is a 1-1 correspondence between LLVM PHI 5187 // nodes and Machine PHI nodes, but the incoming operands have not been 5188 // emitted yet. 5189 for (BasicBlock::iterator I = SuccBB->begin(); 5190 (PN = dyn_cast<PHINode>(I)); ++I) { 5191 // Ignore dead phi's. 5192 if (PN->use_empty()) continue; 5193 5194 unsigned Reg; 5195 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 5196 5197 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 5198 unsigned &RegOut = ConstantsOut[C]; 5199 if (RegOut == 0) { 5200 RegOut = FuncInfo.CreateRegForValue(C); 5201 SDL.CopyValueToVirtualRegister(C, RegOut); 5202 } 5203 Reg = RegOut; 5204 } else { 5205 Reg = FuncInfo.ValueMap[PHIOp]; 5206 if (Reg == 0) { 5207 assert(isa<AllocaInst>(PHIOp) && 5208 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 5209 "Didn't codegen value into a register!??"); 5210 Reg = FuncInfo.CreateRegForValue(PHIOp); 5211 SDL.CopyValueToVirtualRegister(PHIOp, Reg); 5212 } 5213 } 5214 5215 // Remember that this register needs to added to the machine PHI node as 5216 // the input for this MBB. 5217 MVT VT = TLI.getValueType(PN->getType()); 5218 unsigned NumRegisters = TLI.getNumRegisters(VT); 5219 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 5220 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 5221 } 5222 } 5223 ConstantsOut.clear(); 5224 5225 // Lower the terminator after the copies are emitted. 5226 SDL.visit(*LLVMBB->getTerminator()); 5227 5228 // Copy over any CaseBlock records that may now exist due to SwitchInst 5229 // lowering, as well as any jump table information. 5230 SwitchCases.clear(); 5231 SwitchCases = SDL.SwitchCases; 5232 JTCases.clear(); 5233 JTCases = SDL.JTCases; 5234 BitTestCases.clear(); 5235 BitTestCases = SDL.BitTestCases; 5236 5237 // Make sure the root of the DAG is up-to-date. 5238 DAG.setRoot(SDL.getControlRoot()); 5239 5240 // Check whether calls in this block are real tail calls. Fix up CALL nodes 5241 // with correct tailcall attribute so that the target can rely on the tailcall 5242 // attribute indicating whether the call is really eligible for tail call 5243 // optimization. 5244 CheckDAGForTailCallsAndFixThem(DAG, TLI); 5245} 5246 5247void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { 5248 SmallPtrSet<SDNode*, 128> VisitedNodes; 5249 SmallVector<SDNode*, 128> Worklist; 5250 5251 Worklist.push_back(DAG.getRoot().Val); 5252 5253 APInt Mask; 5254 APInt KnownZero; 5255 APInt KnownOne; 5256 5257 while (!Worklist.empty()) { 5258 SDNode *N = Worklist.back(); 5259 Worklist.pop_back(); 5260 5261 // If we've already seen this node, ignore it. 5262 if (!VisitedNodes.insert(N)) 5263 continue; 5264 5265 // Otherwise, add all chain operands to the worklist. 5266 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5267 if (N->getOperand(i).getValueType() == MVT::Other) 5268 Worklist.push_back(N->getOperand(i).Val); 5269 5270 // If this is a CopyToReg with a vreg dest, process it. 5271 if (N->getOpcode() != ISD::CopyToReg) 5272 continue; 5273 5274 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 5275 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 5276 continue; 5277 5278 // Ignore non-scalar or non-integer values. 5279 SDValue Src = N->getOperand(2); 5280 MVT SrcVT = Src.getValueType(); 5281 if (!SrcVT.isInteger() || SrcVT.isVector()) 5282 continue; 5283 5284 unsigned NumSignBits = DAG.ComputeNumSignBits(Src); 5285 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 5286 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 5287 5288 // Only install this information if it tells us something. 5289 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 5290 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 5291 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5292 if (DestReg >= FLI.LiveOutRegInfo.size()) 5293 FLI.LiveOutRegInfo.resize(DestReg+1); 5294 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 5295 LOI.NumSignBits = NumSignBits; 5296 LOI.KnownOne = NumSignBits; 5297 LOI.KnownZero = NumSignBits; 5298 } 5299 } 5300} 5301 5302void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 5303 std::string GroupName; 5304 if (TimePassesIsEnabled) 5305 GroupName = "Instruction Selection and Scheduling"; 5306 std::string BlockName; 5307 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 5308 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 5309 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' + 5310 BB->getBasicBlock()->getName(); 5311 5312 DOUT << "Initial selection DAG:\n"; 5313 DEBUG(DAG.dump()); 5314 5315 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName); 5316 5317 // Run the DAG combiner in pre-legalize mode. 5318 if (TimePassesIsEnabled) { 5319 NamedRegionTimer T("DAG Combining 1", GroupName); 5320 DAG.Combine(false, *AA); 5321 } else { 5322 DAG.Combine(false, *AA); 5323 } 5324 5325 DOUT << "Optimized lowered selection DAG:\n"; 5326 DEBUG(DAG.dump()); 5327 5328 // Second step, hack on the DAG until it only uses operations and types that 5329 // the target supports. 5330 if (EnableLegalizeTypes) {// Enable this some day. 5331 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " + 5332 BlockName); 5333 5334 if (TimePassesIsEnabled) { 5335 NamedRegionTimer T("Type Legalization", GroupName); 5336 DAG.LegalizeTypes(); 5337 } else { 5338 DAG.LegalizeTypes(); 5339 } 5340 5341 DOUT << "Type-legalized selection DAG:\n"; 5342 DEBUG(DAG.dump()); 5343 5344 // TODO: enable a dag combine pass here. 5345 } 5346 5347 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName); 5348 5349 if (TimePassesIsEnabled) { 5350 NamedRegionTimer T("DAG Legalization", GroupName); 5351 DAG.Legalize(); 5352 } else { 5353 DAG.Legalize(); 5354 } 5355 5356 DOUT << "Legalized selection DAG:\n"; 5357 DEBUG(DAG.dump()); 5358 5359 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName); 5360 5361 // Run the DAG combiner in post-legalize mode. 5362 if (TimePassesIsEnabled) { 5363 NamedRegionTimer T("DAG Combining 2", GroupName); 5364 DAG.Combine(true, *AA); 5365 } else { 5366 DAG.Combine(true, *AA); 5367 } 5368 5369 DOUT << "Optimized legalized selection DAG:\n"; 5370 DEBUG(DAG.dump()); 5371 5372 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName); 5373 5374 if (!FastISel && EnableValueProp) 5375 ComputeLiveOutVRegInfo(DAG); 5376 5377 // Third, instruction select all of the operations to machine code, adding the 5378 // code to the MachineBasicBlock. 5379 if (TimePassesIsEnabled) { 5380 NamedRegionTimer T("Instruction Selection", GroupName); 5381 InstructionSelect(DAG); 5382 } else { 5383 InstructionSelect(DAG); 5384 } 5385 5386 DOUT << "Selected selection DAG:\n"; 5387 DEBUG(DAG.dump()); 5388 5389 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName); 5390 5391 // Schedule machine code. 5392 ScheduleDAG *Scheduler; 5393 if (TimePassesIsEnabled) { 5394 NamedRegionTimer T("Instruction Scheduling", GroupName); 5395 Scheduler = Schedule(DAG); 5396 } else { 5397 Scheduler = Schedule(DAG); 5398 } 5399 5400 if (ViewSUnitDAGs) Scheduler->viewGraph(); 5401 5402 // Emit machine code to BB. This can change 'BB' to the last block being 5403 // inserted into. 5404 if (TimePassesIsEnabled) { 5405 NamedRegionTimer T("Instruction Creation", GroupName); 5406 BB = Scheduler->EmitSchedule(); 5407 } else { 5408 BB = Scheduler->EmitSchedule(); 5409 } 5410 5411 // Free the scheduler state. 5412 if (TimePassesIsEnabled) { 5413 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 5414 delete Scheduler; 5415 } else { 5416 delete Scheduler; 5417 } 5418 5419 // Perform target specific isel post processing. 5420 if (TimePassesIsEnabled) { 5421 NamedRegionTimer T("Instruction Selection Post Processing", GroupName); 5422 InstructionSelectPostProcessing(); 5423 } else { 5424 InstructionSelectPostProcessing(); 5425 } 5426 5427 DOUT << "Selected machine code:\n"; 5428 DEBUG(BB->dump()); 5429} 5430 5431void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 5432 FunctionLoweringInfo &FuncInfo) { 5433 // Define NodeAllocator here so that memory allocation is reused for 5434 // each basic block. 5435 NodeAllocatorType NodeAllocator; 5436 5437 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 5438 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator); 5439} 5440 5441void 5442SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 5443 FunctionLoweringInfo &FuncInfo, 5444 NodeAllocatorType &NodeAllocator) { 5445 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 5446 { 5447 SelectionDAG DAG(TLI, MF, FuncInfo, 5448 getAnalysisToUpdate<MachineModuleInfo>(), 5449 NodeAllocator); 5450 CurDAG = &DAG; 5451 5452 // First step, lower LLVM code to some DAG. This DAG may use operations and 5453 // types that are not supported by the target. 5454 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 5455 5456 // Second step, emit the lowered DAG as machine code. 5457 CodeGenAndEmitDAG(DAG); 5458 } 5459 5460 DOUT << "Total amount of phi nodes to update: " 5461 << PHINodesToUpdate.size() << "\n"; 5462 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 5463 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 5464 << ", " << PHINodesToUpdate[i].second << ")\n";); 5465 5466 // Next, now that we know what the last MBB the LLVM BB expanded is, update 5467 // PHI nodes in successors. 5468 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 5469 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5470 MachineInstr *PHI = PHINodesToUpdate[i].first; 5471 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5472 "This is not a machine PHI node that we are updating!"); 5473 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5474 false)); 5475 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5476 } 5477 return; 5478 } 5479 5480 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 5481 // Lower header first, if it wasn't already lowered 5482 if (!BitTestCases[i].Emitted) { 5483 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5484 getAnalysisToUpdate<MachineModuleInfo>(), 5485 NodeAllocator); 5486 CurDAG = &HSDAG; 5487 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5488 // Set the current basic block to the mbb we wish to insert the code into 5489 BB = BitTestCases[i].Parent; 5490 HSDL.setCurrentBasicBlock(BB); 5491 // Emit the code 5492 HSDL.visitBitTestHeader(BitTestCases[i]); 5493 HSDAG.setRoot(HSDL.getRoot()); 5494 CodeGenAndEmitDAG(HSDAG); 5495 } 5496 5497 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5498 SelectionDAG BSDAG(TLI, MF, FuncInfo, 5499 getAnalysisToUpdate<MachineModuleInfo>(), 5500 NodeAllocator); 5501 CurDAG = &BSDAG; 5502 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 5503 // Set the current basic block to the mbb we wish to insert the code into 5504 BB = BitTestCases[i].Cases[j].ThisBB; 5505 BSDL.setCurrentBasicBlock(BB); 5506 // Emit the code 5507 if (j+1 != ej) 5508 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 5509 BitTestCases[i].Reg, 5510 BitTestCases[i].Cases[j]); 5511 else 5512 BSDL.visitBitTestCase(BitTestCases[i].Default, 5513 BitTestCases[i].Reg, 5514 BitTestCases[i].Cases[j]); 5515 5516 5517 BSDAG.setRoot(BSDL.getRoot()); 5518 CodeGenAndEmitDAG(BSDAG); 5519 } 5520 5521 // Update PHI Nodes 5522 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5523 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5524 MachineBasicBlock *PHIBB = PHI->getParent(); 5525 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5526 "This is not a machine PHI node that we are updating!"); 5527 // This is "default" BB. We have two jumps to it. From "header" BB and 5528 // from last "case" BB. 5529 if (PHIBB == BitTestCases[i].Default) { 5530 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5531 false)); 5532 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 5533 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5534 false)); 5535 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 5536 back().ThisBB)); 5537 } 5538 // One of "cases" BB. 5539 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5540 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 5541 if (cBB->succ_end() != 5542 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 5543 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5544 false)); 5545 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 5546 } 5547 } 5548 } 5549 } 5550 5551 // If the JumpTable record is filled in, then we need to emit a jump table. 5552 // Updating the PHI nodes is tricky in this case, since we need to determine 5553 // whether the PHI is a successor of the range check MBB or the jump table MBB 5554 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 5555 // Lower header first, if it wasn't already lowered 5556 if (!JTCases[i].first.Emitted) { 5557 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5558 getAnalysisToUpdate<MachineModuleInfo>(), 5559 NodeAllocator); 5560 CurDAG = &HSDAG; 5561 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5562 // Set the current basic block to the mbb we wish to insert the code into 5563 BB = JTCases[i].first.HeaderBB; 5564 HSDL.setCurrentBasicBlock(BB); 5565 // Emit the code 5566 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 5567 HSDAG.setRoot(HSDL.getRoot()); 5568 CodeGenAndEmitDAG(HSDAG); 5569 } 5570 5571 SelectionDAG JSDAG(TLI, MF, FuncInfo, 5572 getAnalysisToUpdate<MachineModuleInfo>(), 5573 NodeAllocator); 5574 CurDAG = &JSDAG; 5575 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 5576 // Set the current basic block to the mbb we wish to insert the code into 5577 BB = JTCases[i].second.MBB; 5578 JSDL.setCurrentBasicBlock(BB); 5579 // Emit the code 5580 JSDL.visitJumpTable(JTCases[i].second); 5581 JSDAG.setRoot(JSDL.getRoot()); 5582 CodeGenAndEmitDAG(JSDAG); 5583 5584 // Update PHI Nodes 5585 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5586 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5587 MachineBasicBlock *PHIBB = PHI->getParent(); 5588 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5589 "This is not a machine PHI node that we are updating!"); 5590 // "default" BB. We can go there only from header BB. 5591 if (PHIBB == JTCases[i].second.Default) { 5592 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5593 false)); 5594 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 5595 } 5596 // JT BB. Just iterate over successors here 5597 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 5598 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5599 false)); 5600 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5601 } 5602 } 5603 } 5604 5605 // If the switch block involved a branch to one of the actual successors, we 5606 // need to update PHI nodes in that block. 5607 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5608 MachineInstr *PHI = PHINodesToUpdate[i].first; 5609 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5610 "This is not a machine PHI node that we are updating!"); 5611 if (BB->isSuccessor(PHI->getParent())) { 5612 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5613 false)); 5614 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5615 } 5616 } 5617 5618 // If we generated any switch lowering information, build and codegen any 5619 // additional DAGs necessary. 5620 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5621 SelectionDAG SDAG(TLI, MF, FuncInfo, 5622 getAnalysisToUpdate<MachineModuleInfo>(), 5623 NodeAllocator); 5624 CurDAG = &SDAG; 5625 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5626 5627 // Set the current basic block to the mbb we wish to insert the code into 5628 BB = SwitchCases[i].ThisBB; 5629 SDL.setCurrentBasicBlock(BB); 5630 5631 // Emit the code 5632 SDL.visitSwitchCase(SwitchCases[i]); 5633 SDAG.setRoot(SDL.getRoot()); 5634 CodeGenAndEmitDAG(SDAG); 5635 5636 // Handle any PHI nodes in successors of this chunk, as if we were coming 5637 // from the original BB before switch expansion. Note that PHI nodes can 5638 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5639 // handle them the right number of times. 5640 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5641 for (MachineBasicBlock::iterator Phi = BB->begin(); 5642 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5643 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5644 for (unsigned pn = 0; ; ++pn) { 5645 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5646 if (PHINodesToUpdate[pn].first == Phi) { 5647 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5648 second, false)); 5649 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5650 break; 5651 } 5652 } 5653 } 5654 5655 // Don't process RHS if same block as LHS. 5656 if (BB == SwitchCases[i].FalseBB) 5657 SwitchCases[i].FalseBB = 0; 5658 5659 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5660 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5661 SwitchCases[i].FalseBB = 0; 5662 } 5663 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5664 } 5665} 5666 5667 5668/// Schedule - Pick a safe ordering for instructions for each 5669/// target node in the graph. 5670/// 5671ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { 5672 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5673 5674 if (!Ctor) { 5675 Ctor = ISHeuristic; 5676 RegisterScheduler::setDefault(Ctor); 5677 } 5678 5679 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); 5680 Scheduler->Run(); 5681 5682 return Scheduler; 5683} 5684 5685 5686HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5687 return new HazardRecognizer(); 5688} 5689 5690//===----------------------------------------------------------------------===// 5691// Helper functions used by the generated instruction selector. 5692//===----------------------------------------------------------------------===// 5693// Calls to these methods are generated by tblgen. 5694 5695/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5696/// the dag combiner simplified the 255, we still want to match. RHS is the 5697/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5698/// specified in the .td file (e.g. 255). 5699bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 5700 int64_t DesiredMaskS) const { 5701 const APInt &ActualMask = RHS->getAPIntValue(); 5702 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5703 5704 // If the actual mask exactly matches, success! 5705 if (ActualMask == DesiredMask) 5706 return true; 5707 5708 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5709 if (ActualMask.intersects(~DesiredMask)) 5710 return false; 5711 5712 // Otherwise, the DAG Combiner may have proven that the value coming in is 5713 // either already zero or is not demanded. Check for known zero input bits. 5714 APInt NeededMask = DesiredMask & ~ActualMask; 5715 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5716 return true; 5717 5718 // TODO: check to see if missing bits are just not demanded. 5719 5720 // Otherwise, this pattern doesn't match. 5721 return false; 5722} 5723 5724/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5725/// the dag combiner simplified the 255, we still want to match. RHS is the 5726/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5727/// specified in the .td file (e.g. 255). 5728bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 5729 int64_t DesiredMaskS) const { 5730 const APInt &ActualMask = RHS->getAPIntValue(); 5731 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5732 5733 // If the actual mask exactly matches, success! 5734 if (ActualMask == DesiredMask) 5735 return true; 5736 5737 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5738 if (ActualMask.intersects(~DesiredMask)) 5739 return false; 5740 5741 // Otherwise, the DAG Combiner may have proven that the value coming in is 5742 // either already zero or is not demanded. Check for known zero input bits. 5743 APInt NeededMask = DesiredMask & ~ActualMask; 5744 5745 APInt KnownZero, KnownOne; 5746 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5747 5748 // If all the missing bits in the or are already known to be set, match! 5749 if ((NeededMask & KnownOne) == NeededMask) 5750 return true; 5751 5752 // TODO: check to see if missing bits are just not demanded. 5753 5754 // Otherwise, this pattern doesn't match. 5755 return false; 5756} 5757 5758 5759/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5760/// by tblgen. Others should not call it. 5761void SelectionDAGISel:: 5762SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) { 5763 std::vector<SDValue> InOps; 5764 std::swap(InOps, Ops); 5765 5766 Ops.push_back(InOps[0]); // input chain. 5767 Ops.push_back(InOps[1]); // input asm string. 5768 5769 unsigned i = 2, e = InOps.size(); 5770 if (InOps[e-1].getValueType() == MVT::Flag) 5771 --e; // Don't process a flag operand if it is here. 5772 5773 while (i != e) { 5774 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5775 if ((Flags & 7) != 4 /*MEM*/) { 5776 // Just skip over this operand, copying the operands verbatim. 5777 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5778 i += (Flags >> 3) + 1; 5779 } else { 5780 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5781 // Otherwise, this is a memory operand. Ask the target to select it. 5782 std::vector<SDValue> SelOps; 5783 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5784 cerr << "Could not match memory address. Inline asm failure!\n"; 5785 exit(1); 5786 } 5787 5788 // Add this to the output node. 5789 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5790 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5791 IntPtrTy)); 5792 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5793 i += 2; 5794 } 5795 } 5796 5797 // Add the flag input back if present. 5798 if (e != InOps.size()) 5799 Ops.push_back(InOps.back()); 5800} 5801 5802char SelectionDAGISel::ID = 0; 5803