SelectionDAGISel.cpp revision 918b7c82f8f53241a5bb354931abfe53634bfc4c
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/TargetTransformInfo.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/FunctionLoweringInfo.h" 25#include "llvm/CodeGen/GCMetadata.h" 26#include "llvm/CodeGen/GCStrategy.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/Constants.h" 37#include "llvm/IR/Function.h" 38#include "llvm/IR/InlineAsm.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/IntrinsicInst.h" 41#include "llvm/IR/Intrinsics.h" 42#include "llvm/IR/LLVMContext.h" 43#include "llvm/IR/Module.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLibraryInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "llvm/Target/TargetOptions.h" 55#include "llvm/Target/TargetRegisterInfo.h" 56#include "llvm/Target/TargetSubtargetInfo.h" 57#include "llvm/Transforms/Utils/BasicBlockUtils.h" 58#include <algorithm> 59using namespace llvm; 60 61STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 62STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 63STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 64STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 65STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 67STATISTIC(NumFastIselFailLowerArguments, 68 "Number of entry blocks where fast isel failed to lower arguments"); 69 70#ifndef NDEBUG 71static cl::opt<bool> 72EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 73 cl::desc("Enable extra verbose messages in the \"fast\" " 74 "instruction selector")); 75 76 // Terminators 77STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 78STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 79STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 80STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 81STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 82STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 83STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 84 85 // Standard binary operators... 86STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 87STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 88STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 89STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 90STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 91STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 92STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 93STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 94STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 95STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 96STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 97STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 98 99 // Logical operators... 100STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 101STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 102STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 103 104 // Memory instructions... 105STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 106STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 107STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 108STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 109STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 110STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 111STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 112 113 // Convert instructions... 114STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 115STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 116STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 117STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 118STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 119STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 120STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 121STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 122STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 123STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 124STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 125STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 126 127 // Other instructions... 128STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 129STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 130STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 131STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 132STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 133STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 134STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 135STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 136STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 137STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 138STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 139STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 140STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 141STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 142STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 143#endif 144 145static cl::opt<bool> 146EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 147 cl::desc("Enable verbose messages in the \"fast\" " 148 "instruction selector")); 149static cl::opt<bool> 150EnableFastISelAbort("fast-isel-abort", cl::Hidden, 151 cl::desc("Enable abort calls when \"fast\" instruction selection " 152 "fails to lower an instruction")); 153static cl::opt<bool> 154EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 155 cl::desc("Enable abort calls when \"fast\" instruction selection " 156 "fails to lower a formal argument")); 157 158static cl::opt<bool> 159UseMBPI("use-mbpi", 160 cl::desc("use Machine Branch Probability Info"), 161 cl::init(true), cl::Hidden); 162 163#ifndef NDEBUG 164static cl::opt<bool> 165ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 166 cl::desc("Pop up a window to show dags before the first " 167 "dag combine pass")); 168static cl::opt<bool> 169ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 170 cl::desc("Pop up a window to show dags before legalize types")); 171static cl::opt<bool> 172ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 173 cl::desc("Pop up a window to show dags before legalize")); 174static cl::opt<bool> 175ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 176 cl::desc("Pop up a window to show dags before the second " 177 "dag combine pass")); 178static cl::opt<bool> 179ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 180 cl::desc("Pop up a window to show dags before the post legalize types" 181 " dag combine pass")); 182static cl::opt<bool> 183ViewISelDAGs("view-isel-dags", cl::Hidden, 184 cl::desc("Pop up a window to show isel dags as they are selected")); 185static cl::opt<bool> 186ViewSchedDAGs("view-sched-dags", cl::Hidden, 187 cl::desc("Pop up a window to show sched dags as they are processed")); 188static cl::opt<bool> 189ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 190 cl::desc("Pop up a window to show SUnit dags after they are processed")); 191#else 192static const bool ViewDAGCombine1 = false, 193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 194 ViewDAGCombine2 = false, 195 ViewDAGCombineLT = false, 196 ViewISelDAGs = false, ViewSchedDAGs = false, 197 ViewSUnitDAGs = false; 198#endif 199 200//===---------------------------------------------------------------------===// 201/// 202/// RegisterScheduler class - Track the registration of instruction schedulers. 203/// 204//===---------------------------------------------------------------------===// 205MachinePassRegistry RegisterScheduler::Registry; 206 207//===---------------------------------------------------------------------===// 208/// 209/// ISHeuristic command line option for instruction schedulers. 210/// 211//===---------------------------------------------------------------------===// 212static cl::opt<RegisterScheduler::FunctionPassCtor, false, 213 RegisterPassParser<RegisterScheduler> > 214ISHeuristic("pre-RA-sched", 215 cl::init(&createDefaultScheduler), 216 cl::desc("Instruction schedulers available (before register" 217 " allocation):")); 218 219static RegisterScheduler 220defaultListDAGScheduler("default", "Best scheduler for the target", 221 createDefaultScheduler); 222 223namespace llvm { 224 //===--------------------------------------------------------------------===// 225 /// createDefaultScheduler - This creates an instruction scheduler appropriate 226 /// for the target. 227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 228 CodeGenOpt::Level OptLevel) { 229 const TargetLowering *TLI = IS->getTargetLowering(); 230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 231 232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 233 TLI->getSchedulingPreference() == Sched::Source) 234 return createSourceListDAGScheduler(IS, OptLevel); 235 if (TLI->getSchedulingPreference() == Sched::RegPressure) 236 return createBURRListDAGScheduler(IS, OptLevel); 237 if (TLI->getSchedulingPreference() == Sched::Hybrid) 238 return createHybridListDAGScheduler(IS, OptLevel); 239 if (TLI->getSchedulingPreference() == Sched::VLIW) 240 return createVLIWDAGScheduler(IS, OptLevel); 241 assert(TLI->getSchedulingPreference() == Sched::ILP && 242 "Unknown sched type!"); 243 return createILPListDAGScheduler(IS, OptLevel); 244 } 245} 246 247// EmitInstrWithCustomInserter - This method should be implemented by targets 248// that mark instructions with the 'usesCustomInserter' flag. These 249// instructions are special in various ways, which require special support to 250// insert. The specified MachineInstr is created but not inserted into any 251// basic blocks, and this method is called to expand it into a sequence of 252// instructions, potentially also creating new basic blocks and control flow. 253// When new basic blocks are inserted and the edges from MBB to its successors 254// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 255// DenseMap. 256MachineBasicBlock * 257TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 258 MachineBasicBlock *MBB) const { 259#ifndef NDEBUG 260 dbgs() << "If a target marks an instruction with " 261 "'usesCustomInserter', it must implement " 262 "TargetLowering::EmitInstrWithCustomInserter!"; 263#endif 264 llvm_unreachable(0); 265} 266 267void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 268 SDNode *Node) const { 269 assert(!MI->hasPostISelHook() && 270 "If a target marks an instruction with 'hasPostISelHook', " 271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 272} 273 274//===----------------------------------------------------------------------===// 275// SelectionDAGISel code 276//===----------------------------------------------------------------------===// 277 278SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 279 CodeGenOpt::Level OL) : 280 MachineFunctionPass(ID), TM(tm), 281 FuncInfo(new FunctionLoweringInfo(TM)), 282 CurDAG(new SelectionDAG(tm, OL)), 283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 284 GFI(), 285 OptLevel(OL), 286 DAGSize(0) { 287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 291 } 292 293SelectionDAGISel::~SelectionDAGISel() { 294 delete SDB; 295 delete CurDAG; 296 delete FuncInfo; 297} 298 299void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 300 AU.addRequired<AliasAnalysis>(); 301 AU.addPreserved<AliasAnalysis>(); 302 AU.addRequired<GCModuleInfo>(); 303 AU.addPreserved<GCModuleInfo>(); 304 AU.addRequired<TargetLibraryInfo>(); 305 if (UseMBPI && OptLevel != CodeGenOpt::None) 306 AU.addRequired<BranchProbabilityInfo>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 311/// may trap on it. In this case we have to split the edge so that the path 312/// through the predecessor block that doesn't go to the phi block doesn't 313/// execute the possibly trapping instruction. 314/// 315/// This is required for correctness, so it must be done at -O0. 316/// 317static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 318 // Loop for blocks with phi nodes. 319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 320 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 321 if (PN == 0) continue; 322 323 ReprocessBlock: 324 // For each block with a PHI node, check to see if any of the input values 325 // are potentially trapping constant expressions. Constant expressions are 326 // the only potentially trapping value that can occur as the argument to a 327 // PHI. 328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 331 if (CE == 0 || !CE->canTrap()) continue; 332 333 // The only case we have to worry about is when the edge is critical. 334 // Since this block has a PHI Node, we assume it has multiple input 335 // edges: check to see if the pred has multiple successors. 336 BasicBlock *Pred = PN->getIncomingBlock(i); 337 if (Pred->getTerminator()->getNumSuccessors() == 1) 338 continue; 339 340 // Okay, we have to split this edge. 341 SplitCriticalEdge(Pred->getTerminator(), 342 GetSuccessorNumber(Pred, BB), SDISel, true); 343 goto ReprocessBlock; 344 } 345 } 346} 347 348bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 349 // Do some sanity-checking on the command-line options. 350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 351 "-fast-isel-verbose requires -fast-isel"); 352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 353 "-fast-isel-abort requires -fast-isel"); 354 355 const Function &Fn = *mf.getFunction(); 356 const TargetInstrInfo &TII = *TM.getInstrInfo(); 357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 358 359 MF = &mf; 360 RegInfo = &MF->getRegInfo(); 361 AA = &getAnalysis<AliasAnalysis>(); 362 LibInfo = &getAnalysis<TargetLibraryInfo>(); 363 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 365 366 TargetSubtargetInfo &ST = 367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 368 ST.resetSubtargetFeatures(MF); 369 TM.resetTargetOptions(MF); 370 371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 372 373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 374 375 CurDAG->init(*MF, TTI); 376 FuncInfo->set(Fn, *MF); 377 378 if (UseMBPI && OptLevel != CodeGenOpt::None) 379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 380 else 381 FuncInfo->BPI = 0; 382 383 SDB->init(GFI, *AA, LibInfo); 384 385 MF->setHasMSInlineAsm(false); 386 SelectAllBasicBlocks(Fn); 387 388 // If the first basic block in the function has live ins that need to be 389 // copied into vregs, emit the copies into the top of the block before 390 // emitting the code for the block. 391 MachineBasicBlock *EntryMBB = MF->begin(); 392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 393 394 DenseMap<unsigned, unsigned> LiveInMap; 395 if (!FuncInfo->ArgDbgValues.empty()) 396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 397 E = RegInfo->livein_end(); LI != E; ++LI) 398 if (LI->second) 399 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 400 401 // Insert DBG_VALUE instructions for function arguments to the entry block. 402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 404 bool hasFI = MI->getOperand(0).isFI(); 405 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 406 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 407 EntryMBB->insert(EntryMBB->begin(), MI); 408 else { 409 MachineInstr *Def = RegInfo->getVRegDef(Reg); 410 MachineBasicBlock::iterator InsertPos = Def; 411 // FIXME: VR def may not be in entry block. 412 Def->getParent()->insert(llvm::next(InsertPos), MI); 413 } 414 415 // If Reg is live-in then update debug info to track its copy in a vreg. 416 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 417 if (LDI != LiveInMap.end()) { 418 assert(!hasFI && "There's no handling of frame pointer updating here yet " 419 "- add if needed"); 420 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 421 MachineBasicBlock::iterator InsertPos = Def; 422 const MDNode *Variable = 423 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 424 unsigned Offset = MI->getOperand(1).getImm(); 425 // Def is never a terminator here, so it is ok to increment InsertPos. 426 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 427 TII.get(TargetOpcode::DBG_VALUE)) 428 .addReg(LDI->second, RegState::Debug) 429 .addImm(Offset).addMetadata(Variable); 430 431 // If this vreg is directly copied into an exported register then 432 // that COPY instructions also need DBG_VALUE, if it is the only 433 // user of LDI->second. 434 MachineInstr *CopyUseMI = NULL; 435 for (MachineRegisterInfo::use_iterator 436 UI = RegInfo->use_begin(LDI->second); 437 MachineInstr *UseMI = UI.skipInstruction();) { 438 if (UseMI->isDebugValue()) continue; 439 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 440 CopyUseMI = UseMI; continue; 441 } 442 // Otherwise this is another use or second copy use. 443 CopyUseMI = NULL; break; 444 } 445 if (CopyUseMI) { 446 MachineInstr *NewMI = 447 BuildMI(*MF, CopyUseMI->getDebugLoc(), 448 TII.get(TargetOpcode::DBG_VALUE)) 449 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 450 .addImm(Offset).addMetadata(Variable); 451 MachineBasicBlock::iterator Pos = CopyUseMI; 452 EntryMBB->insertAfter(Pos, NewMI); 453 } 454 } 455 } 456 457 // Determine if there are any calls in this machine function. 458 MachineFrameInfo *MFI = MF->getFrameInfo(); 459 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 460 ++I) { 461 462 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 463 break; 464 465 const MachineBasicBlock *MBB = I; 466 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 467 II != IE; ++II) { 468 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 469 if ((MCID.isCall() && !MCID.isReturn()) || 470 II->isStackAligningInlineAsm()) { 471 MFI->setHasCalls(true); 472 } 473 if (II->isMSInlineAsm()) { 474 MF->setHasMSInlineAsm(true); 475 } 476 } 477 } 478 479 // Determine if there is a call to setjmp in the machine function. 480 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 481 482 // Replace forward-declared registers with the registers containing 483 // the desired value. 484 MachineRegisterInfo &MRI = MF->getRegInfo(); 485 for (DenseMap<unsigned, unsigned>::iterator 486 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 487 I != E; ++I) { 488 unsigned From = I->first; 489 unsigned To = I->second; 490 // If To is also scheduled to be replaced, find what its ultimate 491 // replacement is. 492 for (;;) { 493 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 494 if (J == E) break; 495 To = J->second; 496 } 497 // Replace it. 498 MRI.replaceRegWith(From, To); 499 } 500 501 // Freeze the set of reserved registers now that MachineFrameInfo has been 502 // set up. All the information required by getReservedRegs() should be 503 // available now. 504 MRI.freezeReservedRegs(*MF); 505 506 // Release function-specific state. SDB and CurDAG are already cleared 507 // at this point. 508 FuncInfo->clear(); 509 510 return true; 511} 512 513void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 514 BasicBlock::const_iterator End, 515 bool &HadTailCall) { 516 // Lower all of the non-terminator instructions. If a call is emitted 517 // as a tail call, cease emitting nodes for this block. Terminators 518 // are handled below. 519 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 520 SDB->visit(*I); 521 522 // Make sure the root of the DAG is up-to-date. 523 CurDAG->setRoot(SDB->getControlRoot()); 524 HadTailCall = SDB->HasTailCall; 525 SDB->clear(); 526 527 // Final step, emit the lowered DAG as machine code. 528 CodeGenAndEmitDAG(); 529} 530 531void SelectionDAGISel::ComputeLiveOutVRegInfo() { 532 SmallPtrSet<SDNode*, 128> VisitedNodes; 533 SmallVector<SDNode*, 128> Worklist; 534 535 Worklist.push_back(CurDAG->getRoot().getNode()); 536 537 APInt KnownZero; 538 APInt KnownOne; 539 540 do { 541 SDNode *N = Worklist.pop_back_val(); 542 543 // If we've already seen this node, ignore it. 544 if (!VisitedNodes.insert(N)) 545 continue; 546 547 // Otherwise, add all chain operands to the worklist. 548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 549 if (N->getOperand(i).getValueType() == MVT::Other) 550 Worklist.push_back(N->getOperand(i).getNode()); 551 552 // If this is a CopyToReg with a vreg dest, process it. 553 if (N->getOpcode() != ISD::CopyToReg) 554 continue; 555 556 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 557 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 558 continue; 559 560 // Ignore non-scalar or non-integer values. 561 SDValue Src = N->getOperand(2); 562 EVT SrcVT = Src.getValueType(); 563 if (!SrcVT.isInteger() || SrcVT.isVector()) 564 continue; 565 566 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 567 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 568 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 569 } while (!Worklist.empty()); 570} 571 572void SelectionDAGISel::CodeGenAndEmitDAG() { 573 std::string GroupName; 574 if (TimePassesIsEnabled) 575 GroupName = "Instruction Selection and Scheduling"; 576 std::string BlockName; 577 int BlockNumber = -1; 578 (void)BlockNumber; 579#ifdef NDEBUG 580 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 581 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 582 ViewSUnitDAGs) 583#endif 584 { 585 BlockNumber = FuncInfo->MBB->getNumber(); 586 BlockName = MF->getName().str() + ":" + 587 FuncInfo->MBB->getBasicBlock()->getName().str(); 588 } 589 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 590 << " '" << BlockName << "'\n"; CurDAG->dump()); 591 592 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 593 594 // Run the DAG combiner in pre-legalize mode. 595 { 596 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 597 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 598 } 599 600 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 601 << " '" << BlockName << "'\n"; CurDAG->dump()); 602 603 // Second step, hack on the DAG until it only uses operations and types that 604 // the target supports. 605 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 606 BlockName); 607 608 bool Changed; 609 { 610 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 611 Changed = CurDAG->LegalizeTypes(); 612 } 613 614 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 615 << " '" << BlockName << "'\n"; CurDAG->dump()); 616 617 if (Changed) { 618 if (ViewDAGCombineLT) 619 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 620 621 // Run the DAG combiner in post-type-legalize mode. 622 { 623 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 624 TimePassesIsEnabled); 625 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 626 } 627 628 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 629 << " '" << BlockName << "'\n"; CurDAG->dump()); 630 631 } 632 633 { 634 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 635 Changed = CurDAG->LegalizeVectors(); 636 } 637 638 if (Changed) { 639 { 640 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 641 CurDAG->LegalizeTypes(); 642 } 643 644 if (ViewDAGCombineLT) 645 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 646 647 // Run the DAG combiner in post-type-legalize mode. 648 { 649 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 650 TimePassesIsEnabled); 651 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 652 } 653 654 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 655 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 656 } 657 658 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 659 660 { 661 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 662 CurDAG->Legalize(); 663 } 664 665 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 666 << " '" << BlockName << "'\n"; CurDAG->dump()); 667 668 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 669 670 // Run the DAG combiner in post-legalize mode. 671 { 672 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 673 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 674 } 675 676 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 677 << " '" << BlockName << "'\n"; CurDAG->dump()); 678 679 if (OptLevel != CodeGenOpt::None) 680 ComputeLiveOutVRegInfo(); 681 682 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 683 684 // Third, instruction select all of the operations to machine code, adding the 685 // code to the MachineBasicBlock. 686 { 687 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 688 DoInstructionSelection(); 689 } 690 691 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 692 << " '" << BlockName << "'\n"; CurDAG->dump()); 693 694 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 695 696 // Schedule machine code. 697 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 698 { 699 NamedRegionTimer T("Instruction Scheduling", GroupName, 700 TimePassesIsEnabled); 701 Scheduler->Run(CurDAG, FuncInfo->MBB); 702 } 703 704 if (ViewSUnitDAGs) Scheduler->viewGraph(); 705 706 // Emit machine code to BB. This can change 'BB' to the last block being 707 // inserted into. 708 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 709 { 710 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 711 712 // FuncInfo->InsertPt is passed by reference and set to the end of the 713 // scheduled instructions. 714 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 715 } 716 717 // If the block was split, make sure we update any references that are used to 718 // update PHI nodes later on. 719 if (FirstMBB != LastMBB) 720 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 721 722 // Free the scheduler state. 723 { 724 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 725 TimePassesIsEnabled); 726 delete Scheduler; 727 } 728 729 // Free the SelectionDAG state, now that we're finished with it. 730 CurDAG->clear(); 731} 732 733namespace { 734/// ISelUpdater - helper class to handle updates of the instruction selection 735/// graph. 736class ISelUpdater : public SelectionDAG::DAGUpdateListener { 737 SelectionDAG::allnodes_iterator &ISelPosition; 738public: 739 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 740 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 741 742 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 743 /// deleted is the current ISelPosition node, update ISelPosition. 744 /// 745 virtual void NodeDeleted(SDNode *N, SDNode *E) { 746 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 747 ++ISelPosition; 748 } 749}; 750} // end anonymous namespace 751 752void SelectionDAGISel::DoInstructionSelection() { 753 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 754 << FuncInfo->MBB->getNumber() 755 << " '" << FuncInfo->MBB->getName() << "'\n"); 756 757 PreprocessISelDAG(); 758 759 // Select target instructions for the DAG. 760 { 761 // Number all nodes with a topological order and set DAGSize. 762 DAGSize = CurDAG->AssignTopologicalOrder(); 763 764 // Create a dummy node (which is not added to allnodes), that adds 765 // a reference to the root node, preventing it from being deleted, 766 // and tracking any changes of the root. 767 HandleSDNode Dummy(CurDAG->getRoot()); 768 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 769 ++ISelPosition; 770 771 // Make sure that ISelPosition gets properly updated when nodes are deleted 772 // in calls made from this function. 773 ISelUpdater ISU(*CurDAG, ISelPosition); 774 775 // The AllNodes list is now topological-sorted. Visit the 776 // nodes by starting at the end of the list (the root of the 777 // graph) and preceding back toward the beginning (the entry 778 // node). 779 while (ISelPosition != CurDAG->allnodes_begin()) { 780 SDNode *Node = --ISelPosition; 781 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 782 // but there are currently some corner cases that it misses. Also, this 783 // makes it theoretically possible to disable the DAGCombiner. 784 if (Node->use_empty()) 785 continue; 786 787 SDNode *ResNode = Select(Node); 788 789 // FIXME: This is pretty gross. 'Select' should be changed to not return 790 // anything at all and this code should be nuked with a tactical strike. 791 792 // If node should not be replaced, continue with the next one. 793 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 794 continue; 795 // Replace node. 796 if (ResNode) { 797 ReplaceUses(Node, ResNode); 798 } 799 800 // If after the replacement this node is not used any more, 801 // remove this dead node. 802 if (Node->use_empty()) // Don't delete EntryToken, etc. 803 CurDAG->RemoveDeadNode(Node); 804 } 805 806 CurDAG->setRoot(Dummy.getValue()); 807 } 808 809 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 810 811 PostprocessISelDAG(); 812} 813 814/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 815/// do other setup for EH landing-pad blocks. 816void SelectionDAGISel::PrepareEHLandingPad() { 817 MachineBasicBlock *MBB = FuncInfo->MBB; 818 819 // Add a label to mark the beginning of the landing pad. Deletion of the 820 // landing pad can thus be detected via the MachineModuleInfo. 821 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 822 823 // Assign the call site to the landing pad's begin label. 824 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 825 826 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 827 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 828 .addSym(Label); 829 830 // Mark exception register as live in. 831 const TargetLowering *TLI = getTargetLowering(); 832 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 833 if (unsigned Reg = TLI->getExceptionPointerRegister()) 834 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 835 836 // Mark exception selector register as live in. 837 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 838 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 839} 840 841/// isFoldedOrDeadInstruction - Return true if the specified instruction is 842/// side-effect free and is either dead or folded into a generated instruction. 843/// Return false if it needs to be emitted. 844static bool isFoldedOrDeadInstruction(const Instruction *I, 845 FunctionLoweringInfo *FuncInfo) { 846 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 847 !isa<TerminatorInst>(I) && // Terminators aren't folded. 848 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 849 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 850 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 851} 852 853#ifndef NDEBUG 854// Collect per Instruction statistics for fast-isel misses. Only those 855// instructions that cause the bail are accounted for. It does not account for 856// instructions higher in the block. Thus, summing the per instructions stats 857// will not add up to what is reported by NumFastIselFailures. 858static void collectFailStats(const Instruction *I) { 859 switch (I->getOpcode()) { 860 default: assert (0 && "<Invalid operator> "); 861 862 // Terminators 863 case Instruction::Ret: NumFastIselFailRet++; return; 864 case Instruction::Br: NumFastIselFailBr++; return; 865 case Instruction::Switch: NumFastIselFailSwitch++; return; 866 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 867 case Instruction::Invoke: NumFastIselFailInvoke++; return; 868 case Instruction::Resume: NumFastIselFailResume++; return; 869 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 870 871 // Standard binary operators... 872 case Instruction::Add: NumFastIselFailAdd++; return; 873 case Instruction::FAdd: NumFastIselFailFAdd++; return; 874 case Instruction::Sub: NumFastIselFailSub++; return; 875 case Instruction::FSub: NumFastIselFailFSub++; return; 876 case Instruction::Mul: NumFastIselFailMul++; return; 877 case Instruction::FMul: NumFastIselFailFMul++; return; 878 case Instruction::UDiv: NumFastIselFailUDiv++; return; 879 case Instruction::SDiv: NumFastIselFailSDiv++; return; 880 case Instruction::FDiv: NumFastIselFailFDiv++; return; 881 case Instruction::URem: NumFastIselFailURem++; return; 882 case Instruction::SRem: NumFastIselFailSRem++; return; 883 case Instruction::FRem: NumFastIselFailFRem++; return; 884 885 // Logical operators... 886 case Instruction::And: NumFastIselFailAnd++; return; 887 case Instruction::Or: NumFastIselFailOr++; return; 888 case Instruction::Xor: NumFastIselFailXor++; return; 889 890 // Memory instructions... 891 case Instruction::Alloca: NumFastIselFailAlloca++; return; 892 case Instruction::Load: NumFastIselFailLoad++; return; 893 case Instruction::Store: NumFastIselFailStore++; return; 894 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 895 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 896 case Instruction::Fence: NumFastIselFailFence++; return; 897 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 898 899 // Convert instructions... 900 case Instruction::Trunc: NumFastIselFailTrunc++; return; 901 case Instruction::ZExt: NumFastIselFailZExt++; return; 902 case Instruction::SExt: NumFastIselFailSExt++; return; 903 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 904 case Instruction::FPExt: NumFastIselFailFPExt++; return; 905 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 906 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 907 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 908 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 909 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 910 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 911 case Instruction::BitCast: NumFastIselFailBitCast++; return; 912 913 // Other instructions... 914 case Instruction::ICmp: NumFastIselFailICmp++; return; 915 case Instruction::FCmp: NumFastIselFailFCmp++; return; 916 case Instruction::PHI: NumFastIselFailPHI++; return; 917 case Instruction::Select: NumFastIselFailSelect++; return; 918 case Instruction::Call: NumFastIselFailCall++; return; 919 case Instruction::Shl: NumFastIselFailShl++; return; 920 case Instruction::LShr: NumFastIselFailLShr++; return; 921 case Instruction::AShr: NumFastIselFailAShr++; return; 922 case Instruction::VAArg: NumFastIselFailVAArg++; return; 923 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 924 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 925 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 926 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 927 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 928 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 929 } 930} 931#endif 932 933void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 934 // Initialize the Fast-ISel state, if needed. 935 FastISel *FastIS = 0; 936 if (TM.Options.EnableFastISel) 937 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 938 939 // Iterate over all basic blocks in the function. 940 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 941 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 942 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 943 const BasicBlock *LLVMBB = *I; 944 945 if (OptLevel != CodeGenOpt::None) { 946 bool AllPredsVisited = true; 947 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 948 PI != PE; ++PI) { 949 if (!FuncInfo->VisitedBBs.count(*PI)) { 950 AllPredsVisited = false; 951 break; 952 } 953 } 954 955 if (AllPredsVisited) { 956 for (BasicBlock::const_iterator I = LLVMBB->begin(); 957 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 958 FuncInfo->ComputePHILiveOutRegInfo(PN); 959 } else { 960 for (BasicBlock::const_iterator I = LLVMBB->begin(); 961 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 962 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 963 } 964 965 FuncInfo->VisitedBBs.insert(LLVMBB); 966 } 967 968 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 969 BasicBlock::const_iterator const End = LLVMBB->end(); 970 BasicBlock::const_iterator BI = End; 971 972 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 973 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 974 975 // Setup an EH landing-pad block. 976 FuncInfo->ExceptionPointerVirtReg = 0; 977 FuncInfo->ExceptionSelectorVirtReg = 0; 978 if (FuncInfo->MBB->isLandingPad()) 979 PrepareEHLandingPad(); 980 981 // Before doing SelectionDAG ISel, see if FastISel has been requested. 982 if (FastIS) { 983 FastIS->startNewBlock(); 984 985 // Emit code for any incoming arguments. This must happen before 986 // beginning FastISel on the entry block. 987 if (LLVMBB == &Fn.getEntryBlock()) { 988 ++NumEntryBlocks; 989 990 // Lower any arguments needed in this block if this is the entry block. 991 if (!FastIS->LowerArguments()) { 992 // Fast isel failed to lower these arguments 993 ++NumFastIselFailLowerArguments; 994 if (EnableFastISelAbortArgs) 995 llvm_unreachable("FastISel didn't lower all arguments"); 996 997 // Use SelectionDAG argument lowering 998 LowerArguments(Fn); 999 CurDAG->setRoot(SDB->getControlRoot()); 1000 SDB->clear(); 1001 CodeGenAndEmitDAG(); 1002 } 1003 1004 // If we inserted any instructions at the beginning, make a note of 1005 // where they are, so we can be sure to emit subsequent instructions 1006 // after them. 1007 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1008 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1009 else 1010 FastIS->setLastLocalValue(0); 1011 } 1012 1013 unsigned NumFastIselRemaining = std::distance(Begin, End); 1014 // Do FastISel on as many instructions as possible. 1015 for (; BI != Begin; --BI) { 1016 const Instruction *Inst = llvm::prior(BI); 1017 1018 // If we no longer require this instruction, skip it. 1019 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1020 --NumFastIselRemaining; 1021 continue; 1022 } 1023 1024 // Bottom-up: reset the insert pos at the top, after any local-value 1025 // instructions. 1026 FastIS->recomputeInsertPt(); 1027 1028 // Try to select the instruction with FastISel. 1029 if (FastIS->SelectInstruction(Inst)) { 1030 --NumFastIselRemaining; 1031 ++NumFastIselSuccess; 1032 // If fast isel succeeded, skip over all the folded instructions, and 1033 // then see if there is a load right before the selected instructions. 1034 // Try to fold the load if so. 1035 const Instruction *BeforeInst = Inst; 1036 while (BeforeInst != Begin) { 1037 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1038 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1039 break; 1040 } 1041 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1042 BeforeInst->hasOneUse() && 1043 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1044 // If we succeeded, don't re-select the load. 1045 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1046 --NumFastIselRemaining; 1047 ++NumFastIselSuccess; 1048 } 1049 continue; 1050 } 1051 1052#ifndef NDEBUG 1053 if (EnableFastISelVerbose2) 1054 collectFailStats(Inst); 1055#endif 1056 1057 // Then handle certain instructions as single-LLVM-Instruction blocks. 1058 if (isa<CallInst>(Inst)) { 1059 1060 if (EnableFastISelVerbose || EnableFastISelAbort) { 1061 dbgs() << "FastISel missed call: "; 1062 Inst->dump(); 1063 } 1064 1065 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1066 unsigned &R = FuncInfo->ValueMap[Inst]; 1067 if (!R) 1068 R = FuncInfo->CreateRegs(Inst->getType()); 1069 } 1070 1071 bool HadTailCall = false; 1072 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1073 SelectBasicBlock(Inst, BI, HadTailCall); 1074 1075 // If the call was emitted as a tail call, we're done with the block. 1076 // We also need to delete any previously emitted instructions. 1077 if (HadTailCall) { 1078 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1079 --BI; 1080 break; 1081 } 1082 1083 // Recompute NumFastIselRemaining as Selection DAG instruction 1084 // selection may have handled the call, input args, etc. 1085 unsigned RemainingNow = std::distance(Begin, BI); 1086 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1087 NumFastIselRemaining = RemainingNow; 1088 continue; 1089 } 1090 1091 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1092 // Don't abort, and use a different message for terminator misses. 1093 NumFastIselFailures += NumFastIselRemaining; 1094 if (EnableFastISelVerbose || EnableFastISelAbort) { 1095 dbgs() << "FastISel missed terminator: "; 1096 Inst->dump(); 1097 } 1098 } else { 1099 NumFastIselFailures += NumFastIselRemaining; 1100 if (EnableFastISelVerbose || EnableFastISelAbort) { 1101 dbgs() << "FastISel miss: "; 1102 Inst->dump(); 1103 } 1104 if (EnableFastISelAbort) 1105 // The "fast" selector couldn't handle something and bailed. 1106 // For the purpose of debugging, just abort. 1107 llvm_unreachable("FastISel didn't select the entire block"); 1108 } 1109 break; 1110 } 1111 1112 FastIS->recomputeInsertPt(); 1113 } else { 1114 // Lower any arguments needed in this block if this is the entry block. 1115 if (LLVMBB == &Fn.getEntryBlock()) { 1116 ++NumEntryBlocks; 1117 LowerArguments(Fn); 1118 } 1119 } 1120 1121 if (Begin != BI) 1122 ++NumDAGBlocks; 1123 else 1124 ++NumFastIselBlocks; 1125 1126 if (Begin != BI) { 1127 // Run SelectionDAG instruction selection on the remainder of the block 1128 // not handled by FastISel. If FastISel is not run, this is the entire 1129 // block. 1130 bool HadTailCall; 1131 SelectBasicBlock(Begin, BI, HadTailCall); 1132 } 1133 1134 FinishBasicBlock(); 1135 FuncInfo->PHINodesToUpdate.clear(); 1136 } 1137 1138 delete FastIS; 1139 SDB->clearDanglingDebugInfo(); 1140} 1141 1142void 1143SelectionDAGISel::FinishBasicBlock() { 1144 1145 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1146 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1147 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1148 dbgs() << "Node " << i << " : (" 1149 << FuncInfo->PHINodesToUpdate[i].first 1150 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1151 1152 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1153 // PHI nodes in successors. 1154 if (SDB->SwitchCases.empty() && 1155 SDB->JTCases.empty() && 1156 SDB->BitTestCases.empty()) { 1157 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1158 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1159 assert(PHI->isPHI() && 1160 "This is not a machine PHI node that we are updating!"); 1161 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1162 continue; 1163 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1164 } 1165 return; 1166 } 1167 1168 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1169 // Lower header first, if it wasn't already lowered 1170 if (!SDB->BitTestCases[i].Emitted) { 1171 // Set the current basic block to the mbb we wish to insert the code into 1172 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1173 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1174 // Emit the code 1175 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1176 CurDAG->setRoot(SDB->getRoot()); 1177 SDB->clear(); 1178 CodeGenAndEmitDAG(); 1179 } 1180 1181 uint32_t UnhandledWeight = 0; 1182 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1183 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1184 1185 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1186 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1187 // Set the current basic block to the mbb we wish to insert the code into 1188 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1189 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1190 // Emit the code 1191 if (j+1 != ej) 1192 SDB->visitBitTestCase(SDB->BitTestCases[i], 1193 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1194 UnhandledWeight, 1195 SDB->BitTestCases[i].Reg, 1196 SDB->BitTestCases[i].Cases[j], 1197 FuncInfo->MBB); 1198 else 1199 SDB->visitBitTestCase(SDB->BitTestCases[i], 1200 SDB->BitTestCases[i].Default, 1201 UnhandledWeight, 1202 SDB->BitTestCases[i].Reg, 1203 SDB->BitTestCases[i].Cases[j], 1204 FuncInfo->MBB); 1205 1206 1207 CurDAG->setRoot(SDB->getRoot()); 1208 SDB->clear(); 1209 CodeGenAndEmitDAG(); 1210 } 1211 1212 // Update PHI Nodes 1213 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1214 pi != pe; ++pi) { 1215 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1216 MachineBasicBlock *PHIBB = PHI->getParent(); 1217 assert(PHI->isPHI() && 1218 "This is not a machine PHI node that we are updating!"); 1219 // This is "default" BB. We have two jumps to it. From "header" BB and 1220 // from last "case" BB. 1221 if (PHIBB == SDB->BitTestCases[i].Default) 1222 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1223 .addMBB(SDB->BitTestCases[i].Parent) 1224 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1225 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1226 // One of "cases" BB. 1227 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1228 j != ej; ++j) { 1229 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1230 if (cBB->isSuccessor(PHIBB)) 1231 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1232 } 1233 } 1234 } 1235 SDB->BitTestCases.clear(); 1236 1237 // If the JumpTable record is filled in, then we need to emit a jump table. 1238 // Updating the PHI nodes is tricky in this case, since we need to determine 1239 // whether the PHI is a successor of the range check MBB or the jump table MBB 1240 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1241 // Lower header first, if it wasn't already lowered 1242 if (!SDB->JTCases[i].first.Emitted) { 1243 // Set the current basic block to the mbb we wish to insert the code into 1244 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1245 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1246 // Emit the code 1247 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1248 FuncInfo->MBB); 1249 CurDAG->setRoot(SDB->getRoot()); 1250 SDB->clear(); 1251 CodeGenAndEmitDAG(); 1252 } 1253 1254 // Set the current basic block to the mbb we wish to insert the code into 1255 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1256 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1257 // Emit the code 1258 SDB->visitJumpTable(SDB->JTCases[i].second); 1259 CurDAG->setRoot(SDB->getRoot()); 1260 SDB->clear(); 1261 CodeGenAndEmitDAG(); 1262 1263 // Update PHI Nodes 1264 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1265 pi != pe; ++pi) { 1266 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1267 MachineBasicBlock *PHIBB = PHI->getParent(); 1268 assert(PHI->isPHI() && 1269 "This is not a machine PHI node that we are updating!"); 1270 // "default" BB. We can go there only from header BB. 1271 if (PHIBB == SDB->JTCases[i].second.Default) 1272 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1273 .addMBB(SDB->JTCases[i].first.HeaderBB); 1274 // JT BB. Just iterate over successors here 1275 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1276 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1277 } 1278 } 1279 SDB->JTCases.clear(); 1280 1281 // If the switch block involved a branch to one of the actual successors, we 1282 // need to update PHI nodes in that block. 1283 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1284 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1285 assert(PHI->isPHI() && 1286 "This is not a machine PHI node that we are updating!"); 1287 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1288 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1289 } 1290 1291 // If we generated any switch lowering information, build and codegen any 1292 // additional DAGs necessary. 1293 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1294 // Set the current basic block to the mbb we wish to insert the code into 1295 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1296 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1297 1298 // Determine the unique successors. 1299 SmallVector<MachineBasicBlock *, 2> Succs; 1300 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1301 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1302 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1303 1304 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1305 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1306 CurDAG->setRoot(SDB->getRoot()); 1307 SDB->clear(); 1308 CodeGenAndEmitDAG(); 1309 1310 // Remember the last block, now that any splitting is done, for use in 1311 // populating PHI nodes in successors. 1312 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1313 1314 // Handle any PHI nodes in successors of this chunk, as if we were coming 1315 // from the original BB before switch expansion. Note that PHI nodes can 1316 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1317 // handle them the right number of times. 1318 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1319 FuncInfo->MBB = Succs[i]; 1320 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1321 // FuncInfo->MBB may have been removed from the CFG if a branch was 1322 // constant folded. 1323 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1324 for (MachineBasicBlock::iterator 1325 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1326 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1327 MachineInstrBuilder PHI(*MF, MBBI); 1328 // This value for this PHI node is recorded in PHINodesToUpdate. 1329 for (unsigned pn = 0; ; ++pn) { 1330 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1331 "Didn't find PHI entry!"); 1332 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1333 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1334 break; 1335 } 1336 } 1337 } 1338 } 1339 } 1340 } 1341 SDB->SwitchCases.clear(); 1342} 1343 1344 1345/// Create the scheduler. If a specific scheduler was specified 1346/// via the SchedulerRegistry, use it, otherwise select the 1347/// one preferred by the target. 1348/// 1349ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1350 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1351 1352 if (!Ctor) { 1353 Ctor = ISHeuristic; 1354 RegisterScheduler::setDefault(Ctor); 1355 } 1356 1357 return Ctor(this, OptLevel); 1358} 1359 1360//===----------------------------------------------------------------------===// 1361// Helper functions used by the generated instruction selector. 1362//===----------------------------------------------------------------------===// 1363// Calls to these methods are generated by tblgen. 1364 1365/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1366/// the dag combiner simplified the 255, we still want to match. RHS is the 1367/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1368/// specified in the .td file (e.g. 255). 1369bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1370 int64_t DesiredMaskS) const { 1371 const APInt &ActualMask = RHS->getAPIntValue(); 1372 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1373 1374 // If the actual mask exactly matches, success! 1375 if (ActualMask == DesiredMask) 1376 return true; 1377 1378 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1379 if (ActualMask.intersects(~DesiredMask)) 1380 return false; 1381 1382 // Otherwise, the DAG Combiner may have proven that the value coming in is 1383 // either already zero or is not demanded. Check for known zero input bits. 1384 APInt NeededMask = DesiredMask & ~ActualMask; 1385 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1386 return true; 1387 1388 // TODO: check to see if missing bits are just not demanded. 1389 1390 // Otherwise, this pattern doesn't match. 1391 return false; 1392} 1393 1394/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1395/// the dag combiner simplified the 255, we still want to match. RHS is the 1396/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1397/// specified in the .td file (e.g. 255). 1398bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1399 int64_t DesiredMaskS) const { 1400 const APInt &ActualMask = RHS->getAPIntValue(); 1401 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1402 1403 // If the actual mask exactly matches, success! 1404 if (ActualMask == DesiredMask) 1405 return true; 1406 1407 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1408 if (ActualMask.intersects(~DesiredMask)) 1409 return false; 1410 1411 // Otherwise, the DAG Combiner may have proven that the value coming in is 1412 // either already zero or is not demanded. Check for known zero input bits. 1413 APInt NeededMask = DesiredMask & ~ActualMask; 1414 1415 APInt KnownZero, KnownOne; 1416 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1417 1418 // If all the missing bits in the or are already known to be set, match! 1419 if ((NeededMask & KnownOne) == NeededMask) 1420 return true; 1421 1422 // TODO: check to see if missing bits are just not demanded. 1423 1424 // Otherwise, this pattern doesn't match. 1425 return false; 1426} 1427 1428 1429/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1430/// by tblgen. Others should not call it. 1431void SelectionDAGISel:: 1432SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1433 std::vector<SDValue> InOps; 1434 std::swap(InOps, Ops); 1435 1436 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1437 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1438 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1439 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1440 1441 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1442 if (InOps[e-1].getValueType() == MVT::Glue) 1443 --e; // Don't process a glue operand if it is here. 1444 1445 while (i != e) { 1446 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1447 if (!InlineAsm::isMemKind(Flags)) { 1448 // Just skip over this operand, copying the operands verbatim. 1449 Ops.insert(Ops.end(), InOps.begin()+i, 1450 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1451 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1452 } else { 1453 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1454 "Memory operand with multiple values?"); 1455 // Otherwise, this is a memory operand. Ask the target to select it. 1456 std::vector<SDValue> SelOps; 1457 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1458 report_fatal_error("Could not match memory address. Inline asm" 1459 " failure!"); 1460 1461 // Add this to the output node. 1462 unsigned NewFlags = 1463 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1464 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1465 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1466 i += 2; 1467 } 1468 } 1469 1470 // Add the glue input back if present. 1471 if (e != InOps.size()) 1472 Ops.push_back(InOps.back()); 1473} 1474 1475/// findGlueUse - Return use of MVT::Glue value produced by the specified 1476/// SDNode. 1477/// 1478static SDNode *findGlueUse(SDNode *N) { 1479 unsigned FlagResNo = N->getNumValues()-1; 1480 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1481 SDUse &Use = I.getUse(); 1482 if (Use.getResNo() == FlagResNo) 1483 return Use.getUser(); 1484 } 1485 return NULL; 1486} 1487 1488/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1489/// This function recursively traverses up the operand chain, ignoring 1490/// certain nodes. 1491static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1492 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1493 bool IgnoreChains) { 1494 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1495 // greater than all of its (recursive) operands. If we scan to a point where 1496 // 'use' is smaller than the node we're scanning for, then we know we will 1497 // never find it. 1498 // 1499 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1500 // happen because we scan down to newly selected nodes in the case of glue 1501 // uses. 1502 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1503 return false; 1504 1505 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1506 // won't fail if we scan it again. 1507 if (!Visited.insert(Use)) 1508 return false; 1509 1510 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1511 // Ignore chain uses, they are validated by HandleMergeInputChains. 1512 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1513 continue; 1514 1515 SDNode *N = Use->getOperand(i).getNode(); 1516 if (N == Def) { 1517 if (Use == ImmedUse || Use == Root) 1518 continue; // We are not looking for immediate use. 1519 assert(N != Root); 1520 return true; 1521 } 1522 1523 // Traverse up the operand chain. 1524 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1525 return true; 1526 } 1527 return false; 1528} 1529 1530/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1531/// operand node N of U during instruction selection that starts at Root. 1532bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1533 SDNode *Root) const { 1534 if (OptLevel == CodeGenOpt::None) return false; 1535 return N.hasOneUse(); 1536} 1537 1538/// IsLegalToFold - Returns true if the specific operand node N of 1539/// U can be folded during instruction selection that starts at Root. 1540bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1541 CodeGenOpt::Level OptLevel, 1542 bool IgnoreChains) { 1543 if (OptLevel == CodeGenOpt::None) return false; 1544 1545 // If Root use can somehow reach N through a path that that doesn't contain 1546 // U then folding N would create a cycle. e.g. In the following 1547 // diagram, Root can reach N through X. If N is folded into into Root, then 1548 // X is both a predecessor and a successor of U. 1549 // 1550 // [N*] // 1551 // ^ ^ // 1552 // / \ // 1553 // [U*] [X]? // 1554 // ^ ^ // 1555 // \ / // 1556 // \ / // 1557 // [Root*] // 1558 // 1559 // * indicates nodes to be folded together. 1560 // 1561 // If Root produces glue, then it gets (even more) interesting. Since it 1562 // will be "glued" together with its glue use in the scheduler, we need to 1563 // check if it might reach N. 1564 // 1565 // [N*] // 1566 // ^ ^ // 1567 // / \ // 1568 // [U*] [X]? // 1569 // ^ ^ // 1570 // \ \ // 1571 // \ | // 1572 // [Root*] | // 1573 // ^ | // 1574 // f | // 1575 // | / // 1576 // [Y] / // 1577 // ^ / // 1578 // f / // 1579 // | / // 1580 // [GU] // 1581 // 1582 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1583 // (call it Fold), then X is a predecessor of GU and a successor of 1584 // Fold. But since Fold and GU are glued together, this will create 1585 // a cycle in the scheduling graph. 1586 1587 // If the node has glue, walk down the graph to the "lowest" node in the 1588 // glueged set. 1589 EVT VT = Root->getValueType(Root->getNumValues()-1); 1590 while (VT == MVT::Glue) { 1591 SDNode *GU = findGlueUse(Root); 1592 if (GU == NULL) 1593 break; 1594 Root = GU; 1595 VT = Root->getValueType(Root->getNumValues()-1); 1596 1597 // If our query node has a glue result with a use, we've walked up it. If 1598 // the user (which has already been selected) has a chain or indirectly uses 1599 // the chain, our WalkChainUsers predicate will not consider it. Because of 1600 // this, we cannot ignore chains in this predicate. 1601 IgnoreChains = false; 1602 } 1603 1604 1605 SmallPtrSet<SDNode*, 16> Visited; 1606 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1607} 1608 1609SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1610 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1611 SelectInlineAsmMemoryOperands(Ops); 1612 1613 EVT VTs[] = { MVT::Other, MVT::Glue }; 1614 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1615 VTs, &Ops[0], Ops.size()); 1616 New->setNodeId(-1); 1617 return New.getNode(); 1618} 1619 1620SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1621 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1622} 1623 1624/// GetVBR - decode a vbr encoding whose top bit is set. 1625LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1626GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1627 assert(Val >= 128 && "Not a VBR"); 1628 Val &= 127; // Remove first vbr bit. 1629 1630 unsigned Shift = 7; 1631 uint64_t NextBits; 1632 do { 1633 NextBits = MatcherTable[Idx++]; 1634 Val |= (NextBits&127) << Shift; 1635 Shift += 7; 1636 } while (NextBits & 128); 1637 1638 return Val; 1639} 1640 1641 1642/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1643/// interior glue and chain results to use the new glue and chain results. 1644void SelectionDAGISel:: 1645UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1646 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1647 SDValue InputGlue, 1648 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1649 bool isMorphNodeTo) { 1650 SmallVector<SDNode*, 4> NowDeadNodes; 1651 1652 // Now that all the normal results are replaced, we replace the chain and 1653 // glue results if present. 1654 if (!ChainNodesMatched.empty()) { 1655 assert(InputChain.getNode() != 0 && 1656 "Matched input chains but didn't produce a chain"); 1657 // Loop over all of the nodes we matched that produced a chain result. 1658 // Replace all the chain results with the final chain we ended up with. 1659 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1660 SDNode *ChainNode = ChainNodesMatched[i]; 1661 1662 // If this node was already deleted, don't look at it. 1663 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1664 continue; 1665 1666 // Don't replace the results of the root node if we're doing a 1667 // MorphNodeTo. 1668 if (ChainNode == NodeToMatch && isMorphNodeTo) 1669 continue; 1670 1671 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1672 if (ChainVal.getValueType() == MVT::Glue) 1673 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1674 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1675 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1676 1677 // If the node became dead and we haven't already seen it, delete it. 1678 if (ChainNode->use_empty() && 1679 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1680 NowDeadNodes.push_back(ChainNode); 1681 } 1682 } 1683 1684 // If the result produces glue, update any glue results in the matched 1685 // pattern with the glue result. 1686 if (InputGlue.getNode() != 0) { 1687 // Handle any interior nodes explicitly marked. 1688 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1689 SDNode *FRN = GlueResultNodesMatched[i]; 1690 1691 // If this node was already deleted, don't look at it. 1692 if (FRN->getOpcode() == ISD::DELETED_NODE) 1693 continue; 1694 1695 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1696 "Doesn't have a glue result"); 1697 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1698 InputGlue); 1699 1700 // If the node became dead and we haven't already seen it, delete it. 1701 if (FRN->use_empty() && 1702 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1703 NowDeadNodes.push_back(FRN); 1704 } 1705 } 1706 1707 if (!NowDeadNodes.empty()) 1708 CurDAG->RemoveDeadNodes(NowDeadNodes); 1709 1710 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1711} 1712 1713enum ChainResult { 1714 CR_Simple, 1715 CR_InducesCycle, 1716 CR_LeadsToInteriorNode 1717}; 1718 1719/// WalkChainUsers - Walk down the users of the specified chained node that is 1720/// part of the pattern we're matching, looking at all of the users we find. 1721/// This determines whether something is an interior node, whether we have a 1722/// non-pattern node in between two pattern nodes (which prevent folding because 1723/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1724/// between pattern nodes (in which case the TF becomes part of the pattern). 1725/// 1726/// The walk we do here is guaranteed to be small because we quickly get down to 1727/// already selected nodes "below" us. 1728static ChainResult 1729WalkChainUsers(const SDNode *ChainedNode, 1730 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1731 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1732 ChainResult Result = CR_Simple; 1733 1734 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1735 E = ChainedNode->use_end(); UI != E; ++UI) { 1736 // Make sure the use is of the chain, not some other value we produce. 1737 if (UI.getUse().getValueType() != MVT::Other) continue; 1738 1739 SDNode *User = *UI; 1740 1741 // If we see an already-selected machine node, then we've gone beyond the 1742 // pattern that we're selecting down into the already selected chunk of the 1743 // DAG. 1744 if (User->isMachineOpcode() || 1745 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1746 continue; 1747 1748 unsigned UserOpcode = User->getOpcode(); 1749 if (UserOpcode == ISD::CopyToReg || 1750 UserOpcode == ISD::CopyFromReg || 1751 UserOpcode == ISD::INLINEASM || 1752 UserOpcode == ISD::EH_LABEL || 1753 UserOpcode == ISD::LIFETIME_START || 1754 UserOpcode == ISD::LIFETIME_END) { 1755 // If their node ID got reset to -1 then they've already been selected. 1756 // Treat them like a MachineOpcode. 1757 if (User->getNodeId() == -1) 1758 continue; 1759 } 1760 1761 // If we have a TokenFactor, we handle it specially. 1762 if (User->getOpcode() != ISD::TokenFactor) { 1763 // If the node isn't a token factor and isn't part of our pattern, then it 1764 // must be a random chained node in between two nodes we're selecting. 1765 // This happens when we have something like: 1766 // x = load ptr 1767 // call 1768 // y = x+4 1769 // store y -> ptr 1770 // Because we structurally match the load/store as a read/modify/write, 1771 // but the call is chained between them. We cannot fold in this case 1772 // because it would induce a cycle in the graph. 1773 if (!std::count(ChainedNodesInPattern.begin(), 1774 ChainedNodesInPattern.end(), User)) 1775 return CR_InducesCycle; 1776 1777 // Otherwise we found a node that is part of our pattern. For example in: 1778 // x = load ptr 1779 // y = x+4 1780 // store y -> ptr 1781 // This would happen when we're scanning down from the load and see the 1782 // store as a user. Record that there is a use of ChainedNode that is 1783 // part of the pattern and keep scanning uses. 1784 Result = CR_LeadsToInteriorNode; 1785 InteriorChainedNodes.push_back(User); 1786 continue; 1787 } 1788 1789 // If we found a TokenFactor, there are two cases to consider: first if the 1790 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1791 // uses of the TF are in our pattern) we just want to ignore it. Second, 1792 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1793 // [Load chain] 1794 // ^ 1795 // | 1796 // [Load] 1797 // ^ ^ 1798 // | \ DAG's like cheese 1799 // / \ do you? 1800 // / | 1801 // [TokenFactor] [Op] 1802 // ^ ^ 1803 // | | 1804 // \ / 1805 // \ / 1806 // [Store] 1807 // 1808 // In this case, the TokenFactor becomes part of our match and we rewrite it 1809 // as a new TokenFactor. 1810 // 1811 // To distinguish these two cases, do a recursive walk down the uses. 1812 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1813 case CR_Simple: 1814 // If the uses of the TokenFactor are just already-selected nodes, ignore 1815 // it, it is "below" our pattern. 1816 continue; 1817 case CR_InducesCycle: 1818 // If the uses of the TokenFactor lead to nodes that are not part of our 1819 // pattern that are not selected, folding would turn this into a cycle, 1820 // bail out now. 1821 return CR_InducesCycle; 1822 case CR_LeadsToInteriorNode: 1823 break; // Otherwise, keep processing. 1824 } 1825 1826 // Okay, we know we're in the interesting interior case. The TokenFactor 1827 // is now going to be considered part of the pattern so that we rewrite its 1828 // uses (it may have uses that are not part of the pattern) with the 1829 // ultimate chain result of the generated code. We will also add its chain 1830 // inputs as inputs to the ultimate TokenFactor we create. 1831 Result = CR_LeadsToInteriorNode; 1832 ChainedNodesInPattern.push_back(User); 1833 InteriorChainedNodes.push_back(User); 1834 continue; 1835 } 1836 1837 return Result; 1838} 1839 1840/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1841/// operation for when the pattern matched at least one node with a chains. The 1842/// input vector contains a list of all of the chained nodes that we match. We 1843/// must determine if this is a valid thing to cover (i.e. matching it won't 1844/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1845/// be used as the input node chain for the generated nodes. 1846static SDValue 1847HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1848 SelectionDAG *CurDAG) { 1849 // Walk all of the chained nodes we've matched, recursively scanning down the 1850 // users of the chain result. This adds any TokenFactor nodes that are caught 1851 // in between chained nodes to the chained and interior nodes list. 1852 SmallVector<SDNode*, 3> InteriorChainedNodes; 1853 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1854 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1855 InteriorChainedNodes) == CR_InducesCycle) 1856 return SDValue(); // Would induce a cycle. 1857 } 1858 1859 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1860 // that we are interested in. Form our input TokenFactor node. 1861 SmallVector<SDValue, 3> InputChains; 1862 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1863 // Add the input chain of this node to the InputChains list (which will be 1864 // the operands of the generated TokenFactor) if it's not an interior node. 1865 SDNode *N = ChainNodesMatched[i]; 1866 if (N->getOpcode() != ISD::TokenFactor) { 1867 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1868 continue; 1869 1870 // Otherwise, add the input chain. 1871 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1872 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1873 InputChains.push_back(InChain); 1874 continue; 1875 } 1876 1877 // If we have a token factor, we want to add all inputs of the token factor 1878 // that are not part of the pattern we're matching. 1879 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1880 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1881 N->getOperand(op).getNode())) 1882 InputChains.push_back(N->getOperand(op)); 1883 } 1884 } 1885 1886 SDValue Res; 1887 if (InputChains.size() == 1) 1888 return InputChains[0]; 1889 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 1890 MVT::Other, &InputChains[0], InputChains.size()); 1891} 1892 1893/// MorphNode - Handle morphing a node in place for the selector. 1894SDNode *SelectionDAGISel:: 1895MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1896 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1897 // It is possible we're using MorphNodeTo to replace a node with no 1898 // normal results with one that has a normal result (or we could be 1899 // adding a chain) and the input could have glue and chains as well. 1900 // In this case we need to shift the operands down. 1901 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1902 // than the old isel though. 1903 int OldGlueResultNo = -1, OldChainResultNo = -1; 1904 1905 unsigned NTMNumResults = Node->getNumValues(); 1906 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1907 OldGlueResultNo = NTMNumResults-1; 1908 if (NTMNumResults != 1 && 1909 Node->getValueType(NTMNumResults-2) == MVT::Other) 1910 OldChainResultNo = NTMNumResults-2; 1911 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1912 OldChainResultNo = NTMNumResults-1; 1913 1914 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1915 // that this deletes operands of the old node that become dead. 1916 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1917 1918 // MorphNodeTo can operate in two ways: if an existing node with the 1919 // specified operands exists, it can just return it. Otherwise, it 1920 // updates the node in place to have the requested operands. 1921 if (Res == Node) { 1922 // If we updated the node in place, reset the node ID. To the isel, 1923 // this should be just like a newly allocated machine node. 1924 Res->setNodeId(-1); 1925 } 1926 1927 unsigned ResNumResults = Res->getNumValues(); 1928 // Move the glue if needed. 1929 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1930 (unsigned)OldGlueResultNo != ResNumResults-1) 1931 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1932 SDValue(Res, ResNumResults-1)); 1933 1934 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1935 --ResNumResults; 1936 1937 // Move the chain reference if needed. 1938 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1939 (unsigned)OldChainResultNo != ResNumResults-1) 1940 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1941 SDValue(Res, ResNumResults-1)); 1942 1943 // Otherwise, no replacement happened because the node already exists. Replace 1944 // Uses of the old node with the new one. 1945 if (Res != Node) 1946 CurDAG->ReplaceAllUsesWith(Node, Res); 1947 1948 return Res; 1949} 1950 1951/// CheckSame - Implements OP_CheckSame. 1952LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1953CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1954 SDValue N, 1955 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1956 // Accept if it is exactly the same as a previously recorded node. 1957 unsigned RecNo = MatcherTable[MatcherIndex++]; 1958 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1959 return N == RecordedNodes[RecNo].first; 1960} 1961 1962/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1963LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1964CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1965 const SelectionDAGISel &SDISel) { 1966 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1967} 1968 1969/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1970LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1971CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1972 const SelectionDAGISel &SDISel, SDNode *N) { 1973 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1974} 1975 1976LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1977CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1978 SDNode *N) { 1979 uint16_t Opc = MatcherTable[MatcherIndex++]; 1980 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1981 return N->getOpcode() == Opc; 1982} 1983 1984LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1985CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1986 SDValue N, const TargetLowering *TLI) { 1987 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1988 if (N.getValueType() == VT) return true; 1989 1990 // Handle the case when VT is iPTR. 1991 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 1992} 1993 1994LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1995CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1996 SDValue N, const TargetLowering *TLI, 1997 unsigned ChildNo) { 1998 if (ChildNo >= N.getNumOperands()) 1999 return false; // Match fails if out of range child #. 2000 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2001} 2002 2003LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2004CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2005 SDValue N) { 2006 return cast<CondCodeSDNode>(N)->get() == 2007 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2008} 2009 2010LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2011CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2012 SDValue N, const TargetLowering *TLI) { 2013 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2014 if (cast<VTSDNode>(N)->getVT() == VT) 2015 return true; 2016 2017 // Handle the case when VT is iPTR. 2018 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2019} 2020 2021LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2022CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2023 SDValue N) { 2024 int64_t Val = MatcherTable[MatcherIndex++]; 2025 if (Val & 128) 2026 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2027 2028 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2029 return C != 0 && C->getSExtValue() == Val; 2030} 2031 2032LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2033CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2034 SDValue N, const SelectionDAGISel &SDISel) { 2035 int64_t Val = MatcherTable[MatcherIndex++]; 2036 if (Val & 128) 2037 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2038 2039 if (N->getOpcode() != ISD::AND) return false; 2040 2041 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2042 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2043} 2044 2045LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2046CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2047 SDValue N, const SelectionDAGISel &SDISel) { 2048 int64_t Val = MatcherTable[MatcherIndex++]; 2049 if (Val & 128) 2050 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2051 2052 if (N->getOpcode() != ISD::OR) return false; 2053 2054 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2055 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2056} 2057 2058/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2059/// scope, evaluate the current node. If the current predicate is known to 2060/// fail, set Result=true and return anything. If the current predicate is 2061/// known to pass, set Result=false and return the MatcherIndex to continue 2062/// with. If the current predicate is unknown, set Result=false and return the 2063/// MatcherIndex to continue with. 2064static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2065 unsigned Index, SDValue N, 2066 bool &Result, 2067 const SelectionDAGISel &SDISel, 2068 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2069 switch (Table[Index++]) { 2070 default: 2071 Result = false; 2072 return Index-1; // Could not evaluate this predicate. 2073 case SelectionDAGISel::OPC_CheckSame: 2074 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2075 return Index; 2076 case SelectionDAGISel::OPC_CheckPatternPredicate: 2077 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2078 return Index; 2079 case SelectionDAGISel::OPC_CheckPredicate: 2080 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2081 return Index; 2082 case SelectionDAGISel::OPC_CheckOpcode: 2083 Result = !::CheckOpcode(Table, Index, N.getNode()); 2084 return Index; 2085 case SelectionDAGISel::OPC_CheckType: 2086 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2087 return Index; 2088 case SelectionDAGISel::OPC_CheckChild0Type: 2089 case SelectionDAGISel::OPC_CheckChild1Type: 2090 case SelectionDAGISel::OPC_CheckChild2Type: 2091 case SelectionDAGISel::OPC_CheckChild3Type: 2092 case SelectionDAGISel::OPC_CheckChild4Type: 2093 case SelectionDAGISel::OPC_CheckChild5Type: 2094 case SelectionDAGISel::OPC_CheckChild6Type: 2095 case SelectionDAGISel::OPC_CheckChild7Type: 2096 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2097 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2098 return Index; 2099 case SelectionDAGISel::OPC_CheckCondCode: 2100 Result = !::CheckCondCode(Table, Index, N); 2101 return Index; 2102 case SelectionDAGISel::OPC_CheckValueType: 2103 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2104 return Index; 2105 case SelectionDAGISel::OPC_CheckInteger: 2106 Result = !::CheckInteger(Table, Index, N); 2107 return Index; 2108 case SelectionDAGISel::OPC_CheckAndImm: 2109 Result = !::CheckAndImm(Table, Index, N, SDISel); 2110 return Index; 2111 case SelectionDAGISel::OPC_CheckOrImm: 2112 Result = !::CheckOrImm(Table, Index, N, SDISel); 2113 return Index; 2114 } 2115} 2116 2117namespace { 2118 2119struct MatchScope { 2120 /// FailIndex - If this match fails, this is the index to continue with. 2121 unsigned FailIndex; 2122 2123 /// NodeStack - The node stack when the scope was formed. 2124 SmallVector<SDValue, 4> NodeStack; 2125 2126 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2127 unsigned NumRecordedNodes; 2128 2129 /// NumMatchedMemRefs - The number of matched memref entries. 2130 unsigned NumMatchedMemRefs; 2131 2132 /// InputChain/InputGlue - The current chain/glue 2133 SDValue InputChain, InputGlue; 2134 2135 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2136 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2137}; 2138 2139} 2140 2141SDNode *SelectionDAGISel:: 2142SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2143 unsigned TableSize) { 2144 // FIXME: Should these even be selected? Handle these cases in the caller? 2145 switch (NodeToMatch->getOpcode()) { 2146 default: 2147 break; 2148 case ISD::EntryToken: // These nodes remain the same. 2149 case ISD::BasicBlock: 2150 case ISD::Register: 2151 case ISD::RegisterMask: 2152 //case ISD::VALUETYPE: 2153 //case ISD::CONDCODE: 2154 case ISD::HANDLENODE: 2155 case ISD::MDNODE_SDNODE: 2156 case ISD::TargetConstant: 2157 case ISD::TargetConstantFP: 2158 case ISD::TargetConstantPool: 2159 case ISD::TargetFrameIndex: 2160 case ISD::TargetExternalSymbol: 2161 case ISD::TargetBlockAddress: 2162 case ISD::TargetJumpTable: 2163 case ISD::TargetGlobalTLSAddress: 2164 case ISD::TargetGlobalAddress: 2165 case ISD::TokenFactor: 2166 case ISD::CopyFromReg: 2167 case ISD::CopyToReg: 2168 case ISD::EH_LABEL: 2169 case ISD::LIFETIME_START: 2170 case ISD::LIFETIME_END: 2171 NodeToMatch->setNodeId(-1); // Mark selected. 2172 return 0; 2173 case ISD::AssertSext: 2174 case ISD::AssertZext: 2175 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2176 NodeToMatch->getOperand(0)); 2177 return 0; 2178 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2179 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2180 } 2181 2182 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2183 2184 // Set up the node stack with NodeToMatch as the only node on the stack. 2185 SmallVector<SDValue, 8> NodeStack; 2186 SDValue N = SDValue(NodeToMatch, 0); 2187 NodeStack.push_back(N); 2188 2189 // MatchScopes - Scopes used when matching, if a match failure happens, this 2190 // indicates where to continue checking. 2191 SmallVector<MatchScope, 8> MatchScopes; 2192 2193 // RecordedNodes - This is the set of nodes that have been recorded by the 2194 // state machine. The second value is the parent of the node, or null if the 2195 // root is recorded. 2196 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2197 2198 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2199 // pattern. 2200 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2201 2202 // These are the current input chain and glue for use when generating nodes. 2203 // Various Emit operations change these. For example, emitting a copytoreg 2204 // uses and updates these. 2205 SDValue InputChain, InputGlue; 2206 2207 // ChainNodesMatched - If a pattern matches nodes that have input/output 2208 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2209 // which ones they are. The result is captured into this list so that we can 2210 // update the chain results when the pattern is complete. 2211 SmallVector<SDNode*, 3> ChainNodesMatched; 2212 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2213 2214 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2215 NodeToMatch->dump(CurDAG); 2216 dbgs() << '\n'); 2217 2218 // Determine where to start the interpreter. Normally we start at opcode #0, 2219 // but if the state machine starts with an OPC_SwitchOpcode, then we 2220 // accelerate the first lookup (which is guaranteed to be hot) with the 2221 // OpcodeOffset table. 2222 unsigned MatcherIndex = 0; 2223 2224 if (!OpcodeOffset.empty()) { 2225 // Already computed the OpcodeOffset table, just index into it. 2226 if (N.getOpcode() < OpcodeOffset.size()) 2227 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2228 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2229 2230 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2231 // Otherwise, the table isn't computed, but the state machine does start 2232 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2233 // is the first time we're selecting an instruction. 2234 unsigned Idx = 1; 2235 while (1) { 2236 // Get the size of this case. 2237 unsigned CaseSize = MatcherTable[Idx++]; 2238 if (CaseSize & 128) 2239 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2240 if (CaseSize == 0) break; 2241 2242 // Get the opcode, add the index to the table. 2243 uint16_t Opc = MatcherTable[Idx++]; 2244 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2245 if (Opc >= OpcodeOffset.size()) 2246 OpcodeOffset.resize((Opc+1)*2); 2247 OpcodeOffset[Opc] = Idx; 2248 Idx += CaseSize; 2249 } 2250 2251 // Okay, do the lookup for the first opcode. 2252 if (N.getOpcode() < OpcodeOffset.size()) 2253 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2254 } 2255 2256 while (1) { 2257 assert(MatcherIndex < TableSize && "Invalid index"); 2258#ifndef NDEBUG 2259 unsigned CurrentOpcodeIndex = MatcherIndex; 2260#endif 2261 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2262 switch (Opcode) { 2263 case OPC_Scope: { 2264 // Okay, the semantics of this operation are that we should push a scope 2265 // then evaluate the first child. However, pushing a scope only to have 2266 // the first check fail (which then pops it) is inefficient. If we can 2267 // determine immediately that the first check (or first several) will 2268 // immediately fail, don't even bother pushing a scope for them. 2269 unsigned FailIndex; 2270 2271 while (1) { 2272 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2273 if (NumToSkip & 128) 2274 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2275 // Found the end of the scope with no match. 2276 if (NumToSkip == 0) { 2277 FailIndex = 0; 2278 break; 2279 } 2280 2281 FailIndex = MatcherIndex+NumToSkip; 2282 2283 unsigned MatcherIndexOfPredicate = MatcherIndex; 2284 (void)MatcherIndexOfPredicate; // silence warning. 2285 2286 // If we can't evaluate this predicate without pushing a scope (e.g. if 2287 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2288 // push the scope and evaluate the full predicate chain. 2289 bool Result; 2290 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2291 Result, *this, RecordedNodes); 2292 if (!Result) 2293 break; 2294 2295 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2296 << "index " << MatcherIndexOfPredicate 2297 << ", continuing at " << FailIndex << "\n"); 2298 ++NumDAGIselRetries; 2299 2300 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2301 // move to the next case. 2302 MatcherIndex = FailIndex; 2303 } 2304 2305 // If the whole scope failed to match, bail. 2306 if (FailIndex == 0) break; 2307 2308 // Push a MatchScope which indicates where to go if the first child fails 2309 // to match. 2310 MatchScope NewEntry; 2311 NewEntry.FailIndex = FailIndex; 2312 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2313 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2314 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2315 NewEntry.InputChain = InputChain; 2316 NewEntry.InputGlue = InputGlue; 2317 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2318 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2319 MatchScopes.push_back(NewEntry); 2320 continue; 2321 } 2322 case OPC_RecordNode: { 2323 // Remember this node, it may end up being an operand in the pattern. 2324 SDNode *Parent = 0; 2325 if (NodeStack.size() > 1) 2326 Parent = NodeStack[NodeStack.size()-2].getNode(); 2327 RecordedNodes.push_back(std::make_pair(N, Parent)); 2328 continue; 2329 } 2330 2331 case OPC_RecordChild0: case OPC_RecordChild1: 2332 case OPC_RecordChild2: case OPC_RecordChild3: 2333 case OPC_RecordChild4: case OPC_RecordChild5: 2334 case OPC_RecordChild6: case OPC_RecordChild7: { 2335 unsigned ChildNo = Opcode-OPC_RecordChild0; 2336 if (ChildNo >= N.getNumOperands()) 2337 break; // Match fails if out of range child #. 2338 2339 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2340 N.getNode())); 2341 continue; 2342 } 2343 case OPC_RecordMemRef: 2344 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2345 continue; 2346 2347 case OPC_CaptureGlueInput: 2348 // If the current node has an input glue, capture it in InputGlue. 2349 if (N->getNumOperands() != 0 && 2350 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2351 InputGlue = N->getOperand(N->getNumOperands()-1); 2352 continue; 2353 2354 case OPC_MoveChild: { 2355 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2356 if (ChildNo >= N.getNumOperands()) 2357 break; // Match fails if out of range child #. 2358 N = N.getOperand(ChildNo); 2359 NodeStack.push_back(N); 2360 continue; 2361 } 2362 2363 case OPC_MoveParent: 2364 // Pop the current node off the NodeStack. 2365 NodeStack.pop_back(); 2366 assert(!NodeStack.empty() && "Node stack imbalance!"); 2367 N = NodeStack.back(); 2368 continue; 2369 2370 case OPC_CheckSame: 2371 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2372 continue; 2373 case OPC_CheckPatternPredicate: 2374 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2375 continue; 2376 case OPC_CheckPredicate: 2377 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2378 N.getNode())) 2379 break; 2380 continue; 2381 case OPC_CheckComplexPat: { 2382 unsigned CPNum = MatcherTable[MatcherIndex++]; 2383 unsigned RecNo = MatcherTable[MatcherIndex++]; 2384 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2385 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2386 RecordedNodes[RecNo].first, CPNum, 2387 RecordedNodes)) 2388 break; 2389 continue; 2390 } 2391 case OPC_CheckOpcode: 2392 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2393 continue; 2394 2395 case OPC_CheckType: 2396 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2397 break; 2398 continue; 2399 2400 case OPC_SwitchOpcode: { 2401 unsigned CurNodeOpcode = N.getOpcode(); 2402 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2403 unsigned CaseSize; 2404 while (1) { 2405 // Get the size of this case. 2406 CaseSize = MatcherTable[MatcherIndex++]; 2407 if (CaseSize & 128) 2408 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2409 if (CaseSize == 0) break; 2410 2411 uint16_t Opc = MatcherTable[MatcherIndex++]; 2412 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2413 2414 // If the opcode matches, then we will execute this case. 2415 if (CurNodeOpcode == Opc) 2416 break; 2417 2418 // Otherwise, skip over this case. 2419 MatcherIndex += CaseSize; 2420 } 2421 2422 // If no cases matched, bail out. 2423 if (CaseSize == 0) break; 2424 2425 // Otherwise, execute the case we found. 2426 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2427 << " to " << MatcherIndex << "\n"); 2428 continue; 2429 } 2430 2431 case OPC_SwitchType: { 2432 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2433 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2434 unsigned CaseSize; 2435 while (1) { 2436 // Get the size of this case. 2437 CaseSize = MatcherTable[MatcherIndex++]; 2438 if (CaseSize & 128) 2439 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2440 if (CaseSize == 0) break; 2441 2442 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2443 if (CaseVT == MVT::iPTR) 2444 CaseVT = getTargetLowering()->getPointerTy(); 2445 2446 // If the VT matches, then we will execute this case. 2447 if (CurNodeVT == CaseVT) 2448 break; 2449 2450 // Otherwise, skip over this case. 2451 MatcherIndex += CaseSize; 2452 } 2453 2454 // If no cases matched, bail out. 2455 if (CaseSize == 0) break; 2456 2457 // Otherwise, execute the case we found. 2458 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2459 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2460 continue; 2461 } 2462 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2463 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2464 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2465 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2466 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2467 Opcode-OPC_CheckChild0Type)) 2468 break; 2469 continue; 2470 case OPC_CheckCondCode: 2471 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2472 continue; 2473 case OPC_CheckValueType: 2474 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2475 break; 2476 continue; 2477 case OPC_CheckInteger: 2478 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2479 continue; 2480 case OPC_CheckAndImm: 2481 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2482 continue; 2483 case OPC_CheckOrImm: 2484 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2485 continue; 2486 2487 case OPC_CheckFoldableChainNode: { 2488 assert(NodeStack.size() != 1 && "No parent node"); 2489 // Verify that all intermediate nodes between the root and this one have 2490 // a single use. 2491 bool HasMultipleUses = false; 2492 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2493 if (!NodeStack[i].hasOneUse()) { 2494 HasMultipleUses = true; 2495 break; 2496 } 2497 if (HasMultipleUses) break; 2498 2499 // Check to see that the target thinks this is profitable to fold and that 2500 // we can fold it without inducing cycles in the graph. 2501 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2502 NodeToMatch) || 2503 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2504 NodeToMatch, OptLevel, 2505 true/*We validate our own chains*/)) 2506 break; 2507 2508 continue; 2509 } 2510 case OPC_EmitInteger: { 2511 MVT::SimpleValueType VT = 2512 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2513 int64_t Val = MatcherTable[MatcherIndex++]; 2514 if (Val & 128) 2515 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2516 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2517 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2518 continue; 2519 } 2520 case OPC_EmitRegister: { 2521 MVT::SimpleValueType VT = 2522 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2523 unsigned RegNo = MatcherTable[MatcherIndex++]; 2524 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2525 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2526 continue; 2527 } 2528 case OPC_EmitRegister2: { 2529 // For targets w/ more than 256 register names, the register enum 2530 // values are stored in two bytes in the matcher table (just like 2531 // opcodes). 2532 MVT::SimpleValueType VT = 2533 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2534 unsigned RegNo = MatcherTable[MatcherIndex++]; 2535 RegNo |= MatcherTable[MatcherIndex++] << 8; 2536 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2537 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2538 continue; 2539 } 2540 2541 case OPC_EmitConvertToTarget: { 2542 // Convert from IMM/FPIMM to target version. 2543 unsigned RecNo = MatcherTable[MatcherIndex++]; 2544 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2545 SDValue Imm = RecordedNodes[RecNo].first; 2546 2547 if (Imm->getOpcode() == ISD::Constant) { 2548 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2549 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2550 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2551 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2552 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2553 } 2554 2555 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2556 continue; 2557 } 2558 2559 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2560 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2561 // These are space-optimized forms of OPC_EmitMergeInputChains. 2562 assert(InputChain.getNode() == 0 && 2563 "EmitMergeInputChains should be the first chain producing node"); 2564 assert(ChainNodesMatched.empty() && 2565 "Should only have one EmitMergeInputChains per match"); 2566 2567 // Read all of the chained nodes. 2568 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2569 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2570 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2571 2572 // FIXME: What if other value results of the node have uses not matched 2573 // by this pattern? 2574 if (ChainNodesMatched.back() != NodeToMatch && 2575 !RecordedNodes[RecNo].first.hasOneUse()) { 2576 ChainNodesMatched.clear(); 2577 break; 2578 } 2579 2580 // Merge the input chains if they are not intra-pattern references. 2581 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2582 2583 if (InputChain.getNode() == 0) 2584 break; // Failed to merge. 2585 continue; 2586 } 2587 2588 case OPC_EmitMergeInputChains: { 2589 assert(InputChain.getNode() == 0 && 2590 "EmitMergeInputChains should be the first chain producing node"); 2591 // This node gets a list of nodes we matched in the input that have 2592 // chains. We want to token factor all of the input chains to these nodes 2593 // together. However, if any of the input chains is actually one of the 2594 // nodes matched in this pattern, then we have an intra-match reference. 2595 // Ignore these because the newly token factored chain should not refer to 2596 // the old nodes. 2597 unsigned NumChains = MatcherTable[MatcherIndex++]; 2598 assert(NumChains != 0 && "Can't TF zero chains"); 2599 2600 assert(ChainNodesMatched.empty() && 2601 "Should only have one EmitMergeInputChains per match"); 2602 2603 // Read all of the chained nodes. 2604 for (unsigned i = 0; i != NumChains; ++i) { 2605 unsigned RecNo = MatcherTable[MatcherIndex++]; 2606 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2607 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2608 2609 // FIXME: What if other value results of the node have uses not matched 2610 // by this pattern? 2611 if (ChainNodesMatched.back() != NodeToMatch && 2612 !RecordedNodes[RecNo].first.hasOneUse()) { 2613 ChainNodesMatched.clear(); 2614 break; 2615 } 2616 } 2617 2618 // If the inner loop broke out, the match fails. 2619 if (ChainNodesMatched.empty()) 2620 break; 2621 2622 // Merge the input chains if they are not intra-pattern references. 2623 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2624 2625 if (InputChain.getNode() == 0) 2626 break; // Failed to merge. 2627 2628 continue; 2629 } 2630 2631 case OPC_EmitCopyToReg: { 2632 unsigned RecNo = MatcherTable[MatcherIndex++]; 2633 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2634 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2635 2636 if (InputChain.getNode() == 0) 2637 InputChain = CurDAG->getEntryNode(); 2638 2639 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2640 DestPhysReg, RecordedNodes[RecNo].first, 2641 InputGlue); 2642 2643 InputGlue = InputChain.getValue(1); 2644 continue; 2645 } 2646 2647 case OPC_EmitNodeXForm: { 2648 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2649 unsigned RecNo = MatcherTable[MatcherIndex++]; 2650 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2651 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2652 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2653 continue; 2654 } 2655 2656 case OPC_EmitNode: 2657 case OPC_MorphNodeTo: { 2658 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2659 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2660 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2661 // Get the result VT list. 2662 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2663 SmallVector<EVT, 4> VTs; 2664 for (unsigned i = 0; i != NumVTs; ++i) { 2665 MVT::SimpleValueType VT = 2666 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2667 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2668 VTs.push_back(VT); 2669 } 2670 2671 if (EmitNodeInfo & OPFL_Chain) 2672 VTs.push_back(MVT::Other); 2673 if (EmitNodeInfo & OPFL_GlueOutput) 2674 VTs.push_back(MVT::Glue); 2675 2676 // This is hot code, so optimize the two most common cases of 1 and 2 2677 // results. 2678 SDVTList VTList; 2679 if (VTs.size() == 1) 2680 VTList = CurDAG->getVTList(VTs[0]); 2681 else if (VTs.size() == 2) 2682 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2683 else 2684 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2685 2686 // Get the operand list. 2687 unsigned NumOps = MatcherTable[MatcherIndex++]; 2688 SmallVector<SDValue, 8> Ops; 2689 for (unsigned i = 0; i != NumOps; ++i) { 2690 unsigned RecNo = MatcherTable[MatcherIndex++]; 2691 if (RecNo & 128) 2692 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2693 2694 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2695 Ops.push_back(RecordedNodes[RecNo].first); 2696 } 2697 2698 // If there are variadic operands to add, handle them now. 2699 if (EmitNodeInfo & OPFL_VariadicInfo) { 2700 // Determine the start index to copy from. 2701 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2702 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2703 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2704 "Invalid variadic node"); 2705 // Copy all of the variadic operands, not including a potential glue 2706 // input. 2707 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2708 i != e; ++i) { 2709 SDValue V = NodeToMatch->getOperand(i); 2710 if (V.getValueType() == MVT::Glue) break; 2711 Ops.push_back(V); 2712 } 2713 } 2714 2715 // If this has chain/glue inputs, add them. 2716 if (EmitNodeInfo & OPFL_Chain) 2717 Ops.push_back(InputChain); 2718 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2719 Ops.push_back(InputGlue); 2720 2721 // Create the node. 2722 SDNode *Res = 0; 2723 if (Opcode != OPC_MorphNodeTo) { 2724 // If this is a normal EmitNode command, just create the new node and 2725 // add the results to the RecordedNodes list. 2726 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2727 VTList, Ops); 2728 2729 // Add all the non-glue/non-chain results to the RecordedNodes list. 2730 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2731 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2732 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2733 (SDNode*) 0)); 2734 } 2735 2736 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2737 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2738 EmitNodeInfo); 2739 } else { 2740 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2741 // We will visit the equivalent node later. 2742 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2743 return 0; 2744 } 2745 2746 // If the node had chain/glue results, update our notion of the current 2747 // chain and glue. 2748 if (EmitNodeInfo & OPFL_GlueOutput) { 2749 InputGlue = SDValue(Res, VTs.size()-1); 2750 if (EmitNodeInfo & OPFL_Chain) 2751 InputChain = SDValue(Res, VTs.size()-2); 2752 } else if (EmitNodeInfo & OPFL_Chain) 2753 InputChain = SDValue(Res, VTs.size()-1); 2754 2755 // If the OPFL_MemRefs glue is set on this node, slap all of the 2756 // accumulated memrefs onto it. 2757 // 2758 // FIXME: This is vastly incorrect for patterns with multiple outputs 2759 // instructions that access memory and for ComplexPatterns that match 2760 // loads. 2761 if (EmitNodeInfo & OPFL_MemRefs) { 2762 // Only attach load or store memory operands if the generated 2763 // instruction may load or store. 2764 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2765 bool mayLoad = MCID.mayLoad(); 2766 bool mayStore = MCID.mayStore(); 2767 2768 unsigned NumMemRefs = 0; 2769 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2770 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2771 if ((*I)->isLoad()) { 2772 if (mayLoad) 2773 ++NumMemRefs; 2774 } else if ((*I)->isStore()) { 2775 if (mayStore) 2776 ++NumMemRefs; 2777 } else { 2778 ++NumMemRefs; 2779 } 2780 } 2781 2782 MachineSDNode::mmo_iterator MemRefs = 2783 MF->allocateMemRefsArray(NumMemRefs); 2784 2785 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2786 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2787 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2788 if ((*I)->isLoad()) { 2789 if (mayLoad) 2790 *MemRefsPos++ = *I; 2791 } else if ((*I)->isStore()) { 2792 if (mayStore) 2793 *MemRefsPos++ = *I; 2794 } else { 2795 *MemRefsPos++ = *I; 2796 } 2797 } 2798 2799 cast<MachineSDNode>(Res) 2800 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2801 } 2802 2803 DEBUG(dbgs() << " " 2804 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2805 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 2806 2807 // If this was a MorphNodeTo then we're completely done! 2808 if (Opcode == OPC_MorphNodeTo) { 2809 // Update chain and glue uses. 2810 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2811 InputGlue, GlueResultNodesMatched, true); 2812 return Res; 2813 } 2814 2815 continue; 2816 } 2817 2818 case OPC_MarkGlueResults: { 2819 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2820 2821 // Read and remember all the glue-result nodes. 2822 for (unsigned i = 0; i != NumNodes; ++i) { 2823 unsigned RecNo = MatcherTable[MatcherIndex++]; 2824 if (RecNo & 128) 2825 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2826 2827 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2828 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2829 } 2830 continue; 2831 } 2832 2833 case OPC_CompleteMatch: { 2834 // The match has been completed, and any new nodes (if any) have been 2835 // created. Patch up references to the matched dag to use the newly 2836 // created nodes. 2837 unsigned NumResults = MatcherTable[MatcherIndex++]; 2838 2839 for (unsigned i = 0; i != NumResults; ++i) { 2840 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2841 if (ResSlot & 128) 2842 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2843 2844 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2845 SDValue Res = RecordedNodes[ResSlot].first; 2846 2847 assert(i < NodeToMatch->getNumValues() && 2848 NodeToMatch->getValueType(i) != MVT::Other && 2849 NodeToMatch->getValueType(i) != MVT::Glue && 2850 "Invalid number of results to complete!"); 2851 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2852 NodeToMatch->getValueType(i) == MVT::iPTR || 2853 Res.getValueType() == MVT::iPTR || 2854 NodeToMatch->getValueType(i).getSizeInBits() == 2855 Res.getValueType().getSizeInBits()) && 2856 "invalid replacement"); 2857 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2858 } 2859 2860 // If the root node defines glue, add it to the glue nodes to update list. 2861 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2862 GlueResultNodesMatched.push_back(NodeToMatch); 2863 2864 // Update chain and glue uses. 2865 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2866 InputGlue, GlueResultNodesMatched, false); 2867 2868 assert(NodeToMatch->use_empty() && 2869 "Didn't replace all uses of the node?"); 2870 2871 // FIXME: We just return here, which interacts correctly with SelectRoot 2872 // above. We should fix this to not return an SDNode* anymore. 2873 return 0; 2874 } 2875 } 2876 2877 // If the code reached this point, then the match failed. See if there is 2878 // another child to try in the current 'Scope', otherwise pop it until we 2879 // find a case to check. 2880 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2881 ++NumDAGIselRetries; 2882 while (1) { 2883 if (MatchScopes.empty()) { 2884 CannotYetSelect(NodeToMatch); 2885 return 0; 2886 } 2887 2888 // Restore the interpreter state back to the point where the scope was 2889 // formed. 2890 MatchScope &LastScope = MatchScopes.back(); 2891 RecordedNodes.resize(LastScope.NumRecordedNodes); 2892 NodeStack.clear(); 2893 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2894 N = NodeStack.back(); 2895 2896 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2897 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2898 MatcherIndex = LastScope.FailIndex; 2899 2900 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 2901 2902 InputChain = LastScope.InputChain; 2903 InputGlue = LastScope.InputGlue; 2904 if (!LastScope.HasChainNodesMatched) 2905 ChainNodesMatched.clear(); 2906 if (!LastScope.HasGlueResultNodesMatched) 2907 GlueResultNodesMatched.clear(); 2908 2909 // Check to see what the offset is at the new MatcherIndex. If it is zero 2910 // we have reached the end of this scope, otherwise we have another child 2911 // in the current scope to try. 2912 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2913 if (NumToSkip & 128) 2914 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2915 2916 // If we have another child in this scope to match, update FailIndex and 2917 // try it. 2918 if (NumToSkip != 0) { 2919 LastScope.FailIndex = MatcherIndex+NumToSkip; 2920 break; 2921 } 2922 2923 // End of this scope, pop it and try the next child in the containing 2924 // scope. 2925 MatchScopes.pop_back(); 2926 } 2927 } 2928} 2929 2930 2931 2932void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2933 std::string msg; 2934 raw_string_ostream Msg(msg); 2935 Msg << "Cannot select: "; 2936 2937 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2938 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2939 N->getOpcode() != ISD::INTRINSIC_VOID) { 2940 N->printrFull(Msg, CurDAG); 2941 Msg << "\nIn function: " << MF->getName(); 2942 } else { 2943 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2944 unsigned iid = 2945 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2946 if (iid < Intrinsic::num_intrinsics) 2947 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2948 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2949 Msg << "target intrinsic %" << TII->getName(iid); 2950 else 2951 Msg << "unknown intrinsic #" << iid; 2952 } 2953 report_fatal_error(Msg.str()); 2954} 2955 2956char SelectionDAGISel::ID = 0; 2957