SelectionDAGISel.cpp revision 91aac1015e6714d959801dd8d60f55a72827dc4d
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/ScheduleDAG.h" 39#include "llvm/CodeGen/SchedulerRegistry.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetData.h" 43#include "llvm/Target/TargetFrameInfo.h" 44#include "llvm/Target/TargetInstrInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/Timer.h" 52#include <algorithm> 53using namespace llvm; 54 55static cl::opt<bool> 56EnableValueProp("enable-value-prop", cl::Hidden); 57static cl::opt<bool> 58EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 59static cl::opt<bool> 60EnableFastISel("fast-isel", cl::Hidden, 61 cl::desc("Enable the experimental \"fast\" instruction selector")); 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the experimental \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewISelDAGs("view-isel-dags", cl::Hidden, 91 cl::desc("Pop up a window to show isel dags as they are selected")); 92static cl::opt<bool> 93ViewSchedDAGs("view-sched-dags", cl::Hidden, 94 cl::desc("Pop up a window to show sched dags as they are processed")); 95static cl::opt<bool> 96ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 97 cl::desc("Pop up a window to show SUnit dags after they are processed")); 98#else 99static const bool ViewDAGCombine1 = false, 100 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 101 ViewDAGCombine2 = false, 102 ViewISelDAGs = false, ViewSchedDAGs = false, 103 ViewSUnitDAGs = false; 104#endif 105 106//===---------------------------------------------------------------------===// 107/// 108/// RegisterScheduler class - Track the registration of instruction schedulers. 109/// 110//===---------------------------------------------------------------------===// 111MachinePassRegistry RegisterScheduler::Registry; 112 113//===---------------------------------------------------------------------===// 114/// 115/// ISHeuristic command line option for instruction schedulers. 116/// 117//===---------------------------------------------------------------------===// 118static cl::opt<RegisterScheduler::FunctionPassCtor, false, 119 RegisterPassParser<RegisterScheduler> > 120ISHeuristic("pre-RA-sched", 121 cl::init(&createDefaultScheduler), 122 cl::desc("Instruction schedulers available (before register" 123 " allocation):")); 124 125static RegisterScheduler 126defaultListDAGScheduler("default", " Best scheduler for the target", 127 createDefaultScheduler); 128 129namespace llvm { 130 //===--------------------------------------------------------------------===// 131 /// createDefaultScheduler - This creates an instruction scheduler appropriate 132 /// for the target. 133 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 134 SelectionDAG *DAG, 135 MachineBasicBlock *BB, 136 bool Fast) { 137 TargetLowering &TLI = IS->getTargetLowering(); 138 139 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 140 return createTDListDAGScheduler(IS, DAG, BB, Fast); 141 } else { 142 assert(TLI.getSchedulingPreference() == 143 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 144 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 145 } 146 } 147} 148 149// EmitInstrWithCustomInserter - This method should be implemented by targets 150// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 151// instructions are special in various ways, which require special support to 152// insert. The specified MachineInstr is created but not inserted into any 153// basic blocks, and the scheduler passes ownership of it to this method. 154MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 155 MachineBasicBlock *MBB) { 156 cerr << "If a target marks an instruction with " 157 << "'usesCustomDAGSchedInserter', it must implement " 158 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 159 abort(); 160 return 0; 161} 162 163/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 164/// physical register has only a single copy use, then coalesced the copy 165/// if possible. 166static void EmitLiveInCopy(MachineBasicBlock *MBB, 167 MachineBasicBlock::iterator &InsertPos, 168 unsigned VirtReg, unsigned PhysReg, 169 const TargetRegisterClass *RC, 170 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 171 const MachineRegisterInfo &MRI, 172 const TargetRegisterInfo &TRI, 173 const TargetInstrInfo &TII) { 174 unsigned NumUses = 0; 175 MachineInstr *UseMI = NULL; 176 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 177 UE = MRI.use_end(); UI != UE; ++UI) { 178 UseMI = &*UI; 179 if (++NumUses > 1) 180 break; 181 } 182 183 // If the number of uses is not one, or the use is not a move instruction, 184 // don't coalesce. Also, only coalesce away a virtual register to virtual 185 // register copy. 186 bool Coalesced = false; 187 unsigned SrcReg, DstReg; 188 if (NumUses == 1 && 189 TII.isMoveInstr(*UseMI, SrcReg, DstReg) && 190 TargetRegisterInfo::isVirtualRegister(DstReg)) { 191 VirtReg = DstReg; 192 Coalesced = true; 193 } 194 195 // Now find an ideal location to insert the copy. 196 MachineBasicBlock::iterator Pos = InsertPos; 197 while (Pos != MBB->begin()) { 198 MachineInstr *PrevMI = prior(Pos); 199 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 200 // copyRegToReg might emit multiple instructions to do a copy. 201 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 202 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 203 // This is what the BB looks like right now: 204 // r1024 = mov r0 205 // ... 206 // r1 = mov r1024 207 // 208 // We want to insert "r1025 = mov r1". Inserting this copy below the 209 // move to r1024 makes it impossible for that move to be coalesced. 210 // 211 // r1025 = mov r1 212 // r1024 = mov r0 213 // ... 214 // r1 = mov 1024 215 // r2 = mov 1025 216 break; // Woot! Found a good location. 217 --Pos; 218 } 219 220 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 221 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 222 if (Coalesced) { 223 if (&*InsertPos == UseMI) ++InsertPos; 224 MBB->erase(UseMI); 225 } 226} 227 228/// EmitLiveInCopies - If this is the first basic block in the function, 229/// and if it has live ins that need to be copied into vregs, emit the 230/// copies into the block. 231static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 232 const MachineRegisterInfo &MRI, 233 const TargetRegisterInfo &TRI, 234 const TargetInstrInfo &TII) { 235 if (SchedLiveInCopies) { 236 // Emit the copies at a heuristically-determined location in the block. 237 DenseMap<MachineInstr*, unsigned> CopyRegMap; 238 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 239 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 240 E = MRI.livein_end(); LI != E; ++LI) 241 if (LI->second) { 242 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 243 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 244 RC, CopyRegMap, MRI, TRI, TII); 245 } 246 } else { 247 // Emit the copies into the top of the block. 248 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 249 E = MRI.livein_end(); LI != E; ++LI) 250 if (LI->second) { 251 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 252 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 253 LI->second, LI->first, RC, RC); 254 } 255 } 256} 257 258//===----------------------------------------------------------------------===// 259// SelectionDAGISel code 260//===----------------------------------------------------------------------===// 261 262SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) : 263 FunctionPass(&ID), TLI(tli), 264 FuncInfo(new FunctionLoweringInfo(TLI)), 265 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 266 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)), 267 GFI(), 268 Fast(fast), 269 DAGSize(0) 270{} 271 272SelectionDAGISel::~SelectionDAGISel() { 273 delete SDL; 274 delete CurDAG; 275 delete FuncInfo; 276} 277 278unsigned SelectionDAGISel::MakeReg(MVT VT) { 279 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 280} 281 282void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 283 AU.addRequired<AliasAnalysis>(); 284 AU.addRequired<GCModuleInfo>(); 285 AU.setPreservesAll(); 286} 287 288bool SelectionDAGISel::runOnFunction(Function &Fn) { 289 // Do some sanity-checking on the command-line options. 290 assert((!EnableFastISelVerbose || EnableFastISel) && 291 "-fast-isel-verbose requires -fast-isel"); 292 assert((!EnableFastISelAbort || EnableFastISel) && 293 "-fast-isel-abort requires -fast-isel"); 294 295 // Get alias analysis for load/store combining. 296 AA = &getAnalysis<AliasAnalysis>(); 297 298 TargetMachine &TM = TLI.getTargetMachine(); 299 MachineFunction &MF = MachineFunction::construct(&Fn, TM); 300 const MachineRegisterInfo &MRI = MF.getRegInfo(); 301 const TargetInstrInfo &TII = *TM.getInstrInfo(); 302 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 303 304 if (MF.getFunction()->hasGC()) 305 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction()); 306 else 307 GFI = 0; 308 RegInfo = &MF.getRegInfo(); 309 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 310 311 FuncInfo->set(Fn, MF, EnableFastISel); 312 CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>()); 313 SDL->init(GFI, *AA); 314 315 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 316 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 317 // Mark landing pad. 318 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 319 320 SelectAllBasicBlocks(Fn, MF); 321 322 // If the first basic block in the function has live ins that need to be 323 // copied into vregs, emit the copies into the top of the block before 324 // emitting the code for the block. 325 EmitLiveInCopies(MF.begin(), MRI, TRI, TII); 326 327 // Add function live-ins to entry block live-in set. 328 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 329 E = RegInfo->livein_end(); I != E; ++I) 330 MF.begin()->addLiveIn(I->first); 331 332#ifndef NDEBUG 333 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 334 "Not all catch info was assigned to a landing pad!"); 335#endif 336 337 FuncInfo->clear(); 338 339 return true; 340} 341 342static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 343 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 344 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 345 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 346 // Apply the catch info to DestBB. 347 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 348#ifndef NDEBUG 349 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 350 FLI.CatchInfoFound.insert(EHSel); 351#endif 352 } 353} 354 355/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 356/// whether object offset >= 0. 357static bool 358IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 359 if (!isa<FrameIndexSDNode>(Op)) return false; 360 361 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 362 int FrameIdx = FrameIdxNode->getIndex(); 363 return MFI->isFixedObjectIndex(FrameIdx) && 364 MFI->getObjectOffset(FrameIdx) >= 0; 365} 366 367/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 368/// possibly be overwritten when lowering the outgoing arguments in a tail 369/// call. Currently the implementation of this call is very conservative and 370/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 371/// virtual registers would be overwritten by direct lowering. 372static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 373 MachineFrameInfo * MFI) { 374 RegisterSDNode * OpReg = NULL; 375 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 376 (Op.getOpcode()== ISD::CopyFromReg && 377 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 378 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 379 (Op.getOpcode() == ISD::LOAD && 380 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 381 (Op.getOpcode() == ISD::MERGE_VALUES && 382 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD && 383 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()). 384 getOperand(1)))) 385 return true; 386 return false; 387} 388 389/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 390/// DAG and fixes their tailcall attribute operand. 391static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 392 TargetLowering& TLI) { 393 SDNode * Ret = NULL; 394 SDValue Terminator = DAG.getRoot(); 395 396 // Find RET node. 397 if (Terminator.getOpcode() == ISD::RET) { 398 Ret = Terminator.getNode(); 399 } 400 401 // Fix tail call attribute of CALL nodes. 402 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 403 BI = DAG.allnodes_end(); BI != BE; ) { 404 --BI; 405 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) { 406 SDValue OpRet(Ret, 0); 407 SDValue OpCall(BI, 0); 408 bool isMarkedTailCall = TheCall->isTailCall(); 409 // If CALL node has tail call attribute set to true and the call is not 410 // eligible (no RET or the target rejects) the attribute is fixed to 411 // false. The TargetLowering::IsEligibleForTailCallOptimization function 412 // must correctly identify tail call optimizable calls. 413 if (!isMarkedTailCall) continue; 414 if (Ret==NULL || 415 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) { 416 // Not eligible. Mark CALL node as non tail call. Note that we 417 // can modify the call node in place since calls are not CSE'd. 418 TheCall->setNotTailCall(); 419 } else { 420 // Look for tail call clobbered arguments. Emit a series of 421 // copyto/copyfrom virtual register nodes to protect them. 422 SmallVector<SDValue, 32> Ops; 423 SDValue Chain = TheCall->getChain(), InFlag; 424 Ops.push_back(Chain); 425 Ops.push_back(TheCall->getCallee()); 426 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 427 SDValue Arg = TheCall->getArg(i); 428 bool isByVal = TheCall->getArgFlags(i).isByVal(); 429 MachineFunction &MF = DAG.getMachineFunction(); 430 MachineFrameInfo *MFI = MF.getFrameInfo(); 431 if (!isByVal && 432 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 433 MVT VT = Arg.getValueType(); 434 unsigned VReg = MF.getRegInfo(). 435 createVirtualRegister(TLI.getRegClassFor(VT)); 436 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 437 InFlag = Chain.getValue(1); 438 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 439 Chain = Arg.getValue(1); 440 InFlag = Arg.getValue(2); 441 } 442 Ops.push_back(Arg); 443 Ops.push_back(TheCall->getArgFlagsVal(i)); 444 } 445 // Link in chain of CopyTo/CopyFromReg. 446 Ops[0] = Chain; 447 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 448 } 449 } 450 } 451} 452 453void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 454 BasicBlock::iterator Begin, 455 BasicBlock::iterator End) { 456 SDL->setCurrentBasicBlock(BB); 457 458 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo(); 459 460 if (MMI && BB->isLandingPad()) { 461 // Add a label to mark the beginning of the landing pad. Deletion of the 462 // landing pad can thus be detected via the MachineModuleInfo. 463 unsigned LabelID = MMI->addLandingPad(BB); 464 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL, 465 CurDAG->getEntryNode(), LabelID)); 466 467 // Mark exception register as live in. 468 unsigned Reg = TLI.getExceptionAddressRegister(); 469 if (Reg) BB->addLiveIn(Reg); 470 471 // Mark exception selector register as live in. 472 Reg = TLI.getExceptionSelectorRegister(); 473 if (Reg) BB->addLiveIn(Reg); 474 475 // FIXME: Hack around an exception handling flaw (PR1508): the personality 476 // function and list of typeids logically belong to the invoke (or, if you 477 // like, the basic block containing the invoke), and need to be associated 478 // with it in the dwarf exception handling tables. Currently however the 479 // information is provided by an intrinsic (eh.selector) that can be moved 480 // to unexpected places by the optimizers: if the unwind edge is critical, 481 // then breaking it can result in the intrinsics being in the successor of 482 // the landing pad, not the landing pad itself. This results in exceptions 483 // not being caught because no typeids are associated with the invoke. 484 // This may not be the only way things can go wrong, but it is the only way 485 // we try to work around for the moment. 486 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 487 488 if (Br && Br->isUnconditional()) { // Critical edge? 489 BasicBlock::iterator I, E; 490 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 491 if (isa<EHSelectorInst>(I)) 492 break; 493 494 if (I == E) 495 // No catch info found - try to extract some from the successor. 496 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 497 } 498 } 499 500 // Lower all of the non-terminator instructions. 501 for (BasicBlock::iterator I = Begin; I != End; ++I) 502 if (!isa<TerminatorInst>(I)) 503 SDL->visit(*I); 504 505 // Ensure that all instructions which are used outside of their defining 506 // blocks are available as virtual registers. Invoke is handled elsewhere. 507 for (BasicBlock::iterator I = Begin; I != End; ++I) 508 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 509 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I); 510 if (VMI != FuncInfo->ValueMap.end()) 511 SDL->CopyValueToVirtualRegister(I, VMI->second); 512 } 513 514 // Handle PHI nodes in successor blocks. 515 if (End == LLVMBB->end()) { 516 HandlePHINodesInSuccessorBlocks(LLVMBB); 517 518 // Lower the terminator after the copies are emitted. 519 SDL->visit(*LLVMBB->getTerminator()); 520 } 521 522 // Make sure the root of the DAG is up-to-date. 523 CurDAG->setRoot(SDL->getControlRoot()); 524 525 // Check whether calls in this block are real tail calls. Fix up CALL nodes 526 // with correct tailcall attribute so that the target can rely on the tailcall 527 // attribute indicating whether the call is really eligible for tail call 528 // optimization. 529 if (PerformTailCallOpt) 530 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI); 531 532 // Final step, emit the lowered DAG as machine code. 533 CodeGenAndEmitDAG(); 534 SDL->clear(); 535} 536 537void SelectionDAGISel::ComputeLiveOutVRegInfo() { 538 SmallPtrSet<SDNode*, 128> VisitedNodes; 539 SmallVector<SDNode*, 128> Worklist; 540 541 Worklist.push_back(CurDAG->getRoot().getNode()); 542 543 APInt Mask; 544 APInt KnownZero; 545 APInt KnownOne; 546 547 while (!Worklist.empty()) { 548 SDNode *N = Worklist.back(); 549 Worklist.pop_back(); 550 551 // If we've already seen this node, ignore it. 552 if (!VisitedNodes.insert(N)) 553 continue; 554 555 // Otherwise, add all chain operands to the worklist. 556 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 557 if (N->getOperand(i).getValueType() == MVT::Other) 558 Worklist.push_back(N->getOperand(i).getNode()); 559 560 // If this is a CopyToReg with a vreg dest, process it. 561 if (N->getOpcode() != ISD::CopyToReg) 562 continue; 563 564 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 565 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 566 continue; 567 568 // Ignore non-scalar or non-integer values. 569 SDValue Src = N->getOperand(2); 570 MVT SrcVT = Src.getValueType(); 571 if (!SrcVT.isInteger() || SrcVT.isVector()) 572 continue; 573 574 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 575 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 576 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 577 578 // Only install this information if it tells us something. 579 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 580 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 581 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo(); 582 if (DestReg >= FLI.LiveOutRegInfo.size()) 583 FLI.LiveOutRegInfo.resize(DestReg+1); 584 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 585 LOI.NumSignBits = NumSignBits; 586 LOI.KnownOne = NumSignBits; 587 LOI.KnownZero = NumSignBits; 588 } 589 } 590} 591 592void SelectionDAGISel::CodeGenAndEmitDAG() { 593 std::string GroupName; 594 if (TimePassesIsEnabled) 595 GroupName = "Instruction Selection and Scheduling"; 596 std::string BlockName; 597 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 598 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 599 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' + 600 BB->getBasicBlock()->getName(); 601 602 DOUT << "Initial selection DAG:\n"; 603 DEBUG(CurDAG->dump()); 604 605 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 606 607 // Run the DAG combiner in pre-legalize mode. 608 if (TimePassesIsEnabled) { 609 NamedRegionTimer T("DAG Combining 1", GroupName); 610 CurDAG->Combine(false, *AA, Fast); 611 } else { 612 CurDAG->Combine(false, *AA, Fast); 613 } 614 615 DOUT << "Optimized lowered selection DAG:\n"; 616 DEBUG(CurDAG->dump()); 617 618 // Second step, hack on the DAG until it only uses operations and types that 619 // the target supports. 620 if (EnableLegalizeTypes) {// Enable this some day. 621 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 622 BlockName); 623 624 if (TimePassesIsEnabled) { 625 NamedRegionTimer T("Type Legalization", GroupName); 626 CurDAG->LegalizeTypes(); 627 } else { 628 CurDAG->LegalizeTypes(); 629 } 630 631 DOUT << "Type-legalized selection DAG:\n"; 632 DEBUG(CurDAG->dump()); 633 634 // TODO: enable a dag combine pass here. 635 } 636 637 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 638 639 if (TimePassesIsEnabled) { 640 NamedRegionTimer T("DAG Legalization", GroupName); 641 CurDAG->Legalize(); 642 } else { 643 CurDAG->Legalize(); 644 } 645 646 DOUT << "Legalized selection DAG:\n"; 647 DEBUG(CurDAG->dump()); 648 649 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 650 651 // Run the DAG combiner in post-legalize mode. 652 if (TimePassesIsEnabled) { 653 NamedRegionTimer T("DAG Combining 2", GroupName); 654 CurDAG->Combine(true, *AA, Fast); 655 } else { 656 CurDAG->Combine(true, *AA, Fast); 657 } 658 659 DOUT << "Optimized legalized selection DAG:\n"; 660 DEBUG(CurDAG->dump()); 661 662 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 663 664 if (!Fast && EnableValueProp) 665 ComputeLiveOutVRegInfo(); 666 667 // Third, instruction select all of the operations to machine code, adding the 668 // code to the MachineBasicBlock. 669 if (TimePassesIsEnabled) { 670 NamedRegionTimer T("Instruction Selection", GroupName); 671 InstructionSelect(); 672 } else { 673 InstructionSelect(); 674 } 675 676 DOUT << "Selected selection DAG:\n"; 677 DEBUG(CurDAG->dump()); 678 679 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 680 681 // Schedule machine code. 682 ScheduleDAG *Scheduler; 683 if (TimePassesIsEnabled) { 684 NamedRegionTimer T("Instruction Scheduling", GroupName); 685 Scheduler = Schedule(); 686 } else { 687 Scheduler = Schedule(); 688 } 689 690 if (ViewSUnitDAGs) Scheduler->viewGraph(); 691 692 // Emit machine code to BB. This can change 'BB' to the last block being 693 // inserted into. 694 if (TimePassesIsEnabled) { 695 NamedRegionTimer T("Instruction Creation", GroupName); 696 BB = Scheduler->EmitSchedule(); 697 } else { 698 BB = Scheduler->EmitSchedule(); 699 } 700 701 // Free the scheduler state. 702 if (TimePassesIsEnabled) { 703 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 704 delete Scheduler; 705 } else { 706 delete Scheduler; 707 } 708 709 DOUT << "Selected machine code:\n"; 710 DEBUG(BB->dump()); 711} 712 713void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) { 714 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 715 BasicBlock *LLVMBB = &*I; 716 BB = FuncInfo->MBBMap[LLVMBB]; 717 718 BasicBlock::iterator const Begin = LLVMBB->begin(); 719 BasicBlock::iterator const End = LLVMBB->end(); 720 BasicBlock::iterator BI = Begin; 721 722 // Lower any arguments needed in this block if this is the entry block. 723 if (LLVMBB == &Fn.getEntryBlock()) 724 LowerArguments(LLVMBB); 725 726 // Before doing SelectionDAG ISel, see if FastISel has been requested. 727 // FastISel doesn't support EH landing pads, which require special handling. 728 if (EnableFastISel && !BB->isLandingPad()) { 729 if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, FuncInfo->ValueMap, 730 FuncInfo->MBBMap, 731 FuncInfo->StaticAllocaMap)) { 732 // Emit code for any incoming arguments. This must happen before 733 // beginning FastISel on the entry block. 734 if (LLVMBB == &Fn.getEntryBlock()) { 735 CurDAG->setRoot(SDL->getControlRoot()); 736 CodeGenAndEmitDAG(); 737 SDL->clear(); 738 } 739 F->setCurrentBlock(BB); 740 // Do FastISel on as many instructions as possible. 741 for (; BI != End; ++BI) { 742 // Just before the terminator instruction, insert instructions to 743 // feed PHI nodes in successor blocks. 744 if (isa<TerminatorInst>(BI)) 745 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, F)) { 746 if (EnableFastISelVerbose || EnableFastISelAbort) { 747 cerr << "FastISel miss: "; 748 BI->dump(); 749 } 750 if (EnableFastISelAbort) 751 assert(0 && "FastISel didn't handle a PHI in a successor"); 752 break; 753 } 754 755 // First try normal tablegen-generated "fast" selection. 756 if (F->SelectInstruction(BI)) 757 continue; 758 759 // Next, try calling the target to attempt to handle the instruction. 760 if (F->TargetSelectInstruction(BI)) 761 continue; 762 763 // Then handle certain instructions as single-LLVM-Instruction blocks. 764 if (isa<CallInst>(BI)) { 765 if (BI->getType() != Type::VoidTy) { 766 unsigned &R = FuncInfo->ValueMap[BI]; 767 if (!R) 768 R = FuncInfo->CreateRegForValue(BI); 769 } 770 771 SelectBasicBlock(LLVMBB, BI, next(BI)); 772 continue; 773 } 774 775 // Otherwise, give up on FastISel for the rest of the block. 776 // For now, be a little lenient about non-branch terminators. 777 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 778 if (EnableFastISelVerbose || EnableFastISelAbort) { 779 cerr << "FastISel miss: "; 780 BI->dump(); 781 } 782 if (EnableFastISelAbort) 783 // The "fast" selector couldn't handle something and bailed. 784 // For the purpose of debugging, just abort. 785 assert(0 && "FastISel didn't select the entire block"); 786 } 787 break; 788 } 789 delete F; 790 } 791 } 792 793 // Run SelectionDAG instruction selection on the remainder of the block 794 // not handled by FastISel. If FastISel is not run, this is the entire 795 // block. 796 if (BI != End) 797 SelectBasicBlock(LLVMBB, BI, End); 798 799 FinishBasicBlock(); 800 } 801} 802 803void 804SelectionDAGISel::FinishBasicBlock() { 805 806 // Perform target specific isel post processing. 807 InstructionSelectPostProcessing(); 808 809 DOUT << "Target-post-processed machine code:\n"; 810 DEBUG(BB->dump()); 811 812 DOUT << "Total amount of phi nodes to update: " 813 << SDL->PHINodesToUpdate.size() << "\n"; 814 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 815 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 816 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 817 818 // Next, now that we know what the last MBB the LLVM BB expanded is, update 819 // PHI nodes in successors. 820 if (SDL->SwitchCases.empty() && 821 SDL->JTCases.empty() && 822 SDL->BitTestCases.empty()) { 823 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 824 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 825 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 826 "This is not a machine PHI node that we are updating!"); 827 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 828 false)); 829 PHI->addOperand(MachineOperand::CreateMBB(BB)); 830 } 831 SDL->PHINodesToUpdate.clear(); 832 return; 833 } 834 835 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 836 // Lower header first, if it wasn't already lowered 837 if (!SDL->BitTestCases[i].Emitted) { 838 // Set the current basic block to the mbb we wish to insert the code into 839 BB = SDL->BitTestCases[i].Parent; 840 SDL->setCurrentBasicBlock(BB); 841 // Emit the code 842 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 843 CurDAG->setRoot(SDL->getRoot()); 844 CodeGenAndEmitDAG(); 845 SDL->clear(); 846 } 847 848 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 849 // Set the current basic block to the mbb we wish to insert the code into 850 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 851 SDL->setCurrentBasicBlock(BB); 852 // Emit the code 853 if (j+1 != ej) 854 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 855 SDL->BitTestCases[i].Reg, 856 SDL->BitTestCases[i].Cases[j]); 857 else 858 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 859 SDL->BitTestCases[i].Reg, 860 SDL->BitTestCases[i].Cases[j]); 861 862 863 CurDAG->setRoot(SDL->getRoot()); 864 CodeGenAndEmitDAG(); 865 SDL->clear(); 866 } 867 868 // Update PHI Nodes 869 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 870 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 871 MachineBasicBlock *PHIBB = PHI->getParent(); 872 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 873 "This is not a machine PHI node that we are updating!"); 874 // This is "default" BB. We have two jumps to it. From "header" BB and 875 // from last "case" BB. 876 if (PHIBB == SDL->BitTestCases[i].Default) { 877 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 878 false)); 879 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 880 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 881 false)); 882 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 883 back().ThisBB)); 884 } 885 // One of "cases" BB. 886 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 887 j != ej; ++j) { 888 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 889 if (cBB->succ_end() != 890 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 891 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 892 false)); 893 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 894 } 895 } 896 } 897 } 898 SDL->BitTestCases.clear(); 899 900 // If the JumpTable record is filled in, then we need to emit a jump table. 901 // Updating the PHI nodes is tricky in this case, since we need to determine 902 // whether the PHI is a successor of the range check MBB or the jump table MBB 903 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 904 // Lower header first, if it wasn't already lowered 905 if (!SDL->JTCases[i].first.Emitted) { 906 // Set the current basic block to the mbb we wish to insert the code into 907 BB = SDL->JTCases[i].first.HeaderBB; 908 SDL->setCurrentBasicBlock(BB); 909 // Emit the code 910 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 911 CurDAG->setRoot(SDL->getRoot()); 912 CodeGenAndEmitDAG(); 913 SDL->clear(); 914 } 915 916 // Set the current basic block to the mbb we wish to insert the code into 917 BB = SDL->JTCases[i].second.MBB; 918 SDL->setCurrentBasicBlock(BB); 919 // Emit the code 920 SDL->visitJumpTable(SDL->JTCases[i].second); 921 CurDAG->setRoot(SDL->getRoot()); 922 CodeGenAndEmitDAG(); 923 SDL->clear(); 924 925 // Update PHI Nodes 926 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 927 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 928 MachineBasicBlock *PHIBB = PHI->getParent(); 929 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 930 "This is not a machine PHI node that we are updating!"); 931 // "default" BB. We can go there only from header BB. 932 if (PHIBB == SDL->JTCases[i].second.Default) { 933 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 934 false)); 935 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 936 } 937 // JT BB. Just iterate over successors here 938 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 939 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 940 false)); 941 PHI->addOperand(MachineOperand::CreateMBB(BB)); 942 } 943 } 944 } 945 SDL->JTCases.clear(); 946 947 // If the switch block involved a branch to one of the actual successors, we 948 // need to update PHI nodes in that block. 949 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 950 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 951 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 952 "This is not a machine PHI node that we are updating!"); 953 if (BB->isSuccessor(PHI->getParent())) { 954 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 955 false)); 956 PHI->addOperand(MachineOperand::CreateMBB(BB)); 957 } 958 } 959 960 // If we generated any switch lowering information, build and codegen any 961 // additional DAGs necessary. 962 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 963 // Set the current basic block to the mbb we wish to insert the code into 964 BB = SDL->SwitchCases[i].ThisBB; 965 SDL->setCurrentBasicBlock(BB); 966 967 // Emit the code 968 SDL->visitSwitchCase(SDL->SwitchCases[i]); 969 CurDAG->setRoot(SDL->getRoot()); 970 CodeGenAndEmitDAG(); 971 SDL->clear(); 972 973 // Handle any PHI nodes in successors of this chunk, as if we were coming 974 // from the original BB before switch expansion. Note that PHI nodes can 975 // occur multiple times in PHINodesToUpdate. We have to be very careful to 976 // handle them the right number of times. 977 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 978 for (MachineBasicBlock::iterator Phi = BB->begin(); 979 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 980 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 981 for (unsigned pn = 0; ; ++pn) { 982 assert(pn != SDL->PHINodesToUpdate.size() && 983 "Didn't find PHI entry!"); 984 if (SDL->PHINodesToUpdate[pn].first == Phi) { 985 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 986 second, false)); 987 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 988 break; 989 } 990 } 991 } 992 993 // Don't process RHS if same block as LHS. 994 if (BB == SDL->SwitchCases[i].FalseBB) 995 SDL->SwitchCases[i].FalseBB = 0; 996 997 // If we haven't handled the RHS, do so now. Otherwise, we're done. 998 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 999 SDL->SwitchCases[i].FalseBB = 0; 1000 } 1001 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 1002 } 1003 SDL->SwitchCases.clear(); 1004 1005 SDL->PHINodesToUpdate.clear(); 1006} 1007 1008 1009/// Schedule - Pick a safe ordering for instructions for each 1010/// target node in the graph. 1011/// 1012ScheduleDAG *SelectionDAGISel::Schedule() { 1013 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1014 1015 if (!Ctor) { 1016 Ctor = ISHeuristic; 1017 RegisterScheduler::setDefault(Ctor); 1018 } 1019 1020 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast); 1021 Scheduler->Run(); 1022 1023 return Scheduler; 1024} 1025 1026 1027HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1028 return new HazardRecognizer(); 1029} 1030 1031//===----------------------------------------------------------------------===// 1032// Helper functions used by the generated instruction selector. 1033//===----------------------------------------------------------------------===// 1034// Calls to these methods are generated by tblgen. 1035 1036/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1037/// the dag combiner simplified the 255, we still want to match. RHS is the 1038/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1039/// specified in the .td file (e.g. 255). 1040bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1041 int64_t DesiredMaskS) const { 1042 const APInt &ActualMask = RHS->getAPIntValue(); 1043 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1044 1045 // If the actual mask exactly matches, success! 1046 if (ActualMask == DesiredMask) 1047 return true; 1048 1049 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1050 if (ActualMask.intersects(~DesiredMask)) 1051 return false; 1052 1053 // Otherwise, the DAG Combiner may have proven that the value coming in is 1054 // either already zero or is not demanded. Check for known zero input bits. 1055 APInt NeededMask = DesiredMask & ~ActualMask; 1056 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1057 return true; 1058 1059 // TODO: check to see if missing bits are just not demanded. 1060 1061 // Otherwise, this pattern doesn't match. 1062 return false; 1063} 1064 1065/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1066/// the dag combiner simplified the 255, we still want to match. RHS is the 1067/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1068/// specified in the .td file (e.g. 255). 1069bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1070 int64_t DesiredMaskS) const { 1071 const APInt &ActualMask = RHS->getAPIntValue(); 1072 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1073 1074 // If the actual mask exactly matches, success! 1075 if (ActualMask == DesiredMask) 1076 return true; 1077 1078 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1079 if (ActualMask.intersects(~DesiredMask)) 1080 return false; 1081 1082 // Otherwise, the DAG Combiner may have proven that the value coming in is 1083 // either already zero or is not demanded. Check for known zero input bits. 1084 APInt NeededMask = DesiredMask & ~ActualMask; 1085 1086 APInt KnownZero, KnownOne; 1087 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1088 1089 // If all the missing bits in the or are already known to be set, match! 1090 if ((NeededMask & KnownOne) == NeededMask) 1091 return true; 1092 1093 // TODO: check to see if missing bits are just not demanded. 1094 1095 // Otherwise, this pattern doesn't match. 1096 return false; 1097} 1098 1099 1100/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1101/// by tblgen. Others should not call it. 1102void SelectionDAGISel:: 1103SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1104 std::vector<SDValue> InOps; 1105 std::swap(InOps, Ops); 1106 1107 Ops.push_back(InOps[0]); // input chain. 1108 Ops.push_back(InOps[1]); // input asm string. 1109 1110 unsigned i = 2, e = InOps.size(); 1111 if (InOps[e-1].getValueType() == MVT::Flag) 1112 --e; // Don't process a flag operand if it is here. 1113 1114 while (i != e) { 1115 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1116 if ((Flags & 7) != 4 /*MEM*/ && 1117 (Flags & 7) != 7 /*MEM OVERLAPS EARLYCLOBBER*/) { 1118 // Just skip over this operand, copying the operands verbatim. 1119 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 1120 i += (Flags >> 3) + 1; 1121 } else { 1122 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 1123 // Otherwise, this is a memory operand. Ask the target to select it. 1124 std::vector<SDValue> SelOps; 1125 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1126 cerr << "Could not match memory address. Inline asm failure!\n"; 1127 exit(1); 1128 } 1129 1130 // Add this to the output node. 1131 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy(); 1132 Ops.push_back(CurDAG->getTargetConstant((Flags & 7) | (SelOps.size()<< 3), 1133 IntPtrTy)); 1134 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1135 i += 2; 1136 } 1137 } 1138 1139 // Add the flag input back if present. 1140 if (e != InOps.size()) 1141 Ops.push_back(InOps.back()); 1142} 1143 1144char SelectionDAGISel::ID = 0; 1145