SelectionDAGISel.cpp revision 927f866105fa29feb32c050ee823d60c2509ec76
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322MachineBasicBlock * 323SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 324 const BasicBlock *LLVMBB, 325 BasicBlock::const_iterator Begin, 326 BasicBlock::const_iterator End, 327 bool &HadTailCall) { 328 // Lower all of the non-terminator instructions. If a call is emitted 329 // as a tail call, cease emitting nodes for this block. Terminators 330 // are handled below. 331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 332 SDB->visit(*I); 333 334 // Make sure the root of the DAG is up-to-date. 335 CurDAG->setRoot(SDB->getControlRoot()); 336 HadTailCall = SDB->HasTailCall; 337 SDB->clear(); 338 339 // Final step, emit the lowered DAG as machine code. 340 return CodeGenAndEmitDAG(BB); 341} 342 343namespace { 344/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 345/// nodes from the worklist. 346class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 347 SmallVector<SDNode*, 128> &Worklist; 348 SmallPtrSet<SDNode*, 128> &InWorklist; 349public: 350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 351 SmallPtrSet<SDNode*, 128> &inwl) 352 : Worklist(wl), InWorklist(inwl) {} 353 354 void RemoveFromWorklist(SDNode *N) { 355 if (!InWorklist.erase(N)) return; 356 357 SmallVector<SDNode*, 128>::iterator I = 358 std::find(Worklist.begin(), Worklist.end(), N); 359 assert(I != Worklist.end() && "Not in worklist"); 360 361 *I = Worklist.back(); 362 Worklist.pop_back(); 363 } 364 365 virtual void NodeDeleted(SDNode *N, SDNode *E) { 366 RemoveFromWorklist(N); 367 } 368 369 virtual void NodeUpdated(SDNode *N) { 370 // Ignore updates. 371 } 372}; 373} 374 375void SelectionDAGISel::ComputeLiveOutVRegInfo() { 376 SmallPtrSet<SDNode*, 128> VisitedNodes; 377 SmallVector<SDNode*, 128> Worklist; 378 379 Worklist.push_back(CurDAG->getRoot().getNode()); 380 381 APInt Mask; 382 APInt KnownZero; 383 APInt KnownOne; 384 385 do { 386 SDNode *N = Worklist.pop_back_val(); 387 388 // If we've already seen this node, ignore it. 389 if (!VisitedNodes.insert(N)) 390 continue; 391 392 // Otherwise, add all chain operands to the worklist. 393 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 394 if (N->getOperand(i).getValueType() == MVT::Other) 395 Worklist.push_back(N->getOperand(i).getNode()); 396 397 // If this is a CopyToReg with a vreg dest, process it. 398 if (N->getOpcode() != ISD::CopyToReg) 399 continue; 400 401 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 402 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 403 continue; 404 405 // Ignore non-scalar or non-integer values. 406 SDValue Src = N->getOperand(2); 407 EVT SrcVT = Src.getValueType(); 408 if (!SrcVT.isInteger() || SrcVT.isVector()) 409 continue; 410 411 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 412 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 413 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 414 415 // Only install this information if it tells us something. 416 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 417 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 418 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 419 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 420 FunctionLoweringInfo::LiveOutInfo &LOI = 421 FuncInfo->LiveOutRegInfo[DestReg]; 422 LOI.NumSignBits = NumSignBits; 423 LOI.KnownOne = KnownOne; 424 LOI.KnownZero = KnownZero; 425 } 426 } while (!Worklist.empty()); 427} 428 429MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 430 std::string GroupName; 431 if (TimePassesIsEnabled) 432 GroupName = "Instruction Selection and Scheduling"; 433 std::string BlockName; 434 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 435 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 436 ViewSUnitDAGs) 437 BlockName = MF->getFunction()->getNameStr() + ":" + 438 BB->getBasicBlock()->getNameStr(); 439 440 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 441 442 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 443 444 // Run the DAG combiner in pre-legalize mode. 445 { 446 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 447 CurDAG->Combine(Unrestricted, *AA, OptLevel); 448 } 449 450 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 451 452 // Second step, hack on the DAG until it only uses operations and types that 453 // the target supports. 454 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 455 BlockName); 456 457 bool Changed; 458 { 459 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 460 Changed = CurDAG->LegalizeTypes(); 461 } 462 463 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 464 465 if (Changed) { 466 if (ViewDAGCombineLT) 467 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 468 469 // Run the DAG combiner in post-type-legalize mode. 470 { 471 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 472 TimePassesIsEnabled); 473 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 474 } 475 476 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 477 CurDAG->dump()); 478 } 479 480 { 481 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 482 Changed = CurDAG->LegalizeVectors(); 483 } 484 485 if (Changed) { 486 { 487 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 488 CurDAG->LegalizeTypes(); 489 } 490 491 if (ViewDAGCombineLT) 492 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 493 494 // Run the DAG combiner in post-type-legalize mode. 495 { 496 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 497 TimePassesIsEnabled); 498 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 499 } 500 501 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 502 CurDAG->dump()); 503 } 504 505 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 506 507 { 508 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 509 CurDAG->Legalize(OptLevel); 510 } 511 512 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 513 514 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 515 516 // Run the DAG combiner in post-legalize mode. 517 { 518 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 519 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 520 } 521 522 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 523 524 if (OptLevel != CodeGenOpt::None) 525 ComputeLiveOutVRegInfo(); 526 527 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 528 529 // Third, instruction select all of the operations to machine code, adding the 530 // code to the MachineBasicBlock. 531 { 532 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 533 DoInstructionSelection(); 534 } 535 536 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 537 538 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 539 540 // Schedule machine code. 541 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 542 { 543 NamedRegionTimer T("Instruction Scheduling", GroupName, 544 TimePassesIsEnabled); 545 Scheduler->Run(CurDAG, BB, BB->end()); 546 } 547 548 if (ViewSUnitDAGs) Scheduler->viewGraph(); 549 550 // Emit machine code to BB. This can change 'BB' to the last block being 551 // inserted into. 552 { 553 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 554 BB = Scheduler->EmitSchedule(); 555 } 556 557 // Free the scheduler state. 558 { 559 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 560 TimePassesIsEnabled); 561 delete Scheduler; 562 } 563 564 // Free the SelectionDAG state, now that we're finished with it. 565 CurDAG->clear(); 566 567 return BB; 568} 569 570void SelectionDAGISel::DoInstructionSelection() { 571 DEBUG(errs() << "===== Instruction selection begins:\n"); 572 573 PreprocessISelDAG(); 574 575 // Select target instructions for the DAG. 576 { 577 // Number all nodes with a topological order and set DAGSize. 578 DAGSize = CurDAG->AssignTopologicalOrder(); 579 580 // Create a dummy node (which is not added to allnodes), that adds 581 // a reference to the root node, preventing it from being deleted, 582 // and tracking any changes of the root. 583 HandleSDNode Dummy(CurDAG->getRoot()); 584 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 585 ++ISelPosition; 586 587 // The AllNodes list is now topological-sorted. Visit the 588 // nodes by starting at the end of the list (the root of the 589 // graph) and preceding back toward the beginning (the entry 590 // node). 591 while (ISelPosition != CurDAG->allnodes_begin()) { 592 SDNode *Node = --ISelPosition; 593 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 594 // but there are currently some corner cases that it misses. Also, this 595 // makes it theoretically possible to disable the DAGCombiner. 596 if (Node->use_empty()) 597 continue; 598 599 SDNode *ResNode = Select(Node); 600 601 // FIXME: This is pretty gross. 'Select' should be changed to not return 602 // anything at all and this code should be nuked with a tactical strike. 603 604 // If node should not be replaced, continue with the next one. 605 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 606 continue; 607 // Replace node. 608 if (ResNode) 609 ReplaceUses(Node, ResNode); 610 611 // If after the replacement this node is not used any more, 612 // remove this dead node. 613 if (Node->use_empty()) { // Don't delete EntryToken, etc. 614 ISelUpdater ISU(ISelPosition); 615 CurDAG->RemoveDeadNode(Node, &ISU); 616 } 617 } 618 619 CurDAG->setRoot(Dummy.getValue()); 620 } 621 622 DEBUG(errs() << "===== Instruction selection ends:\n"); 623 624 PostprocessISelDAG(); 625} 626 627/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 628/// do other setup for EH landing-pad blocks. 629void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 630 // Add a label to mark the beginning of the landing pad. Deletion of the 631 // landing pad can thus be detected via the MachineModuleInfo. 632 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 633 634 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 635 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 636 637 // Mark exception register as live in. 638 unsigned Reg = TLI.getExceptionAddressRegister(); 639 if (Reg) BB->addLiveIn(Reg); 640 641 // Mark exception selector register as live in. 642 Reg = TLI.getExceptionSelectorRegister(); 643 if (Reg) BB->addLiveIn(Reg); 644 645 // FIXME: Hack around an exception handling flaw (PR1508): the personality 646 // function and list of typeids logically belong to the invoke (or, if you 647 // like, the basic block containing the invoke), and need to be associated 648 // with it in the dwarf exception handling tables. Currently however the 649 // information is provided by an intrinsic (eh.selector) that can be moved 650 // to unexpected places by the optimizers: if the unwind edge is critical, 651 // then breaking it can result in the intrinsics being in the successor of 652 // the landing pad, not the landing pad itself. This results 653 // in exceptions not being caught because no typeids are associated with 654 // the invoke. This may not be the only way things can go wrong, but it 655 // is the only way we try to work around for the moment. 656 const BasicBlock *LLVMBB = BB->getBasicBlock(); 657 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 658 659 if (Br && Br->isUnconditional()) { // Critical edge? 660 BasicBlock::const_iterator I, E; 661 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 662 if (isa<EHSelectorInst>(I)) 663 break; 664 665 if (I == E) 666 // No catch info found - try to extract some from the successor. 667 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 668 } 669} 670 671void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 672 // Initialize the Fast-ISel state, if needed. 673 FastISel *FastIS = 0; 674 if (EnableFastISel) 675 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 676 FuncInfo->StaticAllocaMap, 677 FuncInfo->PHINodesToUpdate 678#ifndef NDEBUG 679 , FuncInfo->CatchInfoLost 680#endif 681 ); 682 683 // Iterate over all basic blocks in the function. 684 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 685 const BasicBlock *LLVMBB = &*I; 686 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 687 688 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 689 BasicBlock::const_iterator const End = LLVMBB->end(); 690 BasicBlock::const_iterator BI = Begin; 691 692 // Lower any arguments needed in this block if this is the entry block. 693 if (LLVMBB == &Fn.getEntryBlock()) 694 LowerArguments(LLVMBB); 695 696 // Setup an EH landing-pad block. 697 if (BB->isLandingPad()) 698 PrepareEHLandingPad(BB); 699 700 // Before doing SelectionDAG ISel, see if FastISel has been requested. 701 if (FastIS) { 702 // Emit code for any incoming arguments. This must happen before 703 // beginning FastISel on the entry block. 704 if (LLVMBB == &Fn.getEntryBlock()) { 705 CurDAG->setRoot(SDB->getControlRoot()); 706 SDB->clear(); 707 BB = CodeGenAndEmitDAG(BB); 708 } 709 FastIS->startNewBlock(BB); 710 // Do FastISel on as many instructions as possible. 711 for (; BI != End; ++BI) { 712 // Try to select the instruction with FastISel. 713 if (FastIS->SelectInstruction(BI)) 714 continue; 715 716 // Then handle certain instructions as single-LLVM-Instruction blocks. 717 if (isa<CallInst>(BI)) { 718 ++NumFastIselFailures; 719 if (EnableFastISelVerbose || EnableFastISelAbort) { 720 dbgs() << "FastISel missed call: "; 721 BI->dump(); 722 } 723 724 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 725 unsigned &R = FuncInfo->ValueMap[BI]; 726 if (!R) 727 R = FuncInfo->CreateRegForValue(BI); 728 } 729 730 bool HadTailCall = false; 731 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 732 733 // If the call was emitted as a tail call, we're done with the block. 734 if (HadTailCall) { 735 BI = End; 736 break; 737 } 738 739 // If the instruction was codegen'd with multiple blocks, 740 // inform the FastISel object where to resume inserting. 741 FastIS->setCurrentBlock(BB); 742 continue; 743 } 744 745 // Otherwise, give up on FastISel for the rest of the block. 746 // For now, be a little lenient about non-branch terminators. 747 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 748 ++NumFastIselFailures; 749 if (EnableFastISelVerbose || EnableFastISelAbort) { 750 dbgs() << "FastISel miss: "; 751 BI->dump(); 752 } 753 if (EnableFastISelAbort) 754 // The "fast" selector couldn't handle something and bailed. 755 // For the purpose of debugging, just abort. 756 llvm_unreachable("FastISel didn't select the entire block"); 757 } 758 break; 759 } 760 } 761 762 // Run SelectionDAG instruction selection on the remainder of the block 763 // not handled by FastISel. If FastISel is not run, this is the entire 764 // block. 765 if (BI != End) { 766 bool HadTailCall; 767 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 768 } 769 770 FinishBasicBlock(BB); 771 FuncInfo->PHINodesToUpdate.clear(); 772 } 773 774 delete FastIS; 775} 776 777void 778SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 779 780 DEBUG(dbgs() << "Total amount of phi nodes to update: " 781 << FuncInfo->PHINodesToUpdate.size() << "\n"; 782 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 783 dbgs() << "Node " << i << " : (" 784 << FuncInfo->PHINodesToUpdate[i].first 785 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 786 787 // Next, now that we know what the last MBB the LLVM BB expanded is, update 788 // PHI nodes in successors. 789 if (SDB->SwitchCases.empty() && 790 SDB->JTCases.empty() && 791 SDB->BitTestCases.empty()) { 792 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 793 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 794 assert(PHI->isPHI() && 795 "This is not a machine PHI node that we are updating!"); 796 if (!BB->isSuccessor(PHI->getParent())) 797 continue; 798 PHI->addOperand( 799 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 800 PHI->addOperand(MachineOperand::CreateMBB(BB)); 801 } 802 return; 803 } 804 805 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 806 // Lower header first, if it wasn't already lowered 807 if (!SDB->BitTestCases[i].Emitted) { 808 // Set the current basic block to the mbb we wish to insert the code into 809 BB = SDB->BitTestCases[i].Parent; 810 // Emit the code 811 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 812 CurDAG->setRoot(SDB->getRoot()); 813 SDB->clear(); 814 BB = CodeGenAndEmitDAG(BB); 815 } 816 817 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 818 // Set the current basic block to the mbb we wish to insert the code into 819 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 820 // Emit the code 821 if (j+1 != ej) 822 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 823 SDB->BitTestCases[i].Reg, 824 SDB->BitTestCases[i].Cases[j], 825 BB); 826 else 827 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 828 SDB->BitTestCases[i].Reg, 829 SDB->BitTestCases[i].Cases[j], 830 BB); 831 832 833 CurDAG->setRoot(SDB->getRoot()); 834 SDB->clear(); 835 BB = CodeGenAndEmitDAG(BB); 836 } 837 838 // Update PHI Nodes 839 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 840 pi != pe; ++pi) { 841 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 842 MachineBasicBlock *PHIBB = PHI->getParent(); 843 assert(PHI->isPHI() && 844 "This is not a machine PHI node that we are updating!"); 845 // This is "default" BB. We have two jumps to it. From "header" BB and 846 // from last "case" BB. 847 if (PHIBB == SDB->BitTestCases[i].Default) { 848 PHI->addOperand(MachineOperand:: 849 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 850 false)); 851 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 852 PHI->addOperand(MachineOperand:: 853 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 854 false)); 855 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 856 back().ThisBB)); 857 } 858 // One of "cases" BB. 859 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 860 j != ej; ++j) { 861 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 862 if (cBB->isSuccessor(PHIBB)) { 863 PHI->addOperand(MachineOperand:: 864 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 865 false)); 866 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 867 } 868 } 869 } 870 } 871 SDB->BitTestCases.clear(); 872 873 // If the JumpTable record is filled in, then we need to emit a jump table. 874 // Updating the PHI nodes is tricky in this case, since we need to determine 875 // whether the PHI is a successor of the range check MBB or the jump table MBB 876 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 877 // Lower header first, if it wasn't already lowered 878 if (!SDB->JTCases[i].first.Emitted) { 879 // Set the current basic block to the mbb we wish to insert the code into 880 BB = SDB->JTCases[i].first.HeaderBB; 881 // Emit the code 882 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 883 BB); 884 CurDAG->setRoot(SDB->getRoot()); 885 SDB->clear(); 886 BB = CodeGenAndEmitDAG(BB); 887 } 888 889 // Set the current basic block to the mbb we wish to insert the code into 890 BB = SDB->JTCases[i].second.MBB; 891 // Emit the code 892 SDB->visitJumpTable(SDB->JTCases[i].second); 893 CurDAG->setRoot(SDB->getRoot()); 894 SDB->clear(); 895 BB = CodeGenAndEmitDAG(BB); 896 897 // Update PHI Nodes 898 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 899 pi != pe; ++pi) { 900 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 901 MachineBasicBlock *PHIBB = PHI->getParent(); 902 assert(PHI->isPHI() && 903 "This is not a machine PHI node that we are updating!"); 904 // "default" BB. We can go there only from header BB. 905 if (PHIBB == SDB->JTCases[i].second.Default) { 906 PHI->addOperand 907 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 908 false)); 909 PHI->addOperand 910 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 911 } 912 // JT BB. Just iterate over successors here 913 if (BB->isSuccessor(PHIBB)) { 914 PHI->addOperand 915 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 916 false)); 917 PHI->addOperand(MachineOperand::CreateMBB(BB)); 918 } 919 } 920 } 921 SDB->JTCases.clear(); 922 923 // If the switch block involved a branch to one of the actual successors, we 924 // need to update PHI nodes in that block. 925 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 926 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 927 assert(PHI->isPHI() && 928 "This is not a machine PHI node that we are updating!"); 929 if (BB->isSuccessor(PHI->getParent())) { 930 PHI->addOperand( 931 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 932 PHI->addOperand(MachineOperand::CreateMBB(BB)); 933 } 934 } 935 936 // If we generated any switch lowering information, build and codegen any 937 // additional DAGs necessary. 938 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 939 // Set the current basic block to the mbb we wish to insert the code into 940 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 941 942 // Determine the unique successors. 943 SmallVector<MachineBasicBlock *, 2> Succs; 944 Succs.push_back(SDB->SwitchCases[i].TrueBB); 945 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 946 Succs.push_back(SDB->SwitchCases[i].FalseBB); 947 948 // Emit the code. Note that this could result in ThisBB being split, so 949 // we need to check for updates. 950 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 951 CurDAG->setRoot(SDB->getRoot()); 952 SDB->clear(); 953 ThisBB = CodeGenAndEmitDAG(BB); 954 955 // Handle any PHI nodes in successors of this chunk, as if we were coming 956 // from the original BB before switch expansion. Note that PHI nodes can 957 // occur multiple times in PHINodesToUpdate. We have to be very careful to 958 // handle them the right number of times. 959 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 960 BB = Succs[i]; 961 // BB may have been removed from the CFG if a branch was constant folded. 962 if (ThisBB->isSuccessor(BB)) { 963 for (MachineBasicBlock::iterator Phi = BB->begin(); 964 Phi != BB->end() && Phi->isPHI(); 965 ++Phi) { 966 // This value for this PHI node is recorded in PHINodesToUpdate. 967 for (unsigned pn = 0; ; ++pn) { 968 assert(pn != FuncInfo->PHINodesToUpdate.size() && 969 "Didn't find PHI entry!"); 970 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 971 Phi->addOperand(MachineOperand:: 972 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 973 false)); 974 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 975 break; 976 } 977 } 978 } 979 } 980 } 981 } 982 SDB->SwitchCases.clear(); 983} 984 985 986/// Create the scheduler. If a specific scheduler was specified 987/// via the SchedulerRegistry, use it, otherwise select the 988/// one preferred by the target. 989/// 990ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 991 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 992 993 if (!Ctor) { 994 Ctor = ISHeuristic; 995 RegisterScheduler::setDefault(Ctor); 996 } 997 998 return Ctor(this, OptLevel); 999} 1000 1001ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1002 return new ScheduleHazardRecognizer(); 1003} 1004 1005//===----------------------------------------------------------------------===// 1006// Helper functions used by the generated instruction selector. 1007//===----------------------------------------------------------------------===// 1008// Calls to these methods are generated by tblgen. 1009 1010/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1011/// the dag combiner simplified the 255, we still want to match. RHS is the 1012/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1013/// specified in the .td file (e.g. 255). 1014bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1015 int64_t DesiredMaskS) const { 1016 const APInt &ActualMask = RHS->getAPIntValue(); 1017 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1018 1019 // If the actual mask exactly matches, success! 1020 if (ActualMask == DesiredMask) 1021 return true; 1022 1023 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1024 if (ActualMask.intersects(~DesiredMask)) 1025 return false; 1026 1027 // Otherwise, the DAG Combiner may have proven that the value coming in is 1028 // either already zero or is not demanded. Check for known zero input bits. 1029 APInt NeededMask = DesiredMask & ~ActualMask; 1030 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1031 return true; 1032 1033 // TODO: check to see if missing bits are just not demanded. 1034 1035 // Otherwise, this pattern doesn't match. 1036 return false; 1037} 1038 1039/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1040/// the dag combiner simplified the 255, we still want to match. RHS is the 1041/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1042/// specified in the .td file (e.g. 255). 1043bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1044 int64_t DesiredMaskS) const { 1045 const APInt &ActualMask = RHS->getAPIntValue(); 1046 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1047 1048 // If the actual mask exactly matches, success! 1049 if (ActualMask == DesiredMask) 1050 return true; 1051 1052 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1053 if (ActualMask.intersects(~DesiredMask)) 1054 return false; 1055 1056 // Otherwise, the DAG Combiner may have proven that the value coming in is 1057 // either already zero or is not demanded. Check for known zero input bits. 1058 APInt NeededMask = DesiredMask & ~ActualMask; 1059 1060 APInt KnownZero, KnownOne; 1061 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1062 1063 // If all the missing bits in the or are already known to be set, match! 1064 if ((NeededMask & KnownOne) == NeededMask) 1065 return true; 1066 1067 // TODO: check to see if missing bits are just not demanded. 1068 1069 // Otherwise, this pattern doesn't match. 1070 return false; 1071} 1072 1073 1074/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1075/// by tblgen. Others should not call it. 1076void SelectionDAGISel:: 1077SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1078 std::vector<SDValue> InOps; 1079 std::swap(InOps, Ops); 1080 1081 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1082 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1083 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1084 1085 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1086 if (InOps[e-1].getValueType() == MVT::Flag) 1087 --e; // Don't process a flag operand if it is here. 1088 1089 while (i != e) { 1090 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1091 if (!InlineAsm::isMemKind(Flags)) { 1092 // Just skip over this operand, copying the operands verbatim. 1093 Ops.insert(Ops.end(), InOps.begin()+i, 1094 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1095 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1096 } else { 1097 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1098 "Memory operand with multiple values?"); 1099 // Otherwise, this is a memory operand. Ask the target to select it. 1100 std::vector<SDValue> SelOps; 1101 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1102 report_fatal_error("Could not match memory address. Inline asm" 1103 " failure!"); 1104 1105 // Add this to the output node. 1106 unsigned NewFlags = 1107 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1108 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1109 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1110 i += 2; 1111 } 1112 } 1113 1114 // Add the flag input back if present. 1115 if (e != InOps.size()) 1116 Ops.push_back(InOps.back()); 1117} 1118 1119/// findFlagUse - Return use of EVT::Flag value produced by the specified 1120/// SDNode. 1121/// 1122static SDNode *findFlagUse(SDNode *N) { 1123 unsigned FlagResNo = N->getNumValues()-1; 1124 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1125 SDUse &Use = I.getUse(); 1126 if (Use.getResNo() == FlagResNo) 1127 return Use.getUser(); 1128 } 1129 return NULL; 1130} 1131 1132/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1133/// This function recursively traverses up the operand chain, ignoring 1134/// certain nodes. 1135static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1136 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1137 bool IgnoreChains) { 1138 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1139 // greater than all of its (recursive) operands. If we scan to a point where 1140 // 'use' is smaller than the node we're scanning for, then we know we will 1141 // never find it. 1142 // 1143 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1144 // happen because we scan down to newly selected nodes in the case of flag 1145 // uses. 1146 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1147 return false; 1148 1149 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1150 // won't fail if we scan it again. 1151 if (!Visited.insert(Use)) 1152 return false; 1153 1154 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1155 // Ignore chain uses, they are validated by HandleMergeInputChains. 1156 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1157 continue; 1158 1159 SDNode *N = Use->getOperand(i).getNode(); 1160 if (N == Def) { 1161 if (Use == ImmedUse || Use == Root) 1162 continue; // We are not looking for immediate use. 1163 assert(N != Root); 1164 return true; 1165 } 1166 1167 // Traverse up the operand chain. 1168 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1169 return true; 1170 } 1171 return false; 1172} 1173 1174/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1175/// operand node N of U during instruction selection that starts at Root. 1176bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1177 SDNode *Root) const { 1178 if (OptLevel == CodeGenOpt::None) return false; 1179 return N.hasOneUse(); 1180} 1181 1182/// IsLegalToFold - Returns true if the specific operand node N of 1183/// U can be folded during instruction selection that starts at Root. 1184bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1185 CodeGenOpt::Level OptLevel, 1186 bool IgnoreChains) { 1187 if (OptLevel == CodeGenOpt::None) return false; 1188 1189 // If Root use can somehow reach N through a path that that doesn't contain 1190 // U then folding N would create a cycle. e.g. In the following 1191 // diagram, Root can reach N through X. If N is folded into into Root, then 1192 // X is both a predecessor and a successor of U. 1193 // 1194 // [N*] // 1195 // ^ ^ // 1196 // / \ // 1197 // [U*] [X]? // 1198 // ^ ^ // 1199 // \ / // 1200 // \ / // 1201 // [Root*] // 1202 // 1203 // * indicates nodes to be folded together. 1204 // 1205 // If Root produces a flag, then it gets (even more) interesting. Since it 1206 // will be "glued" together with its flag use in the scheduler, we need to 1207 // check if it might reach N. 1208 // 1209 // [N*] // 1210 // ^ ^ // 1211 // / \ // 1212 // [U*] [X]? // 1213 // ^ ^ // 1214 // \ \ // 1215 // \ | // 1216 // [Root*] | // 1217 // ^ | // 1218 // f | // 1219 // | / // 1220 // [Y] / // 1221 // ^ / // 1222 // f / // 1223 // | / // 1224 // [FU] // 1225 // 1226 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1227 // (call it Fold), then X is a predecessor of FU and a successor of 1228 // Fold. But since Fold and FU are flagged together, this will create 1229 // a cycle in the scheduling graph. 1230 1231 // If the node has flags, walk down the graph to the "lowest" node in the 1232 // flagged set. 1233 EVT VT = Root->getValueType(Root->getNumValues()-1); 1234 while (VT == MVT::Flag) { 1235 SDNode *FU = findFlagUse(Root); 1236 if (FU == NULL) 1237 break; 1238 Root = FU; 1239 VT = Root->getValueType(Root->getNumValues()-1); 1240 1241 // If our query node has a flag result with a use, we've walked up it. If 1242 // the user (which has already been selected) has a chain or indirectly uses 1243 // the chain, our WalkChainUsers predicate will not consider it. Because of 1244 // this, we cannot ignore chains in this predicate. 1245 IgnoreChains = false; 1246 } 1247 1248 1249 SmallPtrSet<SDNode*, 16> Visited; 1250 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1251} 1252 1253SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1254 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1255 SelectInlineAsmMemoryOperands(Ops); 1256 1257 std::vector<EVT> VTs; 1258 VTs.push_back(MVT::Other); 1259 VTs.push_back(MVT::Flag); 1260 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1261 VTs, &Ops[0], Ops.size()); 1262 New->setNodeId(-1); 1263 return New.getNode(); 1264} 1265 1266SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1267 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1268} 1269 1270/// GetVBR - decode a vbr encoding whose top bit is set. 1271ALWAYS_INLINE static uint64_t 1272GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1273 assert(Val >= 128 && "Not a VBR"); 1274 Val &= 127; // Remove first vbr bit. 1275 1276 unsigned Shift = 7; 1277 uint64_t NextBits; 1278 do { 1279 NextBits = MatcherTable[Idx++]; 1280 Val |= (NextBits&127) << Shift; 1281 Shift += 7; 1282 } while (NextBits & 128); 1283 1284 return Val; 1285} 1286 1287 1288/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1289/// interior flag and chain results to use the new flag and chain results. 1290void SelectionDAGISel:: 1291UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1292 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1293 SDValue InputFlag, 1294 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1295 bool isMorphNodeTo) { 1296 SmallVector<SDNode*, 4> NowDeadNodes; 1297 1298 ISelUpdater ISU(ISelPosition); 1299 1300 // Now that all the normal results are replaced, we replace the chain and 1301 // flag results if present. 1302 if (!ChainNodesMatched.empty()) { 1303 assert(InputChain.getNode() != 0 && 1304 "Matched input chains but didn't produce a chain"); 1305 // Loop over all of the nodes we matched that produced a chain result. 1306 // Replace all the chain results with the final chain we ended up with. 1307 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1308 SDNode *ChainNode = ChainNodesMatched[i]; 1309 1310 // If this node was already deleted, don't look at it. 1311 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1312 continue; 1313 1314 // Don't replace the results of the root node if we're doing a 1315 // MorphNodeTo. 1316 if (ChainNode == NodeToMatch && isMorphNodeTo) 1317 continue; 1318 1319 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1320 if (ChainVal.getValueType() == MVT::Flag) 1321 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1322 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1323 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1324 1325 // If the node became dead and we haven't already seen it, delete it. 1326 if (ChainNode->use_empty() && 1327 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1328 NowDeadNodes.push_back(ChainNode); 1329 } 1330 } 1331 1332 // If the result produces a flag, update any flag results in the matched 1333 // pattern with the flag result. 1334 if (InputFlag.getNode() != 0) { 1335 // Handle any interior nodes explicitly marked. 1336 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1337 SDNode *FRN = FlagResultNodesMatched[i]; 1338 1339 // If this node was already deleted, don't look at it. 1340 if (FRN->getOpcode() == ISD::DELETED_NODE) 1341 continue; 1342 1343 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1344 "Doesn't have a flag result"); 1345 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1346 InputFlag, &ISU); 1347 1348 // If the node became dead and we haven't already seen it, delete it. 1349 if (FRN->use_empty() && 1350 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1351 NowDeadNodes.push_back(FRN); 1352 } 1353 } 1354 1355 if (!NowDeadNodes.empty()) 1356 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1357 1358 DEBUG(errs() << "ISEL: Match complete!\n"); 1359} 1360 1361enum ChainResult { 1362 CR_Simple, 1363 CR_InducesCycle, 1364 CR_LeadsToInteriorNode 1365}; 1366 1367/// WalkChainUsers - Walk down the users of the specified chained node that is 1368/// part of the pattern we're matching, looking at all of the users we find. 1369/// This determines whether something is an interior node, whether we have a 1370/// non-pattern node in between two pattern nodes (which prevent folding because 1371/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1372/// between pattern nodes (in which case the TF becomes part of the pattern). 1373/// 1374/// The walk we do here is guaranteed to be small because we quickly get down to 1375/// already selected nodes "below" us. 1376static ChainResult 1377WalkChainUsers(SDNode *ChainedNode, 1378 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1379 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1380 ChainResult Result = CR_Simple; 1381 1382 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1383 E = ChainedNode->use_end(); UI != E; ++UI) { 1384 // Make sure the use is of the chain, not some other value we produce. 1385 if (UI.getUse().getValueType() != MVT::Other) continue; 1386 1387 SDNode *User = *UI; 1388 1389 // If we see an already-selected machine node, then we've gone beyond the 1390 // pattern that we're selecting down into the already selected chunk of the 1391 // DAG. 1392 if (User->isMachineOpcode() || 1393 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1394 continue; 1395 1396 if (User->getOpcode() == ISD::CopyToReg || 1397 User->getOpcode() == ISD::CopyFromReg || 1398 User->getOpcode() == ISD::INLINEASM || 1399 User->getOpcode() == ISD::EH_LABEL) { 1400 // If their node ID got reset to -1 then they've already been selected. 1401 // Treat them like a MachineOpcode. 1402 if (User->getNodeId() == -1) 1403 continue; 1404 } 1405 1406 // If we have a TokenFactor, we handle it specially. 1407 if (User->getOpcode() != ISD::TokenFactor) { 1408 // If the node isn't a token factor and isn't part of our pattern, then it 1409 // must be a random chained node in between two nodes we're selecting. 1410 // This happens when we have something like: 1411 // x = load ptr 1412 // call 1413 // y = x+4 1414 // store y -> ptr 1415 // Because we structurally match the load/store as a read/modify/write, 1416 // but the call is chained between them. We cannot fold in this case 1417 // because it would induce a cycle in the graph. 1418 if (!std::count(ChainedNodesInPattern.begin(), 1419 ChainedNodesInPattern.end(), User)) 1420 return CR_InducesCycle; 1421 1422 // Otherwise we found a node that is part of our pattern. For example in: 1423 // x = load ptr 1424 // y = x+4 1425 // store y -> ptr 1426 // This would happen when we're scanning down from the load and see the 1427 // store as a user. Record that there is a use of ChainedNode that is 1428 // part of the pattern and keep scanning uses. 1429 Result = CR_LeadsToInteriorNode; 1430 InteriorChainedNodes.push_back(User); 1431 continue; 1432 } 1433 1434 // If we found a TokenFactor, there are two cases to consider: first if the 1435 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1436 // uses of the TF are in our pattern) we just want to ignore it. Second, 1437 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1438 // [Load chain] 1439 // ^ 1440 // | 1441 // [Load] 1442 // ^ ^ 1443 // | \ DAG's like cheese 1444 // / \ do you? 1445 // / | 1446 // [TokenFactor] [Op] 1447 // ^ ^ 1448 // | | 1449 // \ / 1450 // \ / 1451 // [Store] 1452 // 1453 // In this case, the TokenFactor becomes part of our match and we rewrite it 1454 // as a new TokenFactor. 1455 // 1456 // To distinguish these two cases, do a recursive walk down the uses. 1457 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1458 case CR_Simple: 1459 // If the uses of the TokenFactor are just already-selected nodes, ignore 1460 // it, it is "below" our pattern. 1461 continue; 1462 case CR_InducesCycle: 1463 // If the uses of the TokenFactor lead to nodes that are not part of our 1464 // pattern that are not selected, folding would turn this into a cycle, 1465 // bail out now. 1466 return CR_InducesCycle; 1467 case CR_LeadsToInteriorNode: 1468 break; // Otherwise, keep processing. 1469 } 1470 1471 // Okay, we know we're in the interesting interior case. The TokenFactor 1472 // is now going to be considered part of the pattern so that we rewrite its 1473 // uses (it may have uses that are not part of the pattern) with the 1474 // ultimate chain result of the generated code. We will also add its chain 1475 // inputs as inputs to the ultimate TokenFactor we create. 1476 Result = CR_LeadsToInteriorNode; 1477 ChainedNodesInPattern.push_back(User); 1478 InteriorChainedNodes.push_back(User); 1479 continue; 1480 } 1481 1482 return Result; 1483} 1484 1485/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1486/// operation for when the pattern matched at least one node with a chains. The 1487/// input vector contains a list of all of the chained nodes that we match. We 1488/// must determine if this is a valid thing to cover (i.e. matching it won't 1489/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1490/// be used as the input node chain for the generated nodes. 1491static SDValue 1492HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1493 SelectionDAG *CurDAG) { 1494 // Walk all of the chained nodes we've matched, recursively scanning down the 1495 // users of the chain result. This adds any TokenFactor nodes that are caught 1496 // in between chained nodes to the chained and interior nodes list. 1497 SmallVector<SDNode*, 3> InteriorChainedNodes; 1498 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1499 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1500 InteriorChainedNodes) == CR_InducesCycle) 1501 return SDValue(); // Would induce a cycle. 1502 } 1503 1504 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1505 // that we are interested in. Form our input TokenFactor node. 1506 SmallVector<SDValue, 3> InputChains; 1507 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1508 // Add the input chain of this node to the InputChains list (which will be 1509 // the operands of the generated TokenFactor) if it's not an interior node. 1510 SDNode *N = ChainNodesMatched[i]; 1511 if (N->getOpcode() != ISD::TokenFactor) { 1512 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1513 continue; 1514 1515 // Otherwise, add the input chain. 1516 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1517 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1518 InputChains.push_back(InChain); 1519 continue; 1520 } 1521 1522 // If we have a token factor, we want to add all inputs of the token factor 1523 // that are not part of the pattern we're matching. 1524 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1525 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1526 N->getOperand(op).getNode())) 1527 InputChains.push_back(N->getOperand(op)); 1528 } 1529 } 1530 1531 SDValue Res; 1532 if (InputChains.size() == 1) 1533 return InputChains[0]; 1534 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1535 MVT::Other, &InputChains[0], InputChains.size()); 1536} 1537 1538/// MorphNode - Handle morphing a node in place for the selector. 1539SDNode *SelectionDAGISel:: 1540MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1541 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1542 // It is possible we're using MorphNodeTo to replace a node with no 1543 // normal results with one that has a normal result (or we could be 1544 // adding a chain) and the input could have flags and chains as well. 1545 // In this case we need to shift the operands down. 1546 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1547 // than the old isel though. 1548 int OldFlagResultNo = -1, OldChainResultNo = -1; 1549 1550 unsigned NTMNumResults = Node->getNumValues(); 1551 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1552 OldFlagResultNo = NTMNumResults-1; 1553 if (NTMNumResults != 1 && 1554 Node->getValueType(NTMNumResults-2) == MVT::Other) 1555 OldChainResultNo = NTMNumResults-2; 1556 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1557 OldChainResultNo = NTMNumResults-1; 1558 1559 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1560 // that this deletes operands of the old node that become dead. 1561 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1562 1563 // MorphNodeTo can operate in two ways: if an existing node with the 1564 // specified operands exists, it can just return it. Otherwise, it 1565 // updates the node in place to have the requested operands. 1566 if (Res == Node) { 1567 // If we updated the node in place, reset the node ID. To the isel, 1568 // this should be just like a newly allocated machine node. 1569 Res->setNodeId(-1); 1570 } 1571 1572 unsigned ResNumResults = Res->getNumValues(); 1573 // Move the flag if needed. 1574 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1575 (unsigned)OldFlagResultNo != ResNumResults-1) 1576 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1577 SDValue(Res, ResNumResults-1)); 1578 1579 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1580 --ResNumResults; 1581 1582 // Move the chain reference if needed. 1583 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1584 (unsigned)OldChainResultNo != ResNumResults-1) 1585 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1586 SDValue(Res, ResNumResults-1)); 1587 1588 // Otherwise, no replacement happened because the node already exists. Replace 1589 // Uses of the old node with the new one. 1590 if (Res != Node) 1591 CurDAG->ReplaceAllUsesWith(Node, Res); 1592 1593 return Res; 1594} 1595 1596/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1597ALWAYS_INLINE static bool 1598CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1599 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1600 // Accept if it is exactly the same as a previously recorded node. 1601 unsigned RecNo = MatcherTable[MatcherIndex++]; 1602 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1603 return N == RecordedNodes[RecNo]; 1604} 1605 1606/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1607ALWAYS_INLINE static bool 1608CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1609 SelectionDAGISel &SDISel) { 1610 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1611} 1612 1613/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1614ALWAYS_INLINE static bool 1615CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1616 SelectionDAGISel &SDISel, SDNode *N) { 1617 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1618} 1619 1620ALWAYS_INLINE static bool 1621CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1622 SDNode *N) { 1623 uint16_t Opc = MatcherTable[MatcherIndex++]; 1624 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1625 return N->getOpcode() == Opc; 1626} 1627 1628ALWAYS_INLINE static bool 1629CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1630 SDValue N, const TargetLowering &TLI) { 1631 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1632 if (N.getValueType() == VT) return true; 1633 1634 // Handle the case when VT is iPTR. 1635 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1636} 1637 1638ALWAYS_INLINE static bool 1639CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1640 SDValue N, const TargetLowering &TLI, 1641 unsigned ChildNo) { 1642 if (ChildNo >= N.getNumOperands()) 1643 return false; // Match fails if out of range child #. 1644 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1645} 1646 1647 1648ALWAYS_INLINE static bool 1649CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1650 SDValue N) { 1651 return cast<CondCodeSDNode>(N)->get() == 1652 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1653} 1654 1655ALWAYS_INLINE static bool 1656CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1657 SDValue N, const TargetLowering &TLI) { 1658 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1659 if (cast<VTSDNode>(N)->getVT() == VT) 1660 return true; 1661 1662 // Handle the case when VT is iPTR. 1663 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1664} 1665 1666ALWAYS_INLINE static bool 1667CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1668 SDValue N) { 1669 int64_t Val = MatcherTable[MatcherIndex++]; 1670 if (Val & 128) 1671 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1672 1673 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1674 return C != 0 && C->getSExtValue() == Val; 1675} 1676 1677ALWAYS_INLINE static bool 1678CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1679 SDValue N, SelectionDAGISel &SDISel) { 1680 int64_t Val = MatcherTable[MatcherIndex++]; 1681 if (Val & 128) 1682 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1683 1684 if (N->getOpcode() != ISD::AND) return false; 1685 1686 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1687 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1688} 1689 1690ALWAYS_INLINE static bool 1691CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1692 SDValue N, SelectionDAGISel &SDISel) { 1693 int64_t Val = MatcherTable[MatcherIndex++]; 1694 if (Val & 128) 1695 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1696 1697 if (N->getOpcode() != ISD::OR) return false; 1698 1699 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1700 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1701} 1702 1703/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1704/// scope, evaluate the current node. If the current predicate is known to 1705/// fail, set Result=true and return anything. If the current predicate is 1706/// known to pass, set Result=false and return the MatcherIndex to continue 1707/// with. If the current predicate is unknown, set Result=false and return the 1708/// MatcherIndex to continue with. 1709static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1710 unsigned Index, SDValue N, 1711 bool &Result, SelectionDAGISel &SDISel, 1712 SmallVectorImpl<SDValue> &RecordedNodes){ 1713 switch (Table[Index++]) { 1714 default: 1715 Result = false; 1716 return Index-1; // Could not evaluate this predicate. 1717 case SelectionDAGISel::OPC_CheckSame: 1718 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1719 return Index; 1720 case SelectionDAGISel::OPC_CheckPatternPredicate: 1721 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1722 return Index; 1723 case SelectionDAGISel::OPC_CheckPredicate: 1724 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1725 return Index; 1726 case SelectionDAGISel::OPC_CheckOpcode: 1727 Result = !::CheckOpcode(Table, Index, N.getNode()); 1728 return Index; 1729 case SelectionDAGISel::OPC_CheckType: 1730 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1731 return Index; 1732 case SelectionDAGISel::OPC_CheckChild0Type: 1733 case SelectionDAGISel::OPC_CheckChild1Type: 1734 case SelectionDAGISel::OPC_CheckChild2Type: 1735 case SelectionDAGISel::OPC_CheckChild3Type: 1736 case SelectionDAGISel::OPC_CheckChild4Type: 1737 case SelectionDAGISel::OPC_CheckChild5Type: 1738 case SelectionDAGISel::OPC_CheckChild6Type: 1739 case SelectionDAGISel::OPC_CheckChild7Type: 1740 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1741 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1742 return Index; 1743 case SelectionDAGISel::OPC_CheckCondCode: 1744 Result = !::CheckCondCode(Table, Index, N); 1745 return Index; 1746 case SelectionDAGISel::OPC_CheckValueType: 1747 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1748 return Index; 1749 case SelectionDAGISel::OPC_CheckInteger: 1750 Result = !::CheckInteger(Table, Index, N); 1751 return Index; 1752 case SelectionDAGISel::OPC_CheckAndImm: 1753 Result = !::CheckAndImm(Table, Index, N, SDISel); 1754 return Index; 1755 case SelectionDAGISel::OPC_CheckOrImm: 1756 Result = !::CheckOrImm(Table, Index, N, SDISel); 1757 return Index; 1758 } 1759} 1760 1761namespace { 1762 1763struct MatchScope { 1764 /// FailIndex - If this match fails, this is the index to continue with. 1765 unsigned FailIndex; 1766 1767 /// NodeStack - The node stack when the scope was formed. 1768 SmallVector<SDValue, 4> NodeStack; 1769 1770 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1771 unsigned NumRecordedNodes; 1772 1773 /// NumMatchedMemRefs - The number of matched memref entries. 1774 unsigned NumMatchedMemRefs; 1775 1776 /// InputChain/InputFlag - The current chain/flag 1777 SDValue InputChain, InputFlag; 1778 1779 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1780 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1781}; 1782 1783} 1784 1785SDNode *SelectionDAGISel:: 1786SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1787 unsigned TableSize) { 1788 // FIXME: Should these even be selected? Handle these cases in the caller? 1789 switch (NodeToMatch->getOpcode()) { 1790 default: 1791 break; 1792 case ISD::EntryToken: // These nodes remain the same. 1793 case ISD::BasicBlock: 1794 case ISD::Register: 1795 //case ISD::VALUETYPE: 1796 //case ISD::CONDCODE: 1797 case ISD::HANDLENODE: 1798 case ISD::MDNODE_SDNODE: 1799 case ISD::TargetConstant: 1800 case ISD::TargetConstantFP: 1801 case ISD::TargetConstantPool: 1802 case ISD::TargetFrameIndex: 1803 case ISD::TargetExternalSymbol: 1804 case ISD::TargetBlockAddress: 1805 case ISD::TargetJumpTable: 1806 case ISD::TargetGlobalTLSAddress: 1807 case ISD::TargetGlobalAddress: 1808 case ISD::TokenFactor: 1809 case ISD::CopyFromReg: 1810 case ISD::CopyToReg: 1811 case ISD::EH_LABEL: 1812 NodeToMatch->setNodeId(-1); // Mark selected. 1813 return 0; 1814 case ISD::AssertSext: 1815 case ISD::AssertZext: 1816 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1817 NodeToMatch->getOperand(0)); 1818 return 0; 1819 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1820 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1821 } 1822 1823 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1824 1825 // Set up the node stack with NodeToMatch as the only node on the stack. 1826 SmallVector<SDValue, 8> NodeStack; 1827 SDValue N = SDValue(NodeToMatch, 0); 1828 NodeStack.push_back(N); 1829 1830 // MatchScopes - Scopes used when matching, if a match failure happens, this 1831 // indicates where to continue checking. 1832 SmallVector<MatchScope, 8> MatchScopes; 1833 1834 // RecordedNodes - This is the set of nodes that have been recorded by the 1835 // state machine. 1836 SmallVector<SDValue, 8> RecordedNodes; 1837 1838 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1839 // pattern. 1840 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1841 1842 // These are the current input chain and flag for use when generating nodes. 1843 // Various Emit operations change these. For example, emitting a copytoreg 1844 // uses and updates these. 1845 SDValue InputChain, InputFlag; 1846 1847 // ChainNodesMatched - If a pattern matches nodes that have input/output 1848 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1849 // which ones they are. The result is captured into this list so that we can 1850 // update the chain results when the pattern is complete. 1851 SmallVector<SDNode*, 3> ChainNodesMatched; 1852 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1853 1854 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1855 NodeToMatch->dump(CurDAG); 1856 errs() << '\n'); 1857 1858 // Determine where to start the interpreter. Normally we start at opcode #0, 1859 // but if the state machine starts with an OPC_SwitchOpcode, then we 1860 // accelerate the first lookup (which is guaranteed to be hot) with the 1861 // OpcodeOffset table. 1862 unsigned MatcherIndex = 0; 1863 1864 if (!OpcodeOffset.empty()) { 1865 // Already computed the OpcodeOffset table, just index into it. 1866 if (N.getOpcode() < OpcodeOffset.size()) 1867 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1868 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1869 1870 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1871 // Otherwise, the table isn't computed, but the state machine does start 1872 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1873 // is the first time we're selecting an instruction. 1874 unsigned Idx = 1; 1875 while (1) { 1876 // Get the size of this case. 1877 unsigned CaseSize = MatcherTable[Idx++]; 1878 if (CaseSize & 128) 1879 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1880 if (CaseSize == 0) break; 1881 1882 // Get the opcode, add the index to the table. 1883 uint16_t Opc = MatcherTable[Idx++]; 1884 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1885 if (Opc >= OpcodeOffset.size()) 1886 OpcodeOffset.resize((Opc+1)*2); 1887 OpcodeOffset[Opc] = Idx; 1888 Idx += CaseSize; 1889 } 1890 1891 // Okay, do the lookup for the first opcode. 1892 if (N.getOpcode() < OpcodeOffset.size()) 1893 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1894 } 1895 1896 while (1) { 1897 assert(MatcherIndex < TableSize && "Invalid index"); 1898#ifndef NDEBUG 1899 unsigned CurrentOpcodeIndex = MatcherIndex; 1900#endif 1901 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1902 switch (Opcode) { 1903 case OPC_Scope: { 1904 // Okay, the semantics of this operation are that we should push a scope 1905 // then evaluate the first child. However, pushing a scope only to have 1906 // the first check fail (which then pops it) is inefficient. If we can 1907 // determine immediately that the first check (or first several) will 1908 // immediately fail, don't even bother pushing a scope for them. 1909 unsigned FailIndex; 1910 1911 while (1) { 1912 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1913 if (NumToSkip & 128) 1914 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1915 // Found the end of the scope with no match. 1916 if (NumToSkip == 0) { 1917 FailIndex = 0; 1918 break; 1919 } 1920 1921 FailIndex = MatcherIndex+NumToSkip; 1922 1923 unsigned MatcherIndexOfPredicate = MatcherIndex; 1924 (void)MatcherIndexOfPredicate; // silence warning. 1925 1926 // If we can't evaluate this predicate without pushing a scope (e.g. if 1927 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1928 // push the scope and evaluate the full predicate chain. 1929 bool Result; 1930 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1931 Result, *this, RecordedNodes); 1932 if (!Result) 1933 break; 1934 1935 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1936 << "index " << MatcherIndexOfPredicate 1937 << ", continuing at " << FailIndex << "\n"); 1938 ++NumDAGIselRetries; 1939 1940 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1941 // move to the next case. 1942 MatcherIndex = FailIndex; 1943 } 1944 1945 // If the whole scope failed to match, bail. 1946 if (FailIndex == 0) break; 1947 1948 // Push a MatchScope which indicates where to go if the first child fails 1949 // to match. 1950 MatchScope NewEntry; 1951 NewEntry.FailIndex = FailIndex; 1952 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1953 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1954 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1955 NewEntry.InputChain = InputChain; 1956 NewEntry.InputFlag = InputFlag; 1957 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1958 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1959 MatchScopes.push_back(NewEntry); 1960 continue; 1961 } 1962 case OPC_RecordNode: 1963 // Remember this node, it may end up being an operand in the pattern. 1964 RecordedNodes.push_back(N); 1965 continue; 1966 1967 case OPC_RecordChild0: case OPC_RecordChild1: 1968 case OPC_RecordChild2: case OPC_RecordChild3: 1969 case OPC_RecordChild4: case OPC_RecordChild5: 1970 case OPC_RecordChild6: case OPC_RecordChild7: { 1971 unsigned ChildNo = Opcode-OPC_RecordChild0; 1972 if (ChildNo >= N.getNumOperands()) 1973 break; // Match fails if out of range child #. 1974 1975 RecordedNodes.push_back(N->getOperand(ChildNo)); 1976 continue; 1977 } 1978 case OPC_RecordMemRef: 1979 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 1980 continue; 1981 1982 case OPC_CaptureFlagInput: 1983 // If the current node has an input flag, capture it in InputFlag. 1984 if (N->getNumOperands() != 0 && 1985 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 1986 InputFlag = N->getOperand(N->getNumOperands()-1); 1987 continue; 1988 1989 case OPC_MoveChild: { 1990 unsigned ChildNo = MatcherTable[MatcherIndex++]; 1991 if (ChildNo >= N.getNumOperands()) 1992 break; // Match fails if out of range child #. 1993 N = N.getOperand(ChildNo); 1994 NodeStack.push_back(N); 1995 continue; 1996 } 1997 1998 case OPC_MoveParent: 1999 // Pop the current node off the NodeStack. 2000 NodeStack.pop_back(); 2001 assert(!NodeStack.empty() && "Node stack imbalance!"); 2002 N = NodeStack.back(); 2003 continue; 2004 2005 case OPC_CheckSame: 2006 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2007 continue; 2008 case OPC_CheckPatternPredicate: 2009 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2010 continue; 2011 case OPC_CheckPredicate: 2012 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2013 N.getNode())) 2014 break; 2015 continue; 2016 case OPC_CheckComplexPat: { 2017 unsigned CPNum = MatcherTable[MatcherIndex++]; 2018 unsigned RecNo = MatcherTable[MatcherIndex++]; 2019 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2020 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2021 RecordedNodes)) 2022 break; 2023 continue; 2024 } 2025 case OPC_CheckOpcode: 2026 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2027 continue; 2028 2029 case OPC_CheckType: 2030 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2031 continue; 2032 2033 case OPC_SwitchOpcode: { 2034 unsigned CurNodeOpcode = N.getOpcode(); 2035 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2036 unsigned CaseSize; 2037 while (1) { 2038 // Get the size of this case. 2039 CaseSize = MatcherTable[MatcherIndex++]; 2040 if (CaseSize & 128) 2041 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2042 if (CaseSize == 0) break; 2043 2044 uint16_t Opc = MatcherTable[MatcherIndex++]; 2045 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2046 2047 // If the opcode matches, then we will execute this case. 2048 if (CurNodeOpcode == Opc) 2049 break; 2050 2051 // Otherwise, skip over this case. 2052 MatcherIndex += CaseSize; 2053 } 2054 2055 // If no cases matched, bail out. 2056 if (CaseSize == 0) break; 2057 2058 // Otherwise, execute the case we found. 2059 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2060 << " to " << MatcherIndex << "\n"); 2061 continue; 2062 } 2063 2064 case OPC_SwitchType: { 2065 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2066 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2067 unsigned CaseSize; 2068 while (1) { 2069 // Get the size of this case. 2070 CaseSize = MatcherTable[MatcherIndex++]; 2071 if (CaseSize & 128) 2072 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2073 if (CaseSize == 0) break; 2074 2075 MVT::SimpleValueType CaseVT = 2076 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2077 if (CaseVT == MVT::iPTR) 2078 CaseVT = TLI.getPointerTy().SimpleTy; 2079 2080 // If the VT matches, then we will execute this case. 2081 if (CurNodeVT == CaseVT) 2082 break; 2083 2084 // Otherwise, skip over this case. 2085 MatcherIndex += CaseSize; 2086 } 2087 2088 // If no cases matched, bail out. 2089 if (CaseSize == 0) break; 2090 2091 // Otherwise, execute the case we found. 2092 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2093 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2094 continue; 2095 } 2096 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2097 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2098 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2099 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2100 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2101 Opcode-OPC_CheckChild0Type)) 2102 break; 2103 continue; 2104 case OPC_CheckCondCode: 2105 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2106 continue; 2107 case OPC_CheckValueType: 2108 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2109 continue; 2110 case OPC_CheckInteger: 2111 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2112 continue; 2113 case OPC_CheckAndImm: 2114 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2115 continue; 2116 case OPC_CheckOrImm: 2117 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2118 continue; 2119 2120 case OPC_CheckFoldableChainNode: { 2121 assert(NodeStack.size() != 1 && "No parent node"); 2122 // Verify that all intermediate nodes between the root and this one have 2123 // a single use. 2124 bool HasMultipleUses = false; 2125 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2126 if (!NodeStack[i].hasOneUse()) { 2127 HasMultipleUses = true; 2128 break; 2129 } 2130 if (HasMultipleUses) break; 2131 2132 // Check to see that the target thinks this is profitable to fold and that 2133 // we can fold it without inducing cycles in the graph. 2134 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2135 NodeToMatch) || 2136 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2137 NodeToMatch, OptLevel, 2138 true/*We validate our own chains*/)) 2139 break; 2140 2141 continue; 2142 } 2143 case OPC_EmitInteger: { 2144 MVT::SimpleValueType VT = 2145 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2146 int64_t Val = MatcherTable[MatcherIndex++]; 2147 if (Val & 128) 2148 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2149 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2150 continue; 2151 } 2152 case OPC_EmitRegister: { 2153 MVT::SimpleValueType VT = 2154 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2155 unsigned RegNo = MatcherTable[MatcherIndex++]; 2156 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2157 continue; 2158 } 2159 2160 case OPC_EmitConvertToTarget: { 2161 // Convert from IMM/FPIMM to target version. 2162 unsigned RecNo = MatcherTable[MatcherIndex++]; 2163 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2164 SDValue Imm = RecordedNodes[RecNo]; 2165 2166 if (Imm->getOpcode() == ISD::Constant) { 2167 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2168 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2169 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2170 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2171 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2172 } 2173 2174 RecordedNodes.push_back(Imm); 2175 continue; 2176 } 2177 2178 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2179 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2180 // These are space-optimized forms of OPC_EmitMergeInputChains. 2181 assert(InputChain.getNode() == 0 && 2182 "EmitMergeInputChains should be the first chain producing node"); 2183 assert(ChainNodesMatched.empty() && 2184 "Should only have one EmitMergeInputChains per match"); 2185 2186 // Read all of the chained nodes. 2187 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2188 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2189 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2190 2191 // FIXME: What if other value results of the node have uses not matched 2192 // by this pattern? 2193 if (ChainNodesMatched.back() != NodeToMatch && 2194 !RecordedNodes[RecNo].hasOneUse()) { 2195 ChainNodesMatched.clear(); 2196 break; 2197 } 2198 2199 // Merge the input chains if they are not intra-pattern references. 2200 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2201 2202 if (InputChain.getNode() == 0) 2203 break; // Failed to merge. 2204 continue; 2205 } 2206 2207 case OPC_EmitMergeInputChains: { 2208 assert(InputChain.getNode() == 0 && 2209 "EmitMergeInputChains should be the first chain producing node"); 2210 // This node gets a list of nodes we matched in the input that have 2211 // chains. We want to token factor all of the input chains to these nodes 2212 // together. However, if any of the input chains is actually one of the 2213 // nodes matched in this pattern, then we have an intra-match reference. 2214 // Ignore these because the newly token factored chain should not refer to 2215 // the old nodes. 2216 unsigned NumChains = MatcherTable[MatcherIndex++]; 2217 assert(NumChains != 0 && "Can't TF zero chains"); 2218 2219 assert(ChainNodesMatched.empty() && 2220 "Should only have one EmitMergeInputChains per match"); 2221 2222 // Read all of the chained nodes. 2223 for (unsigned i = 0; i != NumChains; ++i) { 2224 unsigned RecNo = MatcherTable[MatcherIndex++]; 2225 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2226 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2227 2228 // FIXME: What if other value results of the node have uses not matched 2229 // by this pattern? 2230 if (ChainNodesMatched.back() != NodeToMatch && 2231 !RecordedNodes[RecNo].hasOneUse()) { 2232 ChainNodesMatched.clear(); 2233 break; 2234 } 2235 } 2236 2237 // If the inner loop broke out, the match fails. 2238 if (ChainNodesMatched.empty()) 2239 break; 2240 2241 // Merge the input chains if they are not intra-pattern references. 2242 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2243 2244 if (InputChain.getNode() == 0) 2245 break; // Failed to merge. 2246 2247 continue; 2248 } 2249 2250 case OPC_EmitCopyToReg: { 2251 unsigned RecNo = MatcherTable[MatcherIndex++]; 2252 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2253 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2254 2255 if (InputChain.getNode() == 0) 2256 InputChain = CurDAG->getEntryNode(); 2257 2258 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2259 DestPhysReg, RecordedNodes[RecNo], 2260 InputFlag); 2261 2262 InputFlag = InputChain.getValue(1); 2263 continue; 2264 } 2265 2266 case OPC_EmitNodeXForm: { 2267 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2268 unsigned RecNo = MatcherTable[MatcherIndex++]; 2269 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2270 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2271 continue; 2272 } 2273 2274 case OPC_EmitNode: 2275 case OPC_MorphNodeTo: { 2276 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2277 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2278 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2279 // Get the result VT list. 2280 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2281 SmallVector<EVT, 4> VTs; 2282 for (unsigned i = 0; i != NumVTs; ++i) { 2283 MVT::SimpleValueType VT = 2284 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2285 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2286 VTs.push_back(VT); 2287 } 2288 2289 if (EmitNodeInfo & OPFL_Chain) 2290 VTs.push_back(MVT::Other); 2291 if (EmitNodeInfo & OPFL_FlagOutput) 2292 VTs.push_back(MVT::Flag); 2293 2294 // This is hot code, so optimize the two most common cases of 1 and 2 2295 // results. 2296 SDVTList VTList; 2297 if (VTs.size() == 1) 2298 VTList = CurDAG->getVTList(VTs[0]); 2299 else if (VTs.size() == 2) 2300 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2301 else 2302 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2303 2304 // Get the operand list. 2305 unsigned NumOps = MatcherTable[MatcherIndex++]; 2306 SmallVector<SDValue, 8> Ops; 2307 for (unsigned i = 0; i != NumOps; ++i) { 2308 unsigned RecNo = MatcherTable[MatcherIndex++]; 2309 if (RecNo & 128) 2310 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2311 2312 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2313 Ops.push_back(RecordedNodes[RecNo]); 2314 } 2315 2316 // If there are variadic operands to add, handle them now. 2317 if (EmitNodeInfo & OPFL_VariadicInfo) { 2318 // Determine the start index to copy from. 2319 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2320 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2321 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2322 "Invalid variadic node"); 2323 // Copy all of the variadic operands, not including a potential flag 2324 // input. 2325 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2326 i != e; ++i) { 2327 SDValue V = NodeToMatch->getOperand(i); 2328 if (V.getValueType() == MVT::Flag) break; 2329 Ops.push_back(V); 2330 } 2331 } 2332 2333 // If this has chain/flag inputs, add them. 2334 if (EmitNodeInfo & OPFL_Chain) 2335 Ops.push_back(InputChain); 2336 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2337 Ops.push_back(InputFlag); 2338 2339 // Create the node. 2340 SDNode *Res = 0; 2341 if (Opcode != OPC_MorphNodeTo) { 2342 // If this is a normal EmitNode command, just create the new node and 2343 // add the results to the RecordedNodes list. 2344 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2345 VTList, Ops.data(), Ops.size()); 2346 2347 // Add all the non-flag/non-chain results to the RecordedNodes list. 2348 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2349 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2350 RecordedNodes.push_back(SDValue(Res, i)); 2351 } 2352 2353 } else { 2354 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2355 EmitNodeInfo); 2356 } 2357 2358 // If the node had chain/flag results, update our notion of the current 2359 // chain and flag. 2360 if (EmitNodeInfo & OPFL_FlagOutput) { 2361 InputFlag = SDValue(Res, VTs.size()-1); 2362 if (EmitNodeInfo & OPFL_Chain) 2363 InputChain = SDValue(Res, VTs.size()-2); 2364 } else if (EmitNodeInfo & OPFL_Chain) 2365 InputChain = SDValue(Res, VTs.size()-1); 2366 2367 // If the OPFL_MemRefs flag is set on this node, slap all of the 2368 // accumulated memrefs onto it. 2369 // 2370 // FIXME: This is vastly incorrect for patterns with multiple outputs 2371 // instructions that access memory and for ComplexPatterns that match 2372 // loads. 2373 if (EmitNodeInfo & OPFL_MemRefs) { 2374 MachineSDNode::mmo_iterator MemRefs = 2375 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2376 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2377 cast<MachineSDNode>(Res) 2378 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2379 } 2380 2381 DEBUG(errs() << " " 2382 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2383 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2384 2385 // If this was a MorphNodeTo then we're completely done! 2386 if (Opcode == OPC_MorphNodeTo) { 2387 // Update chain and flag uses. 2388 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2389 InputFlag, FlagResultNodesMatched, true); 2390 return Res; 2391 } 2392 2393 continue; 2394 } 2395 2396 case OPC_MarkFlagResults: { 2397 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2398 2399 // Read and remember all the flag-result nodes. 2400 for (unsigned i = 0; i != NumNodes; ++i) { 2401 unsigned RecNo = MatcherTable[MatcherIndex++]; 2402 if (RecNo & 128) 2403 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2404 2405 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2406 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2407 } 2408 continue; 2409 } 2410 2411 case OPC_CompleteMatch: { 2412 // The match has been completed, and any new nodes (if any) have been 2413 // created. Patch up references to the matched dag to use the newly 2414 // created nodes. 2415 unsigned NumResults = MatcherTable[MatcherIndex++]; 2416 2417 for (unsigned i = 0; i != NumResults; ++i) { 2418 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2419 if (ResSlot & 128) 2420 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2421 2422 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2423 SDValue Res = RecordedNodes[ResSlot]; 2424 2425 assert(i < NodeToMatch->getNumValues() && 2426 NodeToMatch->getValueType(i) != MVT::Other && 2427 NodeToMatch->getValueType(i) != MVT::Flag && 2428 "Invalid number of results to complete!"); 2429 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2430 NodeToMatch->getValueType(i) == MVT::iPTR || 2431 Res.getValueType() == MVT::iPTR || 2432 NodeToMatch->getValueType(i).getSizeInBits() == 2433 Res.getValueType().getSizeInBits()) && 2434 "invalid replacement"); 2435 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2436 } 2437 2438 // If the root node defines a flag, add it to the flag nodes to update 2439 // list. 2440 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2441 FlagResultNodesMatched.push_back(NodeToMatch); 2442 2443 // Update chain and flag uses. 2444 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2445 InputFlag, FlagResultNodesMatched, false); 2446 2447 assert(NodeToMatch->use_empty() && 2448 "Didn't replace all uses of the node?"); 2449 2450 // FIXME: We just return here, which interacts correctly with SelectRoot 2451 // above. We should fix this to not return an SDNode* anymore. 2452 return 0; 2453 } 2454 } 2455 2456 // If the code reached this point, then the match failed. See if there is 2457 // another child to try in the current 'Scope', otherwise pop it until we 2458 // find a case to check. 2459 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2460 ++NumDAGIselRetries; 2461 while (1) { 2462 if (MatchScopes.empty()) { 2463 CannotYetSelect(NodeToMatch); 2464 return 0; 2465 } 2466 2467 // Restore the interpreter state back to the point where the scope was 2468 // formed. 2469 MatchScope &LastScope = MatchScopes.back(); 2470 RecordedNodes.resize(LastScope.NumRecordedNodes); 2471 NodeStack.clear(); 2472 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2473 N = NodeStack.back(); 2474 2475 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2476 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2477 MatcherIndex = LastScope.FailIndex; 2478 2479 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2480 2481 InputChain = LastScope.InputChain; 2482 InputFlag = LastScope.InputFlag; 2483 if (!LastScope.HasChainNodesMatched) 2484 ChainNodesMatched.clear(); 2485 if (!LastScope.HasFlagResultNodesMatched) 2486 FlagResultNodesMatched.clear(); 2487 2488 // Check to see what the offset is at the new MatcherIndex. If it is zero 2489 // we have reached the end of this scope, otherwise we have another child 2490 // in the current scope to try. 2491 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2492 if (NumToSkip & 128) 2493 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2494 2495 // If we have another child in this scope to match, update FailIndex and 2496 // try it. 2497 if (NumToSkip != 0) { 2498 LastScope.FailIndex = MatcherIndex+NumToSkip; 2499 break; 2500 } 2501 2502 // End of this scope, pop it and try the next child in the containing 2503 // scope. 2504 MatchScopes.pop_back(); 2505 } 2506 } 2507} 2508 2509 2510 2511void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2512 std::string msg; 2513 raw_string_ostream Msg(msg); 2514 Msg << "Cannot yet select: "; 2515 2516 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2517 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2518 N->getOpcode() != ISD::INTRINSIC_VOID) { 2519 N->printrFull(Msg, CurDAG); 2520 } else { 2521 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2522 unsigned iid = 2523 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2524 if (iid < Intrinsic::num_intrinsics) 2525 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2526 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2527 Msg << "target intrinsic %" << TII->getName(iid); 2528 else 2529 Msg << "unknown intrinsic #" << iid; 2530 } 2531 report_fatal_error(Msg.str()); 2532} 2533 2534char SelectionDAGISel::ID = 0; 2535