SelectionDAGISel.cpp revision 9373beba6010dd34316a801c3a9b37ab9e048031
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "llvm/CodeGen/ScheduleDAG.h" 17#include "llvm/CallingConv.h" 18#include "llvm/Constants.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Function.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/InlineAsm.h" 23#include "llvm/Instructions.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/IntrinsicInst.h" 26#include "llvm/CodeGen/IntrinsicLowering.h" 27#include "llvm/CodeGen/MachineDebugInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachinePassRegistry.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/CodeGen/SSARegMap.h" 35#include "llvm/Target/MRegisterInfo.h" 36#include "llvm/Target/TargetData.h" 37#include "llvm/Target/TargetFrameInfo.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetLowering.h" 40#include "llvm/Target/TargetMachine.h" 41#include "llvm/Target/TargetOptions.h" 42#include "llvm/Transforms/Utils/BasicBlockUtils.h" 43#include "llvm/Support/CommandLine.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Visibility.h" 47#include <map> 48#include <set> 49#include <iostream> 50#include <algorithm> 51using namespace llvm; 52 53#ifndef NDEBUG 54static cl::opt<bool> 55ViewISelDAGs("view-isel-dags", cl::Hidden, 56 cl::desc("Pop up a window to show isel dags as they are selected")); 57static cl::opt<bool> 58ViewSchedDAGs("view-sched-dags", cl::Hidden, 59 cl::desc("Pop up a window to show sched dags as they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 62#endif 63 64namespace { 65 cl::opt<const char *, false, RegisterPassParser<RegisterScheduler> > 66 ISHeuristic("sched", 67 cl::init("default"), 68 cl::desc("Instruction schedulers available:")); 69 70 static RegisterScheduler 71 defaultListDAGScheduler("default", " Best scheduler for the target", 72 createDefaultScheduler); 73} // namespace 74 75namespace { 76 /// RegsForValue - This struct represents the physical registers that a 77 /// particular value is assigned and the type information about the value. 78 /// This is needed because values can be promoted into larger registers and 79 /// expanded into multiple smaller registers than the value. 80 struct VISIBILITY_HIDDEN RegsForValue { 81 /// Regs - This list hold the register (for legal and promoted values) 82 /// or register set (for expanded values) that the value should be assigned 83 /// to. 84 std::vector<unsigned> Regs; 85 86 /// RegVT - The value type of each register. 87 /// 88 MVT::ValueType RegVT; 89 90 /// ValueVT - The value type of the LLVM value, which may be promoted from 91 /// RegVT or made from merging the two expanded parts. 92 MVT::ValueType ValueVT; 93 94 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 95 96 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 97 : RegVT(regvt), ValueVT(valuevt) { 98 Regs.push_back(Reg); 99 } 100 RegsForValue(const std::vector<unsigned> ®s, 101 MVT::ValueType regvt, MVT::ValueType valuevt) 102 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 103 } 104 105 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 106 /// this value and returns the result as a ValueVT value. This uses 107 /// Chain/Flag as the input and updates them for the output Chain/Flag. 108 SDOperand getCopyFromRegs(SelectionDAG &DAG, 109 SDOperand &Chain, SDOperand &Flag) const; 110 111 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 112 /// specified value into the registers specified by this object. This uses 113 /// Chain/Flag as the input and updates them for the output Chain/Flag. 114 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 115 SDOperand &Chain, SDOperand &Flag, 116 MVT::ValueType PtrVT) const; 117 118 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 119 /// operand list. This adds the code marker and includes the number of 120 /// values added into it. 121 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 122 std::vector<SDOperand> &Ops) const; 123 }; 124} 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 131 SelectionDAG *DAG, 132 MachineBasicBlock *BB) { 133 TargetLowering &TLI = IS->getTargetLowering(); 134 135 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 136 return createTDListDAGScheduler(IS, DAG, BB); 137 } else { 138 assert(TLI.getSchedulingPreference() == 139 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 140 return createBURRListDAGScheduler(IS, DAG, BB); 141 } 142 } 143 144 145 //===--------------------------------------------------------------------===// 146 /// FunctionLoweringInfo - This contains information that is global to a 147 /// function that is used when lowering a region of the function. 148 class FunctionLoweringInfo { 149 public: 150 TargetLowering &TLI; 151 Function &Fn; 152 MachineFunction &MF; 153 SSARegMap *RegMap; 154 155 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 156 157 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 158 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 159 160 /// ValueMap - Since we emit code for the function a basic block at a time, 161 /// we must remember which virtual registers hold the values for 162 /// cross-basic-block values. 163 std::map<const Value*, unsigned> ValueMap; 164 165 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 166 /// the entry block. This allows the allocas to be efficiently referenced 167 /// anywhere in the function. 168 std::map<const AllocaInst*, int> StaticAllocaMap; 169 170 unsigned MakeReg(MVT::ValueType VT) { 171 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 172 } 173 174 unsigned CreateRegForValue(const Value *V); 175 176 unsigned InitializeRegForValue(const Value *V) { 177 unsigned &R = ValueMap[V]; 178 assert(R == 0 && "Already initialized this value register!"); 179 return R = CreateRegForValue(V); 180 } 181 }; 182} 183 184/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 185/// PHI nodes or outside of the basic block that defines it, or used by a 186/// switch instruction, which may expand to multiple basic blocks. 187static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 188 if (isa<PHINode>(I)) return true; 189 BasicBlock *BB = I->getParent(); 190 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 191 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 192 isa<SwitchInst>(*UI)) 193 return true; 194 return false; 195} 196 197/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 198/// entry block, return true. This includes arguments used by switches, since 199/// the switch may expand into multiple basic blocks. 200static bool isOnlyUsedInEntryBlock(Argument *A) { 201 BasicBlock *Entry = A->getParent()->begin(); 202 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 203 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 204 return false; // Use not in entry block. 205 return true; 206} 207 208FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 209 Function &fn, MachineFunction &mf) 210 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 211 212 // Create a vreg for each argument register that is not dead and is used 213 // outside of the entry block for the function. 214 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 215 AI != E; ++AI) 216 if (!isOnlyUsedInEntryBlock(AI)) 217 InitializeRegForValue(AI); 218 219 // Initialize the mapping of values to registers. This is only set up for 220 // instruction values that are used outside of the block that defines 221 // them. 222 Function::iterator BB = Fn.begin(), EB = Fn.end(); 223 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 224 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 225 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) { 226 const Type *Ty = AI->getAllocatedType(); 227 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 228 unsigned Align = 229 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 230 AI->getAlignment()); 231 232 // If the alignment of the value is smaller than the size of the value, 233 // and if the size of the value is particularly small (<= 8 bytes), 234 // round up to the size of the value for potentially better performance. 235 // 236 // FIXME: This could be made better with a preferred alignment hook in 237 // TargetData. It serves primarily to 8-byte align doubles for X86. 238 if (Align < TySize && TySize <= 8) Align = TySize; 239 TySize *= CUI->getValue(); // Get total allocated size. 240 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 241 StaticAllocaMap[AI] = 242 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 243 } 244 245 for (; BB != EB; ++BB) 246 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 247 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 248 if (!isa<AllocaInst>(I) || 249 !StaticAllocaMap.count(cast<AllocaInst>(I))) 250 InitializeRegForValue(I); 251 252 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 253 // also creates the initial PHI MachineInstrs, though none of the input 254 // operands are populated. 255 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 256 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 257 MBBMap[BB] = MBB; 258 MF.getBasicBlockList().push_back(MBB); 259 260 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 261 // appropriate. 262 PHINode *PN; 263 for (BasicBlock::iterator I = BB->begin(); 264 (PN = dyn_cast<PHINode>(I)); ++I) 265 if (!PN->use_empty()) { 266 MVT::ValueType VT = TLI.getValueType(PN->getType()); 267 unsigned NumElements; 268 if (VT != MVT::Vector) 269 NumElements = TLI.getNumElements(VT); 270 else { 271 MVT::ValueType VT1,VT2; 272 NumElements = 273 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 274 VT1, VT2); 275 } 276 unsigned PHIReg = ValueMap[PN]; 277 assert(PHIReg &&"PHI node does not have an assigned virtual register!"); 278 for (unsigned i = 0; i != NumElements; ++i) 279 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i); 280 } 281 } 282} 283 284/// CreateRegForValue - Allocate the appropriate number of virtual registers of 285/// the correctly promoted or expanded types. Assign these registers 286/// consecutive vreg numbers and return the first assigned number. 287unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 288 MVT::ValueType VT = TLI.getValueType(V->getType()); 289 290 // The number of multiples of registers that we need, to, e.g., split up 291 // a <2 x int64> -> 4 x i32 registers. 292 unsigned NumVectorRegs = 1; 293 294 // If this is a packed type, figure out what type it will decompose into 295 // and how many of the elements it will use. 296 if (VT == MVT::Vector) { 297 const PackedType *PTy = cast<PackedType>(V->getType()); 298 unsigned NumElts = PTy->getNumElements(); 299 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 300 301 // Divide the input until we get to a supported size. This will always 302 // end with a scalar if the target doesn't support vectors. 303 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { 304 NumElts >>= 1; 305 NumVectorRegs <<= 1; 306 } 307 if (NumElts == 1) 308 VT = EltTy; 309 else 310 VT = getVectorType(EltTy, NumElts); 311 } 312 313 // The common case is that we will only create one register for this 314 // value. If we have that case, create and return the virtual register. 315 unsigned NV = TLI.getNumElements(VT); 316 if (NV == 1) { 317 // If we are promoting this value, pick the next largest supported type. 318 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 319 unsigned Reg = MakeReg(PromotedType); 320 // If this is a vector of supported or promoted types (e.g. 4 x i16), 321 // create all of the registers. 322 for (unsigned i = 1; i != NumVectorRegs; ++i) 323 MakeReg(PromotedType); 324 return Reg; 325 } 326 327 // If this value is represented with multiple target registers, make sure 328 // to create enough consecutive registers of the right (smaller) type. 329 unsigned NT = VT-1; // Find the type to use. 330 while (TLI.getNumElements((MVT::ValueType)NT) != 1) 331 --NT; 332 333 unsigned R = MakeReg((MVT::ValueType)NT); 334 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 335 MakeReg((MVT::ValueType)NT); 336 return R; 337} 338 339//===----------------------------------------------------------------------===// 340/// SelectionDAGLowering - This is the common target-independent lowering 341/// implementation that is parameterized by a TargetLowering object. 342/// Also, targets can overload any lowering method. 343/// 344namespace llvm { 345class SelectionDAGLowering { 346 MachineBasicBlock *CurMBB; 347 348 std::map<const Value*, SDOperand> NodeMap; 349 350 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 351 /// them up and then emit token factor nodes when possible. This allows us to 352 /// get simple disambiguation between loads without worrying about alias 353 /// analysis. 354 std::vector<SDOperand> PendingLoads; 355 356 /// Case - A pair of values to record the Value for a switch case, and the 357 /// case's target basic block. 358 typedef std::pair<Constant*, MachineBasicBlock*> Case; 359 typedef std::vector<Case>::iterator CaseItr; 360 typedef std::pair<CaseItr, CaseItr> CaseRange; 361 362 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 363 /// of conditional branches. 364 struct CaseRec { 365 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 366 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 367 368 /// CaseBB - The MBB in which to emit the compare and branch 369 MachineBasicBlock *CaseBB; 370 /// LT, GE - If nonzero, we know the current case value must be less-than or 371 /// greater-than-or-equal-to these Constants. 372 Constant *LT; 373 Constant *GE; 374 /// Range - A pair of iterators representing the range of case values to be 375 /// processed at this point in the binary search tree. 376 CaseRange Range; 377 }; 378 379 /// The comparison function for sorting Case values. 380 struct CaseCmp { 381 bool operator () (const Case& C1, const Case& C2) { 382 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first)) 383 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue(); 384 385 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first); 386 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue(); 387 } 388 }; 389 390public: 391 // TLI - This is information that describes the available target features we 392 // need for lowering. This indicates when operations are unavailable, 393 // implemented with a libcall, etc. 394 TargetLowering &TLI; 395 SelectionDAG &DAG; 396 const TargetData *TD; 397 398 /// SwitchCases - Vector of CaseBlock structures used to communicate 399 /// SwitchInst code generation information. 400 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 401 SelectionDAGISel::JumpTable JT; 402 403 /// FuncInfo - Information about the function as a whole. 404 /// 405 FunctionLoweringInfo &FuncInfo; 406 407 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 408 FunctionLoweringInfo &funcinfo) 409 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 410 JT(0,0,0,0), FuncInfo(funcinfo) { 411 } 412 413 /// getRoot - Return the current virtual root of the Selection DAG. 414 /// 415 SDOperand getRoot() { 416 if (PendingLoads.empty()) 417 return DAG.getRoot(); 418 419 if (PendingLoads.size() == 1) { 420 SDOperand Root = PendingLoads[0]; 421 DAG.setRoot(Root); 422 PendingLoads.clear(); 423 return Root; 424 } 425 426 // Otherwise, we have to make a token factor node. 427 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads); 428 PendingLoads.clear(); 429 DAG.setRoot(Root); 430 return Root; 431 } 432 433 void visit(Instruction &I) { visit(I.getOpcode(), I); } 434 435 void visit(unsigned Opcode, User &I) { 436 switch (Opcode) { 437 default: assert(0 && "Unknown instruction type encountered!"); 438 abort(); 439 // Build the switch statement using the Instruction.def file. 440#define HANDLE_INST(NUM, OPCODE, CLASS) \ 441 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 442#include "llvm/Instruction.def" 443 } 444 } 445 446 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 447 448 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 449 SDOperand SrcValue, SDOperand Root, 450 bool isVolatile); 451 452 SDOperand getIntPtrConstant(uint64_t Val) { 453 return DAG.getConstant(Val, TLI.getPointerTy()); 454 } 455 456 SDOperand getValue(const Value *V); 457 458 const SDOperand &setValue(const Value *V, SDOperand NewN) { 459 SDOperand &N = NodeMap[V]; 460 assert(N.Val == 0 && "Already set a value for this node!"); 461 return N = NewN; 462 } 463 464 RegsForValue GetRegistersForValue(const std::string &ConstrCode, 465 MVT::ValueType VT, 466 bool OutReg, bool InReg, 467 std::set<unsigned> &OutputRegs, 468 std::set<unsigned> &InputRegs); 469 470 // Terminator instructions. 471 void visitRet(ReturnInst &I); 472 void visitBr(BranchInst &I); 473 void visitSwitch(SwitchInst &I); 474 void visitUnreachable(UnreachableInst &I) { /* noop */ } 475 476 // Helper for visitSwitch 477 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 478 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 479 480 // These all get lowered before this pass. 481 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); } 482 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); } 483 484 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp); 485 void visitShift(User &I, unsigned Opcode); 486 void visitAdd(User &I) { 487 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD); 488 } 489 void visitSub(User &I); 490 void visitMul(User &I) { 491 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL); 492 } 493 void visitDiv(User &I) { 494 const Type *Ty = I.getType(); 495 visitBinary(I, 496 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV, 497 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV); 498 } 499 void visitRem(User &I) { 500 const Type *Ty = I.getType(); 501 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0); 502 } 503 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); } 504 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); } 505 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); } 506 void visitShl(User &I) { visitShift(I, ISD::SHL); } 507 void visitShr(User &I) { 508 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA); 509 } 510 511 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc, 512 ISD::CondCode FPOpc); 513 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ, 514 ISD::SETOEQ); } 515 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE, 516 ISD::SETUNE); } 517 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE, 518 ISD::SETOLE); } 519 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE, 520 ISD::SETOGE); } 521 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT, 522 ISD::SETOLT); } 523 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT, 524 ISD::SETOGT); } 525 526 void visitExtractElement(User &I); 527 void visitInsertElement(User &I); 528 void visitShuffleVector(User &I); 529 530 void visitGetElementPtr(User &I); 531 void visitCast(User &I); 532 void visitSelect(User &I); 533 534 void visitMalloc(MallocInst &I); 535 void visitFree(FreeInst &I); 536 void visitAlloca(AllocaInst &I); 537 void visitLoad(LoadInst &I); 538 void visitStore(StoreInst &I); 539 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 540 void visitCall(CallInst &I); 541 void visitInlineAsm(CallInst &I); 542 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 543 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 544 545 void visitVAStart(CallInst &I); 546 void visitVAArg(VAArgInst &I); 547 void visitVAEnd(CallInst &I); 548 void visitVACopy(CallInst &I); 549 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress); 550 551 void visitMemIntrinsic(CallInst &I, unsigned Op); 552 553 void visitUserOp1(Instruction &I) { 554 assert(0 && "UserOp1 should not exist at instruction selection time!"); 555 abort(); 556 } 557 void visitUserOp2(Instruction &I) { 558 assert(0 && "UserOp2 should not exist at instruction selection time!"); 559 abort(); 560 } 561}; 562} // end namespace llvm 563 564SDOperand SelectionDAGLowering::getValue(const Value *V) { 565 SDOperand &N = NodeMap[V]; 566 if (N.Val) return N; 567 568 const Type *VTy = V->getType(); 569 MVT::ValueType VT = TLI.getValueType(VTy); 570 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 571 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 572 visit(CE->getOpcode(), *CE); 573 assert(N.Val && "visit didn't populate the ValueMap!"); 574 return N; 575 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 576 return N = DAG.getGlobalAddress(GV, VT); 577 } else if (isa<ConstantPointerNull>(C)) { 578 return N = DAG.getConstant(0, TLI.getPointerTy()); 579 } else if (isa<UndefValue>(C)) { 580 if (!isa<PackedType>(VTy)) 581 return N = DAG.getNode(ISD::UNDEF, VT); 582 583 // Create a VBUILD_VECTOR of undef nodes. 584 const PackedType *PTy = cast<PackedType>(VTy); 585 unsigned NumElements = PTy->getNumElements(); 586 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 587 588 std::vector<SDOperand> Ops; 589 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 590 591 // Create a VConstant node with generic Vector type. 592 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 593 Ops.push_back(DAG.getValueType(PVT)); 594 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 595 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 596 return N = DAG.getConstantFP(CFP->getValue(), VT); 597 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) { 598 unsigned NumElements = PTy->getNumElements(); 599 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 600 601 // Now that we know the number and type of the elements, push a 602 // Constant or ConstantFP node onto the ops list for each element of 603 // the packed constant. 604 std::vector<SDOperand> Ops; 605 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) { 606 for (unsigned i = 0; i != NumElements; ++i) 607 Ops.push_back(getValue(CP->getOperand(i))); 608 } else { 609 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 610 SDOperand Op; 611 if (MVT::isFloatingPoint(PVT)) 612 Op = DAG.getConstantFP(0, PVT); 613 else 614 Op = DAG.getConstant(0, PVT); 615 Ops.assign(NumElements, Op); 616 } 617 618 // Create a VBUILD_VECTOR node with generic Vector type. 619 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 620 Ops.push_back(DAG.getValueType(PVT)); 621 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 622 } else { 623 // Canonicalize all constant ints to be unsigned. 624 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT); 625 } 626 } 627 628 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 629 std::map<const AllocaInst*, int>::iterator SI = 630 FuncInfo.StaticAllocaMap.find(AI); 631 if (SI != FuncInfo.StaticAllocaMap.end()) 632 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 633 } 634 635 std::map<const Value*, unsigned>::const_iterator VMI = 636 FuncInfo.ValueMap.find(V); 637 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); 638 639 unsigned InReg = VMI->second; 640 641 // If this type is not legal, make it so now. 642 if (VT != MVT::Vector) { 643 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 644 645 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 646 if (DestVT < VT) { 647 // Source must be expanded. This input value is actually coming from the 648 // register pair VMI->second and VMI->second+1. 649 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 650 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 651 } else if (DestVT > VT) { // Promotion case 652 if (MVT::isFloatingPoint(VT)) 653 N = DAG.getNode(ISD::FP_ROUND, VT, N); 654 else 655 N = DAG.getNode(ISD::TRUNCATE, VT, N); 656 } 657 } else { 658 // Otherwise, if this is a vector, make it available as a generic vector 659 // here. 660 MVT::ValueType PTyElementVT, PTyLegalElementVT; 661 const PackedType *PTy = cast<PackedType>(VTy); 662 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT, 663 PTyLegalElementVT); 664 665 // Build a VBUILD_VECTOR with the input registers. 666 std::vector<SDOperand> Ops; 667 if (PTyElementVT == PTyLegalElementVT) { 668 // If the value types are legal, just VBUILD the CopyFromReg nodes. 669 for (unsigned i = 0; i != NE; ++i) 670 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 671 PTyElementVT)); 672 } else if (PTyElementVT < PTyLegalElementVT) { 673 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate. 674 for (unsigned i = 0; i != NE; ++i) { 675 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 676 PTyElementVT); 677 if (MVT::isFloatingPoint(PTyElementVT)) 678 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 679 else 680 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 681 Ops.push_back(Op); 682 } 683 } else { 684 // If the register was expanded, use BUILD_PAIR. 685 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 686 for (unsigned i = 0; i != NE/2; ++i) { 687 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 688 PTyElementVT); 689 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 690 PTyElementVT); 691 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); 692 } 693 } 694 695 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 696 Ops.push_back(DAG.getValueType(PTyLegalElementVT)); 697 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 698 699 // Finally, use a VBIT_CONVERT to make this available as the appropriate 700 // vector type. 701 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 702 DAG.getConstant(PTy->getNumElements(), 703 MVT::i32), 704 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 705 } 706 707 return N; 708} 709 710 711void SelectionDAGLowering::visitRet(ReturnInst &I) { 712 if (I.getNumOperands() == 0) { 713 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 714 return; 715 } 716 std::vector<SDOperand> NewValues; 717 NewValues.push_back(getRoot()); 718 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 719 SDOperand RetOp = getValue(I.getOperand(i)); 720 bool isSigned = I.getOperand(i)->getType()->isSigned(); 721 722 // If this is an integer return value, we need to promote it ourselves to 723 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 724 // than sign/zero. 725 // FIXME: C calling convention requires the return type to be promoted to 726 // at least 32-bit. But this is not necessary for non-C calling conventions. 727 if (MVT::isInteger(RetOp.getValueType()) && 728 RetOp.getValueType() < MVT::i64) { 729 MVT::ValueType TmpVT; 730 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 731 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 732 else 733 TmpVT = MVT::i32; 734 735 if (isSigned) 736 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp); 737 else 738 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp); 739 } 740 NewValues.push_back(RetOp); 741 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32)); 742 } 743 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues)); 744} 745 746void SelectionDAGLowering::visitBr(BranchInst &I) { 747 // Update machine-CFG edges. 748 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 749 CurMBB->addSuccessor(Succ0MBB); 750 751 // Figure out which block is immediately after the current one. 752 MachineBasicBlock *NextBlock = 0; 753 MachineFunction::iterator BBI = CurMBB; 754 if (++BBI != CurMBB->getParent()->end()) 755 NextBlock = BBI; 756 757 if (I.isUnconditional()) { 758 // If this is not a fall-through branch, emit the branch. 759 if (Succ0MBB != NextBlock) 760 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 761 DAG.getBasicBlock(Succ0MBB))); 762 } else { 763 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 764 CurMBB->addSuccessor(Succ1MBB); 765 766 SDOperand Cond = getValue(I.getCondition()); 767 if (Succ1MBB == NextBlock) { 768 // If the condition is false, fall through. This means we should branch 769 // if the condition is true to Succ #0. 770 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 771 Cond, DAG.getBasicBlock(Succ0MBB))); 772 } else if (Succ0MBB == NextBlock) { 773 // If the condition is true, fall through. This means we should branch if 774 // the condition is false to Succ #1. Invert the condition first. 775 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 776 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 777 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 778 Cond, DAG.getBasicBlock(Succ1MBB))); 779 } else { 780 std::vector<SDOperand> Ops; 781 Ops.push_back(getRoot()); 782 // If the false case is the current basic block, then this is a self 783 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it 784 // adds an extra instruction in the loop. Instead, invert the 785 // condition and emit "Loop: ... br!cond Loop; br Out. 786 if (CurMBB == Succ1MBB) { 787 std::swap(Succ0MBB, Succ1MBB); 788 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 789 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 790 } 791 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 792 DAG.getBasicBlock(Succ0MBB)); 793 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True, 794 DAG.getBasicBlock(Succ1MBB))); 795 } 796 } 797} 798 799/// visitSwitchCase - Emits the necessary code to represent a single node in 800/// the binary search tree resulting from lowering a switch instruction. 801void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 802 SDOperand SwitchOp = getValue(CB.SwitchV); 803 SDOperand CaseOp = getValue(CB.CaseC); 804 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC); 805 806 // Set NextBlock to be the MBB immediately after the current one, if any. 807 // This is used to avoid emitting unnecessary branches to the next block. 808 MachineBasicBlock *NextBlock = 0; 809 MachineFunction::iterator BBI = CurMBB; 810 if (++BBI != CurMBB->getParent()->end()) 811 NextBlock = BBI; 812 813 // If the lhs block is the next block, invert the condition so that we can 814 // fall through to the lhs instead of the rhs block. 815 if (CB.LHSBB == NextBlock) { 816 std::swap(CB.LHSBB, CB.RHSBB); 817 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 818 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 819 } 820 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 821 DAG.getBasicBlock(CB.LHSBB)); 822 if (CB.RHSBB == NextBlock) 823 DAG.setRoot(BrCond); 824 else 825 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 826 DAG.getBasicBlock(CB.RHSBB))); 827 // Update successor info 828 CurMBB->addSuccessor(CB.LHSBB); 829 CurMBB->addSuccessor(CB.RHSBB); 830} 831 832/// visitSwitchCase - Emits the necessary code to represent a single node in 833/// the binary search tree resulting from lowering a switch instruction. 834void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 835 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically, 836 // we need to add the address of the jump table to the value loaded, since 837 // the entries in the jump table will be differences rather than absolute 838 // addresses. 839 840 // Emit the code for the jump table 841 MVT::ValueType PTy = TLI.getPointerTy(); 842 assert((PTy == MVT::i32 || PTy == MVT::i64) && 843 "Jump table entries are 32-bit values"); 844 // PIC jump table entries are 32-bit values. 845 unsigned EntrySize = 846 (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 847 ? 4 : MVT::getSizeInBits(PTy)/8; 848 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 849 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy, 850 DAG.getConstant(EntrySize, PTy)); 851 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy); 852 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB); 853 SDOperand LD = DAG.getLoad(MVT::i32, Copy.getValue(1), ADD, 854 DAG.getSrcValue(0)); 855 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 856 ADD = DAG.getNode(ISD::ADD, PTy, 857 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), TAB); 858 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD)); 859 } else { 860 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD)); 861 } 862} 863 864void SelectionDAGLowering::visitSwitch(SwitchInst &I) { 865 // Figure out which block is immediately after the current one. 866 MachineBasicBlock *NextBlock = 0; 867 MachineFunction::iterator BBI = CurMBB; 868 if (++BBI != CurMBB->getParent()->end()) 869 NextBlock = BBI; 870 871 // If there is only the default destination, branch to it if it is not the 872 // next basic block. Otherwise, just fall through. 873 if (I.getNumOperands() == 2) { 874 // Update machine-CFG edges. 875 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()]; 876 // If this is not a fall-through branch, emit the branch. 877 if (DefaultMBB != NextBlock) 878 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 879 DAG.getBasicBlock(DefaultMBB))); 880 CurMBB->addSuccessor(DefaultMBB); 881 return; 882 } 883 884 // If there are any non-default case statements, create a vector of Cases 885 // representing each one, and sort the vector so that we can efficiently 886 // create a binary search tree from them. 887 std::vector<Case> Cases; 888 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) { 889 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)]; 890 Cases.push_back(Case(I.getSuccessorValue(i), SMBB)); 891 } 892 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 893 894 // Get the Value to be switched on and default basic blocks, which will be 895 // inserted into CaseBlock records, representing basic blocks in the binary 896 // search tree. 897 Value *SV = I.getOperand(0); 898 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()]; 899 900 // Get the MachineFunction which holds the current MBB. This is used during 901 // emission of jump tables, and when inserting any additional MBBs necessary 902 // to represent the switch. 903 MachineFunction *CurMF = CurMBB->getParent(); 904 const BasicBlock *LLVMBB = CurMBB->getBasicBlock(); 905 906 // If the switch has more than 5 blocks, and at least 31.25% dense, and the 907 // target supports indirect branches, then emit a jump table rather than 908 // lowering the switch to a binary tree of conditional branches. 909 // FIXME: Make this work with PIC code 910 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) && 911 Cases.size() > 5) { 912 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue(); 913 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue(); 914 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL); 915 916 if (Density >= 0.3125) { 917 // Create a new basic block to hold the code for loading the address 918 // of the jump table, and jumping to it. Update successor information; 919 // we will either branch to the default case for the switch, or the jump 920 // table. 921 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 922 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 923 CurMBB->addSuccessor(Default); 924 CurMBB->addSuccessor(JumpTableBB); 925 926 // Subtract the lowest switch case value from the value being switched on 927 // and conditional branch to default mbb if the result is greater than the 928 // difference between smallest and largest cases. 929 SDOperand SwitchOp = getValue(SV); 930 MVT::ValueType VT = SwitchOp.getValueType(); 931 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 932 DAG.getConstant(First, VT)); 933 934 // The SDNode we just created, which holds the value being switched on 935 // minus the the smallest case value, needs to be copied to a virtual 936 // register so it can be used as an index into the jump table in a 937 // subsequent basic block. This value may be smaller or larger than the 938 // target's pointer type, and therefore require extension or truncating. 939 if (VT > TLI.getPointerTy()) 940 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 941 else 942 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 943 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 944 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 945 946 // Emit the range check for the jump table, and branch to the default 947 // block for the switch statement if the value being switched on exceeds 948 // the largest case in the switch. 949 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 950 DAG.getConstant(Last-First,VT), ISD::SETUGT); 951 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 952 DAG.getBasicBlock(Default))); 953 954 // Build a vector of destination BBs, corresponding to each target 955 // of the jump table. If the value of the jump table slot corresponds to 956 // a case statement, push the case's BB onto the vector, otherwise, push 957 // the default BB. 958 std::set<MachineBasicBlock*> UniqueBBs; 959 std::vector<MachineBasicBlock*> DestBBs; 960 uint64_t TEI = First; 961 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) { 962 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) { 963 DestBBs.push_back(ii->second); 964 UniqueBBs.insert(ii->second); 965 ++ii; 966 } else { 967 DestBBs.push_back(Default); 968 UniqueBBs.insert(Default); 969 } 970 } 971 972 // Update successor info 973 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(), 974 ee = UniqueBBs.end(); ii != ee; ++ii) 975 JumpTableBB->addSuccessor(*ii); 976 977 // Create a jump table index for this jump table, or return an existing 978 // one. 979 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 980 981 // Set the jump table information so that we can codegen it as a second 982 // MachineBasicBlock 983 JT.Reg = JumpTableReg; 984 JT.JTI = JTI; 985 JT.MBB = JumpTableBB; 986 JT.Default = Default; 987 return; 988 } 989 } 990 991 // Push the initial CaseRec onto the worklist 992 std::vector<CaseRec> CaseVec; 993 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 994 995 while (!CaseVec.empty()) { 996 // Grab a record representing a case range to process off the worklist 997 CaseRec CR = CaseVec.back(); 998 CaseVec.pop_back(); 999 1000 // Size is the number of Cases represented by this range. If Size is 1, 1001 // then we are processing a leaf of the binary search tree. Otherwise, 1002 // we need to pick a pivot, and push left and right ranges onto the 1003 // worklist. 1004 unsigned Size = CR.Range.second - CR.Range.first; 1005 1006 if (Size == 1) { 1007 // Create a CaseBlock record representing a conditional branch to 1008 // the Case's target mbb if the value being switched on SV is equal 1009 // to C. Otherwise, branch to default. 1010 Constant *C = CR.Range.first->first; 1011 MachineBasicBlock *Target = CR.Range.first->second; 1012 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default, 1013 CR.CaseBB); 1014 // If the MBB representing the leaf node is the current MBB, then just 1015 // call visitSwitchCase to emit the code into the current block. 1016 // Otherwise, push the CaseBlock onto the vector to be later processed 1017 // by SDISel, and insert the node's MBB before the next MBB. 1018 if (CR.CaseBB == CurMBB) 1019 visitSwitchCase(CB); 1020 else { 1021 SwitchCases.push_back(CB); 1022 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB); 1023 } 1024 } else { 1025 // split case range at pivot 1026 CaseItr Pivot = CR.Range.first + (Size / 2); 1027 CaseRange LHSR(CR.Range.first, Pivot); 1028 CaseRange RHSR(Pivot, CR.Range.second); 1029 Constant *C = Pivot->first; 1030 MachineBasicBlock *RHSBB = 0, *LHSBB = 0; 1031 // We know that we branch to the LHS if the Value being switched on is 1032 // less than the Pivot value, C. We use this to optimize our binary 1033 // tree a bit, by recognizing that if SV is greater than or equal to the 1034 // LHS's Case Value, and that Case Value is exactly one less than the 1035 // Pivot's Value, then we can branch directly to the LHS's Target, 1036 // rather than creating a leaf node for it. 1037 if ((LHSR.second - LHSR.first) == 1 && 1038 LHSR.first->first == CR.GE && 1039 cast<ConstantIntegral>(C)->getRawValue() == 1040 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) { 1041 LHSBB = LHSR.first->second; 1042 } else { 1043 LHSBB = new MachineBasicBlock(LLVMBB); 1044 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR)); 1045 } 1046 // Similar to the optimization above, if the Value being switched on is 1047 // known to be less than the Constant CR.LT, and the current Case Value 1048 // is CR.LT - 1, then we can branch directly to the target block for 1049 // the current Case Value, rather than emitting a RHS leaf node for it. 1050 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1051 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() == 1052 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) { 1053 RHSBB = RHSR.first->second; 1054 } else { 1055 RHSBB = new MachineBasicBlock(LLVMBB); 1056 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR)); 1057 } 1058 // Create a CaseBlock record representing a conditional branch to 1059 // the LHS node if the value being switched on SV is less than C. 1060 // Otherwise, branch to LHS. 1061 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT; 1062 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB); 1063 if (CR.CaseBB == CurMBB) 1064 visitSwitchCase(CB); 1065 else { 1066 SwitchCases.push_back(CB); 1067 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB); 1068 } 1069 } 1070 } 1071} 1072 1073void SelectionDAGLowering::visitSub(User &I) { 1074 // -0.0 - X --> fneg 1075 if (I.getType()->isFloatingPoint()) { 1076 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1077 if (CFP->isExactlyValue(-0.0)) { 1078 SDOperand Op2 = getValue(I.getOperand(1)); 1079 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1080 return; 1081 } 1082 } 1083 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB); 1084} 1085 1086void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp, 1087 unsigned VecOp) { 1088 const Type *Ty = I.getType(); 1089 SDOperand Op1 = getValue(I.getOperand(0)); 1090 SDOperand Op2 = getValue(I.getOperand(1)); 1091 1092 if (Ty->isIntegral()) { 1093 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2)); 1094 } else if (Ty->isFloatingPoint()) { 1095 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2)); 1096 } else { 1097 const PackedType *PTy = cast<PackedType>(Ty); 1098 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32); 1099 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType())); 1100 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ)); 1101 } 1102} 1103 1104void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1105 SDOperand Op1 = getValue(I.getOperand(0)); 1106 SDOperand Op2 = getValue(I.getOperand(1)); 1107 1108 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1109 1110 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1111} 1112 1113void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode, 1114 ISD::CondCode UnsignedOpcode, 1115 ISD::CondCode FPOpcode) { 1116 SDOperand Op1 = getValue(I.getOperand(0)); 1117 SDOperand Op2 = getValue(I.getOperand(1)); 1118 ISD::CondCode Opcode = SignedOpcode; 1119 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint()) 1120 Opcode = FPOpcode; 1121 else if (I.getOperand(0)->getType()->isUnsigned()) 1122 Opcode = UnsignedOpcode; 1123 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1124} 1125 1126void SelectionDAGLowering::visitSelect(User &I) { 1127 SDOperand Cond = getValue(I.getOperand(0)); 1128 SDOperand TrueVal = getValue(I.getOperand(1)); 1129 SDOperand FalseVal = getValue(I.getOperand(2)); 1130 if (!isa<PackedType>(I.getType())) { 1131 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 1132 TrueVal, FalseVal)); 1133 } else { 1134 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 1135 *(TrueVal.Val->op_end()-2), 1136 *(TrueVal.Val->op_end()-1))); 1137 } 1138} 1139 1140void SelectionDAGLowering::visitCast(User &I) { 1141 SDOperand N = getValue(I.getOperand(0)); 1142 MVT::ValueType SrcVT = N.getValueType(); 1143 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1144 1145 if (DestVT == MVT::Vector) { 1146 // This is a cast to a vector from something else. This is always a bit 1147 // convert. Get information about the input vector. 1148 const PackedType *DestTy = cast<PackedType>(I.getType()); 1149 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1150 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 1151 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 1152 DAG.getValueType(EltVT))); 1153 } else if (SrcVT == DestVT) { 1154 setValue(&I, N); // noop cast. 1155 } else if (DestVT == MVT::i1) { 1156 // Cast to bool is a comparison against zero, not truncation to zero. 1157 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) : 1158 DAG.getConstantFP(0.0, N.getValueType()); 1159 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE)); 1160 } else if (isInteger(SrcVT)) { 1161 if (isInteger(DestVT)) { // Int -> Int cast 1162 if (DestVT < SrcVT) // Truncating cast? 1163 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 1164 else if (I.getOperand(0)->getType()->isSigned()) 1165 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 1166 else 1167 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 1168 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast 1169 if (I.getOperand(0)->getType()->isSigned()) 1170 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 1171 else 1172 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 1173 } else { 1174 assert(0 && "Unknown cast!"); 1175 } 1176 } else if (isFloatingPoint(SrcVT)) { 1177 if (isFloatingPoint(DestVT)) { // FP -> FP cast 1178 if (DestVT < SrcVT) // Rounding cast? 1179 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 1180 else 1181 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 1182 } else if (isInteger(DestVT)) { // FP -> Int cast. 1183 if (I.getType()->isSigned()) 1184 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 1185 else 1186 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 1187 } else { 1188 assert(0 && "Unknown cast!"); 1189 } 1190 } else { 1191 assert(SrcVT == MVT::Vector && "Unknown cast!"); 1192 assert(DestVT != MVT::Vector && "Casts to vector already handled!"); 1193 // This is a cast from a vector to something else. This is always a bit 1194 // convert. Get information about the input vector. 1195 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 1196 } 1197} 1198 1199void SelectionDAGLowering::visitInsertElement(User &I) { 1200 SDOperand InVec = getValue(I.getOperand(0)); 1201 SDOperand InVal = getValue(I.getOperand(1)); 1202 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1203 getValue(I.getOperand(2))); 1204 1205 SDOperand Num = *(InVec.Val->op_end()-2); 1206 SDOperand Typ = *(InVec.Val->op_end()-1); 1207 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 1208 InVec, InVal, InIdx, Num, Typ)); 1209} 1210 1211void SelectionDAGLowering::visitExtractElement(User &I) { 1212 SDOperand InVec = getValue(I.getOperand(0)); 1213 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1214 getValue(I.getOperand(1))); 1215 SDOperand Typ = *(InVec.Val->op_end()-1); 1216 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 1217 TLI.getValueType(I.getType()), InVec, InIdx)); 1218} 1219 1220void SelectionDAGLowering::visitShuffleVector(User &I) { 1221 SDOperand V1 = getValue(I.getOperand(0)); 1222 SDOperand V2 = getValue(I.getOperand(1)); 1223 SDOperand Mask = getValue(I.getOperand(2)); 1224 1225 SDOperand Num = *(V1.Val->op_end()-2); 1226 SDOperand Typ = *(V2.Val->op_end()-1); 1227 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 1228 V1, V2, Mask, Num, Typ)); 1229} 1230 1231 1232void SelectionDAGLowering::visitGetElementPtr(User &I) { 1233 SDOperand N = getValue(I.getOperand(0)); 1234 const Type *Ty = I.getOperand(0)->getType(); 1235 1236 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 1237 OI != E; ++OI) { 1238 Value *Idx = *OI; 1239 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 1240 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 1241 if (Field) { 1242 // N = N + Offset 1243 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field]; 1244 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 1245 getIntPtrConstant(Offset)); 1246 } 1247 Ty = StTy->getElementType(Field); 1248 } else { 1249 Ty = cast<SequentialType>(Ty)->getElementType(); 1250 1251 // If this is a constant subscript, handle it quickly. 1252 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 1253 if (CI->getRawValue() == 0) continue; 1254 1255 uint64_t Offs; 1256 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI)) 1257 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); 1258 else 1259 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue(); 1260 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 1261 continue; 1262 } 1263 1264 // N = N + Idx * ElementSize; 1265 uint64_t ElementSize = TD->getTypeSize(Ty); 1266 SDOperand IdxN = getValue(Idx); 1267 1268 // If the index is smaller or larger than intptr_t, truncate or extend 1269 // it. 1270 if (IdxN.getValueType() < N.getValueType()) { 1271 if (Idx->getType()->isSigned()) 1272 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 1273 else 1274 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN); 1275 } else if (IdxN.getValueType() > N.getValueType()) 1276 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 1277 1278 // If this is a multiply by a power of two, turn it into a shl 1279 // immediately. This is a very common case. 1280 if (isPowerOf2_64(ElementSize)) { 1281 unsigned Amt = Log2_64(ElementSize); 1282 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 1283 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 1284 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1285 continue; 1286 } 1287 1288 SDOperand Scale = getIntPtrConstant(ElementSize); 1289 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 1290 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1291 } 1292 } 1293 setValue(&I, N); 1294} 1295 1296void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 1297 // If this is a fixed sized alloca in the entry block of the function, 1298 // allocate it statically on the stack. 1299 if (FuncInfo.StaticAllocaMap.count(&I)) 1300 return; // getValue will auto-populate this. 1301 1302 const Type *Ty = I.getAllocatedType(); 1303 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 1304 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 1305 I.getAlignment()); 1306 1307 SDOperand AllocSize = getValue(I.getArraySize()); 1308 MVT::ValueType IntPtr = TLI.getPointerTy(); 1309 if (IntPtr < AllocSize.getValueType()) 1310 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 1311 else if (IntPtr > AllocSize.getValueType()) 1312 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 1313 1314 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 1315 getIntPtrConstant(TySize)); 1316 1317 // Handle alignment. If the requested alignment is less than or equal to the 1318 // stack alignment, ignore it and round the size of the allocation up to the 1319 // stack alignment size. If the size is greater than the stack alignment, we 1320 // note this in the DYNAMIC_STACKALLOC node. 1321 unsigned StackAlign = 1322 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1323 if (Align <= StackAlign) { 1324 Align = 0; 1325 // Add SA-1 to the size. 1326 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 1327 getIntPtrConstant(StackAlign-1)); 1328 // Mask out the low bits for alignment purposes. 1329 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 1330 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 1331 } 1332 1333 std::vector<MVT::ValueType> VTs; 1334 VTs.push_back(AllocSize.getValueType()); 1335 VTs.push_back(MVT::Other); 1336 std::vector<SDOperand> Ops; 1337 Ops.push_back(getRoot()); 1338 Ops.push_back(AllocSize); 1339 Ops.push_back(getIntPtrConstant(Align)); 1340 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 1341 DAG.setRoot(setValue(&I, DSA).getValue(1)); 1342 1343 // Inform the Frame Information that we have just allocated a variable-sized 1344 // object. 1345 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 1346} 1347 1348void SelectionDAGLowering::visitLoad(LoadInst &I) { 1349 SDOperand Ptr = getValue(I.getOperand(0)); 1350 1351 SDOperand Root; 1352 if (I.isVolatile()) 1353 Root = getRoot(); 1354 else { 1355 // Do not serialize non-volatile loads against each other. 1356 Root = DAG.getRoot(); 1357 } 1358 1359 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)), 1360 Root, I.isVolatile())); 1361} 1362 1363SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 1364 SDOperand SrcValue, SDOperand Root, 1365 bool isVolatile) { 1366 SDOperand L; 1367 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) { 1368 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 1369 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue); 1370 } else { 1371 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue); 1372 } 1373 1374 if (isVolatile) 1375 DAG.setRoot(L.getValue(1)); 1376 else 1377 PendingLoads.push_back(L.getValue(1)); 1378 1379 return L; 1380} 1381 1382 1383void SelectionDAGLowering::visitStore(StoreInst &I) { 1384 Value *SrcV = I.getOperand(0); 1385 SDOperand Src = getValue(SrcV); 1386 SDOperand Ptr = getValue(I.getOperand(1)); 1387 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr, 1388 DAG.getSrcValue(I.getOperand(1)))); 1389} 1390 1391/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 1392/// access memory and has no other side effects at all. 1393static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 1394#define GET_NO_MEMORY_INTRINSICS 1395#include "llvm/Intrinsics.gen" 1396#undef GET_NO_MEMORY_INTRINSICS 1397 return false; 1398} 1399 1400// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 1401// have any side-effects or if it only reads memory. 1402static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 1403#define GET_SIDE_EFFECT_INFO 1404#include "llvm/Intrinsics.gen" 1405#undef GET_SIDE_EFFECT_INFO 1406 return false; 1407} 1408 1409/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 1410/// node. 1411void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 1412 unsigned Intrinsic) { 1413 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 1414 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 1415 1416 // Build the operand list. 1417 std::vector<SDOperand> Ops; 1418 if (HasChain) { // If this intrinsic has side-effects, chainify it. 1419 if (OnlyLoad) { 1420 // We don't need to serialize loads against other loads. 1421 Ops.push_back(DAG.getRoot()); 1422 } else { 1423 Ops.push_back(getRoot()); 1424 } 1425 } 1426 1427 // Add the intrinsic ID as an integer operand. 1428 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 1429 1430 // Add all operands of the call to the operand list. 1431 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1432 SDOperand Op = getValue(I.getOperand(i)); 1433 1434 // If this is a vector type, force it to the right packed type. 1435 if (Op.getValueType() == MVT::Vector) { 1436 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType()); 1437 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 1438 1439 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 1440 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 1441 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 1442 } 1443 1444 assert(TLI.isTypeLegal(Op.getValueType()) && 1445 "Intrinsic uses a non-legal type?"); 1446 Ops.push_back(Op); 1447 } 1448 1449 std::vector<MVT::ValueType> VTs; 1450 if (I.getType() != Type::VoidTy) { 1451 MVT::ValueType VT = TLI.getValueType(I.getType()); 1452 if (VT == MVT::Vector) { 1453 const PackedType *DestTy = cast<PackedType>(I.getType()); 1454 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1455 1456 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 1457 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 1458 } 1459 1460 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 1461 VTs.push_back(VT); 1462 } 1463 if (HasChain) 1464 VTs.push_back(MVT::Other); 1465 1466 // Create the node. 1467 SDOperand Result; 1468 if (!HasChain) 1469 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops); 1470 else if (I.getType() != Type::VoidTy) 1471 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops); 1472 else 1473 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops); 1474 1475 if (HasChain) { 1476 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 1477 if (OnlyLoad) 1478 PendingLoads.push_back(Chain); 1479 else 1480 DAG.setRoot(Chain); 1481 } 1482 if (I.getType() != Type::VoidTy) { 1483 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) { 1484 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 1485 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 1486 DAG.getConstant(PTy->getNumElements(), MVT::i32), 1487 DAG.getValueType(EVT)); 1488 } 1489 setValue(&I, Result); 1490 } 1491} 1492 1493/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 1494/// we want to emit this as a call to a named external function, return the name 1495/// otherwise lower it and return null. 1496const char * 1497SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 1498 switch (Intrinsic) { 1499 default: 1500 // By default, turn this into a target intrinsic node. 1501 visitTargetIntrinsic(I, Intrinsic); 1502 return 0; 1503 case Intrinsic::vastart: visitVAStart(I); return 0; 1504 case Intrinsic::vaend: visitVAEnd(I); return 0; 1505 case Intrinsic::vacopy: visitVACopy(I); return 0; 1506 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0; 1507 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0; 1508 case Intrinsic::setjmp: 1509 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 1510 break; 1511 case Intrinsic::longjmp: 1512 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 1513 break; 1514 case Intrinsic::memcpy_i32: 1515 case Intrinsic::memcpy_i64: 1516 visitMemIntrinsic(I, ISD::MEMCPY); 1517 return 0; 1518 case Intrinsic::memset_i32: 1519 case Intrinsic::memset_i64: 1520 visitMemIntrinsic(I, ISD::MEMSET); 1521 return 0; 1522 case Intrinsic::memmove_i32: 1523 case Intrinsic::memmove_i64: 1524 visitMemIntrinsic(I, ISD::MEMMOVE); 1525 return 0; 1526 1527 case Intrinsic::dbg_stoppoint: { 1528 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1529 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 1530 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) { 1531 std::vector<SDOperand> Ops; 1532 1533 Ops.push_back(getRoot()); 1534 Ops.push_back(getValue(SPI.getLineValue())); 1535 Ops.push_back(getValue(SPI.getColumnValue())); 1536 1537 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext()); 1538 assert(DD && "Not a debug information descriptor"); 1539 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 1540 1541 Ops.push_back(DAG.getString(CompileUnit->getFileName())); 1542 Ops.push_back(DAG.getString(CompileUnit->getDirectory())); 1543 1544 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops)); 1545 } 1546 1547 return 0; 1548 } 1549 case Intrinsic::dbg_region_start: { 1550 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1551 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 1552 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) { 1553 std::vector<SDOperand> Ops; 1554 1555 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext()); 1556 1557 Ops.push_back(getRoot()); 1558 Ops.push_back(DAG.getConstant(LabelID, MVT::i32)); 1559 1560 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops)); 1561 } 1562 1563 return 0; 1564 } 1565 case Intrinsic::dbg_region_end: { 1566 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1567 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 1568 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) { 1569 std::vector<SDOperand> Ops; 1570 1571 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext()); 1572 1573 Ops.push_back(getRoot()); 1574 Ops.push_back(DAG.getConstant(LabelID, MVT::i32)); 1575 1576 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops)); 1577 } 1578 1579 return 0; 1580 } 1581 case Intrinsic::dbg_func_start: { 1582 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1583 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 1584 if (DebugInfo && FSI.getSubprogram() && 1585 DebugInfo->Verify(FSI.getSubprogram())) { 1586 std::vector<SDOperand> Ops; 1587 1588 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram()); 1589 1590 Ops.push_back(getRoot()); 1591 Ops.push_back(DAG.getConstant(LabelID, MVT::i32)); 1592 1593 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops)); 1594 } 1595 1596 return 0; 1597 } 1598 case Intrinsic::dbg_declare: { 1599 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1600 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 1601 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) { 1602 std::vector<SDOperand> Ops; 1603 1604 SDOperand AddressOp = getValue(DI.getAddress()); 1605 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) { 1606 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex()); 1607 } 1608 } 1609 1610 return 0; 1611 } 1612 1613 case Intrinsic::isunordered_f32: 1614 case Intrinsic::isunordered_f64: 1615 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)), 1616 getValue(I.getOperand(2)), ISD::SETUO)); 1617 return 0; 1618 1619 case Intrinsic::sqrt_f32: 1620 case Intrinsic::sqrt_f64: 1621 setValue(&I, DAG.getNode(ISD::FSQRT, 1622 getValue(I.getOperand(1)).getValueType(), 1623 getValue(I.getOperand(1)))); 1624 return 0; 1625 case Intrinsic::pcmarker: { 1626 SDOperand Tmp = getValue(I.getOperand(1)); 1627 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 1628 return 0; 1629 } 1630 case Intrinsic::readcyclecounter: { 1631 std::vector<MVT::ValueType> VTs; 1632 VTs.push_back(MVT::i64); 1633 VTs.push_back(MVT::Other); 1634 std::vector<SDOperand> Ops; 1635 Ops.push_back(getRoot()); 1636 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops); 1637 setValue(&I, Tmp); 1638 DAG.setRoot(Tmp.getValue(1)); 1639 return 0; 1640 } 1641 case Intrinsic::bswap_i16: 1642 case Intrinsic::bswap_i32: 1643 case Intrinsic::bswap_i64: 1644 setValue(&I, DAG.getNode(ISD::BSWAP, 1645 getValue(I.getOperand(1)).getValueType(), 1646 getValue(I.getOperand(1)))); 1647 return 0; 1648 case Intrinsic::cttz_i8: 1649 case Intrinsic::cttz_i16: 1650 case Intrinsic::cttz_i32: 1651 case Intrinsic::cttz_i64: 1652 setValue(&I, DAG.getNode(ISD::CTTZ, 1653 getValue(I.getOperand(1)).getValueType(), 1654 getValue(I.getOperand(1)))); 1655 return 0; 1656 case Intrinsic::ctlz_i8: 1657 case Intrinsic::ctlz_i16: 1658 case Intrinsic::ctlz_i32: 1659 case Intrinsic::ctlz_i64: 1660 setValue(&I, DAG.getNode(ISD::CTLZ, 1661 getValue(I.getOperand(1)).getValueType(), 1662 getValue(I.getOperand(1)))); 1663 return 0; 1664 case Intrinsic::ctpop_i8: 1665 case Intrinsic::ctpop_i16: 1666 case Intrinsic::ctpop_i32: 1667 case Intrinsic::ctpop_i64: 1668 setValue(&I, DAG.getNode(ISD::CTPOP, 1669 getValue(I.getOperand(1)).getValueType(), 1670 getValue(I.getOperand(1)))); 1671 return 0; 1672 case Intrinsic::stacksave: { 1673 std::vector<MVT::ValueType> VTs; 1674 VTs.push_back(TLI.getPointerTy()); 1675 VTs.push_back(MVT::Other); 1676 std::vector<SDOperand> Ops; 1677 Ops.push_back(getRoot()); 1678 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops); 1679 setValue(&I, Tmp); 1680 DAG.setRoot(Tmp.getValue(1)); 1681 return 0; 1682 } 1683 case Intrinsic::stackrestore: { 1684 SDOperand Tmp = getValue(I.getOperand(1)); 1685 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 1686 return 0; 1687 } 1688 case Intrinsic::prefetch: 1689 // FIXME: Currently discarding prefetches. 1690 return 0; 1691 } 1692} 1693 1694 1695void SelectionDAGLowering::visitCall(CallInst &I) { 1696 const char *RenameFn = 0; 1697 if (Function *F = I.getCalledFunction()) { 1698 if (F->isExternal()) 1699 if (unsigned IID = F->getIntrinsicID()) { 1700 RenameFn = visitIntrinsicCall(I, IID); 1701 if (!RenameFn) 1702 return; 1703 } else { // Not an LLVM intrinsic. 1704 const std::string &Name = F->getName(); 1705 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 1706 if (I.getNumOperands() == 3 && // Basic sanity checks. 1707 I.getOperand(1)->getType()->isFloatingPoint() && 1708 I.getType() == I.getOperand(1)->getType() && 1709 I.getType() == I.getOperand(2)->getType()) { 1710 SDOperand LHS = getValue(I.getOperand(1)); 1711 SDOperand RHS = getValue(I.getOperand(2)); 1712 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 1713 LHS, RHS)); 1714 return; 1715 } 1716 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 1717 if (I.getNumOperands() == 2 && // Basic sanity checks. 1718 I.getOperand(1)->getType()->isFloatingPoint() && 1719 I.getType() == I.getOperand(1)->getType()) { 1720 SDOperand Tmp = getValue(I.getOperand(1)); 1721 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 1722 return; 1723 } 1724 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 1725 if (I.getNumOperands() == 2 && // Basic sanity checks. 1726 I.getOperand(1)->getType()->isFloatingPoint() && 1727 I.getType() == I.getOperand(1)->getType()) { 1728 SDOperand Tmp = getValue(I.getOperand(1)); 1729 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 1730 return; 1731 } 1732 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 1733 if (I.getNumOperands() == 2 && // Basic sanity checks. 1734 I.getOperand(1)->getType()->isFloatingPoint() && 1735 I.getType() == I.getOperand(1)->getType()) { 1736 SDOperand Tmp = getValue(I.getOperand(1)); 1737 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 1738 return; 1739 } 1740 } 1741 } 1742 } else if (isa<InlineAsm>(I.getOperand(0))) { 1743 visitInlineAsm(I); 1744 return; 1745 } 1746 1747 SDOperand Callee; 1748 if (!RenameFn) 1749 Callee = getValue(I.getOperand(0)); 1750 else 1751 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 1752 std::vector<std::pair<SDOperand, const Type*> > Args; 1753 Args.reserve(I.getNumOperands()); 1754 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1755 Value *Arg = I.getOperand(i); 1756 SDOperand ArgNode = getValue(Arg); 1757 Args.push_back(std::make_pair(ArgNode, Arg->getType())); 1758 } 1759 1760 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); 1761 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1762 1763 std::pair<SDOperand,SDOperand> Result = 1764 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(), 1765 I.isTailCall(), Callee, Args, DAG); 1766 if (I.getType() != Type::VoidTy) 1767 setValue(&I, Result.first); 1768 DAG.setRoot(Result.second); 1769} 1770 1771SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 1772 SDOperand &Chain, SDOperand &Flag)const{ 1773 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 1774 Chain = Val.getValue(1); 1775 Flag = Val.getValue(2); 1776 1777 // If the result was expanded, copy from the top part. 1778 if (Regs.size() > 1) { 1779 assert(Regs.size() == 2 && 1780 "Cannot expand to more than 2 elts yet!"); 1781 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 1782 Chain = Val.getValue(1); 1783 Flag = Val.getValue(2); 1784 if (DAG.getTargetLoweringInfo().isLittleEndian()) 1785 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 1786 else 1787 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 1788 } 1789 1790 // Otherwise, if the return value was promoted or extended, truncate it to the 1791 // appropriate type. 1792 if (RegVT == ValueVT) 1793 return Val; 1794 1795 if (MVT::isInteger(RegVT)) { 1796 if (ValueVT < RegVT) 1797 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1798 else 1799 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 1800 } else { 1801 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 1802 } 1803} 1804 1805/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 1806/// specified value into the registers specified by this object. This uses 1807/// Chain/Flag as the input and updates them for the output Chain/Flag. 1808void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 1809 SDOperand &Chain, SDOperand &Flag, 1810 MVT::ValueType PtrVT) const { 1811 if (Regs.size() == 1) { 1812 // If there is a single register and the types differ, this must be 1813 // a promotion. 1814 if (RegVT != ValueVT) { 1815 if (MVT::isInteger(RegVT)) { 1816 if (RegVT < ValueVT) 1817 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 1818 else 1819 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 1820 } else 1821 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 1822 } 1823 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 1824 Flag = Chain.getValue(1); 1825 } else { 1826 std::vector<unsigned> R(Regs); 1827 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 1828 std::reverse(R.begin(), R.end()); 1829 1830 for (unsigned i = 0, e = R.size(); i != e; ++i) { 1831 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 1832 DAG.getConstant(i, PtrVT)); 1833 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 1834 Flag = Chain.getValue(1); 1835 } 1836 } 1837} 1838 1839/// AddInlineAsmOperands - Add this value to the specified inlineasm node 1840/// operand list. This adds the code marker and includes the number of 1841/// values added into it. 1842void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 1843 std::vector<SDOperand> &Ops) const { 1844 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32)); 1845 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 1846 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 1847} 1848 1849/// isAllocatableRegister - If the specified register is safe to allocate, 1850/// i.e. it isn't a stack pointer or some other special register, return the 1851/// register class for the register. Otherwise, return null. 1852static const TargetRegisterClass * 1853isAllocatableRegister(unsigned Reg, MachineFunction &MF, 1854 const TargetLowering &TLI, const MRegisterInfo *MRI) { 1855 MVT::ValueType FoundVT = MVT::Other; 1856 const TargetRegisterClass *FoundRC = 0; 1857 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 1858 E = MRI->regclass_end(); RCI != E; ++RCI) { 1859 MVT::ValueType ThisVT = MVT::Other; 1860 1861 const TargetRegisterClass *RC = *RCI; 1862 // If none of the the value types for this register class are valid, we 1863 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1864 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1865 I != E; ++I) { 1866 if (TLI.isTypeLegal(*I)) { 1867 // If we have already found this register in a different register class, 1868 // choose the one with the largest VT specified. For example, on 1869 // PowerPC, we favor f64 register classes over f32. 1870 if (FoundVT == MVT::Other || 1871 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 1872 ThisVT = *I; 1873 break; 1874 } 1875 } 1876 } 1877 1878 if (ThisVT == MVT::Other) continue; 1879 1880 // NOTE: This isn't ideal. In particular, this might allocate the 1881 // frame pointer in functions that need it (due to them not being taken 1882 // out of allocation, because a variable sized allocation hasn't been seen 1883 // yet). This is a slight code pessimization, but should still work. 1884 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 1885 E = RC->allocation_order_end(MF); I != E; ++I) 1886 if (*I == Reg) { 1887 // We found a matching register class. Keep looking at others in case 1888 // we find one with larger registers that this physreg is also in. 1889 FoundRC = RC; 1890 FoundVT = ThisVT; 1891 break; 1892 } 1893 } 1894 return FoundRC; 1895} 1896 1897RegsForValue SelectionDAGLowering:: 1898GetRegistersForValue(const std::string &ConstrCode, 1899 MVT::ValueType VT, bool isOutReg, bool isInReg, 1900 std::set<unsigned> &OutputRegs, 1901 std::set<unsigned> &InputRegs) { 1902 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 1903 TLI.getRegForInlineAsmConstraint(ConstrCode, VT); 1904 std::vector<unsigned> Regs; 1905 1906 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1; 1907 MVT::ValueType RegVT; 1908 MVT::ValueType ValueVT = VT; 1909 1910 if (PhysReg.first) { 1911 if (VT == MVT::Other) 1912 ValueVT = *PhysReg.second->vt_begin(); 1913 1914 // Get the actual register value type. This is important, because the user 1915 // may have asked for (e.g.) the AX register in i32 type. We need to 1916 // remember that AX is actually i16 to get the right extension. 1917 RegVT = *PhysReg.second->vt_begin(); 1918 1919 // This is a explicit reference to a physical register. 1920 Regs.push_back(PhysReg.first); 1921 1922 // If this is an expanded reference, add the rest of the regs to Regs. 1923 if (NumRegs != 1) { 1924 TargetRegisterClass::iterator I = PhysReg.second->begin(); 1925 TargetRegisterClass::iterator E = PhysReg.second->end(); 1926 for (; *I != PhysReg.first; ++I) 1927 assert(I != E && "Didn't find reg!"); 1928 1929 // Already added the first reg. 1930 --NumRegs; ++I; 1931 for (; NumRegs; --NumRegs, ++I) { 1932 assert(I != E && "Ran out of registers to allocate!"); 1933 Regs.push_back(*I); 1934 } 1935 } 1936 return RegsForValue(Regs, RegVT, ValueVT); 1937 } 1938 1939 // This is a reference to a register class. Allocate NumRegs consecutive, 1940 // available, registers from the class. 1941 std::vector<unsigned> RegClassRegs = 1942 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT); 1943 1944 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 1945 MachineFunction &MF = *CurMBB->getParent(); 1946 unsigned NumAllocated = 0; 1947 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 1948 unsigned Reg = RegClassRegs[i]; 1949 // See if this register is available. 1950 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 1951 (isInReg && InputRegs.count(Reg))) { // Already used. 1952 // Make sure we find consecutive registers. 1953 NumAllocated = 0; 1954 continue; 1955 } 1956 1957 // Check to see if this register is allocatable (i.e. don't give out the 1958 // stack pointer). 1959 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 1960 if (!RC) { 1961 // Make sure we find consecutive registers. 1962 NumAllocated = 0; 1963 continue; 1964 } 1965 1966 // Okay, this register is good, we can use it. 1967 ++NumAllocated; 1968 1969 // If we allocated enough consecutive 1970 if (NumAllocated == NumRegs) { 1971 unsigned RegStart = (i-NumAllocated)+1; 1972 unsigned RegEnd = i+1; 1973 // Mark all of the allocated registers used. 1974 for (unsigned i = RegStart; i != RegEnd; ++i) { 1975 unsigned Reg = RegClassRegs[i]; 1976 Regs.push_back(Reg); 1977 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used. 1978 if (isInReg) InputRegs.insert(Reg); // Mark reg used. 1979 } 1980 1981 return RegsForValue(Regs, *RC->vt_begin(), VT); 1982 } 1983 } 1984 1985 // Otherwise, we couldn't allocate enough registers for this. 1986 return RegsForValue(); 1987} 1988 1989 1990/// visitInlineAsm - Handle a call to an InlineAsm object. 1991/// 1992void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 1993 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 1994 1995 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 1996 MVT::Other); 1997 1998 // Note, we treat inline asms both with and without side-effects as the same. 1999 // If an inline asm doesn't have side effects and doesn't access memory, we 2000 // could not choose to not chain it. 2001 bool hasSideEffects = IA->hasSideEffects(); 2002 2003 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 2004 std::vector<MVT::ValueType> ConstraintVTs; 2005 2006 /// AsmNodeOperands - A list of pairs. The first element is a register, the 2007 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set 2008 /// if it is a def of that register. 2009 std::vector<SDOperand> AsmNodeOperands; 2010 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 2011 AsmNodeOperands.push_back(AsmStr); 2012 2013 SDOperand Chain = getRoot(); 2014 SDOperand Flag; 2015 2016 // We fully assign registers here at isel time. This is not optimal, but 2017 // should work. For register classes that correspond to LLVM classes, we 2018 // could let the LLVM RA do its thing, but we currently don't. Do a prepass 2019 // over the constraints, collecting fixed registers that we know we can't use. 2020 std::set<unsigned> OutputRegs, InputRegs; 2021 unsigned OpNum = 1; 2022 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2023 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2024 std::string &ConstraintCode = Constraints[i].Codes[0]; 2025 2026 MVT::ValueType OpVT; 2027 2028 // Compute the value type for each operand and add it to ConstraintVTs. 2029 switch (Constraints[i].Type) { 2030 case InlineAsm::isOutput: 2031 if (!Constraints[i].isIndirectOutput) { 2032 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2033 OpVT = TLI.getValueType(I.getType()); 2034 } else { 2035 const Type *OpTy = I.getOperand(OpNum)->getType(); 2036 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType()); 2037 OpNum++; // Consumes a call operand. 2038 } 2039 break; 2040 case InlineAsm::isInput: 2041 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType()); 2042 OpNum++; // Consumes a call operand. 2043 break; 2044 case InlineAsm::isClobber: 2045 OpVT = MVT::Other; 2046 break; 2047 } 2048 2049 ConstraintVTs.push_back(OpVT); 2050 2051 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0) 2052 continue; // Not assigned a fixed reg. 2053 2054 // Build a list of regs that this operand uses. This always has a single 2055 // element for promoted/expanded operands. 2056 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT, 2057 false, false, 2058 OutputRegs, InputRegs); 2059 2060 switch (Constraints[i].Type) { 2061 case InlineAsm::isOutput: 2062 // We can't assign any other output to this register. 2063 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2064 // If this is an early-clobber output, it cannot be assigned to the same 2065 // value as the input reg. 2066 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2067 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2068 break; 2069 case InlineAsm::isInput: 2070 // We can't assign any other input to this register. 2071 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2072 break; 2073 case InlineAsm::isClobber: 2074 // Clobbered regs cannot be used as inputs or outputs. 2075 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2076 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2077 break; 2078 } 2079 } 2080 2081 // Loop over all of the inputs, copying the operand values into the 2082 // appropriate registers and processing the output regs. 2083 RegsForValue RetValRegs; 2084 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 2085 OpNum = 1; 2086 2087 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2088 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2089 std::string &ConstraintCode = Constraints[i].Codes[0]; 2090 2091 switch (Constraints[i].Type) { 2092 case InlineAsm::isOutput: { 2093 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2094 if (ConstraintCode.size() == 1) // not a physreg name. 2095 CTy = TLI.getConstraintType(ConstraintCode[0]); 2096 2097 if (CTy == TargetLowering::C_Memory) { 2098 // Memory output. 2099 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2100 2101 // Check that the operand (the address to store to) isn't a float. 2102 if (!MVT::isInteger(InOperandVal.getValueType())) 2103 assert(0 && "MATCH FAIL!"); 2104 2105 if (!Constraints[i].isIndirectOutput) 2106 assert(0 && "MATCH FAIL!"); 2107 2108 OpNum++; // Consumes a call operand. 2109 2110 // Extend/truncate to the right pointer type if needed. 2111 MVT::ValueType PtrType = TLI.getPointerTy(); 2112 if (InOperandVal.getValueType() < PtrType) 2113 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2114 else if (InOperandVal.getValueType() > PtrType) 2115 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2116 2117 // Add information to the INLINEASM node to know about this output. 2118 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2119 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2120 AsmNodeOperands.push_back(InOperandVal); 2121 break; 2122 } 2123 2124 // Otherwise, this is a register output. 2125 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2126 2127 // If this is an early-clobber output, or if there is an input 2128 // constraint that matches this, we need to reserve the input register 2129 // so no other inputs allocate to it. 2130 bool UsesInputRegister = false; 2131 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2132 UsesInputRegister = true; 2133 2134 // Copy the output from the appropriate register. Find a register that 2135 // we can use. 2136 RegsForValue Regs = 2137 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2138 true, UsesInputRegister, 2139 OutputRegs, InputRegs); 2140 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!"); 2141 2142 if (!Constraints[i].isIndirectOutput) { 2143 assert(RetValRegs.Regs.empty() && 2144 "Cannot have multiple output constraints yet!"); 2145 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2146 RetValRegs = Regs; 2147 } else { 2148 IndirectStoresToEmit.push_back(std::make_pair(Regs, 2149 I.getOperand(OpNum))); 2150 OpNum++; // Consumes a call operand. 2151 } 2152 2153 // Add information to the INLINEASM node to know that this register is 2154 // set. 2155 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands); 2156 break; 2157 } 2158 case InlineAsm::isInput: { 2159 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2160 OpNum++; // Consumes a call operand. 2161 2162 if (isdigit(ConstraintCode[0])) { // Matching constraint? 2163 // If this is required to match an output register we have already set, 2164 // just use its register. 2165 unsigned OperandNo = atoi(ConstraintCode.c_str()); 2166 2167 // Scan until we find the definition we already emitted of this operand. 2168 // When we find it, create a RegsForValue operand. 2169 unsigned CurOp = 2; // The first operand. 2170 for (; OperandNo; --OperandNo) { 2171 // Advance to the next operand. 2172 unsigned NumOps = 2173 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2174 assert(((NumOps & 7) == 2 /*REGDEF*/ || 2175 (NumOps & 7) == 4 /*MEM*/) && 2176 "Skipped past definitions?"); 2177 CurOp += (NumOps>>3)+1; 2178 } 2179 2180 unsigned NumOps = 2181 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2182 assert((NumOps & 7) == 2 /*REGDEF*/ && 2183 "Skipped past definitions?"); 2184 2185 // Add NumOps>>3 registers to MatchedRegs. 2186 RegsForValue MatchedRegs; 2187 MatchedRegs.ValueVT = InOperandVal.getValueType(); 2188 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 2189 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 2190 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 2191 MatchedRegs.Regs.push_back(Reg); 2192 } 2193 2194 // Use the produced MatchedRegs object to 2195 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 2196 TLI.getPointerTy()); 2197 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 2198 break; 2199 } 2200 2201 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2202 if (ConstraintCode.size() == 1) // not a physreg name. 2203 CTy = TLI.getConstraintType(ConstraintCode[0]); 2204 2205 if (CTy == TargetLowering::C_Other) { 2206 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0])) 2207 assert(0 && "MATCH FAIL!"); 2208 2209 // Add information to the INLINEASM node to know about this input. 2210 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 2211 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2212 AsmNodeOperands.push_back(InOperandVal); 2213 break; 2214 } else if (CTy == TargetLowering::C_Memory) { 2215 // Memory input. 2216 2217 // Check that the operand isn't a float. 2218 if (!MVT::isInteger(InOperandVal.getValueType())) 2219 assert(0 && "MATCH FAIL!"); 2220 2221 // Extend/truncate to the right pointer type if needed. 2222 MVT::ValueType PtrType = TLI.getPointerTy(); 2223 if (InOperandVal.getValueType() < PtrType) 2224 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2225 else if (InOperandVal.getValueType() > PtrType) 2226 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2227 2228 // Add information to the INLINEASM node to know about this input. 2229 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2230 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2231 AsmNodeOperands.push_back(InOperandVal); 2232 break; 2233 } 2234 2235 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2236 2237 // Copy the input into the appropriate registers. 2238 RegsForValue InRegs = 2239 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2240 false, true, OutputRegs, InputRegs); 2241 // FIXME: should be match fail. 2242 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!"); 2243 2244 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy()); 2245 2246 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); 2247 break; 2248 } 2249 case InlineAsm::isClobber: { 2250 RegsForValue ClobberedRegs = 2251 GetRegistersForValue(ConstraintCode, MVT::Other, false, false, 2252 OutputRegs, InputRegs); 2253 // Add the clobbered value to the operand list, so that the register 2254 // allocator is aware that the physreg got clobbered. 2255 if (!ClobberedRegs.Regs.empty()) 2256 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands); 2257 break; 2258 } 2259 } 2260 } 2261 2262 // Finish up input operands. 2263 AsmNodeOperands[0] = Chain; 2264 if (Flag.Val) AsmNodeOperands.push_back(Flag); 2265 2266 std::vector<MVT::ValueType> VTs; 2267 VTs.push_back(MVT::Other); 2268 VTs.push_back(MVT::Flag); 2269 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands); 2270 Flag = Chain.getValue(1); 2271 2272 // If this asm returns a register value, copy the result from that register 2273 // and set it as the value of the call. 2274 if (!RetValRegs.Regs.empty()) 2275 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag)); 2276 2277 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 2278 2279 // Process indirect outputs, first output all of the flagged copies out of 2280 // physregs. 2281 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 2282 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 2283 Value *Ptr = IndirectStoresToEmit[i].second; 2284 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 2285 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 2286 } 2287 2288 // Emit the non-flagged stores from the physregs. 2289 std::vector<SDOperand> OutChains; 2290 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 2291 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 2292 StoresToEmit[i].first, 2293 getValue(StoresToEmit[i].second), 2294 DAG.getSrcValue(StoresToEmit[i].second))); 2295 if (!OutChains.empty()) 2296 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains); 2297 DAG.setRoot(Chain); 2298} 2299 2300 2301void SelectionDAGLowering::visitMalloc(MallocInst &I) { 2302 SDOperand Src = getValue(I.getOperand(0)); 2303 2304 MVT::ValueType IntPtr = TLI.getPointerTy(); 2305 2306 if (IntPtr < Src.getValueType()) 2307 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 2308 else if (IntPtr > Src.getValueType()) 2309 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 2310 2311 // Scale the source by the type size. 2312 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 2313 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 2314 Src, getIntPtrConstant(ElementSize)); 2315 2316 std::vector<std::pair<SDOperand, const Type*> > Args; 2317 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType())); 2318 2319 std::pair<SDOperand,SDOperand> Result = 2320 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true, 2321 DAG.getExternalSymbol("malloc", IntPtr), 2322 Args, DAG); 2323 setValue(&I, Result.first); // Pointers always fit in registers 2324 DAG.setRoot(Result.second); 2325} 2326 2327void SelectionDAGLowering::visitFree(FreeInst &I) { 2328 std::vector<std::pair<SDOperand, const Type*> > Args; 2329 Args.push_back(std::make_pair(getValue(I.getOperand(0)), 2330 TLI.getTargetData()->getIntPtrType())); 2331 MVT::ValueType IntPtr = TLI.getPointerTy(); 2332 std::pair<SDOperand,SDOperand> Result = 2333 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true, 2334 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 2335 DAG.setRoot(Result.second); 2336} 2337 2338// InsertAtEndOfBasicBlock - This method should be implemented by targets that 2339// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 2340// instructions are special in various ways, which require special support to 2341// insert. The specified MachineInstr is created but not inserted into any 2342// basic blocks, and the scheduler passes ownership of it to this method. 2343MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2344 MachineBasicBlock *MBB) { 2345 std::cerr << "If a target marks an instruction with " 2346 "'usesCustomDAGSchedInserter', it must implement " 2347 "TargetLowering::InsertAtEndOfBasicBlock!\n"; 2348 abort(); 2349 return 0; 2350} 2351 2352void SelectionDAGLowering::visitVAStart(CallInst &I) { 2353 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 2354 getValue(I.getOperand(1)), 2355 DAG.getSrcValue(I.getOperand(1)))); 2356} 2357 2358void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 2359 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 2360 getValue(I.getOperand(0)), 2361 DAG.getSrcValue(I.getOperand(0))); 2362 setValue(&I, V); 2363 DAG.setRoot(V.getValue(1)); 2364} 2365 2366void SelectionDAGLowering::visitVAEnd(CallInst &I) { 2367 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 2368 getValue(I.getOperand(1)), 2369 DAG.getSrcValue(I.getOperand(1)))); 2370} 2371 2372void SelectionDAGLowering::visitVACopy(CallInst &I) { 2373 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 2374 getValue(I.getOperand(1)), 2375 getValue(I.getOperand(2)), 2376 DAG.getSrcValue(I.getOperand(1)), 2377 DAG.getSrcValue(I.getOperand(2)))); 2378} 2379 2380/// TargetLowering::LowerArguments - This is the default LowerArguments 2381/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 2382/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 2383/// integrated into SDISel. 2384std::vector<SDOperand> 2385TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 2386 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 2387 std::vector<SDOperand> Ops; 2388 Ops.push_back(DAG.getRoot()); 2389 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 2390 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 2391 2392 // Add one result value for each formal argument. 2393 std::vector<MVT::ValueType> RetVals; 2394 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2395 MVT::ValueType VT = getValueType(I->getType()); 2396 2397 switch (getTypeAction(VT)) { 2398 default: assert(0 && "Unknown type action!"); 2399 case Legal: 2400 RetVals.push_back(VT); 2401 break; 2402 case Promote: 2403 RetVals.push_back(getTypeToTransformTo(VT)); 2404 break; 2405 case Expand: 2406 if (VT != MVT::Vector) { 2407 // If this is a large integer, it needs to be broken up into small 2408 // integers. Figure out what the destination type is and how many small 2409 // integers it turns into. 2410 MVT::ValueType NVT = getTypeToTransformTo(VT); 2411 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2412 for (unsigned i = 0; i != NumVals; ++i) 2413 RetVals.push_back(NVT); 2414 } else { 2415 // Otherwise, this is a vector type. We only support legal vectors 2416 // right now. 2417 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements(); 2418 const Type *EltTy = cast<PackedType>(I->getType())->getElementType(); 2419 2420 // Figure out if there is a Packed type corresponding to this Vector 2421 // type. If so, convert to the packed type. 2422 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2423 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2424 RetVals.push_back(TVT); 2425 } else { 2426 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2427 } 2428 } 2429 break; 2430 } 2431 } 2432 2433 RetVals.push_back(MVT::Other); 2434 2435 // Create the node. 2436 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val; 2437 2438 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 2439 2440 // Set up the return result vector. 2441 Ops.clear(); 2442 unsigned i = 0; 2443 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2444 MVT::ValueType VT = getValueType(I->getType()); 2445 2446 switch (getTypeAction(VT)) { 2447 default: assert(0 && "Unknown type action!"); 2448 case Legal: 2449 Ops.push_back(SDOperand(Result, i++)); 2450 break; 2451 case Promote: { 2452 SDOperand Op(Result, i++); 2453 if (MVT::isInteger(VT)) { 2454 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 2455 : ISD::AssertZext; 2456 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT)); 2457 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2458 } else { 2459 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2460 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 2461 } 2462 Ops.push_back(Op); 2463 break; 2464 } 2465 case Expand: 2466 if (VT != MVT::Vector) { 2467 // If this is a large integer, it needs to be reassembled from small 2468 // integers. Figure out what the source elt type is and how many small 2469 // integers it is. 2470 MVT::ValueType NVT = getTypeToTransformTo(VT); 2471 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2472 if (NumVals == 2) { 2473 SDOperand Lo = SDOperand(Result, i++); 2474 SDOperand Hi = SDOperand(Result, i++); 2475 2476 if (!isLittleEndian()) 2477 std::swap(Lo, Hi); 2478 2479 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi)); 2480 } else { 2481 // Value scalarized into many values. Unimp for now. 2482 assert(0 && "Cannot expand i64 -> i16 yet!"); 2483 } 2484 } else { 2485 // Otherwise, this is a vector type. We only support legal vectors 2486 // right now. 2487 const PackedType *PTy = cast<PackedType>(I->getType()); 2488 unsigned NumElems = PTy->getNumElements(); 2489 const Type *EltTy = PTy->getElementType(); 2490 2491 // Figure out if there is a Packed type corresponding to this Vector 2492 // type. If so, convert to the packed type. 2493 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2494 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2495 SDOperand N = SDOperand(Result, i++); 2496 // Handle copies from generic vectors to registers. 2497 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 2498 DAG.getConstant(NumElems, MVT::i32), 2499 DAG.getValueType(getValueType(EltTy))); 2500 Ops.push_back(N); 2501 } else { 2502 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2503 abort(); 2504 } 2505 } 2506 break; 2507 } 2508 } 2509 return Ops; 2510} 2511 2512 2513/// TargetLowering::LowerCallTo - This is the default LowerCallTo 2514/// implementation, which just inserts an ISD::CALL node, which is later custom 2515/// lowered by the target to something concrete. FIXME: When all targets are 2516/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 2517std::pair<SDOperand, SDOperand> 2518TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 2519 unsigned CallingConv, bool isTailCall, 2520 SDOperand Callee, 2521 ArgListTy &Args, SelectionDAG &DAG) { 2522 std::vector<SDOperand> Ops; 2523 Ops.push_back(Chain); // Op#0 - Chain 2524 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 2525 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 2526 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 2527 Ops.push_back(Callee); 2528 2529 // Handle all of the outgoing arguments. 2530 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 2531 MVT::ValueType VT = getValueType(Args[i].second); 2532 SDOperand Op = Args[i].first; 2533 bool isSigned = Args[i].second->isSigned(); 2534 switch (getTypeAction(VT)) { 2535 default: assert(0 && "Unknown type action!"); 2536 case Legal: 2537 Ops.push_back(Op); 2538 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2539 break; 2540 case Promote: 2541 if (MVT::isInteger(VT)) { 2542 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 2543 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 2544 } else { 2545 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2546 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 2547 } 2548 Ops.push_back(Op); 2549 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2550 break; 2551 case Expand: 2552 if (VT != MVT::Vector) { 2553 // If this is a large integer, it needs to be broken down into small 2554 // integers. Figure out what the source elt type is and how many small 2555 // integers it is. 2556 MVT::ValueType NVT = getTypeToTransformTo(VT); 2557 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2558 if (NumVals == 2) { 2559 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, 2560 DAG.getConstant(0, getPointerTy())); 2561 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, 2562 DAG.getConstant(1, getPointerTy())); 2563 if (!isLittleEndian()) 2564 std::swap(Lo, Hi); 2565 2566 Ops.push_back(Lo); 2567 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2568 Ops.push_back(Hi); 2569 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2570 } else { 2571 // Value scalarized into many values. Unimp for now. 2572 assert(0 && "Cannot expand i64 -> i16 yet!"); 2573 } 2574 } else { 2575 // Otherwise, this is a vector type. We only support legal vectors 2576 // right now. 2577 const PackedType *PTy = cast<PackedType>(Args[i].second); 2578 unsigned NumElems = PTy->getNumElements(); 2579 const Type *EltTy = PTy->getElementType(); 2580 2581 // Figure out if there is a Packed type corresponding to this Vector 2582 // type. If so, convert to the packed type. 2583 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2584 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2585 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. 2586 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 2587 Ops.push_back(Op); 2588 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2589 } else { 2590 assert(0 && "Don't support illegal by-val vector call args yet!"); 2591 abort(); 2592 } 2593 } 2594 break; 2595 } 2596 } 2597 2598 // Figure out the result value types. 2599 std::vector<MVT::ValueType> RetTys; 2600 2601 if (RetTy != Type::VoidTy) { 2602 MVT::ValueType VT = getValueType(RetTy); 2603 switch (getTypeAction(VT)) { 2604 default: assert(0 && "Unknown type action!"); 2605 case Legal: 2606 RetTys.push_back(VT); 2607 break; 2608 case Promote: 2609 RetTys.push_back(getTypeToTransformTo(VT)); 2610 break; 2611 case Expand: 2612 if (VT != MVT::Vector) { 2613 // If this is a large integer, it needs to be reassembled from small 2614 // integers. Figure out what the source elt type is and how many small 2615 // integers it is. 2616 MVT::ValueType NVT = getTypeToTransformTo(VT); 2617 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2618 for (unsigned i = 0; i != NumVals; ++i) 2619 RetTys.push_back(NVT); 2620 } else { 2621 // Otherwise, this is a vector type. We only support legal vectors 2622 // right now. 2623 const PackedType *PTy = cast<PackedType>(RetTy); 2624 unsigned NumElems = PTy->getNumElements(); 2625 const Type *EltTy = PTy->getElementType(); 2626 2627 // Figure out if there is a Packed type corresponding to this Vector 2628 // type. If so, convert to the packed type. 2629 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2630 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2631 RetTys.push_back(TVT); 2632 } else { 2633 assert(0 && "Don't support illegal by-val vector call results yet!"); 2634 abort(); 2635 } 2636 } 2637 } 2638 } 2639 2640 RetTys.push_back(MVT::Other); // Always has a chain. 2641 2642 // Finally, create the CALL node. 2643 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops); 2644 2645 // This returns a pair of operands. The first element is the 2646 // return value for the function (if RetTy is not VoidTy). The second 2647 // element is the outgoing token chain. 2648 SDOperand ResVal; 2649 if (RetTys.size() != 1) { 2650 MVT::ValueType VT = getValueType(RetTy); 2651 if (RetTys.size() == 2) { 2652 ResVal = Res; 2653 2654 // If this value was promoted, truncate it down. 2655 if (ResVal.getValueType() != VT) { 2656 if (VT == MVT::Vector) { 2657 // Insert a VBITCONVERT to convert from the packed result type to the 2658 // MVT::Vector type. 2659 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements(); 2660 const Type *EltTy = cast<PackedType>(RetTy)->getElementType(); 2661 2662 // Figure out if there is a Packed type corresponding to this Vector 2663 // type. If so, convert to the packed type. 2664 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2665 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2666 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 2667 // "N x PTyElementVT" MVT::Vector type. 2668 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 2669 DAG.getConstant(NumElems, MVT::i32), 2670 DAG.getValueType(getValueType(EltTy))); 2671 } else { 2672 abort(); 2673 } 2674 } else if (MVT::isInteger(VT)) { 2675 unsigned AssertOp = RetTy->isSigned() ? 2676 ISD::AssertSext : ISD::AssertZext; 2677 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 2678 DAG.getValueType(VT)); 2679 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 2680 } else { 2681 assert(MVT::isFloatingPoint(VT)); 2682 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 2683 } 2684 } 2685 } else if (RetTys.size() == 3) { 2686 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 2687 Res.getValue(0), Res.getValue(1)); 2688 2689 } else { 2690 assert(0 && "Case not handled yet!"); 2691 } 2692 } 2693 2694 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 2695} 2696 2697 2698 2699// It is always conservatively correct for llvm.returnaddress and 2700// llvm.frameaddress to return 0. 2701// 2702// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be 2703// expanded to 0 if the target wants. 2704std::pair<SDOperand, SDOperand> 2705TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, 2706 unsigned Depth, SelectionDAG &DAG) { 2707 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain); 2708} 2709 2710SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2711 assert(0 && "LowerOperation not implemented for this target!"); 2712 abort(); 2713 return SDOperand(); 2714} 2715 2716SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 2717 SelectionDAG &DAG) { 2718 assert(0 && "CustomPromoteOperation not implemented for this target!"); 2719 abort(); 2720 return SDOperand(); 2721} 2722 2723void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) { 2724 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue(); 2725 std::pair<SDOperand,SDOperand> Result = 2726 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG); 2727 setValue(&I, Result.first); 2728 DAG.setRoot(Result.second); 2729} 2730 2731/// getMemsetValue - Vectorized representation of the memset value 2732/// operand. 2733static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 2734 SelectionDAG &DAG) { 2735 MVT::ValueType CurVT = VT; 2736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2737 uint64_t Val = C->getValue() & 255; 2738 unsigned Shift = 8; 2739 while (CurVT != MVT::i8) { 2740 Val = (Val << Shift) | Val; 2741 Shift <<= 1; 2742 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 2743 } 2744 return DAG.getConstant(Val, VT); 2745 } else { 2746 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2747 unsigned Shift = 8; 2748 while (CurVT != MVT::i8) { 2749 Value = 2750 DAG.getNode(ISD::OR, VT, 2751 DAG.getNode(ISD::SHL, VT, Value, 2752 DAG.getConstant(Shift, MVT::i8)), Value); 2753 Shift <<= 1; 2754 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 2755 } 2756 2757 return Value; 2758 } 2759} 2760 2761/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2762/// used when a memcpy is turned into a memset when the source is a constant 2763/// string ptr. 2764static SDOperand getMemsetStringVal(MVT::ValueType VT, 2765 SelectionDAG &DAG, TargetLowering &TLI, 2766 std::string &Str, unsigned Offset) { 2767 MVT::ValueType CurVT = VT; 2768 uint64_t Val = 0; 2769 unsigned MSB = getSizeInBits(VT) / 8; 2770 if (TLI.isLittleEndian()) 2771 Offset = Offset + MSB - 1; 2772 for (unsigned i = 0; i != MSB; ++i) { 2773 Val = (Val << 8) | Str[Offset]; 2774 Offset += TLI.isLittleEndian() ? -1 : 1; 2775 } 2776 return DAG.getConstant(Val, VT); 2777} 2778 2779/// getMemBasePlusOffset - Returns base and offset node for the 2780static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 2781 SelectionDAG &DAG, TargetLowering &TLI) { 2782 MVT::ValueType VT = Base.getValueType(); 2783 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2784} 2785 2786/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2787/// to replace the memset / memcpy is below the threshold. It also returns the 2788/// types of the sequence of memory ops to perform memset / memcpy. 2789static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 2790 unsigned Limit, uint64_t Size, 2791 unsigned Align, TargetLowering &TLI) { 2792 MVT::ValueType VT; 2793 2794 if (TLI.allowsUnalignedMemoryAccesses()) { 2795 VT = MVT::i64; 2796 } else { 2797 switch (Align & 7) { 2798 case 0: 2799 VT = MVT::i64; 2800 break; 2801 case 4: 2802 VT = MVT::i32; 2803 break; 2804 case 2: 2805 VT = MVT::i16; 2806 break; 2807 default: 2808 VT = MVT::i8; 2809 break; 2810 } 2811 } 2812 2813 MVT::ValueType LVT = MVT::i64; 2814 while (!TLI.isTypeLegal(LVT)) 2815 LVT = (MVT::ValueType)((unsigned)LVT - 1); 2816 assert(MVT::isInteger(LVT)); 2817 2818 if (VT > LVT) 2819 VT = LVT; 2820 2821 unsigned NumMemOps = 0; 2822 while (Size != 0) { 2823 unsigned VTSize = getSizeInBits(VT) / 8; 2824 while (VTSize > Size) { 2825 VT = (MVT::ValueType)((unsigned)VT - 1); 2826 VTSize >>= 1; 2827 } 2828 assert(MVT::isInteger(VT)); 2829 2830 if (++NumMemOps > Limit) 2831 return false; 2832 MemOps.push_back(VT); 2833 Size -= VTSize; 2834 } 2835 2836 return true; 2837} 2838 2839void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 2840 SDOperand Op1 = getValue(I.getOperand(1)); 2841 SDOperand Op2 = getValue(I.getOperand(2)); 2842 SDOperand Op3 = getValue(I.getOperand(3)); 2843 SDOperand Op4 = getValue(I.getOperand(4)); 2844 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 2845 if (Align == 0) Align = 1; 2846 2847 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 2848 std::vector<MVT::ValueType> MemOps; 2849 2850 // Expand memset / memcpy to a series of load / store ops 2851 // if the size operand falls below a certain threshold. 2852 std::vector<SDOperand> OutChains; 2853 switch (Op) { 2854 default: break; // Do nothing for now. 2855 case ISD::MEMSET: { 2856 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 2857 Size->getValue(), Align, TLI)) { 2858 unsigned NumMemOps = MemOps.size(); 2859 unsigned Offset = 0; 2860 for (unsigned i = 0; i < NumMemOps; i++) { 2861 MVT::ValueType VT = MemOps[i]; 2862 unsigned VTSize = getSizeInBits(VT) / 8; 2863 SDOperand Value = getMemsetValue(Op2, VT, DAG); 2864 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(), 2865 Value, 2866 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 2867 DAG.getSrcValue(I.getOperand(1), Offset)); 2868 OutChains.push_back(Store); 2869 Offset += VTSize; 2870 } 2871 } 2872 break; 2873 } 2874 case ISD::MEMCPY: { 2875 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 2876 Size->getValue(), Align, TLI)) { 2877 unsigned NumMemOps = MemOps.size(); 2878 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 2879 GlobalAddressSDNode *G = NULL; 2880 std::string Str; 2881 bool CopyFromStr = false; 2882 2883 if (Op2.getOpcode() == ISD::GlobalAddress) 2884 G = cast<GlobalAddressSDNode>(Op2); 2885 else if (Op2.getOpcode() == ISD::ADD && 2886 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 2887 Op2.getOperand(1).getOpcode() == ISD::Constant) { 2888 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 2889 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 2890 } 2891 if (G) { 2892 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2893 if (GV) { 2894 Str = GV->getStringValue(false); 2895 if (!Str.empty()) { 2896 CopyFromStr = true; 2897 SrcOff += SrcDelta; 2898 } 2899 } 2900 } 2901 2902 for (unsigned i = 0; i < NumMemOps; i++) { 2903 MVT::ValueType VT = MemOps[i]; 2904 unsigned VTSize = getSizeInBits(VT) / 8; 2905 SDOperand Value, Chain, Store; 2906 2907 if (CopyFromStr) { 2908 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2909 Chain = getRoot(); 2910 Store = 2911 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 2912 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 2913 DAG.getSrcValue(I.getOperand(1), DstOff)); 2914 } else { 2915 Value = DAG.getLoad(VT, getRoot(), 2916 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 2917 DAG.getSrcValue(I.getOperand(2), SrcOff)); 2918 Chain = Value.getValue(1); 2919 Store = 2920 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 2921 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 2922 DAG.getSrcValue(I.getOperand(1), DstOff)); 2923 } 2924 OutChains.push_back(Store); 2925 SrcOff += VTSize; 2926 DstOff += VTSize; 2927 } 2928 } 2929 break; 2930 } 2931 } 2932 2933 if (!OutChains.empty()) { 2934 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 2935 return; 2936 } 2937 } 2938 2939 std::vector<SDOperand> Ops; 2940 Ops.push_back(getRoot()); 2941 Ops.push_back(Op1); 2942 Ops.push_back(Op2); 2943 Ops.push_back(Op3); 2944 Ops.push_back(Op4); 2945 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops)); 2946} 2947 2948//===----------------------------------------------------------------------===// 2949// SelectionDAGISel code 2950//===----------------------------------------------------------------------===// 2951 2952unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 2953 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 2954} 2955 2956void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 2957 // FIXME: we only modify the CFG to split critical edges. This 2958 // updates dom and loop info. 2959} 2960 2961 2962/// OptimizeNoopCopyExpression - We have determined that the specified cast 2963/// instruction is a noop copy (e.g. it's casting from one pointer type to 2964/// another, int->uint, or int->sbyte on PPC. 2965/// 2966/// Return true if any changes are made. 2967static bool OptimizeNoopCopyExpression(CastInst *CI) { 2968 BasicBlock *DefBB = CI->getParent(); 2969 2970 /// InsertedCasts - Only insert a cast in each block once. 2971 std::map<BasicBlock*, CastInst*> InsertedCasts; 2972 2973 bool MadeChange = false; 2974 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); 2975 UI != E; ) { 2976 Use &TheUse = UI.getUse(); 2977 Instruction *User = cast<Instruction>(*UI); 2978 2979 // Figure out which BB this cast is used in. For PHI's this is the 2980 // appropriate predecessor block. 2981 BasicBlock *UserBB = User->getParent(); 2982 if (PHINode *PN = dyn_cast<PHINode>(User)) { 2983 unsigned OpVal = UI.getOperandNo()/2; 2984 UserBB = PN->getIncomingBlock(OpVal); 2985 } 2986 2987 // Preincrement use iterator so we don't invalidate it. 2988 ++UI; 2989 2990 // If this user is in the same block as the cast, don't change the cast. 2991 if (UserBB == DefBB) continue; 2992 2993 // If we have already inserted a cast into this block, use it. 2994 CastInst *&InsertedCast = InsertedCasts[UserBB]; 2995 2996 if (!InsertedCast) { 2997 BasicBlock::iterator InsertPt = UserBB->begin(); 2998 while (isa<PHINode>(InsertPt)) ++InsertPt; 2999 3000 InsertedCast = 3001 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); 3002 MadeChange = true; 3003 } 3004 3005 // Replace a use of the cast with a use of the new casat. 3006 TheUse = InsertedCast; 3007 } 3008 3009 // If we removed all uses, nuke the cast. 3010 if (CI->use_empty()) 3011 CI->eraseFromParent(); 3012 3013 return MadeChange; 3014} 3015 3016/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, 3017/// casting to the type of GEPI. 3018static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB, 3019 Instruction *GEPI, Value *Ptr, 3020 Value *PtrOffset) { 3021 if (V) return V; // Already computed. 3022 3023 BasicBlock::iterator InsertPt; 3024 if (BB == GEPI->getParent()) { 3025 // If insert into the GEP's block, insert right after the GEP. 3026 InsertPt = GEPI; 3027 ++InsertPt; 3028 } else { 3029 // Otherwise, insert at the top of BB, after any PHI nodes 3030 InsertPt = BB->begin(); 3031 while (isa<PHINode>(InsertPt)) ++InsertPt; 3032 } 3033 3034 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into 3035 // BB so that there is only one value live across basic blocks (the cast 3036 // operand). 3037 if (CastInst *CI = dyn_cast<CastInst>(Ptr)) 3038 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType())) 3039 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); 3040 3041 // Add the offset, cast it to the right type. 3042 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); 3043 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt); 3044} 3045 3046/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to 3047/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One 3048/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's 3049/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to 3050/// sink PtrOffset into user blocks where doing so will likely allow us to fold 3051/// the constant add into a load or store instruction. Additionally, if a user 3052/// is a pointer-pointer cast, we look through it to find its users. 3053static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr, 3054 Constant *PtrOffset, BasicBlock *DefBB, 3055 GetElementPtrInst *GEPI, 3056 std::map<BasicBlock*,Instruction*> &InsertedExprs) { 3057 while (!RepPtr->use_empty()) { 3058 Instruction *User = cast<Instruction>(RepPtr->use_back()); 3059 3060 // If the user is a Pointer-Pointer cast, recurse. 3061 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) { 3062 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3063 3064 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we 3065 // could invalidate an iterator. 3066 User->setOperand(0, UndefValue::get(RepPtr->getType())); 3067 continue; 3068 } 3069 3070 // If this is a load of the pointer, or a store through the pointer, emit 3071 // the increment into the load/store block. 3072 Instruction *NewVal; 3073 if (isa<LoadInst>(User) || 3074 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) { 3075 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], 3076 User->getParent(), GEPI, 3077 Ptr, PtrOffset); 3078 } else { 3079 // If this use is not foldable into the addressing mode, use a version 3080 // emitted in the GEP block. 3081 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI, 3082 Ptr, PtrOffset); 3083 } 3084 3085 if (GEPI->getType() != RepPtr->getType()) { 3086 BasicBlock::iterator IP = NewVal; 3087 ++IP; 3088 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP); 3089 } 3090 User->replaceUsesOfWith(RepPtr, NewVal); 3091 } 3092} 3093 3094 3095/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction 3096/// selection, we want to be a bit careful about some things. In particular, if 3097/// we have a GEP instruction that is used in a different block than it is 3098/// defined, the addressing expression of the GEP cannot be folded into loads or 3099/// stores that use it. In this case, decompose the GEP and move constant 3100/// indices into blocks that use it. 3101static bool OptimizeGEPExpression(GetElementPtrInst *GEPI, 3102 const TargetData *TD) { 3103 // If this GEP is only used inside the block it is defined in, there is no 3104 // need to rewrite it. 3105 bool isUsedOutsideDefBB = false; 3106 BasicBlock *DefBB = GEPI->getParent(); 3107 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end(); 3108 UI != E; ++UI) { 3109 if (cast<Instruction>(*UI)->getParent() != DefBB) { 3110 isUsedOutsideDefBB = true; 3111 break; 3112 } 3113 } 3114 if (!isUsedOutsideDefBB) return false; 3115 3116 // If this GEP has no non-zero constant indices, there is nothing we can do, 3117 // ignore it. 3118 bool hasConstantIndex = false; 3119 bool hasVariableIndex = false; 3120 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3121 E = GEPI->op_end(); OI != E; ++OI) { 3122 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) { 3123 if (CI->getRawValue()) { 3124 hasConstantIndex = true; 3125 break; 3126 } 3127 } else { 3128 hasVariableIndex = true; 3129 } 3130 } 3131 3132 // If this is a "GEP X, 0, 0, 0", turn this into a cast. 3133 if (!hasConstantIndex && !hasVariableIndex) { 3134 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(), 3135 GEPI->getName(), GEPI); 3136 GEPI->replaceAllUsesWith(NC); 3137 GEPI->eraseFromParent(); 3138 return true; 3139 } 3140 3141 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses. 3142 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) 3143 return false; 3144 3145 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the 3146 // constant offset (which we now know is non-zero) and deal with it later. 3147 uint64_t ConstantOffset = 0; 3148 const Type *UIntPtrTy = TD->getIntPtrType(); 3149 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI); 3150 const Type *Ty = GEPI->getOperand(0)->getType(); 3151 3152 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3153 E = GEPI->op_end(); OI != E; ++OI) { 3154 Value *Idx = *OI; 3155 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 3156 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 3157 if (Field) 3158 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field]; 3159 Ty = StTy->getElementType(Field); 3160 } else { 3161 Ty = cast<SequentialType>(Ty)->getElementType(); 3162 3163 // Handle constant subscripts. 3164 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3165 if (CI->getRawValue() == 0) continue; 3166 3167 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI)) 3168 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); 3169 else 3170 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue(); 3171 continue; 3172 } 3173 3174 // Ptr = Ptr + Idx * ElementSize; 3175 3176 // Cast Idx to UIntPtrTy if needed. 3177 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI); 3178 3179 uint64_t ElementSize = TD->getTypeSize(Ty); 3180 // Mask off bits that should not be set. 3181 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3182 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize); 3183 3184 // Multiply by the element size and add to the base. 3185 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI); 3186 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI); 3187 } 3188 } 3189 3190 // Make sure that the offset fits in uintptr_t. 3191 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3192 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset); 3193 3194 // Okay, we have now emitted all of the variable index parts to the BB that 3195 // the GEP is defined in. Loop over all of the using instructions, inserting 3196 // an "add Ptr, ConstantOffset" into each block that uses it and update the 3197 // instruction to use the newly computed value, making GEPI dead. When the 3198 // user is a load or store instruction address, we emit the add into the user 3199 // block, otherwise we use a canonical version right next to the gep (these 3200 // won't be foldable as addresses, so we might as well share the computation). 3201 3202 std::map<BasicBlock*,Instruction*> InsertedExprs; 3203 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3204 3205 // Finally, the GEP is dead, remove it. 3206 GEPI->eraseFromParent(); 3207 3208 return true; 3209} 3210 3211bool SelectionDAGISel::runOnFunction(Function &Fn) { 3212 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 3213 RegMap = MF.getSSARegMap(); 3214 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n"); 3215 3216 // First, split all critical edges for PHI nodes with incoming values that are 3217 // constants, this way the load of the constant into a vreg will not be placed 3218 // into MBBs that are used some other way. 3219 // 3220 // In this pass we also look for GEP and cast instructions that are used 3221 // across basic blocks and rewrite them to improve basic-block-at-a-time 3222 // selection. 3223 // 3224 // 3225 bool MadeChange = true; 3226 while (MadeChange) { 3227 MadeChange = false; 3228 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 3229 PHINode *PN; 3230 BasicBlock::iterator BBI; 3231 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI) 3232 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) 3233 if (isa<Constant>(PN->getIncomingValue(i))) 3234 SplitCriticalEdge(PN->getIncomingBlock(i), BB); 3235 3236 for (BasicBlock::iterator E = BB->end(); BBI != E; ) { 3237 Instruction *I = BBI++; 3238 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) { 3239 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData()); 3240 } else if (CastInst *CI = dyn_cast<CastInst>(I)) { 3241 // If this is a noop copy, sink it into user blocks to reduce the number 3242 // of virtual registers that must be created and coallesced. 3243 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); 3244 MVT::ValueType DstVT = TLI.getValueType(CI->getType()); 3245 3246 // This is an fp<->int conversion? 3247 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT)) 3248 continue; 3249 3250 // If this is an extension, it will be a zero or sign extension, which 3251 // isn't a noop. 3252 if (SrcVT < DstVT) continue; 3253 3254 // If these values will be promoted, find out what they will be promoted 3255 // to. This helps us consider truncates on PPC as noop copies when they 3256 // are. 3257 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) 3258 SrcVT = TLI.getTypeToTransformTo(SrcVT); 3259 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) 3260 DstVT = TLI.getTypeToTransformTo(DstVT); 3261 3262 // If, after promotion, these are the same types, this is a noop copy. 3263 if (SrcVT == DstVT) 3264 MadeChange |= OptimizeNoopCopyExpression(CI); 3265 } 3266 } 3267 } 3268 } 3269 3270 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 3271 3272 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 3273 SelectBasicBlock(I, MF, FuncInfo); 3274 3275 return true; 3276} 3277 3278 3279SDOperand SelectionDAGISel:: 3280CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) { 3281 SDOperand Op = SDL.getValue(V); 3282 assert((Op.getOpcode() != ISD::CopyFromReg || 3283 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 3284 "Copy from a reg to the same reg!"); 3285 3286 // If this type is not legal, we must make sure to not create an invalid 3287 // register use. 3288 MVT::ValueType SrcVT = Op.getValueType(); 3289 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 3290 SelectionDAG &DAG = SDL.DAG; 3291 if (SrcVT == DestVT) { 3292 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 3293 } else if (SrcVT == MVT::Vector) { 3294 // Handle copies from generic vectors to registers. 3295 MVT::ValueType PTyElementVT, PTyLegalElementVT; 3296 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()), 3297 PTyElementVT, PTyLegalElementVT); 3298 3299 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 3300 // MVT::Vector type. 3301 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 3302 DAG.getConstant(NE, MVT::i32), 3303 DAG.getValueType(PTyElementVT)); 3304 3305 // Loop over all of the elements of the resultant vector, 3306 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 3307 // copying them into output registers. 3308 std::vector<SDOperand> OutChains; 3309 SDOperand Root = SDL.getRoot(); 3310 for (unsigned i = 0; i != NE; ++i) { 3311 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 3312 Op, DAG.getConstant(i, TLI.getPointerTy())); 3313 if (PTyElementVT == PTyLegalElementVT) { 3314 // Elements are legal. 3315 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3316 } else if (PTyLegalElementVT > PTyElementVT) { 3317 // Elements are promoted. 3318 if (MVT::isFloatingPoint(PTyLegalElementVT)) 3319 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 3320 else 3321 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 3322 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3323 } else { 3324 // Elements are expanded. 3325 // The src value is expanded into multiple registers. 3326 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3327 Elt, DAG.getConstant(0, TLI.getPointerTy())); 3328 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3329 Elt, DAG.getConstant(1, TLI.getPointerTy())); 3330 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 3331 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 3332 } 3333 } 3334 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains); 3335 } else if (SrcVT < DestVT) { 3336 // The src value is promoted to the register. 3337 if (MVT::isFloatingPoint(SrcVT)) 3338 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 3339 else 3340 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 3341 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 3342 } else { 3343 // The src value is expanded into multiple registers. 3344 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3345 Op, DAG.getConstant(0, TLI.getPointerTy())); 3346 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3347 Op, DAG.getConstant(1, TLI.getPointerTy())); 3348 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo); 3349 return DAG.getCopyToReg(Op, Reg+1, Hi); 3350 } 3351} 3352 3353void SelectionDAGISel:: 3354LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 3355 std::vector<SDOperand> &UnorderedChains) { 3356 // If this is the entry block, emit arguments. 3357 Function &F = *BB->getParent(); 3358 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 3359 SDOperand OldRoot = SDL.DAG.getRoot(); 3360 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 3361 3362 unsigned a = 0; 3363 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 3364 AI != E; ++AI, ++a) 3365 if (!AI->use_empty()) { 3366 SDL.setValue(AI, Args[a]); 3367 3368 // If this argument is live outside of the entry block, insert a copy from 3369 // whereever we got it to the vreg that other BB's will reference it as. 3370 if (FuncInfo.ValueMap.count(AI)) { 3371 SDOperand Copy = 3372 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 3373 UnorderedChains.push_back(Copy); 3374 } 3375 } 3376 3377 // Finally, if the target has anything special to do, allow it to do so. 3378 // FIXME: this should insert code into the DAG! 3379 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 3380} 3381 3382void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 3383 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 3384 FunctionLoweringInfo &FuncInfo) { 3385 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 3386 3387 std::vector<SDOperand> UnorderedChains; 3388 3389 // Lower any arguments needed in this block if this is the entry block. 3390 if (LLVMBB == &LLVMBB->getParent()->front()) 3391 LowerArguments(LLVMBB, SDL, UnorderedChains); 3392 3393 BB = FuncInfo.MBBMap[LLVMBB]; 3394 SDL.setCurrentBasicBlock(BB); 3395 3396 // Lower all of the non-terminator instructions. 3397 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 3398 I != E; ++I) 3399 SDL.visit(*I); 3400 3401 // Ensure that all instructions which are used outside of their defining 3402 // blocks are available as virtual registers. 3403 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 3404 if (!I->use_empty() && !isa<PHINode>(I)) { 3405 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 3406 if (VMI != FuncInfo.ValueMap.end()) 3407 UnorderedChains.push_back( 3408 CopyValueToVirtualRegister(SDL, I, VMI->second)); 3409 } 3410 3411 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 3412 // ensure constants are generated when needed. Remember the virtual registers 3413 // that need to be added to the Machine PHI nodes as input. We cannot just 3414 // directly add them, because expansion might result in multiple MBB's for one 3415 // BB. As such, the start of the BB might correspond to a different MBB than 3416 // the end. 3417 // 3418 3419 // Emit constants only once even if used by multiple PHI nodes. 3420 std::map<Constant*, unsigned> ConstantsOut; 3421 3422 // Check successor nodes PHI nodes that expect a constant to be available from 3423 // this block. 3424 TerminatorInst *TI = LLVMBB->getTerminator(); 3425 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 3426 BasicBlock *SuccBB = TI->getSuccessor(succ); 3427 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin(); 3428 PHINode *PN; 3429 3430 // At this point we know that there is a 1-1 correspondence between LLVM PHI 3431 // nodes and Machine PHI nodes, but the incoming operands have not been 3432 // emitted yet. 3433 for (BasicBlock::iterator I = SuccBB->begin(); 3434 (PN = dyn_cast<PHINode>(I)); ++I) 3435 if (!PN->use_empty()) { 3436 unsigned Reg; 3437 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 3438 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 3439 unsigned &RegOut = ConstantsOut[C]; 3440 if (RegOut == 0) { 3441 RegOut = FuncInfo.CreateRegForValue(C); 3442 UnorderedChains.push_back( 3443 CopyValueToVirtualRegister(SDL, C, RegOut)); 3444 } 3445 Reg = RegOut; 3446 } else { 3447 Reg = FuncInfo.ValueMap[PHIOp]; 3448 if (Reg == 0) { 3449 assert(isa<AllocaInst>(PHIOp) && 3450 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 3451 "Didn't codegen value into a register!??"); 3452 Reg = FuncInfo.CreateRegForValue(PHIOp); 3453 UnorderedChains.push_back( 3454 CopyValueToVirtualRegister(SDL, PHIOp, Reg)); 3455 } 3456 } 3457 3458 // Remember that this register needs to added to the machine PHI node as 3459 // the input for this MBB. 3460 MVT::ValueType VT = TLI.getValueType(PN->getType()); 3461 unsigned NumElements; 3462 if (VT != MVT::Vector) 3463 NumElements = TLI.getNumElements(VT); 3464 else { 3465 MVT::ValueType VT1,VT2; 3466 NumElements = 3467 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 3468 VT1, VT2); 3469 } 3470 for (unsigned i = 0, e = NumElements; i != e; ++i) 3471 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 3472 } 3473 } 3474 ConstantsOut.clear(); 3475 3476 // Turn all of the unordered chains into one factored node. 3477 if (!UnorderedChains.empty()) { 3478 SDOperand Root = SDL.getRoot(); 3479 if (Root.getOpcode() != ISD::EntryToken) { 3480 unsigned i = 0, e = UnorderedChains.size(); 3481 for (; i != e; ++i) { 3482 assert(UnorderedChains[i].Val->getNumOperands() > 1); 3483 if (UnorderedChains[i].Val->getOperand(0) == Root) 3484 break; // Don't add the root if we already indirectly depend on it. 3485 } 3486 3487 if (i == e) 3488 UnorderedChains.push_back(Root); 3489 } 3490 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains)); 3491 } 3492 3493 // Lower the terminator after the copies are emitted. 3494 SDL.visit(*LLVMBB->getTerminator()); 3495 3496 // Copy over any CaseBlock records that may now exist due to SwitchInst 3497 // lowering, as well as any jump table information. 3498 SwitchCases.clear(); 3499 SwitchCases = SDL.SwitchCases; 3500 JT = SDL.JT; 3501 3502 // Make sure the root of the DAG is up-to-date. 3503 DAG.setRoot(SDL.getRoot()); 3504} 3505 3506void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 3507 // Run the DAG combiner in pre-legalize mode. 3508 DAG.Combine(false); 3509 3510 DEBUG(std::cerr << "Lowered selection DAG:\n"); 3511 DEBUG(DAG.dump()); 3512 3513 // Second step, hack on the DAG until it only uses operations and types that 3514 // the target supports. 3515 DAG.Legalize(); 3516 3517 DEBUG(std::cerr << "Legalized selection DAG:\n"); 3518 DEBUG(DAG.dump()); 3519 3520 // Run the DAG combiner in post-legalize mode. 3521 DAG.Combine(true); 3522 3523 if (ViewISelDAGs) DAG.viewGraph(); 3524 3525 // Third, instruction select all of the operations to machine code, adding the 3526 // code to the MachineBasicBlock. 3527 InstructionSelectBasicBlock(DAG); 3528 3529 DEBUG(std::cerr << "Selected machine code:\n"); 3530 DEBUG(BB->dump()); 3531} 3532 3533void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 3534 FunctionLoweringInfo &FuncInfo) { 3535 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 3536 { 3537 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3538 CurDAG = &DAG; 3539 3540 // First step, lower LLVM code to some DAG. This DAG may use operations and 3541 // types that are not supported by the target. 3542 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 3543 3544 // Second step, emit the lowered DAG as machine code. 3545 CodeGenAndEmitDAG(DAG); 3546 } 3547 3548 // Next, now that we know what the last MBB the LLVM BB expanded is, update 3549 // PHI nodes in successors. 3550 if (SwitchCases.empty() && JT.Reg == 0) { 3551 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 3552 MachineInstr *PHI = PHINodesToUpdate[i].first; 3553 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3554 "This is not a machine PHI node that we are updating!"); 3555 PHI->addRegOperand(PHINodesToUpdate[i].second); 3556 PHI->addMachineBasicBlockOperand(BB); 3557 } 3558 return; 3559 } 3560 3561 // If the JumpTable record is filled in, then we need to emit a jump table. 3562 // Updating the PHI nodes is tricky in this case, since we need to determine 3563 // whether the PHI is a successor of the range check MBB or the jump table MBB 3564 if (JT.Reg) { 3565 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch"); 3566 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3567 CurDAG = &SDAG; 3568 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 3569 MachineBasicBlock *RangeBB = BB; 3570 // Set the current basic block to the mbb we wish to insert the code into 3571 BB = JT.MBB; 3572 SDL.setCurrentBasicBlock(BB); 3573 // Emit the code 3574 SDL.visitJumpTable(JT); 3575 SDAG.setRoot(SDL.getRoot()); 3576 CodeGenAndEmitDAG(SDAG); 3577 // Update PHI Nodes 3578 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 3579 MachineInstr *PHI = PHINodesToUpdate[pi].first; 3580 MachineBasicBlock *PHIBB = PHI->getParent(); 3581 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3582 "This is not a machine PHI node that we are updating!"); 3583 if (PHIBB == JT.Default) { 3584 PHI->addRegOperand(PHINodesToUpdate[pi].second); 3585 PHI->addMachineBasicBlockOperand(RangeBB); 3586 } 3587 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 3588 PHI->addRegOperand(PHINodesToUpdate[pi].second); 3589 PHI->addMachineBasicBlockOperand(BB); 3590 } 3591 } 3592 return; 3593 } 3594 3595 // If we generated any switch lowering information, build and codegen any 3596 // additional DAGs necessary. 3597 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 3598 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3599 CurDAG = &SDAG; 3600 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 3601 // Set the current basic block to the mbb we wish to insert the code into 3602 BB = SwitchCases[i].ThisBB; 3603 SDL.setCurrentBasicBlock(BB); 3604 // Emit the code 3605 SDL.visitSwitchCase(SwitchCases[i]); 3606 SDAG.setRoot(SDL.getRoot()); 3607 CodeGenAndEmitDAG(SDAG); 3608 // Iterate over the phi nodes, if there is a phi node in a successor of this 3609 // block (for instance, the default block), then add a pair of operands to 3610 // the phi node for this block, as if we were coming from the original 3611 // BB before switch expansion. 3612 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 3613 MachineInstr *PHI = PHINodesToUpdate[pi].first; 3614 MachineBasicBlock *PHIBB = PHI->getParent(); 3615 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3616 "This is not a machine PHI node that we are updating!"); 3617 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) { 3618 PHI->addRegOperand(PHINodesToUpdate[pi].second); 3619 PHI->addMachineBasicBlockOperand(BB); 3620 } 3621 } 3622 } 3623} 3624 3625 3626//===----------------------------------------------------------------------===// 3627/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 3628/// target node in the graph. 3629void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 3630 if (ViewSchedDAGs) DAG.viewGraph(); 3631 3632 static RegisterScheduler::FunctionPassCtor Ctor = 3633 RegisterScheduler::getDefault(); 3634 3635 if (!Ctor) { 3636 Ctor = RegisterScheduler::FindCtor(ISHeuristic); 3637 RegisterScheduler::setDefault(Ctor); 3638 } 3639 3640 assert(Ctor && "No instruction scheduler found"); 3641 ScheduleDAG *SL = Ctor(this, &DAG, BB); 3642 BB = SL->Run(); 3643 delete SL; 3644} 3645 3646 3647HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 3648 return new HazardRecognizer(); 3649} 3650 3651 3652/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 3653/// by tblgen. Others should not call it. 3654void SelectionDAGISel:: 3655SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 3656 std::vector<SDOperand> InOps; 3657 std::swap(InOps, Ops); 3658 3659 Ops.push_back(InOps[0]); // input chain. 3660 Ops.push_back(InOps[1]); // input asm string. 3661 3662 unsigned i = 2, e = InOps.size(); 3663 if (InOps[e-1].getValueType() == MVT::Flag) 3664 --e; // Don't process a flag operand if it is here. 3665 3666 while (i != e) { 3667 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 3668 if ((Flags & 7) != 4 /*MEM*/) { 3669 // Just skip over this operand, copying the operands verbatim. 3670 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 3671 i += (Flags >> 3) + 1; 3672 } else { 3673 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 3674 // Otherwise, this is a memory operand. Ask the target to select it. 3675 std::vector<SDOperand> SelOps; 3676 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 3677 std::cerr << "Could not match memory address. Inline asm failure!\n"; 3678 exit(1); 3679 } 3680 3681 // Add this to the output node. 3682 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32)); 3683 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 3684 i += 2; 3685 } 3686 } 3687 3688 // Add the flag input back if present. 3689 if (e != InOps.size()) 3690 Ops.push_back(InOps.back()); 3691} 3692