SelectionDAGISel.cpp revision 9851e78217bb61e1626440fb09204bee37e22728
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 CodeGenOpt::Level OptLevel) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (OptLevel == CodeGenOpt::None) 143 return createFastDAGScheduler(IS, OptLevel); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, OptLevel); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, OptLevel); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and this method is called to expand it into a sequence of 157// instructions, potentially also creating new basic blocks and control flow. 158// When new basic blocks are inserted and the edges from MBB to its successors 159// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 160// DenseMap. 161MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 162 MachineBasicBlock *MBB, 163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 164#ifndef NDEBUG 165 dbgs() << "If a target marks an instruction with " 166 "'usesCustomInserter', it must implement " 167 "TargetLowering::EmitInstrWithCustomInserter!"; 168#endif 169 llvm_unreachable(0); 170 return 0; 171} 172 173/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 174/// physical register has only a single copy use, then coalesced the copy 175/// if possible. 176static void EmitLiveInCopy(MachineBasicBlock *MBB, 177 MachineBasicBlock::iterator &InsertPos, 178 unsigned VirtReg, unsigned PhysReg, 179 const TargetRegisterClass *RC, 180 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 181 const MachineRegisterInfo &MRI, 182 const TargetRegisterInfo &TRI, 183 const TargetInstrInfo &TII) { 184 unsigned NumUses = 0; 185 MachineInstr *UseMI = NULL; 186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 187 UE = MRI.use_end(); UI != UE; ++UI) { 188 UseMI = &*UI; 189 if (++NumUses > 1) 190 break; 191 } 192 193 // If the number of uses is not one, or the use is not a move instruction, 194 // don't coalesce. Also, only coalesce away a virtual register to virtual 195 // register copy. 196 bool Coalesced = false; 197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 198 if (NumUses == 1 && 199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 200 TargetRegisterInfo::isVirtualRegister(DstReg)) { 201 VirtReg = DstReg; 202 Coalesced = true; 203 } 204 205 // Now find an ideal location to insert the copy. 206 MachineBasicBlock::iterator Pos = InsertPos; 207 while (Pos != MBB->begin()) { 208 MachineInstr *PrevMI = prior(Pos); 209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 210 // copyRegToReg might emit multiple instructions to do a copy. 211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 213 // This is what the BB looks like right now: 214 // r1024 = mov r0 215 // ... 216 // r1 = mov r1024 217 // 218 // We want to insert "r1025 = mov r1". Inserting this copy below the 219 // move to r1024 makes it impossible for that move to be coalesced. 220 // 221 // r1025 = mov r1 222 // r1024 = mov r0 223 // ... 224 // r1 = mov 1024 225 // r2 = mov 1025 226 break; // Woot! Found a good location. 227 --Pos; 228 } 229 230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 231 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 232 (void) Emitted; 233 234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 235 if (Coalesced) { 236 if (&*InsertPos == UseMI) ++InsertPos; 237 MBB->erase(UseMI); 238 } 239} 240 241/// EmitLiveInCopies - If this is the first basic block in the function, 242/// and if it has live ins that need to be copied into vregs, emit the 243/// copies into the block. 244static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 245 const MachineRegisterInfo &MRI, 246 const TargetRegisterInfo &TRI, 247 const TargetInstrInfo &TII) { 248 if (SchedLiveInCopies) { 249 // Emit the copies at a heuristically-determined location in the block. 250 DenseMap<MachineInstr*, unsigned> CopyRegMap; 251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 253 E = MRI.livein_end(); LI != E; ++LI) 254 if (LI->second) { 255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 257 RC, CopyRegMap, MRI, TRI, TII); 258 } 259 } else { 260 // Emit the copies into the top of the block. 261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 262 E = MRI.livein_end(); LI != E; ++LI) 263 if (LI->second) { 264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 266 LI->second, LI->first, RC, RC); 267 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 268 (void) Emitted; 269 } 270 } 271} 272 273//===----------------------------------------------------------------------===// 274// SelectionDAGISel code 275//===----------------------------------------------------------------------===// 276 277SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 279 FuncInfo(new FunctionLoweringInfo(TLI)), 280 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 282 GFI(), 283 OptLevel(OL), 284 DAGSize(0) 285{} 286 287SelectionDAGISel::~SelectionDAGISel() { 288 delete SDB; 289 delete CurDAG; 290 delete FuncInfo; 291} 292 293unsigned SelectionDAGISel::MakeReg(EVT VT) { 294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 295} 296 297void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 298 AU.addRequired<AliasAnalysis>(); 299 AU.addPreserved<AliasAnalysis>(); 300 AU.addRequired<GCModuleInfo>(); 301 AU.addPreserved<GCModuleInfo>(); 302 AU.addRequired<DwarfWriter>(); 303 AU.addPreserved<DwarfWriter>(); 304 MachineFunctionPass::getAnalysisUsage(AU); 305} 306 307bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 308 Function &Fn = *mf.getFunction(); 309 310 // Do some sanity-checking on the command-line options. 311 assert((!EnableFastISelVerbose || EnableFastISel) && 312 "-fast-isel-verbose requires -fast-isel"); 313 assert((!EnableFastISelAbort || EnableFastISel) && 314 "-fast-isel-abort requires -fast-isel"); 315 316 // Get alias analysis for load/store combining. 317 AA = &getAnalysis<AliasAnalysis>(); 318 319 MF = &mf; 320 const TargetInstrInfo &TII = *TM.getInstrInfo(); 321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 322 323 if (Fn.hasGC()) 324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 325 else 326 GFI = 0; 327 RegInfo = &MF->getRegInfo(); 328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 329 330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 332 CurDAG->init(*MF, MMI, DW); 333 FuncInfo->set(Fn, *MF, EnableFastISel); 334 SDB->init(GFI, *AA); 335 336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 338 // Mark landing pad. 339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 340 341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 342 343 // If the first basic block in the function has live ins that need to be 344 // copied into vregs, emit the copies into the top of the block before 345 // emitting the code for the block. 346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 347 348 // Add function live-ins to entry block live-in set. 349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 350 E = RegInfo->livein_end(); I != E; ++I) 351 MF->begin()->addLiveIn(I->first); 352 353#ifndef NDEBUG 354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 355 "Not all catch info was assigned to a landing pad!"); 356#endif 357 358 FuncInfo->clear(); 359 360 return true; 361} 362 363/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 364/// attached with this instruction. 365static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 366 SelectionDAGBuilder *SDB, 367 FastISel *FastIS, MachineFunction *MF) { 368 if (isa<DbgInfoIntrinsic>(I)) return; 369 370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 371 DILocation DILoc(Dbg); 372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 373 374 SDB->setCurDebugLoc(Loc); 375 376 if (FastIS) 377 FastIS->setCurDebugLoc(Loc); 378 379 // If the function doesn't have a default debug location yet, set 380 // it. This is kind of a hack. 381 if (MF->getDefaultDebugLoc().isUnknown()) 382 MF->setDefaultDebugLoc(Loc); 383 } 384} 385 386/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 387static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 389 if (FastIS) 390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 391} 392 393void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 394 BasicBlock::iterator Begin, 395 BasicBlock::iterator End, 396 bool &HadTailCall) { 397 SDB->setCurrentBasicBlock(BB); 398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 399 400 // Lower all of the non-terminator instructions. If a call is emitted 401 // as a tail call, cease emitting nodes for this block. 402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 404 405 if (!isa<TerminatorInst>(I)) { 406 SDB->visit(*I); 407 408 // Set the current debug location back to "unknown" so that it doesn't 409 // spuriously apply to subsequent instructions. 410 ResetDebugLoc(SDB, 0); 411 } 412 } 413 414 if (!SDB->HasTailCall) { 415 // Ensure that all instructions which are used outside of their defining 416 // blocks are available as virtual registers. Invoke is handled elsewhere. 417 for (BasicBlock::iterator I = Begin; I != End; ++I) 418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 419 SDB->CopyToExportRegsIfNeeded(I); 420 421 // Handle PHI nodes in successor blocks. 422 if (End == LLVMBB->end()) { 423 HandlePHINodesInSuccessorBlocks(LLVMBB); 424 425 // Lower the terminator after the copies are emitted. 426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 427 SDB->visit(*LLVMBB->getTerminator()); 428 ResetDebugLoc(SDB, 0); 429 } 430 } 431 432 // Make sure the root of the DAG is up-to-date. 433 CurDAG->setRoot(SDB->getControlRoot()); 434 435 // Final step, emit the lowered DAG as machine code. 436 CodeGenAndEmitDAG(); 437 HadTailCall = SDB->HasTailCall; 438 SDB->clear(); 439} 440 441namespace { 442/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 443/// nodes from the worklist. 444class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 445 SmallVector<SDNode*, 128> &Worklist; 446public: 447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {} 448 449 virtual void NodeDeleted(SDNode *N, SDNode *E) { 450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 451 Worklist.end()); 452 } 453 454 virtual void NodeUpdated(SDNode *N) { 455 // Ignore updates. 456 } 457}; 458} 459 460/// TrivialTruncElim - Eliminate some trivial nops that can result from 461/// ShrinkDemandedOps: (trunc (ext n)) -> n. 462static bool TrivialTruncElim(SDValue Op, 463 TargetLowering::TargetLoweringOpt &TLO) { 464 SDValue N0 = Op.getOperand(0); 465 EVT VT = Op.getValueType(); 466 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 467 N0.getOpcode() == ISD::SIGN_EXTEND || 468 N0.getOpcode() == ISD::ANY_EXTEND) && 469 N0.getOperand(0).getValueType() == VT) { 470 return TLO.CombineTo(Op, N0.getOperand(0)); 471 } 472 return false; 473} 474 475/// ShrinkDemandedOps - A late transformation pass that shrink expressions 476/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 477/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 478void SelectionDAGISel::ShrinkDemandedOps() { 479 SmallVector<SDNode*, 128> Worklist; 480 481 // Add all the dag nodes to the worklist. 482 Worklist.reserve(CurDAG->allnodes_size()); 483 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 484 E = CurDAG->allnodes_end(); I != E; ++I) 485 Worklist.push_back(I); 486 487 APInt Mask; 488 APInt KnownZero; 489 APInt KnownOne; 490 491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 492 while (!Worklist.empty()) { 493 SDNode *N = Worklist.pop_back_val(); 494 495 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 496 CurDAG->DeleteNode(N); 497 continue; 498 } 499 500 // Run ShrinkDemandedOp on scalar binary operations. 501 if (N->getNumValues() == 1 && 502 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) { 503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 504 APInt Demanded = APInt::getAllOnesValue(BitWidth); 505 APInt KnownZero, KnownOne; 506 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 507 KnownZero, KnownOne, TLO) || 508 (N->getOpcode() == ISD::TRUNCATE && 509 TrivialTruncElim(SDValue(N, 0), TLO))) { 510 // Revisit the node. 511 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 512 Worklist.end()); 513 Worklist.push_back(N); 514 515 // Replace the old value with the new one. 516 DEBUG(errs() << "\nReplacing "; 517 TLO.Old.getNode()->dump(CurDAG); 518 errs() << "\nWith: "; 519 TLO.New.getNode()->dump(CurDAG); 520 errs() << '\n'); 521 522 Worklist.push_back(TLO.New.getNode()); 523 524 SDOPsWorkListRemover DeadNodes(Worklist); 525 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 526 527 if (TLO.Old.getNode()->use_empty()) { 528 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 529 i != e; ++i) { 530 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 531 if (OpNode->hasOneUse()) { 532 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 533 OpNode), Worklist.end()); 534 Worklist.push_back(OpNode); 535 } 536 } 537 538 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 539 TLO.Old.getNode()), Worklist.end()); 540 CurDAG->DeleteNode(TLO.Old.getNode()); 541 } 542 } 543 } 544 } 545} 546 547void SelectionDAGISel::ComputeLiveOutVRegInfo() { 548 SmallPtrSet<SDNode*, 128> VisitedNodes; 549 SmallVector<SDNode*, 128> Worklist; 550 551 Worklist.push_back(CurDAG->getRoot().getNode()); 552 553 APInt Mask; 554 APInt KnownZero; 555 APInt KnownOne; 556 557 do { 558 SDNode *N = Worklist.pop_back_val(); 559 560 // If we've already seen this node, ignore it. 561 if (!VisitedNodes.insert(N)) 562 continue; 563 564 // Otherwise, add all chain operands to the worklist. 565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 566 if (N->getOperand(i).getValueType() == MVT::Other) 567 Worklist.push_back(N->getOperand(i).getNode()); 568 569 // If this is a CopyToReg with a vreg dest, process it. 570 if (N->getOpcode() != ISD::CopyToReg) 571 continue; 572 573 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 574 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 575 continue; 576 577 // Ignore non-scalar or non-integer values. 578 SDValue Src = N->getOperand(2); 579 EVT SrcVT = Src.getValueType(); 580 if (!SrcVT.isInteger() || SrcVT.isVector()) 581 continue; 582 583 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 584 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 585 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 586 587 // Only install this information if it tells us something. 588 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 589 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 590 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 591 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 592 FunctionLoweringInfo::LiveOutInfo &LOI = 593 FuncInfo->LiveOutRegInfo[DestReg]; 594 LOI.NumSignBits = NumSignBits; 595 LOI.KnownOne = KnownOne; 596 LOI.KnownZero = KnownZero; 597 } 598 } while (!Worklist.empty()); 599} 600 601void SelectionDAGISel::CodeGenAndEmitDAG() { 602 std::string GroupName; 603 if (TimePassesIsEnabled) 604 GroupName = "Instruction Selection and Scheduling"; 605 std::string BlockName; 606 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 607 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 608 ViewSUnitDAGs) 609 BlockName = MF->getFunction()->getNameStr() + ":" + 610 BB->getBasicBlock()->getNameStr(); 611 612 DEBUG(dbgs() << "Initial selection DAG:\n"); 613 DEBUG(CurDAG->dump()); 614 615 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 616 617 // Run the DAG combiner in pre-legalize mode. 618 if (TimePassesIsEnabled) { 619 NamedRegionTimer T("DAG Combining 1", GroupName); 620 CurDAG->Combine(Unrestricted, *AA, OptLevel); 621 } else { 622 CurDAG->Combine(Unrestricted, *AA, OptLevel); 623 } 624 625 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 626 DEBUG(CurDAG->dump()); 627 628 // Second step, hack on the DAG until it only uses operations and types that 629 // the target supports. 630 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 631 BlockName); 632 633 bool Changed; 634 if (TimePassesIsEnabled) { 635 NamedRegionTimer T("Type Legalization", GroupName); 636 Changed = CurDAG->LegalizeTypes(); 637 } else { 638 Changed = CurDAG->LegalizeTypes(); 639 } 640 641 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 642 DEBUG(CurDAG->dump()); 643 644 if (Changed) { 645 if (ViewDAGCombineLT) 646 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 647 648 // Run the DAG combiner in post-type-legalize mode. 649 if (TimePassesIsEnabled) { 650 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 651 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 652 } else { 653 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 654 } 655 656 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 657 DEBUG(CurDAG->dump()); 658 } 659 660 if (TimePassesIsEnabled) { 661 NamedRegionTimer T("Vector Legalization", GroupName); 662 Changed = CurDAG->LegalizeVectors(); 663 } else { 664 Changed = CurDAG->LegalizeVectors(); 665 } 666 667 if (Changed) { 668 if (TimePassesIsEnabled) { 669 NamedRegionTimer T("Type Legalization 2", GroupName); 670 CurDAG->LegalizeTypes(); 671 } else { 672 CurDAG->LegalizeTypes(); 673 } 674 675 if (ViewDAGCombineLT) 676 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 677 678 // Run the DAG combiner in post-type-legalize mode. 679 if (TimePassesIsEnabled) { 680 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 681 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 682 } else { 683 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 684 } 685 686 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 687 DEBUG(CurDAG->dump()); 688 } 689 690 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 691 692 if (TimePassesIsEnabled) { 693 NamedRegionTimer T("DAG Legalization", GroupName); 694 CurDAG->Legalize(OptLevel); 695 } else { 696 CurDAG->Legalize(OptLevel); 697 } 698 699 DEBUG(dbgs() << "Legalized selection DAG:\n"); 700 DEBUG(CurDAG->dump()); 701 702 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 703 704 // Run the DAG combiner in post-legalize mode. 705 if (TimePassesIsEnabled) { 706 NamedRegionTimer T("DAG Combining 2", GroupName); 707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 708 } else { 709 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 710 } 711 712 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 713 DEBUG(CurDAG->dump()); 714 715 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 716 717 if (OptLevel != CodeGenOpt::None) { 718 ShrinkDemandedOps(); 719 ComputeLiveOutVRegInfo(); 720 } 721 722 // Third, instruction select all of the operations to machine code, adding the 723 // code to the MachineBasicBlock. 724 if (TimePassesIsEnabled) { 725 NamedRegionTimer T("Instruction Selection", GroupName); 726 DoInstructionSelection(); 727 } else { 728 DoInstructionSelection(); 729 } 730 731 DEBUG(dbgs() << "Selected selection DAG:\n"); 732 DEBUG(CurDAG->dump()); 733 734 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 735 736 // Schedule machine code. 737 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 738 if (TimePassesIsEnabled) { 739 NamedRegionTimer T("Instruction Scheduling", GroupName); 740 Scheduler->Run(CurDAG, BB, BB->end()); 741 } else { 742 Scheduler->Run(CurDAG, BB, BB->end()); 743 } 744 745 if (ViewSUnitDAGs) Scheduler->viewGraph(); 746 747 // Emit machine code to BB. This can change 'BB' to the last block being 748 // inserted into. 749 if (TimePassesIsEnabled) { 750 NamedRegionTimer T("Instruction Creation", GroupName); 751 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 752 } else { 753 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 754 } 755 756 // Free the scheduler state. 757 if (TimePassesIsEnabled) { 758 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 759 delete Scheduler; 760 } else { 761 delete Scheduler; 762 } 763 764 DEBUG(dbgs() << "Selected machine code:\n"); 765 DEBUG(BB->dump()); 766} 767 768void SelectionDAGISel::DoInstructionSelection() { 769 DEBUG(errs() << "===== Instruction selection begins:\n"); 770 771 PreprocessISelDAG(); 772 773 // Select target instructions for the DAG. 774 { 775 // Number all nodes with a topological order and set DAGSize. 776 DAGSize = CurDAG->AssignTopologicalOrder(); 777 778 // Create a dummy node (which is not added to allnodes), that adds 779 // a reference to the root node, preventing it from being deleted, 780 // and tracking any changes of the root. 781 HandleSDNode Dummy(CurDAG->getRoot()); 782 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 783 ++ISelPosition; 784 785 // The AllNodes list is now topological-sorted. Visit the 786 // nodes by starting at the end of the list (the root of the 787 // graph) and preceding back toward the beginning (the entry 788 // node). 789 while (ISelPosition != CurDAG->allnodes_begin()) { 790 SDNode *Node = --ISelPosition; 791 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 792 // but there are currently some corner cases that it misses. Also, this 793 // makes it theoretically possible to disable the DAGCombiner. 794 if (Node->use_empty()) 795 continue; 796 797 SDNode *ResNode = Select(Node); 798 799 // FIXME: This is pretty gross. 'Select' should be changed to not return 800 // anything at all and this code should be nuked with a tactical strike. 801 802 // If node should not be replaced, continue with the next one. 803 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 804 continue; 805 // Replace node. 806 if (ResNode) 807 ReplaceUses(Node, ResNode); 808 809 // If after the replacement this node is not used any more, 810 // remove this dead node. 811 if (Node->use_empty()) { // Don't delete EntryToken, etc. 812 ISelUpdater ISU(ISelPosition); 813 CurDAG->RemoveDeadNode(Node, &ISU); 814 } 815 } 816 817 CurDAG->setRoot(Dummy.getValue()); 818 } 819 DEBUG(errs() << "===== Instruction selection ends:\n"); 820 821 PostprocessISelDAG(); 822 823 // FIXME: This shouldn't be needed, remove it. 824 CurDAG->RemoveDeadNodes(); 825} 826 827 828void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 829 MachineFunction &MF, 830 MachineModuleInfo *MMI, 831 DwarfWriter *DW, 832 const TargetInstrInfo &TII) { 833 // Initialize the Fast-ISel state, if needed. 834 FastISel *FastIS = 0; 835 if (EnableFastISel) 836 FastIS = TLI.createFastISel(MF, MMI, DW, 837 FuncInfo->ValueMap, 838 FuncInfo->MBBMap, 839 FuncInfo->StaticAllocaMap 840#ifndef NDEBUG 841 , FuncInfo->CatchInfoLost 842#endif 843 ); 844 845 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 846 847 // Iterate over all basic blocks in the function. 848 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 849 BasicBlock *LLVMBB = &*I; 850 BB = FuncInfo->MBBMap[LLVMBB]; 851 852 BasicBlock::iterator const Begin = LLVMBB->begin(); 853 BasicBlock::iterator const End = LLVMBB->end(); 854 BasicBlock::iterator BI = Begin; 855 856 // Lower any arguments needed in this block if this is the entry block. 857 bool SuppressFastISel = false; 858 if (LLVMBB == &Fn.getEntryBlock()) { 859 LowerArguments(LLVMBB); 860 861 // If any of the arguments has the byval attribute, forgo 862 // fast-isel in the entry block. 863 if (FastIS) { 864 unsigned j = 1; 865 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 866 I != E; ++I, ++j) 867 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 868 if (EnableFastISelVerbose || EnableFastISelAbort) 869 dbgs() << "FastISel skips entry block due to byval argument\n"; 870 SuppressFastISel = true; 871 break; 872 } 873 } 874 } 875 876 if (MMI && BB->isLandingPad()) { 877 // Add a label to mark the beginning of the landing pad. Deletion of the 878 // landing pad can thus be detected via the MachineModuleInfo. 879 unsigned LabelID = MMI->addLandingPad(BB); 880 881 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 882 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 883 884 // Mark exception register as live in. 885 unsigned Reg = TLI.getExceptionAddressRegister(); 886 if (Reg) BB->addLiveIn(Reg); 887 888 // Mark exception selector register as live in. 889 Reg = TLI.getExceptionSelectorRegister(); 890 if (Reg) BB->addLiveIn(Reg); 891 892 // FIXME: Hack around an exception handling flaw (PR1508): the personality 893 // function and list of typeids logically belong to the invoke (or, if you 894 // like, the basic block containing the invoke), and need to be associated 895 // with it in the dwarf exception handling tables. Currently however the 896 // information is provided by an intrinsic (eh.selector) that can be moved 897 // to unexpected places by the optimizers: if the unwind edge is critical, 898 // then breaking it can result in the intrinsics being in the successor of 899 // the landing pad, not the landing pad itself. This results 900 // in exceptions not being caught because no typeids are associated with 901 // the invoke. This may not be the only way things can go wrong, but it 902 // is the only way we try to work around for the moment. 903 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 904 905 if (Br && Br->isUnconditional()) { // Critical edge? 906 BasicBlock::iterator I, E; 907 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 908 if (isa<EHSelectorInst>(I)) 909 break; 910 911 if (I == E) 912 // No catch info found - try to extract some from the successor. 913 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 914 } 915 } 916 917 // Before doing SelectionDAG ISel, see if FastISel has been requested. 918 if (FastIS && !SuppressFastISel) { 919 // Emit code for any incoming arguments. This must happen before 920 // beginning FastISel on the entry block. 921 if (LLVMBB == &Fn.getEntryBlock()) { 922 CurDAG->setRoot(SDB->getControlRoot()); 923 CodeGenAndEmitDAG(); 924 SDB->clear(); 925 } 926 FastIS->startNewBlock(BB); 927 // Do FastISel on as many instructions as possible. 928 for (; BI != End; ++BI) { 929 // Just before the terminator instruction, insert instructions to 930 // feed PHI nodes in successor blocks. 931 if (isa<TerminatorInst>(BI)) 932 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 933 ResetDebugLoc(SDB, FastIS); 934 if (EnableFastISelVerbose || EnableFastISelAbort) { 935 dbgs() << "FastISel miss: "; 936 BI->dump(); 937 } 938 assert(!EnableFastISelAbort && 939 "FastISel didn't handle a PHI in a successor"); 940 break; 941 } 942 943 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 944 945 // Try to select the instruction with FastISel. 946 if (FastIS->SelectInstruction(BI)) { 947 ResetDebugLoc(SDB, FastIS); 948 continue; 949 } 950 951 // Clear out the debug location so that it doesn't carry over to 952 // unrelated instructions. 953 ResetDebugLoc(SDB, FastIS); 954 955 // Then handle certain instructions as single-LLVM-Instruction blocks. 956 if (isa<CallInst>(BI)) { 957 if (EnableFastISelVerbose || EnableFastISelAbort) { 958 dbgs() << "FastISel missed call: "; 959 BI->dump(); 960 } 961 962 if (!BI->getType()->isVoidTy()) { 963 unsigned &R = FuncInfo->ValueMap[BI]; 964 if (!R) 965 R = FuncInfo->CreateRegForValue(BI); 966 } 967 968 bool HadTailCall = false; 969 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 970 971 // If the call was emitted as a tail call, we're done with the block. 972 if (HadTailCall) { 973 BI = End; 974 break; 975 } 976 977 // If the instruction was codegen'd with multiple blocks, 978 // inform the FastISel object where to resume inserting. 979 FastIS->setCurrentBlock(BB); 980 continue; 981 } 982 983 // Otherwise, give up on FastISel for the rest of the block. 984 // For now, be a little lenient about non-branch terminators. 985 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 986 if (EnableFastISelVerbose || EnableFastISelAbort) { 987 dbgs() << "FastISel miss: "; 988 BI->dump(); 989 } 990 if (EnableFastISelAbort) 991 // The "fast" selector couldn't handle something and bailed. 992 // For the purpose of debugging, just abort. 993 llvm_unreachable("FastISel didn't select the entire block"); 994 } 995 break; 996 } 997 } 998 999 // Run SelectionDAG instruction selection on the remainder of the block 1000 // not handled by FastISel. If FastISel is not run, this is the entire 1001 // block. 1002 if (BI != End) { 1003 bool HadTailCall; 1004 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1005 } 1006 1007 FinishBasicBlock(); 1008 } 1009 1010 delete FastIS; 1011} 1012 1013void 1014SelectionDAGISel::FinishBasicBlock() { 1015 1016 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1017 DEBUG(BB->dump()); 1018 1019 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1020 << SDB->PHINodesToUpdate.size() << "\n"); 1021 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1022 dbgs() << "Node " << i << " : (" 1023 << SDB->PHINodesToUpdate[i].first 1024 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1025 1026 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1027 // PHI nodes in successors. 1028 if (SDB->SwitchCases.empty() && 1029 SDB->JTCases.empty() && 1030 SDB->BitTestCases.empty()) { 1031 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1032 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1033 assert(PHI->isPHI() && 1034 "This is not a machine PHI node that we are updating!"); 1035 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1036 false)); 1037 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1038 } 1039 SDB->PHINodesToUpdate.clear(); 1040 return; 1041 } 1042 1043 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1044 // Lower header first, if it wasn't already lowered 1045 if (!SDB->BitTestCases[i].Emitted) { 1046 // Set the current basic block to the mbb we wish to insert the code into 1047 BB = SDB->BitTestCases[i].Parent; 1048 SDB->setCurrentBasicBlock(BB); 1049 // Emit the code 1050 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1051 CurDAG->setRoot(SDB->getRoot()); 1052 CodeGenAndEmitDAG(); 1053 SDB->clear(); 1054 } 1055 1056 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1057 // Set the current basic block to the mbb we wish to insert the code into 1058 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1059 SDB->setCurrentBasicBlock(BB); 1060 // Emit the code 1061 if (j+1 != ej) 1062 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1063 SDB->BitTestCases[i].Reg, 1064 SDB->BitTestCases[i].Cases[j]); 1065 else 1066 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1067 SDB->BitTestCases[i].Reg, 1068 SDB->BitTestCases[i].Cases[j]); 1069 1070 1071 CurDAG->setRoot(SDB->getRoot()); 1072 CodeGenAndEmitDAG(); 1073 SDB->clear(); 1074 } 1075 1076 // Update PHI Nodes 1077 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1078 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1079 MachineBasicBlock *PHIBB = PHI->getParent(); 1080 assert(PHI->isPHI() && 1081 "This is not a machine PHI node that we are updating!"); 1082 // This is "default" BB. We have two jumps to it. From "header" BB and 1083 // from last "case" BB. 1084 if (PHIBB == SDB->BitTestCases[i].Default) { 1085 PHI->addOperand(MachineOperand:: 1086 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1087 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1088 PHI->addOperand(MachineOperand:: 1089 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1090 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1091 back().ThisBB)); 1092 } 1093 // One of "cases" BB. 1094 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1095 j != ej; ++j) { 1096 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1097 if (cBB->isSuccessor(PHIBB)) { 1098 PHI->addOperand(MachineOperand:: 1099 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1100 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1101 } 1102 } 1103 } 1104 } 1105 SDB->BitTestCases.clear(); 1106 1107 // If the JumpTable record is filled in, then we need to emit a jump table. 1108 // Updating the PHI nodes is tricky in this case, since we need to determine 1109 // whether the PHI is a successor of the range check MBB or the jump table MBB 1110 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1111 // Lower header first, if it wasn't already lowered 1112 if (!SDB->JTCases[i].first.Emitted) { 1113 // Set the current basic block to the mbb we wish to insert the code into 1114 BB = SDB->JTCases[i].first.HeaderBB; 1115 SDB->setCurrentBasicBlock(BB); 1116 // Emit the code 1117 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1118 CurDAG->setRoot(SDB->getRoot()); 1119 CodeGenAndEmitDAG(); 1120 SDB->clear(); 1121 } 1122 1123 // Set the current basic block to the mbb we wish to insert the code into 1124 BB = SDB->JTCases[i].second.MBB; 1125 SDB->setCurrentBasicBlock(BB); 1126 // Emit the code 1127 SDB->visitJumpTable(SDB->JTCases[i].second); 1128 CurDAG->setRoot(SDB->getRoot()); 1129 CodeGenAndEmitDAG(); 1130 SDB->clear(); 1131 1132 // Update PHI Nodes 1133 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1134 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1135 MachineBasicBlock *PHIBB = PHI->getParent(); 1136 assert(PHI->isPHI() && 1137 "This is not a machine PHI node that we are updating!"); 1138 // "default" BB. We can go there only from header BB. 1139 if (PHIBB == SDB->JTCases[i].second.Default) { 1140 PHI->addOperand 1141 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1142 PHI->addOperand 1143 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1144 } 1145 // JT BB. Just iterate over successors here 1146 if (BB->isSuccessor(PHIBB)) { 1147 PHI->addOperand 1148 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1149 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1150 } 1151 } 1152 } 1153 SDB->JTCases.clear(); 1154 1155 // If the switch block involved a branch to one of the actual successors, we 1156 // need to update PHI nodes in that block. 1157 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1158 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1159 assert(PHI->isPHI() && 1160 "This is not a machine PHI node that we are updating!"); 1161 if (BB->isSuccessor(PHI->getParent())) { 1162 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1163 false)); 1164 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1165 } 1166 } 1167 1168 // If we generated any switch lowering information, build and codegen any 1169 // additional DAGs necessary. 1170 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1171 // Set the current basic block to the mbb we wish to insert the code into 1172 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1173 SDB->setCurrentBasicBlock(BB); 1174 1175 // Emit the code 1176 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1177 CurDAG->setRoot(SDB->getRoot()); 1178 CodeGenAndEmitDAG(); 1179 1180 // Handle any PHI nodes in successors of this chunk, as if we were coming 1181 // from the original BB before switch expansion. Note that PHI nodes can 1182 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1183 // handle them the right number of times. 1184 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1185 // If new BB's are created during scheduling, the edges may have been 1186 // updated. That is, the edge from ThisBB to BB may have been split and 1187 // BB's predecessor is now another block. 1188 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1189 SDB->EdgeMapping.find(BB); 1190 if (EI != SDB->EdgeMapping.end()) 1191 ThisBB = EI->second; 1192 1193 // BB may have been removed from the CFG if a branch was constant folded. 1194 if (ThisBB->isSuccessor(BB)) { 1195 for (MachineBasicBlock::iterator Phi = BB->begin(); 1196 Phi != BB->end() && Phi->isPHI(); 1197 ++Phi) { 1198 // This value for this PHI node is recorded in PHINodesToUpdate. 1199 for (unsigned pn = 0; ; ++pn) { 1200 assert(pn != SDB->PHINodesToUpdate.size() && 1201 "Didn't find PHI entry!"); 1202 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1203 Phi->addOperand(MachineOperand:: 1204 CreateReg(SDB->PHINodesToUpdate[pn].second, 1205 false)); 1206 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1207 break; 1208 } 1209 } 1210 } 1211 } 1212 1213 // Don't process RHS if same block as LHS. 1214 if (BB == SDB->SwitchCases[i].FalseBB) 1215 SDB->SwitchCases[i].FalseBB = 0; 1216 1217 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1218 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1219 SDB->SwitchCases[i].FalseBB = 0; 1220 } 1221 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1222 SDB->clear(); 1223 } 1224 SDB->SwitchCases.clear(); 1225 1226 SDB->PHINodesToUpdate.clear(); 1227} 1228 1229 1230/// Create the scheduler. If a specific scheduler was specified 1231/// via the SchedulerRegistry, use it, otherwise select the 1232/// one preferred by the target. 1233/// 1234ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1235 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1236 1237 if (!Ctor) { 1238 Ctor = ISHeuristic; 1239 RegisterScheduler::setDefault(Ctor); 1240 } 1241 1242 return Ctor(this, OptLevel); 1243} 1244 1245ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1246 return new ScheduleHazardRecognizer(); 1247} 1248 1249//===----------------------------------------------------------------------===// 1250// Helper functions used by the generated instruction selector. 1251//===----------------------------------------------------------------------===// 1252// Calls to these methods are generated by tblgen. 1253 1254/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1255/// the dag combiner simplified the 255, we still want to match. RHS is the 1256/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1257/// specified in the .td file (e.g. 255). 1258bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1259 int64_t DesiredMaskS) const { 1260 const APInt &ActualMask = RHS->getAPIntValue(); 1261 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1262 1263 // If the actual mask exactly matches, success! 1264 if (ActualMask == DesiredMask) 1265 return true; 1266 1267 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1268 if (ActualMask.intersects(~DesiredMask)) 1269 return false; 1270 1271 // Otherwise, the DAG Combiner may have proven that the value coming in is 1272 // either already zero or is not demanded. Check for known zero input bits. 1273 APInt NeededMask = DesiredMask & ~ActualMask; 1274 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1275 return true; 1276 1277 // TODO: check to see if missing bits are just not demanded. 1278 1279 // Otherwise, this pattern doesn't match. 1280 return false; 1281} 1282 1283/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1284/// the dag combiner simplified the 255, we still want to match. RHS is the 1285/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1286/// specified in the .td file (e.g. 255). 1287bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1288 int64_t DesiredMaskS) const { 1289 const APInt &ActualMask = RHS->getAPIntValue(); 1290 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1291 1292 // If the actual mask exactly matches, success! 1293 if (ActualMask == DesiredMask) 1294 return true; 1295 1296 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1297 if (ActualMask.intersects(~DesiredMask)) 1298 return false; 1299 1300 // Otherwise, the DAG Combiner may have proven that the value coming in is 1301 // either already zero or is not demanded. Check for known zero input bits. 1302 APInt NeededMask = DesiredMask & ~ActualMask; 1303 1304 APInt KnownZero, KnownOne; 1305 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1306 1307 // If all the missing bits in the or are already known to be set, match! 1308 if ((NeededMask & KnownOne) == NeededMask) 1309 return true; 1310 1311 // TODO: check to see if missing bits are just not demanded. 1312 1313 // Otherwise, this pattern doesn't match. 1314 return false; 1315} 1316 1317 1318/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1319/// by tblgen. Others should not call it. 1320void SelectionDAGISel:: 1321SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1322 std::vector<SDValue> InOps; 1323 std::swap(InOps, Ops); 1324 1325 Ops.push_back(InOps[0]); // input chain. 1326 Ops.push_back(InOps[1]); // input asm string. 1327 1328 unsigned i = 2, e = InOps.size(); 1329 if (InOps[e-1].getValueType() == MVT::Flag) 1330 --e; // Don't process a flag operand if it is here. 1331 1332 while (i != e) { 1333 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1334 if ((Flags & 7) != 4 /*MEM*/) { 1335 // Just skip over this operand, copying the operands verbatim. 1336 Ops.insert(Ops.end(), InOps.begin()+i, 1337 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1338 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1339 } else { 1340 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1341 "Memory operand with multiple values?"); 1342 // Otherwise, this is a memory operand. Ask the target to select it. 1343 std::vector<SDValue> SelOps; 1344 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1345 llvm_report_error("Could not match memory address. Inline asm" 1346 " failure!"); 1347 } 1348 1349 // Add this to the output node. 1350 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1351 MVT::i32)); 1352 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1353 i += 2; 1354 } 1355 } 1356 1357 // Add the flag input back if present. 1358 if (e != InOps.size()) 1359 Ops.push_back(InOps.back()); 1360} 1361 1362/// findFlagUse - Return use of EVT::Flag value produced by the specified 1363/// SDNode. 1364/// 1365static SDNode *findFlagUse(SDNode *N) { 1366 unsigned FlagResNo = N->getNumValues()-1; 1367 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1368 SDUse &Use = I.getUse(); 1369 if (Use.getResNo() == FlagResNo) 1370 return Use.getUser(); 1371 } 1372 return NULL; 1373} 1374 1375/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1376/// This function recursively traverses up the operand chain, ignoring 1377/// certain nodes. 1378static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1379 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1380 bool IgnoreChains) { 1381 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1382 // greater than all of its (recursive) operands. If we scan to a point where 1383 // 'use' is smaller than the node we're scanning for, then we know we will 1384 // never find it. 1385 // 1386 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1387 // happen because we scan down to newly selected nodes in the case of flag 1388 // uses. 1389 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1390 return false; 1391 1392 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1393 // won't fail if we scan it again. 1394 if (!Visited.insert(Use)) 1395 return false; 1396 1397 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1398 // Ignore chain uses, they are validated by HandleMergeInputChains. 1399 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1400 continue; 1401 1402 SDNode *N = Use->getOperand(i).getNode(); 1403 if (N == Def) { 1404 if (Use == ImmedUse || Use == Root) 1405 continue; // We are not looking for immediate use. 1406 assert(N != Root); 1407 return true; 1408 } 1409 1410 // Traverse up the operand chain. 1411 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1412 return true; 1413 } 1414 return false; 1415} 1416 1417/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1418/// be reached. Return true if that's the case. However, ignore direct uses 1419/// by ImmedUse (which would be U in the example illustrated in 1420/// IsLegalToFold) and by Root (which can happen in the store case). 1421/// FIXME: to be really generic, we should allow direct use by any node 1422/// that is being folded. But realisticly since we only fold loads which 1423/// have one non-chain use, we only need to watch out for load/op/store 1424/// and load/op/cmp case where the root (store / cmp) may reach the load via 1425/// its chain operand. 1426static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse, 1427 bool IgnoreChains) { 1428 SmallPtrSet<SDNode*, 16> Visited; 1429 return findNonImmUse(Root, Def, ImmedUse, Root, Visited, IgnoreChains); 1430} 1431 1432/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1433/// operand node N of U during instruction selection that starts at Root. 1434bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1435 SDNode *Root) const { 1436 if (OptLevel == CodeGenOpt::None) return false; 1437 return N.hasOneUse(); 1438} 1439 1440/// IsLegalToFold - Returns true if the specific operand node N of 1441/// U can be folded during instruction selection that starts at Root. 1442bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1443 bool IgnoreChains) const { 1444 if (OptLevel == CodeGenOpt::None) return false; 1445 1446 // If Root use can somehow reach N through a path that that doesn't contain 1447 // U then folding N would create a cycle. e.g. In the following 1448 // diagram, Root can reach N through X. If N is folded into into Root, then 1449 // X is both a predecessor and a successor of U. 1450 // 1451 // [N*] // 1452 // ^ ^ // 1453 // / \ // 1454 // [U*] [X]? // 1455 // ^ ^ // 1456 // \ / // 1457 // \ / // 1458 // [Root*] // 1459 // 1460 // * indicates nodes to be folded together. 1461 // 1462 // If Root produces a flag, then it gets (even more) interesting. Since it 1463 // will be "glued" together with its flag use in the scheduler, we need to 1464 // check if it might reach N. 1465 // 1466 // [N*] // 1467 // ^ ^ // 1468 // / \ // 1469 // [U*] [X]? // 1470 // ^ ^ // 1471 // \ \ // 1472 // \ | // 1473 // [Root*] | // 1474 // ^ | // 1475 // f | // 1476 // | / // 1477 // [Y] / // 1478 // ^ / // 1479 // f / // 1480 // | / // 1481 // [FU] // 1482 // 1483 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1484 // (call it Fold), then X is a predecessor of FU and a successor of 1485 // Fold. But since Fold and FU are flagged together, this will create 1486 // a cycle in the scheduling graph. 1487 1488 EVT VT = Root->getValueType(Root->getNumValues()-1); 1489 while (VT == MVT::Flag) { 1490 SDNode *FU = findFlagUse(Root); 1491 if (FU == NULL) 1492 break; 1493 Root = FU; 1494 VT = Root->getValueType(Root->getNumValues()-1); 1495 } 1496 1497 return !isNonImmUse(Root, N.getNode(), U, IgnoreChains); 1498} 1499 1500SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1501 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1502 SelectInlineAsmMemoryOperands(Ops); 1503 1504 std::vector<EVT> VTs; 1505 VTs.push_back(MVT::Other); 1506 VTs.push_back(MVT::Flag); 1507 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1508 VTs, &Ops[0], Ops.size()); 1509 New->setNodeId(-1); 1510 return New.getNode(); 1511} 1512 1513SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1514 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1515} 1516 1517SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1518 SDValue Chain = N->getOperand(0); 1519 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1520 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1521 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL, 1522 MVT::Other, Tmp, Chain); 1523} 1524 1525/// GetVBR - decode a vbr encoding whose top bit is set. 1526ALWAYS_INLINE static uint64_t 1527GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1528 assert(Val >= 128 && "Not a VBR"); 1529 Val &= 127; // Remove first vbr bit. 1530 1531 unsigned Shift = 7; 1532 uint64_t NextBits; 1533 do { 1534 NextBits = MatcherTable[Idx++]; 1535 Val |= (NextBits&127) << Shift; 1536 Shift += 7; 1537 } while (NextBits & 128); 1538 1539 return Val; 1540} 1541 1542 1543/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1544/// interior flag and chain results to use the new flag and chain results. 1545void SelectionDAGISel:: 1546UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1547 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1548 SDValue InputFlag, 1549 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1550 bool isMorphNodeTo) { 1551 SmallVector<SDNode*, 4> NowDeadNodes; 1552 1553 ISelUpdater ISU(ISelPosition); 1554 1555 // Now that all the normal results are replaced, we replace the chain and 1556 // flag results if present. 1557 if (!ChainNodesMatched.empty()) { 1558 assert(InputChain.getNode() != 0 && 1559 "Matched input chains but didn't produce a chain"); 1560 // Loop over all of the nodes we matched that produced a chain result. 1561 // Replace all the chain results with the final chain we ended up with. 1562 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1563 SDNode *ChainNode = ChainNodesMatched[i]; 1564 1565 // If this node was already deleted, don't look at it. 1566 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1567 continue; 1568 1569 // Don't replace the results of the root node if we're doing a 1570 // MorphNodeTo. 1571 if (ChainNode == NodeToMatch && isMorphNodeTo) 1572 continue; 1573 1574 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1575 if (ChainVal.getValueType() == MVT::Flag) 1576 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1577 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1578 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1579 1580 // If the node became dead, delete it. 1581 if (ChainNode->use_empty()) 1582 NowDeadNodes.push_back(ChainNode); 1583 } 1584 } 1585 1586 // If the result produces a flag, update any flag results in the matched 1587 // pattern with the flag result. 1588 if (InputFlag.getNode() != 0) { 1589 // Handle any interior nodes explicitly marked. 1590 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1591 SDNode *FRN = FlagResultNodesMatched[i]; 1592 1593 // If this node was already deleted, don't look at it. 1594 if (FRN->getOpcode() == ISD::DELETED_NODE) 1595 continue; 1596 1597 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1598 "Doesn't have a flag result"); 1599 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1600 InputFlag, &ISU); 1601 1602 // If the node became dead, delete it. 1603 if (FRN->use_empty()) 1604 NowDeadNodes.push_back(FRN); 1605 } 1606 } 1607 1608 if (!NowDeadNodes.empty()) 1609 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1610 1611 DEBUG(errs() << "ISEL: Match complete!\n"); 1612} 1613 1614enum ChainResult { 1615 CR_Simple, 1616 CR_InducesCycle, 1617 CR_LeadsToInteriorNode 1618}; 1619 1620/// WalkChainUsers - Walk down the users of the specified chained node that is 1621/// part of the pattern we're matching, looking at all of the users we find. 1622/// This determines whether something is an interior node, whether we have a 1623/// non-pattern node in between two pattern nodes (which prevent folding because 1624/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1625/// between pattern nodes (in which case the TF becomes part of the pattern). 1626/// 1627/// The walk we do here is guaranteed to be small because we quickly get down to 1628/// already selected nodes "below" us. 1629static ChainResult 1630WalkChainUsers(SDNode *ChainedNode, 1631 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1632 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1633 ChainResult Result = CR_Simple; 1634 1635 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1636 E = ChainedNode->use_end(); UI != E; ++UI) { 1637 // Make sure the use is of the chain, not some other value we produce. 1638 if (UI.getUse().getValueType() != MVT::Other) continue; 1639 1640 SDNode *User = *UI; 1641 1642 // If we see an already-selected machine node, then we've gone beyond the 1643 // pattern that we're selecting down into the already selected chunk of the 1644 // DAG. 1645 if (User->isMachineOpcode() || 1646 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1647 continue; 1648 1649 if (User->getOpcode() == ISD::CopyToReg || 1650 User->getOpcode() == ISD::CopyFromReg || 1651 User->getOpcode() == ISD::INLINEASM) { 1652 // If their node ID got reset to -1 then they've already been selected. 1653 // Treat them like a MachineOpcode. 1654 if (User->getNodeId() == -1) 1655 continue; 1656 } 1657 1658 // If we have a TokenFactor, we handle it specially. 1659 if (User->getOpcode() != ISD::TokenFactor) { 1660 // If the node isn't a token factor and isn't part of our pattern, then it 1661 // must be a random chained node in between two nodes we're selecting. 1662 // This happens when we have something like: 1663 // x = load ptr 1664 // call 1665 // y = x+4 1666 // store y -> ptr 1667 // Because we structurally match the load/store as a read/modify/write, 1668 // but the call is chained between them. We cannot fold in this case 1669 // because it would induce a cycle in the graph. 1670 if (!std::count(ChainedNodesInPattern.begin(), 1671 ChainedNodesInPattern.end(), User)) 1672 return CR_InducesCycle; 1673 1674 // Otherwise we found a node that is part of our pattern. For example in: 1675 // x = load ptr 1676 // y = x+4 1677 // store y -> ptr 1678 // This would happen when we're scanning down from the load and see the 1679 // store as a user. Record that there is a use of ChainedNode that is 1680 // part of the pattern and keep scanning uses. 1681 Result = CR_LeadsToInteriorNode; 1682 InteriorChainedNodes.push_back(User); 1683 continue; 1684 } 1685 1686 // If we found a TokenFactor, there are two cases to consider: first if the 1687 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1688 // uses of the TF are in our pattern) we just want to ignore it. Second, 1689 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1690 // [Load chain] 1691 // ^ 1692 // | 1693 // [Load] 1694 // ^ ^ 1695 // | \ DAG's like cheese 1696 // / \ do you? 1697 // / | 1698 // [TokenFactor] [Op] 1699 // ^ ^ 1700 // | | 1701 // \ / 1702 // \ / 1703 // [Store] 1704 // 1705 // In this case, the TokenFactor becomes part of our match and we rewrite it 1706 // as a new TokenFactor. 1707 // 1708 // To distinguish these two cases, do a recursive walk down the uses. 1709 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1710 case CR_Simple: 1711 // If the uses of the TokenFactor are just already-selected nodes, ignore 1712 // it, it is "below" our pattern. 1713 continue; 1714 case CR_InducesCycle: 1715 // If the uses of the TokenFactor lead to nodes that are not part of our 1716 // pattern that are not selected, folding would turn this into a cycle, 1717 // bail out now. 1718 return CR_InducesCycle; 1719 case CR_LeadsToInteriorNode: 1720 break; // Otherwise, keep processing. 1721 } 1722 1723 // Okay, we know we're in the interesting interior case. The TokenFactor 1724 // is now going to be considered part of the pattern so that we rewrite its 1725 // uses (it may have uses that are not part of the pattern) with the 1726 // ultimate chain result of the generated code. We will also add its chain 1727 // inputs as inputs to the ultimate TokenFactor we create. 1728 Result = CR_LeadsToInteriorNode; 1729 ChainedNodesInPattern.push_back(User); 1730 InteriorChainedNodes.push_back(User); 1731 continue; 1732 } 1733 1734 return Result; 1735} 1736 1737/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1738/// operation for when the pattern matched at least one node with a chains. The 1739/// input vector contains a list of all of the chained nodes that we match. We 1740/// must determine if this is a valid thing to cover (i.e. matching it won't 1741/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1742/// be used as the input node chain for the generated nodes. 1743static SDValue 1744HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1745 SelectionDAG *CurDAG) { 1746 // Walk all of the chained nodes we've matched, recursively scanning down the 1747 // users of the chain result. This adds any TokenFactor nodes that are caught 1748 // in between chained nodes to the chained and interior nodes list. 1749 SmallVector<SDNode*, 3> InteriorChainedNodes; 1750 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1751 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1752 InteriorChainedNodes) == CR_InducesCycle) 1753 return SDValue(); // Would induce a cycle. 1754 } 1755 1756 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1757 // that we are interested in. Form our input TokenFactor node. 1758 SmallVector<SDValue, 3> InputChains; 1759 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1760 // Add the input chain of this node to the InputChains list (which will be 1761 // the operands of the generated TokenFactor) if it's not an interior node. 1762 SDNode *N = ChainNodesMatched[i]; 1763 if (N->getOpcode() != ISD::TokenFactor) { 1764 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1765 continue; 1766 1767 // Otherwise, add the input chain. 1768 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1769 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1770 InputChains.push_back(InChain); 1771 continue; 1772 } 1773 1774 // If we have a token factor, we want to add all inputs of the token factor 1775 // that are not part of the pattern we're matching. 1776 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1777 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1778 N->getOperand(op).getNode())) 1779 InputChains.push_back(N->getOperand(op)); 1780 } 1781 } 1782 1783 SDValue Res; 1784 if (InputChains.size() == 1) 1785 return InputChains[0]; 1786 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1787 MVT::Other, &InputChains[0], InputChains.size()); 1788} 1789 1790/// MorphNode - Handle morphing a node in place for the selector. 1791SDNode *SelectionDAGISel:: 1792MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1793 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1794 // It is possible we're using MorphNodeTo to replace a node with no 1795 // normal results with one that has a normal result (or we could be 1796 // adding a chain) and the input could have flags and chains as well. 1797 // In this case we need to shifting the operands down. 1798 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1799 // than the old isel though. We should sink this into MorphNodeTo. 1800 int OldFlagResultNo = -1, OldChainResultNo = -1; 1801 1802 unsigned NTMNumResults = Node->getNumValues(); 1803 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1804 OldFlagResultNo = NTMNumResults-1; 1805 if (NTMNumResults != 1 && 1806 Node->getValueType(NTMNumResults-2) == MVT::Other) 1807 OldChainResultNo = NTMNumResults-2; 1808 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1809 OldChainResultNo = NTMNumResults-1; 1810 1811 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1812 // that this deletes operands of the old node that become dead. 1813 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1814 1815 // MorphNodeTo can operate in two ways: if an existing node with the 1816 // specified operands exists, it can just return it. Otherwise, it 1817 // updates the node in place to have the requested operands. 1818 if (Res == Node) { 1819 // If we updated the node in place, reset the node ID. To the isel, 1820 // this should be just like a newly allocated machine node. 1821 Res->setNodeId(-1); 1822 } 1823 1824 unsigned ResNumResults = Res->getNumValues(); 1825 // Move the flag if needed. 1826 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1827 (unsigned)OldFlagResultNo != ResNumResults-1) 1828 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1829 SDValue(Res, ResNumResults-1)); 1830 1831 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1832 --ResNumResults; 1833 1834 // Move the chain reference if needed. 1835 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1836 (unsigned)OldChainResultNo != ResNumResults-1) 1837 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1838 SDValue(Res, ResNumResults-1)); 1839 1840 // Otherwise, no replacement happened because the node already exists. Replace 1841 // Uses of the old node with the new one. 1842 if (Res != Node) 1843 CurDAG->ReplaceAllUsesWith(Node, Res); 1844 1845 return Res; 1846} 1847 1848/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1849ALWAYS_INLINE static bool 1850CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1851 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1852 // Accept if it is exactly the same as a previously recorded node. 1853 unsigned RecNo = MatcherTable[MatcherIndex++]; 1854 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1855 return N == RecordedNodes[RecNo]; 1856} 1857 1858/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1859ALWAYS_INLINE static bool 1860CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1861 SelectionDAGISel &SDISel) { 1862 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1863} 1864 1865/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1866ALWAYS_INLINE static bool 1867CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1868 SelectionDAGISel &SDISel, SDNode *N) { 1869 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1870} 1871 1872ALWAYS_INLINE static bool 1873CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1874 SDNode *N) { 1875 return N->getOpcode() == MatcherTable[MatcherIndex++]; 1876} 1877 1878ALWAYS_INLINE static bool 1879CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1880 SDValue N, const TargetLowering &TLI) { 1881 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1882 if (N.getValueType() == VT) return true; 1883 1884 // Handle the case when VT is iPTR. 1885 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1886} 1887 1888ALWAYS_INLINE static bool 1889CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1890 SDValue N, const TargetLowering &TLI, 1891 unsigned ChildNo) { 1892 if (ChildNo >= N.getNumOperands()) 1893 return false; // Match fails if out of range child #. 1894 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1895} 1896 1897 1898ALWAYS_INLINE static bool 1899CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1900 SDValue N) { 1901 return cast<CondCodeSDNode>(N)->get() == 1902 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1903} 1904 1905ALWAYS_INLINE static bool 1906CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1907 SDValue N, const TargetLowering &TLI) { 1908 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1909 if (cast<VTSDNode>(N)->getVT() == VT) 1910 return true; 1911 1912 // Handle the case when VT is iPTR. 1913 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1914} 1915 1916ALWAYS_INLINE static bool 1917CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1918 SDValue N) { 1919 int64_t Val = MatcherTable[MatcherIndex++]; 1920 if (Val & 128) 1921 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1922 1923 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1924 return C != 0 && C->getSExtValue() == Val; 1925} 1926 1927ALWAYS_INLINE static bool 1928CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1929 SDValue N, SelectionDAGISel &SDISel) { 1930 int64_t Val = MatcherTable[MatcherIndex++]; 1931 if (Val & 128) 1932 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1933 1934 if (N->getOpcode() != ISD::AND) return false; 1935 1936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1937 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1938} 1939 1940ALWAYS_INLINE static bool 1941CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1942 SDValue N, SelectionDAGISel &SDISel) { 1943 int64_t Val = MatcherTable[MatcherIndex++]; 1944 if (Val & 128) 1945 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1946 1947 if (N->getOpcode() != ISD::OR) return false; 1948 1949 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1950 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1951} 1952 1953/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1954/// scope, evaluate the current node. If the current predicate is known to 1955/// fail, set Result=true and return anything. If the current predicate is 1956/// known to pass, set Result=false and return the MatcherIndex to continue 1957/// with. If the current predicate is unknown, set Result=false and return the 1958/// MatcherIndex to continue with. 1959static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1960 unsigned Index, SDValue N, 1961 bool &Result, SelectionDAGISel &SDISel, 1962 SmallVectorImpl<SDValue> &RecordedNodes){ 1963 switch (Table[Index++]) { 1964 default: 1965 Result = false; 1966 return Index-1; // Could not evaluate this predicate. 1967 case SelectionDAGISel::OPC_CheckSame: 1968 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1969 return Index; 1970 case SelectionDAGISel::OPC_CheckPatternPredicate: 1971 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1972 return Index; 1973 case SelectionDAGISel::OPC_CheckPredicate: 1974 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1975 return Index; 1976 case SelectionDAGISel::OPC_CheckOpcode: 1977 Result = !::CheckOpcode(Table, Index, N.getNode()); 1978 return Index; 1979 case SelectionDAGISel::OPC_CheckType: 1980 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1981 return Index; 1982 case SelectionDAGISel::OPC_CheckChild0Type: 1983 case SelectionDAGISel::OPC_CheckChild1Type: 1984 case SelectionDAGISel::OPC_CheckChild2Type: 1985 case SelectionDAGISel::OPC_CheckChild3Type: 1986 case SelectionDAGISel::OPC_CheckChild4Type: 1987 case SelectionDAGISel::OPC_CheckChild5Type: 1988 case SelectionDAGISel::OPC_CheckChild6Type: 1989 case SelectionDAGISel::OPC_CheckChild7Type: 1990 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1991 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1992 return Index; 1993 case SelectionDAGISel::OPC_CheckCondCode: 1994 Result = !::CheckCondCode(Table, Index, N); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckValueType: 1997 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckInteger: 2000 Result = !::CheckInteger(Table, Index, N); 2001 return Index; 2002 case SelectionDAGISel::OPC_CheckAndImm: 2003 Result = !::CheckAndImm(Table, Index, N, SDISel); 2004 return Index; 2005 case SelectionDAGISel::OPC_CheckOrImm: 2006 Result = !::CheckOrImm(Table, Index, N, SDISel); 2007 return Index; 2008 } 2009} 2010 2011 2012struct MatchScope { 2013 /// FailIndex - If this match fails, this is the index to continue with. 2014 unsigned FailIndex; 2015 2016 /// NodeStack - The node stack when the scope was formed. 2017 SmallVector<SDValue, 4> NodeStack; 2018 2019 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2020 unsigned NumRecordedNodes; 2021 2022 /// NumMatchedMemRefs - The number of matched memref entries. 2023 unsigned NumMatchedMemRefs; 2024 2025 /// InputChain/InputFlag - The current chain/flag 2026 SDValue InputChain, InputFlag; 2027 2028 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2029 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2030}; 2031 2032SDNode *SelectionDAGISel:: 2033SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2034 unsigned TableSize) { 2035 // FIXME: Should these even be selected? Handle these cases in the caller? 2036 switch (NodeToMatch->getOpcode()) { 2037 default: 2038 break; 2039 case ISD::EntryToken: // These nodes remain the same. 2040 case ISD::BasicBlock: 2041 case ISD::Register: 2042 case ISD::HANDLENODE: 2043 case ISD::TargetConstant: 2044 case ISD::TargetConstantFP: 2045 case ISD::TargetConstantPool: 2046 case ISD::TargetFrameIndex: 2047 case ISD::TargetExternalSymbol: 2048 case ISD::TargetBlockAddress: 2049 case ISD::TargetJumpTable: 2050 case ISD::TargetGlobalTLSAddress: 2051 case ISD::TargetGlobalAddress: 2052 case ISD::TokenFactor: 2053 case ISD::CopyFromReg: 2054 case ISD::CopyToReg: 2055 NodeToMatch->setNodeId(-1); // Mark selected. 2056 return 0; 2057 case ISD::AssertSext: 2058 case ISD::AssertZext: 2059 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2060 NodeToMatch->getOperand(0)); 2061 return 0; 2062 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2063 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch); 2064 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2065 } 2066 2067 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2068 2069 // Set up the node stack with NodeToMatch as the only node on the stack. 2070 SmallVector<SDValue, 8> NodeStack; 2071 SDValue N = SDValue(NodeToMatch, 0); 2072 NodeStack.push_back(N); 2073 2074 // MatchScopes - Scopes used when matching, if a match failure happens, this 2075 // indicates where to continue checking. 2076 SmallVector<MatchScope, 8> MatchScopes; 2077 2078 // RecordedNodes - This is the set of nodes that have been recorded by the 2079 // state machine. 2080 SmallVector<SDValue, 8> RecordedNodes; 2081 2082 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2083 // pattern. 2084 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2085 2086 // These are the current input chain and flag for use when generating nodes. 2087 // Various Emit operations change these. For example, emitting a copytoreg 2088 // uses and updates these. 2089 SDValue InputChain, InputFlag; 2090 2091 // ChainNodesMatched - If a pattern matches nodes that have input/output 2092 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2093 // which ones they are. The result is captured into this list so that we can 2094 // update the chain results when the pattern is complete. 2095 SmallVector<SDNode*, 3> ChainNodesMatched; 2096 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2097 2098 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2099 NodeToMatch->dump(CurDAG); 2100 errs() << '\n'); 2101 2102 // Determine where to start the interpreter. Normally we start at opcode #0, 2103 // but if the state machine starts with an OPC_SwitchOpcode, then we 2104 // accelerate the first lookup (which is guaranteed to be hot) with the 2105 // OpcodeOffset table. 2106 unsigned MatcherIndex = 0; 2107 2108 if (!OpcodeOffset.empty()) { 2109 // Already computed the OpcodeOffset table, just index into it. 2110 if (N.getOpcode() < OpcodeOffset.size()) 2111 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2112 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2113 2114 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2115 // Otherwise, the table isn't computed, but the state machine does start 2116 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2117 // is the first time we're selecting an instruction. 2118 unsigned Idx = 1; 2119 while (1) { 2120 // Get the size of this case. 2121 unsigned CaseSize = MatcherTable[Idx++]; 2122 if (CaseSize & 128) 2123 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2124 if (CaseSize == 0) break; 2125 2126 // Get the opcode, add the index to the table. 2127 unsigned Opc = MatcherTable[Idx++]; 2128 if (Opc >= OpcodeOffset.size()) 2129 OpcodeOffset.resize((Opc+1)*2); 2130 OpcodeOffset[Opc] = Idx; 2131 Idx += CaseSize; 2132 } 2133 2134 // Okay, do the lookup for the first opcode. 2135 if (N.getOpcode() < OpcodeOffset.size()) 2136 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2137 } 2138 2139 while (1) { 2140 assert(MatcherIndex < TableSize && "Invalid index"); 2141 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2142 switch (Opcode) { 2143 case OPC_Scope: { 2144 // Okay, the semantics of this operation are that we should push a scope 2145 // then evaluate the first child. However, pushing a scope only to have 2146 // the first check fail (which then pops it) is inefficient. If we can 2147 // determine immediately that the first check (or first several) will 2148 // immediately fail, don't even bother pushing a scope for them. 2149 unsigned FailIndex; 2150 2151 while (1) { 2152 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2153 if (NumToSkip & 128) 2154 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2155 // Found the end of the scope with no match. 2156 if (NumToSkip == 0) { 2157 FailIndex = 0; 2158 break; 2159 } 2160 2161 FailIndex = MatcherIndex+NumToSkip; 2162 2163 // If we can't evaluate this predicate without pushing a scope (e.g. if 2164 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2165 // push the scope and evaluate the full predicate chain. 2166 bool Result; 2167 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2168 Result, *this, RecordedNodes); 2169 if (!Result) 2170 break; 2171 2172 DEBUG(errs() << " Skipped scope entry at index " << MatcherIndex 2173 << " continuing at " << FailIndex << "\n"); 2174 2175 2176 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2177 // move to the next case. 2178 MatcherIndex = FailIndex; 2179 } 2180 2181 // If the whole scope failed to match, bail. 2182 if (FailIndex == 0) break; 2183 2184 // Push a MatchScope which indicates where to go if the first child fails 2185 // to match. 2186 MatchScope NewEntry; 2187 NewEntry.FailIndex = FailIndex; 2188 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2189 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2190 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2191 NewEntry.InputChain = InputChain; 2192 NewEntry.InputFlag = InputFlag; 2193 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2194 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2195 MatchScopes.push_back(NewEntry); 2196 continue; 2197 } 2198 case OPC_RecordNode: 2199 // Remember this node, it may end up being an operand in the pattern. 2200 RecordedNodes.push_back(N); 2201 continue; 2202 2203 case OPC_RecordChild0: case OPC_RecordChild1: 2204 case OPC_RecordChild2: case OPC_RecordChild3: 2205 case OPC_RecordChild4: case OPC_RecordChild5: 2206 case OPC_RecordChild6: case OPC_RecordChild7: { 2207 unsigned ChildNo = Opcode-OPC_RecordChild0; 2208 if (ChildNo >= N.getNumOperands()) 2209 break; // Match fails if out of range child #. 2210 2211 RecordedNodes.push_back(N->getOperand(ChildNo)); 2212 continue; 2213 } 2214 case OPC_RecordMemRef: 2215 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2216 continue; 2217 2218 case OPC_CaptureFlagInput: 2219 // If the current node has an input flag, capture it in InputFlag. 2220 if (N->getNumOperands() != 0 && 2221 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2222 InputFlag = N->getOperand(N->getNumOperands()-1); 2223 continue; 2224 2225 case OPC_MoveChild: { 2226 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2227 if (ChildNo >= N.getNumOperands()) 2228 break; // Match fails if out of range child #. 2229 N = N.getOperand(ChildNo); 2230 NodeStack.push_back(N); 2231 continue; 2232 } 2233 2234 case OPC_MoveParent: 2235 // Pop the current node off the NodeStack. 2236 NodeStack.pop_back(); 2237 assert(!NodeStack.empty() && "Node stack imbalance!"); 2238 N = NodeStack.back(); 2239 continue; 2240 2241 case OPC_CheckSame: 2242 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2243 continue; 2244 case OPC_CheckPatternPredicate: 2245 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2246 continue; 2247 case OPC_CheckPredicate: 2248 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2249 N.getNode())) 2250 break; 2251 continue; 2252 case OPC_CheckComplexPat: 2253 if (!CheckComplexPattern(NodeToMatch, N, 2254 MatcherTable[MatcherIndex++], RecordedNodes)) 2255 break; 2256 continue; 2257 case OPC_CheckOpcode: 2258 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2259 continue; 2260 2261 case OPC_CheckType: 2262 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2263 continue; 2264 2265 case OPC_SwitchOpcode: { 2266 unsigned CurNodeOpcode = N.getOpcode(); 2267 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2268 unsigned CaseSize; 2269 while (1) { 2270 // Get the size of this case. 2271 CaseSize = MatcherTable[MatcherIndex++]; 2272 if (CaseSize & 128) 2273 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2274 if (CaseSize == 0) break; 2275 2276 // If the opcode matches, then we will execute this case. 2277 if (CurNodeOpcode == MatcherTable[MatcherIndex++]) 2278 break; 2279 2280 // Otherwise, skip over this case. 2281 MatcherIndex += CaseSize; 2282 } 2283 2284 // If no cases matched, bail out. 2285 if (CaseSize == 0) break; 2286 2287 // Otherwise, execute the case we found. 2288 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2289 << " to " << MatcherIndex << "\n"); 2290 continue; 2291 } 2292 2293 case OPC_SwitchType: { 2294 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2295 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2296 unsigned CaseSize; 2297 while (1) { 2298 // Get the size of this case. 2299 CaseSize = MatcherTable[MatcherIndex++]; 2300 if (CaseSize & 128) 2301 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2302 if (CaseSize == 0) break; 2303 2304 MVT::SimpleValueType CaseVT = 2305 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2306 if (CaseVT == MVT::iPTR) 2307 CaseVT = TLI.getPointerTy().SimpleTy; 2308 2309 // If the VT matches, then we will execute this case. 2310 if (CurNodeVT == CaseVT) 2311 break; 2312 2313 // Otherwise, skip over this case. 2314 MatcherIndex += CaseSize; 2315 } 2316 2317 // If no cases matched, bail out. 2318 if (CaseSize == 0) break; 2319 2320 // Otherwise, execute the case we found. 2321 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2322 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2323 continue; 2324 } 2325 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2326 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2327 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2328 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2329 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2330 Opcode-OPC_CheckChild0Type)) 2331 break; 2332 continue; 2333 case OPC_CheckCondCode: 2334 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2335 continue; 2336 case OPC_CheckValueType: 2337 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2338 continue; 2339 case OPC_CheckInteger: 2340 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2341 continue; 2342 case OPC_CheckAndImm: 2343 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2344 continue; 2345 case OPC_CheckOrImm: 2346 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2347 continue; 2348 2349 case OPC_CheckFoldableChainNode: { 2350 assert(NodeStack.size() != 1 && "No parent node"); 2351 // Verify that all intermediate nodes between the root and this one have 2352 // a single use. 2353 bool HasMultipleUses = false; 2354 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2355 if (!NodeStack[i].hasOneUse()) { 2356 HasMultipleUses = true; 2357 break; 2358 } 2359 if (HasMultipleUses) break; 2360 2361 // Check to see that the target thinks this is profitable to fold and that 2362 // we can fold it without inducing cycles in the graph. 2363 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2364 NodeToMatch) || 2365 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2366 NodeToMatch, true/*We validate our own chains*/)) 2367 break; 2368 2369 continue; 2370 } 2371 case OPC_EmitInteger: { 2372 MVT::SimpleValueType VT = 2373 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2374 int64_t Val = MatcherTable[MatcherIndex++]; 2375 if (Val & 128) 2376 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2377 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2378 continue; 2379 } 2380 case OPC_EmitRegister: { 2381 MVT::SimpleValueType VT = 2382 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2383 unsigned RegNo = MatcherTable[MatcherIndex++]; 2384 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2385 continue; 2386 } 2387 2388 case OPC_EmitConvertToTarget: { 2389 // Convert from IMM/FPIMM to target version. 2390 unsigned RecNo = MatcherTable[MatcherIndex++]; 2391 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2392 SDValue Imm = RecordedNodes[RecNo]; 2393 2394 if (Imm->getOpcode() == ISD::Constant) { 2395 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2396 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2397 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2398 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2399 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2400 } 2401 2402 RecordedNodes.push_back(Imm); 2403 continue; 2404 } 2405 2406 case OPC_EmitMergeInputChains: { 2407 assert(InputChain.getNode() == 0 && 2408 "EmitMergeInputChains should be the first chain producing node"); 2409 // This node gets a list of nodes we matched in the input that have 2410 // chains. We want to token factor all of the input chains to these nodes 2411 // together. However, if any of the input chains is actually one of the 2412 // nodes matched in this pattern, then we have an intra-match reference. 2413 // Ignore these because the newly token factored chain should not refer to 2414 // the old nodes. 2415 unsigned NumChains = MatcherTable[MatcherIndex++]; 2416 assert(NumChains != 0 && "Can't TF zero chains"); 2417 2418 assert(ChainNodesMatched.empty() && 2419 "Should only have one EmitMergeInputChains per match"); 2420 2421 // Read all of the chained nodes. 2422 for (unsigned i = 0; i != NumChains; ++i) { 2423 unsigned RecNo = MatcherTable[MatcherIndex++]; 2424 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2425 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2426 2427 // FIXME: What if other value results of the node have uses not matched 2428 // by this pattern? 2429 if (ChainNodesMatched.back() != NodeToMatch && 2430 !RecordedNodes[RecNo].hasOneUse()) { 2431 ChainNodesMatched.clear(); 2432 break; 2433 } 2434 } 2435 2436 // If the inner loop broke out, the match fails. 2437 if (ChainNodesMatched.empty()) 2438 break; 2439 2440 // Merge the input chains if they are not intra-pattern references. 2441 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2442 2443 if (InputChain.getNode() == 0) 2444 break; // Failed to merge. 2445 2446 continue; 2447 } 2448 2449 case OPC_EmitCopyToReg: { 2450 unsigned RecNo = MatcherTable[MatcherIndex++]; 2451 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2452 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2453 2454 if (InputChain.getNode() == 0) 2455 InputChain = CurDAG->getEntryNode(); 2456 2457 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2458 DestPhysReg, RecordedNodes[RecNo], 2459 InputFlag); 2460 2461 InputFlag = InputChain.getValue(1); 2462 continue; 2463 } 2464 2465 case OPC_EmitNodeXForm: { 2466 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2467 unsigned RecNo = MatcherTable[MatcherIndex++]; 2468 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2469 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2470 continue; 2471 } 2472 2473 case OPC_EmitNode: 2474 case OPC_MorphNodeTo: { 2475 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2476 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2477 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2478 // Get the result VT list. 2479 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2480 SmallVector<EVT, 4> VTs; 2481 for (unsigned i = 0; i != NumVTs; ++i) { 2482 MVT::SimpleValueType VT = 2483 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2484 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2485 VTs.push_back(VT); 2486 } 2487 2488 if (EmitNodeInfo & OPFL_Chain) 2489 VTs.push_back(MVT::Other); 2490 if (EmitNodeInfo & OPFL_FlagOutput) 2491 VTs.push_back(MVT::Flag); 2492 2493 // This is hot code, so optimize the two most common cases of 1 and 2 2494 // results. 2495 SDVTList VTList; 2496 if (VTs.size() == 1) 2497 VTList = CurDAG->getVTList(VTs[0]); 2498 else if (VTs.size() == 2) 2499 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2500 else 2501 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2502 2503 // Get the operand list. 2504 unsigned NumOps = MatcherTable[MatcherIndex++]; 2505 SmallVector<SDValue, 8> Ops; 2506 for (unsigned i = 0; i != NumOps; ++i) { 2507 unsigned RecNo = MatcherTable[MatcherIndex++]; 2508 if (RecNo & 128) 2509 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2510 2511 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2512 Ops.push_back(RecordedNodes[RecNo]); 2513 } 2514 2515 // If there are variadic operands to add, handle them now. 2516 if (EmitNodeInfo & OPFL_VariadicInfo) { 2517 // Determine the start index to copy from. 2518 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2519 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2520 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2521 "Invalid variadic node"); 2522 // Copy all of the variadic operands, not including a potential flag 2523 // input. 2524 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2525 i != e; ++i) { 2526 SDValue V = NodeToMatch->getOperand(i); 2527 if (V.getValueType() == MVT::Flag) break; 2528 Ops.push_back(V); 2529 } 2530 } 2531 2532 // If this has chain/flag inputs, add them. 2533 if (EmitNodeInfo & OPFL_Chain) 2534 Ops.push_back(InputChain); 2535 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2536 Ops.push_back(InputFlag); 2537 2538 // Create the node. 2539 SDNode *Res = 0; 2540 if (Opcode != OPC_MorphNodeTo) { 2541 // If this is a normal EmitNode command, just create the new node and 2542 // add the results to the RecordedNodes list. 2543 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2544 VTList, Ops.data(), Ops.size()); 2545 2546 // Add all the non-flag/non-chain results to the RecordedNodes list. 2547 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2548 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2549 RecordedNodes.push_back(SDValue(Res, i)); 2550 } 2551 2552 } else { 2553 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2554 EmitNodeInfo); 2555 } 2556 2557 // If the node had chain/flag results, update our notion of the current 2558 // chain and flag. 2559 if (EmitNodeInfo & OPFL_FlagOutput) { 2560 InputFlag = SDValue(Res, VTs.size()-1); 2561 if (EmitNodeInfo & OPFL_Chain) 2562 InputChain = SDValue(Res, VTs.size()-2); 2563 } else if (EmitNodeInfo & OPFL_Chain) 2564 InputChain = SDValue(Res, VTs.size()-1); 2565 2566 // If the OPFL_MemRefs flag is set on this node, slap all of the 2567 // accumulated memrefs onto it. 2568 // 2569 // FIXME: This is vastly incorrect for patterns with multiple outputs 2570 // instructions that access memory and for ComplexPatterns that match 2571 // loads. 2572 if (EmitNodeInfo & OPFL_MemRefs) { 2573 MachineSDNode::mmo_iterator MemRefs = 2574 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2575 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2576 cast<MachineSDNode>(Res) 2577 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2578 } 2579 2580 DEBUG(errs() << " " 2581 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2582 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2583 2584 // If this was a MorphNodeTo then we're completely done! 2585 if (Opcode == OPC_MorphNodeTo) { 2586 // Update chain and flag uses. 2587 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2588 InputFlag, FlagResultNodesMatched, true); 2589 return Res; 2590 } 2591 2592 continue; 2593 } 2594 2595 case OPC_MarkFlagResults: { 2596 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2597 2598 // Read and remember all the flag-result nodes. 2599 for (unsigned i = 0; i != NumNodes; ++i) { 2600 unsigned RecNo = MatcherTable[MatcherIndex++]; 2601 if (RecNo & 128) 2602 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2603 2604 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2605 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2606 } 2607 continue; 2608 } 2609 2610 case OPC_CompleteMatch: { 2611 // The match has been completed, and any new nodes (if any) have been 2612 // created. Patch up references to the matched dag to use the newly 2613 // created nodes. 2614 unsigned NumResults = MatcherTable[MatcherIndex++]; 2615 2616 for (unsigned i = 0; i != NumResults; ++i) { 2617 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2618 if (ResSlot & 128) 2619 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2620 2621 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2622 SDValue Res = RecordedNodes[ResSlot]; 2623 2624 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program 2625 // after (parallel) on input patterns are removed. This would also 2626 // allow us to stop encoding #results in OPC_CompleteMatch's table 2627 // entry. 2628 if (NodeToMatch->getNumValues() <= i || 2629 NodeToMatch->getValueType(i) == MVT::Other || 2630 NodeToMatch->getValueType(i) == MVT::Flag) 2631 break; 2632 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2633 NodeToMatch->getValueType(i) == MVT::iPTR || 2634 Res.getValueType() == MVT::iPTR || 2635 NodeToMatch->getValueType(i).getSizeInBits() == 2636 Res.getValueType().getSizeInBits()) && 2637 "invalid replacement"); 2638 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2639 } 2640 2641 // If the root node defines a flag, add it to the flag nodes to update 2642 // list. 2643 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2644 FlagResultNodesMatched.push_back(NodeToMatch); 2645 2646 // Update chain and flag uses. 2647 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2648 InputFlag, FlagResultNodesMatched, false); 2649 2650 assert(NodeToMatch->use_empty() && 2651 "Didn't replace all uses of the node?"); 2652 2653 // FIXME: We just return here, which interacts correctly with SelectRoot 2654 // above. We should fix this to not return an SDNode* anymore. 2655 return 0; 2656 } 2657 } 2658 2659 // If the code reached this point, then the match failed. See if there is 2660 // another child to try in the current 'Scope', otherwise pop it until we 2661 // find a case to check. 2662 while (1) { 2663 if (MatchScopes.empty()) { 2664 CannotYetSelect(NodeToMatch); 2665 return 0; 2666 } 2667 2668 // Restore the interpreter state back to the point where the scope was 2669 // formed. 2670 MatchScope &LastScope = MatchScopes.back(); 2671 RecordedNodes.resize(LastScope.NumRecordedNodes); 2672 NodeStack.clear(); 2673 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2674 N = NodeStack.back(); 2675 2676 DEBUG(errs() << " Match failed at index " << MatcherIndex 2677 << " continuing at " << LastScope.FailIndex << "\n"); 2678 2679 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2680 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2681 MatcherIndex = LastScope.FailIndex; 2682 2683 InputChain = LastScope.InputChain; 2684 InputFlag = LastScope.InputFlag; 2685 if (!LastScope.HasChainNodesMatched) 2686 ChainNodesMatched.clear(); 2687 if (!LastScope.HasFlagResultNodesMatched) 2688 FlagResultNodesMatched.clear(); 2689 2690 // Check to see what the offset is at the new MatcherIndex. If it is zero 2691 // we have reached the end of this scope, otherwise we have another child 2692 // in the current scope to try. 2693 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2694 if (NumToSkip & 128) 2695 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2696 2697 // If we have another child in this scope to match, update FailIndex and 2698 // try it. 2699 if (NumToSkip != 0) { 2700 LastScope.FailIndex = MatcherIndex+NumToSkip; 2701 break; 2702 } 2703 2704 // End of this scope, pop it and try the next child in the containing 2705 // scope. 2706 MatchScopes.pop_back(); 2707 } 2708 } 2709} 2710 2711 2712 2713void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2714 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN || 2715 N->getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2716 N->getOpcode() == ISD::INTRINSIC_VOID) 2717 return CannotYetSelectIntrinsic(N); 2718 2719 std::string msg; 2720 raw_string_ostream Msg(msg); 2721 Msg << "Cannot yet select: "; 2722 N->printrFull(Msg, CurDAG); 2723 llvm_report_error(Msg.str()); 2724} 2725 2726void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) { 2727 dbgs() << "Cannot yet select: "; 2728 unsigned iid = 2729 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == 2730 MVT::Other))->getZExtValue(); 2731 if (iid < Intrinsic::num_intrinsics) 2732 llvm_report_error("Cannot yet select: intrinsic %" + 2733 Intrinsic::getName((Intrinsic::ID)iid)); 2734 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 2735 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 2736 tii->getName(iid)); 2737} 2738 2739char SelectionDAGISel::ID = 0; 2740