SelectionDAGISel.cpp revision 9ce2e9d5a07cb3e0176cb32838231243829d67c5
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57static cl::opt<bool> 58ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 59 cl::desc("Pop up a window to show SUnit dags after they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 62#endif 63 64//===---------------------------------------------------------------------===// 65/// 66/// RegisterScheduler class - Track the registration of instruction schedulers. 67/// 68//===---------------------------------------------------------------------===// 69MachinePassRegistry RegisterScheduler::Registry; 70 71//===---------------------------------------------------------------------===// 72/// 73/// ISHeuristic command line option for instruction schedulers. 74/// 75//===---------------------------------------------------------------------===// 76namespace { 77 cl::opt<RegisterScheduler::FunctionPassCtor, false, 78 RegisterPassParser<RegisterScheduler> > 79 ISHeuristic("pre-RA-sched", 80 cl::init(&createDefaultScheduler), 81 cl::desc("Instruction schedulers available (before register allocation):")); 82 83 static RegisterScheduler 84 defaultListDAGScheduler("default", " Best scheduler for the target", 85 createDefaultScheduler); 86} // namespace 87 88namespace { struct AsmOperandInfo; } 89 90namespace { 91 /// RegsForValue - This struct represents the physical registers that a 92 /// particular value is assigned and the type information about the value. 93 /// This is needed because values can be promoted into larger registers and 94 /// expanded into multiple smaller registers than the value. 95 struct VISIBILITY_HIDDEN RegsForValue { 96 /// Regs - This list holds the register (for legal and promoted values) 97 /// or register set (for expanded values) that the value should be assigned 98 /// to. 99 std::vector<unsigned> Regs; 100 101 /// RegVT - The value type of each register. 102 /// 103 MVT::ValueType RegVT; 104 105 /// ValueVT - The value type of the LLVM value, which may be promoted from 106 /// RegVT or made from merging the two expanded parts. 107 MVT::ValueType ValueVT; 108 109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 110 111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 112 : RegVT(regvt), ValueVT(valuevt) { 113 Regs.push_back(Reg); 114 } 115 RegsForValue(const std::vector<unsigned> ®s, 116 MVT::ValueType regvt, MVT::ValueType valuevt) 117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 118 } 119 120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 121 /// this value and returns the result as a ValueVT value. This uses 122 /// Chain/Flag as the input and updates them for the output Chain/Flag. 123 /// If the Flag pointer is NULL, no flag is used. 124 SDOperand getCopyFromRegs(SelectionDAG &DAG, 125 SDOperand &Chain, SDOperand *Flag) const; 126 127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 128 /// specified value into the registers specified by this object. This uses 129 /// Chain/Flag as the input and updates them for the output Chain/Flag. 130 /// If the Flag pointer is NULL, no flag is used. 131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 132 SDOperand &Chain, SDOperand *Flag) const; 133 134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 135 /// operand list. This adds the code marker and includes the number of 136 /// values added into it. 137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 138 std::vector<SDOperand> &Ops) const; 139 }; 140} 141 142namespace llvm { 143 //===--------------------------------------------------------------------===// 144 /// createDefaultScheduler - This creates an instruction scheduler appropriate 145 /// for the target. 146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 147 SelectionDAG *DAG, 148 MachineBasicBlock *BB) { 149 TargetLowering &TLI = IS->getTargetLowering(); 150 151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 152 return createTDListDAGScheduler(IS, DAG, BB); 153 } else { 154 assert(TLI.getSchedulingPreference() == 155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 156 return createBURRListDAGScheduler(IS, DAG, BB); 157 } 158 } 159 160 161 //===--------------------------------------------------------------------===// 162 /// FunctionLoweringInfo - This contains information that is global to a 163 /// function that is used when lowering a region of the function. 164 class FunctionLoweringInfo { 165 public: 166 TargetLowering &TLI; 167 Function &Fn; 168 MachineFunction &MF; 169 SSARegMap *RegMap; 170 171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 172 173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 175 176 /// ValueMap - Since we emit code for the function a basic block at a time, 177 /// we must remember which virtual registers hold the values for 178 /// cross-basic-block values. 179 DenseMap<const Value*, unsigned> ValueMap; 180 181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 182 /// the entry block. This allows the allocas to be efficiently referenced 183 /// anywhere in the function. 184 std::map<const AllocaInst*, int> StaticAllocaMap; 185 186#ifndef NDEBUG 187 SmallSet<Instruction*, 8> CatchInfoLost; 188 SmallSet<Instruction*, 8> CatchInfoFound; 189#endif 190 191 unsigned MakeReg(MVT::ValueType VT) { 192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 193 } 194 195 /// isExportedInst - Return true if the specified value is an instruction 196 /// exported from its block. 197 bool isExportedInst(const Value *V) { 198 return ValueMap.count(V); 199 } 200 201 unsigned CreateRegForValue(const Value *V); 202 203 unsigned InitializeRegForValue(const Value *V) { 204 unsigned &R = ValueMap[V]; 205 assert(R == 0 && "Already initialized this value register!"); 206 return R = CreateRegForValue(V); 207 } 208 }; 209} 210 211/// isSelector - Return true if this instruction is a call to the 212/// eh.selector intrinsic. 213static bool isSelector(Instruction *I) { 214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 216 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 217 return false; 218} 219 220/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 221/// PHI nodes or outside of the basic block that defines it, or used by a 222/// switch instruction, which may expand to multiple basic blocks. 223static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 224 if (isa<PHINode>(I)) return true; 225 BasicBlock *BB = I->getParent(); 226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 228 // FIXME: Remove switchinst special case. 229 isa<SwitchInst>(*UI)) 230 return true; 231 return false; 232} 233 234/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 235/// entry block, return true. This includes arguments used by switches, since 236/// the switch may expand into multiple basic blocks. 237static bool isOnlyUsedInEntryBlock(Argument *A) { 238 BasicBlock *Entry = A->getParent()->begin(); 239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 241 return false; // Use not in entry block. 242 return true; 243} 244 245FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 246 Function &fn, MachineFunction &mf) 247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 248 249 // Create a vreg for each argument register that is not dead and is used 250 // outside of the entry block for the function. 251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 252 AI != E; ++AI) 253 if (!isOnlyUsedInEntryBlock(AI)) 254 InitializeRegForValue(AI); 255 256 // Initialize the mapping of values to registers. This is only set up for 257 // instruction values that are used outside of the block that defines 258 // them. 259 Function::iterator BB = Fn.begin(), EB = Fn.end(); 260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 263 const Type *Ty = AI->getAllocatedType(); 264 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 265 unsigned Align = 266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 267 AI->getAlignment()); 268 269 TySize *= CUI->getZExtValue(); // Get total allocated size. 270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 271 StaticAllocaMap[AI] = 272 MF.getFrameInfo()->CreateStackObject(TySize, Align); 273 } 274 275 for (; BB != EB; ++BB) 276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 278 if (!isa<AllocaInst>(I) || 279 !StaticAllocaMap.count(cast<AllocaInst>(I))) 280 InitializeRegForValue(I); 281 282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 283 // also creates the initial PHI MachineInstrs, though none of the input 284 // operands are populated. 285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 286 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 287 MBBMap[BB] = MBB; 288 MF.getBasicBlockList().push_back(MBB); 289 290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 291 // appropriate. 292 PHINode *PN; 293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 294 if (PN->use_empty()) continue; 295 296 MVT::ValueType VT = TLI.getValueType(PN->getType()); 297 unsigned NumRegisters = TLI.getNumRegisters(VT); 298 unsigned PHIReg = ValueMap[PN]; 299 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 301 for (unsigned i = 0; i != NumRegisters; ++i) 302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 303 } 304 } 305} 306 307/// CreateRegForValue - Allocate the appropriate number of virtual registers of 308/// the correctly promoted or expanded types. Assign these registers 309/// consecutive vreg numbers and return the first assigned number. 310unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 311 MVT::ValueType VT = TLI.getValueType(V->getType()); 312 313 unsigned NumRegisters = TLI.getNumRegisters(VT); 314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 315 316 unsigned R = MakeReg(RegisterVT); 317 for (unsigned i = 1; i != NumRegisters; ++i) 318 MakeReg(RegisterVT); 319 320 return R; 321} 322 323//===----------------------------------------------------------------------===// 324/// SelectionDAGLowering - This is the common target-independent lowering 325/// implementation that is parameterized by a TargetLowering object. 326/// Also, targets can overload any lowering method. 327/// 328namespace llvm { 329class SelectionDAGLowering { 330 MachineBasicBlock *CurMBB; 331 332 DenseMap<const Value*, SDOperand> NodeMap; 333 334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 335 /// them up and then emit token factor nodes when possible. This allows us to 336 /// get simple disambiguation between loads without worrying about alias 337 /// analysis. 338 std::vector<SDOperand> PendingLoads; 339 340 /// Case - A struct to record the Value for a switch case, and the 341 /// case's target basic block. 342 struct Case { 343 Constant* Low; 344 Constant* High; 345 MachineBasicBlock* BB; 346 347 Case() : Low(0), High(0), BB(0) { } 348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 349 Low(low), High(high), BB(bb) { } 350 uint64_t size() const { 351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 353 return (rHigh - rLow + 1ULL); 354 } 355 }; 356 357 struct CaseBits { 358 uint64_t Mask; 359 MachineBasicBlock* BB; 360 unsigned Bits; 361 362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 363 Mask(mask), BB(bb), Bits(bits) { } 364 }; 365 366 typedef std::vector<Case> CaseVector; 367 typedef std::vector<CaseBits> CaseBitsVector; 368 typedef CaseVector::iterator CaseItr; 369 typedef std::pair<CaseItr, CaseItr> CaseRange; 370 371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 372 /// of conditional branches. 373 struct CaseRec { 374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 375 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 376 377 /// CaseBB - The MBB in which to emit the compare and branch 378 MachineBasicBlock *CaseBB; 379 /// LT, GE - If nonzero, we know the current case value must be less-than or 380 /// greater-than-or-equal-to these Constants. 381 Constant *LT; 382 Constant *GE; 383 /// Range - A pair of iterators representing the range of case values to be 384 /// processed at this point in the binary search tree. 385 CaseRange Range; 386 }; 387 388 typedef std::vector<CaseRec> CaseRecVector; 389 390 /// The comparison function for sorting the switch case values in the vector. 391 /// WARNING: Case ranges should be disjoint! 392 struct CaseCmp { 393 bool operator () (const Case& C1, const Case& C2) { 394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 397 return CI1->getValue().slt(CI2->getValue()); 398 } 399 }; 400 401 struct CaseBitsCmp { 402 bool operator () (const CaseBits& C1, const CaseBits& C2) { 403 return C1.Bits > C2.Bits; 404 } 405 }; 406 407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 408 409public: 410 // TLI - This is information that describes the available target features we 411 // need for lowering. This indicates when operations are unavailable, 412 // implemented with a libcall, etc. 413 TargetLowering &TLI; 414 SelectionDAG &DAG; 415 const TargetData *TD; 416 AliasAnalysis &AA; 417 418 /// SwitchCases - Vector of CaseBlock structures used to communicate 419 /// SwitchInst code generation information. 420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 421 /// JTCases - Vector of JumpTable structures used to communicate 422 /// SwitchInst code generation information. 423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 425 426 /// FuncInfo - Information about the function as a whole. 427 /// 428 FunctionLoweringInfo &FuncInfo; 429 430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 431 AliasAnalysis &aa, 432 FunctionLoweringInfo &funcinfo) 433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 434 FuncInfo(funcinfo) { 435 } 436 437 /// getRoot - Return the current virtual root of the Selection DAG. 438 /// 439 SDOperand getRoot() { 440 if (PendingLoads.empty()) 441 return DAG.getRoot(); 442 443 if (PendingLoads.size() == 1) { 444 SDOperand Root = PendingLoads[0]; 445 DAG.setRoot(Root); 446 PendingLoads.clear(); 447 return Root; 448 } 449 450 // Otherwise, we have to make a token factor node. 451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 452 &PendingLoads[0], PendingLoads.size()); 453 PendingLoads.clear(); 454 DAG.setRoot(Root); 455 return Root; 456 } 457 458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 459 460 void visit(Instruction &I) { visit(I.getOpcode(), I); } 461 462 void visit(unsigned Opcode, User &I) { 463 // Note: this doesn't use InstVisitor, because it has to work with 464 // ConstantExpr's in addition to instructions. 465 switch (Opcode) { 466 default: assert(0 && "Unknown instruction type encountered!"); 467 abort(); 468 // Build the switch statement using the Instruction.def file. 469#define HANDLE_INST(NUM, OPCODE, CLASS) \ 470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 471#include "llvm/Instruction.def" 472 } 473 } 474 475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 476 477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 478 const Value *SV, SDOperand Root, 479 bool isVolatile, unsigned Alignment); 480 481 SDOperand getIntPtrConstant(uint64_t Val) { 482 return DAG.getConstant(Val, TLI.getPointerTy()); 483 } 484 485 SDOperand getValue(const Value *V); 486 487 void setValue(const Value *V, SDOperand NewN) { 488 SDOperand &N = NodeMap[V]; 489 assert(N.Val == 0 && "Already set a value for this node!"); 490 N = NewN; 491 } 492 493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 494 std::set<unsigned> &OutputRegs, 495 std::set<unsigned> &InputRegs); 496 497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 499 unsigned Opc); 500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 501 void ExportFromCurrentBlock(Value *V); 502 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall, 503 MachineBasicBlock *LandingPad = NULL); 504 505 // Terminator instructions. 506 void visitRet(ReturnInst &I); 507 void visitBr(BranchInst &I); 508 void visitSwitch(SwitchInst &I); 509 void visitUnreachable(UnreachableInst &I) { /* noop */ } 510 511 // Helpers for visitSwitch 512 bool handleSmallSwitchRange(CaseRec& CR, 513 CaseRecVector& WorkList, 514 Value* SV, 515 MachineBasicBlock* Default); 516 bool handleJTSwitchCase(CaseRec& CR, 517 CaseRecVector& WorkList, 518 Value* SV, 519 MachineBasicBlock* Default); 520 bool handleBTSplitSwitchCase(CaseRec& CR, 521 CaseRecVector& WorkList, 522 Value* SV, 523 MachineBasicBlock* Default); 524 bool handleBitTestsSwitchCase(CaseRec& CR, 525 CaseRecVector& WorkList, 526 Value* SV, 527 MachineBasicBlock* Default); 528 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 529 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 530 void visitBitTestCase(MachineBasicBlock* NextMBB, 531 unsigned Reg, 532 SelectionDAGISel::BitTestCase &B); 533 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 534 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 535 SelectionDAGISel::JumpTableHeader &JTH); 536 537 // These all get lowered before this pass. 538 void visitInvoke(InvokeInst &I); 539 void visitUnwind(UnwindInst &I); 540 541 void visitBinary(User &I, unsigned OpCode); 542 void visitShift(User &I, unsigned Opcode); 543 void visitAdd(User &I) { 544 if (I.getType()->isFPOrFPVector()) 545 visitBinary(I, ISD::FADD); 546 else 547 visitBinary(I, ISD::ADD); 548 } 549 void visitSub(User &I); 550 void visitMul(User &I) { 551 if (I.getType()->isFPOrFPVector()) 552 visitBinary(I, ISD::FMUL); 553 else 554 visitBinary(I, ISD::MUL); 555 } 556 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 557 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 558 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 559 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 560 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 561 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 562 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 563 void visitOr (User &I) { visitBinary(I, ISD::OR); } 564 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 565 void visitShl (User &I) { visitShift(I, ISD::SHL); } 566 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 567 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 568 void visitICmp(User &I); 569 void visitFCmp(User &I); 570 // Visit the conversion instructions 571 void visitTrunc(User &I); 572 void visitZExt(User &I); 573 void visitSExt(User &I); 574 void visitFPTrunc(User &I); 575 void visitFPExt(User &I); 576 void visitFPToUI(User &I); 577 void visitFPToSI(User &I); 578 void visitUIToFP(User &I); 579 void visitSIToFP(User &I); 580 void visitPtrToInt(User &I); 581 void visitIntToPtr(User &I); 582 void visitBitCast(User &I); 583 584 void visitExtractElement(User &I); 585 void visitInsertElement(User &I); 586 void visitShuffleVector(User &I); 587 588 void visitGetElementPtr(User &I); 589 void visitSelect(User &I); 590 591 void visitMalloc(MallocInst &I); 592 void visitFree(FreeInst &I); 593 void visitAlloca(AllocaInst &I); 594 void visitLoad(LoadInst &I); 595 void visitStore(StoreInst &I); 596 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 597 void visitCall(CallInst &I); 598 void visitInlineAsm(CallSite CS); 599 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 600 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 601 602 void visitVAStart(CallInst &I); 603 void visitVAArg(VAArgInst &I); 604 void visitVAEnd(CallInst &I); 605 void visitVACopy(CallInst &I); 606 607 void visitMemIntrinsic(CallInst &I, unsigned Op); 608 609 void visitUserOp1(Instruction &I) { 610 assert(0 && "UserOp1 should not exist at instruction selection time!"); 611 abort(); 612 } 613 void visitUserOp2(Instruction &I) { 614 assert(0 && "UserOp2 should not exist at instruction selection time!"); 615 abort(); 616 } 617}; 618} // end namespace llvm 619 620 621/// getCopyFromParts - Create a value that contains the 622/// specified legal parts combined into the value they represent. 623static SDOperand getCopyFromParts(SelectionDAG &DAG, 624 const SDOperand *Parts, 625 unsigned NumParts, 626 MVT::ValueType PartVT, 627 MVT::ValueType ValueVT, 628 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 629 if (!MVT::isVector(ValueVT) || NumParts == 1) { 630 SDOperand Val = Parts[0]; 631 632 // If the value was expanded, copy from the top part. 633 if (NumParts > 1) { 634 assert(NumParts == 2 && 635 "Cannot expand to more than 2 elts yet!"); 636 SDOperand Hi = Parts[1]; 637 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 638 std::swap(Val, Hi); 639 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 640 } 641 642 // Otherwise, if the value was promoted or extended, truncate it to the 643 // appropriate type. 644 if (PartVT == ValueVT) 645 return Val; 646 647 if (MVT::isVector(PartVT)) { 648 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 649 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 650 } 651 652 if (MVT::isVector(ValueVT)) { 653 assert(NumParts == 1 && 654 MVT::getVectorElementType(ValueVT) == PartVT && 655 MVT::getVectorNumElements(ValueVT) == 1 && 656 "Only trivial scalar-to-vector conversions should get here!"); 657 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 658 } 659 660 if (MVT::isInteger(PartVT) && 661 MVT::isInteger(ValueVT)) { 662 if (ValueVT < PartVT) { 663 // For a truncate, see if we have any information to 664 // indicate whether the truncated bits will always be 665 // zero or sign-extension. 666 if (AssertOp != ISD::DELETED_NODE) 667 Val = DAG.getNode(AssertOp, PartVT, Val, 668 DAG.getValueType(ValueVT)); 669 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 670 } else { 671 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 672 } 673 } 674 675 if (MVT::isFloatingPoint(PartVT) && 676 MVT::isFloatingPoint(ValueVT)) 677 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 678 679 if (MVT::getSizeInBits(PartVT) == 680 MVT::getSizeInBits(ValueVT)) 681 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 682 683 assert(0 && "Unknown mismatch!"); 684 } 685 686 // Handle a multi-element vector. 687 MVT::ValueType IntermediateVT, RegisterVT; 688 unsigned NumIntermediates; 689 unsigned NumRegs = 690 DAG.getTargetLoweringInfo() 691 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 692 RegisterVT); 693 694 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 695 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 696 assert(RegisterVT == Parts[0].getValueType() && 697 "Part type doesn't match part!"); 698 699 // Assemble the parts into intermediate operands. 700 SmallVector<SDOperand, 8> Ops(NumIntermediates); 701 if (NumIntermediates == NumParts) { 702 // If the register was not expanded, truncate or copy the value, 703 // as appropriate. 704 for (unsigned i = 0; i != NumParts; ++i) 705 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 706 PartVT, IntermediateVT); 707 } else if (NumParts > 0) { 708 // If the intermediate type was expanded, build the intermediate operands 709 // from the parts. 710 assert(NumParts % NumIntermediates == 0 && 711 "Must expand into a divisible number of parts!"); 712 unsigned Factor = NumParts / NumIntermediates; 713 for (unsigned i = 0; i != NumIntermediates; ++i) 714 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 715 PartVT, IntermediateVT); 716 } 717 718 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 719 // operands. 720 return DAG.getNode(MVT::isVector(IntermediateVT) ? 721 ISD::CONCAT_VECTORS : 722 ISD::BUILD_VECTOR, 723 ValueVT, &Ops[0], NumIntermediates); 724} 725 726/// getCopyToParts - Create a series of nodes that contain the 727/// specified value split into legal parts. 728static void getCopyToParts(SelectionDAG &DAG, 729 SDOperand Val, 730 SDOperand *Parts, 731 unsigned NumParts, 732 MVT::ValueType PartVT) { 733 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 734 MVT::ValueType PtrVT = TLI.getPointerTy(); 735 MVT::ValueType ValueVT = Val.getValueType(); 736 737 if (!MVT::isVector(ValueVT) || NumParts == 1) { 738 // If the value was expanded, copy from the parts. 739 if (NumParts > 1) { 740 for (unsigned i = 0; i != NumParts; ++i) 741 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 742 DAG.getConstant(i, PtrVT)); 743 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 744 std::reverse(Parts, Parts + NumParts); 745 return; 746 } 747 748 // If there is a single part and the types differ, this must be 749 // a promotion. 750 if (PartVT != ValueVT) { 751 if (MVT::isVector(PartVT)) { 752 assert(MVT::isVector(ValueVT) && 753 "Not a vector-vector cast?"); 754 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 755 } else if (MVT::isVector(ValueVT)) { 756 assert(NumParts == 1 && 757 MVT::getVectorElementType(ValueVT) == PartVT && 758 MVT::getVectorNumElements(ValueVT) == 1 && 759 "Only trivial vector-to-scalar conversions should get here!"); 760 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 761 DAG.getConstant(0, PtrVT)); 762 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 763 if (PartVT < ValueVT) 764 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 765 else 766 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 767 } else if (MVT::isFloatingPoint(PartVT) && 768 MVT::isFloatingPoint(ValueVT)) { 769 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 770 } else if (MVT::getSizeInBits(PartVT) == 771 MVT::getSizeInBits(ValueVT)) { 772 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 773 } else { 774 assert(0 && "Unknown mismatch!"); 775 } 776 } 777 Parts[0] = Val; 778 return; 779 } 780 781 // Handle a multi-element vector. 782 MVT::ValueType IntermediateVT, RegisterVT; 783 unsigned NumIntermediates; 784 unsigned NumRegs = 785 DAG.getTargetLoweringInfo() 786 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 787 RegisterVT); 788 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 789 790 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 791 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 792 793 // Split the vector into intermediate operands. 794 SmallVector<SDOperand, 8> Ops(NumIntermediates); 795 for (unsigned i = 0; i != NumIntermediates; ++i) 796 if (MVT::isVector(IntermediateVT)) 797 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 798 IntermediateVT, Val, 799 DAG.getConstant(i * (NumElements / NumIntermediates), 800 PtrVT)); 801 else 802 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 803 IntermediateVT, Val, 804 DAG.getConstant(i, PtrVT)); 805 806 // Split the intermediate operands into legal parts. 807 if (NumParts == NumIntermediates) { 808 // If the register was not expanded, promote or copy the value, 809 // as appropriate. 810 for (unsigned i = 0; i != NumParts; ++i) 811 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 812 } else if (NumParts > 0) { 813 // If the intermediate type was expanded, split each the value into 814 // legal parts. 815 assert(NumParts % NumIntermediates == 0 && 816 "Must expand into a divisible number of parts!"); 817 unsigned Factor = NumParts / NumIntermediates; 818 for (unsigned i = 0; i != NumIntermediates; ++i) 819 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 820 } 821} 822 823 824SDOperand SelectionDAGLowering::getValue(const Value *V) { 825 SDOperand &N = NodeMap[V]; 826 if (N.Val) return N; 827 828 const Type *VTy = V->getType(); 829 MVT::ValueType VT = TLI.getValueType(VTy); 830 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 831 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 832 visit(CE->getOpcode(), *CE); 833 SDOperand N1 = NodeMap[V]; 834 assert(N1.Val && "visit didn't populate the ValueMap!"); 835 return N1; 836 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 837 return N = DAG.getGlobalAddress(GV, VT); 838 } else if (isa<ConstantPointerNull>(C)) { 839 return N = DAG.getConstant(0, TLI.getPointerTy()); 840 } else if (isa<UndefValue>(C)) { 841 if (!isa<VectorType>(VTy)) 842 return N = DAG.getNode(ISD::UNDEF, VT); 843 844 // Create a BUILD_VECTOR of undef nodes. 845 const VectorType *PTy = cast<VectorType>(VTy); 846 unsigned NumElements = PTy->getNumElements(); 847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 848 849 SmallVector<SDOperand, 8> Ops; 850 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 851 852 // Create a VConstant node with generic Vector type. 853 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 854 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 855 &Ops[0], Ops.size()); 856 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 857 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 858 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 859 unsigned NumElements = PTy->getNumElements(); 860 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 861 862 // Now that we know the number and type of the elements, push a 863 // Constant or ConstantFP node onto the ops list for each element of 864 // the vector constant. 865 SmallVector<SDOperand, 8> Ops; 866 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 867 for (unsigned i = 0; i != NumElements; ++i) 868 Ops.push_back(getValue(CP->getOperand(i))); 869 } else { 870 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 871 SDOperand Op; 872 if (MVT::isFloatingPoint(PVT)) 873 Op = DAG.getConstantFP(0, PVT); 874 else 875 Op = DAG.getConstant(0, PVT); 876 Ops.assign(NumElements, Op); 877 } 878 879 // Create a BUILD_VECTOR node. 880 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 881 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 882 Ops.size()); 883 } else { 884 // Canonicalize all constant ints to be unsigned. 885 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 886 } 887 } 888 889 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 890 std::map<const AllocaInst*, int>::iterator SI = 891 FuncInfo.StaticAllocaMap.find(AI); 892 if (SI != FuncInfo.StaticAllocaMap.end()) 893 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 894 } 895 896 unsigned InReg = FuncInfo.ValueMap[V]; 897 assert(InReg && "Value not in map!"); 898 899 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 900 unsigned NumRegs = TLI.getNumRegisters(VT); 901 902 std::vector<unsigned> Regs(NumRegs); 903 for (unsigned i = 0; i != NumRegs; ++i) 904 Regs[i] = InReg + i; 905 906 RegsForValue RFV(Regs, RegisterVT, VT); 907 SDOperand Chain = DAG.getEntryNode(); 908 909 return RFV.getCopyFromRegs(DAG, Chain, NULL); 910} 911 912 913void SelectionDAGLowering::visitRet(ReturnInst &I) { 914 if (I.getNumOperands() == 0) { 915 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 916 return; 917 } 918 SmallVector<SDOperand, 8> NewValues; 919 NewValues.push_back(getRoot()); 920 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 921 SDOperand RetOp = getValue(I.getOperand(i)); 922 923 // If this is an integer return value, we need to promote it ourselves to 924 // the full width of a register, since getCopyToParts and Legalize will use 925 // ANY_EXTEND rather than sign/zero. 926 // FIXME: C calling convention requires the return type to be promoted to 927 // at least 32-bit. But this is not necessary for non-C calling conventions. 928 if (MVT::isInteger(RetOp.getValueType()) && 929 RetOp.getValueType() < MVT::i64) { 930 MVT::ValueType TmpVT; 931 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 932 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 933 else 934 TmpVT = MVT::i32; 935 const Function *F = I.getParent()->getParent(); 936 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 937 if (F->paramHasAttr(0, ParamAttr::SExt)) 938 ExtendKind = ISD::SIGN_EXTEND; 939 if (F->paramHasAttr(0, ParamAttr::ZExt)) 940 ExtendKind = ISD::ZERO_EXTEND; 941 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 942 NewValues.push_back(RetOp); 943 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 944 } else { 945 MVT::ValueType VT = RetOp.getValueType(); 946 unsigned NumParts = TLI.getNumRegisters(VT); 947 MVT::ValueType PartVT = TLI.getRegisterType(VT); 948 SmallVector<SDOperand, 4> Parts(NumParts); 949 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 950 for (unsigned i = 0; i < NumParts; ++i) { 951 NewValues.push_back(Parts[i]); 952 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 953 } 954 } 955 } 956 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 957 &NewValues[0], NewValues.size())); 958} 959 960/// ExportFromCurrentBlock - If this condition isn't known to be exported from 961/// the current basic block, add it to ValueMap now so that we'll get a 962/// CopyTo/FromReg. 963void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 964 // No need to export constants. 965 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 966 967 // Already exported? 968 if (FuncInfo.isExportedInst(V)) return; 969 970 unsigned Reg = FuncInfo.InitializeRegForValue(V); 971 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 972} 973 974bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 975 const BasicBlock *FromBB) { 976 // The operands of the setcc have to be in this block. We don't know 977 // how to export them from some other block. 978 if (Instruction *VI = dyn_cast<Instruction>(V)) { 979 // Can export from current BB. 980 if (VI->getParent() == FromBB) 981 return true; 982 983 // Is already exported, noop. 984 return FuncInfo.isExportedInst(V); 985 } 986 987 // If this is an argument, we can export it if the BB is the entry block or 988 // if it is already exported. 989 if (isa<Argument>(V)) { 990 if (FromBB == &FromBB->getParent()->getEntryBlock()) 991 return true; 992 993 // Otherwise, can only export this if it is already exported. 994 return FuncInfo.isExportedInst(V); 995 } 996 997 // Otherwise, constants can always be exported. 998 return true; 999} 1000 1001static bool InBlock(const Value *V, const BasicBlock *BB) { 1002 if (const Instruction *I = dyn_cast<Instruction>(V)) 1003 return I->getParent() == BB; 1004 return true; 1005} 1006 1007/// FindMergedConditions - If Cond is an expression like 1008void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1009 MachineBasicBlock *TBB, 1010 MachineBasicBlock *FBB, 1011 MachineBasicBlock *CurBB, 1012 unsigned Opc) { 1013 // If this node is not part of the or/and tree, emit it as a branch. 1014 Instruction *BOp = dyn_cast<Instruction>(Cond); 1015 1016 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1017 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1018 BOp->getParent() != CurBB->getBasicBlock() || 1019 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1020 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1021 const BasicBlock *BB = CurBB->getBasicBlock(); 1022 1023 // If the leaf of the tree is a comparison, merge the condition into 1024 // the caseblock. 1025 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1026 // The operands of the cmp have to be in this block. We don't know 1027 // how to export them from some other block. If this is the first block 1028 // of the sequence, no exporting is needed. 1029 (CurBB == CurMBB || 1030 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1031 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1032 BOp = cast<Instruction>(Cond); 1033 ISD::CondCode Condition; 1034 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1035 switch (IC->getPredicate()) { 1036 default: assert(0 && "Unknown icmp predicate opcode!"); 1037 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1038 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1039 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1040 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1041 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1042 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1043 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1044 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1045 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1046 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1047 } 1048 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1049 ISD::CondCode FPC, FOC; 1050 switch (FC->getPredicate()) { 1051 default: assert(0 && "Unknown fcmp predicate opcode!"); 1052 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1053 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1054 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1055 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1056 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1057 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1058 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1059 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1060 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1061 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1062 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1063 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1064 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1065 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1066 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1067 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1068 } 1069 if (FiniteOnlyFPMath()) 1070 Condition = FOC; 1071 else 1072 Condition = FPC; 1073 } else { 1074 Condition = ISD::SETEQ; // silence warning. 1075 assert(0 && "Unknown compare instruction"); 1076 } 1077 1078 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1079 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1080 SwitchCases.push_back(CB); 1081 return; 1082 } 1083 1084 // Create a CaseBlock record representing this branch. 1085 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1086 NULL, TBB, FBB, CurBB); 1087 SwitchCases.push_back(CB); 1088 return; 1089 } 1090 1091 1092 // Create TmpBB after CurBB. 1093 MachineFunction::iterator BBI = CurBB; 1094 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1095 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1096 1097 if (Opc == Instruction::Or) { 1098 // Codegen X | Y as: 1099 // jmp_if_X TBB 1100 // jmp TmpBB 1101 // TmpBB: 1102 // jmp_if_Y TBB 1103 // jmp FBB 1104 // 1105 1106 // Emit the LHS condition. 1107 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1108 1109 // Emit the RHS condition into TmpBB. 1110 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1111 } else { 1112 assert(Opc == Instruction::And && "Unknown merge op!"); 1113 // Codegen X & Y as: 1114 // jmp_if_X TmpBB 1115 // jmp FBB 1116 // TmpBB: 1117 // jmp_if_Y TBB 1118 // jmp FBB 1119 // 1120 // This requires creation of TmpBB after CurBB. 1121 1122 // Emit the LHS condition. 1123 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1124 1125 // Emit the RHS condition into TmpBB. 1126 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1127 } 1128} 1129 1130/// If the set of cases should be emitted as a series of branches, return true. 1131/// If we should emit this as a bunch of and/or'd together conditions, return 1132/// false. 1133static bool 1134ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1135 if (Cases.size() != 2) return true; 1136 1137 // If this is two comparisons of the same values or'd or and'd together, they 1138 // will get folded into a single comparison, so don't emit two blocks. 1139 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1140 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1141 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1142 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1143 return false; 1144 } 1145 1146 return true; 1147} 1148 1149void SelectionDAGLowering::visitBr(BranchInst &I) { 1150 // Update machine-CFG edges. 1151 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1152 1153 // Figure out which block is immediately after the current one. 1154 MachineBasicBlock *NextBlock = 0; 1155 MachineFunction::iterator BBI = CurMBB; 1156 if (++BBI != CurMBB->getParent()->end()) 1157 NextBlock = BBI; 1158 1159 if (I.isUnconditional()) { 1160 // If this is not a fall-through branch, emit the branch. 1161 if (Succ0MBB != NextBlock) 1162 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1163 DAG.getBasicBlock(Succ0MBB))); 1164 1165 // Update machine-CFG edges. 1166 CurMBB->addSuccessor(Succ0MBB); 1167 return; 1168 } 1169 1170 // If this condition is one of the special cases we handle, do special stuff 1171 // now. 1172 Value *CondVal = I.getCondition(); 1173 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1174 1175 // If this is a series of conditions that are or'd or and'd together, emit 1176 // this as a sequence of branches instead of setcc's with and/or operations. 1177 // For example, instead of something like: 1178 // cmp A, B 1179 // C = seteq 1180 // cmp D, E 1181 // F = setle 1182 // or C, F 1183 // jnz foo 1184 // Emit: 1185 // cmp A, B 1186 // je foo 1187 // cmp D, E 1188 // jle foo 1189 // 1190 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1191 if (BOp->hasOneUse() && 1192 (BOp->getOpcode() == Instruction::And || 1193 BOp->getOpcode() == Instruction::Or)) { 1194 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1195 // If the compares in later blocks need to use values not currently 1196 // exported from this block, export them now. This block should always 1197 // be the first entry. 1198 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1199 1200 // Allow some cases to be rejected. 1201 if (ShouldEmitAsBranches(SwitchCases)) { 1202 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1203 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1204 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1205 } 1206 1207 // Emit the branch for this block. 1208 visitSwitchCase(SwitchCases[0]); 1209 SwitchCases.erase(SwitchCases.begin()); 1210 return; 1211 } 1212 1213 // Okay, we decided not to do this, remove any inserted MBB's and clear 1214 // SwitchCases. 1215 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1216 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1217 1218 SwitchCases.clear(); 1219 } 1220 } 1221 1222 // Create a CaseBlock record representing this branch. 1223 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1224 NULL, Succ0MBB, Succ1MBB, CurMBB); 1225 // Use visitSwitchCase to actually insert the fast branch sequence for this 1226 // cond branch. 1227 visitSwitchCase(CB); 1228} 1229 1230/// visitSwitchCase - Emits the necessary code to represent a single node in 1231/// the binary search tree resulting from lowering a switch instruction. 1232void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1233 SDOperand Cond; 1234 SDOperand CondLHS = getValue(CB.CmpLHS); 1235 1236 // Build the setcc now. 1237 if (CB.CmpMHS == NULL) { 1238 // Fold "(X == true)" to X and "(X == false)" to !X to 1239 // handle common cases produced by branch lowering. 1240 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1241 Cond = CondLHS; 1242 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1243 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1244 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1245 } else 1246 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1247 } else { 1248 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1249 1250 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1251 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1252 1253 SDOperand CmpOp = getValue(CB.CmpMHS); 1254 MVT::ValueType VT = CmpOp.getValueType(); 1255 1256 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1257 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1258 } else { 1259 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1260 Cond = DAG.getSetCC(MVT::i1, SUB, 1261 DAG.getConstant(High-Low, VT), ISD::SETULE); 1262 } 1263 1264 } 1265 1266 // Set NextBlock to be the MBB immediately after the current one, if any. 1267 // This is used to avoid emitting unnecessary branches to the next block. 1268 MachineBasicBlock *NextBlock = 0; 1269 MachineFunction::iterator BBI = CurMBB; 1270 if (++BBI != CurMBB->getParent()->end()) 1271 NextBlock = BBI; 1272 1273 // If the lhs block is the next block, invert the condition so that we can 1274 // fall through to the lhs instead of the rhs block. 1275 if (CB.TrueBB == NextBlock) { 1276 std::swap(CB.TrueBB, CB.FalseBB); 1277 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1278 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1279 } 1280 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1281 DAG.getBasicBlock(CB.TrueBB)); 1282 if (CB.FalseBB == NextBlock) 1283 DAG.setRoot(BrCond); 1284 else 1285 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1286 DAG.getBasicBlock(CB.FalseBB))); 1287 // Update successor info 1288 CurMBB->addSuccessor(CB.TrueBB); 1289 CurMBB->addSuccessor(CB.FalseBB); 1290} 1291 1292/// visitJumpTable - Emit JumpTable node in the current MBB 1293void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1294 // Emit the code for the jump table 1295 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1296 MVT::ValueType PTy = TLI.getPointerTy(); 1297 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1298 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1299 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1300 Table, Index)); 1301 return; 1302} 1303 1304/// visitJumpTableHeader - This function emits necessary code to produce index 1305/// in the JumpTable from switch case. 1306void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1307 SelectionDAGISel::JumpTableHeader &JTH) { 1308 // Subtract the lowest switch case value from the value being switched on 1309 // and conditional branch to default mbb if the result is greater than the 1310 // difference between smallest and largest cases. 1311 SDOperand SwitchOp = getValue(JTH.SValue); 1312 MVT::ValueType VT = SwitchOp.getValueType(); 1313 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1314 DAG.getConstant(JTH.First, VT)); 1315 1316 // The SDNode we just created, which holds the value being switched on 1317 // minus the the smallest case value, needs to be copied to a virtual 1318 // register so it can be used as an index into the jump table in a 1319 // subsequent basic block. This value may be smaller or larger than the 1320 // target's pointer type, and therefore require extension or truncating. 1321 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1322 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1323 else 1324 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1325 1326 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1327 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1328 JT.Reg = JumpTableReg; 1329 1330 // Emit the range check for the jump table, and branch to the default 1331 // block for the switch statement if the value being switched on exceeds 1332 // the largest case in the switch. 1333 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1334 DAG.getConstant(JTH.Last-JTH.First,VT), 1335 ISD::SETUGT); 1336 1337 // Set NextBlock to be the MBB immediately after the current one, if any. 1338 // This is used to avoid emitting unnecessary branches to the next block. 1339 MachineBasicBlock *NextBlock = 0; 1340 MachineFunction::iterator BBI = CurMBB; 1341 if (++BBI != CurMBB->getParent()->end()) 1342 NextBlock = BBI; 1343 1344 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1345 DAG.getBasicBlock(JT.Default)); 1346 1347 if (JT.MBB == NextBlock) 1348 DAG.setRoot(BrCond); 1349 else 1350 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1351 DAG.getBasicBlock(JT.MBB))); 1352 1353 return; 1354} 1355 1356/// visitBitTestHeader - This function emits necessary code to produce value 1357/// suitable for "bit tests" 1358void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1359 // Subtract the minimum value 1360 SDOperand SwitchOp = getValue(B.SValue); 1361 MVT::ValueType VT = SwitchOp.getValueType(); 1362 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1363 DAG.getConstant(B.First, VT)); 1364 1365 // Check range 1366 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1367 DAG.getConstant(B.Range, VT), 1368 ISD::SETUGT); 1369 1370 SDOperand ShiftOp; 1371 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1372 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1373 else 1374 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1375 1376 // Make desired shift 1377 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1378 DAG.getConstant(1, TLI.getPointerTy()), 1379 ShiftOp); 1380 1381 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1382 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1383 B.Reg = SwitchReg; 1384 1385 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1386 DAG.getBasicBlock(B.Default)); 1387 1388 // Set NextBlock to be the MBB immediately after the current one, if any. 1389 // This is used to avoid emitting unnecessary branches to the next block. 1390 MachineBasicBlock *NextBlock = 0; 1391 MachineFunction::iterator BBI = CurMBB; 1392 if (++BBI != CurMBB->getParent()->end()) 1393 NextBlock = BBI; 1394 1395 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1396 if (MBB == NextBlock) 1397 DAG.setRoot(BrRange); 1398 else 1399 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1400 DAG.getBasicBlock(MBB))); 1401 1402 CurMBB->addSuccessor(B.Default); 1403 CurMBB->addSuccessor(MBB); 1404 1405 return; 1406} 1407 1408/// visitBitTestCase - this function produces one "bit test" 1409void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1410 unsigned Reg, 1411 SelectionDAGISel::BitTestCase &B) { 1412 // Emit bit tests and jumps 1413 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1414 1415 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1416 SwitchVal, 1417 DAG.getConstant(B.Mask, 1418 TLI.getPointerTy())); 1419 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1420 DAG.getConstant(0, TLI.getPointerTy()), 1421 ISD::SETNE); 1422 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1423 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1424 1425 // Set NextBlock to be the MBB immediately after the current one, if any. 1426 // This is used to avoid emitting unnecessary branches to the next block. 1427 MachineBasicBlock *NextBlock = 0; 1428 MachineFunction::iterator BBI = CurMBB; 1429 if (++BBI != CurMBB->getParent()->end()) 1430 NextBlock = BBI; 1431 1432 if (NextMBB == NextBlock) 1433 DAG.setRoot(BrAnd); 1434 else 1435 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1436 DAG.getBasicBlock(NextMBB))); 1437 1438 CurMBB->addSuccessor(B.TargetBB); 1439 CurMBB->addSuccessor(NextMBB); 1440 1441 return; 1442} 1443 1444void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1445 // Retrieve successors. 1446 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1447 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1448 1449 if (isa<InlineAsm>(I.getCalledValue())) 1450 visitInlineAsm(&I); 1451 else 1452 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1453 1454 // If the value of the invoke is used outside of its defining block, make it 1455 // available as a virtual register. 1456 if (!I.use_empty()) { 1457 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1458 if (VMI != FuncInfo.ValueMap.end()) 1459 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1460 } 1461 1462 // Drop into normal successor. 1463 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1464 DAG.getBasicBlock(Return))); 1465 1466 // Update successor info 1467 CurMBB->addSuccessor(Return); 1468 CurMBB->addSuccessor(LandingPad); 1469} 1470 1471void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1472} 1473 1474/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1475/// small case ranges). 1476bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1477 CaseRecVector& WorkList, 1478 Value* SV, 1479 MachineBasicBlock* Default) { 1480 Case& BackCase = *(CR.Range.second-1); 1481 1482 // Size is the number of Cases represented by this range. 1483 unsigned Size = CR.Range.second - CR.Range.first; 1484 if (Size > 3) 1485 return false; 1486 1487 // Get the MachineFunction which holds the current MBB. This is used when 1488 // inserting any additional MBBs necessary to represent the switch. 1489 MachineFunction *CurMF = CurMBB->getParent(); 1490 1491 // Figure out which block is immediately after the current one. 1492 MachineBasicBlock *NextBlock = 0; 1493 MachineFunction::iterator BBI = CR.CaseBB; 1494 1495 if (++BBI != CurMBB->getParent()->end()) 1496 NextBlock = BBI; 1497 1498 // TODO: If any two of the cases has the same destination, and if one value 1499 // is the same as the other, but has one bit unset that the other has set, 1500 // use bit manipulation to do two compares at once. For example: 1501 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1502 1503 // Rearrange the case blocks so that the last one falls through if possible. 1504 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1505 // The last case block won't fall through into 'NextBlock' if we emit the 1506 // branches in this order. See if rearranging a case value would help. 1507 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1508 if (I->BB == NextBlock) { 1509 std::swap(*I, BackCase); 1510 break; 1511 } 1512 } 1513 } 1514 1515 // Create a CaseBlock record representing a conditional branch to 1516 // the Case's target mbb if the value being switched on SV is equal 1517 // to C. 1518 MachineBasicBlock *CurBlock = CR.CaseBB; 1519 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1520 MachineBasicBlock *FallThrough; 1521 if (I != E-1) { 1522 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1523 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1524 } else { 1525 // If the last case doesn't match, go to the default block. 1526 FallThrough = Default; 1527 } 1528 1529 Value *RHS, *LHS, *MHS; 1530 ISD::CondCode CC; 1531 if (I->High == I->Low) { 1532 // This is just small small case range :) containing exactly 1 case 1533 CC = ISD::SETEQ; 1534 LHS = SV; RHS = I->High; MHS = NULL; 1535 } else { 1536 CC = ISD::SETLE; 1537 LHS = I->Low; MHS = SV; RHS = I->High; 1538 } 1539 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1540 I->BB, FallThrough, CurBlock); 1541 1542 // If emitting the first comparison, just call visitSwitchCase to emit the 1543 // code into the current block. Otherwise, push the CaseBlock onto the 1544 // vector to be later processed by SDISel, and insert the node's MBB 1545 // before the next MBB. 1546 if (CurBlock == CurMBB) 1547 visitSwitchCase(CB); 1548 else 1549 SwitchCases.push_back(CB); 1550 1551 CurBlock = FallThrough; 1552 } 1553 1554 return true; 1555} 1556 1557static inline bool areJTsAllowed(const TargetLowering &TLI) { 1558 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1559 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1560} 1561 1562/// handleJTSwitchCase - Emit jumptable for current switch case range 1563bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1564 CaseRecVector& WorkList, 1565 Value* SV, 1566 MachineBasicBlock* Default) { 1567 Case& FrontCase = *CR.Range.first; 1568 Case& BackCase = *(CR.Range.second-1); 1569 1570 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1571 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1572 1573 uint64_t TSize = 0; 1574 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1575 I!=E; ++I) 1576 TSize += I->size(); 1577 1578 if (!areJTsAllowed(TLI) || TSize <= 3) 1579 return false; 1580 1581 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1582 if (Density < 0.4) 1583 return false; 1584 1585 DOUT << "Lowering jump table\n" 1586 << "First entry: " << First << ". Last entry: " << Last << "\n" 1587 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1588 1589 // Get the MachineFunction which holds the current MBB. This is used when 1590 // inserting any additional MBBs necessary to represent the switch. 1591 MachineFunction *CurMF = CurMBB->getParent(); 1592 1593 // Figure out which block is immediately after the current one. 1594 MachineBasicBlock *NextBlock = 0; 1595 MachineFunction::iterator BBI = CR.CaseBB; 1596 1597 if (++BBI != CurMBB->getParent()->end()) 1598 NextBlock = BBI; 1599 1600 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1601 1602 // Create a new basic block to hold the code for loading the address 1603 // of the jump table, and jumping to it. Update successor information; 1604 // we will either branch to the default case for the switch, or the jump 1605 // table. 1606 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1607 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1608 CR.CaseBB->addSuccessor(Default); 1609 CR.CaseBB->addSuccessor(JumpTableBB); 1610 1611 // Build a vector of destination BBs, corresponding to each target 1612 // of the jump table. If the value of the jump table slot corresponds to 1613 // a case statement, push the case's BB onto the vector, otherwise, push 1614 // the default BB. 1615 std::vector<MachineBasicBlock*> DestBBs; 1616 int64_t TEI = First; 1617 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1618 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1619 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1620 1621 if ((Low <= TEI) && (TEI <= High)) { 1622 DestBBs.push_back(I->BB); 1623 if (TEI==High) 1624 ++I; 1625 } else { 1626 DestBBs.push_back(Default); 1627 } 1628 } 1629 1630 // Update successor info. Add one edge to each unique successor. 1631 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1632 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1633 E = DestBBs.end(); I != E; ++I) { 1634 if (!SuccsHandled[(*I)->getNumber()]) { 1635 SuccsHandled[(*I)->getNumber()] = true; 1636 JumpTableBB->addSuccessor(*I); 1637 } 1638 } 1639 1640 // Create a jump table index for this jump table, or return an existing 1641 // one. 1642 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1643 1644 // Set the jump table information so that we can codegen it as a second 1645 // MachineBasicBlock 1646 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1647 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1648 (CR.CaseBB == CurMBB)); 1649 if (CR.CaseBB == CurMBB) 1650 visitJumpTableHeader(JT, JTH); 1651 1652 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1653 1654 return true; 1655} 1656 1657/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1658/// 2 subtrees. 1659bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1660 CaseRecVector& WorkList, 1661 Value* SV, 1662 MachineBasicBlock* Default) { 1663 // Get the MachineFunction which holds the current MBB. This is used when 1664 // inserting any additional MBBs necessary to represent the switch. 1665 MachineFunction *CurMF = CurMBB->getParent(); 1666 1667 // Figure out which block is immediately after the current one. 1668 MachineBasicBlock *NextBlock = 0; 1669 MachineFunction::iterator BBI = CR.CaseBB; 1670 1671 if (++BBI != CurMBB->getParent()->end()) 1672 NextBlock = BBI; 1673 1674 Case& FrontCase = *CR.Range.first; 1675 Case& BackCase = *(CR.Range.second-1); 1676 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1677 1678 // Size is the number of Cases represented by this range. 1679 unsigned Size = CR.Range.second - CR.Range.first; 1680 1681 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1682 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1683 double FMetric = 0; 1684 CaseItr Pivot = CR.Range.first + Size/2; 1685 1686 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1687 // (heuristically) allow us to emit JumpTable's later. 1688 uint64_t TSize = 0; 1689 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1690 I!=E; ++I) 1691 TSize += I->size(); 1692 1693 uint64_t LSize = FrontCase.size(); 1694 uint64_t RSize = TSize-LSize; 1695 DOUT << "Selecting best pivot: \n" 1696 << "First: " << First << ", Last: " << Last <<"\n" 1697 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1698 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1699 J!=E; ++I, ++J) { 1700 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1701 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1702 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1703 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1704 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1705 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1706 // Should always split in some non-trivial place 1707 DOUT <<"=>Step\n" 1708 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1709 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1710 << "Metric: " << Metric << "\n"; 1711 if (FMetric < Metric) { 1712 Pivot = J; 1713 FMetric = Metric; 1714 DOUT << "Current metric set to: " << FMetric << "\n"; 1715 } 1716 1717 LSize += J->size(); 1718 RSize -= J->size(); 1719 } 1720 if (areJTsAllowed(TLI)) { 1721 // If our case is dense we *really* should handle it earlier! 1722 assert((FMetric > 0) && "Should handle dense range earlier!"); 1723 } else { 1724 Pivot = CR.Range.first + Size/2; 1725 } 1726 1727 CaseRange LHSR(CR.Range.first, Pivot); 1728 CaseRange RHSR(Pivot, CR.Range.second); 1729 Constant *C = Pivot->Low; 1730 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1731 1732 // We know that we branch to the LHS if the Value being switched on is 1733 // less than the Pivot value, C. We use this to optimize our binary 1734 // tree a bit, by recognizing that if SV is greater than or equal to the 1735 // LHS's Case Value, and that Case Value is exactly one less than the 1736 // Pivot's Value, then we can branch directly to the LHS's Target, 1737 // rather than creating a leaf node for it. 1738 if ((LHSR.second - LHSR.first) == 1 && 1739 LHSR.first->High == CR.GE && 1740 cast<ConstantInt>(C)->getSExtValue() == 1741 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1742 TrueBB = LHSR.first->BB; 1743 } else { 1744 TrueBB = new MachineBasicBlock(LLVMBB); 1745 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1746 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1747 } 1748 1749 // Similar to the optimization above, if the Value being switched on is 1750 // known to be less than the Constant CR.LT, and the current Case Value 1751 // is CR.LT - 1, then we can branch directly to the target block for 1752 // the current Case Value, rather than emitting a RHS leaf node for it. 1753 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1754 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1755 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1756 FalseBB = RHSR.first->BB; 1757 } else { 1758 FalseBB = new MachineBasicBlock(LLVMBB); 1759 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1760 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1761 } 1762 1763 // Create a CaseBlock record representing a conditional branch to 1764 // the LHS node if the value being switched on SV is less than C. 1765 // Otherwise, branch to LHS. 1766 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1767 TrueBB, FalseBB, CR.CaseBB); 1768 1769 if (CR.CaseBB == CurMBB) 1770 visitSwitchCase(CB); 1771 else 1772 SwitchCases.push_back(CB); 1773 1774 return true; 1775} 1776 1777/// handleBitTestsSwitchCase - if current case range has few destination and 1778/// range span less, than machine word bitwidth, encode case range into series 1779/// of masks and emit bit tests with these masks. 1780bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1781 CaseRecVector& WorkList, 1782 Value* SV, 1783 MachineBasicBlock* Default){ 1784 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1785 1786 Case& FrontCase = *CR.Range.first; 1787 Case& BackCase = *(CR.Range.second-1); 1788 1789 // Get the MachineFunction which holds the current MBB. This is used when 1790 // inserting any additional MBBs necessary to represent the switch. 1791 MachineFunction *CurMF = CurMBB->getParent(); 1792 1793 unsigned numCmps = 0; 1794 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1795 I!=E; ++I) { 1796 // Single case counts one, case range - two. 1797 if (I->Low == I->High) 1798 numCmps +=1; 1799 else 1800 numCmps +=2; 1801 } 1802 1803 // Count unique destinations 1804 SmallSet<MachineBasicBlock*, 4> Dests; 1805 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1806 Dests.insert(I->BB); 1807 if (Dests.size() > 3) 1808 // Don't bother the code below, if there are too much unique destinations 1809 return false; 1810 } 1811 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1812 << "Total number of comparisons: " << numCmps << "\n"; 1813 1814 // Compute span of values. 1815 Constant* minValue = FrontCase.Low; 1816 Constant* maxValue = BackCase.High; 1817 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1818 cast<ConstantInt>(minValue)->getSExtValue(); 1819 DOUT << "Compare range: " << range << "\n" 1820 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1821 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1822 1823 if (range>=IntPtrBits || 1824 (!(Dests.size() == 1 && numCmps >= 3) && 1825 !(Dests.size() == 2 && numCmps >= 5) && 1826 !(Dests.size() >= 3 && numCmps >= 6))) 1827 return false; 1828 1829 DOUT << "Emitting bit tests\n"; 1830 int64_t lowBound = 0; 1831 1832 // Optimize the case where all the case values fit in a 1833 // word without having to subtract minValue. In this case, 1834 // we can optimize away the subtraction. 1835 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1836 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1837 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1838 } else { 1839 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1840 } 1841 1842 CaseBitsVector CasesBits; 1843 unsigned i, count = 0; 1844 1845 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1846 MachineBasicBlock* Dest = I->BB; 1847 for (i = 0; i < count; ++i) 1848 if (Dest == CasesBits[i].BB) 1849 break; 1850 1851 if (i == count) { 1852 assert((count < 3) && "Too much destinations to test!"); 1853 CasesBits.push_back(CaseBits(0, Dest, 0)); 1854 count++; 1855 } 1856 1857 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1858 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1859 1860 for (uint64_t j = lo; j <= hi; j++) { 1861 CasesBits[i].Mask |= 1ULL << j; 1862 CasesBits[i].Bits++; 1863 } 1864 1865 } 1866 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1867 1868 SelectionDAGISel::BitTestInfo BTC; 1869 1870 // Figure out which block is immediately after the current one. 1871 MachineFunction::iterator BBI = CR.CaseBB; 1872 ++BBI; 1873 1874 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1875 1876 DOUT << "Cases:\n"; 1877 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1878 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1879 << ", BB: " << CasesBits[i].BB << "\n"; 1880 1881 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1882 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1883 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1884 CaseBB, 1885 CasesBits[i].BB)); 1886 } 1887 1888 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1889 -1U, (CR.CaseBB == CurMBB), 1890 CR.CaseBB, Default, BTC); 1891 1892 if (CR.CaseBB == CurMBB) 1893 visitBitTestHeader(BTB); 1894 1895 BitTestCases.push_back(BTB); 1896 1897 return true; 1898} 1899 1900 1901// Clusterify - Transform simple list of Cases into list of CaseRange's 1902unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1903 const SwitchInst& SI) { 1904 unsigned numCmps = 0; 1905 1906 // Start with "simple" cases 1907 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1908 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1909 Cases.push_back(Case(SI.getSuccessorValue(i), 1910 SI.getSuccessorValue(i), 1911 SMBB)); 1912 } 1913 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1914 1915 // Merge case into clusters 1916 if (Cases.size()>=2) 1917 // Must recompute end() each iteration because it may be 1918 // invalidated by erase if we hold on to it 1919 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1920 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1921 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1922 MachineBasicBlock* nextBB = J->BB; 1923 MachineBasicBlock* currentBB = I->BB; 1924 1925 // If the two neighboring cases go to the same destination, merge them 1926 // into a single case. 1927 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1928 I->High = J->High; 1929 J = Cases.erase(J); 1930 } else { 1931 I = J++; 1932 } 1933 } 1934 1935 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1936 if (I->Low != I->High) 1937 // A range counts double, since it requires two compares. 1938 ++numCmps; 1939 } 1940 1941 return numCmps; 1942} 1943 1944void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1945 // Figure out which block is immediately after the current one. 1946 MachineBasicBlock *NextBlock = 0; 1947 MachineFunction::iterator BBI = CurMBB; 1948 1949 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1950 1951 // If there is only the default destination, branch to it if it is not the 1952 // next basic block. Otherwise, just fall through. 1953 if (SI.getNumOperands() == 2) { 1954 // Update machine-CFG edges. 1955 1956 // If this is not a fall-through branch, emit the branch. 1957 if (Default != NextBlock) 1958 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1959 DAG.getBasicBlock(Default))); 1960 1961 CurMBB->addSuccessor(Default); 1962 return; 1963 } 1964 1965 // If there are any non-default case statements, create a vector of Cases 1966 // representing each one, and sort the vector so that we can efficiently 1967 // create a binary search tree from them. 1968 CaseVector Cases; 1969 unsigned numCmps = Clusterify(Cases, SI); 1970 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1971 << ". Total compares: " << numCmps << "\n"; 1972 1973 // Get the Value to be switched on and default basic blocks, which will be 1974 // inserted into CaseBlock records, representing basic blocks in the binary 1975 // search tree. 1976 Value *SV = SI.getOperand(0); 1977 1978 // Push the initial CaseRec onto the worklist 1979 CaseRecVector WorkList; 1980 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1981 1982 while (!WorkList.empty()) { 1983 // Grab a record representing a case range to process off the worklist 1984 CaseRec CR = WorkList.back(); 1985 WorkList.pop_back(); 1986 1987 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1988 continue; 1989 1990 // If the range has few cases (two or less) emit a series of specific 1991 // tests. 1992 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1993 continue; 1994 1995 // If the switch has more than 5 blocks, and at least 40% dense, and the 1996 // target supports indirect branches, then emit a jump table rather than 1997 // lowering the switch to a binary tree of conditional branches. 1998 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1999 continue; 2000 2001 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2002 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2003 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2004 } 2005} 2006 2007 2008void SelectionDAGLowering::visitSub(User &I) { 2009 // -0.0 - X --> fneg 2010 const Type *Ty = I.getType(); 2011 if (isa<VectorType>(Ty)) { 2012 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2013 const VectorType *DestTy = cast<VectorType>(I.getType()); 2014 const Type *ElTy = DestTy->getElementType(); 2015 if (ElTy->isFloatingPoint()) { 2016 unsigned VL = DestTy->getNumElements(); 2017 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2018 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2019 if (CV == CNZ) { 2020 SDOperand Op2 = getValue(I.getOperand(1)); 2021 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2022 return; 2023 } 2024 } 2025 } 2026 } 2027 if (Ty->isFloatingPoint()) { 2028 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2029 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2030 SDOperand Op2 = getValue(I.getOperand(1)); 2031 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2032 return; 2033 } 2034 } 2035 2036 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2037} 2038 2039void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2040 SDOperand Op1 = getValue(I.getOperand(0)); 2041 SDOperand Op2 = getValue(I.getOperand(1)); 2042 2043 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2044} 2045 2046void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2047 SDOperand Op1 = getValue(I.getOperand(0)); 2048 SDOperand Op2 = getValue(I.getOperand(1)); 2049 2050 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2051 MVT::getSizeInBits(Op2.getValueType())) 2052 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2053 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2054 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2055 2056 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2057} 2058 2059void SelectionDAGLowering::visitICmp(User &I) { 2060 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2061 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2062 predicate = IC->getPredicate(); 2063 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2064 predicate = ICmpInst::Predicate(IC->getPredicate()); 2065 SDOperand Op1 = getValue(I.getOperand(0)); 2066 SDOperand Op2 = getValue(I.getOperand(1)); 2067 ISD::CondCode Opcode; 2068 switch (predicate) { 2069 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2070 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2071 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2072 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2073 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2074 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2075 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2076 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2077 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2078 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2079 default: 2080 assert(!"Invalid ICmp predicate value"); 2081 Opcode = ISD::SETEQ; 2082 break; 2083 } 2084 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2085} 2086 2087void SelectionDAGLowering::visitFCmp(User &I) { 2088 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2089 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2090 predicate = FC->getPredicate(); 2091 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2092 predicate = FCmpInst::Predicate(FC->getPredicate()); 2093 SDOperand Op1 = getValue(I.getOperand(0)); 2094 SDOperand Op2 = getValue(I.getOperand(1)); 2095 ISD::CondCode Condition, FOC, FPC; 2096 switch (predicate) { 2097 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2098 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2099 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2100 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2101 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2102 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2103 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2104 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2105 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2106 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2107 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2108 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2109 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2110 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2111 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2112 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2113 default: 2114 assert(!"Invalid FCmp predicate value"); 2115 FOC = FPC = ISD::SETFALSE; 2116 break; 2117 } 2118 if (FiniteOnlyFPMath()) 2119 Condition = FOC; 2120 else 2121 Condition = FPC; 2122 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2123} 2124 2125void SelectionDAGLowering::visitSelect(User &I) { 2126 SDOperand Cond = getValue(I.getOperand(0)); 2127 SDOperand TrueVal = getValue(I.getOperand(1)); 2128 SDOperand FalseVal = getValue(I.getOperand(2)); 2129 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2130 TrueVal, FalseVal)); 2131} 2132 2133 2134void SelectionDAGLowering::visitTrunc(User &I) { 2135 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2136 SDOperand N = getValue(I.getOperand(0)); 2137 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2138 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2139} 2140 2141void SelectionDAGLowering::visitZExt(User &I) { 2142 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2143 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2144 SDOperand N = getValue(I.getOperand(0)); 2145 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2146 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2147} 2148 2149void SelectionDAGLowering::visitSExt(User &I) { 2150 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2151 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2152 SDOperand N = getValue(I.getOperand(0)); 2153 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2154 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2155} 2156 2157void SelectionDAGLowering::visitFPTrunc(User &I) { 2158 // FPTrunc is never a no-op cast, no need to check 2159 SDOperand N = getValue(I.getOperand(0)); 2160 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2161 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2162} 2163 2164void SelectionDAGLowering::visitFPExt(User &I){ 2165 // FPTrunc is never a no-op cast, no need to check 2166 SDOperand N = getValue(I.getOperand(0)); 2167 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2168 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2169} 2170 2171void SelectionDAGLowering::visitFPToUI(User &I) { 2172 // FPToUI is never a no-op cast, no need to check 2173 SDOperand N = getValue(I.getOperand(0)); 2174 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2175 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2176} 2177 2178void SelectionDAGLowering::visitFPToSI(User &I) { 2179 // FPToSI is never a no-op cast, no need to check 2180 SDOperand N = getValue(I.getOperand(0)); 2181 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2182 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2183} 2184 2185void SelectionDAGLowering::visitUIToFP(User &I) { 2186 // UIToFP is never a no-op cast, no need to check 2187 SDOperand N = getValue(I.getOperand(0)); 2188 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2189 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2190} 2191 2192void SelectionDAGLowering::visitSIToFP(User &I){ 2193 // UIToFP is never a no-op cast, no need to check 2194 SDOperand N = getValue(I.getOperand(0)); 2195 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2196 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2197} 2198 2199void SelectionDAGLowering::visitPtrToInt(User &I) { 2200 // What to do depends on the size of the integer and the size of the pointer. 2201 // We can either truncate, zero extend, or no-op, accordingly. 2202 SDOperand N = getValue(I.getOperand(0)); 2203 MVT::ValueType SrcVT = N.getValueType(); 2204 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2205 SDOperand Result; 2206 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2207 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2208 else 2209 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2210 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2211 setValue(&I, Result); 2212} 2213 2214void SelectionDAGLowering::visitIntToPtr(User &I) { 2215 // What to do depends on the size of the integer and the size of the pointer. 2216 // We can either truncate, zero extend, or no-op, accordingly. 2217 SDOperand N = getValue(I.getOperand(0)); 2218 MVT::ValueType SrcVT = N.getValueType(); 2219 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2220 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2221 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2222 else 2223 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2224 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2225} 2226 2227void SelectionDAGLowering::visitBitCast(User &I) { 2228 SDOperand N = getValue(I.getOperand(0)); 2229 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2230 2231 // BitCast assures us that source and destination are the same size so this 2232 // is either a BIT_CONVERT or a no-op. 2233 if (DestVT != N.getValueType()) 2234 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2235 else 2236 setValue(&I, N); // noop cast. 2237} 2238 2239void SelectionDAGLowering::visitInsertElement(User &I) { 2240 SDOperand InVec = getValue(I.getOperand(0)); 2241 SDOperand InVal = getValue(I.getOperand(1)); 2242 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2243 getValue(I.getOperand(2))); 2244 2245 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2246 TLI.getValueType(I.getType()), 2247 InVec, InVal, InIdx)); 2248} 2249 2250void SelectionDAGLowering::visitExtractElement(User &I) { 2251 SDOperand InVec = getValue(I.getOperand(0)); 2252 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2253 getValue(I.getOperand(1))); 2254 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2255 TLI.getValueType(I.getType()), InVec, InIdx)); 2256} 2257 2258void SelectionDAGLowering::visitShuffleVector(User &I) { 2259 SDOperand V1 = getValue(I.getOperand(0)); 2260 SDOperand V2 = getValue(I.getOperand(1)); 2261 SDOperand Mask = getValue(I.getOperand(2)); 2262 2263 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2264 TLI.getValueType(I.getType()), 2265 V1, V2, Mask)); 2266} 2267 2268 2269void SelectionDAGLowering::visitGetElementPtr(User &I) { 2270 SDOperand N = getValue(I.getOperand(0)); 2271 const Type *Ty = I.getOperand(0)->getType(); 2272 2273 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2274 OI != E; ++OI) { 2275 Value *Idx = *OI; 2276 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2277 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2278 if (Field) { 2279 // N = N + Offset 2280 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2281 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2282 getIntPtrConstant(Offset)); 2283 } 2284 Ty = StTy->getElementType(Field); 2285 } else { 2286 Ty = cast<SequentialType>(Ty)->getElementType(); 2287 2288 // If this is a constant subscript, handle it quickly. 2289 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2290 if (CI->getZExtValue() == 0) continue; 2291 uint64_t Offs = 2292 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2293 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2294 continue; 2295 } 2296 2297 // N = N + Idx * ElementSize; 2298 uint64_t ElementSize = TD->getABITypeSize(Ty); 2299 SDOperand IdxN = getValue(Idx); 2300 2301 // If the index is smaller or larger than intptr_t, truncate or extend 2302 // it. 2303 if (IdxN.getValueType() < N.getValueType()) { 2304 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2305 } else if (IdxN.getValueType() > N.getValueType()) 2306 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2307 2308 // If this is a multiply by a power of two, turn it into a shl 2309 // immediately. This is a very common case. 2310 if (isPowerOf2_64(ElementSize)) { 2311 unsigned Amt = Log2_64(ElementSize); 2312 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2313 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2314 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2315 continue; 2316 } 2317 2318 SDOperand Scale = getIntPtrConstant(ElementSize); 2319 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2320 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2321 } 2322 } 2323 setValue(&I, N); 2324} 2325 2326void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2327 // If this is a fixed sized alloca in the entry block of the function, 2328 // allocate it statically on the stack. 2329 if (FuncInfo.StaticAllocaMap.count(&I)) 2330 return; // getValue will auto-populate this. 2331 2332 const Type *Ty = I.getAllocatedType(); 2333 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2334 unsigned Align = 2335 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2336 I.getAlignment()); 2337 2338 SDOperand AllocSize = getValue(I.getArraySize()); 2339 MVT::ValueType IntPtr = TLI.getPointerTy(); 2340 if (IntPtr < AllocSize.getValueType()) 2341 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2342 else if (IntPtr > AllocSize.getValueType()) 2343 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2344 2345 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2346 getIntPtrConstant(TySize)); 2347 2348 // Handle alignment. If the requested alignment is less than or equal to 2349 // the stack alignment, ignore it. If the size is greater than or equal to 2350 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2351 unsigned StackAlign = 2352 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2353 if (Align <= StackAlign) 2354 Align = 0; 2355 2356 // Round the size of the allocation up to the stack alignment size 2357 // by add SA-1 to the size. 2358 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2359 getIntPtrConstant(StackAlign-1)); 2360 // Mask out the low bits for alignment purposes. 2361 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2362 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2363 2364 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2365 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2366 MVT::Other); 2367 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2368 setValue(&I, DSA); 2369 DAG.setRoot(DSA.getValue(1)); 2370 2371 // Inform the Frame Information that we have just allocated a variable-sized 2372 // object. 2373 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2374} 2375 2376void SelectionDAGLowering::visitLoad(LoadInst &I) { 2377 SDOperand Ptr = getValue(I.getOperand(0)); 2378 2379 SDOperand Root; 2380 if (I.isVolatile()) 2381 Root = getRoot(); 2382 else { 2383 // Do not serialize non-volatile loads against each other. 2384 Root = DAG.getRoot(); 2385 } 2386 2387 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2388 Root, I.isVolatile(), I.getAlignment())); 2389} 2390 2391SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2392 const Value *SV, SDOperand Root, 2393 bool isVolatile, 2394 unsigned Alignment) { 2395 SDOperand L = 2396 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2397 isVolatile, Alignment); 2398 2399 if (isVolatile) 2400 DAG.setRoot(L.getValue(1)); 2401 else 2402 PendingLoads.push_back(L.getValue(1)); 2403 2404 return L; 2405} 2406 2407 2408void SelectionDAGLowering::visitStore(StoreInst &I) { 2409 Value *SrcV = I.getOperand(0); 2410 SDOperand Src = getValue(SrcV); 2411 SDOperand Ptr = getValue(I.getOperand(1)); 2412 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2413 I.isVolatile(), I.getAlignment())); 2414} 2415 2416/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2417/// node. 2418void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2419 unsigned Intrinsic) { 2420 bool HasChain = !I.doesNotAccessMemory(); 2421 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2422 2423 // Build the operand list. 2424 SmallVector<SDOperand, 8> Ops; 2425 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2426 if (OnlyLoad) { 2427 // We don't need to serialize loads against other loads. 2428 Ops.push_back(DAG.getRoot()); 2429 } else { 2430 Ops.push_back(getRoot()); 2431 } 2432 } 2433 2434 // Add the intrinsic ID as an integer operand. 2435 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2436 2437 // Add all operands of the call to the operand list. 2438 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2439 SDOperand Op = getValue(I.getOperand(i)); 2440 assert(TLI.isTypeLegal(Op.getValueType()) && 2441 "Intrinsic uses a non-legal type?"); 2442 Ops.push_back(Op); 2443 } 2444 2445 std::vector<MVT::ValueType> VTs; 2446 if (I.getType() != Type::VoidTy) { 2447 MVT::ValueType VT = TLI.getValueType(I.getType()); 2448 if (MVT::isVector(VT)) { 2449 const VectorType *DestTy = cast<VectorType>(I.getType()); 2450 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2451 2452 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2453 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2454 } 2455 2456 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2457 VTs.push_back(VT); 2458 } 2459 if (HasChain) 2460 VTs.push_back(MVT::Other); 2461 2462 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2463 2464 // Create the node. 2465 SDOperand Result; 2466 if (!HasChain) 2467 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2468 &Ops[0], Ops.size()); 2469 else if (I.getType() != Type::VoidTy) 2470 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2471 &Ops[0], Ops.size()); 2472 else 2473 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2474 &Ops[0], Ops.size()); 2475 2476 if (HasChain) { 2477 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2478 if (OnlyLoad) 2479 PendingLoads.push_back(Chain); 2480 else 2481 DAG.setRoot(Chain); 2482 } 2483 if (I.getType() != Type::VoidTy) { 2484 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2485 MVT::ValueType VT = TLI.getValueType(PTy); 2486 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2487 } 2488 setValue(&I, Result); 2489 } 2490} 2491 2492/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2493static GlobalVariable *ExtractTypeInfo (Value *V) { 2494 V = IntrinsicInst::StripPointerCasts(V); 2495 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2496 assert (GV || isa<ConstantPointerNull>(V) && 2497 "TypeInfo must be a global variable or NULL"); 2498 return GV; 2499} 2500 2501/// addCatchInfo - Extract the personality and type infos from an eh.selector 2502/// call, and add them to the specified machine basic block. 2503static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2504 MachineBasicBlock *MBB) { 2505 // Inform the MachineModuleInfo of the personality for this landing pad. 2506 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2507 assert(CE->getOpcode() == Instruction::BitCast && 2508 isa<Function>(CE->getOperand(0)) && 2509 "Personality should be a function"); 2510 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2511 2512 // Gather all the type infos for this landing pad and pass them along to 2513 // MachineModuleInfo. 2514 std::vector<GlobalVariable *> TyInfo; 2515 unsigned N = I.getNumOperands(); 2516 2517 for (unsigned i = N - 1; i > 2; --i) { 2518 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2519 unsigned FilterLength = CI->getZExtValue(); 2520 unsigned FirstCatch = i + FilterLength + !FilterLength; 2521 assert (FirstCatch <= N && "Invalid filter length"); 2522 2523 if (FirstCatch < N) { 2524 TyInfo.reserve(N - FirstCatch); 2525 for (unsigned j = FirstCatch; j < N; ++j) 2526 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2527 MMI->addCatchTypeInfo(MBB, TyInfo); 2528 TyInfo.clear(); 2529 } 2530 2531 if (!FilterLength) { 2532 // Cleanup. 2533 MMI->addCleanup(MBB); 2534 } else { 2535 // Filter. 2536 TyInfo.reserve(FilterLength - 1); 2537 for (unsigned j = i + 1; j < FirstCatch; ++j) 2538 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2539 MMI->addFilterTypeInfo(MBB, TyInfo); 2540 TyInfo.clear(); 2541 } 2542 2543 N = i; 2544 } 2545 } 2546 2547 if (N > 3) { 2548 TyInfo.reserve(N - 3); 2549 for (unsigned j = 3; j < N; ++j) 2550 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2551 MMI->addCatchTypeInfo(MBB, TyInfo); 2552 } 2553} 2554 2555/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2556/// we want to emit this as a call to a named external function, return the name 2557/// otherwise lower it and return null. 2558const char * 2559SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2560 switch (Intrinsic) { 2561 default: 2562 // By default, turn this into a target intrinsic node. 2563 visitTargetIntrinsic(I, Intrinsic); 2564 return 0; 2565 case Intrinsic::vastart: visitVAStart(I); return 0; 2566 case Intrinsic::vaend: visitVAEnd(I); return 0; 2567 case Intrinsic::vacopy: visitVACopy(I); return 0; 2568 case Intrinsic::returnaddress: 2569 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2570 getValue(I.getOperand(1)))); 2571 return 0; 2572 case Intrinsic::frameaddress: 2573 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2574 getValue(I.getOperand(1)))); 2575 return 0; 2576 case Intrinsic::setjmp: 2577 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2578 break; 2579 case Intrinsic::longjmp: 2580 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2581 break; 2582 case Intrinsic::memcpy_i32: 2583 case Intrinsic::memcpy_i64: 2584 visitMemIntrinsic(I, ISD::MEMCPY); 2585 return 0; 2586 case Intrinsic::memset_i32: 2587 case Intrinsic::memset_i64: 2588 visitMemIntrinsic(I, ISD::MEMSET); 2589 return 0; 2590 case Intrinsic::memmove_i32: 2591 case Intrinsic::memmove_i64: 2592 visitMemIntrinsic(I, ISD::MEMMOVE); 2593 return 0; 2594 2595 case Intrinsic::dbg_stoppoint: { 2596 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2597 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2598 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2599 SDOperand Ops[5]; 2600 2601 Ops[0] = getRoot(); 2602 Ops[1] = getValue(SPI.getLineValue()); 2603 Ops[2] = getValue(SPI.getColumnValue()); 2604 2605 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2606 assert(DD && "Not a debug information descriptor"); 2607 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2608 2609 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2610 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2611 2612 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2613 } 2614 2615 return 0; 2616 } 2617 case Intrinsic::dbg_region_start: { 2618 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2619 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2620 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2621 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2622 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2623 DAG.getConstant(LabelID, MVT::i32))); 2624 } 2625 2626 return 0; 2627 } 2628 case Intrinsic::dbg_region_end: { 2629 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2630 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2631 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2632 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2633 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2634 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2635 } 2636 2637 return 0; 2638 } 2639 case Intrinsic::dbg_func_start: { 2640 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2641 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2642 if (MMI && FSI.getSubprogram() && 2643 MMI->Verify(FSI.getSubprogram())) { 2644 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2645 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2646 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2647 } 2648 2649 return 0; 2650 } 2651 case Intrinsic::dbg_declare: { 2652 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2653 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2654 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2655 SDOperand AddressOp = getValue(DI.getAddress()); 2656 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2657 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2658 } 2659 2660 return 0; 2661 } 2662 2663 case Intrinsic::eh_exception: { 2664 if (ExceptionHandling) { 2665 if (!CurMBB->isLandingPad()) { 2666 // FIXME: Mark exception register as live in. Hack for PR1508. 2667 unsigned Reg = TLI.getExceptionAddressRegister(); 2668 if (Reg) CurMBB->addLiveIn(Reg); 2669 } 2670 // Insert the EXCEPTIONADDR instruction. 2671 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2672 SDOperand Ops[1]; 2673 Ops[0] = DAG.getRoot(); 2674 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2675 setValue(&I, Op); 2676 DAG.setRoot(Op.getValue(1)); 2677 } else { 2678 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2679 } 2680 return 0; 2681 } 2682 2683 case Intrinsic::eh_selector_i32: 2684 case Intrinsic::eh_selector_i64: { 2685 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2686 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2687 MVT::i32 : MVT::i64); 2688 2689 if (ExceptionHandling && MMI) { 2690 if (CurMBB->isLandingPad()) 2691 addCatchInfo(I, MMI, CurMBB); 2692 else { 2693#ifndef NDEBUG 2694 FuncInfo.CatchInfoLost.insert(&I); 2695#endif 2696 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2697 unsigned Reg = TLI.getExceptionSelectorRegister(); 2698 if (Reg) CurMBB->addLiveIn(Reg); 2699 } 2700 2701 // Insert the EHSELECTION instruction. 2702 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2703 SDOperand Ops[2]; 2704 Ops[0] = getValue(I.getOperand(1)); 2705 Ops[1] = getRoot(); 2706 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2707 setValue(&I, Op); 2708 DAG.setRoot(Op.getValue(1)); 2709 } else { 2710 setValue(&I, DAG.getConstant(0, VT)); 2711 } 2712 2713 return 0; 2714 } 2715 2716 case Intrinsic::eh_typeid_for_i32: 2717 case Intrinsic::eh_typeid_for_i64: { 2718 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2719 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2720 MVT::i32 : MVT::i64); 2721 2722 if (MMI) { 2723 // Find the type id for the given typeinfo. 2724 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2725 2726 unsigned TypeID = MMI->getTypeIDFor(GV); 2727 setValue(&I, DAG.getConstant(TypeID, VT)); 2728 } else { 2729 // Return something different to eh_selector. 2730 setValue(&I, DAG.getConstant(1, VT)); 2731 } 2732 2733 return 0; 2734 } 2735 2736 case Intrinsic::eh_return: { 2737 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2738 2739 if (MMI && ExceptionHandling) { 2740 MMI->setCallsEHReturn(true); 2741 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2742 MVT::Other, 2743 getRoot(), 2744 getValue(I.getOperand(1)), 2745 getValue(I.getOperand(2)))); 2746 } else { 2747 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2748 } 2749 2750 return 0; 2751 } 2752 2753 case Intrinsic::eh_unwind_init: { 2754 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2755 MMI->setCallsUnwindInit(true); 2756 } 2757 2758 return 0; 2759 } 2760 2761 case Intrinsic::eh_dwarf_cfa: { 2762 if (ExceptionHandling) { 2763 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2764 SDOperand CfaArg; 2765 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2766 CfaArg = DAG.getNode(ISD::TRUNCATE, 2767 TLI.getPointerTy(), getValue(I.getOperand(1))); 2768 else 2769 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2770 TLI.getPointerTy(), getValue(I.getOperand(1))); 2771 2772 SDOperand Offset = DAG.getNode(ISD::ADD, 2773 TLI.getPointerTy(), 2774 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2775 TLI.getPointerTy()), 2776 CfaArg); 2777 setValue(&I, DAG.getNode(ISD::ADD, 2778 TLI.getPointerTy(), 2779 DAG.getNode(ISD::FRAMEADDR, 2780 TLI.getPointerTy(), 2781 DAG.getConstant(0, 2782 TLI.getPointerTy())), 2783 Offset)); 2784 } else { 2785 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2786 } 2787 2788 return 0; 2789 } 2790 2791 case Intrinsic::sqrt: 2792 setValue(&I, DAG.getNode(ISD::FSQRT, 2793 getValue(I.getOperand(1)).getValueType(), 2794 getValue(I.getOperand(1)))); 2795 return 0; 2796 case Intrinsic::powi: 2797 setValue(&I, DAG.getNode(ISD::FPOWI, 2798 getValue(I.getOperand(1)).getValueType(), 2799 getValue(I.getOperand(1)), 2800 getValue(I.getOperand(2)))); 2801 return 0; 2802 case Intrinsic::sin: 2803 setValue(&I, DAG.getNode(ISD::FSIN, 2804 getValue(I.getOperand(1)).getValueType(), 2805 getValue(I.getOperand(1)))); 2806 return 0; 2807 case Intrinsic::cos: 2808 setValue(&I, DAG.getNode(ISD::FCOS, 2809 getValue(I.getOperand(1)).getValueType(), 2810 getValue(I.getOperand(1)))); 2811 return 0; 2812 case Intrinsic::pow: 2813 setValue(&I, DAG.getNode(ISD::FPOW, 2814 getValue(I.getOperand(1)).getValueType(), 2815 getValue(I.getOperand(1)), 2816 getValue(I.getOperand(2)))); 2817 return 0; 2818 case Intrinsic::pcmarker: { 2819 SDOperand Tmp = getValue(I.getOperand(1)); 2820 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2821 return 0; 2822 } 2823 case Intrinsic::readcyclecounter: { 2824 SDOperand Op = getRoot(); 2825 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2826 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2827 &Op, 1); 2828 setValue(&I, Tmp); 2829 DAG.setRoot(Tmp.getValue(1)); 2830 return 0; 2831 } 2832 case Intrinsic::part_select: { 2833 // Currently not implemented: just abort 2834 assert(0 && "part_select intrinsic not implemented"); 2835 abort(); 2836 } 2837 case Intrinsic::part_set: { 2838 // Currently not implemented: just abort 2839 assert(0 && "part_set intrinsic not implemented"); 2840 abort(); 2841 } 2842 case Intrinsic::bswap: 2843 setValue(&I, DAG.getNode(ISD::BSWAP, 2844 getValue(I.getOperand(1)).getValueType(), 2845 getValue(I.getOperand(1)))); 2846 return 0; 2847 case Intrinsic::cttz: { 2848 SDOperand Arg = getValue(I.getOperand(1)); 2849 MVT::ValueType Ty = Arg.getValueType(); 2850 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2851 setValue(&I, result); 2852 return 0; 2853 } 2854 case Intrinsic::ctlz: { 2855 SDOperand Arg = getValue(I.getOperand(1)); 2856 MVT::ValueType Ty = Arg.getValueType(); 2857 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2858 setValue(&I, result); 2859 return 0; 2860 } 2861 case Intrinsic::ctpop: { 2862 SDOperand Arg = getValue(I.getOperand(1)); 2863 MVT::ValueType Ty = Arg.getValueType(); 2864 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2865 setValue(&I, result); 2866 return 0; 2867 } 2868 case Intrinsic::stacksave: { 2869 SDOperand Op = getRoot(); 2870 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2871 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2872 setValue(&I, Tmp); 2873 DAG.setRoot(Tmp.getValue(1)); 2874 return 0; 2875 } 2876 case Intrinsic::stackrestore: { 2877 SDOperand Tmp = getValue(I.getOperand(1)); 2878 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2879 return 0; 2880 } 2881 case Intrinsic::prefetch: 2882 // FIXME: Currently discarding prefetches. 2883 return 0; 2884 2885 case Intrinsic::var_annotation: 2886 // Discard annotate attributes 2887 return 0; 2888 2889 case Intrinsic::init_trampoline: { 2890 const Function *F = 2891 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 2892 2893 SDOperand Ops[6]; 2894 Ops[0] = getRoot(); 2895 Ops[1] = getValue(I.getOperand(1)); 2896 Ops[2] = getValue(I.getOperand(2)); 2897 Ops[3] = getValue(I.getOperand(3)); 2898 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 2899 Ops[5] = DAG.getSrcValue(F); 2900 2901 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 2902 DAG.getNodeValueTypes(TLI.getPointerTy(), 2903 MVT::Other), 2, 2904 Ops, 6); 2905 2906 setValue(&I, Tmp); 2907 DAG.setRoot(Tmp.getValue(1)); 2908 return 0; 2909 } 2910 case Intrinsic::flt_rounds: { 2911 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32)); 2912 return 0; 2913 } 2914 } 2915} 2916 2917 2918void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, 2919 bool IsTailCall, 2920 MachineBasicBlock *LandingPad) { 2921 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 2922 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2923 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2924 unsigned BeginLabel = 0, EndLabel = 0; 2925 2926 TargetLowering::ArgListTy Args; 2927 TargetLowering::ArgListEntry Entry; 2928 Args.reserve(CS.arg_size()); 2929 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 2930 i != e; ++i) { 2931 SDOperand ArgNode = getValue(*i); 2932 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 2933 2934 unsigned attrInd = i - CS.arg_begin() + 1; 2935 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 2936 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 2937 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 2938 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 2939 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 2940 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 2941 Args.push_back(Entry); 2942 } 2943 2944 bool MarkTryRange = LandingPad || 2945 // C++ requires special handling of 'nounwind' calls. 2946 (CS.doesNotThrow()); 2947 2948 if (MarkTryRange && ExceptionHandling && MMI) { 2949 // Insert a label before the invoke call to mark the try range. This can be 2950 // used to detect deletion of the invoke via the MachineModuleInfo. 2951 BeginLabel = MMI->NextLabelID(); 2952 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2953 DAG.getConstant(BeginLabel, MVT::i32))); 2954 } 2955 2956 std::pair<SDOperand,SDOperand> Result = 2957 TLI.LowerCallTo(getRoot(), CS.getType(), 2958 CS.paramHasAttr(0, ParamAttr::SExt), 2959 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 2960 Callee, Args, DAG); 2961 if (CS.getType() != Type::VoidTy) 2962 setValue(CS.getInstruction(), Result.first); 2963 DAG.setRoot(Result.second); 2964 2965 if (MarkTryRange && ExceptionHandling && MMI) { 2966 // Insert a label at the end of the invoke call to mark the try range. This 2967 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2968 EndLabel = MMI->NextLabelID(); 2969 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2970 DAG.getConstant(EndLabel, MVT::i32))); 2971 2972 // Inform MachineModuleInfo of range. 2973 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2974 } 2975} 2976 2977 2978void SelectionDAGLowering::visitCall(CallInst &I) { 2979 const char *RenameFn = 0; 2980 if (Function *F = I.getCalledFunction()) { 2981 if (F->isDeclaration()) { 2982 if (unsigned IID = F->getIntrinsicID()) { 2983 RenameFn = visitIntrinsicCall(I, IID); 2984 if (!RenameFn) 2985 return; 2986 } 2987 } 2988 2989 // Check for well-known libc/libm calls. If the function is internal, it 2990 // can't be a library call. 2991 unsigned NameLen = F->getNameLen(); 2992 if (!F->hasInternalLinkage() && NameLen) { 2993 const char *NameStr = F->getNameStart(); 2994 if (NameStr[0] == 'c' && 2995 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 2996 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 2997 if (I.getNumOperands() == 3 && // Basic sanity checks. 2998 I.getOperand(1)->getType()->isFloatingPoint() && 2999 I.getType() == I.getOperand(1)->getType() && 3000 I.getType() == I.getOperand(2)->getType()) { 3001 SDOperand LHS = getValue(I.getOperand(1)); 3002 SDOperand RHS = getValue(I.getOperand(2)); 3003 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3004 LHS, RHS)); 3005 return; 3006 } 3007 } else if (NameStr[0] == 'f' && 3008 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3009 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3010 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3011 if (I.getNumOperands() == 2 && // Basic sanity checks. 3012 I.getOperand(1)->getType()->isFloatingPoint() && 3013 I.getType() == I.getOperand(1)->getType()) { 3014 SDOperand Tmp = getValue(I.getOperand(1)); 3015 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3016 return; 3017 } 3018 } else if (NameStr[0] == 's' && 3019 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3020 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3021 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3022 if (I.getNumOperands() == 2 && // Basic sanity checks. 3023 I.getOperand(1)->getType()->isFloatingPoint() && 3024 I.getType() == I.getOperand(1)->getType()) { 3025 SDOperand Tmp = getValue(I.getOperand(1)); 3026 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3027 return; 3028 } 3029 } else if (NameStr[0] == 'c' && 3030 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3031 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3032 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3033 if (I.getNumOperands() == 2 && // Basic sanity checks. 3034 I.getOperand(1)->getType()->isFloatingPoint() && 3035 I.getType() == I.getOperand(1)->getType()) { 3036 SDOperand Tmp = getValue(I.getOperand(1)); 3037 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3038 return; 3039 } 3040 } 3041 } 3042 } else if (isa<InlineAsm>(I.getOperand(0))) { 3043 visitInlineAsm(&I); 3044 return; 3045 } 3046 3047 SDOperand Callee; 3048 if (!RenameFn) 3049 Callee = getValue(I.getOperand(0)); 3050 else 3051 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3052 3053 LowerCallTo(&I, Callee, I.isTailCall()); 3054} 3055 3056 3057/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3058/// this value and returns the result as a ValueVT value. This uses 3059/// Chain/Flag as the input and updates them for the output Chain/Flag. 3060/// If the Flag pointer is NULL, no flag is used. 3061SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3062 SDOperand &Chain, SDOperand *Flag)const{ 3063 // Copy the legal parts from the registers. 3064 unsigned NumParts = Regs.size(); 3065 SmallVector<SDOperand, 8> Parts(NumParts); 3066 for (unsigned i = 0; i != NumParts; ++i) { 3067 SDOperand Part = Flag ? 3068 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3069 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3070 Chain = Part.getValue(1); 3071 if (Flag) 3072 *Flag = Part.getValue(2); 3073 Parts[i] = Part; 3074 } 3075 3076 // Assemble the legal parts into the final value. 3077 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3078} 3079 3080/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3081/// specified value into the registers specified by this object. This uses 3082/// Chain/Flag as the input and updates them for the output Chain/Flag. 3083/// If the Flag pointer is NULL, no flag is used. 3084void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3085 SDOperand &Chain, SDOperand *Flag) const { 3086 // Get the list of the values's legal parts. 3087 unsigned NumParts = Regs.size(); 3088 SmallVector<SDOperand, 8> Parts(NumParts); 3089 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3090 3091 // Copy the parts into the registers. 3092 for (unsigned i = 0; i != NumParts; ++i) { 3093 SDOperand Part = Flag ? 3094 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3095 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3096 Chain = Part.getValue(0); 3097 if (Flag) 3098 *Flag = Part.getValue(1); 3099 } 3100} 3101 3102/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3103/// operand list. This adds the code marker and includes the number of 3104/// values added into it. 3105void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3106 std::vector<SDOperand> &Ops) const { 3107 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3108 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3109 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3110 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3111} 3112 3113/// isAllocatableRegister - If the specified register is safe to allocate, 3114/// i.e. it isn't a stack pointer or some other special register, return the 3115/// register class for the register. Otherwise, return null. 3116static const TargetRegisterClass * 3117isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3118 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3119 MVT::ValueType FoundVT = MVT::Other; 3120 const TargetRegisterClass *FoundRC = 0; 3121 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3122 E = MRI->regclass_end(); RCI != E; ++RCI) { 3123 MVT::ValueType ThisVT = MVT::Other; 3124 3125 const TargetRegisterClass *RC = *RCI; 3126 // If none of the the value types for this register class are valid, we 3127 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3128 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3129 I != E; ++I) { 3130 if (TLI.isTypeLegal(*I)) { 3131 // If we have already found this register in a different register class, 3132 // choose the one with the largest VT specified. For example, on 3133 // PowerPC, we favor f64 register classes over f32. 3134 if (FoundVT == MVT::Other || 3135 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3136 ThisVT = *I; 3137 break; 3138 } 3139 } 3140 } 3141 3142 if (ThisVT == MVT::Other) continue; 3143 3144 // NOTE: This isn't ideal. In particular, this might allocate the 3145 // frame pointer in functions that need it (due to them not being taken 3146 // out of allocation, because a variable sized allocation hasn't been seen 3147 // yet). This is a slight code pessimization, but should still work. 3148 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3149 E = RC->allocation_order_end(MF); I != E; ++I) 3150 if (*I == Reg) { 3151 // We found a matching register class. Keep looking at others in case 3152 // we find one with larger registers that this physreg is also in. 3153 FoundRC = RC; 3154 FoundVT = ThisVT; 3155 break; 3156 } 3157 } 3158 return FoundRC; 3159} 3160 3161 3162namespace { 3163/// AsmOperandInfo - This contains information for each constraint that we are 3164/// lowering. 3165struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3166 /// ConstraintCode - This contains the actual string for the code, like "m". 3167 std::string ConstraintCode; 3168 3169 /// ConstraintType - Information about the constraint code, e.g. Register, 3170 /// RegisterClass, Memory, Other, Unknown. 3171 TargetLowering::ConstraintType ConstraintType; 3172 3173 /// CallOperand/CallOperandval - If this is the result output operand or a 3174 /// clobber, this is null, otherwise it is the incoming operand to the 3175 /// CallInst. This gets modified as the asm is processed. 3176 SDOperand CallOperand; 3177 Value *CallOperandVal; 3178 3179 /// ConstraintVT - The ValueType for the operand value. 3180 MVT::ValueType ConstraintVT; 3181 3182 /// AssignedRegs - If this is a register or register class operand, this 3183 /// contains the set of register corresponding to the operand. 3184 RegsForValue AssignedRegs; 3185 3186 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3187 : InlineAsm::ConstraintInfo(info), 3188 ConstraintType(TargetLowering::C_Unknown), 3189 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3190 } 3191 3192 void ComputeConstraintToUse(const TargetLowering &TLI); 3193 3194 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3195 /// busy in OutputRegs/InputRegs. 3196 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3197 std::set<unsigned> &OutputRegs, 3198 std::set<unsigned> &InputRegs) const { 3199 if (isOutReg) 3200 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3201 if (isInReg) 3202 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3203 } 3204}; 3205} // end anon namespace. 3206 3207/// getConstraintGenerality - Return an integer indicating how general CT is. 3208static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3209 switch (CT) { 3210 default: assert(0 && "Unknown constraint type!"); 3211 case TargetLowering::C_Other: 3212 case TargetLowering::C_Unknown: 3213 return 0; 3214 case TargetLowering::C_Register: 3215 return 1; 3216 case TargetLowering::C_RegisterClass: 3217 return 2; 3218 case TargetLowering::C_Memory: 3219 return 3; 3220 } 3221} 3222 3223void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3224 assert(!Codes.empty() && "Must have at least one constraint"); 3225 3226 std::string *Current = &Codes[0]; 3227 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3228 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3229 ConstraintCode = *Current; 3230 ConstraintType = CurType; 3231 return; 3232 } 3233 3234 unsigned CurGenerality = getConstraintGenerality(CurType); 3235 3236 // If we have multiple constraints, try to pick the most general one ahead 3237 // of time. This isn't a wonderful solution, but handles common cases. 3238 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3239 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3240 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3241 if (ThisGenerality > CurGenerality) { 3242 // This constraint letter is more general than the previous one, 3243 // use it. 3244 CurType = ThisType; 3245 Current = &Codes[j]; 3246 CurGenerality = ThisGenerality; 3247 } 3248 } 3249 3250 ConstraintCode = *Current; 3251 ConstraintType = CurType; 3252} 3253 3254 3255void SelectionDAGLowering:: 3256GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3257 std::set<unsigned> &OutputRegs, 3258 std::set<unsigned> &InputRegs) { 3259 // Compute whether this value requires an input register, an output register, 3260 // or both. 3261 bool isOutReg = false; 3262 bool isInReg = false; 3263 switch (OpInfo.Type) { 3264 case InlineAsm::isOutput: 3265 isOutReg = true; 3266 3267 // If this is an early-clobber output, or if there is an input 3268 // constraint that matches this, we need to reserve the input register 3269 // so no other inputs allocate to it. 3270 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3271 break; 3272 case InlineAsm::isInput: 3273 isInReg = true; 3274 isOutReg = false; 3275 break; 3276 case InlineAsm::isClobber: 3277 isOutReg = true; 3278 isInReg = true; 3279 break; 3280 } 3281 3282 3283 MachineFunction &MF = DAG.getMachineFunction(); 3284 std::vector<unsigned> Regs; 3285 3286 // If this is a constraint for a single physreg, or a constraint for a 3287 // register class, find it. 3288 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3289 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3290 OpInfo.ConstraintVT); 3291 3292 unsigned NumRegs = 1; 3293 if (OpInfo.ConstraintVT != MVT::Other) 3294 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3295 MVT::ValueType RegVT; 3296 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3297 3298 3299 // If this is a constraint for a specific physical register, like {r17}, 3300 // assign it now. 3301 if (PhysReg.first) { 3302 if (OpInfo.ConstraintVT == MVT::Other) 3303 ValueVT = *PhysReg.second->vt_begin(); 3304 3305 // Get the actual register value type. This is important, because the user 3306 // may have asked for (e.g.) the AX register in i32 type. We need to 3307 // remember that AX is actually i16 to get the right extension. 3308 RegVT = *PhysReg.second->vt_begin(); 3309 3310 // This is a explicit reference to a physical register. 3311 Regs.push_back(PhysReg.first); 3312 3313 // If this is an expanded reference, add the rest of the regs to Regs. 3314 if (NumRegs != 1) { 3315 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3316 TargetRegisterClass::iterator E = PhysReg.second->end(); 3317 for (; *I != PhysReg.first; ++I) 3318 assert(I != E && "Didn't find reg!"); 3319 3320 // Already added the first reg. 3321 --NumRegs; ++I; 3322 for (; NumRegs; --NumRegs, ++I) { 3323 assert(I != E && "Ran out of registers to allocate!"); 3324 Regs.push_back(*I); 3325 } 3326 } 3327 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3328 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3329 return; 3330 } 3331 3332 // Otherwise, if this was a reference to an LLVM register class, create vregs 3333 // for this reference. 3334 std::vector<unsigned> RegClassRegs; 3335 const TargetRegisterClass *RC = PhysReg.second; 3336 if (RC) { 3337 // If this is an early clobber or tied register, our regalloc doesn't know 3338 // how to maintain the constraint. If it isn't, go ahead and create vreg 3339 // and let the regalloc do the right thing. 3340 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3341 // If there is some other early clobber and this is an input register, 3342 // then we are forced to pre-allocate the input reg so it doesn't 3343 // conflict with the earlyclobber. 3344 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3345 RegVT = *PhysReg.second->vt_begin(); 3346 3347 if (OpInfo.ConstraintVT == MVT::Other) 3348 ValueVT = RegVT; 3349 3350 // Create the appropriate number of virtual registers. 3351 SSARegMap *RegMap = MF.getSSARegMap(); 3352 for (; NumRegs; --NumRegs) 3353 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3354 3355 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3356 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3357 return; 3358 } 3359 3360 // Otherwise, we can't allocate it. Let the code below figure out how to 3361 // maintain these constraints. 3362 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3363 3364 } else { 3365 // This is a reference to a register class that doesn't directly correspond 3366 // to an LLVM register class. Allocate NumRegs consecutive, available, 3367 // registers from the class. 3368 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3369 OpInfo.ConstraintVT); 3370 } 3371 3372 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3373 unsigned NumAllocated = 0; 3374 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3375 unsigned Reg = RegClassRegs[i]; 3376 // See if this register is available. 3377 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3378 (isInReg && InputRegs.count(Reg))) { // Already used. 3379 // Make sure we find consecutive registers. 3380 NumAllocated = 0; 3381 continue; 3382 } 3383 3384 // Check to see if this register is allocatable (i.e. don't give out the 3385 // stack pointer). 3386 if (RC == 0) { 3387 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3388 if (!RC) { // Couldn't allocate this register. 3389 // Reset NumAllocated to make sure we return consecutive registers. 3390 NumAllocated = 0; 3391 continue; 3392 } 3393 } 3394 3395 // Okay, this register is good, we can use it. 3396 ++NumAllocated; 3397 3398 // If we allocated enough consecutive registers, succeed. 3399 if (NumAllocated == NumRegs) { 3400 unsigned RegStart = (i-NumAllocated)+1; 3401 unsigned RegEnd = i+1; 3402 // Mark all of the allocated registers used. 3403 for (unsigned i = RegStart; i != RegEnd; ++i) 3404 Regs.push_back(RegClassRegs[i]); 3405 3406 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3407 OpInfo.ConstraintVT); 3408 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3409 return; 3410 } 3411 } 3412 3413 // Otherwise, we couldn't allocate enough registers for this. 3414 return; 3415} 3416 3417 3418/// visitInlineAsm - Handle a call to an InlineAsm object. 3419/// 3420void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 3421 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3422 3423 /// ConstraintOperands - Information about all of the constraints. 3424 std::vector<AsmOperandInfo> ConstraintOperands; 3425 3426 SDOperand Chain = getRoot(); 3427 SDOperand Flag; 3428 3429 std::set<unsigned> OutputRegs, InputRegs; 3430 3431 // Do a prepass over the constraints, canonicalizing them, and building up the 3432 // ConstraintOperands list. 3433 std::vector<InlineAsm::ConstraintInfo> 3434 ConstraintInfos = IA->ParseConstraints(); 3435 3436 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3437 // constraint. If so, we can't let the register allocator allocate any input 3438 // registers, because it will not know to avoid the earlyclobbered output reg. 3439 bool SawEarlyClobber = false; 3440 3441 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3442 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3443 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3444 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3445 3446 MVT::ValueType OpVT = MVT::Other; 3447 3448 // Compute the value type for each operand. 3449 switch (OpInfo.Type) { 3450 case InlineAsm::isOutput: 3451 if (!OpInfo.isIndirect) { 3452 // The return value of the call is this value. As such, there is no 3453 // corresponding argument. 3454 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3455 OpVT = TLI.getValueType(CS.getType()); 3456 } else { 3457 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3458 } 3459 break; 3460 case InlineAsm::isInput: 3461 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3462 break; 3463 case InlineAsm::isClobber: 3464 // Nothing to do. 3465 break; 3466 } 3467 3468 // If this is an input or an indirect output, process the call argument. 3469 // BasicBlocks are labels, currently appearing only in asm's. 3470 if (OpInfo.CallOperandVal) { 3471 if (isa<BasicBlock>(OpInfo.CallOperandVal)) 3472 OpInfo.CallOperand = 3473 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]); 3474 else { 3475 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3476 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3477 // If this is an indirect operand, the operand is a pointer to the 3478 // accessed type. 3479 if (OpInfo.isIndirect) 3480 OpTy = cast<PointerType>(OpTy)->getElementType(); 3481 3482 // If OpTy is not a first-class value, it may be a struct/union that we 3483 // can tile with integers. 3484 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3485 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3486 switch (BitSize) { 3487 default: break; 3488 case 1: 3489 case 8: 3490 case 16: 3491 case 32: 3492 case 64: 3493 OpTy = IntegerType::get(BitSize); 3494 break; 3495 } 3496 } 3497 3498 OpVT = TLI.getValueType(OpTy, true); 3499 } 3500 } 3501 3502 OpInfo.ConstraintVT = OpVT; 3503 3504 // Compute the constraint code and ConstraintType to use. 3505 OpInfo.ComputeConstraintToUse(TLI); 3506 3507 // Keep track of whether we see an earlyclobber. 3508 SawEarlyClobber |= OpInfo.isEarlyClobber; 3509 3510 // If this is a memory input, and if the operand is not indirect, do what we 3511 // need to to provide an address for the memory input. 3512 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3513 !OpInfo.isIndirect) { 3514 assert(OpInfo.Type == InlineAsm::isInput && 3515 "Can only indirectify direct input operands!"); 3516 3517 // Memory operands really want the address of the value. If we don't have 3518 // an indirect input, put it in the constpool if we can, otherwise spill 3519 // it to a stack slot. 3520 3521 // If the operand is a float, integer, or vector constant, spill to a 3522 // constant pool entry to get its address. 3523 Value *OpVal = OpInfo.CallOperandVal; 3524 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3525 isa<ConstantVector>(OpVal)) { 3526 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3527 TLI.getPointerTy()); 3528 } else { 3529 // Otherwise, create a stack slot and emit a store to it before the 3530 // asm. 3531 const Type *Ty = OpVal->getType(); 3532 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3533 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3534 MachineFunction &MF = DAG.getMachineFunction(); 3535 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3536 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3537 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3538 OpInfo.CallOperand = StackSlot; 3539 } 3540 3541 // There is no longer a Value* corresponding to this operand. 3542 OpInfo.CallOperandVal = 0; 3543 // It is now an indirect operand. 3544 OpInfo.isIndirect = true; 3545 } 3546 3547 // If this constraint is for a specific register, allocate it before 3548 // anything else. 3549 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3550 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3551 } 3552 ConstraintInfos.clear(); 3553 3554 3555 // Second pass - Loop over all of the operands, assigning virtual or physregs 3556 // to registerclass operands. 3557 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3558 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3559 3560 // C_Register operands have already been allocated, Other/Memory don't need 3561 // to be. 3562 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3563 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3564 } 3565 3566 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3567 std::vector<SDOperand> AsmNodeOperands; 3568 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3569 AsmNodeOperands.push_back( 3570 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3571 3572 3573 // Loop over all of the inputs, copying the operand values into the 3574 // appropriate registers and processing the output regs. 3575 RegsForValue RetValRegs; 3576 3577 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3578 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3579 3580 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3581 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3582 3583 switch (OpInfo.Type) { 3584 case InlineAsm::isOutput: { 3585 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3586 OpInfo.ConstraintType != TargetLowering::C_Register) { 3587 // Memory output, or 'other' output (e.g. 'X' constraint). 3588 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3589 3590 // Add information to the INLINEASM node to know about this output. 3591 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3592 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3593 TLI.getPointerTy())); 3594 AsmNodeOperands.push_back(OpInfo.CallOperand); 3595 break; 3596 } 3597 3598 // Otherwise, this is a register or register class output. 3599 3600 // Copy the output from the appropriate register. Find a register that 3601 // we can use. 3602 if (OpInfo.AssignedRegs.Regs.empty()) { 3603 cerr << "Couldn't allocate output reg for contraint '" 3604 << OpInfo.ConstraintCode << "'!\n"; 3605 exit(1); 3606 } 3607 3608 if (!OpInfo.isIndirect) { 3609 // This is the result value of the call. 3610 assert(RetValRegs.Regs.empty() && 3611 "Cannot have multiple output constraints yet!"); 3612 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3613 RetValRegs = OpInfo.AssignedRegs; 3614 } else { 3615 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3616 OpInfo.CallOperandVal)); 3617 } 3618 3619 // Add information to the INLINEASM node to know that this register is 3620 // set. 3621 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3622 AsmNodeOperands); 3623 break; 3624 } 3625 case InlineAsm::isInput: { 3626 SDOperand InOperandVal = OpInfo.CallOperand; 3627 3628 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3629 // If this is required to match an output register we have already set, 3630 // just use its register. 3631 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3632 3633 // Scan until we find the definition we already emitted of this operand. 3634 // When we find it, create a RegsForValue operand. 3635 unsigned CurOp = 2; // The first operand. 3636 for (; OperandNo; --OperandNo) { 3637 // Advance to the next operand. 3638 unsigned NumOps = 3639 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3640 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3641 (NumOps & 7) == 4 /*MEM*/) && 3642 "Skipped past definitions?"); 3643 CurOp += (NumOps>>3)+1; 3644 } 3645 3646 unsigned NumOps = 3647 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3648 if ((NumOps & 7) == 2 /*REGDEF*/) { 3649 // Add NumOps>>3 registers to MatchedRegs. 3650 RegsForValue MatchedRegs; 3651 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3652 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3653 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3654 unsigned Reg = 3655 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3656 MatchedRegs.Regs.push_back(Reg); 3657 } 3658 3659 // Use the produced MatchedRegs object to 3660 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3661 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3662 break; 3663 } else { 3664 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3665 assert(0 && "matching constraints for memory operands unimp"); 3666 } 3667 } 3668 3669 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3670 assert(!OpInfo.isIndirect && 3671 "Don't know how to handle indirect other inputs yet!"); 3672 3673 std::vector<SDOperand> Ops; 3674 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3675 Ops, DAG); 3676 if (Ops.empty()) { 3677 cerr << "Invalid operand for inline asm constraint '" 3678 << OpInfo.ConstraintCode << "'!\n"; 3679 exit(1); 3680 } 3681 3682 // Add information to the INLINEASM node to know about this input. 3683 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3684 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3685 TLI.getPointerTy())); 3686 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3687 break; 3688 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3689 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3690 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3691 "Memory operands expect pointer values"); 3692 3693 // Add information to the INLINEASM node to know about this input. 3694 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3695 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3696 TLI.getPointerTy())); 3697 AsmNodeOperands.push_back(InOperandVal); 3698 break; 3699 } 3700 3701 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3702 OpInfo.ConstraintType == TargetLowering::C_Register) && 3703 "Unknown constraint type!"); 3704 assert(!OpInfo.isIndirect && 3705 "Don't know how to handle indirect register inputs yet!"); 3706 3707 // Copy the input into the appropriate registers. 3708 assert(!OpInfo.AssignedRegs.Regs.empty() && 3709 "Couldn't allocate input reg!"); 3710 3711 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3712 3713 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3714 AsmNodeOperands); 3715 break; 3716 } 3717 case InlineAsm::isClobber: { 3718 // Add the clobbered value to the operand list, so that the register 3719 // allocator is aware that the physreg got clobbered. 3720 if (!OpInfo.AssignedRegs.Regs.empty()) 3721 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3722 AsmNodeOperands); 3723 break; 3724 } 3725 } 3726 } 3727 3728 // Finish up input operands. 3729 AsmNodeOperands[0] = Chain; 3730 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3731 3732 Chain = DAG.getNode(ISD::INLINEASM, 3733 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3734 &AsmNodeOperands[0], AsmNodeOperands.size()); 3735 Flag = Chain.getValue(1); 3736 3737 // If this asm returns a register value, copy the result from that register 3738 // and set it as the value of the call. 3739 if (!RetValRegs.Regs.empty()) { 3740 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3741 3742 // If the result of the inline asm is a vector, it may have the wrong 3743 // width/num elts. Make sure to convert it to the right type with 3744 // bit_convert. 3745 if (MVT::isVector(Val.getValueType())) { 3746 const VectorType *VTy = cast<VectorType>(CS.getType()); 3747 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3748 3749 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3750 } 3751 3752 setValue(CS.getInstruction(), Val); 3753 } 3754 3755 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3756 3757 // Process indirect outputs, first output all of the flagged copies out of 3758 // physregs. 3759 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3760 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3761 Value *Ptr = IndirectStoresToEmit[i].second; 3762 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3763 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3764 } 3765 3766 // Emit the non-flagged stores from the physregs. 3767 SmallVector<SDOperand, 8> OutChains; 3768 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3769 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3770 getValue(StoresToEmit[i].second), 3771 StoresToEmit[i].second, 0)); 3772 if (!OutChains.empty()) 3773 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3774 &OutChains[0], OutChains.size()); 3775 DAG.setRoot(Chain); 3776} 3777 3778 3779void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3780 SDOperand Src = getValue(I.getOperand(0)); 3781 3782 MVT::ValueType IntPtr = TLI.getPointerTy(); 3783 3784 if (IntPtr < Src.getValueType()) 3785 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3786 else if (IntPtr > Src.getValueType()) 3787 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3788 3789 // Scale the source by the type size. 3790 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 3791 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3792 Src, getIntPtrConstant(ElementSize)); 3793 3794 TargetLowering::ArgListTy Args; 3795 TargetLowering::ArgListEntry Entry; 3796 Entry.Node = Src; 3797 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3798 Args.push_back(Entry); 3799 3800 std::pair<SDOperand,SDOperand> Result = 3801 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3802 DAG.getExternalSymbol("malloc", IntPtr), 3803 Args, DAG); 3804 setValue(&I, Result.first); // Pointers always fit in registers 3805 DAG.setRoot(Result.second); 3806} 3807 3808void SelectionDAGLowering::visitFree(FreeInst &I) { 3809 TargetLowering::ArgListTy Args; 3810 TargetLowering::ArgListEntry Entry; 3811 Entry.Node = getValue(I.getOperand(0)); 3812 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3813 Args.push_back(Entry); 3814 MVT::ValueType IntPtr = TLI.getPointerTy(); 3815 std::pair<SDOperand,SDOperand> Result = 3816 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3817 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3818 DAG.setRoot(Result.second); 3819} 3820 3821// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3822// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3823// instructions are special in various ways, which require special support to 3824// insert. The specified MachineInstr is created but not inserted into any 3825// basic blocks, and the scheduler passes ownership of it to this method. 3826MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3827 MachineBasicBlock *MBB) { 3828 cerr << "If a target marks an instruction with " 3829 << "'usesCustomDAGSchedInserter', it must implement " 3830 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3831 abort(); 3832 return 0; 3833} 3834 3835void SelectionDAGLowering::visitVAStart(CallInst &I) { 3836 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3837 getValue(I.getOperand(1)), 3838 DAG.getSrcValue(I.getOperand(1)))); 3839} 3840 3841void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3842 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3843 getValue(I.getOperand(0)), 3844 DAG.getSrcValue(I.getOperand(0))); 3845 setValue(&I, V); 3846 DAG.setRoot(V.getValue(1)); 3847} 3848 3849void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3850 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3851 getValue(I.getOperand(1)), 3852 DAG.getSrcValue(I.getOperand(1)))); 3853} 3854 3855void SelectionDAGLowering::visitVACopy(CallInst &I) { 3856 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3857 getValue(I.getOperand(1)), 3858 getValue(I.getOperand(2)), 3859 DAG.getSrcValue(I.getOperand(1)), 3860 DAG.getSrcValue(I.getOperand(2)))); 3861} 3862 3863/// TargetLowering::LowerArguments - This is the default LowerArguments 3864/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3865/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3866/// integrated into SDISel. 3867std::vector<SDOperand> 3868TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3869 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3870 std::vector<SDOperand> Ops; 3871 Ops.push_back(DAG.getRoot()); 3872 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3873 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3874 3875 // Add one result value for each formal argument. 3876 std::vector<MVT::ValueType> RetVals; 3877 unsigned j = 1; 3878 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3879 I != E; ++I, ++j) { 3880 MVT::ValueType VT = getValueType(I->getType()); 3881 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3882 unsigned OriginalAlignment = 3883 getTargetData()->getABITypeAlignment(I->getType()); 3884 3885 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3886 // that is zero extended! 3887 if (F.paramHasAttr(j, ParamAttr::ZExt)) 3888 Flags &= ~(ISD::ParamFlags::SExt); 3889 if (F.paramHasAttr(j, ParamAttr::SExt)) 3890 Flags |= ISD::ParamFlags::SExt; 3891 if (F.paramHasAttr(j, ParamAttr::InReg)) 3892 Flags |= ISD::ParamFlags::InReg; 3893 if (F.paramHasAttr(j, ParamAttr::StructRet)) 3894 Flags |= ISD::ParamFlags::StructReturn; 3895 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 3896 Flags |= ISD::ParamFlags::ByVal; 3897 const PointerType *Ty = cast<PointerType>(I->getType()); 3898 const StructType *STy = cast<StructType>(Ty->getElementType()); 3899 unsigned StructAlign = 3900 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 3901 unsigned StructSize = getTargetData()->getABITypeSize(STy); 3902 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3903 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3904 } 3905 if (F.paramHasAttr(j, ParamAttr::Nest)) 3906 Flags |= ISD::ParamFlags::Nest; 3907 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3908 3909 switch (getTypeAction(VT)) { 3910 default: assert(0 && "Unknown type action!"); 3911 case Legal: 3912 RetVals.push_back(VT); 3913 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3914 break; 3915 case Promote: 3916 RetVals.push_back(getTypeToTransformTo(VT)); 3917 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3918 break; 3919 case Expand: { 3920 // If this is an illegal type, it needs to be broken up to fit into 3921 // registers. 3922 MVT::ValueType RegisterVT = getRegisterType(VT); 3923 unsigned NumRegs = getNumRegisters(VT); 3924 for (unsigned i = 0; i != NumRegs; ++i) { 3925 RetVals.push_back(RegisterVT); 3926 // if it isn't first piece, alignment must be 1 3927 if (i > 0) 3928 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3929 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3930 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3931 } 3932 break; 3933 } 3934 } 3935 } 3936 3937 RetVals.push_back(MVT::Other); 3938 3939 // Create the node. 3940 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3941 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3942 &Ops[0], Ops.size()).Val; 3943 unsigned NumArgRegs = Result->getNumValues() - 1; 3944 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3945 3946 // Set up the return result vector. 3947 Ops.clear(); 3948 unsigned i = 0; 3949 unsigned Idx = 1; 3950 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3951 ++I, ++Idx) { 3952 MVT::ValueType VT = getValueType(I->getType()); 3953 3954 switch (getTypeAction(VT)) { 3955 default: assert(0 && "Unknown type action!"); 3956 case Legal: 3957 Ops.push_back(SDOperand(Result, i++)); 3958 break; 3959 case Promote: { 3960 SDOperand Op(Result, i++); 3961 if (MVT::isInteger(VT)) { 3962 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 3963 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3964 DAG.getValueType(VT)); 3965 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 3966 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3967 DAG.getValueType(VT)); 3968 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3969 } else { 3970 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3971 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3972 } 3973 Ops.push_back(Op); 3974 break; 3975 } 3976 case Expand: { 3977 MVT::ValueType PartVT = getRegisterType(VT); 3978 unsigned NumParts = getNumRegisters(VT); 3979 SmallVector<SDOperand, 4> Parts(NumParts); 3980 for (unsigned j = 0; j != NumParts; ++j) 3981 Parts[j] = SDOperand(Result, i++); 3982 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3983 break; 3984 } 3985 } 3986 } 3987 assert(i == NumArgRegs && "Argument register count mismatch!"); 3988 return Ops; 3989} 3990 3991 3992/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3993/// implementation, which just inserts an ISD::CALL node, which is later custom 3994/// lowered by the target to something concrete. FIXME: When all targets are 3995/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3996std::pair<SDOperand, SDOperand> 3997TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3998 bool RetTyIsSigned, bool isVarArg, 3999 unsigned CallingConv, bool isTailCall, 4000 SDOperand Callee, 4001 ArgListTy &Args, SelectionDAG &DAG) { 4002 SmallVector<SDOperand, 32> Ops; 4003 Ops.push_back(Chain); // Op#0 - Chain 4004 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4005 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4006 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4007 Ops.push_back(Callee); 4008 4009 // Handle all of the outgoing arguments. 4010 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4011 MVT::ValueType VT = getValueType(Args[i].Ty); 4012 SDOperand Op = Args[i].Node; 4013 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4014 unsigned OriginalAlignment = 4015 getTargetData()->getABITypeAlignment(Args[i].Ty); 4016 4017 if (Args[i].isSExt) 4018 Flags |= ISD::ParamFlags::SExt; 4019 if (Args[i].isZExt) 4020 Flags |= ISD::ParamFlags::ZExt; 4021 if (Args[i].isInReg) 4022 Flags |= ISD::ParamFlags::InReg; 4023 if (Args[i].isSRet) 4024 Flags |= ISD::ParamFlags::StructReturn; 4025 if (Args[i].isByVal) { 4026 Flags |= ISD::ParamFlags::ByVal; 4027 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4028 const StructType *STy = cast<StructType>(Ty->getElementType()); 4029 unsigned StructAlign = 4030 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 4031 unsigned StructSize = getTargetData()->getABITypeSize(STy); 4032 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 4033 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 4034 } 4035 if (Args[i].isNest) 4036 Flags |= ISD::ParamFlags::Nest; 4037 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4038 4039 switch (getTypeAction(VT)) { 4040 default: assert(0 && "Unknown type action!"); 4041 case Legal: 4042 Ops.push_back(Op); 4043 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4044 break; 4045 case Promote: 4046 if (MVT::isInteger(VT)) { 4047 unsigned ExtOp; 4048 if (Args[i].isSExt) 4049 ExtOp = ISD::SIGN_EXTEND; 4050 else if (Args[i].isZExt) 4051 ExtOp = ISD::ZERO_EXTEND; 4052 else 4053 ExtOp = ISD::ANY_EXTEND; 4054 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 4055 } else { 4056 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 4057 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 4058 } 4059 Ops.push_back(Op); 4060 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4061 break; 4062 case Expand: { 4063 MVT::ValueType PartVT = getRegisterType(VT); 4064 unsigned NumParts = getNumRegisters(VT); 4065 SmallVector<SDOperand, 4> Parts(NumParts); 4066 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 4067 for (unsigned i = 0; i != NumParts; ++i) { 4068 // if it isn't first piece, alignment must be 1 4069 unsigned MyFlags = Flags; 4070 if (i != 0) 4071 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4072 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4073 4074 Ops.push_back(Parts[i]); 4075 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4076 } 4077 break; 4078 } 4079 } 4080 } 4081 4082 // Figure out the result value types. 4083 MVT::ValueType VT = getValueType(RetTy); 4084 MVT::ValueType RegisterVT = getRegisterType(VT); 4085 unsigned NumRegs = getNumRegisters(VT); 4086 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4087 for (unsigned i = 0; i != NumRegs; ++i) 4088 RetTys[i] = RegisterVT; 4089 4090 RetTys.push_back(MVT::Other); // Always has a chain. 4091 4092 // Create the CALL node. 4093 SDOperand Res = DAG.getNode(ISD::CALL, 4094 DAG.getVTList(&RetTys[0], NumRegs + 1), 4095 &Ops[0], Ops.size()); 4096 Chain = Res.getValue(NumRegs); 4097 4098 // Gather up the call result into a single value. 4099 if (RetTy != Type::VoidTy) { 4100 ISD::NodeType AssertOp = ISD::AssertSext; 4101 if (!RetTyIsSigned) 4102 AssertOp = ISD::AssertZext; 4103 SmallVector<SDOperand, 4> Results(NumRegs); 4104 for (unsigned i = 0; i != NumRegs; ++i) 4105 Results[i] = Res.getValue(i); 4106 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4107 } 4108 4109 return std::make_pair(Res, Chain); 4110} 4111 4112SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4113 assert(0 && "LowerOperation not implemented for this target!"); 4114 abort(); 4115 return SDOperand(); 4116} 4117 4118SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4119 SelectionDAG &DAG) { 4120 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4121 abort(); 4122 return SDOperand(); 4123} 4124 4125/// getMemsetValue - Vectorized representation of the memset value 4126/// operand. 4127static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4128 SelectionDAG &DAG) { 4129 MVT::ValueType CurVT = VT; 4130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4131 uint64_t Val = C->getValue() & 255; 4132 unsigned Shift = 8; 4133 while (CurVT != MVT::i8) { 4134 Val = (Val << Shift) | Val; 4135 Shift <<= 1; 4136 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4137 } 4138 return DAG.getConstant(Val, VT); 4139 } else { 4140 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4141 unsigned Shift = 8; 4142 while (CurVT != MVT::i8) { 4143 Value = 4144 DAG.getNode(ISD::OR, VT, 4145 DAG.getNode(ISD::SHL, VT, Value, 4146 DAG.getConstant(Shift, MVT::i8)), Value); 4147 Shift <<= 1; 4148 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4149 } 4150 4151 return Value; 4152 } 4153} 4154 4155/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4156/// used when a memcpy is turned into a memset when the source is a constant 4157/// string ptr. 4158static SDOperand getMemsetStringVal(MVT::ValueType VT, 4159 SelectionDAG &DAG, TargetLowering &TLI, 4160 std::string &Str, unsigned Offset) { 4161 uint64_t Val = 0; 4162 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4163 if (TLI.isLittleEndian()) 4164 Offset = Offset + MSB - 1; 4165 for (unsigned i = 0; i != MSB; ++i) { 4166 Val = (Val << 8) | (unsigned char)Str[Offset]; 4167 Offset += TLI.isLittleEndian() ? -1 : 1; 4168 } 4169 return DAG.getConstant(Val, VT); 4170} 4171 4172/// getMemBasePlusOffset - Returns base and offset node for the 4173static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4174 SelectionDAG &DAG, TargetLowering &TLI) { 4175 MVT::ValueType VT = Base.getValueType(); 4176 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4177} 4178 4179/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4180/// to replace the memset / memcpy is below the threshold. It also returns the 4181/// types of the sequence of memory ops to perform memset / memcpy. 4182static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4183 unsigned Limit, uint64_t Size, 4184 unsigned Align, TargetLowering &TLI) { 4185 MVT::ValueType VT; 4186 4187 if (TLI.allowsUnalignedMemoryAccesses()) { 4188 VT = MVT::i64; 4189 } else { 4190 switch (Align & 7) { 4191 case 0: 4192 VT = MVT::i64; 4193 break; 4194 case 4: 4195 VT = MVT::i32; 4196 break; 4197 case 2: 4198 VT = MVT::i16; 4199 break; 4200 default: 4201 VT = MVT::i8; 4202 break; 4203 } 4204 } 4205 4206 MVT::ValueType LVT = MVT::i64; 4207 while (!TLI.isTypeLegal(LVT)) 4208 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4209 assert(MVT::isInteger(LVT)); 4210 4211 if (VT > LVT) 4212 VT = LVT; 4213 4214 unsigned NumMemOps = 0; 4215 while (Size != 0) { 4216 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4217 while (VTSize > Size) { 4218 VT = (MVT::ValueType)((unsigned)VT - 1); 4219 VTSize >>= 1; 4220 } 4221 assert(MVT::isInteger(VT)); 4222 4223 if (++NumMemOps > Limit) 4224 return false; 4225 MemOps.push_back(VT); 4226 Size -= VTSize; 4227 } 4228 4229 return true; 4230} 4231 4232void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4233 SDOperand Op1 = getValue(I.getOperand(1)); 4234 SDOperand Op2 = getValue(I.getOperand(2)); 4235 SDOperand Op3 = getValue(I.getOperand(3)); 4236 SDOperand Op4 = getValue(I.getOperand(4)); 4237 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4238 if (Align == 0) Align = 1; 4239 4240 // If the source and destination are known to not be aliases, we can 4241 // lower memmove as memcpy. 4242 if (Op == ISD::MEMMOVE) { 4243 uint64_t Size = -1ULL; 4244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4245 Size = C->getValue(); 4246 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4247 AliasAnalysis::NoAlias) 4248 Op = ISD::MEMCPY; 4249 } 4250 4251 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4252 std::vector<MVT::ValueType> MemOps; 4253 4254 // Expand memset / memcpy to a series of load / store ops 4255 // if the size operand falls below a certain threshold. 4256 SmallVector<SDOperand, 8> OutChains; 4257 switch (Op) { 4258 default: break; // Do nothing for now. 4259 case ISD::MEMSET: { 4260 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4261 Size->getValue(), Align, TLI)) { 4262 unsigned NumMemOps = MemOps.size(); 4263 unsigned Offset = 0; 4264 for (unsigned i = 0; i < NumMemOps; i++) { 4265 MVT::ValueType VT = MemOps[i]; 4266 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4267 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4268 SDOperand Store = DAG.getStore(getRoot(), Value, 4269 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4270 I.getOperand(1), Offset); 4271 OutChains.push_back(Store); 4272 Offset += VTSize; 4273 } 4274 } 4275 break; 4276 } 4277 case ISD::MEMCPY: { 4278 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4279 Size->getValue(), Align, TLI)) { 4280 unsigned NumMemOps = MemOps.size(); 4281 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4282 GlobalAddressSDNode *G = NULL; 4283 std::string Str; 4284 bool CopyFromStr = false; 4285 4286 if (Op2.getOpcode() == ISD::GlobalAddress) 4287 G = cast<GlobalAddressSDNode>(Op2); 4288 else if (Op2.getOpcode() == ISD::ADD && 4289 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4290 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4291 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4292 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4293 } 4294 if (G) { 4295 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4296 if (GV && GV->isConstant()) { 4297 Str = GV->getStringValue(false); 4298 if (!Str.empty()) { 4299 CopyFromStr = true; 4300 SrcOff += SrcDelta; 4301 } 4302 } 4303 } 4304 4305 for (unsigned i = 0; i < NumMemOps; i++) { 4306 MVT::ValueType VT = MemOps[i]; 4307 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4308 SDOperand Value, Chain, Store; 4309 4310 if (CopyFromStr) { 4311 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4312 Chain = getRoot(); 4313 Store = 4314 DAG.getStore(Chain, Value, 4315 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4316 I.getOperand(1), DstOff); 4317 } else { 4318 Value = DAG.getLoad(VT, getRoot(), 4319 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4320 I.getOperand(2), SrcOff, false, Align); 4321 Chain = Value.getValue(1); 4322 Store = 4323 DAG.getStore(Chain, Value, 4324 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4325 I.getOperand(1), DstOff, false, Align); 4326 } 4327 OutChains.push_back(Store); 4328 SrcOff += VTSize; 4329 DstOff += VTSize; 4330 } 4331 } 4332 break; 4333 } 4334 } 4335 4336 if (!OutChains.empty()) { 4337 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4338 &OutChains[0], OutChains.size())); 4339 return; 4340 } 4341 } 4342 4343 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1); 4344 SDOperand Node; 4345 switch(Op) { 4346 default: 4347 assert(0 && "Unknown Op"); 4348 case ISD::MEMCPY: 4349 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4350 break; 4351 case ISD::MEMMOVE: 4352 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4353 break; 4354 case ISD::MEMSET: 4355 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4356 break; 4357 } 4358 DAG.setRoot(Node); 4359} 4360 4361//===----------------------------------------------------------------------===// 4362// SelectionDAGISel code 4363//===----------------------------------------------------------------------===// 4364 4365unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4366 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4367} 4368 4369void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4370 AU.addRequired<AliasAnalysis>(); 4371 AU.setPreservesAll(); 4372} 4373 4374 4375 4376bool SelectionDAGISel::runOnFunction(Function &Fn) { 4377 // Get alias analysis for load/store combining. 4378 AA = &getAnalysis<AliasAnalysis>(); 4379 4380 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4381 RegMap = MF.getSSARegMap(); 4382 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4383 4384 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4385 4386 if (ExceptionHandling) 4387 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4388 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4389 // Mark landing pad. 4390 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4391 4392 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4393 SelectBasicBlock(I, MF, FuncInfo); 4394 4395 // Add function live-ins to entry block live-in set. 4396 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4397 BB = FuncInfo.MBBMap[EntryBB]; 4398 if (!MF.livein_empty()) 4399 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4400 E = MF.livein_end(); I != E; ++I) 4401 BB->addLiveIn(I->first); 4402 4403#ifndef NDEBUG 4404 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4405 "Not all catch info was assigned to a landing pad!"); 4406#endif 4407 4408 return true; 4409} 4410 4411SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4412 unsigned Reg) { 4413 SDOperand Op = getValue(V); 4414 assert((Op.getOpcode() != ISD::CopyFromReg || 4415 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4416 "Copy from a reg to the same reg!"); 4417 4418 MVT::ValueType SrcVT = Op.getValueType(); 4419 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4420 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4421 SmallVector<SDOperand, 8> Regs(NumRegs); 4422 SmallVector<SDOperand, 8> Chains(NumRegs); 4423 4424 // Copy the value by legal parts into sequential virtual registers. 4425 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4426 for (unsigned i = 0; i != NumRegs; ++i) 4427 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4428 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4429} 4430 4431void SelectionDAGISel:: 4432LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4433 std::vector<SDOperand> &UnorderedChains) { 4434 // If this is the entry block, emit arguments. 4435 Function &F = *LLVMBB->getParent(); 4436 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4437 SDOperand OldRoot = SDL.DAG.getRoot(); 4438 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4439 4440 unsigned a = 0; 4441 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4442 AI != E; ++AI, ++a) 4443 if (!AI->use_empty()) { 4444 SDL.setValue(AI, Args[a]); 4445 4446 // If this argument is live outside of the entry block, insert a copy from 4447 // whereever we got it to the vreg that other BB's will reference it as. 4448 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4449 if (VMI != FuncInfo.ValueMap.end()) { 4450 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4451 UnorderedChains.push_back(Copy); 4452 } 4453 } 4454 4455 // Finally, if the target has anything special to do, allow it to do so. 4456 // FIXME: this should insert code into the DAG! 4457 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4458} 4459 4460static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4461 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4462 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4463 if (isSelector(I)) { 4464 // Apply the catch info to DestBB. 4465 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4466#ifndef NDEBUG 4467 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4468 FLI.CatchInfoFound.insert(I); 4469#endif 4470 } 4471} 4472 4473/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 4474/// DAG and fixes their tailcall attribute operand. 4475static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 4476 TargetLowering& TLI) { 4477 SDNode * Ret = NULL; 4478 SDOperand Terminator = DAG.getRoot(); 4479 4480 // Find RET node. 4481 if (Terminator.getOpcode() == ISD::RET) { 4482 Ret = Terminator.Val; 4483 } 4484 4485 // Fix tail call attribute of CALL nodes. 4486 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 4487 BI = prior(DAG.allnodes_end()); BI != BE; --BI) { 4488 if (BI->getOpcode() == ISD::CALL) { 4489 SDOperand OpRet(Ret, 0); 4490 SDOperand OpCall(static_cast<SDNode*>(BI), 0); 4491 bool isMarkedTailCall = 4492 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 4493 // If CALL node has tail call attribute set to true and the call is not 4494 // eligible (no RET or the target rejects) the attribute is fixed to 4495 // false. The TargetLowering::IsEligibleForTailCallOptimization function 4496 // must correctly identify tail call optimizable calls. 4497 if (isMarkedTailCall && 4498 (Ret==NULL || 4499 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) { 4500 SmallVector<SDOperand, 32> Ops; 4501 unsigned idx=0; 4502 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 4503 E=OpCall.Val->op_end(); I!=E; I++, idx++) { 4504 if (idx!=3) 4505 Ops.push_back(*I); 4506 else 4507 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 4508 } 4509 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 4510 } 4511 } 4512 } 4513} 4514 4515void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4516 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4517 FunctionLoweringInfo &FuncInfo) { 4518 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo); 4519 4520 std::vector<SDOperand> UnorderedChains; 4521 4522 // Lower any arguments needed in this block if this is the entry block. 4523 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4524 LowerArguments(LLVMBB, SDL, UnorderedChains); 4525 4526 BB = FuncInfo.MBBMap[LLVMBB]; 4527 SDL.setCurrentBasicBlock(BB); 4528 4529 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4530 4531 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4532 // Add a label to mark the beginning of the landing pad. Deletion of the 4533 // landing pad can thus be detected via the MachineModuleInfo. 4534 unsigned LabelID = MMI->addLandingPad(BB); 4535 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4536 DAG.getConstant(LabelID, MVT::i32))); 4537 4538 // Mark exception register as live in. 4539 unsigned Reg = TLI.getExceptionAddressRegister(); 4540 if (Reg) BB->addLiveIn(Reg); 4541 4542 // Mark exception selector register as live in. 4543 Reg = TLI.getExceptionSelectorRegister(); 4544 if (Reg) BB->addLiveIn(Reg); 4545 4546 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4547 // function and list of typeids logically belong to the invoke (or, if you 4548 // like, the basic block containing the invoke), and need to be associated 4549 // with it in the dwarf exception handling tables. Currently however the 4550 // information is provided by an intrinsic (eh.selector) that can be moved 4551 // to unexpected places by the optimizers: if the unwind edge is critical, 4552 // then breaking it can result in the intrinsics being in the successor of 4553 // the landing pad, not the landing pad itself. This results in exceptions 4554 // not being caught because no typeids are associated with the invoke. 4555 // This may not be the only way things can go wrong, but it is the only way 4556 // we try to work around for the moment. 4557 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4558 4559 if (Br && Br->isUnconditional()) { // Critical edge? 4560 BasicBlock::iterator I, E; 4561 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4562 if (isSelector(I)) 4563 break; 4564 4565 if (I == E) 4566 // No catch info found - try to extract some from the successor. 4567 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4568 } 4569 } 4570 4571 // Lower all of the non-terminator instructions. 4572 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4573 I != E; ++I) 4574 SDL.visit(*I); 4575 4576 // Ensure that all instructions which are used outside of their defining 4577 // blocks are available as virtual registers. Invoke is handled elsewhere. 4578 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4579 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4580 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4581 if (VMI != FuncInfo.ValueMap.end()) 4582 UnorderedChains.push_back( 4583 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4584 } 4585 4586 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4587 // ensure constants are generated when needed. Remember the virtual registers 4588 // that need to be added to the Machine PHI nodes as input. We cannot just 4589 // directly add them, because expansion might result in multiple MBB's for one 4590 // BB. As such, the start of the BB might correspond to a different MBB than 4591 // the end. 4592 // 4593 TerminatorInst *TI = LLVMBB->getTerminator(); 4594 4595 // Emit constants only once even if used by multiple PHI nodes. 4596 std::map<Constant*, unsigned> ConstantsOut; 4597 4598 // Vector bool would be better, but vector<bool> is really slow. 4599 std::vector<unsigned char> SuccsHandled; 4600 if (TI->getNumSuccessors()) 4601 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4602 4603 // Check successor nodes' PHI nodes that expect a constant to be available 4604 // from this block. 4605 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4606 BasicBlock *SuccBB = TI->getSuccessor(succ); 4607 if (!isa<PHINode>(SuccBB->begin())) continue; 4608 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4609 4610 // If this terminator has multiple identical successors (common for 4611 // switches), only handle each succ once. 4612 unsigned SuccMBBNo = SuccMBB->getNumber(); 4613 if (SuccsHandled[SuccMBBNo]) continue; 4614 SuccsHandled[SuccMBBNo] = true; 4615 4616 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4617 PHINode *PN; 4618 4619 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4620 // nodes and Machine PHI nodes, but the incoming operands have not been 4621 // emitted yet. 4622 for (BasicBlock::iterator I = SuccBB->begin(); 4623 (PN = dyn_cast<PHINode>(I)); ++I) { 4624 // Ignore dead phi's. 4625 if (PN->use_empty()) continue; 4626 4627 unsigned Reg; 4628 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4629 4630 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4631 unsigned &RegOut = ConstantsOut[C]; 4632 if (RegOut == 0) { 4633 RegOut = FuncInfo.CreateRegForValue(C); 4634 UnorderedChains.push_back( 4635 SDL.CopyValueToVirtualRegister(C, RegOut)); 4636 } 4637 Reg = RegOut; 4638 } else { 4639 Reg = FuncInfo.ValueMap[PHIOp]; 4640 if (Reg == 0) { 4641 assert(isa<AllocaInst>(PHIOp) && 4642 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4643 "Didn't codegen value into a register!??"); 4644 Reg = FuncInfo.CreateRegForValue(PHIOp); 4645 UnorderedChains.push_back( 4646 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4647 } 4648 } 4649 4650 // Remember that this register needs to added to the machine PHI node as 4651 // the input for this MBB. 4652 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4653 unsigned NumRegisters = TLI.getNumRegisters(VT); 4654 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4655 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4656 } 4657 } 4658 ConstantsOut.clear(); 4659 4660 // Turn all of the unordered chains into one factored node. 4661 if (!UnorderedChains.empty()) { 4662 SDOperand Root = SDL.getRoot(); 4663 if (Root.getOpcode() != ISD::EntryToken) { 4664 unsigned i = 0, e = UnorderedChains.size(); 4665 for (; i != e; ++i) { 4666 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4667 if (UnorderedChains[i].Val->getOperand(0) == Root) 4668 break; // Don't add the root if we already indirectly depend on it. 4669 } 4670 4671 if (i == e) 4672 UnorderedChains.push_back(Root); 4673 } 4674 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4675 &UnorderedChains[0], UnorderedChains.size())); 4676 } 4677 4678 // Lower the terminator after the copies are emitted. 4679 SDL.visit(*LLVMBB->getTerminator()); 4680 4681 // Copy over any CaseBlock records that may now exist due to SwitchInst 4682 // lowering, as well as any jump table information. 4683 SwitchCases.clear(); 4684 SwitchCases = SDL.SwitchCases; 4685 JTCases.clear(); 4686 JTCases = SDL.JTCases; 4687 BitTestCases.clear(); 4688 BitTestCases = SDL.BitTestCases; 4689 4690 // Make sure the root of the DAG is up-to-date. 4691 DAG.setRoot(SDL.getRoot()); 4692 4693 // Check whether calls in this block are real tail calls. Fix up CALL nodes 4694 // with correct tailcall attribute so that the target can rely on the tailcall 4695 // attribute indicating whether the call is really eligible for tail call 4696 // optimization. 4697 CheckDAGForTailCallsAndFixThem(DAG, TLI); 4698} 4699 4700void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4701 DOUT << "Lowered selection DAG:\n"; 4702 DEBUG(DAG.dump()); 4703 4704 // Run the DAG combiner in pre-legalize mode. 4705 DAG.Combine(false, *AA); 4706 4707 DOUT << "Optimized lowered selection DAG:\n"; 4708 DEBUG(DAG.dump()); 4709 4710 // Second step, hack on the DAG until it only uses operations and types that 4711 // the target supports. 4712#if 0 // Enable this some day. 4713 DAG.LegalizeTypes(); 4714 // Someday even later, enable a dag combine pass here. 4715#endif 4716 DAG.Legalize(); 4717 4718 DOUT << "Legalized selection DAG:\n"; 4719 DEBUG(DAG.dump()); 4720 4721 // Run the DAG combiner in post-legalize mode. 4722 DAG.Combine(true, *AA); 4723 4724 DOUT << "Optimized legalized selection DAG:\n"; 4725 DEBUG(DAG.dump()); 4726 4727 if (ViewISelDAGs) DAG.viewGraph(); 4728 4729 // Third, instruction select all of the operations to machine code, adding the 4730 // code to the MachineBasicBlock. 4731 InstructionSelectBasicBlock(DAG); 4732 4733 DOUT << "Selected machine code:\n"; 4734 DEBUG(BB->dump()); 4735} 4736 4737void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4738 FunctionLoweringInfo &FuncInfo) { 4739 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4740 { 4741 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4742 CurDAG = &DAG; 4743 4744 // First step, lower LLVM code to some DAG. This DAG may use operations and 4745 // types that are not supported by the target. 4746 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4747 4748 // Second step, emit the lowered DAG as machine code. 4749 CodeGenAndEmitDAG(DAG); 4750 } 4751 4752 DOUT << "Total amount of phi nodes to update: " 4753 << PHINodesToUpdate.size() << "\n"; 4754 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4755 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4756 << ", " << PHINodesToUpdate[i].second << ")\n";); 4757 4758 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4759 // PHI nodes in successors. 4760 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4761 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4762 MachineInstr *PHI = PHINodesToUpdate[i].first; 4763 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4764 "This is not a machine PHI node that we are updating!"); 4765 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 4766 false)); 4767 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4768 } 4769 return; 4770 } 4771 4772 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4773 // Lower header first, if it wasn't already lowered 4774 if (!BitTestCases[i].Emitted) { 4775 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4776 CurDAG = &HSDAG; 4777 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4778 // Set the current basic block to the mbb we wish to insert the code into 4779 BB = BitTestCases[i].Parent; 4780 HSDL.setCurrentBasicBlock(BB); 4781 // Emit the code 4782 HSDL.visitBitTestHeader(BitTestCases[i]); 4783 HSDAG.setRoot(HSDL.getRoot()); 4784 CodeGenAndEmitDAG(HSDAG); 4785 } 4786 4787 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4788 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4789 CurDAG = &BSDAG; 4790 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo); 4791 // Set the current basic block to the mbb we wish to insert the code into 4792 BB = BitTestCases[i].Cases[j].ThisBB; 4793 BSDL.setCurrentBasicBlock(BB); 4794 // Emit the code 4795 if (j+1 != ej) 4796 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4797 BitTestCases[i].Reg, 4798 BitTestCases[i].Cases[j]); 4799 else 4800 BSDL.visitBitTestCase(BitTestCases[i].Default, 4801 BitTestCases[i].Reg, 4802 BitTestCases[i].Cases[j]); 4803 4804 4805 BSDAG.setRoot(BSDL.getRoot()); 4806 CodeGenAndEmitDAG(BSDAG); 4807 } 4808 4809 // Update PHI Nodes 4810 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4811 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4812 MachineBasicBlock *PHIBB = PHI->getParent(); 4813 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4814 "This is not a machine PHI node that we are updating!"); 4815 // This is "default" BB. We have two jumps to it. From "header" BB and 4816 // from last "case" BB. 4817 if (PHIBB == BitTestCases[i].Default) { 4818 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4819 false)); 4820 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 4821 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4822 false)); 4823 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 4824 back().ThisBB)); 4825 } 4826 // One of "cases" BB. 4827 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4828 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4829 if (cBB->succ_end() != 4830 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4831 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4832 false)); 4833 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 4834 } 4835 } 4836 } 4837 } 4838 4839 // If the JumpTable record is filled in, then we need to emit a jump table. 4840 // Updating the PHI nodes is tricky in this case, since we need to determine 4841 // whether the PHI is a successor of the range check MBB or the jump table MBB 4842 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4843 // Lower header first, if it wasn't already lowered 4844 if (!JTCases[i].first.Emitted) { 4845 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4846 CurDAG = &HSDAG; 4847 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4848 // Set the current basic block to the mbb we wish to insert the code into 4849 BB = JTCases[i].first.HeaderBB; 4850 HSDL.setCurrentBasicBlock(BB); 4851 // Emit the code 4852 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4853 HSDAG.setRoot(HSDL.getRoot()); 4854 CodeGenAndEmitDAG(HSDAG); 4855 } 4856 4857 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4858 CurDAG = &JSDAG; 4859 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo); 4860 // Set the current basic block to the mbb we wish to insert the code into 4861 BB = JTCases[i].second.MBB; 4862 JSDL.setCurrentBasicBlock(BB); 4863 // Emit the code 4864 JSDL.visitJumpTable(JTCases[i].second); 4865 JSDAG.setRoot(JSDL.getRoot()); 4866 CodeGenAndEmitDAG(JSDAG); 4867 4868 // Update PHI Nodes 4869 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4870 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4871 MachineBasicBlock *PHIBB = PHI->getParent(); 4872 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4873 "This is not a machine PHI node that we are updating!"); 4874 // "default" BB. We can go there only from header BB. 4875 if (PHIBB == JTCases[i].second.Default) { 4876 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4877 false)); 4878 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 4879 } 4880 // JT BB. Just iterate over successors here 4881 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4882 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 4883 false)); 4884 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4885 } 4886 } 4887 } 4888 4889 // If the switch block involved a branch to one of the actual successors, we 4890 // need to update PHI nodes in that block. 4891 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4892 MachineInstr *PHI = PHINodesToUpdate[i].first; 4893 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4894 "This is not a machine PHI node that we are updating!"); 4895 if (BB->isSuccessor(PHI->getParent())) { 4896 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 4897 false)); 4898 PHI->addOperand(MachineOperand::CreateMBB(BB)); 4899 } 4900 } 4901 4902 // If we generated any switch lowering information, build and codegen any 4903 // additional DAGs necessary. 4904 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4905 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4906 CurDAG = &SDAG; 4907 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo); 4908 4909 // Set the current basic block to the mbb we wish to insert the code into 4910 BB = SwitchCases[i].ThisBB; 4911 SDL.setCurrentBasicBlock(BB); 4912 4913 // Emit the code 4914 SDL.visitSwitchCase(SwitchCases[i]); 4915 SDAG.setRoot(SDL.getRoot()); 4916 CodeGenAndEmitDAG(SDAG); 4917 4918 // Handle any PHI nodes in successors of this chunk, as if we were coming 4919 // from the original BB before switch expansion. Note that PHI nodes can 4920 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4921 // handle them the right number of times. 4922 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4923 for (MachineBasicBlock::iterator Phi = BB->begin(); 4924 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4925 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4926 for (unsigned pn = 0; ; ++pn) { 4927 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4928 if (PHINodesToUpdate[pn].first == Phi) { 4929 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 4930 second, false)); 4931 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 4932 break; 4933 } 4934 } 4935 } 4936 4937 // Don't process RHS if same block as LHS. 4938 if (BB == SwitchCases[i].FalseBB) 4939 SwitchCases[i].FalseBB = 0; 4940 4941 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4942 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4943 SwitchCases[i].FalseBB = 0; 4944 } 4945 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4946 } 4947} 4948 4949 4950//===----------------------------------------------------------------------===// 4951/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4952/// target node in the graph. 4953void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4954 if (ViewSchedDAGs) DAG.viewGraph(); 4955 4956 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4957 4958 if (!Ctor) { 4959 Ctor = ISHeuristic; 4960 RegisterScheduler::setDefault(Ctor); 4961 } 4962 4963 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4964 BB = SL->Run(); 4965 4966 if (ViewSUnitDAGs) SL->viewGraph(); 4967 4968 delete SL; 4969} 4970 4971 4972HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4973 return new HazardRecognizer(); 4974} 4975 4976//===----------------------------------------------------------------------===// 4977// Helper functions used by the generated instruction selector. 4978//===----------------------------------------------------------------------===// 4979// Calls to these methods are generated by tblgen. 4980 4981/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4982/// the dag combiner simplified the 255, we still want to match. RHS is the 4983/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4984/// specified in the .td file (e.g. 255). 4985bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4986 int64_t DesiredMaskS) const { 4987 uint64_t ActualMask = RHS->getValue(); 4988 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4989 4990 // If the actual mask exactly matches, success! 4991 if (ActualMask == DesiredMask) 4992 return true; 4993 4994 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4995 if (ActualMask & ~DesiredMask) 4996 return false; 4997 4998 // Otherwise, the DAG Combiner may have proven that the value coming in is 4999 // either already zero or is not demanded. Check for known zero input bits. 5000 uint64_t NeededMask = DesiredMask & ~ActualMask; 5001 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5002 return true; 5003 5004 // TODO: check to see if missing bits are just not demanded. 5005 5006 // Otherwise, this pattern doesn't match. 5007 return false; 5008} 5009 5010/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5011/// the dag combiner simplified the 255, we still want to match. RHS is the 5012/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5013/// specified in the .td file (e.g. 255). 5014bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 5015 int64_t DesiredMaskS) const { 5016 uint64_t ActualMask = RHS->getValue(); 5017 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5018 5019 // If the actual mask exactly matches, success! 5020 if (ActualMask == DesiredMask) 5021 return true; 5022 5023 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5024 if (ActualMask & ~DesiredMask) 5025 return false; 5026 5027 // Otherwise, the DAG Combiner may have proven that the value coming in is 5028 // either already zero or is not demanded. Check for known zero input bits. 5029 uint64_t NeededMask = DesiredMask & ~ActualMask; 5030 5031 uint64_t KnownZero, KnownOne; 5032 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5033 5034 // If all the missing bits in the or are already known to be set, match! 5035 if ((NeededMask & KnownOne) == NeededMask) 5036 return true; 5037 5038 // TODO: check to see if missing bits are just not demanded. 5039 5040 // Otherwise, this pattern doesn't match. 5041 return false; 5042} 5043 5044 5045/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5046/// by tblgen. Others should not call it. 5047void SelectionDAGISel:: 5048SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5049 std::vector<SDOperand> InOps; 5050 std::swap(InOps, Ops); 5051 5052 Ops.push_back(InOps[0]); // input chain. 5053 Ops.push_back(InOps[1]); // input asm string. 5054 5055 unsigned i = 2, e = InOps.size(); 5056 if (InOps[e-1].getValueType() == MVT::Flag) 5057 --e; // Don't process a flag operand if it is here. 5058 5059 while (i != e) { 5060 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5061 if ((Flags & 7) != 4 /*MEM*/) { 5062 // Just skip over this operand, copying the operands verbatim. 5063 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5064 i += (Flags >> 3) + 1; 5065 } else { 5066 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5067 // Otherwise, this is a memory operand. Ask the target to select it. 5068 std::vector<SDOperand> SelOps; 5069 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5070 cerr << "Could not match memory address. Inline asm failure!\n"; 5071 exit(1); 5072 } 5073 5074 // Add this to the output node. 5075 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5076 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5077 IntPtrTy)); 5078 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5079 i += 2; 5080 } 5081 } 5082 5083 // Add the flag input back if present. 5084 if (e != InOps.size()) 5085 Ops.push_back(InOps.back()); 5086} 5087 5088char SelectionDAGISel::ID = 0; 5089