SelectionDAGISel.cpp revision a0e147ae0b909678c1d4562b7896637ed4542016
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 CodeGenOpt::Level OptLevel) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (OptLevel == CodeGenOpt::None) 143 return createFastDAGScheduler(IS, OptLevel); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, OptLevel); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, OptLevel); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and this method is called to expand it into a sequence of 157// instructions, potentially also creating new basic blocks and control flow. 158// When new basic blocks are inserted and the edges from MBB to its successors 159// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 160// DenseMap. 161MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 162 MachineBasicBlock *MBB, 163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 164#ifndef NDEBUG 165 dbgs() << "If a target marks an instruction with " 166 "'usesCustomInserter', it must implement " 167 "TargetLowering::EmitInstrWithCustomInserter!"; 168#endif 169 llvm_unreachable(0); 170 return 0; 171} 172 173/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 174/// physical register has only a single copy use, then coalesced the copy 175/// if possible. 176static void EmitLiveInCopy(MachineBasicBlock *MBB, 177 MachineBasicBlock::iterator &InsertPos, 178 unsigned VirtReg, unsigned PhysReg, 179 const TargetRegisterClass *RC, 180 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 181 const MachineRegisterInfo &MRI, 182 const TargetRegisterInfo &TRI, 183 const TargetInstrInfo &TII) { 184 unsigned NumUses = 0; 185 MachineInstr *UseMI = NULL; 186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 187 UE = MRI.use_end(); UI != UE; ++UI) { 188 UseMI = &*UI; 189 if (++NumUses > 1) 190 break; 191 } 192 193 // If the number of uses is not one, or the use is not a move instruction, 194 // don't coalesce. Also, only coalesce away a virtual register to virtual 195 // register copy. 196 bool Coalesced = false; 197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 198 if (NumUses == 1 && 199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 200 TargetRegisterInfo::isVirtualRegister(DstReg)) { 201 VirtReg = DstReg; 202 Coalesced = true; 203 } 204 205 // Now find an ideal location to insert the copy. 206 MachineBasicBlock::iterator Pos = InsertPos; 207 while (Pos != MBB->begin()) { 208 MachineInstr *PrevMI = prior(Pos); 209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 210 // copyRegToReg might emit multiple instructions to do a copy. 211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 213 // This is what the BB looks like right now: 214 // r1024 = mov r0 215 // ... 216 // r1 = mov r1024 217 // 218 // We want to insert "r1025 = mov r1". Inserting this copy below the 219 // move to r1024 makes it impossible for that move to be coalesced. 220 // 221 // r1025 = mov r1 222 // r1024 = mov r0 223 // ... 224 // r1 = mov 1024 225 // r2 = mov 1025 226 break; // Woot! Found a good location. 227 --Pos; 228 } 229 230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 231 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 232 (void) Emitted; 233 234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 235 if (Coalesced) { 236 if (&*InsertPos == UseMI) ++InsertPos; 237 MBB->erase(UseMI); 238 } 239} 240 241/// EmitLiveInCopies - If this is the first basic block in the function, 242/// and if it has live ins that need to be copied into vregs, emit the 243/// copies into the block. 244static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 245 const MachineRegisterInfo &MRI, 246 const TargetRegisterInfo &TRI, 247 const TargetInstrInfo &TII) { 248 if (SchedLiveInCopies) { 249 // Emit the copies at a heuristically-determined location in the block. 250 DenseMap<MachineInstr*, unsigned> CopyRegMap; 251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 253 E = MRI.livein_end(); LI != E; ++LI) 254 if (LI->second) { 255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 257 RC, CopyRegMap, MRI, TRI, TII); 258 } 259 } else { 260 // Emit the copies into the top of the block. 261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 262 E = MRI.livein_end(); LI != E; ++LI) 263 if (LI->second) { 264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 266 LI->second, LI->first, RC, RC); 267 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 268 (void) Emitted; 269 } 270 } 271} 272 273//===----------------------------------------------------------------------===// 274// SelectionDAGISel code 275//===----------------------------------------------------------------------===// 276 277SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 279 FuncInfo(new FunctionLoweringInfo(TLI)), 280 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 282 GFI(), 283 OptLevel(OL), 284 DAGSize(0) 285{} 286 287SelectionDAGISel::~SelectionDAGISel() { 288 delete SDB; 289 delete CurDAG; 290 delete FuncInfo; 291} 292 293unsigned SelectionDAGISel::MakeReg(EVT VT) { 294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 295} 296 297void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 298 AU.addRequired<AliasAnalysis>(); 299 AU.addPreserved<AliasAnalysis>(); 300 AU.addRequired<GCModuleInfo>(); 301 AU.addPreserved<GCModuleInfo>(); 302 AU.addRequired<DwarfWriter>(); 303 AU.addPreserved<DwarfWriter>(); 304 MachineFunctionPass::getAnalysisUsage(AU); 305} 306 307bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 308 Function &Fn = *mf.getFunction(); 309 310 // Do some sanity-checking on the command-line options. 311 assert((!EnableFastISelVerbose || EnableFastISel) && 312 "-fast-isel-verbose requires -fast-isel"); 313 assert((!EnableFastISelAbort || EnableFastISel) && 314 "-fast-isel-abort requires -fast-isel"); 315 316 // Get alias analysis for load/store combining. 317 AA = &getAnalysis<AliasAnalysis>(); 318 319 MF = &mf; 320 const TargetInstrInfo &TII = *TM.getInstrInfo(); 321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 322 323 if (Fn.hasGC()) 324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 325 else 326 GFI = 0; 327 RegInfo = &MF->getRegInfo(); 328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 329 330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 332 CurDAG->init(*MF, MMI, DW); 333 FuncInfo->set(Fn, *MF, EnableFastISel); 334 SDB->init(GFI, *AA); 335 336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 338 // Mark landing pad. 339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 340 341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 342 343 // If the first basic block in the function has live ins that need to be 344 // copied into vregs, emit the copies into the top of the block before 345 // emitting the code for the block. 346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 347 348 // Add function live-ins to entry block live-in set. 349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 350 E = RegInfo->livein_end(); I != E; ++I) 351 MF->begin()->addLiveIn(I->first); 352 353#ifndef NDEBUG 354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 355 "Not all catch info was assigned to a landing pad!"); 356#endif 357 358 FuncInfo->clear(); 359 360 return true; 361} 362 363/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 364/// attached with this instruction. 365static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 366 SelectionDAGBuilder *SDB, 367 FastISel *FastIS, MachineFunction *MF) { 368 if (isa<DbgInfoIntrinsic>(I)) return; 369 370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 371 DILocation DILoc(Dbg); 372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 373 374 SDB->setCurDebugLoc(Loc); 375 376 if (FastIS) 377 FastIS->setCurDebugLoc(Loc); 378 379 // If the function doesn't have a default debug location yet, set 380 // it. This is kind of a hack. 381 if (MF->getDefaultDebugLoc().isUnknown()) 382 MF->setDefaultDebugLoc(Loc); 383 } 384} 385 386/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 387static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 389 if (FastIS) 390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 391} 392 393void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 394 BasicBlock::iterator Begin, 395 BasicBlock::iterator End, 396 bool &HadTailCall) { 397 SDB->setCurrentBasicBlock(BB); 398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 399 400 // Lower all of the non-terminator instructions. If a call is emitted 401 // as a tail call, cease emitting nodes for this block. 402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 404 405 if (!isa<TerminatorInst>(I)) { 406 SDB->visit(*I); 407 408 // Set the current debug location back to "unknown" so that it doesn't 409 // spuriously apply to subsequent instructions. 410 ResetDebugLoc(SDB, 0); 411 } 412 } 413 414 if (!SDB->HasTailCall) { 415 // Ensure that all instructions which are used outside of their defining 416 // blocks are available as virtual registers. Invoke is handled elsewhere. 417 for (BasicBlock::iterator I = Begin; I != End; ++I) 418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 419 SDB->CopyToExportRegsIfNeeded(I); 420 421 // Handle PHI nodes in successor blocks. 422 if (End == LLVMBB->end()) { 423 HandlePHINodesInSuccessorBlocks(LLVMBB); 424 425 // Lower the terminator after the copies are emitted. 426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 427 SDB->visit(*LLVMBB->getTerminator()); 428 ResetDebugLoc(SDB, 0); 429 } 430 } 431 432 // Make sure the root of the DAG is up-to-date. 433 CurDAG->setRoot(SDB->getControlRoot()); 434 435 // Final step, emit the lowered DAG as machine code. 436 CodeGenAndEmitDAG(); 437 HadTailCall = SDB->HasTailCall; 438 SDB->clear(); 439} 440 441void SelectionDAGISel::ComputeLiveOutVRegInfo() { 442 SmallPtrSet<SDNode*, 128> VisitedNodes; 443 SmallVector<SDNode*, 128> Worklist; 444 445 Worklist.push_back(CurDAG->getRoot().getNode()); 446 447 APInt Mask; 448 APInt KnownZero; 449 APInt KnownOne; 450 451 while (!Worklist.empty()) { 452 SDNode *N = Worklist.back(); 453 Worklist.pop_back(); 454 455 // If we've already seen this node, ignore it. 456 if (!VisitedNodes.insert(N)) 457 continue; 458 459 // Otherwise, add all chain operands to the worklist. 460 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 461 if (N->getOperand(i).getValueType() == MVT::Other) 462 Worklist.push_back(N->getOperand(i).getNode()); 463 464 // If this is a CopyToReg with a vreg dest, process it. 465 if (N->getOpcode() != ISD::CopyToReg) 466 continue; 467 468 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 469 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 470 continue; 471 472 // Ignore non-scalar or non-integer values. 473 SDValue Src = N->getOperand(2); 474 EVT SrcVT = Src.getValueType(); 475 if (!SrcVT.isInteger() || SrcVT.isVector()) 476 continue; 477 478 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 479 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 480 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 481 482 // Only install this information if it tells us something. 483 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 484 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 485 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 486 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 487 FunctionLoweringInfo::LiveOutInfo &LOI = 488 FuncInfo->LiveOutRegInfo[DestReg]; 489 LOI.NumSignBits = NumSignBits; 490 LOI.KnownOne = KnownOne; 491 LOI.KnownZero = KnownZero; 492 } 493 } 494} 495 496void SelectionDAGISel::CodeGenAndEmitDAG() { 497 std::string GroupName; 498 if (TimePassesIsEnabled) 499 GroupName = "Instruction Selection and Scheduling"; 500 std::string BlockName; 501 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 502 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 503 ViewSUnitDAGs) 504 BlockName = MF->getFunction()->getNameStr() + ":" + 505 BB->getBasicBlock()->getNameStr(); 506 507 DEBUG(dbgs() << "Initial selection DAG:\n"); 508 DEBUG(CurDAG->dump()); 509 510 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 511 512 // Run the DAG combiner in pre-legalize mode. 513 if (TimePassesIsEnabled) { 514 NamedRegionTimer T("DAG Combining 1", GroupName); 515 CurDAG->Combine(Unrestricted, *AA, OptLevel); 516 } else { 517 CurDAG->Combine(Unrestricted, *AA, OptLevel); 518 } 519 520 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 521 DEBUG(CurDAG->dump()); 522 523 // Second step, hack on the DAG until it only uses operations and types that 524 // the target supports. 525 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 526 BlockName); 527 528 bool Changed; 529 if (TimePassesIsEnabled) { 530 NamedRegionTimer T("Type Legalization", GroupName); 531 Changed = CurDAG->LegalizeTypes(); 532 } else { 533 Changed = CurDAG->LegalizeTypes(); 534 } 535 536 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 537 DEBUG(CurDAG->dump()); 538 539 if (Changed) { 540 if (ViewDAGCombineLT) 541 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 542 543 // Run the DAG combiner in post-type-legalize mode. 544 if (TimePassesIsEnabled) { 545 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 546 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 547 } else { 548 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 549 } 550 551 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 552 DEBUG(CurDAG->dump()); 553 } 554 555 if (TimePassesIsEnabled) { 556 NamedRegionTimer T("Vector Legalization", GroupName); 557 Changed = CurDAG->LegalizeVectors(); 558 } else { 559 Changed = CurDAG->LegalizeVectors(); 560 } 561 562 if (Changed) { 563 if (TimePassesIsEnabled) { 564 NamedRegionTimer T("Type Legalization 2", GroupName); 565 CurDAG->LegalizeTypes(); 566 } else { 567 CurDAG->LegalizeTypes(); 568 } 569 570 if (ViewDAGCombineLT) 571 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 572 573 // Run the DAG combiner in post-type-legalize mode. 574 if (TimePassesIsEnabled) { 575 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 576 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 577 } else { 578 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 579 } 580 581 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 582 DEBUG(CurDAG->dump()); 583 } 584 585 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 586 587 if (TimePassesIsEnabled) { 588 NamedRegionTimer T("DAG Legalization", GroupName); 589 CurDAG->Legalize(OptLevel); 590 } else { 591 CurDAG->Legalize(OptLevel); 592 } 593 594 DEBUG(dbgs() << "Legalized selection DAG:\n"); 595 DEBUG(CurDAG->dump()); 596 597 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 598 599 // Run the DAG combiner in post-legalize mode. 600 if (TimePassesIsEnabled) { 601 NamedRegionTimer T("DAG Combining 2", GroupName); 602 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 603 } else { 604 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 605 } 606 607 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 608 DEBUG(CurDAG->dump()); 609 610 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 611 612 if (OptLevel != CodeGenOpt::None) 613 ComputeLiveOutVRegInfo(); 614 615 // Third, instruction select all of the operations to machine code, adding the 616 // code to the MachineBasicBlock. 617 if (TimePassesIsEnabled) { 618 NamedRegionTimer T("Instruction Selection", GroupName); 619 InstructionSelect(); 620 } else { 621 InstructionSelect(); 622 } 623 624 DEBUG(dbgs() << "Selected selection DAG:\n"); 625 DEBUG(CurDAG->dump()); 626 627 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 628 629 // Schedule machine code. 630 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 631 if (TimePassesIsEnabled) { 632 NamedRegionTimer T("Instruction Scheduling", GroupName); 633 Scheduler->Run(CurDAG, BB, BB->end()); 634 } else { 635 Scheduler->Run(CurDAG, BB, BB->end()); 636 } 637 638 if (ViewSUnitDAGs) Scheduler->viewGraph(); 639 640 // Emit machine code to BB. This can change 'BB' to the last block being 641 // inserted into. 642 if (TimePassesIsEnabled) { 643 NamedRegionTimer T("Instruction Creation", GroupName); 644 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 645 } else { 646 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 647 } 648 649 // Free the scheduler state. 650 if (TimePassesIsEnabled) { 651 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 652 delete Scheduler; 653 } else { 654 delete Scheduler; 655 } 656 657 DEBUG(dbgs() << "Selected machine code:\n"); 658 DEBUG(BB->dump()); 659} 660 661void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 662 MachineFunction &MF, 663 MachineModuleInfo *MMI, 664 DwarfWriter *DW, 665 const TargetInstrInfo &TII) { 666 // Initialize the Fast-ISel state, if needed. 667 FastISel *FastIS = 0; 668 if (EnableFastISel) 669 FastIS = TLI.createFastISel(MF, MMI, DW, 670 FuncInfo->ValueMap, 671 FuncInfo->MBBMap, 672 FuncInfo->StaticAllocaMap 673#ifndef NDEBUG 674 , FuncInfo->CatchInfoLost 675#endif 676 ); 677 678 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 679 680 // Iterate over all basic blocks in the function. 681 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 682 BasicBlock *LLVMBB = &*I; 683 BB = FuncInfo->MBBMap[LLVMBB]; 684 685 BasicBlock::iterator const Begin = LLVMBB->begin(); 686 BasicBlock::iterator const End = LLVMBB->end(); 687 BasicBlock::iterator BI = Begin; 688 689 // Lower any arguments needed in this block if this is the entry block. 690 bool SuppressFastISel = false; 691 if (LLVMBB == &Fn.getEntryBlock()) { 692 LowerArguments(LLVMBB); 693 694 // If any of the arguments has the byval attribute, forgo 695 // fast-isel in the entry block. 696 if (FastIS) { 697 unsigned j = 1; 698 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 699 I != E; ++I, ++j) 700 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 701 if (EnableFastISelVerbose || EnableFastISelAbort) 702 dbgs() << "FastISel skips entry block due to byval argument\n"; 703 SuppressFastISel = true; 704 break; 705 } 706 } 707 } 708 709 if (MMI && BB->isLandingPad()) { 710 // Add a label to mark the beginning of the landing pad. Deletion of the 711 // landing pad can thus be detected via the MachineModuleInfo. 712 unsigned LabelID = MMI->addLandingPad(BB); 713 714 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 715 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 716 717 // Mark exception register as live in. 718 unsigned Reg = TLI.getExceptionAddressRegister(); 719 if (Reg) BB->addLiveIn(Reg); 720 721 // Mark exception selector register as live in. 722 Reg = TLI.getExceptionSelectorRegister(); 723 if (Reg) BB->addLiveIn(Reg); 724 725 // FIXME: Hack around an exception handling flaw (PR1508): the personality 726 // function and list of typeids logically belong to the invoke (or, if you 727 // like, the basic block containing the invoke), and need to be associated 728 // with it in the dwarf exception handling tables. Currently however the 729 // information is provided by an intrinsic (eh.selector) that can be moved 730 // to unexpected places by the optimizers: if the unwind edge is critical, 731 // then breaking it can result in the intrinsics being in the successor of 732 // the landing pad, not the landing pad itself. This results in exceptions 733 // not being caught because no typeids are associated with the invoke. 734 // This may not be the only way things can go wrong, but it is the only way 735 // we try to work around for the moment. 736 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 737 738 if (Br && Br->isUnconditional()) { // Critical edge? 739 BasicBlock::iterator I, E; 740 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 741 if (isa<EHSelectorInst>(I)) 742 break; 743 744 if (I == E) 745 // No catch info found - try to extract some from the successor. 746 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 747 } 748 } 749 750 // Before doing SelectionDAG ISel, see if FastISel has been requested. 751 if (FastIS && !SuppressFastISel) { 752 // Emit code for any incoming arguments. This must happen before 753 // beginning FastISel on the entry block. 754 if (LLVMBB == &Fn.getEntryBlock()) { 755 CurDAG->setRoot(SDB->getControlRoot()); 756 CodeGenAndEmitDAG(); 757 SDB->clear(); 758 } 759 FastIS->startNewBlock(BB); 760 // Do FastISel on as many instructions as possible. 761 for (; BI != End; ++BI) { 762 // Just before the terminator instruction, insert instructions to 763 // feed PHI nodes in successor blocks. 764 if (isa<TerminatorInst>(BI)) 765 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 766 ResetDebugLoc(SDB, FastIS); 767 if (EnableFastISelVerbose || EnableFastISelAbort) { 768 dbgs() << "FastISel miss: "; 769 BI->dump(); 770 } 771 assert(!EnableFastISelAbort && 772 "FastISel didn't handle a PHI in a successor"); 773 break; 774 } 775 776 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 777 778 // First try normal tablegen-generated "fast" selection. 779 if (FastIS->SelectInstruction(BI)) { 780 ResetDebugLoc(SDB, FastIS); 781 continue; 782 } 783 784 // Clear out the debug location so that it doesn't carry over to 785 // unrelated instructions. 786 ResetDebugLoc(SDB, FastIS); 787 788 // Then handle certain instructions as single-LLVM-Instruction blocks. 789 if (isa<CallInst>(BI)) { 790 if (EnableFastISelVerbose || EnableFastISelAbort) { 791 dbgs() << "FastISel missed call: "; 792 BI->dump(); 793 } 794 795 if (BI->getType() != Type::getVoidTy(*CurDAG->getContext())) { 796 unsigned &R = FuncInfo->ValueMap[BI]; 797 if (!R) 798 R = FuncInfo->CreateRegForValue(BI); 799 } 800 801 bool HadTailCall = false; 802 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 803 804 // If the call was emitted as a tail call, we're done with the block. 805 if (HadTailCall) { 806 BI = End; 807 break; 808 } 809 810 // If the instruction was codegen'd with multiple blocks, 811 // inform the FastISel object where to resume inserting. 812 FastIS->setCurrentBlock(BB); 813 continue; 814 } 815 816 // Otherwise, give up on FastISel for the rest of the block. 817 // For now, be a little lenient about non-branch terminators. 818 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 819 if (EnableFastISelVerbose || EnableFastISelAbort) { 820 dbgs() << "FastISel miss: "; 821 BI->dump(); 822 } 823 if (EnableFastISelAbort) 824 // The "fast" selector couldn't handle something and bailed. 825 // For the purpose of debugging, just abort. 826 llvm_unreachable("FastISel didn't select the entire block"); 827 } 828 break; 829 } 830 } 831 832 // Run SelectionDAG instruction selection on the remainder of the block 833 // not handled by FastISel. If FastISel is not run, this is the entire 834 // block. 835 if (BI != End) { 836 bool HadTailCall; 837 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 838 } 839 840 FinishBasicBlock(); 841 } 842 843 delete FastIS; 844} 845 846void 847SelectionDAGISel::FinishBasicBlock() { 848 849 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 850 DEBUG(BB->dump()); 851 852 DEBUG(dbgs() << "Total amount of phi nodes to update: " 853 << SDB->PHINodesToUpdate.size() << "\n"); 854 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 855 dbgs() << "Node " << i << " : (" 856 << SDB->PHINodesToUpdate[i].first 857 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 858 859 // Next, now that we know what the last MBB the LLVM BB expanded is, update 860 // PHI nodes in successors. 861 if (SDB->SwitchCases.empty() && 862 SDB->JTCases.empty() && 863 SDB->BitTestCases.empty()) { 864 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 865 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 866 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 867 "This is not a machine PHI node that we are updating!"); 868 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 869 false)); 870 PHI->addOperand(MachineOperand::CreateMBB(BB)); 871 } 872 SDB->PHINodesToUpdate.clear(); 873 return; 874 } 875 876 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 877 // Lower header first, if it wasn't already lowered 878 if (!SDB->BitTestCases[i].Emitted) { 879 // Set the current basic block to the mbb we wish to insert the code into 880 BB = SDB->BitTestCases[i].Parent; 881 SDB->setCurrentBasicBlock(BB); 882 // Emit the code 883 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 884 CurDAG->setRoot(SDB->getRoot()); 885 CodeGenAndEmitDAG(); 886 SDB->clear(); 887 } 888 889 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 890 // Set the current basic block to the mbb we wish to insert the code into 891 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 892 SDB->setCurrentBasicBlock(BB); 893 // Emit the code 894 if (j+1 != ej) 895 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 896 SDB->BitTestCases[i].Reg, 897 SDB->BitTestCases[i].Cases[j]); 898 else 899 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 900 SDB->BitTestCases[i].Reg, 901 SDB->BitTestCases[i].Cases[j]); 902 903 904 CurDAG->setRoot(SDB->getRoot()); 905 CodeGenAndEmitDAG(); 906 SDB->clear(); 907 } 908 909 // Update PHI Nodes 910 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 911 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 912 MachineBasicBlock *PHIBB = PHI->getParent(); 913 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 914 "This is not a machine PHI node that we are updating!"); 915 // This is "default" BB. We have two jumps to it. From "header" BB and 916 // from last "case" BB. 917 if (PHIBB == SDB->BitTestCases[i].Default) { 918 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 919 false)); 920 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 921 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 922 false)); 923 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 924 back().ThisBB)); 925 } 926 // One of "cases" BB. 927 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 928 j != ej; ++j) { 929 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 930 if (cBB->succ_end() != 931 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 932 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 933 false)); 934 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 935 } 936 } 937 } 938 } 939 SDB->BitTestCases.clear(); 940 941 // If the JumpTable record is filled in, then we need to emit a jump table. 942 // Updating the PHI nodes is tricky in this case, since we need to determine 943 // whether the PHI is a successor of the range check MBB or the jump table MBB 944 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 945 // Lower header first, if it wasn't already lowered 946 if (!SDB->JTCases[i].first.Emitted) { 947 // Set the current basic block to the mbb we wish to insert the code into 948 BB = SDB->JTCases[i].first.HeaderBB; 949 SDB->setCurrentBasicBlock(BB); 950 // Emit the code 951 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 952 CurDAG->setRoot(SDB->getRoot()); 953 CodeGenAndEmitDAG(); 954 SDB->clear(); 955 } 956 957 // Set the current basic block to the mbb we wish to insert the code into 958 BB = SDB->JTCases[i].second.MBB; 959 SDB->setCurrentBasicBlock(BB); 960 // Emit the code 961 SDB->visitJumpTable(SDB->JTCases[i].second); 962 CurDAG->setRoot(SDB->getRoot()); 963 CodeGenAndEmitDAG(); 964 SDB->clear(); 965 966 // Update PHI Nodes 967 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 968 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 969 MachineBasicBlock *PHIBB = PHI->getParent(); 970 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 971 "This is not a machine PHI node that we are updating!"); 972 // "default" BB. We can go there only from header BB. 973 if (PHIBB == SDB->JTCases[i].second.Default) { 974 PHI->addOperand 975 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 976 PHI->addOperand 977 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 978 } 979 // JT BB. Just iterate over successors here 980 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 981 PHI->addOperand 982 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 983 PHI->addOperand(MachineOperand::CreateMBB(BB)); 984 } 985 } 986 } 987 SDB->JTCases.clear(); 988 989 // If the switch block involved a branch to one of the actual successors, we 990 // need to update PHI nodes in that block. 991 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 992 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 993 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 994 "This is not a machine PHI node that we are updating!"); 995 if (BB->isSuccessor(PHI->getParent())) { 996 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 997 false)); 998 PHI->addOperand(MachineOperand::CreateMBB(BB)); 999 } 1000 } 1001 1002 // If we generated any switch lowering information, build and codegen any 1003 // additional DAGs necessary. 1004 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1005 // Set the current basic block to the mbb we wish to insert the code into 1006 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1007 SDB->setCurrentBasicBlock(BB); 1008 1009 // Emit the code 1010 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1011 CurDAG->setRoot(SDB->getRoot()); 1012 CodeGenAndEmitDAG(); 1013 1014 // Handle any PHI nodes in successors of this chunk, as if we were coming 1015 // from the original BB before switch expansion. Note that PHI nodes can 1016 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1017 // handle them the right number of times. 1018 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1019 // If new BB's are created during scheduling, the edges may have been 1020 // updated. That is, the edge from ThisBB to BB may have been split and 1021 // BB's predecessor is now another block. 1022 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1023 SDB->EdgeMapping.find(BB); 1024 if (EI != SDB->EdgeMapping.end()) 1025 ThisBB = EI->second; 1026 for (MachineBasicBlock::iterator Phi = BB->begin(); 1027 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 1028 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 1029 for (unsigned pn = 0; ; ++pn) { 1030 assert(pn != SDB->PHINodesToUpdate.size() && 1031 "Didn't find PHI entry!"); 1032 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1033 Phi->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pn]. 1034 second, false)); 1035 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1036 break; 1037 } 1038 } 1039 } 1040 1041 // Don't process RHS if same block as LHS. 1042 if (BB == SDB->SwitchCases[i].FalseBB) 1043 SDB->SwitchCases[i].FalseBB = 0; 1044 1045 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1046 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1047 SDB->SwitchCases[i].FalseBB = 0; 1048 } 1049 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1050 SDB->clear(); 1051 } 1052 SDB->SwitchCases.clear(); 1053 1054 SDB->PHINodesToUpdate.clear(); 1055} 1056 1057 1058/// Create the scheduler. If a specific scheduler was specified 1059/// via the SchedulerRegistry, use it, otherwise select the 1060/// one preferred by the target. 1061/// 1062ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1063 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1064 1065 if (!Ctor) { 1066 Ctor = ISHeuristic; 1067 RegisterScheduler::setDefault(Ctor); 1068 } 1069 1070 return Ctor(this, OptLevel); 1071} 1072 1073ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1074 return new ScheduleHazardRecognizer(); 1075} 1076 1077//===----------------------------------------------------------------------===// 1078// Helper functions used by the generated instruction selector. 1079//===----------------------------------------------------------------------===// 1080// Calls to these methods are generated by tblgen. 1081 1082/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1083/// the dag combiner simplified the 255, we still want to match. RHS is the 1084/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1085/// specified in the .td file (e.g. 255). 1086bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1087 int64_t DesiredMaskS) const { 1088 const APInt &ActualMask = RHS->getAPIntValue(); 1089 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1090 1091 // If the actual mask exactly matches, success! 1092 if (ActualMask == DesiredMask) 1093 return true; 1094 1095 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1096 if (ActualMask.intersects(~DesiredMask)) 1097 return false; 1098 1099 // Otherwise, the DAG Combiner may have proven that the value coming in is 1100 // either already zero or is not demanded. Check for known zero input bits. 1101 APInt NeededMask = DesiredMask & ~ActualMask; 1102 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1103 return true; 1104 1105 // TODO: check to see if missing bits are just not demanded. 1106 1107 // Otherwise, this pattern doesn't match. 1108 return false; 1109} 1110 1111/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1112/// the dag combiner simplified the 255, we still want to match. RHS is the 1113/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1114/// specified in the .td file (e.g. 255). 1115bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1116 int64_t DesiredMaskS) const { 1117 const APInt &ActualMask = RHS->getAPIntValue(); 1118 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1119 1120 // If the actual mask exactly matches, success! 1121 if (ActualMask == DesiredMask) 1122 return true; 1123 1124 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1125 if (ActualMask.intersects(~DesiredMask)) 1126 return false; 1127 1128 // Otherwise, the DAG Combiner may have proven that the value coming in is 1129 // either already zero or is not demanded. Check for known zero input bits. 1130 APInt NeededMask = DesiredMask & ~ActualMask; 1131 1132 APInt KnownZero, KnownOne; 1133 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1134 1135 // If all the missing bits in the or are already known to be set, match! 1136 if ((NeededMask & KnownOne) == NeededMask) 1137 return true; 1138 1139 // TODO: check to see if missing bits are just not demanded. 1140 1141 // Otherwise, this pattern doesn't match. 1142 return false; 1143} 1144 1145 1146/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1147/// by tblgen. Others should not call it. 1148void SelectionDAGISel:: 1149SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1150 std::vector<SDValue> InOps; 1151 std::swap(InOps, Ops); 1152 1153 Ops.push_back(InOps[0]); // input chain. 1154 Ops.push_back(InOps[1]); // input asm string. 1155 1156 unsigned i = 2, e = InOps.size(); 1157 if (InOps[e-1].getValueType() == MVT::Flag) 1158 --e; // Don't process a flag operand if it is here. 1159 1160 while (i != e) { 1161 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1162 if ((Flags & 7) != 4 /*MEM*/) { 1163 // Just skip over this operand, copying the operands verbatim. 1164 Ops.insert(Ops.end(), InOps.begin()+i, 1165 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1166 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1167 } else { 1168 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1169 "Memory operand with multiple values?"); 1170 // Otherwise, this is a memory operand. Ask the target to select it. 1171 std::vector<SDValue> SelOps; 1172 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1173 llvm_report_error("Could not match memory address. Inline asm" 1174 " failure!"); 1175 } 1176 1177 // Add this to the output node. 1178 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1179 MVT::i32)); 1180 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1181 i += 2; 1182 } 1183 } 1184 1185 // Add the flag input back if present. 1186 if (e != InOps.size()) 1187 Ops.push_back(InOps.back()); 1188} 1189 1190/// findFlagUse - Return use of EVT::Flag value produced by the specified 1191/// SDNode. 1192/// 1193static SDNode *findFlagUse(SDNode *N) { 1194 unsigned FlagResNo = N->getNumValues()-1; 1195 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1196 SDUse &Use = I.getUse(); 1197 if (Use.getResNo() == FlagResNo) 1198 return Use.getUser(); 1199 } 1200 return NULL; 1201} 1202 1203/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1204/// This function recursively traverses up the operand chain, ignoring 1205/// certain nodes. 1206static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1207 SDNode *Root, 1208 SmallPtrSet<SDNode*, 16> &Visited) { 1209 if (Use->getNodeId() < Def->getNodeId() || 1210 !Visited.insert(Use)) 1211 return false; 1212 1213 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1214 SDNode *N = Use->getOperand(i).getNode(); 1215 if (N == Def) { 1216 if (Use == ImmedUse || Use == Root) 1217 continue; // We are not looking for immediate use. 1218 assert(N != Root); 1219 return true; 1220 } 1221 1222 // Traverse up the operand chain. 1223 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1224 return true; 1225 } 1226 return false; 1227} 1228 1229/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1230/// be reached. Return true if that's the case. However, ignore direct uses 1231/// by ImmedUse (which would be U in the example illustrated in 1232/// IsLegalAndProfitableToFold) and by Root (which can happen in the store 1233/// case). 1234/// FIXME: to be really generic, we should allow direct use by any node 1235/// that is being folded. But realisticly since we only fold loads which 1236/// have one non-chain use, we only need to watch out for load/op/store 1237/// and load/op/cmp case where the root (store / cmp) may reach the load via 1238/// its chain operand. 1239static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1240 SmallPtrSet<SDNode*, 16> Visited; 1241 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1242} 1243 1244/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 1245/// U can be folded during instruction selection that starts at Root and 1246/// folding N is profitable. 1247bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 1248 SDNode *Root) const { 1249 if (OptLevel == CodeGenOpt::None) return false; 1250 1251 // If Root use can somehow reach N through a path that that doesn't contain 1252 // U then folding N would create a cycle. e.g. In the following 1253 // diagram, Root can reach N through X. If N is folded into into Root, then 1254 // X is both a predecessor and a successor of U. 1255 // 1256 // [N*] // 1257 // ^ ^ // 1258 // / \ // 1259 // [U*] [X]? // 1260 // ^ ^ // 1261 // \ / // 1262 // \ / // 1263 // [Root*] // 1264 // 1265 // * indicates nodes to be folded together. 1266 // 1267 // If Root produces a flag, then it gets (even more) interesting. Since it 1268 // will be "glued" together with its flag use in the scheduler, we need to 1269 // check if it might reach N. 1270 // 1271 // [N*] // 1272 // ^ ^ // 1273 // / \ // 1274 // [U*] [X]? // 1275 // ^ ^ // 1276 // \ \ // 1277 // \ | // 1278 // [Root*] | // 1279 // ^ | // 1280 // f | // 1281 // | / // 1282 // [Y] / // 1283 // ^ / // 1284 // f / // 1285 // | / // 1286 // [FU] // 1287 // 1288 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1289 // (call it Fold), then X is a predecessor of FU and a successor of 1290 // Fold. But since Fold and FU are flagged together, this will create 1291 // a cycle in the scheduling graph. 1292 1293 EVT VT = Root->getValueType(Root->getNumValues()-1); 1294 while (VT == MVT::Flag) { 1295 SDNode *FU = findFlagUse(Root); 1296 if (FU == NULL) 1297 break; 1298 Root = FU; 1299 VT = Root->getValueType(Root->getNumValues()-1); 1300 } 1301 1302 return !isNonImmUse(Root, N, U); 1303} 1304 1305SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1306 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1307 SelectInlineAsmMemoryOperands(Ops); 1308 1309 std::vector<EVT> VTs; 1310 VTs.push_back(MVT::Other); 1311 VTs.push_back(MVT::Flag); 1312 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1313 VTs, &Ops[0], Ops.size()); 1314 return New.getNode(); 1315} 1316 1317SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1318 return CurDAG->SelectNodeTo(N, TargetInstrInfo::IMPLICIT_DEF, 1319 N->getValueType(0)); 1320} 1321 1322SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1323 SDValue Chain = N->getOperand(0); 1324 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1325 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1326 return CurDAG->SelectNodeTo(N, TargetInstrInfo::EH_LABEL, 1327 MVT::Other, Tmp, Chain); 1328} 1329 1330void SelectionDAGISel::CannotYetSelect(SDNode *N) { 1331 std::string msg; 1332 raw_string_ostream Msg(msg); 1333 Msg << "Cannot yet select: "; 1334 N->print(Msg, CurDAG); 1335 llvm_report_error(Msg.str()); 1336} 1337 1338void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) { 1339 dbgs() << "Cannot yet select: "; 1340 unsigned iid = 1341 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == MVT::Other))->getZExtValue(); 1342 if (iid < Intrinsic::num_intrinsics) 1343 llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid)); 1344 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 1345 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 1346 tii->getName(iid)); 1347} 1348 1349char SelectionDAGISel::ID = 0; 1350