SelectionDAGISel.cpp revision a2b56692c8b824b8cc4a0927bb555f3718e9bee8
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/TargetTransformInfo.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/FunctionLoweringInfo.h" 25#include "llvm/CodeGen/GCMetadata.h" 26#include "llvm/CodeGen/GCStrategy.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/Constants.h" 37#include "llvm/IR/Function.h" 38#include "llvm/IR/InlineAsm.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/IntrinsicInst.h" 41#include "llvm/IR/Intrinsics.h" 42#include "llvm/IR/LLVMContext.h" 43#include "llvm/IR/Module.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLibraryInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "llvm/Target/TargetOptions.h" 55#include "llvm/Target/TargetRegisterInfo.h" 56#include "llvm/Target/TargetSubtargetInfo.h" 57#include "llvm/Transforms/Utils/BasicBlockUtils.h" 58#include <algorithm> 59using namespace llvm; 60 61STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 62STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 63STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 64STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 65STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 67STATISTIC(NumFastIselFailLowerArguments, 68 "Number of entry blocks where fast isel failed to lower arguments"); 69 70#ifndef NDEBUG 71static cl::opt<bool> 72EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 73 cl::desc("Enable extra verbose messages in the \"fast\" " 74 "instruction selector")); 75 76 // Terminators 77STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 78STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 79STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 80STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 81STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 82STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 83STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 84 85 // Standard binary operators... 86STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 87STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 88STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 89STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 90STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 91STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 92STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 93STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 94STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 95STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 96STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 97STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 98 99 // Logical operators... 100STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 101STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 102STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 103 104 // Memory instructions... 105STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 106STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 107STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 108STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 109STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 110STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 111STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 112 113 // Convert instructions... 114STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 115STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 116STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 117STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 118STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 119STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 120STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 121STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 122STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 123STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 124STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 125STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 126 127 // Other instructions... 128STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 129STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 130STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 131STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 132STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 133STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 134STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 135STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 136STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 137STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 138STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 139STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 140STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 141STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 142STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 143#endif 144 145static cl::opt<bool> 146EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 147 cl::desc("Enable verbose messages in the \"fast\" " 148 "instruction selector")); 149static cl::opt<bool> 150EnableFastISelAbort("fast-isel-abort", cl::Hidden, 151 cl::desc("Enable abort calls when \"fast\" instruction selection " 152 "fails to lower an instruction")); 153static cl::opt<bool> 154EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 155 cl::desc("Enable abort calls when \"fast\" instruction selection " 156 "fails to lower a formal argument")); 157 158static cl::opt<bool> 159UseMBPI("use-mbpi", 160 cl::desc("use Machine Branch Probability Info"), 161 cl::init(true), cl::Hidden); 162 163#ifndef NDEBUG 164static cl::opt<bool> 165ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 166 cl::desc("Pop up a window to show dags before the first " 167 "dag combine pass")); 168static cl::opt<bool> 169ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 170 cl::desc("Pop up a window to show dags before legalize types")); 171static cl::opt<bool> 172ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 173 cl::desc("Pop up a window to show dags before legalize")); 174static cl::opt<bool> 175ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 176 cl::desc("Pop up a window to show dags before the second " 177 "dag combine pass")); 178static cl::opt<bool> 179ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 180 cl::desc("Pop up a window to show dags before the post legalize types" 181 " dag combine pass")); 182static cl::opt<bool> 183ViewISelDAGs("view-isel-dags", cl::Hidden, 184 cl::desc("Pop up a window to show isel dags as they are selected")); 185static cl::opt<bool> 186ViewSchedDAGs("view-sched-dags", cl::Hidden, 187 cl::desc("Pop up a window to show sched dags as they are processed")); 188static cl::opt<bool> 189ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 190 cl::desc("Pop up a window to show SUnit dags after they are processed")); 191#else 192static const bool ViewDAGCombine1 = false, 193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 194 ViewDAGCombine2 = false, 195 ViewDAGCombineLT = false, 196 ViewISelDAGs = false, ViewSchedDAGs = false, 197 ViewSUnitDAGs = false; 198#endif 199 200//===---------------------------------------------------------------------===// 201/// 202/// RegisterScheduler class - Track the registration of instruction schedulers. 203/// 204//===---------------------------------------------------------------------===// 205MachinePassRegistry RegisterScheduler::Registry; 206 207//===---------------------------------------------------------------------===// 208/// 209/// ISHeuristic command line option for instruction schedulers. 210/// 211//===---------------------------------------------------------------------===// 212static cl::opt<RegisterScheduler::FunctionPassCtor, false, 213 RegisterPassParser<RegisterScheduler> > 214ISHeuristic("pre-RA-sched", 215 cl::init(&createDefaultScheduler), 216 cl::desc("Instruction schedulers available (before register" 217 " allocation):")); 218 219static RegisterScheduler 220defaultListDAGScheduler("default", "Best scheduler for the target", 221 createDefaultScheduler); 222 223namespace llvm { 224 //===--------------------------------------------------------------------===// 225 /// createDefaultScheduler - This creates an instruction scheduler appropriate 226 /// for the target. 227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 228 CodeGenOpt::Level OptLevel) { 229 const TargetLowering &TLI = IS->getTargetLowering(); 230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 231 232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 233 TLI.getSchedulingPreference() == Sched::Source) 234 return createSourceListDAGScheduler(IS, OptLevel); 235 if (TLI.getSchedulingPreference() == Sched::RegPressure) 236 return createBURRListDAGScheduler(IS, OptLevel); 237 if (TLI.getSchedulingPreference() == Sched::Hybrid) 238 return createHybridListDAGScheduler(IS, OptLevel); 239 if (TLI.getSchedulingPreference() == Sched::VLIW) 240 return createVLIWDAGScheduler(IS, OptLevel); 241 assert(TLI.getSchedulingPreference() == Sched::ILP && 242 "Unknown sched type!"); 243 return createILPListDAGScheduler(IS, OptLevel); 244 } 245} 246 247// EmitInstrWithCustomInserter - This method should be implemented by targets 248// that mark instructions with the 'usesCustomInserter' flag. These 249// instructions are special in various ways, which require special support to 250// insert. The specified MachineInstr is created but not inserted into any 251// basic blocks, and this method is called to expand it into a sequence of 252// instructions, potentially also creating new basic blocks and control flow. 253// When new basic blocks are inserted and the edges from MBB to its successors 254// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 255// DenseMap. 256MachineBasicBlock * 257TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 258 MachineBasicBlock *MBB) const { 259#ifndef NDEBUG 260 dbgs() << "If a target marks an instruction with " 261 "'usesCustomInserter', it must implement " 262 "TargetLowering::EmitInstrWithCustomInserter!"; 263#endif 264 llvm_unreachable(0); 265} 266 267void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 268 SDNode *Node) const { 269 assert(!MI->hasPostISelHook() && 270 "If a target marks an instruction with 'hasPostISelHook', " 271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 272} 273 274//===----------------------------------------------------------------------===// 275// SelectionDAGISel code 276//===----------------------------------------------------------------------===// 277 278SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 279 CodeGenOpt::Level OL) : 280 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 281 FuncInfo(new FunctionLoweringInfo(TLI)), 282 CurDAG(new SelectionDAG(tm, OL)), 283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 284 GFI(), 285 OptLevel(OL), 286 DAGSize(0) { 287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 291 } 292 293SelectionDAGISel::~SelectionDAGISel() { 294 delete SDB; 295 delete CurDAG; 296 delete FuncInfo; 297} 298 299void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 300 AU.addRequired<AliasAnalysis>(); 301 AU.addPreserved<AliasAnalysis>(); 302 AU.addRequired<GCModuleInfo>(); 303 AU.addPreserved<GCModuleInfo>(); 304 AU.addRequired<TargetLibraryInfo>(); 305 if (UseMBPI && OptLevel != CodeGenOpt::None) 306 AU.addRequired<BranchProbabilityInfo>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 311/// may trap on it. In this case we have to split the edge so that the path 312/// through the predecessor block that doesn't go to the phi block doesn't 313/// execute the possibly trapping instruction. 314/// 315/// This is required for correctness, so it must be done at -O0. 316/// 317static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 318 // Loop for blocks with phi nodes. 319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 320 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 321 if (PN == 0) continue; 322 323 ReprocessBlock: 324 // For each block with a PHI node, check to see if any of the input values 325 // are potentially trapping constant expressions. Constant expressions are 326 // the only potentially trapping value that can occur as the argument to a 327 // PHI. 328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 331 if (CE == 0 || !CE->canTrap()) continue; 332 333 // The only case we have to worry about is when the edge is critical. 334 // Since this block has a PHI Node, we assume it has multiple input 335 // edges: check to see if the pred has multiple successors. 336 BasicBlock *Pred = PN->getIncomingBlock(i); 337 if (Pred->getTerminator()->getNumSuccessors() == 1) 338 continue; 339 340 // Okay, we have to split this edge. 341 SplitCriticalEdge(Pred->getTerminator(), 342 GetSuccessorNumber(Pred, BB), SDISel, true); 343 goto ReprocessBlock; 344 } 345 } 346} 347 348bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 349 // Do some sanity-checking on the command-line options. 350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 351 "-fast-isel-verbose requires -fast-isel"); 352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 353 "-fast-isel-abort requires -fast-isel"); 354 355 const Function &Fn = *mf.getFunction(); 356 const TargetInstrInfo &TII = *TM.getInstrInfo(); 357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 358 359 MF = &mf; 360 RegInfo = &MF->getRegInfo(); 361 AA = &getAnalysis<AliasAnalysis>(); 362 LibInfo = &getAnalysis<TargetLibraryInfo>(); 363 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 365 366 TargetSubtargetInfo &ST = 367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 368 ST.resetSubtargetFeatures(MF); 369 TM.resetTargetOptions(MF); 370 371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 372 373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 374 375 CurDAG->init(*MF, TTI); 376 FuncInfo->set(Fn, *MF); 377 378 if (UseMBPI && OptLevel != CodeGenOpt::None) 379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 380 else 381 FuncInfo->BPI = 0; 382 383 SDB->init(GFI, *AA, LibInfo); 384 385 MF->setHasMSInlineAsm(false); 386 SelectAllBasicBlocks(Fn); 387 388 // If the first basic block in the function has live ins that need to be 389 // copied into vregs, emit the copies into the top of the block before 390 // emitting the code for the block. 391 MachineBasicBlock *EntryMBB = MF->begin(); 392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 393 394 DenseMap<unsigned, unsigned> LiveInMap; 395 if (!FuncInfo->ArgDbgValues.empty()) 396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 397 E = RegInfo->livein_end(); LI != E; ++LI) 398 if (LI->second) 399 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 400 401 // Insert DBG_VALUE instructions for function arguments to the entry block. 402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 404 unsigned Reg = MI->getOperand(0).getReg(); 405 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 406 EntryMBB->insert(EntryMBB->begin(), MI); 407 else { 408 MachineInstr *Def = RegInfo->getVRegDef(Reg); 409 MachineBasicBlock::iterator InsertPos = Def; 410 // FIXME: VR def may not be in entry block. 411 Def->getParent()->insert(llvm::next(InsertPos), MI); 412 } 413 414 // If Reg is live-in then update debug info to track its copy in a vreg. 415 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 416 if (LDI != LiveInMap.end()) { 417 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 418 MachineBasicBlock::iterator InsertPos = Def; 419 const MDNode *Variable = 420 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 421 unsigned Offset = 0; 422 if (MI->getOperand(1).isImm()) 423 Offset = MI->getOperand(1).getImm(); 424 // Def is never a terminator here, so it is ok to increment InsertPos. 425 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 426 TII.get(TargetOpcode::DBG_VALUE), 427 MI->getOperand(1).isReg(), 428 LDI->second, Offset, Variable); 429 430 // If this vreg is directly copied into an exported register then 431 // that COPY instructions also need DBG_VALUE, if it is the only 432 // user of LDI->second. 433 MachineInstr *CopyUseMI = NULL; 434 for (MachineRegisterInfo::use_iterator 435 UI = RegInfo->use_begin(LDI->second); 436 MachineInstr *UseMI = UI.skipInstruction();) { 437 if (UseMI->isDebugValue()) continue; 438 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 439 CopyUseMI = UseMI; continue; 440 } 441 // Otherwise this is another use or second copy use. 442 CopyUseMI = NULL; break; 443 } 444 if (CopyUseMI) { 445 MachineInstr *NewMI = 446 BuildMI(*MF, CopyUseMI->getDebugLoc(), 447 TII.get(TargetOpcode::DBG_VALUE), 448 Offset!=0, 449 CopyUseMI->getOperand(0).getReg(), 450 Offset, Variable); 451 MachineBasicBlock::iterator Pos = CopyUseMI; 452 EntryMBB->insertAfter(Pos, NewMI); 453 } 454 } 455 } 456 457 // Determine if there are any calls in this machine function. 458 MachineFrameInfo *MFI = MF->getFrameInfo(); 459 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 460 ++I) { 461 462 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 463 break; 464 465 const MachineBasicBlock *MBB = I; 466 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 467 II != IE; ++II) { 468 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 469 if ((MCID.isCall() && !MCID.isReturn()) || 470 II->isStackAligningInlineAsm()) { 471 MFI->setHasCalls(true); 472 } 473 if (II->isMSInlineAsm()) { 474 MF->setHasMSInlineAsm(true); 475 } 476 } 477 } 478 479 // Determine if there is a call to setjmp in the machine function. 480 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 481 482 // Replace forward-declared registers with the registers containing 483 // the desired value. 484 MachineRegisterInfo &MRI = MF->getRegInfo(); 485 for (DenseMap<unsigned, unsigned>::iterator 486 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 487 I != E; ++I) { 488 unsigned From = I->first; 489 unsigned To = I->second; 490 // If To is also scheduled to be replaced, find what its ultimate 491 // replacement is. 492 for (;;) { 493 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 494 if (J == E) break; 495 To = J->second; 496 } 497 // Replace it. 498 MRI.replaceRegWith(From, To); 499 } 500 501 // Freeze the set of reserved registers now that MachineFrameInfo has been 502 // set up. All the information required by getReservedRegs() should be 503 // available now. 504 MRI.freezeReservedRegs(*MF); 505 506 // Release function-specific state. SDB and CurDAG are already cleared 507 // at this point. 508 FuncInfo->clear(); 509 510 return true; 511} 512 513void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 514 BasicBlock::const_iterator End, 515 bool &HadTailCall) { 516 // Lower all of the non-terminator instructions. If a call is emitted 517 // as a tail call, cease emitting nodes for this block. Terminators 518 // are handled below. 519 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 520 SDB->visit(*I); 521 522 // Make sure the root of the DAG is up-to-date. 523 CurDAG->setRoot(SDB->getControlRoot()); 524 HadTailCall = SDB->HasTailCall; 525 SDB->clear(); 526 527 // Final step, emit the lowered DAG as machine code. 528 CodeGenAndEmitDAG(); 529} 530 531void SelectionDAGISel::ComputeLiveOutVRegInfo() { 532 SmallPtrSet<SDNode*, 128> VisitedNodes; 533 SmallVector<SDNode*, 128> Worklist; 534 535 Worklist.push_back(CurDAG->getRoot().getNode()); 536 537 APInt KnownZero; 538 APInt KnownOne; 539 540 do { 541 SDNode *N = Worklist.pop_back_val(); 542 543 // If we've already seen this node, ignore it. 544 if (!VisitedNodes.insert(N)) 545 continue; 546 547 // Otherwise, add all chain operands to the worklist. 548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 549 if (N->getOperand(i).getValueType() == MVT::Other) 550 Worklist.push_back(N->getOperand(i).getNode()); 551 552 // If this is a CopyToReg with a vreg dest, process it. 553 if (N->getOpcode() != ISD::CopyToReg) 554 continue; 555 556 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 557 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 558 continue; 559 560 // Ignore non-scalar or non-integer values. 561 SDValue Src = N->getOperand(2); 562 EVT SrcVT = Src.getValueType(); 563 if (!SrcVT.isInteger() || SrcVT.isVector()) 564 continue; 565 566 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 567 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 568 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 569 } while (!Worklist.empty()); 570} 571 572void SelectionDAGISel::CodeGenAndEmitDAG() { 573 std::string GroupName; 574 if (TimePassesIsEnabled) 575 GroupName = "Instruction Selection and Scheduling"; 576 std::string BlockName; 577 int BlockNumber = -1; 578 (void)BlockNumber; 579#ifdef NDEBUG 580 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 581 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 582 ViewSUnitDAGs) 583#endif 584 { 585 BlockNumber = FuncInfo->MBB->getNumber(); 586 BlockName = MF->getName().str() + ":" + 587 FuncInfo->MBB->getBasicBlock()->getName().str(); 588 } 589 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 590 << " '" << BlockName << "'\n"; CurDAG->dump()); 591 592 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 593 594 // Run the DAG combiner in pre-legalize mode. 595 { 596 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 597 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 598 } 599 600 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 601 << " '" << BlockName << "'\n"; CurDAG->dump()); 602 603 // Second step, hack on the DAG until it only uses operations and types that 604 // the target supports. 605 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 606 BlockName); 607 608 bool Changed; 609 { 610 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 611 Changed = CurDAG->LegalizeTypes(); 612 } 613 614 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 615 << " '" << BlockName << "'\n"; CurDAG->dump()); 616 617 if (Changed) { 618 if (ViewDAGCombineLT) 619 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 620 621 // Run the DAG combiner in post-type-legalize mode. 622 { 623 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 624 TimePassesIsEnabled); 625 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 626 } 627 628 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 629 << " '" << BlockName << "'\n"; CurDAG->dump()); 630 } 631 632 { 633 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 634 Changed = CurDAG->LegalizeVectors(); 635 } 636 637 if (Changed) { 638 { 639 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 640 CurDAG->LegalizeTypes(); 641 } 642 643 if (ViewDAGCombineLT) 644 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 645 646 // Run the DAG combiner in post-type-legalize mode. 647 { 648 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 649 TimePassesIsEnabled); 650 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 651 } 652 653 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 654 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 655 } 656 657 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 658 659 { 660 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 661 CurDAG->Legalize(); 662 } 663 664 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 665 << " '" << BlockName << "'\n"; CurDAG->dump()); 666 667 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 668 669 // Run the DAG combiner in post-legalize mode. 670 { 671 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 672 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 673 } 674 675 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 676 << " '" << BlockName << "'\n"; CurDAG->dump()); 677 678 if (OptLevel != CodeGenOpt::None) 679 ComputeLiveOutVRegInfo(); 680 681 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 682 683 // Third, instruction select all of the operations to machine code, adding the 684 // code to the MachineBasicBlock. 685 { 686 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 687 DoInstructionSelection(); 688 } 689 690 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 691 << " '" << BlockName << "'\n"; CurDAG->dump()); 692 693 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 694 695 // Schedule machine code. 696 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 697 { 698 NamedRegionTimer T("Instruction Scheduling", GroupName, 699 TimePassesIsEnabled); 700 Scheduler->Run(CurDAG, FuncInfo->MBB); 701 } 702 703 if (ViewSUnitDAGs) Scheduler->viewGraph(); 704 705 // Emit machine code to BB. This can change 'BB' to the last block being 706 // inserted into. 707 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 708 { 709 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 710 711 // FuncInfo->InsertPt is passed by reference and set to the end of the 712 // scheduled instructions. 713 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 714 } 715 716 // If the block was split, make sure we update any references that are used to 717 // update PHI nodes later on. 718 if (FirstMBB != LastMBB) 719 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 720 721 // Free the scheduler state. 722 { 723 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 724 TimePassesIsEnabled); 725 delete Scheduler; 726 } 727 728 // Free the SelectionDAG state, now that we're finished with it. 729 CurDAG->clear(); 730} 731 732namespace { 733/// ISelUpdater - helper class to handle updates of the instruction selection 734/// graph. 735class ISelUpdater : public SelectionDAG::DAGUpdateListener { 736 SelectionDAG::allnodes_iterator &ISelPosition; 737public: 738 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 739 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 740 741 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 742 /// deleted is the current ISelPosition node, update ISelPosition. 743 /// 744 virtual void NodeDeleted(SDNode *N, SDNode *E) { 745 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 746 ++ISelPosition; 747 } 748}; 749} // end anonymous namespace 750 751void SelectionDAGISel::DoInstructionSelection() { 752 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 753 << FuncInfo->MBB->getNumber() 754 << " '" << FuncInfo->MBB->getName() << "'\n"); 755 756 PreprocessISelDAG(); 757 758 // Select target instructions for the DAG. 759 { 760 // Number all nodes with a topological order and set DAGSize. 761 DAGSize = CurDAG->AssignTopologicalOrder(); 762 763 // Create a dummy node (which is not added to allnodes), that adds 764 // a reference to the root node, preventing it from being deleted, 765 // and tracking any changes of the root. 766 HandleSDNode Dummy(CurDAG->getRoot()); 767 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 768 ++ISelPosition; 769 770 // Make sure that ISelPosition gets properly updated when nodes are deleted 771 // in calls made from this function. 772 ISelUpdater ISU(*CurDAG, ISelPosition); 773 774 // The AllNodes list is now topological-sorted. Visit the 775 // nodes by starting at the end of the list (the root of the 776 // graph) and preceding back toward the beginning (the entry 777 // node). 778 while (ISelPosition != CurDAG->allnodes_begin()) { 779 SDNode *Node = --ISelPosition; 780 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 781 // but there are currently some corner cases that it misses. Also, this 782 // makes it theoretically possible to disable the DAGCombiner. 783 if (Node->use_empty()) 784 continue; 785 786 SDNode *ResNode = Select(Node); 787 788 // FIXME: This is pretty gross. 'Select' should be changed to not return 789 // anything at all and this code should be nuked with a tactical strike. 790 791 // If node should not be replaced, continue with the next one. 792 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 793 continue; 794 // Replace node. 795 if (ResNode) { 796 // Propagate ordering 797 CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node)); 798 799 ReplaceUses(Node, ResNode); 800 } 801 802 // If after the replacement this node is not used any more, 803 // remove this dead node. 804 if (Node->use_empty()) // Don't delete EntryToken, etc. 805 CurDAG->RemoveDeadNode(Node); 806 } 807 808 CurDAG->setRoot(Dummy.getValue()); 809 } 810 811 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 812 813 PostprocessISelDAG(); 814} 815 816/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 817/// do other setup for EH landing-pad blocks. 818void SelectionDAGISel::PrepareEHLandingPad() { 819 MachineBasicBlock *MBB = FuncInfo->MBB; 820 821 // Add a label to mark the beginning of the landing pad. Deletion of the 822 // landing pad can thus be detected via the MachineModuleInfo. 823 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 824 825 // Assign the call site to the landing pad's begin label. 826 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 827 828 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 829 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 830 .addSym(Label); 831 832 // Mark exception register as live in. 833 unsigned Reg = TLI.getExceptionPointerRegister(); 834 if (Reg) MBB->addLiveIn(Reg); 835 836 // Mark exception selector register as live in. 837 Reg = TLI.getExceptionSelectorRegister(); 838 if (Reg) MBB->addLiveIn(Reg); 839} 840 841/// isFoldedOrDeadInstruction - Return true if the specified instruction is 842/// side-effect free and is either dead or folded into a generated instruction. 843/// Return false if it needs to be emitted. 844static bool isFoldedOrDeadInstruction(const Instruction *I, 845 FunctionLoweringInfo *FuncInfo) { 846 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 847 !isa<TerminatorInst>(I) && // Terminators aren't folded. 848 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 849 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 850 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 851} 852 853#ifndef NDEBUG 854// Collect per Instruction statistics for fast-isel misses. Only those 855// instructions that cause the bail are accounted for. It does not account for 856// instructions higher in the block. Thus, summing the per instructions stats 857// will not add up to what is reported by NumFastIselFailures. 858static void collectFailStats(const Instruction *I) { 859 switch (I->getOpcode()) { 860 default: assert (0 && "<Invalid operator> "); 861 862 // Terminators 863 case Instruction::Ret: NumFastIselFailRet++; return; 864 case Instruction::Br: NumFastIselFailBr++; return; 865 case Instruction::Switch: NumFastIselFailSwitch++; return; 866 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 867 case Instruction::Invoke: NumFastIselFailInvoke++; return; 868 case Instruction::Resume: NumFastIselFailResume++; return; 869 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 870 871 // Standard binary operators... 872 case Instruction::Add: NumFastIselFailAdd++; return; 873 case Instruction::FAdd: NumFastIselFailFAdd++; return; 874 case Instruction::Sub: NumFastIselFailSub++; return; 875 case Instruction::FSub: NumFastIselFailFSub++; return; 876 case Instruction::Mul: NumFastIselFailMul++; return; 877 case Instruction::FMul: NumFastIselFailFMul++; return; 878 case Instruction::UDiv: NumFastIselFailUDiv++; return; 879 case Instruction::SDiv: NumFastIselFailSDiv++; return; 880 case Instruction::FDiv: NumFastIselFailFDiv++; return; 881 case Instruction::URem: NumFastIselFailURem++; return; 882 case Instruction::SRem: NumFastIselFailSRem++; return; 883 case Instruction::FRem: NumFastIselFailFRem++; return; 884 885 // Logical operators... 886 case Instruction::And: NumFastIselFailAnd++; return; 887 case Instruction::Or: NumFastIselFailOr++; return; 888 case Instruction::Xor: NumFastIselFailXor++; return; 889 890 // Memory instructions... 891 case Instruction::Alloca: NumFastIselFailAlloca++; return; 892 case Instruction::Load: NumFastIselFailLoad++; return; 893 case Instruction::Store: NumFastIselFailStore++; return; 894 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 895 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 896 case Instruction::Fence: NumFastIselFailFence++; return; 897 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 898 899 // Convert instructions... 900 case Instruction::Trunc: NumFastIselFailTrunc++; return; 901 case Instruction::ZExt: NumFastIselFailZExt++; return; 902 case Instruction::SExt: NumFastIselFailSExt++; return; 903 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 904 case Instruction::FPExt: NumFastIselFailFPExt++; return; 905 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 906 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 907 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 908 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 909 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 910 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 911 case Instruction::BitCast: NumFastIselFailBitCast++; return; 912 913 // Other instructions... 914 case Instruction::ICmp: NumFastIselFailICmp++; return; 915 case Instruction::FCmp: NumFastIselFailFCmp++; return; 916 case Instruction::PHI: NumFastIselFailPHI++; return; 917 case Instruction::Select: NumFastIselFailSelect++; return; 918 case Instruction::Call: NumFastIselFailCall++; return; 919 case Instruction::Shl: NumFastIselFailShl++; return; 920 case Instruction::LShr: NumFastIselFailLShr++; return; 921 case Instruction::AShr: NumFastIselFailAShr++; return; 922 case Instruction::VAArg: NumFastIselFailVAArg++; return; 923 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 924 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 925 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 926 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 927 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 928 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 929 } 930} 931#endif 932 933void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 934 // Initialize the Fast-ISel state, if needed. 935 FastISel *FastIS = 0; 936 if (TM.Options.EnableFastISel) 937 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 938 939 // Iterate over all basic blocks in the function. 940 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 941 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 942 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 943 const BasicBlock *LLVMBB = *I; 944 945 if (OptLevel != CodeGenOpt::None) { 946 bool AllPredsVisited = true; 947 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 948 PI != PE; ++PI) { 949 if (!FuncInfo->VisitedBBs.count(*PI)) { 950 AllPredsVisited = false; 951 break; 952 } 953 } 954 955 if (AllPredsVisited) { 956 for (BasicBlock::const_iterator I = LLVMBB->begin(); 957 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 958 FuncInfo->ComputePHILiveOutRegInfo(PN); 959 } else { 960 for (BasicBlock::const_iterator I = LLVMBB->begin(); 961 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 962 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 963 } 964 965 FuncInfo->VisitedBBs.insert(LLVMBB); 966 } 967 968 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 969 BasicBlock::const_iterator const End = LLVMBB->end(); 970 BasicBlock::const_iterator BI = End; 971 972 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 973 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 974 975 // Setup an EH landing-pad block. 976 if (FuncInfo->MBB->isLandingPad()) 977 PrepareEHLandingPad(); 978 979 // Before doing SelectionDAG ISel, see if FastISel has been requested. 980 if (FastIS) { 981 FastIS->startNewBlock(); 982 983 // Emit code for any incoming arguments. This must happen before 984 // beginning FastISel on the entry block. 985 if (LLVMBB == &Fn.getEntryBlock()) { 986 ++NumEntryBlocks; 987 988 // Lower any arguments needed in this block if this is the entry block. 989 if (!FastIS->LowerArguments()) { 990 // Fast isel failed to lower these arguments 991 ++NumFastIselFailLowerArguments; 992 if (EnableFastISelAbortArgs) 993 llvm_unreachable("FastISel didn't lower all arguments"); 994 995 // Use SelectionDAG argument lowering 996 LowerArguments(Fn); 997 CurDAG->setRoot(SDB->getControlRoot()); 998 SDB->clear(); 999 CodeGenAndEmitDAG(); 1000 } 1001 1002 // If we inserted any instructions at the beginning, make a note of 1003 // where they are, so we can be sure to emit subsequent instructions 1004 // after them. 1005 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1006 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1007 else 1008 FastIS->setLastLocalValue(0); 1009 } 1010 1011 unsigned NumFastIselRemaining = std::distance(Begin, End); 1012 // Do FastISel on as many instructions as possible. 1013 for (; BI != Begin; --BI) { 1014 const Instruction *Inst = llvm::prior(BI); 1015 1016 // If we no longer require this instruction, skip it. 1017 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1018 --NumFastIselRemaining; 1019 continue; 1020 } 1021 1022 // Bottom-up: reset the insert pos at the top, after any local-value 1023 // instructions. 1024 FastIS->recomputeInsertPt(); 1025 1026 // Try to select the instruction with FastISel. 1027 if (FastIS->SelectInstruction(Inst)) { 1028 --NumFastIselRemaining; 1029 ++NumFastIselSuccess; 1030 // If fast isel succeeded, skip over all the folded instructions, and 1031 // then see if there is a load right before the selected instructions. 1032 // Try to fold the load if so. 1033 const Instruction *BeforeInst = Inst; 1034 while (BeforeInst != Begin) { 1035 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1036 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1037 break; 1038 } 1039 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1040 BeforeInst->hasOneUse() && 1041 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1042 // If we succeeded, don't re-select the load. 1043 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1044 --NumFastIselRemaining; 1045 ++NumFastIselSuccess; 1046 } 1047 continue; 1048 } 1049 1050#ifndef NDEBUG 1051 if (EnableFastISelVerbose2) 1052 collectFailStats(Inst); 1053#endif 1054 1055 // Then handle certain instructions as single-LLVM-Instruction blocks. 1056 if (isa<CallInst>(Inst)) { 1057 1058 if (EnableFastISelVerbose || EnableFastISelAbort) { 1059 dbgs() << "FastISel missed call: "; 1060 Inst->dump(); 1061 } 1062 1063 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1064 unsigned &R = FuncInfo->ValueMap[Inst]; 1065 if (!R) 1066 R = FuncInfo->CreateRegs(Inst->getType()); 1067 } 1068 1069 bool HadTailCall = false; 1070 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1071 SelectBasicBlock(Inst, BI, HadTailCall); 1072 1073 // If the call was emitted as a tail call, we're done with the block. 1074 // We also need to delete any previously emitted instructions. 1075 if (HadTailCall) { 1076 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1077 --BI; 1078 break; 1079 } 1080 1081 // Recompute NumFastIselRemaining as Selection DAG instruction 1082 // selection may have handled the call, input args, etc. 1083 unsigned RemainingNow = std::distance(Begin, BI); 1084 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1085 NumFastIselRemaining = RemainingNow; 1086 continue; 1087 } 1088 1089 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1090 // Don't abort, and use a different message for terminator misses. 1091 NumFastIselFailures += NumFastIselRemaining; 1092 if (EnableFastISelVerbose || EnableFastISelAbort) { 1093 dbgs() << "FastISel missed terminator: "; 1094 Inst->dump(); 1095 } 1096 } else { 1097 NumFastIselFailures += NumFastIselRemaining; 1098 if (EnableFastISelVerbose || EnableFastISelAbort) { 1099 dbgs() << "FastISel miss: "; 1100 Inst->dump(); 1101 } 1102 if (EnableFastISelAbort) 1103 // The "fast" selector couldn't handle something and bailed. 1104 // For the purpose of debugging, just abort. 1105 llvm_unreachable("FastISel didn't select the entire block"); 1106 } 1107 break; 1108 } 1109 1110 FastIS->recomputeInsertPt(); 1111 } else { 1112 // Lower any arguments needed in this block if this is the entry block. 1113 if (LLVMBB == &Fn.getEntryBlock()) { 1114 ++NumEntryBlocks; 1115 LowerArguments(Fn); 1116 } 1117 } 1118 1119 if (Begin != BI) 1120 ++NumDAGBlocks; 1121 else 1122 ++NumFastIselBlocks; 1123 1124 if (Begin != BI) { 1125 // Run SelectionDAG instruction selection on the remainder of the block 1126 // not handled by FastISel. If FastISel is not run, this is the entire 1127 // block. 1128 bool HadTailCall; 1129 SelectBasicBlock(Begin, BI, HadTailCall); 1130 } 1131 1132 FinishBasicBlock(); 1133 FuncInfo->PHINodesToUpdate.clear(); 1134 } 1135 1136 delete FastIS; 1137 SDB->clearDanglingDebugInfo(); 1138} 1139 1140void 1141SelectionDAGISel::FinishBasicBlock() { 1142 1143 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1144 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1145 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1146 dbgs() << "Node " << i << " : (" 1147 << FuncInfo->PHINodesToUpdate[i].first 1148 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1149 1150 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1151 // PHI nodes in successors. 1152 if (SDB->SwitchCases.empty() && 1153 SDB->JTCases.empty() && 1154 SDB->BitTestCases.empty()) { 1155 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1156 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1157 assert(PHI->isPHI() && 1158 "This is not a machine PHI node that we are updating!"); 1159 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1160 continue; 1161 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1162 } 1163 return; 1164 } 1165 1166 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1167 // Lower header first, if it wasn't already lowered 1168 if (!SDB->BitTestCases[i].Emitted) { 1169 // Set the current basic block to the mbb we wish to insert the code into 1170 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1171 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1172 // Emit the code 1173 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1174 CurDAG->setRoot(SDB->getRoot()); 1175 SDB->clear(); 1176 CodeGenAndEmitDAG(); 1177 } 1178 1179 uint32_t UnhandledWeight = 0; 1180 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1181 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1182 1183 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1184 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1185 // Set the current basic block to the mbb we wish to insert the code into 1186 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1187 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1188 // Emit the code 1189 if (j+1 != ej) 1190 SDB->visitBitTestCase(SDB->BitTestCases[i], 1191 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1192 UnhandledWeight, 1193 SDB->BitTestCases[i].Reg, 1194 SDB->BitTestCases[i].Cases[j], 1195 FuncInfo->MBB); 1196 else 1197 SDB->visitBitTestCase(SDB->BitTestCases[i], 1198 SDB->BitTestCases[i].Default, 1199 UnhandledWeight, 1200 SDB->BitTestCases[i].Reg, 1201 SDB->BitTestCases[i].Cases[j], 1202 FuncInfo->MBB); 1203 1204 1205 CurDAG->setRoot(SDB->getRoot()); 1206 SDB->clear(); 1207 CodeGenAndEmitDAG(); 1208 } 1209 1210 // Update PHI Nodes 1211 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1212 pi != pe; ++pi) { 1213 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1214 MachineBasicBlock *PHIBB = PHI->getParent(); 1215 assert(PHI->isPHI() && 1216 "This is not a machine PHI node that we are updating!"); 1217 // This is "default" BB. We have two jumps to it. From "header" BB and 1218 // from last "case" BB. 1219 if (PHIBB == SDB->BitTestCases[i].Default) 1220 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1221 .addMBB(SDB->BitTestCases[i].Parent) 1222 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1223 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1224 // One of "cases" BB. 1225 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1226 j != ej; ++j) { 1227 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1228 if (cBB->isSuccessor(PHIBB)) 1229 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1230 } 1231 } 1232 } 1233 SDB->BitTestCases.clear(); 1234 1235 // If the JumpTable record is filled in, then we need to emit a jump table. 1236 // Updating the PHI nodes is tricky in this case, since we need to determine 1237 // whether the PHI is a successor of the range check MBB or the jump table MBB 1238 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1239 // Lower header first, if it wasn't already lowered 1240 if (!SDB->JTCases[i].first.Emitted) { 1241 // Set the current basic block to the mbb we wish to insert the code into 1242 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1243 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1244 // Emit the code 1245 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1246 FuncInfo->MBB); 1247 CurDAG->setRoot(SDB->getRoot()); 1248 SDB->clear(); 1249 CodeGenAndEmitDAG(); 1250 } 1251 1252 // Set the current basic block to the mbb we wish to insert the code into 1253 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1254 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1255 // Emit the code 1256 SDB->visitJumpTable(SDB->JTCases[i].second); 1257 CurDAG->setRoot(SDB->getRoot()); 1258 SDB->clear(); 1259 CodeGenAndEmitDAG(); 1260 1261 // Update PHI Nodes 1262 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1263 pi != pe; ++pi) { 1264 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1265 MachineBasicBlock *PHIBB = PHI->getParent(); 1266 assert(PHI->isPHI() && 1267 "This is not a machine PHI node that we are updating!"); 1268 // "default" BB. We can go there only from header BB. 1269 if (PHIBB == SDB->JTCases[i].second.Default) 1270 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1271 .addMBB(SDB->JTCases[i].first.HeaderBB); 1272 // JT BB. Just iterate over successors here 1273 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1274 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1275 } 1276 } 1277 SDB->JTCases.clear(); 1278 1279 // If the switch block involved a branch to one of the actual successors, we 1280 // need to update PHI nodes in that block. 1281 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1282 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1283 assert(PHI->isPHI() && 1284 "This is not a machine PHI node that we are updating!"); 1285 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1286 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1287 } 1288 1289 // If we generated any switch lowering information, build and codegen any 1290 // additional DAGs necessary. 1291 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1292 // Set the current basic block to the mbb we wish to insert the code into 1293 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1294 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1295 1296 // Determine the unique successors. 1297 SmallVector<MachineBasicBlock *, 2> Succs; 1298 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1299 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1300 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1301 1302 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1303 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1304 CurDAG->setRoot(SDB->getRoot()); 1305 SDB->clear(); 1306 CodeGenAndEmitDAG(); 1307 1308 // Remember the last block, now that any splitting is done, for use in 1309 // populating PHI nodes in successors. 1310 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1311 1312 // Handle any PHI nodes in successors of this chunk, as if we were coming 1313 // from the original BB before switch expansion. Note that PHI nodes can 1314 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1315 // handle them the right number of times. 1316 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1317 FuncInfo->MBB = Succs[i]; 1318 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1319 // FuncInfo->MBB may have been removed from the CFG if a branch was 1320 // constant folded. 1321 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1322 for (MachineBasicBlock::iterator 1323 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1324 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1325 MachineInstrBuilder PHI(*MF, MBBI); 1326 // This value for this PHI node is recorded in PHINodesToUpdate. 1327 for (unsigned pn = 0; ; ++pn) { 1328 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1329 "Didn't find PHI entry!"); 1330 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1331 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1332 break; 1333 } 1334 } 1335 } 1336 } 1337 } 1338 } 1339 SDB->SwitchCases.clear(); 1340} 1341 1342 1343/// Create the scheduler. If a specific scheduler was specified 1344/// via the SchedulerRegistry, use it, otherwise select the 1345/// one preferred by the target. 1346/// 1347ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1348 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1349 1350 if (!Ctor) { 1351 Ctor = ISHeuristic; 1352 RegisterScheduler::setDefault(Ctor); 1353 } 1354 1355 return Ctor(this, OptLevel); 1356} 1357 1358//===----------------------------------------------------------------------===// 1359// Helper functions used by the generated instruction selector. 1360//===----------------------------------------------------------------------===// 1361// Calls to these methods are generated by tblgen. 1362 1363/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1364/// the dag combiner simplified the 255, we still want to match. RHS is the 1365/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1366/// specified in the .td file (e.g. 255). 1367bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1368 int64_t DesiredMaskS) const { 1369 const APInt &ActualMask = RHS->getAPIntValue(); 1370 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1371 1372 // If the actual mask exactly matches, success! 1373 if (ActualMask == DesiredMask) 1374 return true; 1375 1376 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1377 if (ActualMask.intersects(~DesiredMask)) 1378 return false; 1379 1380 // Otherwise, the DAG Combiner may have proven that the value coming in is 1381 // either already zero or is not demanded. Check for known zero input bits. 1382 APInt NeededMask = DesiredMask & ~ActualMask; 1383 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1384 return true; 1385 1386 // TODO: check to see if missing bits are just not demanded. 1387 1388 // Otherwise, this pattern doesn't match. 1389 return false; 1390} 1391 1392/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1393/// the dag combiner simplified the 255, we still want to match. RHS is the 1394/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1395/// specified in the .td file (e.g. 255). 1396bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1397 int64_t DesiredMaskS) const { 1398 const APInt &ActualMask = RHS->getAPIntValue(); 1399 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1400 1401 // If the actual mask exactly matches, success! 1402 if (ActualMask == DesiredMask) 1403 return true; 1404 1405 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1406 if (ActualMask.intersects(~DesiredMask)) 1407 return false; 1408 1409 // Otherwise, the DAG Combiner may have proven that the value coming in is 1410 // either already zero or is not demanded. Check for known zero input bits. 1411 APInt NeededMask = DesiredMask & ~ActualMask; 1412 1413 APInt KnownZero, KnownOne; 1414 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1415 1416 // If all the missing bits in the or are already known to be set, match! 1417 if ((NeededMask & KnownOne) == NeededMask) 1418 return true; 1419 1420 // TODO: check to see if missing bits are just not demanded. 1421 1422 // Otherwise, this pattern doesn't match. 1423 return false; 1424} 1425 1426 1427/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1428/// by tblgen. Others should not call it. 1429void SelectionDAGISel:: 1430SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1431 std::vector<SDValue> InOps; 1432 std::swap(InOps, Ops); 1433 1434 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1435 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1436 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1437 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1438 1439 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1440 if (InOps[e-1].getValueType() == MVT::Glue) 1441 --e; // Don't process a glue operand if it is here. 1442 1443 while (i != e) { 1444 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1445 if (!InlineAsm::isMemKind(Flags)) { 1446 // Just skip over this operand, copying the operands verbatim. 1447 Ops.insert(Ops.end(), InOps.begin()+i, 1448 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1449 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1450 } else { 1451 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1452 "Memory operand with multiple values?"); 1453 // Otherwise, this is a memory operand. Ask the target to select it. 1454 std::vector<SDValue> SelOps; 1455 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1456 report_fatal_error("Could not match memory address. Inline asm" 1457 " failure!"); 1458 1459 // Add this to the output node. 1460 unsigned NewFlags = 1461 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1462 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1463 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1464 i += 2; 1465 } 1466 } 1467 1468 // Add the glue input back if present. 1469 if (e != InOps.size()) 1470 Ops.push_back(InOps.back()); 1471} 1472 1473/// findGlueUse - Return use of MVT::Glue value produced by the specified 1474/// SDNode. 1475/// 1476static SDNode *findGlueUse(SDNode *N) { 1477 unsigned FlagResNo = N->getNumValues()-1; 1478 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1479 SDUse &Use = I.getUse(); 1480 if (Use.getResNo() == FlagResNo) 1481 return Use.getUser(); 1482 } 1483 return NULL; 1484} 1485 1486/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1487/// This function recursively traverses up the operand chain, ignoring 1488/// certain nodes. 1489static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1490 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1491 bool IgnoreChains) { 1492 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1493 // greater than all of its (recursive) operands. If we scan to a point where 1494 // 'use' is smaller than the node we're scanning for, then we know we will 1495 // never find it. 1496 // 1497 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1498 // happen because we scan down to newly selected nodes in the case of glue 1499 // uses. 1500 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1501 return false; 1502 1503 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1504 // won't fail if we scan it again. 1505 if (!Visited.insert(Use)) 1506 return false; 1507 1508 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1509 // Ignore chain uses, they are validated by HandleMergeInputChains. 1510 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1511 continue; 1512 1513 SDNode *N = Use->getOperand(i).getNode(); 1514 if (N == Def) { 1515 if (Use == ImmedUse || Use == Root) 1516 continue; // We are not looking for immediate use. 1517 assert(N != Root); 1518 return true; 1519 } 1520 1521 // Traverse up the operand chain. 1522 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1523 return true; 1524 } 1525 return false; 1526} 1527 1528/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1529/// operand node N of U during instruction selection that starts at Root. 1530bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1531 SDNode *Root) const { 1532 if (OptLevel == CodeGenOpt::None) return false; 1533 return N.hasOneUse(); 1534} 1535 1536/// IsLegalToFold - Returns true if the specific operand node N of 1537/// U can be folded during instruction selection that starts at Root. 1538bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1539 CodeGenOpt::Level OptLevel, 1540 bool IgnoreChains) { 1541 if (OptLevel == CodeGenOpt::None) return false; 1542 1543 // If Root use can somehow reach N through a path that that doesn't contain 1544 // U then folding N would create a cycle. e.g. In the following 1545 // diagram, Root can reach N through X. If N is folded into into Root, then 1546 // X is both a predecessor and a successor of U. 1547 // 1548 // [N*] // 1549 // ^ ^ // 1550 // / \ // 1551 // [U*] [X]? // 1552 // ^ ^ // 1553 // \ / // 1554 // \ / // 1555 // [Root*] // 1556 // 1557 // * indicates nodes to be folded together. 1558 // 1559 // If Root produces glue, then it gets (even more) interesting. Since it 1560 // will be "glued" together with its glue use in the scheduler, we need to 1561 // check if it might reach N. 1562 // 1563 // [N*] // 1564 // ^ ^ // 1565 // / \ // 1566 // [U*] [X]? // 1567 // ^ ^ // 1568 // \ \ // 1569 // \ | // 1570 // [Root*] | // 1571 // ^ | // 1572 // f | // 1573 // | / // 1574 // [Y] / // 1575 // ^ / // 1576 // f / // 1577 // | / // 1578 // [GU] // 1579 // 1580 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1581 // (call it Fold), then X is a predecessor of GU and a successor of 1582 // Fold. But since Fold and GU are glued together, this will create 1583 // a cycle in the scheduling graph. 1584 1585 // If the node has glue, walk down the graph to the "lowest" node in the 1586 // glueged set. 1587 EVT VT = Root->getValueType(Root->getNumValues()-1); 1588 while (VT == MVT::Glue) { 1589 SDNode *GU = findGlueUse(Root); 1590 if (GU == NULL) 1591 break; 1592 Root = GU; 1593 VT = Root->getValueType(Root->getNumValues()-1); 1594 1595 // If our query node has a glue result with a use, we've walked up it. If 1596 // the user (which has already been selected) has a chain or indirectly uses 1597 // the chain, our WalkChainUsers predicate will not consider it. Because of 1598 // this, we cannot ignore chains in this predicate. 1599 IgnoreChains = false; 1600 } 1601 1602 1603 SmallPtrSet<SDNode*, 16> Visited; 1604 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1605} 1606 1607SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1608 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1609 SelectInlineAsmMemoryOperands(Ops); 1610 1611 EVT VTs[] = { MVT::Other, MVT::Glue }; 1612 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1613 VTs, &Ops[0], Ops.size()); 1614 New->setNodeId(-1); 1615 return New.getNode(); 1616} 1617 1618SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1619 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1620} 1621 1622/// GetVBR - decode a vbr encoding whose top bit is set. 1623LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1624GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1625 assert(Val >= 128 && "Not a VBR"); 1626 Val &= 127; // Remove first vbr bit. 1627 1628 unsigned Shift = 7; 1629 uint64_t NextBits; 1630 do { 1631 NextBits = MatcherTable[Idx++]; 1632 Val |= (NextBits&127) << Shift; 1633 Shift += 7; 1634 } while (NextBits & 128); 1635 1636 return Val; 1637} 1638 1639 1640/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1641/// interior glue and chain results to use the new glue and chain results. 1642void SelectionDAGISel:: 1643UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1644 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1645 SDValue InputGlue, 1646 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1647 bool isMorphNodeTo) { 1648 SmallVector<SDNode*, 4> NowDeadNodes; 1649 1650 // Now that all the normal results are replaced, we replace the chain and 1651 // glue results if present. 1652 if (!ChainNodesMatched.empty()) { 1653 assert(InputChain.getNode() != 0 && 1654 "Matched input chains but didn't produce a chain"); 1655 // Loop over all of the nodes we matched that produced a chain result. 1656 // Replace all the chain results with the final chain we ended up with. 1657 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1658 SDNode *ChainNode = ChainNodesMatched[i]; 1659 1660 // If this node was already deleted, don't look at it. 1661 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1662 continue; 1663 1664 // Don't replace the results of the root node if we're doing a 1665 // MorphNodeTo. 1666 if (ChainNode == NodeToMatch && isMorphNodeTo) 1667 continue; 1668 1669 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1670 if (ChainVal.getValueType() == MVT::Glue) 1671 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1672 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1673 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1674 1675 // If the node became dead and we haven't already seen it, delete it. 1676 if (ChainNode->use_empty() && 1677 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1678 NowDeadNodes.push_back(ChainNode); 1679 } 1680 } 1681 1682 // If the result produces glue, update any glue results in the matched 1683 // pattern with the glue result. 1684 if (InputGlue.getNode() != 0) { 1685 // Handle any interior nodes explicitly marked. 1686 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1687 SDNode *FRN = GlueResultNodesMatched[i]; 1688 1689 // If this node was already deleted, don't look at it. 1690 if (FRN->getOpcode() == ISD::DELETED_NODE) 1691 continue; 1692 1693 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1694 "Doesn't have a glue result"); 1695 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1696 InputGlue); 1697 1698 // If the node became dead and we haven't already seen it, delete it. 1699 if (FRN->use_empty() && 1700 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1701 NowDeadNodes.push_back(FRN); 1702 } 1703 } 1704 1705 if (!NowDeadNodes.empty()) 1706 CurDAG->RemoveDeadNodes(NowDeadNodes); 1707 1708 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1709} 1710 1711enum ChainResult { 1712 CR_Simple, 1713 CR_InducesCycle, 1714 CR_LeadsToInteriorNode 1715}; 1716 1717/// WalkChainUsers - Walk down the users of the specified chained node that is 1718/// part of the pattern we're matching, looking at all of the users we find. 1719/// This determines whether something is an interior node, whether we have a 1720/// non-pattern node in between two pattern nodes (which prevent folding because 1721/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1722/// between pattern nodes (in which case the TF becomes part of the pattern). 1723/// 1724/// The walk we do here is guaranteed to be small because we quickly get down to 1725/// already selected nodes "below" us. 1726static ChainResult 1727WalkChainUsers(const SDNode *ChainedNode, 1728 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1729 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1730 ChainResult Result = CR_Simple; 1731 1732 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1733 E = ChainedNode->use_end(); UI != E; ++UI) { 1734 // Make sure the use is of the chain, not some other value we produce. 1735 if (UI.getUse().getValueType() != MVT::Other) continue; 1736 1737 SDNode *User = *UI; 1738 1739 // If we see an already-selected machine node, then we've gone beyond the 1740 // pattern that we're selecting down into the already selected chunk of the 1741 // DAG. 1742 if (User->isMachineOpcode() || 1743 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1744 continue; 1745 1746 unsigned UserOpcode = User->getOpcode(); 1747 if (UserOpcode == ISD::CopyToReg || 1748 UserOpcode == ISD::CopyFromReg || 1749 UserOpcode == ISD::INLINEASM || 1750 UserOpcode == ISD::EH_LABEL || 1751 UserOpcode == ISD::LIFETIME_START || 1752 UserOpcode == ISD::LIFETIME_END) { 1753 // If their node ID got reset to -1 then they've already been selected. 1754 // Treat them like a MachineOpcode. 1755 if (User->getNodeId() == -1) 1756 continue; 1757 } 1758 1759 // If we have a TokenFactor, we handle it specially. 1760 if (User->getOpcode() != ISD::TokenFactor) { 1761 // If the node isn't a token factor and isn't part of our pattern, then it 1762 // must be a random chained node in between two nodes we're selecting. 1763 // This happens when we have something like: 1764 // x = load ptr 1765 // call 1766 // y = x+4 1767 // store y -> ptr 1768 // Because we structurally match the load/store as a read/modify/write, 1769 // but the call is chained between them. We cannot fold in this case 1770 // because it would induce a cycle in the graph. 1771 if (!std::count(ChainedNodesInPattern.begin(), 1772 ChainedNodesInPattern.end(), User)) 1773 return CR_InducesCycle; 1774 1775 // Otherwise we found a node that is part of our pattern. For example in: 1776 // x = load ptr 1777 // y = x+4 1778 // store y -> ptr 1779 // This would happen when we're scanning down from the load and see the 1780 // store as a user. Record that there is a use of ChainedNode that is 1781 // part of the pattern and keep scanning uses. 1782 Result = CR_LeadsToInteriorNode; 1783 InteriorChainedNodes.push_back(User); 1784 continue; 1785 } 1786 1787 // If we found a TokenFactor, there are two cases to consider: first if the 1788 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1789 // uses of the TF are in our pattern) we just want to ignore it. Second, 1790 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1791 // [Load chain] 1792 // ^ 1793 // | 1794 // [Load] 1795 // ^ ^ 1796 // | \ DAG's like cheese 1797 // / \ do you? 1798 // / | 1799 // [TokenFactor] [Op] 1800 // ^ ^ 1801 // | | 1802 // \ / 1803 // \ / 1804 // [Store] 1805 // 1806 // In this case, the TokenFactor becomes part of our match and we rewrite it 1807 // as a new TokenFactor. 1808 // 1809 // To distinguish these two cases, do a recursive walk down the uses. 1810 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1811 case CR_Simple: 1812 // If the uses of the TokenFactor are just already-selected nodes, ignore 1813 // it, it is "below" our pattern. 1814 continue; 1815 case CR_InducesCycle: 1816 // If the uses of the TokenFactor lead to nodes that are not part of our 1817 // pattern that are not selected, folding would turn this into a cycle, 1818 // bail out now. 1819 return CR_InducesCycle; 1820 case CR_LeadsToInteriorNode: 1821 break; // Otherwise, keep processing. 1822 } 1823 1824 // Okay, we know we're in the interesting interior case. The TokenFactor 1825 // is now going to be considered part of the pattern so that we rewrite its 1826 // uses (it may have uses that are not part of the pattern) with the 1827 // ultimate chain result of the generated code. We will also add its chain 1828 // inputs as inputs to the ultimate TokenFactor we create. 1829 Result = CR_LeadsToInteriorNode; 1830 ChainedNodesInPattern.push_back(User); 1831 InteriorChainedNodes.push_back(User); 1832 continue; 1833 } 1834 1835 return Result; 1836} 1837 1838/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1839/// operation for when the pattern matched at least one node with a chains. The 1840/// input vector contains a list of all of the chained nodes that we match. We 1841/// must determine if this is a valid thing to cover (i.e. matching it won't 1842/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1843/// be used as the input node chain for the generated nodes. 1844static SDValue 1845HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1846 SelectionDAG *CurDAG) { 1847 // Walk all of the chained nodes we've matched, recursively scanning down the 1848 // users of the chain result. This adds any TokenFactor nodes that are caught 1849 // in between chained nodes to the chained and interior nodes list. 1850 SmallVector<SDNode*, 3> InteriorChainedNodes; 1851 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1852 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1853 InteriorChainedNodes) == CR_InducesCycle) 1854 return SDValue(); // Would induce a cycle. 1855 } 1856 1857 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1858 // that we are interested in. Form our input TokenFactor node. 1859 SmallVector<SDValue, 3> InputChains; 1860 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1861 // Add the input chain of this node to the InputChains list (which will be 1862 // the operands of the generated TokenFactor) if it's not an interior node. 1863 SDNode *N = ChainNodesMatched[i]; 1864 if (N->getOpcode() != ISD::TokenFactor) { 1865 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1866 continue; 1867 1868 // Otherwise, add the input chain. 1869 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1870 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1871 InputChains.push_back(InChain); 1872 continue; 1873 } 1874 1875 // If we have a token factor, we want to add all inputs of the token factor 1876 // that are not part of the pattern we're matching. 1877 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1878 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1879 N->getOperand(op).getNode())) 1880 InputChains.push_back(N->getOperand(op)); 1881 } 1882 } 1883 1884 SDValue Res; 1885 if (InputChains.size() == 1) 1886 return InputChains[0]; 1887 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1888 MVT::Other, &InputChains[0], InputChains.size()); 1889} 1890 1891/// MorphNode - Handle morphing a node in place for the selector. 1892SDNode *SelectionDAGISel:: 1893MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1894 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1895 // It is possible we're using MorphNodeTo to replace a node with no 1896 // normal results with one that has a normal result (or we could be 1897 // adding a chain) and the input could have glue and chains as well. 1898 // In this case we need to shift the operands down. 1899 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1900 // than the old isel though. 1901 int OldGlueResultNo = -1, OldChainResultNo = -1; 1902 1903 unsigned NTMNumResults = Node->getNumValues(); 1904 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1905 OldGlueResultNo = NTMNumResults-1; 1906 if (NTMNumResults != 1 && 1907 Node->getValueType(NTMNumResults-2) == MVT::Other) 1908 OldChainResultNo = NTMNumResults-2; 1909 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1910 OldChainResultNo = NTMNumResults-1; 1911 1912 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1913 // that this deletes operands of the old node that become dead. 1914 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1915 1916 // MorphNodeTo can operate in two ways: if an existing node with the 1917 // specified operands exists, it can just return it. Otherwise, it 1918 // updates the node in place to have the requested operands. 1919 if (Res == Node) { 1920 // If we updated the node in place, reset the node ID. To the isel, 1921 // this should be just like a newly allocated machine node. 1922 Res->setNodeId(-1); 1923 } 1924 1925 unsigned ResNumResults = Res->getNumValues(); 1926 // Move the glue if needed. 1927 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1928 (unsigned)OldGlueResultNo != ResNumResults-1) 1929 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1930 SDValue(Res, ResNumResults-1)); 1931 1932 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1933 --ResNumResults; 1934 1935 // Move the chain reference if needed. 1936 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1937 (unsigned)OldChainResultNo != ResNumResults-1) 1938 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1939 SDValue(Res, ResNumResults-1)); 1940 1941 // Otherwise, no replacement happened because the node already exists. Replace 1942 // Uses of the old node with the new one. 1943 if (Res != Node) 1944 CurDAG->ReplaceAllUsesWith(Node, Res); 1945 1946 return Res; 1947} 1948 1949/// CheckSame - Implements OP_CheckSame. 1950LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1951CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1952 SDValue N, 1953 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1954 // Accept if it is exactly the same as a previously recorded node. 1955 unsigned RecNo = MatcherTable[MatcherIndex++]; 1956 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1957 return N == RecordedNodes[RecNo].first; 1958} 1959 1960/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1961LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1962CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1963 const SelectionDAGISel &SDISel) { 1964 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1965} 1966 1967/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1968LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1969CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1970 const SelectionDAGISel &SDISel, SDNode *N) { 1971 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1972} 1973 1974LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1975CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1976 SDNode *N) { 1977 uint16_t Opc = MatcherTable[MatcherIndex++]; 1978 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1979 return N->getOpcode() == Opc; 1980} 1981 1982LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1983CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1984 SDValue N, const TargetLowering &TLI) { 1985 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1986 if (N.getValueType() == VT) return true; 1987 1988 // Handle the case when VT is iPTR. 1989 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1990} 1991 1992LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1993CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1994 SDValue N, const TargetLowering &TLI, 1995 unsigned ChildNo) { 1996 if (ChildNo >= N.getNumOperands()) 1997 return false; // Match fails if out of range child #. 1998 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1999} 2000 2001 2002LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2003CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2004 SDValue N) { 2005 return cast<CondCodeSDNode>(N)->get() == 2006 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2007} 2008 2009LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2010CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2011 SDValue N, const TargetLowering &TLI) { 2012 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2013 if (cast<VTSDNode>(N)->getVT() == VT) 2014 return true; 2015 2016 // Handle the case when VT is iPTR. 2017 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2018} 2019 2020LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2021CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2022 SDValue N) { 2023 int64_t Val = MatcherTable[MatcherIndex++]; 2024 if (Val & 128) 2025 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2026 2027 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2028 return C != 0 && C->getSExtValue() == Val; 2029} 2030 2031LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2032CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2033 SDValue N, const SelectionDAGISel &SDISel) { 2034 int64_t Val = MatcherTable[MatcherIndex++]; 2035 if (Val & 128) 2036 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2037 2038 if (N->getOpcode() != ISD::AND) return false; 2039 2040 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2041 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2042} 2043 2044LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2045CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2046 SDValue N, const SelectionDAGISel &SDISel) { 2047 int64_t Val = MatcherTable[MatcherIndex++]; 2048 if (Val & 128) 2049 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2050 2051 if (N->getOpcode() != ISD::OR) return false; 2052 2053 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2054 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2055} 2056 2057/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2058/// scope, evaluate the current node. If the current predicate is known to 2059/// fail, set Result=true and return anything. If the current predicate is 2060/// known to pass, set Result=false and return the MatcherIndex to continue 2061/// with. If the current predicate is unknown, set Result=false and return the 2062/// MatcherIndex to continue with. 2063static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2064 unsigned Index, SDValue N, 2065 bool &Result, 2066 const SelectionDAGISel &SDISel, 2067 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2068 switch (Table[Index++]) { 2069 default: 2070 Result = false; 2071 return Index-1; // Could not evaluate this predicate. 2072 case SelectionDAGISel::OPC_CheckSame: 2073 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2074 return Index; 2075 case SelectionDAGISel::OPC_CheckPatternPredicate: 2076 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2077 return Index; 2078 case SelectionDAGISel::OPC_CheckPredicate: 2079 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2080 return Index; 2081 case SelectionDAGISel::OPC_CheckOpcode: 2082 Result = !::CheckOpcode(Table, Index, N.getNode()); 2083 return Index; 2084 case SelectionDAGISel::OPC_CheckType: 2085 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2086 return Index; 2087 case SelectionDAGISel::OPC_CheckChild0Type: 2088 case SelectionDAGISel::OPC_CheckChild1Type: 2089 case SelectionDAGISel::OPC_CheckChild2Type: 2090 case SelectionDAGISel::OPC_CheckChild3Type: 2091 case SelectionDAGISel::OPC_CheckChild4Type: 2092 case SelectionDAGISel::OPC_CheckChild5Type: 2093 case SelectionDAGISel::OPC_CheckChild6Type: 2094 case SelectionDAGISel::OPC_CheckChild7Type: 2095 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2096 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2097 return Index; 2098 case SelectionDAGISel::OPC_CheckCondCode: 2099 Result = !::CheckCondCode(Table, Index, N); 2100 return Index; 2101 case SelectionDAGISel::OPC_CheckValueType: 2102 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2103 return Index; 2104 case SelectionDAGISel::OPC_CheckInteger: 2105 Result = !::CheckInteger(Table, Index, N); 2106 return Index; 2107 case SelectionDAGISel::OPC_CheckAndImm: 2108 Result = !::CheckAndImm(Table, Index, N, SDISel); 2109 return Index; 2110 case SelectionDAGISel::OPC_CheckOrImm: 2111 Result = !::CheckOrImm(Table, Index, N, SDISel); 2112 return Index; 2113 } 2114} 2115 2116namespace { 2117 2118struct MatchScope { 2119 /// FailIndex - If this match fails, this is the index to continue with. 2120 unsigned FailIndex; 2121 2122 /// NodeStack - The node stack when the scope was formed. 2123 SmallVector<SDValue, 4> NodeStack; 2124 2125 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2126 unsigned NumRecordedNodes; 2127 2128 /// NumMatchedMemRefs - The number of matched memref entries. 2129 unsigned NumMatchedMemRefs; 2130 2131 /// InputChain/InputGlue - The current chain/glue 2132 SDValue InputChain, InputGlue; 2133 2134 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2135 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2136}; 2137 2138} 2139 2140SDNode *SelectionDAGISel:: 2141SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2142 unsigned TableSize) { 2143 // FIXME: Should these even be selected? Handle these cases in the caller? 2144 switch (NodeToMatch->getOpcode()) { 2145 default: 2146 break; 2147 case ISD::EntryToken: // These nodes remain the same. 2148 case ISD::BasicBlock: 2149 case ISD::Register: 2150 case ISD::RegisterMask: 2151 //case ISD::VALUETYPE: 2152 //case ISD::CONDCODE: 2153 case ISD::HANDLENODE: 2154 case ISD::MDNODE_SDNODE: 2155 case ISD::TargetConstant: 2156 case ISD::TargetConstantFP: 2157 case ISD::TargetConstantPool: 2158 case ISD::TargetFrameIndex: 2159 case ISD::TargetExternalSymbol: 2160 case ISD::TargetBlockAddress: 2161 case ISD::TargetJumpTable: 2162 case ISD::TargetGlobalTLSAddress: 2163 case ISD::TargetGlobalAddress: 2164 case ISD::TokenFactor: 2165 case ISD::CopyFromReg: 2166 case ISD::CopyToReg: 2167 case ISD::EH_LABEL: 2168 case ISD::LIFETIME_START: 2169 case ISD::LIFETIME_END: 2170 NodeToMatch->setNodeId(-1); // Mark selected. 2171 return 0; 2172 case ISD::AssertSext: 2173 case ISD::AssertZext: 2174 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2175 NodeToMatch->getOperand(0)); 2176 return 0; 2177 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2178 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2179 } 2180 2181 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2182 2183 // Set up the node stack with NodeToMatch as the only node on the stack. 2184 SmallVector<SDValue, 8> NodeStack; 2185 SDValue N = SDValue(NodeToMatch, 0); 2186 NodeStack.push_back(N); 2187 2188 // MatchScopes - Scopes used when matching, if a match failure happens, this 2189 // indicates where to continue checking. 2190 SmallVector<MatchScope, 8> MatchScopes; 2191 2192 // RecordedNodes - This is the set of nodes that have been recorded by the 2193 // state machine. The second value is the parent of the node, or null if the 2194 // root is recorded. 2195 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2196 2197 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2198 // pattern. 2199 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2200 2201 // These are the current input chain and glue for use when generating nodes. 2202 // Various Emit operations change these. For example, emitting a copytoreg 2203 // uses and updates these. 2204 SDValue InputChain, InputGlue; 2205 2206 // ChainNodesMatched - If a pattern matches nodes that have input/output 2207 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2208 // which ones they are. The result is captured into this list so that we can 2209 // update the chain results when the pattern is complete. 2210 SmallVector<SDNode*, 3> ChainNodesMatched; 2211 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2212 2213 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2214 NodeToMatch->dump(CurDAG); 2215 dbgs() << '\n'); 2216 2217 // Determine where to start the interpreter. Normally we start at opcode #0, 2218 // but if the state machine starts with an OPC_SwitchOpcode, then we 2219 // accelerate the first lookup (which is guaranteed to be hot) with the 2220 // OpcodeOffset table. 2221 unsigned MatcherIndex = 0; 2222 2223 if (!OpcodeOffset.empty()) { 2224 // Already computed the OpcodeOffset table, just index into it. 2225 if (N.getOpcode() < OpcodeOffset.size()) 2226 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2227 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2228 2229 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2230 // Otherwise, the table isn't computed, but the state machine does start 2231 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2232 // is the first time we're selecting an instruction. 2233 unsigned Idx = 1; 2234 while (1) { 2235 // Get the size of this case. 2236 unsigned CaseSize = MatcherTable[Idx++]; 2237 if (CaseSize & 128) 2238 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2239 if (CaseSize == 0) break; 2240 2241 // Get the opcode, add the index to the table. 2242 uint16_t Opc = MatcherTable[Idx++]; 2243 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2244 if (Opc >= OpcodeOffset.size()) 2245 OpcodeOffset.resize((Opc+1)*2); 2246 OpcodeOffset[Opc] = Idx; 2247 Idx += CaseSize; 2248 } 2249 2250 // Okay, do the lookup for the first opcode. 2251 if (N.getOpcode() < OpcodeOffset.size()) 2252 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2253 } 2254 2255 while (1) { 2256 assert(MatcherIndex < TableSize && "Invalid index"); 2257#ifndef NDEBUG 2258 unsigned CurrentOpcodeIndex = MatcherIndex; 2259#endif 2260 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2261 switch (Opcode) { 2262 case OPC_Scope: { 2263 // Okay, the semantics of this operation are that we should push a scope 2264 // then evaluate the first child. However, pushing a scope only to have 2265 // the first check fail (which then pops it) is inefficient. If we can 2266 // determine immediately that the first check (or first several) will 2267 // immediately fail, don't even bother pushing a scope for them. 2268 unsigned FailIndex; 2269 2270 while (1) { 2271 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2272 if (NumToSkip & 128) 2273 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2274 // Found the end of the scope with no match. 2275 if (NumToSkip == 0) { 2276 FailIndex = 0; 2277 break; 2278 } 2279 2280 FailIndex = MatcherIndex+NumToSkip; 2281 2282 unsigned MatcherIndexOfPredicate = MatcherIndex; 2283 (void)MatcherIndexOfPredicate; // silence warning. 2284 2285 // If we can't evaluate this predicate without pushing a scope (e.g. if 2286 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2287 // push the scope and evaluate the full predicate chain. 2288 bool Result; 2289 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2290 Result, *this, RecordedNodes); 2291 if (!Result) 2292 break; 2293 2294 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2295 << "index " << MatcherIndexOfPredicate 2296 << ", continuing at " << FailIndex << "\n"); 2297 ++NumDAGIselRetries; 2298 2299 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2300 // move to the next case. 2301 MatcherIndex = FailIndex; 2302 } 2303 2304 // If the whole scope failed to match, bail. 2305 if (FailIndex == 0) break; 2306 2307 // Push a MatchScope which indicates where to go if the first child fails 2308 // to match. 2309 MatchScope NewEntry; 2310 NewEntry.FailIndex = FailIndex; 2311 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2312 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2313 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2314 NewEntry.InputChain = InputChain; 2315 NewEntry.InputGlue = InputGlue; 2316 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2317 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2318 MatchScopes.push_back(NewEntry); 2319 continue; 2320 } 2321 case OPC_RecordNode: { 2322 // Remember this node, it may end up being an operand in the pattern. 2323 SDNode *Parent = 0; 2324 if (NodeStack.size() > 1) 2325 Parent = NodeStack[NodeStack.size()-2].getNode(); 2326 RecordedNodes.push_back(std::make_pair(N, Parent)); 2327 continue; 2328 } 2329 2330 case OPC_RecordChild0: case OPC_RecordChild1: 2331 case OPC_RecordChild2: case OPC_RecordChild3: 2332 case OPC_RecordChild4: case OPC_RecordChild5: 2333 case OPC_RecordChild6: case OPC_RecordChild7: { 2334 unsigned ChildNo = Opcode-OPC_RecordChild0; 2335 if (ChildNo >= N.getNumOperands()) 2336 break; // Match fails if out of range child #. 2337 2338 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2339 N.getNode())); 2340 continue; 2341 } 2342 case OPC_RecordMemRef: 2343 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2344 continue; 2345 2346 case OPC_CaptureGlueInput: 2347 // If the current node has an input glue, capture it in InputGlue. 2348 if (N->getNumOperands() != 0 && 2349 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2350 InputGlue = N->getOperand(N->getNumOperands()-1); 2351 continue; 2352 2353 case OPC_MoveChild: { 2354 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2355 if (ChildNo >= N.getNumOperands()) 2356 break; // Match fails if out of range child #. 2357 N = N.getOperand(ChildNo); 2358 NodeStack.push_back(N); 2359 continue; 2360 } 2361 2362 case OPC_MoveParent: 2363 // Pop the current node off the NodeStack. 2364 NodeStack.pop_back(); 2365 assert(!NodeStack.empty() && "Node stack imbalance!"); 2366 N = NodeStack.back(); 2367 continue; 2368 2369 case OPC_CheckSame: 2370 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2371 continue; 2372 case OPC_CheckPatternPredicate: 2373 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2374 continue; 2375 case OPC_CheckPredicate: 2376 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2377 N.getNode())) 2378 break; 2379 continue; 2380 case OPC_CheckComplexPat: { 2381 unsigned CPNum = MatcherTable[MatcherIndex++]; 2382 unsigned RecNo = MatcherTable[MatcherIndex++]; 2383 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2384 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2385 RecordedNodes[RecNo].first, CPNum, 2386 RecordedNodes)) 2387 break; 2388 continue; 2389 } 2390 case OPC_CheckOpcode: 2391 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2392 continue; 2393 2394 case OPC_CheckType: 2395 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2396 continue; 2397 2398 case OPC_SwitchOpcode: { 2399 unsigned CurNodeOpcode = N.getOpcode(); 2400 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2401 unsigned CaseSize; 2402 while (1) { 2403 // Get the size of this case. 2404 CaseSize = MatcherTable[MatcherIndex++]; 2405 if (CaseSize & 128) 2406 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2407 if (CaseSize == 0) break; 2408 2409 uint16_t Opc = MatcherTable[MatcherIndex++]; 2410 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2411 2412 // If the opcode matches, then we will execute this case. 2413 if (CurNodeOpcode == Opc) 2414 break; 2415 2416 // Otherwise, skip over this case. 2417 MatcherIndex += CaseSize; 2418 } 2419 2420 // If no cases matched, bail out. 2421 if (CaseSize == 0) break; 2422 2423 // Otherwise, execute the case we found. 2424 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2425 << " to " << MatcherIndex << "\n"); 2426 continue; 2427 } 2428 2429 case OPC_SwitchType: { 2430 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2431 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2432 unsigned CaseSize; 2433 while (1) { 2434 // Get the size of this case. 2435 CaseSize = MatcherTable[MatcherIndex++]; 2436 if (CaseSize & 128) 2437 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2438 if (CaseSize == 0) break; 2439 2440 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2441 if (CaseVT == MVT::iPTR) 2442 CaseVT = TLI.getPointerTy(); 2443 2444 // If the VT matches, then we will execute this case. 2445 if (CurNodeVT == CaseVT) 2446 break; 2447 2448 // Otherwise, skip over this case. 2449 MatcherIndex += CaseSize; 2450 } 2451 2452 // If no cases matched, bail out. 2453 if (CaseSize == 0) break; 2454 2455 // Otherwise, execute the case we found. 2456 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2457 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2458 continue; 2459 } 2460 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2461 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2462 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2463 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2464 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2465 Opcode-OPC_CheckChild0Type)) 2466 break; 2467 continue; 2468 case OPC_CheckCondCode: 2469 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2470 continue; 2471 case OPC_CheckValueType: 2472 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2473 continue; 2474 case OPC_CheckInteger: 2475 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2476 continue; 2477 case OPC_CheckAndImm: 2478 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2479 continue; 2480 case OPC_CheckOrImm: 2481 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2482 continue; 2483 2484 case OPC_CheckFoldableChainNode: { 2485 assert(NodeStack.size() != 1 && "No parent node"); 2486 // Verify that all intermediate nodes between the root and this one have 2487 // a single use. 2488 bool HasMultipleUses = false; 2489 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2490 if (!NodeStack[i].hasOneUse()) { 2491 HasMultipleUses = true; 2492 break; 2493 } 2494 if (HasMultipleUses) break; 2495 2496 // Check to see that the target thinks this is profitable to fold and that 2497 // we can fold it without inducing cycles in the graph. 2498 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2499 NodeToMatch) || 2500 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2501 NodeToMatch, OptLevel, 2502 true/*We validate our own chains*/)) 2503 break; 2504 2505 continue; 2506 } 2507 case OPC_EmitInteger: { 2508 MVT::SimpleValueType VT = 2509 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2510 int64_t Val = MatcherTable[MatcherIndex++]; 2511 if (Val & 128) 2512 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2513 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2514 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2515 continue; 2516 } 2517 case OPC_EmitRegister: { 2518 MVT::SimpleValueType VT = 2519 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2520 unsigned RegNo = MatcherTable[MatcherIndex++]; 2521 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2522 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2523 continue; 2524 } 2525 case OPC_EmitRegister2: { 2526 // For targets w/ more than 256 register names, the register enum 2527 // values are stored in two bytes in the matcher table (just like 2528 // opcodes). 2529 MVT::SimpleValueType VT = 2530 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2531 unsigned RegNo = MatcherTable[MatcherIndex++]; 2532 RegNo |= MatcherTable[MatcherIndex++] << 8; 2533 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2534 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2535 continue; 2536 } 2537 2538 case OPC_EmitConvertToTarget: { 2539 // Convert from IMM/FPIMM to target version. 2540 unsigned RecNo = MatcherTable[MatcherIndex++]; 2541 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2542 SDValue Imm = RecordedNodes[RecNo].first; 2543 2544 if (Imm->getOpcode() == ISD::Constant) { 2545 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2546 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2547 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2548 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2549 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2550 } 2551 2552 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2553 continue; 2554 } 2555 2556 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2557 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2558 // These are space-optimized forms of OPC_EmitMergeInputChains. 2559 assert(InputChain.getNode() == 0 && 2560 "EmitMergeInputChains should be the first chain producing node"); 2561 assert(ChainNodesMatched.empty() && 2562 "Should only have one EmitMergeInputChains per match"); 2563 2564 // Read all of the chained nodes. 2565 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2566 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2567 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2568 2569 // FIXME: What if other value results of the node have uses not matched 2570 // by this pattern? 2571 if (ChainNodesMatched.back() != NodeToMatch && 2572 !RecordedNodes[RecNo].first.hasOneUse()) { 2573 ChainNodesMatched.clear(); 2574 break; 2575 } 2576 2577 // Merge the input chains if they are not intra-pattern references. 2578 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2579 2580 if (InputChain.getNode() == 0) 2581 break; // Failed to merge. 2582 continue; 2583 } 2584 2585 case OPC_EmitMergeInputChains: { 2586 assert(InputChain.getNode() == 0 && 2587 "EmitMergeInputChains should be the first chain producing node"); 2588 // This node gets a list of nodes we matched in the input that have 2589 // chains. We want to token factor all of the input chains to these nodes 2590 // together. However, if any of the input chains is actually one of the 2591 // nodes matched in this pattern, then we have an intra-match reference. 2592 // Ignore these because the newly token factored chain should not refer to 2593 // the old nodes. 2594 unsigned NumChains = MatcherTable[MatcherIndex++]; 2595 assert(NumChains != 0 && "Can't TF zero chains"); 2596 2597 assert(ChainNodesMatched.empty() && 2598 "Should only have one EmitMergeInputChains per match"); 2599 2600 // Read all of the chained nodes. 2601 for (unsigned i = 0; i != NumChains; ++i) { 2602 unsigned RecNo = MatcherTable[MatcherIndex++]; 2603 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2604 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2605 2606 // FIXME: What if other value results of the node have uses not matched 2607 // by this pattern? 2608 if (ChainNodesMatched.back() != NodeToMatch && 2609 !RecordedNodes[RecNo].first.hasOneUse()) { 2610 ChainNodesMatched.clear(); 2611 break; 2612 } 2613 } 2614 2615 // If the inner loop broke out, the match fails. 2616 if (ChainNodesMatched.empty()) 2617 break; 2618 2619 // Merge the input chains if they are not intra-pattern references. 2620 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2621 2622 if (InputChain.getNode() == 0) 2623 break; // Failed to merge. 2624 2625 continue; 2626 } 2627 2628 case OPC_EmitCopyToReg: { 2629 unsigned RecNo = MatcherTable[MatcherIndex++]; 2630 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2631 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2632 2633 if (InputChain.getNode() == 0) 2634 InputChain = CurDAG->getEntryNode(); 2635 2636 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2637 DestPhysReg, RecordedNodes[RecNo].first, 2638 InputGlue); 2639 2640 InputGlue = InputChain.getValue(1); 2641 continue; 2642 } 2643 2644 case OPC_EmitNodeXForm: { 2645 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2646 unsigned RecNo = MatcherTable[MatcherIndex++]; 2647 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2648 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2649 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2650 continue; 2651 } 2652 2653 case OPC_EmitNode: 2654 case OPC_MorphNodeTo: { 2655 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2656 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2657 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2658 // Get the result VT list. 2659 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2660 SmallVector<EVT, 4> VTs; 2661 for (unsigned i = 0; i != NumVTs; ++i) { 2662 MVT::SimpleValueType VT = 2663 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2664 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2665 VTs.push_back(VT); 2666 } 2667 2668 if (EmitNodeInfo & OPFL_Chain) 2669 VTs.push_back(MVT::Other); 2670 if (EmitNodeInfo & OPFL_GlueOutput) 2671 VTs.push_back(MVT::Glue); 2672 2673 // This is hot code, so optimize the two most common cases of 1 and 2 2674 // results. 2675 SDVTList VTList; 2676 if (VTs.size() == 1) 2677 VTList = CurDAG->getVTList(VTs[0]); 2678 else if (VTs.size() == 2) 2679 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2680 else 2681 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2682 2683 // Get the operand list. 2684 unsigned NumOps = MatcherTable[MatcherIndex++]; 2685 SmallVector<SDValue, 8> Ops; 2686 for (unsigned i = 0; i != NumOps; ++i) { 2687 unsigned RecNo = MatcherTable[MatcherIndex++]; 2688 if (RecNo & 128) 2689 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2690 2691 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2692 Ops.push_back(RecordedNodes[RecNo].first); 2693 } 2694 2695 // If there are variadic operands to add, handle them now. 2696 if (EmitNodeInfo & OPFL_VariadicInfo) { 2697 // Determine the start index to copy from. 2698 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2699 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2700 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2701 "Invalid variadic node"); 2702 // Copy all of the variadic operands, not including a potential glue 2703 // input. 2704 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2705 i != e; ++i) { 2706 SDValue V = NodeToMatch->getOperand(i); 2707 if (V.getValueType() == MVT::Glue) break; 2708 Ops.push_back(V); 2709 } 2710 } 2711 2712 // If this has chain/glue inputs, add them. 2713 if (EmitNodeInfo & OPFL_Chain) 2714 Ops.push_back(InputChain); 2715 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2716 Ops.push_back(InputGlue); 2717 2718 // Create the node. 2719 SDNode *Res = 0; 2720 if (Opcode != OPC_MorphNodeTo) { 2721 // If this is a normal EmitNode command, just create the new node and 2722 // add the results to the RecordedNodes list. 2723 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2724 VTList, Ops); 2725 2726 // Add all the non-glue/non-chain results to the RecordedNodes list. 2727 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2728 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2729 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2730 (SDNode*) 0)); 2731 } 2732 2733 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2734 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2735 EmitNodeInfo); 2736 } else { 2737 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2738 // We will visit the equivalent node later. 2739 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2740 return 0; 2741 } 2742 2743 // If the node had chain/glue results, update our notion of the current 2744 // chain and glue. 2745 if (EmitNodeInfo & OPFL_GlueOutput) { 2746 InputGlue = SDValue(Res, VTs.size()-1); 2747 if (EmitNodeInfo & OPFL_Chain) 2748 InputChain = SDValue(Res, VTs.size()-2); 2749 } else if (EmitNodeInfo & OPFL_Chain) 2750 InputChain = SDValue(Res, VTs.size()-1); 2751 2752 // If the OPFL_MemRefs glue is set on this node, slap all of the 2753 // accumulated memrefs onto it. 2754 // 2755 // FIXME: This is vastly incorrect for patterns with multiple outputs 2756 // instructions that access memory and for ComplexPatterns that match 2757 // loads. 2758 if (EmitNodeInfo & OPFL_MemRefs) { 2759 // Only attach load or store memory operands if the generated 2760 // instruction may load or store. 2761 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2762 bool mayLoad = MCID.mayLoad(); 2763 bool mayStore = MCID.mayStore(); 2764 2765 unsigned NumMemRefs = 0; 2766 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2767 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2768 if ((*I)->isLoad()) { 2769 if (mayLoad) 2770 ++NumMemRefs; 2771 } else if ((*I)->isStore()) { 2772 if (mayStore) 2773 ++NumMemRefs; 2774 } else { 2775 ++NumMemRefs; 2776 } 2777 } 2778 2779 MachineSDNode::mmo_iterator MemRefs = 2780 MF->allocateMemRefsArray(NumMemRefs); 2781 2782 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2783 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2784 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2785 if ((*I)->isLoad()) { 2786 if (mayLoad) 2787 *MemRefsPos++ = *I; 2788 } else if ((*I)->isStore()) { 2789 if (mayStore) 2790 *MemRefsPos++ = *I; 2791 } else { 2792 *MemRefsPos++ = *I; 2793 } 2794 } 2795 2796 cast<MachineSDNode>(Res) 2797 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2798 } 2799 2800 DEBUG(dbgs() << " " 2801 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2802 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 2803 2804 // If this was a MorphNodeTo then we're completely done! 2805 if (Opcode == OPC_MorphNodeTo) { 2806 // Update chain and glue uses. 2807 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2808 InputGlue, GlueResultNodesMatched, true); 2809 return Res; 2810 } 2811 2812 continue; 2813 } 2814 2815 case OPC_MarkGlueResults: { 2816 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2817 2818 // Read and remember all the glue-result nodes. 2819 for (unsigned i = 0; i != NumNodes; ++i) { 2820 unsigned RecNo = MatcherTable[MatcherIndex++]; 2821 if (RecNo & 128) 2822 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2823 2824 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2825 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2826 } 2827 continue; 2828 } 2829 2830 case OPC_CompleteMatch: { 2831 // The match has been completed, and any new nodes (if any) have been 2832 // created. Patch up references to the matched dag to use the newly 2833 // created nodes. 2834 unsigned NumResults = MatcherTable[MatcherIndex++]; 2835 2836 for (unsigned i = 0; i != NumResults; ++i) { 2837 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2838 if (ResSlot & 128) 2839 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2840 2841 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2842 SDValue Res = RecordedNodes[ResSlot].first; 2843 2844 assert(i < NodeToMatch->getNumValues() && 2845 NodeToMatch->getValueType(i) != MVT::Other && 2846 NodeToMatch->getValueType(i) != MVT::Glue && 2847 "Invalid number of results to complete!"); 2848 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2849 NodeToMatch->getValueType(i) == MVT::iPTR || 2850 Res.getValueType() == MVT::iPTR || 2851 NodeToMatch->getValueType(i).getSizeInBits() == 2852 Res.getValueType().getSizeInBits()) && 2853 "invalid replacement"); 2854 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2855 } 2856 2857 // If the root node defines glue, add it to the glue nodes to update list. 2858 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2859 GlueResultNodesMatched.push_back(NodeToMatch); 2860 2861 // Update chain and glue uses. 2862 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2863 InputGlue, GlueResultNodesMatched, false); 2864 2865 assert(NodeToMatch->use_empty() && 2866 "Didn't replace all uses of the node?"); 2867 2868 // FIXME: We just return here, which interacts correctly with SelectRoot 2869 // above. We should fix this to not return an SDNode* anymore. 2870 return 0; 2871 } 2872 } 2873 2874 // If the code reached this point, then the match failed. See if there is 2875 // another child to try in the current 'Scope', otherwise pop it until we 2876 // find a case to check. 2877 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2878 ++NumDAGIselRetries; 2879 while (1) { 2880 if (MatchScopes.empty()) { 2881 CannotYetSelect(NodeToMatch); 2882 return 0; 2883 } 2884 2885 // Restore the interpreter state back to the point where the scope was 2886 // formed. 2887 MatchScope &LastScope = MatchScopes.back(); 2888 RecordedNodes.resize(LastScope.NumRecordedNodes); 2889 NodeStack.clear(); 2890 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2891 N = NodeStack.back(); 2892 2893 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2894 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2895 MatcherIndex = LastScope.FailIndex; 2896 2897 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 2898 2899 InputChain = LastScope.InputChain; 2900 InputGlue = LastScope.InputGlue; 2901 if (!LastScope.HasChainNodesMatched) 2902 ChainNodesMatched.clear(); 2903 if (!LastScope.HasGlueResultNodesMatched) 2904 GlueResultNodesMatched.clear(); 2905 2906 // Check to see what the offset is at the new MatcherIndex. If it is zero 2907 // we have reached the end of this scope, otherwise we have another child 2908 // in the current scope to try. 2909 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2910 if (NumToSkip & 128) 2911 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2912 2913 // If we have another child in this scope to match, update FailIndex and 2914 // try it. 2915 if (NumToSkip != 0) { 2916 LastScope.FailIndex = MatcherIndex+NumToSkip; 2917 break; 2918 } 2919 2920 // End of this scope, pop it and try the next child in the containing 2921 // scope. 2922 MatchScopes.pop_back(); 2923 } 2924 } 2925} 2926 2927 2928 2929void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2930 std::string msg; 2931 raw_string_ostream Msg(msg); 2932 Msg << "Cannot select: "; 2933 2934 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2935 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2936 N->getOpcode() != ISD::INTRINSIC_VOID) { 2937 N->printrFull(Msg, CurDAG); 2938 Msg << "\nIn function: " << MF->getName(); 2939 } else { 2940 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2941 unsigned iid = 2942 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2943 if (iid < Intrinsic::num_intrinsics) 2944 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2945 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2946 Msg << "target intrinsic %" << TII->getName(iid); 2947 else 2948 Msg << "unknown intrinsic #" << iid; 2949 } 2950 report_fatal_error(Msg.str()); 2951} 2952 2953char SelectionDAGISel::ID = 0; 2954