SelectionDAGISel.cpp revision b13033f61c897224a0be2784faa721ff294c5254
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183unsigned SelectionDAGISel::MakeReg(EVT VT) { 184 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 196 // Do some sanity-checking on the command-line options. 197 assert((!EnableFastISelVerbose || EnableFastISel) && 198 "-fast-isel-verbose requires -fast-isel"); 199 assert((!EnableFastISelAbort || EnableFastISel) && 200 "-fast-isel-abort requires -fast-isel"); 201 202 Function &Fn = *mf.getFunction(); 203 const TargetInstrInfo &TII = *TM.getInstrInfo(); 204 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 205 206 MF = &mf; 207 RegInfo = &MF->getRegInfo(); 208 AA = &getAnalysis<AliasAnalysis>(); 209 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 210 211 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 212 213 CurDAG->init(*MF); 214 FuncInfo->set(Fn, *MF, EnableFastISel); 215 SDB->init(GFI, *AA); 216 217 SelectAllBasicBlocks(Fn, *MF, TII); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224#ifndef NDEBUG 225 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 226 "Not all catch info was assigned to a landing pad!"); 227#endif 228 229 FuncInfo->clear(); 230 231 return true; 232} 233 234/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 235/// attached with this instruction. 236static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB, 237 FastISel *FastIS, MachineFunction *MF) { 238 DebugLoc DL = I->getDebugLoc(); 239 if (DL.isUnknown()) return; 240 241 SDB->setCurDebugLoc(DL); 242 243 if (FastIS) 244 FastIS->setCurDebugLoc(DL); 245 246 // If the function doesn't have a default debug location yet, set 247 // it. This is kind of a hack. 248 if (MF->getDefaultDebugLoc().isUnknown()) 249 MF->setDefaultDebugLoc(DL); 250} 251 252/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 253static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 254 SDB->setCurDebugLoc(DebugLoc()); 255 if (FastIS) 256 FastIS->setCurDebugLoc(DebugLoc()); 257} 258 259void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 260 BasicBlock::iterator Begin, 261 BasicBlock::iterator End, 262 bool &HadTailCall) { 263 SDB->setCurrentBasicBlock(BB); 264 265 // Lower all of the non-terminator instructions. If a call is emitted 266 // as a tail call, cease emitting nodes for this block. 267 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 268 SetDebugLoc(I, SDB, 0, MF); 269 270 if (!isa<TerminatorInst>(I)) { 271 SDB->visit(*I); 272 273 // Set the current debug location back to "unknown" so that it doesn't 274 // spuriously apply to subsequent instructions. 275 ResetDebugLoc(SDB, 0); 276 } 277 } 278 279 if (!SDB->HasTailCall) { 280 // Ensure that all instructions which are used outside of their defining 281 // blocks are available as virtual registers. Invoke is handled elsewhere. 282 for (BasicBlock::iterator I = Begin; I != End; ++I) 283 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 284 SDB->CopyToExportRegsIfNeeded(I); 285 286 // Handle PHI nodes in successor blocks. 287 if (End == LLVMBB->end()) { 288 HandlePHINodesInSuccessorBlocks(LLVMBB); 289 290 // Lower the terminator after the copies are emitted. 291 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 292 SDB->visit(*LLVMBB->getTerminator()); 293 ResetDebugLoc(SDB, 0); 294 } 295 } 296 297 // Make sure the root of the DAG is up-to-date. 298 CurDAG->setRoot(SDB->getControlRoot()); 299 300 // Final step, emit the lowered DAG as machine code. 301 CodeGenAndEmitDAG(); 302 HadTailCall = SDB->HasTailCall; 303 SDB->clear(); 304} 305 306namespace { 307/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 308/// nodes from the worklist. 309class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 310 SmallVector<SDNode*, 128> &Worklist; 311 SmallPtrSet<SDNode*, 128> &InWorklist; 312public: 313 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 314 SmallPtrSet<SDNode*, 128> &inwl) 315 : Worklist(wl), InWorklist(inwl) {} 316 317 void RemoveFromWorklist(SDNode *N) { 318 if (!InWorklist.erase(N)) return; 319 320 SmallVector<SDNode*, 128>::iterator I = 321 std::find(Worklist.begin(), Worklist.end(), N); 322 assert(I != Worklist.end() && "Not in worklist"); 323 324 *I = Worklist.back(); 325 Worklist.pop_back(); 326 } 327 328 virtual void NodeDeleted(SDNode *N, SDNode *E) { 329 RemoveFromWorklist(N); 330 } 331 332 virtual void NodeUpdated(SDNode *N) { 333 // Ignore updates. 334 } 335}; 336} 337 338/// TrivialTruncElim - Eliminate some trivial nops that can result from 339/// ShrinkDemandedOps: (trunc (ext n)) -> n. 340static bool TrivialTruncElim(SDValue Op, 341 TargetLowering::TargetLoweringOpt &TLO) { 342 SDValue N0 = Op.getOperand(0); 343 EVT VT = Op.getValueType(); 344 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 345 N0.getOpcode() == ISD::SIGN_EXTEND || 346 N0.getOpcode() == ISD::ANY_EXTEND) && 347 N0.getOperand(0).getValueType() == VT) { 348 return TLO.CombineTo(Op, N0.getOperand(0)); 349 } 350 return false; 351} 352 353/// ShrinkDemandedOps - A late transformation pass that shrink expressions 354/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 355/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 356void SelectionDAGISel::ShrinkDemandedOps() { 357 SmallVector<SDNode*, 128> Worklist; 358 SmallPtrSet<SDNode*, 128> InWorklist; 359 360 // Add all the dag nodes to the worklist. 361 Worklist.reserve(CurDAG->allnodes_size()); 362 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 363 E = CurDAG->allnodes_end(); I != E; ++I) { 364 Worklist.push_back(I); 365 InWorklist.insert(I); 366 } 367 368 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 369 while (!Worklist.empty()) { 370 SDNode *N = Worklist.pop_back_val(); 371 InWorklist.erase(N); 372 373 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 374 // Deleting this node may make its operands dead, add them to the worklist 375 // if they aren't already there. 376 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 377 if (InWorklist.insert(N->getOperand(i).getNode())) 378 Worklist.push_back(N->getOperand(i).getNode()); 379 380 CurDAG->DeleteNode(N); 381 continue; 382 } 383 384 // Run ShrinkDemandedOp on scalar binary operations. 385 if (N->getNumValues() != 1 || 386 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 387 continue; 388 389 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 390 APInt Demanded = APInt::getAllOnesValue(BitWidth); 391 APInt KnownZero, KnownOne; 392 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 393 KnownZero, KnownOne, TLO) && 394 (N->getOpcode() != ISD::TRUNCATE || 395 !TrivialTruncElim(SDValue(N, 0), TLO))) 396 continue; 397 398 // Revisit the node. 399 assert(!InWorklist.count(N) && "Already in worklist"); 400 Worklist.push_back(N); 401 InWorklist.insert(N); 402 403 // Replace the old value with the new one. 404 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 405 TLO.Old.getNode()->dump(CurDAG); 406 errs() << "\nWith: "; 407 TLO.New.getNode()->dump(CurDAG); 408 errs() << '\n'); 409 410 if (InWorklist.insert(TLO.New.getNode())) 411 Worklist.push_back(TLO.New.getNode()); 412 413 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 414 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 415 416 if (!TLO.Old.getNode()->use_empty()) continue; 417 418 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 419 i != e; ++i) { 420 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 421 if (OpNode->hasOneUse()) { 422 // Add OpNode to the end of the list to revisit. 423 DeadNodes.RemoveFromWorklist(OpNode); 424 Worklist.push_back(OpNode); 425 InWorklist.insert(OpNode); 426 } 427 } 428 429 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 430 CurDAG->DeleteNode(TLO.Old.getNode()); 431 } 432} 433 434void SelectionDAGISel::ComputeLiveOutVRegInfo() { 435 SmallPtrSet<SDNode*, 128> VisitedNodes; 436 SmallVector<SDNode*, 128> Worklist; 437 438 Worklist.push_back(CurDAG->getRoot().getNode()); 439 440 APInt Mask; 441 APInt KnownZero; 442 APInt KnownOne; 443 444 do { 445 SDNode *N = Worklist.pop_back_val(); 446 447 // If we've already seen this node, ignore it. 448 if (!VisitedNodes.insert(N)) 449 continue; 450 451 // Otherwise, add all chain operands to the worklist. 452 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 453 if (N->getOperand(i).getValueType() == MVT::Other) 454 Worklist.push_back(N->getOperand(i).getNode()); 455 456 // If this is a CopyToReg with a vreg dest, process it. 457 if (N->getOpcode() != ISD::CopyToReg) 458 continue; 459 460 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 461 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 462 continue; 463 464 // Ignore non-scalar or non-integer values. 465 SDValue Src = N->getOperand(2); 466 EVT SrcVT = Src.getValueType(); 467 if (!SrcVT.isInteger() || SrcVT.isVector()) 468 continue; 469 470 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 471 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 472 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 473 474 // Only install this information if it tells us something. 475 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 476 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 477 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 478 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 479 FunctionLoweringInfo::LiveOutInfo &LOI = 480 FuncInfo->LiveOutRegInfo[DestReg]; 481 LOI.NumSignBits = NumSignBits; 482 LOI.KnownOne = KnownOne; 483 LOI.KnownZero = KnownZero; 484 } 485 } while (!Worklist.empty()); 486} 487 488void SelectionDAGISel::CodeGenAndEmitDAG() { 489 std::string GroupName; 490 if (TimePassesIsEnabled) 491 GroupName = "Instruction Selection and Scheduling"; 492 std::string BlockName; 493 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 494 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 495 ViewSUnitDAGs) 496 BlockName = MF->getFunction()->getNameStr() + ":" + 497 BB->getBasicBlock()->getNameStr(); 498 499 DEBUG(dbgs() << "Initial selection DAG:\n"); 500 DEBUG(CurDAG->dump()); 501 502 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 503 504 // Run the DAG combiner in pre-legalize mode. 505 if (TimePassesIsEnabled) { 506 NamedRegionTimer T("DAG Combining 1", GroupName); 507 CurDAG->Combine(Unrestricted, *AA, OptLevel); 508 } else { 509 CurDAG->Combine(Unrestricted, *AA, OptLevel); 510 } 511 512 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 513 DEBUG(CurDAG->dump()); 514 515 // Second step, hack on the DAG until it only uses operations and types that 516 // the target supports. 517 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 518 BlockName); 519 520 bool Changed; 521 if (TimePassesIsEnabled) { 522 NamedRegionTimer T("Type Legalization", GroupName); 523 Changed = CurDAG->LegalizeTypes(); 524 } else { 525 Changed = CurDAG->LegalizeTypes(); 526 } 527 528 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 529 DEBUG(CurDAG->dump()); 530 531 if (Changed) { 532 if (ViewDAGCombineLT) 533 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 534 535 // Run the DAG combiner in post-type-legalize mode. 536 if (TimePassesIsEnabled) { 537 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 538 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 539 } else { 540 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 541 } 542 543 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 544 DEBUG(CurDAG->dump()); 545 } 546 547 if (TimePassesIsEnabled) { 548 NamedRegionTimer T("Vector Legalization", GroupName); 549 Changed = CurDAG->LegalizeVectors(); 550 } else { 551 Changed = CurDAG->LegalizeVectors(); 552 } 553 554 if (Changed) { 555 if (TimePassesIsEnabled) { 556 NamedRegionTimer T("Type Legalization 2", GroupName); 557 CurDAG->LegalizeTypes(); 558 } else { 559 CurDAG->LegalizeTypes(); 560 } 561 562 if (ViewDAGCombineLT) 563 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 564 565 // Run the DAG combiner in post-type-legalize mode. 566 if (TimePassesIsEnabled) { 567 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 568 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 569 } else { 570 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 571 } 572 573 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 574 DEBUG(CurDAG->dump()); 575 } 576 577 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 578 579 if (TimePassesIsEnabled) { 580 NamedRegionTimer T("DAG Legalization", GroupName); 581 CurDAG->Legalize(OptLevel); 582 } else { 583 CurDAG->Legalize(OptLevel); 584 } 585 586 DEBUG(dbgs() << "Legalized selection DAG:\n"); 587 DEBUG(CurDAG->dump()); 588 589 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 590 591 // Run the DAG combiner in post-legalize mode. 592 if (TimePassesIsEnabled) { 593 NamedRegionTimer T("DAG Combining 2", GroupName); 594 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 595 } else { 596 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 597 } 598 599 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 600 DEBUG(CurDAG->dump()); 601 602 if (OptLevel != CodeGenOpt::None) { 603 ShrinkDemandedOps(); 604 ComputeLiveOutVRegInfo(); 605 } 606 607 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 608 609 // Third, instruction select all of the operations to machine code, adding the 610 // code to the MachineBasicBlock. 611 if (TimePassesIsEnabled) { 612 NamedRegionTimer T("Instruction Selection", GroupName); 613 DoInstructionSelection(); 614 } else { 615 DoInstructionSelection(); 616 } 617 618 DEBUG(dbgs() << "Selected selection DAG:\n"); 619 DEBUG(CurDAG->dump()); 620 621 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 622 623 // Schedule machine code. 624 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 625 if (TimePassesIsEnabled) { 626 NamedRegionTimer T("Instruction Scheduling", GroupName); 627 Scheduler->Run(CurDAG, BB, BB->end()); 628 } else { 629 Scheduler->Run(CurDAG, BB, BB->end()); 630 } 631 632 if (ViewSUnitDAGs) Scheduler->viewGraph(); 633 634 // Emit machine code to BB. This can change 'BB' to the last block being 635 // inserted into. 636 if (TimePassesIsEnabled) { 637 NamedRegionTimer T("Instruction Creation", GroupName); 638 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 639 } else { 640 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 641 } 642 643 // Free the scheduler state. 644 if (TimePassesIsEnabled) { 645 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 646 delete Scheduler; 647 } else { 648 delete Scheduler; 649 } 650 651 DEBUG(dbgs() << "Selected machine code:\n"); 652 DEBUG(BB->dump()); 653} 654 655void SelectionDAGISel::DoInstructionSelection() { 656 DEBUG(errs() << "===== Instruction selection begins:\n"); 657 658 PreprocessISelDAG(); 659 660 // Select target instructions for the DAG. 661 { 662 // Number all nodes with a topological order and set DAGSize. 663 DAGSize = CurDAG->AssignTopologicalOrder(); 664 665 // Create a dummy node (which is not added to allnodes), that adds 666 // a reference to the root node, preventing it from being deleted, 667 // and tracking any changes of the root. 668 HandleSDNode Dummy(CurDAG->getRoot()); 669 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 670 ++ISelPosition; 671 672 // The AllNodes list is now topological-sorted. Visit the 673 // nodes by starting at the end of the list (the root of the 674 // graph) and preceding back toward the beginning (the entry 675 // node). 676 while (ISelPosition != CurDAG->allnodes_begin()) { 677 SDNode *Node = --ISelPosition; 678 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 679 // but there are currently some corner cases that it misses. Also, this 680 // makes it theoretically possible to disable the DAGCombiner. 681 if (Node->use_empty()) 682 continue; 683 684 SDNode *ResNode = Select(Node); 685 686 // FIXME: This is pretty gross. 'Select' should be changed to not return 687 // anything at all and this code should be nuked with a tactical strike. 688 689 // If node should not be replaced, continue with the next one. 690 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 691 continue; 692 // Replace node. 693 if (ResNode) 694 ReplaceUses(Node, ResNode); 695 696 // If after the replacement this node is not used any more, 697 // remove this dead node. 698 if (Node->use_empty()) { // Don't delete EntryToken, etc. 699 ISelUpdater ISU(ISelPosition); 700 CurDAG->RemoveDeadNode(Node, &ISU); 701 } 702 } 703 704 CurDAG->setRoot(Dummy.getValue()); 705 } 706 DEBUG(errs() << "===== Instruction selection ends:\n"); 707 708 PostprocessISelDAG(); 709} 710 711 712void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 713 MachineFunction &MF, 714 const TargetInstrInfo &TII) { 715 // Initialize the Fast-ISel state, if needed. 716 FastISel *FastIS = 0; 717 if (EnableFastISel) 718 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 719 FuncInfo->StaticAllocaMap 720#ifndef NDEBUG 721 , FuncInfo->CatchInfoLost 722#endif 723 ); 724 725 // Iterate over all basic blocks in the function. 726 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 727 BasicBlock *LLVMBB = &*I; 728 BB = FuncInfo->MBBMap[LLVMBB]; 729 730 BasicBlock::iterator const Begin = LLVMBB->begin(); 731 BasicBlock::iterator const End = LLVMBB->end(); 732 BasicBlock::iterator BI = Begin; 733 734 // Lower any arguments needed in this block if this is the entry block. 735 bool SuppressFastISel = false; 736 if (LLVMBB == &Fn.getEntryBlock()) { 737 LowerArguments(LLVMBB); 738 739 // If any of the arguments has the byval attribute, forgo 740 // fast-isel in the entry block. 741 if (FastIS) { 742 unsigned j = 1; 743 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 744 I != E; ++I, ++j) 745 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 746 if (EnableFastISelVerbose || EnableFastISelAbort) 747 dbgs() << "FastISel skips entry block due to byval argument\n"; 748 SuppressFastISel = true; 749 break; 750 } 751 } 752 } 753 754 if (BB->isLandingPad()) { 755 // Add a label to mark the beginning of the landing pad. Deletion of the 756 // landing pad can thus be detected via the MachineModuleInfo. 757 MCSymbol *Label = MF.getMMI().addLandingPad(BB); 758 759 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 760 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 761 762 // Mark exception register as live in. 763 unsigned Reg = TLI.getExceptionAddressRegister(); 764 if (Reg) BB->addLiveIn(Reg); 765 766 // Mark exception selector register as live in. 767 Reg = TLI.getExceptionSelectorRegister(); 768 if (Reg) BB->addLiveIn(Reg); 769 770 // FIXME: Hack around an exception handling flaw (PR1508): the personality 771 // function and list of typeids logically belong to the invoke (or, if you 772 // like, the basic block containing the invoke), and need to be associated 773 // with it in the dwarf exception handling tables. Currently however the 774 // information is provided by an intrinsic (eh.selector) that can be moved 775 // to unexpected places by the optimizers: if the unwind edge is critical, 776 // then breaking it can result in the intrinsics being in the successor of 777 // the landing pad, not the landing pad itself. This results 778 // in exceptions not being caught because no typeids are associated with 779 // the invoke. This may not be the only way things can go wrong, but it 780 // is the only way we try to work around for the moment. 781 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 782 783 if (Br && Br->isUnconditional()) { // Critical edge? 784 BasicBlock::iterator I, E; 785 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 786 if (isa<EHSelectorInst>(I)) 787 break; 788 789 if (I == E) 790 // No catch info found - try to extract some from the successor. 791 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo); 792 } 793 } 794 795 // Before doing SelectionDAG ISel, see if FastISel has been requested. 796 if (FastIS && !SuppressFastISel) { 797 // Emit code for any incoming arguments. This must happen before 798 // beginning FastISel on the entry block. 799 if (LLVMBB == &Fn.getEntryBlock()) { 800 CurDAG->setRoot(SDB->getControlRoot()); 801 CodeGenAndEmitDAG(); 802 SDB->clear(); 803 } 804 FastIS->startNewBlock(BB); 805 // Do FastISel on as many instructions as possible. 806 for (; BI != End; ++BI) { 807 // Just before the terminator instruction, insert instructions to 808 // feed PHI nodes in successor blocks. 809 if (isa<TerminatorInst>(BI)) 810 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 811 ++NumFastIselFailures; 812 ResetDebugLoc(SDB, FastIS); 813 if (EnableFastISelVerbose || EnableFastISelAbort) { 814 dbgs() << "FastISel miss: "; 815 BI->dump(); 816 } 817 assert(!EnableFastISelAbort && 818 "FastISel didn't handle a PHI in a successor"); 819 break; 820 } 821 822 SetDebugLoc(BI, SDB, FastIS, &MF); 823 824 // Try to select the instruction with FastISel. 825 if (FastIS->SelectInstruction(BI)) { 826 ResetDebugLoc(SDB, FastIS); 827 continue; 828 } 829 830 // Clear out the debug location so that it doesn't carry over to 831 // unrelated instructions. 832 ResetDebugLoc(SDB, FastIS); 833 834 // Then handle certain instructions as single-LLVM-Instruction blocks. 835 if (isa<CallInst>(BI)) { 836 ++NumFastIselFailures; 837 if (EnableFastISelVerbose || EnableFastISelAbort) { 838 dbgs() << "FastISel missed call: "; 839 BI->dump(); 840 } 841 842 if (!BI->getType()->isVoidTy()) { 843 unsigned &R = FuncInfo->ValueMap[BI]; 844 if (!R) 845 R = FuncInfo->CreateRegForValue(BI); 846 } 847 848 bool HadTailCall = false; 849 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 850 851 // If the call was emitted as a tail call, we're done with the block. 852 if (HadTailCall) { 853 BI = End; 854 break; 855 } 856 857 // If the instruction was codegen'd with multiple blocks, 858 // inform the FastISel object where to resume inserting. 859 FastIS->setCurrentBlock(BB); 860 continue; 861 } 862 863 // Otherwise, give up on FastISel for the rest of the block. 864 // For now, be a little lenient about non-branch terminators. 865 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 866 ++NumFastIselFailures; 867 if (EnableFastISelVerbose || EnableFastISelAbort) { 868 dbgs() << "FastISel miss: "; 869 BI->dump(); 870 } 871 if (EnableFastISelAbort) 872 // The "fast" selector couldn't handle something and bailed. 873 // For the purpose of debugging, just abort. 874 llvm_unreachable("FastISel didn't select the entire block"); 875 } 876 break; 877 } 878 } 879 880 // Run SelectionDAG instruction selection on the remainder of the block 881 // not handled by FastISel. If FastISel is not run, this is the entire 882 // block. 883 if (BI != End) { 884 bool HadTailCall; 885 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 886 } 887 888 FinishBasicBlock(); 889 } 890 891 delete FastIS; 892} 893 894void 895SelectionDAGISel::FinishBasicBlock() { 896 897 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 898 DEBUG(BB->dump()); 899 900 DEBUG(dbgs() << "Total amount of phi nodes to update: " 901 << SDB->PHINodesToUpdate.size() << "\n"); 902 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 903 dbgs() << "Node " << i << " : (" 904 << SDB->PHINodesToUpdate[i].first 905 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 906 907 // Next, now that we know what the last MBB the LLVM BB expanded is, update 908 // PHI nodes in successors. 909 if (SDB->SwitchCases.empty() && 910 SDB->JTCases.empty() && 911 SDB->BitTestCases.empty()) { 912 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 913 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 914 assert(PHI->isPHI() && 915 "This is not a machine PHI node that we are updating!"); 916 if (!BB->isSuccessor(PHI->getParent())) 917 continue; 918 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 919 false)); 920 PHI->addOperand(MachineOperand::CreateMBB(BB)); 921 } 922 SDB->PHINodesToUpdate.clear(); 923 return; 924 } 925 926 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 927 // Lower header first, if it wasn't already lowered 928 if (!SDB->BitTestCases[i].Emitted) { 929 // Set the current basic block to the mbb we wish to insert the code into 930 BB = SDB->BitTestCases[i].Parent; 931 SDB->setCurrentBasicBlock(BB); 932 // Emit the code 933 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 934 CurDAG->setRoot(SDB->getRoot()); 935 CodeGenAndEmitDAG(); 936 SDB->clear(); 937 } 938 939 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 940 // Set the current basic block to the mbb we wish to insert the code into 941 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 942 SDB->setCurrentBasicBlock(BB); 943 // Emit the code 944 if (j+1 != ej) 945 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 946 SDB->BitTestCases[i].Reg, 947 SDB->BitTestCases[i].Cases[j]); 948 else 949 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 950 SDB->BitTestCases[i].Reg, 951 SDB->BitTestCases[i].Cases[j]); 952 953 954 CurDAG->setRoot(SDB->getRoot()); 955 CodeGenAndEmitDAG(); 956 SDB->clear(); 957 } 958 959 // Update PHI Nodes 960 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 961 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 962 MachineBasicBlock *PHIBB = PHI->getParent(); 963 assert(PHI->isPHI() && 964 "This is not a machine PHI node that we are updating!"); 965 // This is "default" BB. We have two jumps to it. From "header" BB and 966 // from last "case" BB. 967 if (PHIBB == SDB->BitTestCases[i].Default) { 968 PHI->addOperand(MachineOperand:: 969 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 970 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 971 PHI->addOperand(MachineOperand:: 972 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 973 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 974 back().ThisBB)); 975 } 976 // One of "cases" BB. 977 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 978 j != ej; ++j) { 979 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 980 if (cBB->isSuccessor(PHIBB)) { 981 PHI->addOperand(MachineOperand:: 982 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 983 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 984 } 985 } 986 } 987 } 988 SDB->BitTestCases.clear(); 989 990 // If the JumpTable record is filled in, then we need to emit a jump table. 991 // Updating the PHI nodes is tricky in this case, since we need to determine 992 // whether the PHI is a successor of the range check MBB or the jump table MBB 993 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 994 // Lower header first, if it wasn't already lowered 995 if (!SDB->JTCases[i].first.Emitted) { 996 // Set the current basic block to the mbb we wish to insert the code into 997 BB = SDB->JTCases[i].first.HeaderBB; 998 SDB->setCurrentBasicBlock(BB); 999 // Emit the code 1000 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1001 CurDAG->setRoot(SDB->getRoot()); 1002 CodeGenAndEmitDAG(); 1003 SDB->clear(); 1004 } 1005 1006 // Set the current basic block to the mbb we wish to insert the code into 1007 BB = SDB->JTCases[i].second.MBB; 1008 SDB->setCurrentBasicBlock(BB); 1009 // Emit the code 1010 SDB->visitJumpTable(SDB->JTCases[i].second); 1011 CurDAG->setRoot(SDB->getRoot()); 1012 CodeGenAndEmitDAG(); 1013 SDB->clear(); 1014 1015 // Update PHI Nodes 1016 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1017 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1018 MachineBasicBlock *PHIBB = PHI->getParent(); 1019 assert(PHI->isPHI() && 1020 "This is not a machine PHI node that we are updating!"); 1021 // "default" BB. We can go there only from header BB. 1022 if (PHIBB == SDB->JTCases[i].second.Default) { 1023 PHI->addOperand 1024 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1025 PHI->addOperand 1026 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1027 } 1028 // JT BB. Just iterate over successors here 1029 if (BB->isSuccessor(PHIBB)) { 1030 PHI->addOperand 1031 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1032 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1033 } 1034 } 1035 } 1036 SDB->JTCases.clear(); 1037 1038 // If the switch block involved a branch to one of the actual successors, we 1039 // need to update PHI nodes in that block. 1040 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1041 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1042 assert(PHI->isPHI() && 1043 "This is not a machine PHI node that we are updating!"); 1044 if (BB->isSuccessor(PHI->getParent())) { 1045 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1046 false)); 1047 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1048 } 1049 } 1050 1051 // If we generated any switch lowering information, build and codegen any 1052 // additional DAGs necessary. 1053 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1054 // Set the current basic block to the mbb we wish to insert the code into 1055 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1056 SDB->setCurrentBasicBlock(BB); 1057 1058 // Emit the code 1059 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1060 CurDAG->setRoot(SDB->getRoot()); 1061 CodeGenAndEmitDAG(); 1062 1063 // Handle any PHI nodes in successors of this chunk, as if we were coming 1064 // from the original BB before switch expansion. Note that PHI nodes can 1065 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1066 // handle them the right number of times. 1067 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1068 // If new BB's are created during scheduling, the edges may have been 1069 // updated. That is, the edge from ThisBB to BB may have been split and 1070 // BB's predecessor is now another block. 1071 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1072 SDB->EdgeMapping.find(BB); 1073 if (EI != SDB->EdgeMapping.end()) 1074 ThisBB = EI->second; 1075 1076 // BB may have been removed from the CFG if a branch was constant folded. 1077 if (ThisBB->isSuccessor(BB)) { 1078 for (MachineBasicBlock::iterator Phi = BB->begin(); 1079 Phi != BB->end() && Phi->isPHI(); 1080 ++Phi) { 1081 // This value for this PHI node is recorded in PHINodesToUpdate. 1082 for (unsigned pn = 0; ; ++pn) { 1083 assert(pn != SDB->PHINodesToUpdate.size() && 1084 "Didn't find PHI entry!"); 1085 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1086 Phi->addOperand(MachineOperand:: 1087 CreateReg(SDB->PHINodesToUpdate[pn].second, 1088 false)); 1089 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1090 break; 1091 } 1092 } 1093 } 1094 } 1095 1096 // Don't process RHS if same block as LHS. 1097 if (BB == SDB->SwitchCases[i].FalseBB) 1098 SDB->SwitchCases[i].FalseBB = 0; 1099 1100 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1101 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1102 SDB->SwitchCases[i].FalseBB = 0; 1103 } 1104 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1105 SDB->clear(); 1106 } 1107 SDB->SwitchCases.clear(); 1108 1109 SDB->PHINodesToUpdate.clear(); 1110} 1111 1112 1113/// Create the scheduler. If a specific scheduler was specified 1114/// via the SchedulerRegistry, use it, otherwise select the 1115/// one preferred by the target. 1116/// 1117ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1118 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1119 1120 if (!Ctor) { 1121 Ctor = ISHeuristic; 1122 RegisterScheduler::setDefault(Ctor); 1123 } 1124 1125 return Ctor(this, OptLevel); 1126} 1127 1128ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1129 return new ScheduleHazardRecognizer(); 1130} 1131 1132//===----------------------------------------------------------------------===// 1133// Helper functions used by the generated instruction selector. 1134//===----------------------------------------------------------------------===// 1135// Calls to these methods are generated by tblgen. 1136 1137/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1138/// the dag combiner simplified the 255, we still want to match. RHS is the 1139/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1140/// specified in the .td file (e.g. 255). 1141bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1142 int64_t DesiredMaskS) const { 1143 const APInt &ActualMask = RHS->getAPIntValue(); 1144 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1145 1146 // If the actual mask exactly matches, success! 1147 if (ActualMask == DesiredMask) 1148 return true; 1149 1150 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1151 if (ActualMask.intersects(~DesiredMask)) 1152 return false; 1153 1154 // Otherwise, the DAG Combiner may have proven that the value coming in is 1155 // either already zero or is not demanded. Check for known zero input bits. 1156 APInt NeededMask = DesiredMask & ~ActualMask; 1157 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1158 return true; 1159 1160 // TODO: check to see if missing bits are just not demanded. 1161 1162 // Otherwise, this pattern doesn't match. 1163 return false; 1164} 1165 1166/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1167/// the dag combiner simplified the 255, we still want to match. RHS is the 1168/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1169/// specified in the .td file (e.g. 255). 1170bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1171 int64_t DesiredMaskS) const { 1172 const APInt &ActualMask = RHS->getAPIntValue(); 1173 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1174 1175 // If the actual mask exactly matches, success! 1176 if (ActualMask == DesiredMask) 1177 return true; 1178 1179 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1180 if (ActualMask.intersects(~DesiredMask)) 1181 return false; 1182 1183 // Otherwise, the DAG Combiner may have proven that the value coming in is 1184 // either already zero or is not demanded. Check for known zero input bits. 1185 APInt NeededMask = DesiredMask & ~ActualMask; 1186 1187 APInt KnownZero, KnownOne; 1188 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1189 1190 // If all the missing bits in the or are already known to be set, match! 1191 if ((NeededMask & KnownOne) == NeededMask) 1192 return true; 1193 1194 // TODO: check to see if missing bits are just not demanded. 1195 1196 // Otherwise, this pattern doesn't match. 1197 return false; 1198} 1199 1200 1201/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1202/// by tblgen. Others should not call it. 1203void SelectionDAGISel:: 1204SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1205 std::vector<SDValue> InOps; 1206 std::swap(InOps, Ops); 1207 1208 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1209 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1210 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1211 1212 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1213 if (InOps[e-1].getValueType() == MVT::Flag) 1214 --e; // Don't process a flag operand if it is here. 1215 1216 while (i != e) { 1217 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1218 if (!InlineAsm::isMemKind(Flags)) { 1219 // Just skip over this operand, copying the operands verbatim. 1220 Ops.insert(Ops.end(), InOps.begin()+i, 1221 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1222 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1223 } else { 1224 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1225 "Memory operand with multiple values?"); 1226 // Otherwise, this is a memory operand. Ask the target to select it. 1227 std::vector<SDValue> SelOps; 1228 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1229 report_fatal_error("Could not match memory address. Inline asm" 1230 " failure!"); 1231 1232 // Add this to the output node. 1233 unsigned NewFlags = 1234 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1235 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1236 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1237 i += 2; 1238 } 1239 } 1240 1241 // Add the flag input back if present. 1242 if (e != InOps.size()) 1243 Ops.push_back(InOps.back()); 1244} 1245 1246/// findFlagUse - Return use of EVT::Flag value produced by the specified 1247/// SDNode. 1248/// 1249static SDNode *findFlagUse(SDNode *N) { 1250 unsigned FlagResNo = N->getNumValues()-1; 1251 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1252 SDUse &Use = I.getUse(); 1253 if (Use.getResNo() == FlagResNo) 1254 return Use.getUser(); 1255 } 1256 return NULL; 1257} 1258 1259/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1260/// This function recursively traverses up the operand chain, ignoring 1261/// certain nodes. 1262static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1263 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1264 bool IgnoreChains) { 1265 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1266 // greater than all of its (recursive) operands. If we scan to a point where 1267 // 'use' is smaller than the node we're scanning for, then we know we will 1268 // never find it. 1269 // 1270 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1271 // happen because we scan down to newly selected nodes in the case of flag 1272 // uses. 1273 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1274 return false; 1275 1276 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1277 // won't fail if we scan it again. 1278 if (!Visited.insert(Use)) 1279 return false; 1280 1281 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1282 // Ignore chain uses, they are validated by HandleMergeInputChains. 1283 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1284 continue; 1285 1286 SDNode *N = Use->getOperand(i).getNode(); 1287 if (N == Def) { 1288 if (Use == ImmedUse || Use == Root) 1289 continue; // We are not looking for immediate use. 1290 assert(N != Root); 1291 return true; 1292 } 1293 1294 // Traverse up the operand chain. 1295 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1296 return true; 1297 } 1298 return false; 1299} 1300 1301/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1302/// operand node N of U during instruction selection that starts at Root. 1303bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1304 SDNode *Root) const { 1305 if (OptLevel == CodeGenOpt::None) return false; 1306 return N.hasOneUse(); 1307} 1308 1309/// IsLegalToFold - Returns true if the specific operand node N of 1310/// U can be folded during instruction selection that starts at Root. 1311bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1312 bool IgnoreChains) const { 1313 if (OptLevel == CodeGenOpt::None) return false; 1314 1315 // If Root use can somehow reach N through a path that that doesn't contain 1316 // U then folding N would create a cycle. e.g. In the following 1317 // diagram, Root can reach N through X. If N is folded into into Root, then 1318 // X is both a predecessor and a successor of U. 1319 // 1320 // [N*] // 1321 // ^ ^ // 1322 // / \ // 1323 // [U*] [X]? // 1324 // ^ ^ // 1325 // \ / // 1326 // \ / // 1327 // [Root*] // 1328 // 1329 // * indicates nodes to be folded together. 1330 // 1331 // If Root produces a flag, then it gets (even more) interesting. Since it 1332 // will be "glued" together with its flag use in the scheduler, we need to 1333 // check if it might reach N. 1334 // 1335 // [N*] // 1336 // ^ ^ // 1337 // / \ // 1338 // [U*] [X]? // 1339 // ^ ^ // 1340 // \ \ // 1341 // \ | // 1342 // [Root*] | // 1343 // ^ | // 1344 // f | // 1345 // | / // 1346 // [Y] / // 1347 // ^ / // 1348 // f / // 1349 // | / // 1350 // [FU] // 1351 // 1352 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1353 // (call it Fold), then X is a predecessor of FU and a successor of 1354 // Fold. But since Fold and FU are flagged together, this will create 1355 // a cycle in the scheduling graph. 1356 1357 // If the node has flags, walk down the graph to the "lowest" node in the 1358 // flagged set. 1359 EVT VT = Root->getValueType(Root->getNumValues()-1); 1360 while (VT == MVT::Flag) { 1361 SDNode *FU = findFlagUse(Root); 1362 if (FU == NULL) 1363 break; 1364 Root = FU; 1365 VT = Root->getValueType(Root->getNumValues()-1); 1366 1367 // If our query node has a flag result with a use, we've walked up it. If 1368 // the user (which has already been selected) has a chain or indirectly uses 1369 // the chain, our WalkChainUsers predicate will not consider it. Because of 1370 // this, we cannot ignore chains in this predicate. 1371 IgnoreChains = false; 1372 } 1373 1374 1375 SmallPtrSet<SDNode*, 16> Visited; 1376 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1377} 1378 1379SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1380 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1381 SelectInlineAsmMemoryOperands(Ops); 1382 1383 std::vector<EVT> VTs; 1384 VTs.push_back(MVT::Other); 1385 VTs.push_back(MVT::Flag); 1386 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1387 VTs, &Ops[0], Ops.size()); 1388 New->setNodeId(-1); 1389 return New.getNode(); 1390} 1391 1392SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1393 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1394} 1395 1396/// GetVBR - decode a vbr encoding whose top bit is set. 1397ALWAYS_INLINE static uint64_t 1398GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1399 assert(Val >= 128 && "Not a VBR"); 1400 Val &= 127; // Remove first vbr bit. 1401 1402 unsigned Shift = 7; 1403 uint64_t NextBits; 1404 do { 1405 NextBits = MatcherTable[Idx++]; 1406 Val |= (NextBits&127) << Shift; 1407 Shift += 7; 1408 } while (NextBits & 128); 1409 1410 return Val; 1411} 1412 1413 1414/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1415/// interior flag and chain results to use the new flag and chain results. 1416void SelectionDAGISel:: 1417UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1418 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1419 SDValue InputFlag, 1420 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1421 bool isMorphNodeTo) { 1422 SmallVector<SDNode*, 4> NowDeadNodes; 1423 1424 ISelUpdater ISU(ISelPosition); 1425 1426 // Now that all the normal results are replaced, we replace the chain and 1427 // flag results if present. 1428 if (!ChainNodesMatched.empty()) { 1429 assert(InputChain.getNode() != 0 && 1430 "Matched input chains but didn't produce a chain"); 1431 // Loop over all of the nodes we matched that produced a chain result. 1432 // Replace all the chain results with the final chain we ended up with. 1433 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1434 SDNode *ChainNode = ChainNodesMatched[i]; 1435 1436 // If this node was already deleted, don't look at it. 1437 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1438 continue; 1439 1440 // Don't replace the results of the root node if we're doing a 1441 // MorphNodeTo. 1442 if (ChainNode == NodeToMatch && isMorphNodeTo) 1443 continue; 1444 1445 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1446 if (ChainVal.getValueType() == MVT::Flag) 1447 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1448 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1449 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1450 1451 // If the node became dead and we haven't already seen it, delete it. 1452 if (ChainNode->use_empty() && 1453 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1454 NowDeadNodes.push_back(ChainNode); 1455 } 1456 } 1457 1458 // If the result produces a flag, update any flag results in the matched 1459 // pattern with the flag result. 1460 if (InputFlag.getNode() != 0) { 1461 // Handle any interior nodes explicitly marked. 1462 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1463 SDNode *FRN = FlagResultNodesMatched[i]; 1464 1465 // If this node was already deleted, don't look at it. 1466 if (FRN->getOpcode() == ISD::DELETED_NODE) 1467 continue; 1468 1469 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1470 "Doesn't have a flag result"); 1471 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1472 InputFlag, &ISU); 1473 1474 // If the node became dead and we haven't already seen it, delete it. 1475 if (FRN->use_empty() && 1476 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1477 NowDeadNodes.push_back(FRN); 1478 } 1479 } 1480 1481 if (!NowDeadNodes.empty()) 1482 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1483 1484 DEBUG(errs() << "ISEL: Match complete!\n"); 1485} 1486 1487enum ChainResult { 1488 CR_Simple, 1489 CR_InducesCycle, 1490 CR_LeadsToInteriorNode 1491}; 1492 1493/// WalkChainUsers - Walk down the users of the specified chained node that is 1494/// part of the pattern we're matching, looking at all of the users we find. 1495/// This determines whether something is an interior node, whether we have a 1496/// non-pattern node in between two pattern nodes (which prevent folding because 1497/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1498/// between pattern nodes (in which case the TF becomes part of the pattern). 1499/// 1500/// The walk we do here is guaranteed to be small because we quickly get down to 1501/// already selected nodes "below" us. 1502static ChainResult 1503WalkChainUsers(SDNode *ChainedNode, 1504 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1505 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1506 ChainResult Result = CR_Simple; 1507 1508 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1509 E = ChainedNode->use_end(); UI != E; ++UI) { 1510 // Make sure the use is of the chain, not some other value we produce. 1511 if (UI.getUse().getValueType() != MVT::Other) continue; 1512 1513 SDNode *User = *UI; 1514 1515 // If we see an already-selected machine node, then we've gone beyond the 1516 // pattern that we're selecting down into the already selected chunk of the 1517 // DAG. 1518 if (User->isMachineOpcode() || 1519 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1520 continue; 1521 1522 if (User->getOpcode() == ISD::CopyToReg || 1523 User->getOpcode() == ISD::CopyFromReg || 1524 User->getOpcode() == ISD::INLINEASM || 1525 User->getOpcode() == ISD::EH_LABEL) { 1526 // If their node ID got reset to -1 then they've already been selected. 1527 // Treat them like a MachineOpcode. 1528 if (User->getNodeId() == -1) 1529 continue; 1530 } 1531 1532 // If we have a TokenFactor, we handle it specially. 1533 if (User->getOpcode() != ISD::TokenFactor) { 1534 // If the node isn't a token factor and isn't part of our pattern, then it 1535 // must be a random chained node in between two nodes we're selecting. 1536 // This happens when we have something like: 1537 // x = load ptr 1538 // call 1539 // y = x+4 1540 // store y -> ptr 1541 // Because we structurally match the load/store as a read/modify/write, 1542 // but the call is chained between them. We cannot fold in this case 1543 // because it would induce a cycle in the graph. 1544 if (!std::count(ChainedNodesInPattern.begin(), 1545 ChainedNodesInPattern.end(), User)) 1546 return CR_InducesCycle; 1547 1548 // Otherwise we found a node that is part of our pattern. For example in: 1549 // x = load ptr 1550 // y = x+4 1551 // store y -> ptr 1552 // This would happen when we're scanning down from the load and see the 1553 // store as a user. Record that there is a use of ChainedNode that is 1554 // part of the pattern and keep scanning uses. 1555 Result = CR_LeadsToInteriorNode; 1556 InteriorChainedNodes.push_back(User); 1557 continue; 1558 } 1559 1560 // If we found a TokenFactor, there are two cases to consider: first if the 1561 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1562 // uses of the TF are in our pattern) we just want to ignore it. Second, 1563 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1564 // [Load chain] 1565 // ^ 1566 // | 1567 // [Load] 1568 // ^ ^ 1569 // | \ DAG's like cheese 1570 // / \ do you? 1571 // / | 1572 // [TokenFactor] [Op] 1573 // ^ ^ 1574 // | | 1575 // \ / 1576 // \ / 1577 // [Store] 1578 // 1579 // In this case, the TokenFactor becomes part of our match and we rewrite it 1580 // as a new TokenFactor. 1581 // 1582 // To distinguish these two cases, do a recursive walk down the uses. 1583 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1584 case CR_Simple: 1585 // If the uses of the TokenFactor are just already-selected nodes, ignore 1586 // it, it is "below" our pattern. 1587 continue; 1588 case CR_InducesCycle: 1589 // If the uses of the TokenFactor lead to nodes that are not part of our 1590 // pattern that are not selected, folding would turn this into a cycle, 1591 // bail out now. 1592 return CR_InducesCycle; 1593 case CR_LeadsToInteriorNode: 1594 break; // Otherwise, keep processing. 1595 } 1596 1597 // Okay, we know we're in the interesting interior case. The TokenFactor 1598 // is now going to be considered part of the pattern so that we rewrite its 1599 // uses (it may have uses that are not part of the pattern) with the 1600 // ultimate chain result of the generated code. We will also add its chain 1601 // inputs as inputs to the ultimate TokenFactor we create. 1602 Result = CR_LeadsToInteriorNode; 1603 ChainedNodesInPattern.push_back(User); 1604 InteriorChainedNodes.push_back(User); 1605 continue; 1606 } 1607 1608 return Result; 1609} 1610 1611/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1612/// operation for when the pattern matched at least one node with a chains. The 1613/// input vector contains a list of all of the chained nodes that we match. We 1614/// must determine if this is a valid thing to cover (i.e. matching it won't 1615/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1616/// be used as the input node chain for the generated nodes. 1617static SDValue 1618HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1619 SelectionDAG *CurDAG) { 1620 // Walk all of the chained nodes we've matched, recursively scanning down the 1621 // users of the chain result. This adds any TokenFactor nodes that are caught 1622 // in between chained nodes to the chained and interior nodes list. 1623 SmallVector<SDNode*, 3> InteriorChainedNodes; 1624 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1625 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1626 InteriorChainedNodes) == CR_InducesCycle) 1627 return SDValue(); // Would induce a cycle. 1628 } 1629 1630 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1631 // that we are interested in. Form our input TokenFactor node. 1632 SmallVector<SDValue, 3> InputChains; 1633 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1634 // Add the input chain of this node to the InputChains list (which will be 1635 // the operands of the generated TokenFactor) if it's not an interior node. 1636 SDNode *N = ChainNodesMatched[i]; 1637 if (N->getOpcode() != ISD::TokenFactor) { 1638 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1639 continue; 1640 1641 // Otherwise, add the input chain. 1642 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1643 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1644 InputChains.push_back(InChain); 1645 continue; 1646 } 1647 1648 // If we have a token factor, we want to add all inputs of the token factor 1649 // that are not part of the pattern we're matching. 1650 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1651 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1652 N->getOperand(op).getNode())) 1653 InputChains.push_back(N->getOperand(op)); 1654 } 1655 } 1656 1657 SDValue Res; 1658 if (InputChains.size() == 1) 1659 return InputChains[0]; 1660 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1661 MVT::Other, &InputChains[0], InputChains.size()); 1662} 1663 1664/// MorphNode - Handle morphing a node in place for the selector. 1665SDNode *SelectionDAGISel:: 1666MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1667 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1668 // It is possible we're using MorphNodeTo to replace a node with no 1669 // normal results with one that has a normal result (or we could be 1670 // adding a chain) and the input could have flags and chains as well. 1671 // In this case we need to shift the operands down. 1672 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1673 // than the old isel though. 1674 int OldFlagResultNo = -1, OldChainResultNo = -1; 1675 1676 unsigned NTMNumResults = Node->getNumValues(); 1677 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1678 OldFlagResultNo = NTMNumResults-1; 1679 if (NTMNumResults != 1 && 1680 Node->getValueType(NTMNumResults-2) == MVT::Other) 1681 OldChainResultNo = NTMNumResults-2; 1682 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1683 OldChainResultNo = NTMNumResults-1; 1684 1685 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1686 // that this deletes operands of the old node that become dead. 1687 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1688 1689 // MorphNodeTo can operate in two ways: if an existing node with the 1690 // specified operands exists, it can just return it. Otherwise, it 1691 // updates the node in place to have the requested operands. 1692 if (Res == Node) { 1693 // If we updated the node in place, reset the node ID. To the isel, 1694 // this should be just like a newly allocated machine node. 1695 Res->setNodeId(-1); 1696 } 1697 1698 unsigned ResNumResults = Res->getNumValues(); 1699 // Move the flag if needed. 1700 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1701 (unsigned)OldFlagResultNo != ResNumResults-1) 1702 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1703 SDValue(Res, ResNumResults-1)); 1704 1705 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1706 --ResNumResults; 1707 1708 // Move the chain reference if needed. 1709 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1710 (unsigned)OldChainResultNo != ResNumResults-1) 1711 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1712 SDValue(Res, ResNumResults-1)); 1713 1714 // Otherwise, no replacement happened because the node already exists. Replace 1715 // Uses of the old node with the new one. 1716 if (Res != Node) 1717 CurDAG->ReplaceAllUsesWith(Node, Res); 1718 1719 return Res; 1720} 1721 1722/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1723ALWAYS_INLINE static bool 1724CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1725 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1726 // Accept if it is exactly the same as a previously recorded node. 1727 unsigned RecNo = MatcherTable[MatcherIndex++]; 1728 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1729 return N == RecordedNodes[RecNo]; 1730} 1731 1732/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1733ALWAYS_INLINE static bool 1734CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1735 SelectionDAGISel &SDISel) { 1736 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1737} 1738 1739/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1740ALWAYS_INLINE static bool 1741CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1742 SelectionDAGISel &SDISel, SDNode *N) { 1743 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1744} 1745 1746ALWAYS_INLINE static bool 1747CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1748 SDNode *N) { 1749 uint16_t Opc = MatcherTable[MatcherIndex++]; 1750 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1751 return N->getOpcode() == Opc; 1752} 1753 1754ALWAYS_INLINE static bool 1755CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1756 SDValue N, const TargetLowering &TLI) { 1757 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1758 if (N.getValueType() == VT) return true; 1759 1760 // Handle the case when VT is iPTR. 1761 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1762} 1763 1764ALWAYS_INLINE static bool 1765CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1766 SDValue N, const TargetLowering &TLI, 1767 unsigned ChildNo) { 1768 if (ChildNo >= N.getNumOperands()) 1769 return false; // Match fails if out of range child #. 1770 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1771} 1772 1773 1774ALWAYS_INLINE static bool 1775CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1776 SDValue N) { 1777 return cast<CondCodeSDNode>(N)->get() == 1778 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1779} 1780 1781ALWAYS_INLINE static bool 1782CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1783 SDValue N, const TargetLowering &TLI) { 1784 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1785 if (cast<VTSDNode>(N)->getVT() == VT) 1786 return true; 1787 1788 // Handle the case when VT is iPTR. 1789 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1790} 1791 1792ALWAYS_INLINE static bool 1793CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1794 SDValue N) { 1795 int64_t Val = MatcherTable[MatcherIndex++]; 1796 if (Val & 128) 1797 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1798 1799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1800 return C != 0 && C->getSExtValue() == Val; 1801} 1802 1803ALWAYS_INLINE static bool 1804CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1805 SDValue N, SelectionDAGISel &SDISel) { 1806 int64_t Val = MatcherTable[MatcherIndex++]; 1807 if (Val & 128) 1808 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1809 1810 if (N->getOpcode() != ISD::AND) return false; 1811 1812 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1813 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1814} 1815 1816ALWAYS_INLINE static bool 1817CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1818 SDValue N, SelectionDAGISel &SDISel) { 1819 int64_t Val = MatcherTable[MatcherIndex++]; 1820 if (Val & 128) 1821 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1822 1823 if (N->getOpcode() != ISD::OR) return false; 1824 1825 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1826 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1827} 1828 1829/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1830/// scope, evaluate the current node. If the current predicate is known to 1831/// fail, set Result=true and return anything. If the current predicate is 1832/// known to pass, set Result=false and return the MatcherIndex to continue 1833/// with. If the current predicate is unknown, set Result=false and return the 1834/// MatcherIndex to continue with. 1835static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1836 unsigned Index, SDValue N, 1837 bool &Result, SelectionDAGISel &SDISel, 1838 SmallVectorImpl<SDValue> &RecordedNodes){ 1839 switch (Table[Index++]) { 1840 default: 1841 Result = false; 1842 return Index-1; // Could not evaluate this predicate. 1843 case SelectionDAGISel::OPC_CheckSame: 1844 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1845 return Index; 1846 case SelectionDAGISel::OPC_CheckPatternPredicate: 1847 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1848 return Index; 1849 case SelectionDAGISel::OPC_CheckPredicate: 1850 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1851 return Index; 1852 case SelectionDAGISel::OPC_CheckOpcode: 1853 Result = !::CheckOpcode(Table, Index, N.getNode()); 1854 return Index; 1855 case SelectionDAGISel::OPC_CheckType: 1856 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1857 return Index; 1858 case SelectionDAGISel::OPC_CheckChild0Type: 1859 case SelectionDAGISel::OPC_CheckChild1Type: 1860 case SelectionDAGISel::OPC_CheckChild2Type: 1861 case SelectionDAGISel::OPC_CheckChild3Type: 1862 case SelectionDAGISel::OPC_CheckChild4Type: 1863 case SelectionDAGISel::OPC_CheckChild5Type: 1864 case SelectionDAGISel::OPC_CheckChild6Type: 1865 case SelectionDAGISel::OPC_CheckChild7Type: 1866 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1867 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1868 return Index; 1869 case SelectionDAGISel::OPC_CheckCondCode: 1870 Result = !::CheckCondCode(Table, Index, N); 1871 return Index; 1872 case SelectionDAGISel::OPC_CheckValueType: 1873 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1874 return Index; 1875 case SelectionDAGISel::OPC_CheckInteger: 1876 Result = !::CheckInteger(Table, Index, N); 1877 return Index; 1878 case SelectionDAGISel::OPC_CheckAndImm: 1879 Result = !::CheckAndImm(Table, Index, N, SDISel); 1880 return Index; 1881 case SelectionDAGISel::OPC_CheckOrImm: 1882 Result = !::CheckOrImm(Table, Index, N, SDISel); 1883 return Index; 1884 } 1885} 1886 1887 1888struct MatchScope { 1889 /// FailIndex - If this match fails, this is the index to continue with. 1890 unsigned FailIndex; 1891 1892 /// NodeStack - The node stack when the scope was formed. 1893 SmallVector<SDValue, 4> NodeStack; 1894 1895 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1896 unsigned NumRecordedNodes; 1897 1898 /// NumMatchedMemRefs - The number of matched memref entries. 1899 unsigned NumMatchedMemRefs; 1900 1901 /// InputChain/InputFlag - The current chain/flag 1902 SDValue InputChain, InputFlag; 1903 1904 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1905 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1906}; 1907 1908SDNode *SelectionDAGISel:: 1909SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1910 unsigned TableSize) { 1911 // FIXME: Should these even be selected? Handle these cases in the caller? 1912 switch (NodeToMatch->getOpcode()) { 1913 default: 1914 break; 1915 case ISD::EntryToken: // These nodes remain the same. 1916 case ISD::BasicBlock: 1917 case ISD::Register: 1918 //case ISD::VALUETYPE: 1919 //case ISD::CONDCODE: 1920 case ISD::HANDLENODE: 1921 case ISD::MDNODE_SDNODE: 1922 case ISD::TargetConstant: 1923 case ISD::TargetConstantFP: 1924 case ISD::TargetConstantPool: 1925 case ISD::TargetFrameIndex: 1926 case ISD::TargetExternalSymbol: 1927 case ISD::TargetBlockAddress: 1928 case ISD::TargetJumpTable: 1929 case ISD::TargetGlobalTLSAddress: 1930 case ISD::TargetGlobalAddress: 1931 case ISD::TokenFactor: 1932 case ISD::CopyFromReg: 1933 case ISD::CopyToReg: 1934 case ISD::EH_LABEL: 1935 NodeToMatch->setNodeId(-1); // Mark selected. 1936 return 0; 1937 case ISD::AssertSext: 1938 case ISD::AssertZext: 1939 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1940 NodeToMatch->getOperand(0)); 1941 return 0; 1942 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1943 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1944 } 1945 1946 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1947 1948 // Set up the node stack with NodeToMatch as the only node on the stack. 1949 SmallVector<SDValue, 8> NodeStack; 1950 SDValue N = SDValue(NodeToMatch, 0); 1951 NodeStack.push_back(N); 1952 1953 // MatchScopes - Scopes used when matching, if a match failure happens, this 1954 // indicates where to continue checking. 1955 SmallVector<MatchScope, 8> MatchScopes; 1956 1957 // RecordedNodes - This is the set of nodes that have been recorded by the 1958 // state machine. 1959 SmallVector<SDValue, 8> RecordedNodes; 1960 1961 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1962 // pattern. 1963 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1964 1965 // These are the current input chain and flag for use when generating nodes. 1966 // Various Emit operations change these. For example, emitting a copytoreg 1967 // uses and updates these. 1968 SDValue InputChain, InputFlag; 1969 1970 // ChainNodesMatched - If a pattern matches nodes that have input/output 1971 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1972 // which ones they are. The result is captured into this list so that we can 1973 // update the chain results when the pattern is complete. 1974 SmallVector<SDNode*, 3> ChainNodesMatched; 1975 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1976 1977 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1978 NodeToMatch->dump(CurDAG); 1979 errs() << '\n'); 1980 1981 // Determine where to start the interpreter. Normally we start at opcode #0, 1982 // but if the state machine starts with an OPC_SwitchOpcode, then we 1983 // accelerate the first lookup (which is guaranteed to be hot) with the 1984 // OpcodeOffset table. 1985 unsigned MatcherIndex = 0; 1986 1987 if (!OpcodeOffset.empty()) { 1988 // Already computed the OpcodeOffset table, just index into it. 1989 if (N.getOpcode() < OpcodeOffset.size()) 1990 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1991 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1992 1993 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1994 // Otherwise, the table isn't computed, but the state machine does start 1995 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1996 // is the first time we're selecting an instruction. 1997 unsigned Idx = 1; 1998 while (1) { 1999 // Get the size of this case. 2000 unsigned CaseSize = MatcherTable[Idx++]; 2001 if (CaseSize & 128) 2002 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2003 if (CaseSize == 0) break; 2004 2005 // Get the opcode, add the index to the table. 2006 uint16_t Opc = MatcherTable[Idx++]; 2007 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2008 if (Opc >= OpcodeOffset.size()) 2009 OpcodeOffset.resize((Opc+1)*2); 2010 OpcodeOffset[Opc] = Idx; 2011 Idx += CaseSize; 2012 } 2013 2014 // Okay, do the lookup for the first opcode. 2015 if (N.getOpcode() < OpcodeOffset.size()) 2016 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2017 } 2018 2019 while (1) { 2020 assert(MatcherIndex < TableSize && "Invalid index"); 2021#ifndef NDEBUG 2022 unsigned CurrentOpcodeIndex = MatcherIndex; 2023#endif 2024 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2025 switch (Opcode) { 2026 case OPC_Scope: { 2027 // Okay, the semantics of this operation are that we should push a scope 2028 // then evaluate the first child. However, pushing a scope only to have 2029 // the first check fail (which then pops it) is inefficient. If we can 2030 // determine immediately that the first check (or first several) will 2031 // immediately fail, don't even bother pushing a scope for them. 2032 unsigned FailIndex; 2033 2034 while (1) { 2035 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2036 if (NumToSkip & 128) 2037 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2038 // Found the end of the scope with no match. 2039 if (NumToSkip == 0) { 2040 FailIndex = 0; 2041 break; 2042 } 2043 2044 FailIndex = MatcherIndex+NumToSkip; 2045 2046 unsigned MatcherIndexOfPredicate = MatcherIndex; 2047 (void)MatcherIndexOfPredicate; // silence warning. 2048 2049 // If we can't evaluate this predicate without pushing a scope (e.g. if 2050 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2051 // push the scope and evaluate the full predicate chain. 2052 bool Result; 2053 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2054 Result, *this, RecordedNodes); 2055 if (!Result) 2056 break; 2057 2058 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2059 << "index " << MatcherIndexOfPredicate 2060 << ", continuing at " << FailIndex << "\n"); 2061 ++NumDAGIselRetries; 2062 2063 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2064 // move to the next case. 2065 MatcherIndex = FailIndex; 2066 } 2067 2068 // If the whole scope failed to match, bail. 2069 if (FailIndex == 0) break; 2070 2071 // Push a MatchScope which indicates where to go if the first child fails 2072 // to match. 2073 MatchScope NewEntry; 2074 NewEntry.FailIndex = FailIndex; 2075 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2076 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2077 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2078 NewEntry.InputChain = InputChain; 2079 NewEntry.InputFlag = InputFlag; 2080 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2081 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2082 MatchScopes.push_back(NewEntry); 2083 continue; 2084 } 2085 case OPC_RecordNode: 2086 // Remember this node, it may end up being an operand in the pattern. 2087 RecordedNodes.push_back(N); 2088 continue; 2089 2090 case OPC_RecordChild0: case OPC_RecordChild1: 2091 case OPC_RecordChild2: case OPC_RecordChild3: 2092 case OPC_RecordChild4: case OPC_RecordChild5: 2093 case OPC_RecordChild6: case OPC_RecordChild7: { 2094 unsigned ChildNo = Opcode-OPC_RecordChild0; 2095 if (ChildNo >= N.getNumOperands()) 2096 break; // Match fails if out of range child #. 2097 2098 RecordedNodes.push_back(N->getOperand(ChildNo)); 2099 continue; 2100 } 2101 case OPC_RecordMemRef: 2102 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2103 continue; 2104 2105 case OPC_CaptureFlagInput: 2106 // If the current node has an input flag, capture it in InputFlag. 2107 if (N->getNumOperands() != 0 && 2108 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2109 InputFlag = N->getOperand(N->getNumOperands()-1); 2110 continue; 2111 2112 case OPC_MoveChild: { 2113 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2114 if (ChildNo >= N.getNumOperands()) 2115 break; // Match fails if out of range child #. 2116 N = N.getOperand(ChildNo); 2117 NodeStack.push_back(N); 2118 continue; 2119 } 2120 2121 case OPC_MoveParent: 2122 // Pop the current node off the NodeStack. 2123 NodeStack.pop_back(); 2124 assert(!NodeStack.empty() && "Node stack imbalance!"); 2125 N = NodeStack.back(); 2126 continue; 2127 2128 case OPC_CheckSame: 2129 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2130 continue; 2131 case OPC_CheckPatternPredicate: 2132 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2133 continue; 2134 case OPC_CheckPredicate: 2135 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2136 N.getNode())) 2137 break; 2138 continue; 2139 case OPC_CheckComplexPat: { 2140 unsigned CPNum = MatcherTable[MatcherIndex++]; 2141 unsigned RecNo = MatcherTable[MatcherIndex++]; 2142 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2143 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2144 RecordedNodes)) 2145 break; 2146 continue; 2147 } 2148 case OPC_CheckOpcode: 2149 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2150 continue; 2151 2152 case OPC_CheckType: 2153 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2154 continue; 2155 2156 case OPC_SwitchOpcode: { 2157 unsigned CurNodeOpcode = N.getOpcode(); 2158 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2159 unsigned CaseSize; 2160 while (1) { 2161 // Get the size of this case. 2162 CaseSize = MatcherTable[MatcherIndex++]; 2163 if (CaseSize & 128) 2164 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2165 if (CaseSize == 0) break; 2166 2167 uint16_t Opc = MatcherTable[MatcherIndex++]; 2168 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2169 2170 // If the opcode matches, then we will execute this case. 2171 if (CurNodeOpcode == Opc) 2172 break; 2173 2174 // Otherwise, skip over this case. 2175 MatcherIndex += CaseSize; 2176 } 2177 2178 // If no cases matched, bail out. 2179 if (CaseSize == 0) break; 2180 2181 // Otherwise, execute the case we found. 2182 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2183 << " to " << MatcherIndex << "\n"); 2184 continue; 2185 } 2186 2187 case OPC_SwitchType: { 2188 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2189 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2190 unsigned CaseSize; 2191 while (1) { 2192 // Get the size of this case. 2193 CaseSize = MatcherTable[MatcherIndex++]; 2194 if (CaseSize & 128) 2195 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2196 if (CaseSize == 0) break; 2197 2198 MVT::SimpleValueType CaseVT = 2199 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2200 if (CaseVT == MVT::iPTR) 2201 CaseVT = TLI.getPointerTy().SimpleTy; 2202 2203 // If the VT matches, then we will execute this case. 2204 if (CurNodeVT == CaseVT) 2205 break; 2206 2207 // Otherwise, skip over this case. 2208 MatcherIndex += CaseSize; 2209 } 2210 2211 // If no cases matched, bail out. 2212 if (CaseSize == 0) break; 2213 2214 // Otherwise, execute the case we found. 2215 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2216 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2217 continue; 2218 } 2219 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2220 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2221 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2222 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2223 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2224 Opcode-OPC_CheckChild0Type)) 2225 break; 2226 continue; 2227 case OPC_CheckCondCode: 2228 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2229 continue; 2230 case OPC_CheckValueType: 2231 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2232 continue; 2233 case OPC_CheckInteger: 2234 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2235 continue; 2236 case OPC_CheckAndImm: 2237 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2238 continue; 2239 case OPC_CheckOrImm: 2240 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2241 continue; 2242 2243 case OPC_CheckFoldableChainNode: { 2244 assert(NodeStack.size() != 1 && "No parent node"); 2245 // Verify that all intermediate nodes between the root and this one have 2246 // a single use. 2247 bool HasMultipleUses = false; 2248 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2249 if (!NodeStack[i].hasOneUse()) { 2250 HasMultipleUses = true; 2251 break; 2252 } 2253 if (HasMultipleUses) break; 2254 2255 // Check to see that the target thinks this is profitable to fold and that 2256 // we can fold it without inducing cycles in the graph. 2257 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2258 NodeToMatch) || 2259 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2260 NodeToMatch, true/*We validate our own chains*/)) 2261 break; 2262 2263 continue; 2264 } 2265 case OPC_EmitInteger: { 2266 MVT::SimpleValueType VT = 2267 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2268 int64_t Val = MatcherTable[MatcherIndex++]; 2269 if (Val & 128) 2270 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2271 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2272 continue; 2273 } 2274 case OPC_EmitRegister: { 2275 MVT::SimpleValueType VT = 2276 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2277 unsigned RegNo = MatcherTable[MatcherIndex++]; 2278 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2279 continue; 2280 } 2281 2282 case OPC_EmitConvertToTarget: { 2283 // Convert from IMM/FPIMM to target version. 2284 unsigned RecNo = MatcherTable[MatcherIndex++]; 2285 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2286 SDValue Imm = RecordedNodes[RecNo]; 2287 2288 if (Imm->getOpcode() == ISD::Constant) { 2289 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2290 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2291 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2292 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2293 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2294 } 2295 2296 RecordedNodes.push_back(Imm); 2297 continue; 2298 } 2299 2300 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2301 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2302 // These are space-optimized forms of OPC_EmitMergeInputChains. 2303 assert(InputChain.getNode() == 0 && 2304 "EmitMergeInputChains should be the first chain producing node"); 2305 assert(ChainNodesMatched.empty() && 2306 "Should only have one EmitMergeInputChains per match"); 2307 2308 // Read all of the chained nodes. 2309 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2310 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2311 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2312 2313 // FIXME: What if other value results of the node have uses not matched 2314 // by this pattern? 2315 if (ChainNodesMatched.back() != NodeToMatch && 2316 !RecordedNodes[RecNo].hasOneUse()) { 2317 ChainNodesMatched.clear(); 2318 break; 2319 } 2320 2321 // Merge the input chains if they are not intra-pattern references. 2322 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2323 2324 if (InputChain.getNode() == 0) 2325 break; // Failed to merge. 2326 continue; 2327 } 2328 2329 case OPC_EmitMergeInputChains: { 2330 assert(InputChain.getNode() == 0 && 2331 "EmitMergeInputChains should be the first chain producing node"); 2332 // This node gets a list of nodes we matched in the input that have 2333 // chains. We want to token factor all of the input chains to these nodes 2334 // together. However, if any of the input chains is actually one of the 2335 // nodes matched in this pattern, then we have an intra-match reference. 2336 // Ignore these because the newly token factored chain should not refer to 2337 // the old nodes. 2338 unsigned NumChains = MatcherTable[MatcherIndex++]; 2339 assert(NumChains != 0 && "Can't TF zero chains"); 2340 2341 assert(ChainNodesMatched.empty() && 2342 "Should only have one EmitMergeInputChains per match"); 2343 2344 // Read all of the chained nodes. 2345 for (unsigned i = 0; i != NumChains; ++i) { 2346 unsigned RecNo = MatcherTable[MatcherIndex++]; 2347 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2348 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2349 2350 // FIXME: What if other value results of the node have uses not matched 2351 // by this pattern? 2352 if (ChainNodesMatched.back() != NodeToMatch && 2353 !RecordedNodes[RecNo].hasOneUse()) { 2354 ChainNodesMatched.clear(); 2355 break; 2356 } 2357 } 2358 2359 // If the inner loop broke out, the match fails. 2360 if (ChainNodesMatched.empty()) 2361 break; 2362 2363 // Merge the input chains if they are not intra-pattern references. 2364 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2365 2366 if (InputChain.getNode() == 0) 2367 break; // Failed to merge. 2368 2369 continue; 2370 } 2371 2372 case OPC_EmitCopyToReg: { 2373 unsigned RecNo = MatcherTable[MatcherIndex++]; 2374 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2375 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2376 2377 if (InputChain.getNode() == 0) 2378 InputChain = CurDAG->getEntryNode(); 2379 2380 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2381 DestPhysReg, RecordedNodes[RecNo], 2382 InputFlag); 2383 2384 InputFlag = InputChain.getValue(1); 2385 continue; 2386 } 2387 2388 case OPC_EmitNodeXForm: { 2389 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2390 unsigned RecNo = MatcherTable[MatcherIndex++]; 2391 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2392 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2393 continue; 2394 } 2395 2396 case OPC_EmitNode: 2397 case OPC_MorphNodeTo: { 2398 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2399 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2400 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2401 // Get the result VT list. 2402 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2403 SmallVector<EVT, 4> VTs; 2404 for (unsigned i = 0; i != NumVTs; ++i) { 2405 MVT::SimpleValueType VT = 2406 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2407 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2408 VTs.push_back(VT); 2409 } 2410 2411 if (EmitNodeInfo & OPFL_Chain) 2412 VTs.push_back(MVT::Other); 2413 if (EmitNodeInfo & OPFL_FlagOutput) 2414 VTs.push_back(MVT::Flag); 2415 2416 // This is hot code, so optimize the two most common cases of 1 and 2 2417 // results. 2418 SDVTList VTList; 2419 if (VTs.size() == 1) 2420 VTList = CurDAG->getVTList(VTs[0]); 2421 else if (VTs.size() == 2) 2422 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2423 else 2424 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2425 2426 // Get the operand list. 2427 unsigned NumOps = MatcherTable[MatcherIndex++]; 2428 SmallVector<SDValue, 8> Ops; 2429 for (unsigned i = 0; i != NumOps; ++i) { 2430 unsigned RecNo = MatcherTable[MatcherIndex++]; 2431 if (RecNo & 128) 2432 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2433 2434 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2435 Ops.push_back(RecordedNodes[RecNo]); 2436 } 2437 2438 // If there are variadic operands to add, handle them now. 2439 if (EmitNodeInfo & OPFL_VariadicInfo) { 2440 // Determine the start index to copy from. 2441 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2442 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2443 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2444 "Invalid variadic node"); 2445 // Copy all of the variadic operands, not including a potential flag 2446 // input. 2447 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2448 i != e; ++i) { 2449 SDValue V = NodeToMatch->getOperand(i); 2450 if (V.getValueType() == MVT::Flag) break; 2451 Ops.push_back(V); 2452 } 2453 } 2454 2455 // If this has chain/flag inputs, add them. 2456 if (EmitNodeInfo & OPFL_Chain) 2457 Ops.push_back(InputChain); 2458 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2459 Ops.push_back(InputFlag); 2460 2461 // Create the node. 2462 SDNode *Res = 0; 2463 if (Opcode != OPC_MorphNodeTo) { 2464 // If this is a normal EmitNode command, just create the new node and 2465 // add the results to the RecordedNodes list. 2466 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2467 VTList, Ops.data(), Ops.size()); 2468 2469 // Add all the non-flag/non-chain results to the RecordedNodes list. 2470 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2471 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2472 RecordedNodes.push_back(SDValue(Res, i)); 2473 } 2474 2475 } else { 2476 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2477 EmitNodeInfo); 2478 } 2479 2480 // If the node had chain/flag results, update our notion of the current 2481 // chain and flag. 2482 if (EmitNodeInfo & OPFL_FlagOutput) { 2483 InputFlag = SDValue(Res, VTs.size()-1); 2484 if (EmitNodeInfo & OPFL_Chain) 2485 InputChain = SDValue(Res, VTs.size()-2); 2486 } else if (EmitNodeInfo & OPFL_Chain) 2487 InputChain = SDValue(Res, VTs.size()-1); 2488 2489 // If the OPFL_MemRefs flag is set on this node, slap all of the 2490 // accumulated memrefs onto it. 2491 // 2492 // FIXME: This is vastly incorrect for patterns with multiple outputs 2493 // instructions that access memory and for ComplexPatterns that match 2494 // loads. 2495 if (EmitNodeInfo & OPFL_MemRefs) { 2496 MachineSDNode::mmo_iterator MemRefs = 2497 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2498 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2499 cast<MachineSDNode>(Res) 2500 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2501 } 2502 2503 DEBUG(errs() << " " 2504 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2505 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2506 2507 // If this was a MorphNodeTo then we're completely done! 2508 if (Opcode == OPC_MorphNodeTo) { 2509 // Update chain and flag uses. 2510 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2511 InputFlag, FlagResultNodesMatched, true); 2512 return Res; 2513 } 2514 2515 continue; 2516 } 2517 2518 case OPC_MarkFlagResults: { 2519 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2520 2521 // Read and remember all the flag-result nodes. 2522 for (unsigned i = 0; i != NumNodes; ++i) { 2523 unsigned RecNo = MatcherTable[MatcherIndex++]; 2524 if (RecNo & 128) 2525 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2526 2527 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2528 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2529 } 2530 continue; 2531 } 2532 2533 case OPC_CompleteMatch: { 2534 // The match has been completed, and any new nodes (if any) have been 2535 // created. Patch up references to the matched dag to use the newly 2536 // created nodes. 2537 unsigned NumResults = MatcherTable[MatcherIndex++]; 2538 2539 for (unsigned i = 0; i != NumResults; ++i) { 2540 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2541 if (ResSlot & 128) 2542 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2543 2544 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2545 SDValue Res = RecordedNodes[ResSlot]; 2546 2547 assert(i < NodeToMatch->getNumValues() && 2548 NodeToMatch->getValueType(i) != MVT::Other && 2549 NodeToMatch->getValueType(i) != MVT::Flag && 2550 "Invalid number of results to complete!"); 2551 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2552 NodeToMatch->getValueType(i) == MVT::iPTR || 2553 Res.getValueType() == MVT::iPTR || 2554 NodeToMatch->getValueType(i).getSizeInBits() == 2555 Res.getValueType().getSizeInBits()) && 2556 "invalid replacement"); 2557 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2558 } 2559 2560 // If the root node defines a flag, add it to the flag nodes to update 2561 // list. 2562 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2563 FlagResultNodesMatched.push_back(NodeToMatch); 2564 2565 // Update chain and flag uses. 2566 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2567 InputFlag, FlagResultNodesMatched, false); 2568 2569 assert(NodeToMatch->use_empty() && 2570 "Didn't replace all uses of the node?"); 2571 2572 // FIXME: We just return here, which interacts correctly with SelectRoot 2573 // above. We should fix this to not return an SDNode* anymore. 2574 return 0; 2575 } 2576 } 2577 2578 // If the code reached this point, then the match failed. See if there is 2579 // another child to try in the current 'Scope', otherwise pop it until we 2580 // find a case to check. 2581 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2582 ++NumDAGIselRetries; 2583 while (1) { 2584 if (MatchScopes.empty()) { 2585 CannotYetSelect(NodeToMatch); 2586 return 0; 2587 } 2588 2589 // Restore the interpreter state back to the point where the scope was 2590 // formed. 2591 MatchScope &LastScope = MatchScopes.back(); 2592 RecordedNodes.resize(LastScope.NumRecordedNodes); 2593 NodeStack.clear(); 2594 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2595 N = NodeStack.back(); 2596 2597 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2598 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2599 MatcherIndex = LastScope.FailIndex; 2600 2601 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2602 2603 InputChain = LastScope.InputChain; 2604 InputFlag = LastScope.InputFlag; 2605 if (!LastScope.HasChainNodesMatched) 2606 ChainNodesMatched.clear(); 2607 if (!LastScope.HasFlagResultNodesMatched) 2608 FlagResultNodesMatched.clear(); 2609 2610 // Check to see what the offset is at the new MatcherIndex. If it is zero 2611 // we have reached the end of this scope, otherwise we have another child 2612 // in the current scope to try. 2613 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2614 if (NumToSkip & 128) 2615 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2616 2617 // If we have another child in this scope to match, update FailIndex and 2618 // try it. 2619 if (NumToSkip != 0) { 2620 LastScope.FailIndex = MatcherIndex+NumToSkip; 2621 break; 2622 } 2623 2624 // End of this scope, pop it and try the next child in the containing 2625 // scope. 2626 MatchScopes.pop_back(); 2627 } 2628 } 2629} 2630 2631 2632 2633void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2634 std::string msg; 2635 raw_string_ostream Msg(msg); 2636 Msg << "Cannot yet select: "; 2637 2638 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2639 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2640 N->getOpcode() != ISD::INTRINSIC_VOID) { 2641 N->printrFull(Msg, CurDAG); 2642 } else { 2643 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2644 unsigned iid = 2645 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2646 if (iid < Intrinsic::num_intrinsics) 2647 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2648 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2649 Msg << "target intrinsic %" << TII->getName(iid); 2650 else 2651 Msg << "unknown intrinsic #" << iid; 2652 } 2653 report_fatal_error(Msg.str()); 2654} 2655 2656char SelectionDAGISel::ID = 0; 2657