SelectionDAGISel.cpp revision b6d3f2514f08b9451a7b7fb8599c87aba6f0cb7f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 37#include "llvm/CodeGen/SchedulerRegistry.h" 38#include "llvm/CodeGen/SelectionDAG.h" 39#include "llvm/Target/TargetRegisterInfo.h" 40#include "llvm/Target/TargetIntrinsicInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ErrorHandling.h" 48#include "llvm/Support/Timer.h" 49#include "llvm/Support/raw_ostream.h" 50#include "llvm/ADT/Statistic.h" 51#include <algorithm> 52using namespace llvm; 53 54STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 55STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 56 57static cl::opt<bool> 58EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 59 cl::desc("Enable verbose messages in the \"fast\" " 60 "instruction selector")); 61static cl::opt<bool> 62EnableFastISelAbort("fast-isel-abort", cl::Hidden, 63 cl::desc("Enable abort calls when \"fast\" instruction fails")); 64 65#ifndef NDEBUG 66static cl::opt<bool> 67ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 68 cl::desc("Pop up a window to show dags before the first " 69 "dag combine pass")); 70static cl::opt<bool> 71ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 72 cl::desc("Pop up a window to show dags before legalize types")); 73static cl::opt<bool> 74ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 75 cl::desc("Pop up a window to show dags before legalize")); 76static cl::opt<bool> 77ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 78 cl::desc("Pop up a window to show dags before the second " 79 "dag combine pass")); 80static cl::opt<bool> 81ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 82 cl::desc("Pop up a window to show dags before the post legalize types" 83 " dag combine pass")); 84static cl::opt<bool> 85ViewISelDAGs("view-isel-dags", cl::Hidden, 86 cl::desc("Pop up a window to show isel dags as they are selected")); 87static cl::opt<bool> 88ViewSchedDAGs("view-sched-dags", cl::Hidden, 89 cl::desc("Pop up a window to show sched dags as they are processed")); 90static cl::opt<bool> 91ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 92 cl::desc("Pop up a window to show SUnit dags after they are processed")); 93#else 94static const bool ViewDAGCombine1 = false, 95 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 96 ViewDAGCombine2 = false, 97 ViewDAGCombineLT = false, 98 ViewISelDAGs = false, ViewSchedDAGs = false, 99 ViewSUnitDAGs = false; 100#endif 101 102//===---------------------------------------------------------------------===// 103/// 104/// RegisterScheduler class - Track the registration of instruction schedulers. 105/// 106//===---------------------------------------------------------------------===// 107MachinePassRegistry RegisterScheduler::Registry; 108 109//===---------------------------------------------------------------------===// 110/// 111/// ISHeuristic command line option for instruction schedulers. 112/// 113//===---------------------------------------------------------------------===// 114static cl::opt<RegisterScheduler::FunctionPassCtor, false, 115 RegisterPassParser<RegisterScheduler> > 116ISHeuristic("pre-RA-sched", 117 cl::init(&createDefaultScheduler), 118 cl::desc("Instruction schedulers available (before register" 119 " allocation):")); 120 121static RegisterScheduler 122defaultListDAGScheduler("default", "Best scheduler for the target", 123 createDefaultScheduler); 124 125namespace llvm { 126 //===--------------------------------------------------------------------===// 127 /// createDefaultScheduler - This creates an instruction scheduler appropriate 128 /// for the target. 129 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 130 CodeGenOpt::Level OptLevel) { 131 const TargetLowering &TLI = IS->getTargetLowering(); 132 133 if (OptLevel == CodeGenOpt::None) 134 return createFastDAGScheduler(IS, OptLevel); 135 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 136 return createTDListDAGScheduler(IS, OptLevel); 137 assert(TLI.getSchedulingPreference() == 138 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 139 return createBURRListDAGScheduler(IS, OptLevel); 140 } 141} 142 143// EmitInstrWithCustomInserter - This method should be implemented by targets 144// that mark instructions with the 'usesCustomInserter' flag. These 145// instructions are special in various ways, which require special support to 146// insert. The specified MachineInstr is created but not inserted into any 147// basic blocks, and this method is called to expand it into a sequence of 148// instructions, potentially also creating new basic blocks and control flow. 149// When new basic blocks are inserted and the edges from MBB to its successors 150// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 151// DenseMap. 152MachineBasicBlock * 153TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 154 MachineBasicBlock *MBB) const { 155#ifndef NDEBUG 156 dbgs() << "If a target marks an instruction with " 157 "'usesCustomInserter', it must implement " 158 "TargetLowering::EmitInstrWithCustomInserter!"; 159#endif 160 llvm_unreachable(0); 161 return 0; 162} 163 164//===----------------------------------------------------------------------===// 165// SelectionDAGISel code 166//===----------------------------------------------------------------------===// 167 168SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 169 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 170 FuncInfo(new FunctionLoweringInfo(TLI)), 171 CurDAG(new SelectionDAG(tm, *FuncInfo)), 172 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 173 GFI(), 174 OptLevel(OL), 175 DAGSize(0) 176{} 177 178SelectionDAGISel::~SelectionDAGISel() { 179 delete SDB; 180 delete CurDAG; 181 delete FuncInfo; 182} 183 184void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 185 AU.addRequired<AliasAnalysis>(); 186 AU.addPreserved<AliasAnalysis>(); 187 AU.addRequired<GCModuleInfo>(); 188 AU.addPreserved<GCModuleInfo>(); 189 MachineFunctionPass::getAnalysisUsage(AU); 190} 191 192bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 193 // Do some sanity-checking on the command-line options. 194 assert((!EnableFastISelVerbose || EnableFastISel) && 195 "-fast-isel-verbose requires -fast-isel"); 196 assert((!EnableFastISelAbort || EnableFastISel) && 197 "-fast-isel-abort requires -fast-isel"); 198 199 const Function &Fn = *mf.getFunction(); 200 const TargetInstrInfo &TII = *TM.getInstrInfo(); 201 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 202 203 MF = &mf; 204 RegInfo = &MF->getRegInfo(); 205 AA = &getAnalysis<AliasAnalysis>(); 206 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 207 208 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 209 210 CurDAG->init(*MF); 211 FuncInfo->set(Fn, *MF, EnableFastISel); 212 SDB->init(GFI, *AA); 213 214 SelectAllBasicBlocks(Fn); 215 216 // If the first basic block in the function has live ins that need to be 217 // copied into vregs, emit the copies into the top of the block before 218 // emitting the code for the block. 219 MachineBasicBlock *EntryMBB = MF->begin(); 220 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 221 222 // Insert DBG_VALUE instructions for function arguments to the entry block. 223 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 224 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 225 unsigned Reg = MI->getOperand(0).getReg(); 226 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 227 EntryMBB->insert(EntryMBB->begin(), MI); 228 else { 229 MachineInstr *Def = RegInfo->getVRegDef(Reg); 230 MachineBasicBlock::iterator InsertPos = Def; 231 // FIXME: VR def may not be in entry block. 232 Def->getParent()->insert(llvm::next(InsertPos), MI); 233 } 234 } 235 236 // Release function-specific state. SDB and CurDAG are already cleared 237 // at this point. 238 FuncInfo->clear(); 239 240 return true; 241} 242 243MachineBasicBlock * 244SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 245 const BasicBlock *LLVMBB, 246 BasicBlock::const_iterator Begin, 247 BasicBlock::const_iterator End, 248 bool &HadTailCall) { 249 // Lower all of the non-terminator instructions. If a call is emitted 250 // as a tail call, cease emitting nodes for this block. Terminators 251 // are handled below. 252 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 253 SDB->visit(*I); 254 255 // Make sure the root of the DAG is up-to-date. 256 CurDAG->setRoot(SDB->getControlRoot()); 257 HadTailCall = SDB->HasTailCall; 258 SDB->clear(); 259 260 // Final step, emit the lowered DAG as machine code. 261 return CodeGenAndEmitDAG(BB); 262} 263 264namespace { 265/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 266/// nodes from the worklist. 267class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 268 SmallVector<SDNode*, 128> &Worklist; 269 SmallPtrSet<SDNode*, 128> &InWorklist; 270public: 271 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 272 SmallPtrSet<SDNode*, 128> &inwl) 273 : Worklist(wl), InWorklist(inwl) {} 274 275 void RemoveFromWorklist(SDNode *N) { 276 if (!InWorklist.erase(N)) return; 277 278 SmallVector<SDNode*, 128>::iterator I = 279 std::find(Worklist.begin(), Worklist.end(), N); 280 assert(I != Worklist.end() && "Not in worklist"); 281 282 *I = Worklist.back(); 283 Worklist.pop_back(); 284 } 285 286 virtual void NodeDeleted(SDNode *N, SDNode *E) { 287 RemoveFromWorklist(N); 288 } 289 290 virtual void NodeUpdated(SDNode *N) { 291 // Ignore updates. 292 } 293}; 294} 295 296/// TrivialTruncElim - Eliminate some trivial nops that can result from 297/// ShrinkDemandedOps: (trunc (ext n)) -> n. 298static bool TrivialTruncElim(SDValue Op, 299 TargetLowering::TargetLoweringOpt &TLO) { 300 SDValue N0 = Op.getOperand(0); 301 EVT VT = Op.getValueType(); 302 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 303 N0.getOpcode() == ISD::SIGN_EXTEND || 304 N0.getOpcode() == ISD::ANY_EXTEND) && 305 N0.getOperand(0).getValueType() == VT) { 306 return TLO.CombineTo(Op, N0.getOperand(0)); 307 } 308 return false; 309} 310 311/// ShrinkDemandedOps - A late transformation pass that shrink expressions 312/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 313/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 314void SelectionDAGISel::ShrinkDemandedOps() { 315 SmallVector<SDNode*, 128> Worklist; 316 SmallPtrSet<SDNode*, 128> InWorklist; 317 318 // Add all the dag nodes to the worklist. 319 Worklist.reserve(CurDAG->allnodes_size()); 320 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 321 E = CurDAG->allnodes_end(); I != E; ++I) { 322 Worklist.push_back(I); 323 InWorklist.insert(I); 324 } 325 326 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 327 while (!Worklist.empty()) { 328 SDNode *N = Worklist.pop_back_val(); 329 InWorklist.erase(N); 330 331 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 332 // Deleting this node may make its operands dead, add them to the worklist 333 // if they aren't already there. 334 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 335 if (InWorklist.insert(N->getOperand(i).getNode())) 336 Worklist.push_back(N->getOperand(i).getNode()); 337 338 CurDAG->DeleteNode(N); 339 continue; 340 } 341 342 // Run ShrinkDemandedOp on scalar binary operations. 343 if (N->getNumValues() != 1 || 344 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 345 continue; 346 347 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 348 APInt Demanded = APInt::getAllOnesValue(BitWidth); 349 APInt KnownZero, KnownOne; 350 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 351 KnownZero, KnownOne, TLO) && 352 (N->getOpcode() != ISD::TRUNCATE || 353 !TrivialTruncElim(SDValue(N, 0), TLO))) 354 continue; 355 356 // Revisit the node. 357 assert(!InWorklist.count(N) && "Already in worklist"); 358 Worklist.push_back(N); 359 InWorklist.insert(N); 360 361 // Replace the old value with the new one. 362 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 363 TLO.Old.getNode()->dump(CurDAG); 364 errs() << "\nWith: "; 365 TLO.New.getNode()->dump(CurDAG); 366 errs() << '\n'); 367 368 if (InWorklist.insert(TLO.New.getNode())) 369 Worklist.push_back(TLO.New.getNode()); 370 371 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 372 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 373 374 if (!TLO.Old.getNode()->use_empty()) continue; 375 376 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 377 i != e; ++i) { 378 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 379 if (OpNode->hasOneUse()) { 380 // Add OpNode to the end of the list to revisit. 381 DeadNodes.RemoveFromWorklist(OpNode); 382 Worklist.push_back(OpNode); 383 InWorklist.insert(OpNode); 384 } 385 } 386 387 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 388 CurDAG->DeleteNode(TLO.Old.getNode()); 389 } 390} 391 392void SelectionDAGISel::ComputeLiveOutVRegInfo() { 393 SmallPtrSet<SDNode*, 128> VisitedNodes; 394 SmallVector<SDNode*, 128> Worklist; 395 396 Worklist.push_back(CurDAG->getRoot().getNode()); 397 398 APInt Mask; 399 APInt KnownZero; 400 APInt KnownOne; 401 402 do { 403 SDNode *N = Worklist.pop_back_val(); 404 405 // If we've already seen this node, ignore it. 406 if (!VisitedNodes.insert(N)) 407 continue; 408 409 // Otherwise, add all chain operands to the worklist. 410 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 411 if (N->getOperand(i).getValueType() == MVT::Other) 412 Worklist.push_back(N->getOperand(i).getNode()); 413 414 // If this is a CopyToReg with a vreg dest, process it. 415 if (N->getOpcode() != ISD::CopyToReg) 416 continue; 417 418 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 419 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 420 continue; 421 422 // Ignore non-scalar or non-integer values. 423 SDValue Src = N->getOperand(2); 424 EVT SrcVT = Src.getValueType(); 425 if (!SrcVT.isInteger() || SrcVT.isVector()) 426 continue; 427 428 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 429 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 430 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 431 432 // Only install this information if it tells us something. 433 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 434 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 435 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 436 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 437 FunctionLoweringInfo::LiveOutInfo &LOI = 438 FuncInfo->LiveOutRegInfo[DestReg]; 439 LOI.NumSignBits = NumSignBits; 440 LOI.KnownOne = KnownOne; 441 LOI.KnownZero = KnownZero; 442 } 443 } while (!Worklist.empty()); 444} 445 446MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 447 std::string GroupName; 448 if (TimePassesIsEnabled) 449 GroupName = "Instruction Selection and Scheduling"; 450 std::string BlockName; 451 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 452 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 453 ViewSUnitDAGs) 454 BlockName = MF->getFunction()->getNameStr() + ":" + 455 BB->getBasicBlock()->getNameStr(); 456 457 DEBUG(dbgs() << "Initial selection DAG:\n"); 458 DEBUG(CurDAG->dump()); 459 460 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 461 462 // Run the DAG combiner in pre-legalize mode. 463 if (TimePassesIsEnabled) { 464 NamedRegionTimer T("DAG Combining 1", GroupName); 465 CurDAG->Combine(Unrestricted, *AA, OptLevel); 466 } else { 467 CurDAG->Combine(Unrestricted, *AA, OptLevel); 468 } 469 470 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 471 DEBUG(CurDAG->dump()); 472 473 // Second step, hack on the DAG until it only uses operations and types that 474 // the target supports. 475 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 476 BlockName); 477 478 bool Changed; 479 if (TimePassesIsEnabled) { 480 NamedRegionTimer T("Type Legalization", GroupName); 481 Changed = CurDAG->LegalizeTypes(); 482 } else { 483 Changed = CurDAG->LegalizeTypes(); 484 } 485 486 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 487 DEBUG(CurDAG->dump()); 488 489 if (Changed) { 490 if (ViewDAGCombineLT) 491 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 492 493 // Run the DAG combiner in post-type-legalize mode. 494 if (TimePassesIsEnabled) { 495 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 496 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 497 } else { 498 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 499 } 500 501 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 502 DEBUG(CurDAG->dump()); 503 } 504 505 if (TimePassesIsEnabled) { 506 NamedRegionTimer T("Vector Legalization", GroupName); 507 Changed = CurDAG->LegalizeVectors(); 508 } else { 509 Changed = CurDAG->LegalizeVectors(); 510 } 511 512 if (Changed) { 513 if (TimePassesIsEnabled) { 514 NamedRegionTimer T("Type Legalization 2", GroupName); 515 CurDAG->LegalizeTypes(); 516 } else { 517 CurDAG->LegalizeTypes(); 518 } 519 520 if (ViewDAGCombineLT) 521 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 522 523 // Run the DAG combiner in post-type-legalize mode. 524 if (TimePassesIsEnabled) { 525 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 526 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 527 } else { 528 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 529 } 530 531 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 532 DEBUG(CurDAG->dump()); 533 } 534 535 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 536 537 if (TimePassesIsEnabled) { 538 NamedRegionTimer T("DAG Legalization", GroupName); 539 CurDAG->Legalize(OptLevel); 540 } else { 541 CurDAG->Legalize(OptLevel); 542 } 543 544 DEBUG(dbgs() << "Legalized selection DAG:\n"); 545 DEBUG(CurDAG->dump()); 546 547 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 548 549 // Run the DAG combiner in post-legalize mode. 550 if (TimePassesIsEnabled) { 551 NamedRegionTimer T("DAG Combining 2", GroupName); 552 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 553 } else { 554 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 555 } 556 557 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 558 DEBUG(CurDAG->dump()); 559 560 if (OptLevel != CodeGenOpt::None) { 561 ShrinkDemandedOps(); 562 ComputeLiveOutVRegInfo(); 563 } 564 565 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 566 567 // Third, instruction select all of the operations to machine code, adding the 568 // code to the MachineBasicBlock. 569 if (TimePassesIsEnabled) { 570 NamedRegionTimer T("Instruction Selection", GroupName); 571 DoInstructionSelection(); 572 } else { 573 DoInstructionSelection(); 574 } 575 576 DEBUG(dbgs() << "Selected selection DAG:\n"); 577 DEBUG(CurDAG->dump()); 578 579 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 580 581 // Schedule machine code. 582 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 583 if (TimePassesIsEnabled) { 584 NamedRegionTimer T("Instruction Scheduling", GroupName); 585 Scheduler->Run(CurDAG, BB, BB->end()); 586 } else { 587 Scheduler->Run(CurDAG, BB, BB->end()); 588 } 589 590 if (ViewSUnitDAGs) Scheduler->viewGraph(); 591 592 // Emit machine code to BB. This can change 'BB' to the last block being 593 // inserted into. 594 if (TimePassesIsEnabled) { 595 NamedRegionTimer T("Instruction Creation", GroupName); 596 BB = Scheduler->EmitSchedule(); 597 } else { 598 BB = Scheduler->EmitSchedule(); 599 } 600 601 // Free the scheduler state. 602 if (TimePassesIsEnabled) { 603 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 604 delete Scheduler; 605 } else { 606 delete Scheduler; 607 } 608 609 // Determine if there are any calls in this machine function. 610 MachineFrameInfo *MFI = MF->getFrameInfo(); 611 if (!MFI->hasCalls()) { 612 for (MachineBasicBlock::iterator 613 I = BB->begin(), E = BB->end(); I != E; ++I) { 614 const TargetInstrDesc &TID = TM.getInstrInfo()->get(I->getOpcode()); 615 if (I->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 616 MFI->setHasCalls(true); 617 break; 618 } 619 } 620 } 621 622 // Free the SelectionDAG state, now that we're finished with it. 623 CurDAG->clear(); 624 625 return BB; 626} 627 628void SelectionDAGISel::DoInstructionSelection() { 629 DEBUG(errs() << "===== Instruction selection begins:\n"); 630 631 PreprocessISelDAG(); 632 633 // Select target instructions for the DAG. 634 { 635 // Number all nodes with a topological order and set DAGSize. 636 DAGSize = CurDAG->AssignTopologicalOrder(); 637 638 // Create a dummy node (which is not added to allnodes), that adds 639 // a reference to the root node, preventing it from being deleted, 640 // and tracking any changes of the root. 641 HandleSDNode Dummy(CurDAG->getRoot()); 642 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 643 ++ISelPosition; 644 645 // The AllNodes list is now topological-sorted. Visit the 646 // nodes by starting at the end of the list (the root of the 647 // graph) and preceding back toward the beginning (the entry 648 // node). 649 while (ISelPosition != CurDAG->allnodes_begin()) { 650 SDNode *Node = --ISelPosition; 651 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 652 // but there are currently some corner cases that it misses. Also, this 653 // makes it theoretically possible to disable the DAGCombiner. 654 if (Node->use_empty()) 655 continue; 656 657 SDNode *ResNode = Select(Node); 658 659 // FIXME: This is pretty gross. 'Select' should be changed to not return 660 // anything at all and this code should be nuked with a tactical strike. 661 662 // If node should not be replaced, continue with the next one. 663 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 664 continue; 665 // Replace node. 666 if (ResNode) 667 ReplaceUses(Node, ResNode); 668 669 // If after the replacement this node is not used any more, 670 // remove this dead node. 671 if (Node->use_empty()) { // Don't delete EntryToken, etc. 672 ISelUpdater ISU(ISelPosition); 673 CurDAG->RemoveDeadNode(Node, &ISU); 674 } 675 } 676 677 CurDAG->setRoot(Dummy.getValue()); 678 } 679 DEBUG(errs() << "===== Instruction selection ends:\n"); 680 681 PostprocessISelDAG(); 682} 683 684/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 685/// do other setup for EH landing-pad blocks. 686void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 687 // Add a label to mark the beginning of the landing pad. Deletion of the 688 // landing pad can thus be detected via the MachineModuleInfo. 689 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 690 691 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 692 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 693 694 // Mark exception register as live in. 695 unsigned Reg = TLI.getExceptionAddressRegister(); 696 if (Reg) BB->addLiveIn(Reg); 697 698 // Mark exception selector register as live in. 699 Reg = TLI.getExceptionSelectorRegister(); 700 if (Reg) BB->addLiveIn(Reg); 701 702 // FIXME: Hack around an exception handling flaw (PR1508): the personality 703 // function and list of typeids logically belong to the invoke (or, if you 704 // like, the basic block containing the invoke), and need to be associated 705 // with it in the dwarf exception handling tables. Currently however the 706 // information is provided by an intrinsic (eh.selector) that can be moved 707 // to unexpected places by the optimizers: if the unwind edge is critical, 708 // then breaking it can result in the intrinsics being in the successor of 709 // the landing pad, not the landing pad itself. This results 710 // in exceptions not being caught because no typeids are associated with 711 // the invoke. This may not be the only way things can go wrong, but it 712 // is the only way we try to work around for the moment. 713 const BasicBlock *LLVMBB = BB->getBasicBlock(); 714 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 715 716 if (Br && Br->isUnconditional()) { // Critical edge? 717 BasicBlock::const_iterator I, E; 718 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 719 if (isa<EHSelectorInst>(I)) 720 break; 721 722 if (I == E) 723 // No catch info found - try to extract some from the successor. 724 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 725 } 726} 727 728void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 729 // Initialize the Fast-ISel state, if needed. 730 FastISel *FastIS = 0; 731 if (EnableFastISel) 732 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 733 FuncInfo->StaticAllocaMap, 734 FuncInfo->PHINodesToUpdate 735#ifndef NDEBUG 736 , FuncInfo->CatchInfoLost 737#endif 738 ); 739 740 // Iterate over all basic blocks in the function. 741 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 742 const BasicBlock *LLVMBB = &*I; 743 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 744 745 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 746 BasicBlock::const_iterator const End = LLVMBB->end(); 747 BasicBlock::const_iterator BI = Begin; 748 749 // Lower any arguments needed in this block if this is the entry block. 750 if (LLVMBB == &Fn.getEntryBlock()) 751 LowerArguments(LLVMBB); 752 753 // Setup an EH landing-pad block. 754 if (BB->isLandingPad()) 755 PrepareEHLandingPad(BB); 756 757 // Before doing SelectionDAG ISel, see if FastISel has been requested. 758 if (FastIS) { 759 // Emit code for any incoming arguments. This must happen before 760 // beginning FastISel on the entry block. 761 if (LLVMBB == &Fn.getEntryBlock()) { 762 CurDAG->setRoot(SDB->getControlRoot()); 763 SDB->clear(); 764 BB = CodeGenAndEmitDAG(BB); 765 } 766 FastIS->startNewBlock(BB); 767 // Do FastISel on as many instructions as possible. 768 for (; BI != End; ++BI) { 769 // Try to select the instruction with FastISel. 770 if (FastIS->SelectInstruction(BI)) 771 continue; 772 773 // Then handle certain instructions as single-LLVM-Instruction blocks. 774 if (isa<CallInst>(BI)) { 775 ++NumFastIselFailures; 776 if (EnableFastISelVerbose || EnableFastISelAbort) { 777 dbgs() << "FastISel missed call: "; 778 BI->dump(); 779 } 780 781 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 782 unsigned &R = FuncInfo->ValueMap[BI]; 783 if (!R) 784 R = FuncInfo->CreateRegForValue(BI); 785 } 786 787 bool HadTailCall = false; 788 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 789 790 // If the call was emitted as a tail call, we're done with the block. 791 if (HadTailCall) { 792 BI = End; 793 break; 794 } 795 796 // If the instruction was codegen'd with multiple blocks, 797 // inform the FastISel object where to resume inserting. 798 FastIS->setCurrentBlock(BB); 799 continue; 800 } 801 802 // Otherwise, give up on FastISel for the rest of the block. 803 // For now, be a little lenient about non-branch terminators. 804 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 805 ++NumFastIselFailures; 806 if (EnableFastISelVerbose || EnableFastISelAbort) { 807 dbgs() << "FastISel miss: "; 808 BI->dump(); 809 } 810 if (EnableFastISelAbort) 811 // The "fast" selector couldn't handle something and bailed. 812 // For the purpose of debugging, just abort. 813 llvm_unreachable("FastISel didn't select the entire block"); 814 } 815 break; 816 } 817 } 818 819 // Run SelectionDAG instruction selection on the remainder of the block 820 // not handled by FastISel. If FastISel is not run, this is the entire 821 // block. 822 if (BI != End) { 823 bool HadTailCall; 824 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 825 } 826 827 FinishBasicBlock(BB); 828 FuncInfo->PHINodesToUpdate.clear(); 829 } 830 831 delete FastIS; 832} 833 834void 835SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 836 837 DEBUG(dbgs() << "Total amount of phi nodes to update: " 838 << FuncInfo->PHINodesToUpdate.size() << "\n"); 839 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 840 dbgs() << "Node " << i << " : (" 841 << FuncInfo->PHINodesToUpdate[i].first 842 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 843 844 // Next, now that we know what the last MBB the LLVM BB expanded is, update 845 // PHI nodes in successors. 846 if (SDB->SwitchCases.empty() && 847 SDB->JTCases.empty() && 848 SDB->BitTestCases.empty()) { 849 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 850 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 851 assert(PHI->isPHI() && 852 "This is not a machine PHI node that we are updating!"); 853 if (!BB->isSuccessor(PHI->getParent())) 854 continue; 855 PHI->addOperand( 856 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 857 PHI->addOperand(MachineOperand::CreateMBB(BB)); 858 } 859 return; 860 } 861 862 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 863 // Lower header first, if it wasn't already lowered 864 if (!SDB->BitTestCases[i].Emitted) { 865 // Set the current basic block to the mbb we wish to insert the code into 866 BB = SDB->BitTestCases[i].Parent; 867 // Emit the code 868 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 869 CurDAG->setRoot(SDB->getRoot()); 870 SDB->clear(); 871 BB = CodeGenAndEmitDAG(BB); 872 } 873 874 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 875 // Set the current basic block to the mbb we wish to insert the code into 876 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 877 // Emit the code 878 if (j+1 != ej) 879 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 880 SDB->BitTestCases[i].Reg, 881 SDB->BitTestCases[i].Cases[j], 882 BB); 883 else 884 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 885 SDB->BitTestCases[i].Reg, 886 SDB->BitTestCases[i].Cases[j], 887 BB); 888 889 890 CurDAG->setRoot(SDB->getRoot()); 891 SDB->clear(); 892 BB = CodeGenAndEmitDAG(BB); 893 } 894 895 // Update PHI Nodes 896 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 897 pi != pe; ++pi) { 898 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 899 MachineBasicBlock *PHIBB = PHI->getParent(); 900 assert(PHI->isPHI() && 901 "This is not a machine PHI node that we are updating!"); 902 // This is "default" BB. We have two jumps to it. From "header" BB and 903 // from last "case" BB. 904 if (PHIBB == SDB->BitTestCases[i].Default) { 905 PHI->addOperand(MachineOperand:: 906 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 907 false)); 908 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 909 PHI->addOperand(MachineOperand:: 910 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 911 false)); 912 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 913 back().ThisBB)); 914 } 915 // One of "cases" BB. 916 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 917 j != ej; ++j) { 918 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 919 if (cBB->isSuccessor(PHIBB)) { 920 PHI->addOperand(MachineOperand:: 921 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 922 false)); 923 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 924 } 925 } 926 } 927 } 928 SDB->BitTestCases.clear(); 929 930 // If the JumpTable record is filled in, then we need to emit a jump table. 931 // Updating the PHI nodes is tricky in this case, since we need to determine 932 // whether the PHI is a successor of the range check MBB or the jump table MBB 933 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 934 // Lower header first, if it wasn't already lowered 935 if (!SDB->JTCases[i].first.Emitted) { 936 // Set the current basic block to the mbb we wish to insert the code into 937 BB = SDB->JTCases[i].first.HeaderBB; 938 // Emit the code 939 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 940 BB); 941 CurDAG->setRoot(SDB->getRoot()); 942 SDB->clear(); 943 BB = CodeGenAndEmitDAG(BB); 944 } 945 946 // Set the current basic block to the mbb we wish to insert the code into 947 BB = SDB->JTCases[i].second.MBB; 948 // Emit the code 949 SDB->visitJumpTable(SDB->JTCases[i].second); 950 CurDAG->setRoot(SDB->getRoot()); 951 SDB->clear(); 952 BB = CodeGenAndEmitDAG(BB); 953 954 // Update PHI Nodes 955 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 956 pi != pe; ++pi) { 957 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 958 MachineBasicBlock *PHIBB = PHI->getParent(); 959 assert(PHI->isPHI() && 960 "This is not a machine PHI node that we are updating!"); 961 // "default" BB. We can go there only from header BB. 962 if (PHIBB == SDB->JTCases[i].second.Default) { 963 PHI->addOperand 964 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 965 false)); 966 PHI->addOperand 967 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 968 } 969 // JT BB. Just iterate over successors here 970 if (BB->isSuccessor(PHIBB)) { 971 PHI->addOperand 972 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 973 false)); 974 PHI->addOperand(MachineOperand::CreateMBB(BB)); 975 } 976 } 977 } 978 SDB->JTCases.clear(); 979 980 // If the switch block involved a branch to one of the actual successors, we 981 // need to update PHI nodes in that block. 982 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 983 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 984 assert(PHI->isPHI() && 985 "This is not a machine PHI node that we are updating!"); 986 if (BB->isSuccessor(PHI->getParent())) { 987 PHI->addOperand( 988 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 989 PHI->addOperand(MachineOperand::CreateMBB(BB)); 990 } 991 } 992 993 // If we generated any switch lowering information, build and codegen any 994 // additional DAGs necessary. 995 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 996 // Set the current basic block to the mbb we wish to insert the code into 997 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 998 999 // Determine the unique successors. 1000 SmallVector<MachineBasicBlock *, 2> Succs; 1001 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1002 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1003 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1004 1005 // Emit the code. Note that this could result in ThisBB being split, so 1006 // we need to check for updates. 1007 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1008 CurDAG->setRoot(SDB->getRoot()); 1009 SDB->clear(); 1010 ThisBB = CodeGenAndEmitDAG(BB); 1011 1012 // Handle any PHI nodes in successors of this chunk, as if we were coming 1013 // from the original BB before switch expansion. Note that PHI nodes can 1014 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1015 // handle them the right number of times. 1016 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1017 BB = Succs[i]; 1018 // BB may have been removed from the CFG if a branch was constant folded. 1019 if (ThisBB->isSuccessor(BB)) { 1020 for (MachineBasicBlock::iterator Phi = BB->begin(); 1021 Phi != BB->end() && Phi->isPHI(); 1022 ++Phi) { 1023 // This value for this PHI node is recorded in PHINodesToUpdate. 1024 for (unsigned pn = 0; ; ++pn) { 1025 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1026 "Didn't find PHI entry!"); 1027 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1028 Phi->addOperand(MachineOperand:: 1029 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1030 false)); 1031 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1032 break; 1033 } 1034 } 1035 } 1036 } 1037 } 1038 } 1039 SDB->SwitchCases.clear(); 1040} 1041 1042 1043/// Create the scheduler. If a specific scheduler was specified 1044/// via the SchedulerRegistry, use it, otherwise select the 1045/// one preferred by the target. 1046/// 1047ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1048 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1049 1050 if (!Ctor) { 1051 Ctor = ISHeuristic; 1052 RegisterScheduler::setDefault(Ctor); 1053 } 1054 1055 return Ctor(this, OptLevel); 1056} 1057 1058ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1059 return new ScheduleHazardRecognizer(); 1060} 1061 1062//===----------------------------------------------------------------------===// 1063// Helper functions used by the generated instruction selector. 1064//===----------------------------------------------------------------------===// 1065// Calls to these methods are generated by tblgen. 1066 1067/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1068/// the dag combiner simplified the 255, we still want to match. RHS is the 1069/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1070/// specified in the .td file (e.g. 255). 1071bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1072 int64_t DesiredMaskS) const { 1073 const APInt &ActualMask = RHS->getAPIntValue(); 1074 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1075 1076 // If the actual mask exactly matches, success! 1077 if (ActualMask == DesiredMask) 1078 return true; 1079 1080 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1081 if (ActualMask.intersects(~DesiredMask)) 1082 return false; 1083 1084 // Otherwise, the DAG Combiner may have proven that the value coming in is 1085 // either already zero or is not demanded. Check for known zero input bits. 1086 APInt NeededMask = DesiredMask & ~ActualMask; 1087 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1088 return true; 1089 1090 // TODO: check to see if missing bits are just not demanded. 1091 1092 // Otherwise, this pattern doesn't match. 1093 return false; 1094} 1095 1096/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1097/// the dag combiner simplified the 255, we still want to match. RHS is the 1098/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1099/// specified in the .td file (e.g. 255). 1100bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1101 int64_t DesiredMaskS) const { 1102 const APInt &ActualMask = RHS->getAPIntValue(); 1103 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1104 1105 // If the actual mask exactly matches, success! 1106 if (ActualMask == DesiredMask) 1107 return true; 1108 1109 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1110 if (ActualMask.intersects(~DesiredMask)) 1111 return false; 1112 1113 // Otherwise, the DAG Combiner may have proven that the value coming in is 1114 // either already zero or is not demanded. Check for known zero input bits. 1115 APInt NeededMask = DesiredMask & ~ActualMask; 1116 1117 APInt KnownZero, KnownOne; 1118 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1119 1120 // If all the missing bits in the or are already known to be set, match! 1121 if ((NeededMask & KnownOne) == NeededMask) 1122 return true; 1123 1124 // TODO: check to see if missing bits are just not demanded. 1125 1126 // Otherwise, this pattern doesn't match. 1127 return false; 1128} 1129 1130 1131/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1132/// by tblgen. Others should not call it. 1133void SelectionDAGISel:: 1134SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1135 std::vector<SDValue> InOps; 1136 std::swap(InOps, Ops); 1137 1138 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1139 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1140 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1141 1142 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1143 if (InOps[e-1].getValueType() == MVT::Flag) 1144 --e; // Don't process a flag operand if it is here. 1145 1146 while (i != e) { 1147 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1148 if (!InlineAsm::isMemKind(Flags)) { 1149 // Just skip over this operand, copying the operands verbatim. 1150 Ops.insert(Ops.end(), InOps.begin()+i, 1151 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1152 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1153 } else { 1154 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1155 "Memory operand with multiple values?"); 1156 // Otherwise, this is a memory operand. Ask the target to select it. 1157 std::vector<SDValue> SelOps; 1158 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1159 report_fatal_error("Could not match memory address. Inline asm" 1160 " failure!"); 1161 1162 // Add this to the output node. 1163 unsigned NewFlags = 1164 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1165 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1166 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1167 i += 2; 1168 } 1169 } 1170 1171 // Add the flag input back if present. 1172 if (e != InOps.size()) 1173 Ops.push_back(InOps.back()); 1174} 1175 1176/// findFlagUse - Return use of EVT::Flag value produced by the specified 1177/// SDNode. 1178/// 1179static SDNode *findFlagUse(SDNode *N) { 1180 unsigned FlagResNo = N->getNumValues()-1; 1181 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1182 SDUse &Use = I.getUse(); 1183 if (Use.getResNo() == FlagResNo) 1184 return Use.getUser(); 1185 } 1186 return NULL; 1187} 1188 1189/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1190/// This function recursively traverses up the operand chain, ignoring 1191/// certain nodes. 1192static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1193 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1194 bool IgnoreChains) { 1195 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1196 // greater than all of its (recursive) operands. If we scan to a point where 1197 // 'use' is smaller than the node we're scanning for, then we know we will 1198 // never find it. 1199 // 1200 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1201 // happen because we scan down to newly selected nodes in the case of flag 1202 // uses. 1203 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1204 return false; 1205 1206 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1207 // won't fail if we scan it again. 1208 if (!Visited.insert(Use)) 1209 return false; 1210 1211 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1212 // Ignore chain uses, they are validated by HandleMergeInputChains. 1213 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1214 continue; 1215 1216 SDNode *N = Use->getOperand(i).getNode(); 1217 if (N == Def) { 1218 if (Use == ImmedUse || Use == Root) 1219 continue; // We are not looking for immediate use. 1220 assert(N != Root); 1221 return true; 1222 } 1223 1224 // Traverse up the operand chain. 1225 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1226 return true; 1227 } 1228 return false; 1229} 1230 1231/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1232/// operand node N of U during instruction selection that starts at Root. 1233bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1234 SDNode *Root) const { 1235 if (OptLevel == CodeGenOpt::None) return false; 1236 return N.hasOneUse(); 1237} 1238 1239/// IsLegalToFold - Returns true if the specific operand node N of 1240/// U can be folded during instruction selection that starts at Root. 1241bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1242 CodeGenOpt::Level OptLevel, 1243 bool IgnoreChains) { 1244 if (OptLevel == CodeGenOpt::None) return false; 1245 1246 // If Root use can somehow reach N through a path that that doesn't contain 1247 // U then folding N would create a cycle. e.g. In the following 1248 // diagram, Root can reach N through X. If N is folded into into Root, then 1249 // X is both a predecessor and a successor of U. 1250 // 1251 // [N*] // 1252 // ^ ^ // 1253 // / \ // 1254 // [U*] [X]? // 1255 // ^ ^ // 1256 // \ / // 1257 // \ / // 1258 // [Root*] // 1259 // 1260 // * indicates nodes to be folded together. 1261 // 1262 // If Root produces a flag, then it gets (even more) interesting. Since it 1263 // will be "glued" together with its flag use in the scheduler, we need to 1264 // check if it might reach N. 1265 // 1266 // [N*] // 1267 // ^ ^ // 1268 // / \ // 1269 // [U*] [X]? // 1270 // ^ ^ // 1271 // \ \ // 1272 // \ | // 1273 // [Root*] | // 1274 // ^ | // 1275 // f | // 1276 // | / // 1277 // [Y] / // 1278 // ^ / // 1279 // f / // 1280 // | / // 1281 // [FU] // 1282 // 1283 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1284 // (call it Fold), then X is a predecessor of FU and a successor of 1285 // Fold. But since Fold and FU are flagged together, this will create 1286 // a cycle in the scheduling graph. 1287 1288 // If the node has flags, walk down the graph to the "lowest" node in the 1289 // flagged set. 1290 EVT VT = Root->getValueType(Root->getNumValues()-1); 1291 while (VT == MVT::Flag) { 1292 SDNode *FU = findFlagUse(Root); 1293 if (FU == NULL) 1294 break; 1295 Root = FU; 1296 VT = Root->getValueType(Root->getNumValues()-1); 1297 1298 // If our query node has a flag result with a use, we've walked up it. If 1299 // the user (which has already been selected) has a chain or indirectly uses 1300 // the chain, our WalkChainUsers predicate will not consider it. Because of 1301 // this, we cannot ignore chains in this predicate. 1302 IgnoreChains = false; 1303 } 1304 1305 1306 SmallPtrSet<SDNode*, 16> Visited; 1307 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1308} 1309 1310SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1311 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1312 SelectInlineAsmMemoryOperands(Ops); 1313 1314 std::vector<EVT> VTs; 1315 VTs.push_back(MVT::Other); 1316 VTs.push_back(MVT::Flag); 1317 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1318 VTs, &Ops[0], Ops.size()); 1319 New->setNodeId(-1); 1320 return New.getNode(); 1321} 1322 1323SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1324 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1325} 1326 1327/// GetVBR - decode a vbr encoding whose top bit is set. 1328ALWAYS_INLINE static uint64_t 1329GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1330 assert(Val >= 128 && "Not a VBR"); 1331 Val &= 127; // Remove first vbr bit. 1332 1333 unsigned Shift = 7; 1334 uint64_t NextBits; 1335 do { 1336 NextBits = MatcherTable[Idx++]; 1337 Val |= (NextBits&127) << Shift; 1338 Shift += 7; 1339 } while (NextBits & 128); 1340 1341 return Val; 1342} 1343 1344 1345/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1346/// interior flag and chain results to use the new flag and chain results. 1347void SelectionDAGISel:: 1348UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1349 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1350 SDValue InputFlag, 1351 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1352 bool isMorphNodeTo) { 1353 SmallVector<SDNode*, 4> NowDeadNodes; 1354 1355 ISelUpdater ISU(ISelPosition); 1356 1357 // Now that all the normal results are replaced, we replace the chain and 1358 // flag results if present. 1359 if (!ChainNodesMatched.empty()) { 1360 assert(InputChain.getNode() != 0 && 1361 "Matched input chains but didn't produce a chain"); 1362 // Loop over all of the nodes we matched that produced a chain result. 1363 // Replace all the chain results with the final chain we ended up with. 1364 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1365 SDNode *ChainNode = ChainNodesMatched[i]; 1366 1367 // If this node was already deleted, don't look at it. 1368 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1369 continue; 1370 1371 // Don't replace the results of the root node if we're doing a 1372 // MorphNodeTo. 1373 if (ChainNode == NodeToMatch && isMorphNodeTo) 1374 continue; 1375 1376 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1377 if (ChainVal.getValueType() == MVT::Flag) 1378 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1379 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1380 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1381 1382 // If the node became dead and we haven't already seen it, delete it. 1383 if (ChainNode->use_empty() && 1384 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1385 NowDeadNodes.push_back(ChainNode); 1386 } 1387 } 1388 1389 // If the result produces a flag, update any flag results in the matched 1390 // pattern with the flag result. 1391 if (InputFlag.getNode() != 0) { 1392 // Handle any interior nodes explicitly marked. 1393 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1394 SDNode *FRN = FlagResultNodesMatched[i]; 1395 1396 // If this node was already deleted, don't look at it. 1397 if (FRN->getOpcode() == ISD::DELETED_NODE) 1398 continue; 1399 1400 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1401 "Doesn't have a flag result"); 1402 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1403 InputFlag, &ISU); 1404 1405 // If the node became dead and we haven't already seen it, delete it. 1406 if (FRN->use_empty() && 1407 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1408 NowDeadNodes.push_back(FRN); 1409 } 1410 } 1411 1412 if (!NowDeadNodes.empty()) 1413 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1414 1415 DEBUG(errs() << "ISEL: Match complete!\n"); 1416} 1417 1418enum ChainResult { 1419 CR_Simple, 1420 CR_InducesCycle, 1421 CR_LeadsToInteriorNode 1422}; 1423 1424/// WalkChainUsers - Walk down the users of the specified chained node that is 1425/// part of the pattern we're matching, looking at all of the users we find. 1426/// This determines whether something is an interior node, whether we have a 1427/// non-pattern node in between two pattern nodes (which prevent folding because 1428/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1429/// between pattern nodes (in which case the TF becomes part of the pattern). 1430/// 1431/// The walk we do here is guaranteed to be small because we quickly get down to 1432/// already selected nodes "below" us. 1433static ChainResult 1434WalkChainUsers(SDNode *ChainedNode, 1435 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1436 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1437 ChainResult Result = CR_Simple; 1438 1439 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1440 E = ChainedNode->use_end(); UI != E; ++UI) { 1441 // Make sure the use is of the chain, not some other value we produce. 1442 if (UI.getUse().getValueType() != MVT::Other) continue; 1443 1444 SDNode *User = *UI; 1445 1446 // If we see an already-selected machine node, then we've gone beyond the 1447 // pattern that we're selecting down into the already selected chunk of the 1448 // DAG. 1449 if (User->isMachineOpcode() || 1450 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1451 continue; 1452 1453 if (User->getOpcode() == ISD::CopyToReg || 1454 User->getOpcode() == ISD::CopyFromReg || 1455 User->getOpcode() == ISD::INLINEASM || 1456 User->getOpcode() == ISD::EH_LABEL) { 1457 // If their node ID got reset to -1 then they've already been selected. 1458 // Treat them like a MachineOpcode. 1459 if (User->getNodeId() == -1) 1460 continue; 1461 } 1462 1463 // If we have a TokenFactor, we handle it specially. 1464 if (User->getOpcode() != ISD::TokenFactor) { 1465 // If the node isn't a token factor and isn't part of our pattern, then it 1466 // must be a random chained node in between two nodes we're selecting. 1467 // This happens when we have something like: 1468 // x = load ptr 1469 // call 1470 // y = x+4 1471 // store y -> ptr 1472 // Because we structurally match the load/store as a read/modify/write, 1473 // but the call is chained between them. We cannot fold in this case 1474 // because it would induce a cycle in the graph. 1475 if (!std::count(ChainedNodesInPattern.begin(), 1476 ChainedNodesInPattern.end(), User)) 1477 return CR_InducesCycle; 1478 1479 // Otherwise we found a node that is part of our pattern. For example in: 1480 // x = load ptr 1481 // y = x+4 1482 // store y -> ptr 1483 // This would happen when we're scanning down from the load and see the 1484 // store as a user. Record that there is a use of ChainedNode that is 1485 // part of the pattern and keep scanning uses. 1486 Result = CR_LeadsToInteriorNode; 1487 InteriorChainedNodes.push_back(User); 1488 continue; 1489 } 1490 1491 // If we found a TokenFactor, there are two cases to consider: first if the 1492 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1493 // uses of the TF are in our pattern) we just want to ignore it. Second, 1494 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1495 // [Load chain] 1496 // ^ 1497 // | 1498 // [Load] 1499 // ^ ^ 1500 // | \ DAG's like cheese 1501 // / \ do you? 1502 // / | 1503 // [TokenFactor] [Op] 1504 // ^ ^ 1505 // | | 1506 // \ / 1507 // \ / 1508 // [Store] 1509 // 1510 // In this case, the TokenFactor becomes part of our match and we rewrite it 1511 // as a new TokenFactor. 1512 // 1513 // To distinguish these two cases, do a recursive walk down the uses. 1514 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1515 case CR_Simple: 1516 // If the uses of the TokenFactor are just already-selected nodes, ignore 1517 // it, it is "below" our pattern. 1518 continue; 1519 case CR_InducesCycle: 1520 // If the uses of the TokenFactor lead to nodes that are not part of our 1521 // pattern that are not selected, folding would turn this into a cycle, 1522 // bail out now. 1523 return CR_InducesCycle; 1524 case CR_LeadsToInteriorNode: 1525 break; // Otherwise, keep processing. 1526 } 1527 1528 // Okay, we know we're in the interesting interior case. The TokenFactor 1529 // is now going to be considered part of the pattern so that we rewrite its 1530 // uses (it may have uses that are not part of the pattern) with the 1531 // ultimate chain result of the generated code. We will also add its chain 1532 // inputs as inputs to the ultimate TokenFactor we create. 1533 Result = CR_LeadsToInteriorNode; 1534 ChainedNodesInPattern.push_back(User); 1535 InteriorChainedNodes.push_back(User); 1536 continue; 1537 } 1538 1539 return Result; 1540} 1541 1542/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1543/// operation for when the pattern matched at least one node with a chains. The 1544/// input vector contains a list of all of the chained nodes that we match. We 1545/// must determine if this is a valid thing to cover (i.e. matching it won't 1546/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1547/// be used as the input node chain for the generated nodes. 1548static SDValue 1549HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1550 SelectionDAG *CurDAG) { 1551 // Walk all of the chained nodes we've matched, recursively scanning down the 1552 // users of the chain result. This adds any TokenFactor nodes that are caught 1553 // in between chained nodes to the chained and interior nodes list. 1554 SmallVector<SDNode*, 3> InteriorChainedNodes; 1555 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1556 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1557 InteriorChainedNodes) == CR_InducesCycle) 1558 return SDValue(); // Would induce a cycle. 1559 } 1560 1561 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1562 // that we are interested in. Form our input TokenFactor node. 1563 SmallVector<SDValue, 3> InputChains; 1564 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1565 // Add the input chain of this node to the InputChains list (which will be 1566 // the operands of the generated TokenFactor) if it's not an interior node. 1567 SDNode *N = ChainNodesMatched[i]; 1568 if (N->getOpcode() != ISD::TokenFactor) { 1569 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1570 continue; 1571 1572 // Otherwise, add the input chain. 1573 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1574 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1575 InputChains.push_back(InChain); 1576 continue; 1577 } 1578 1579 // If we have a token factor, we want to add all inputs of the token factor 1580 // that are not part of the pattern we're matching. 1581 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1582 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1583 N->getOperand(op).getNode())) 1584 InputChains.push_back(N->getOperand(op)); 1585 } 1586 } 1587 1588 SDValue Res; 1589 if (InputChains.size() == 1) 1590 return InputChains[0]; 1591 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1592 MVT::Other, &InputChains[0], InputChains.size()); 1593} 1594 1595/// MorphNode - Handle morphing a node in place for the selector. 1596SDNode *SelectionDAGISel:: 1597MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1598 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1599 // It is possible we're using MorphNodeTo to replace a node with no 1600 // normal results with one that has a normal result (or we could be 1601 // adding a chain) and the input could have flags and chains as well. 1602 // In this case we need to shift the operands down. 1603 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1604 // than the old isel though. 1605 int OldFlagResultNo = -1, OldChainResultNo = -1; 1606 1607 unsigned NTMNumResults = Node->getNumValues(); 1608 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1609 OldFlagResultNo = NTMNumResults-1; 1610 if (NTMNumResults != 1 && 1611 Node->getValueType(NTMNumResults-2) == MVT::Other) 1612 OldChainResultNo = NTMNumResults-2; 1613 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1614 OldChainResultNo = NTMNumResults-1; 1615 1616 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1617 // that this deletes operands of the old node that become dead. 1618 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1619 1620 // MorphNodeTo can operate in two ways: if an existing node with the 1621 // specified operands exists, it can just return it. Otherwise, it 1622 // updates the node in place to have the requested operands. 1623 if (Res == Node) { 1624 // If we updated the node in place, reset the node ID. To the isel, 1625 // this should be just like a newly allocated machine node. 1626 Res->setNodeId(-1); 1627 } 1628 1629 unsigned ResNumResults = Res->getNumValues(); 1630 // Move the flag if needed. 1631 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1632 (unsigned)OldFlagResultNo != ResNumResults-1) 1633 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1634 SDValue(Res, ResNumResults-1)); 1635 1636 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1637 --ResNumResults; 1638 1639 // Move the chain reference if needed. 1640 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1641 (unsigned)OldChainResultNo != ResNumResults-1) 1642 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1643 SDValue(Res, ResNumResults-1)); 1644 1645 // Otherwise, no replacement happened because the node already exists. Replace 1646 // Uses of the old node with the new one. 1647 if (Res != Node) 1648 CurDAG->ReplaceAllUsesWith(Node, Res); 1649 1650 return Res; 1651} 1652 1653/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1654ALWAYS_INLINE static bool 1655CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1656 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1657 // Accept if it is exactly the same as a previously recorded node. 1658 unsigned RecNo = MatcherTable[MatcherIndex++]; 1659 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1660 return N == RecordedNodes[RecNo]; 1661} 1662 1663/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1664ALWAYS_INLINE static bool 1665CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1666 SelectionDAGISel &SDISel) { 1667 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1668} 1669 1670/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1671ALWAYS_INLINE static bool 1672CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1673 SelectionDAGISel &SDISel, SDNode *N) { 1674 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1675} 1676 1677ALWAYS_INLINE static bool 1678CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1679 SDNode *N) { 1680 uint16_t Opc = MatcherTable[MatcherIndex++]; 1681 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1682 return N->getOpcode() == Opc; 1683} 1684 1685ALWAYS_INLINE static bool 1686CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1687 SDValue N, const TargetLowering &TLI) { 1688 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1689 if (N.getValueType() == VT) return true; 1690 1691 // Handle the case when VT is iPTR. 1692 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1693} 1694 1695ALWAYS_INLINE static bool 1696CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1697 SDValue N, const TargetLowering &TLI, 1698 unsigned ChildNo) { 1699 if (ChildNo >= N.getNumOperands()) 1700 return false; // Match fails if out of range child #. 1701 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1702} 1703 1704 1705ALWAYS_INLINE static bool 1706CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1707 SDValue N) { 1708 return cast<CondCodeSDNode>(N)->get() == 1709 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1710} 1711 1712ALWAYS_INLINE static bool 1713CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1714 SDValue N, const TargetLowering &TLI) { 1715 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1716 if (cast<VTSDNode>(N)->getVT() == VT) 1717 return true; 1718 1719 // Handle the case when VT is iPTR. 1720 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1721} 1722 1723ALWAYS_INLINE static bool 1724CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1725 SDValue N) { 1726 int64_t Val = MatcherTable[MatcherIndex++]; 1727 if (Val & 128) 1728 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1729 1730 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1731 return C != 0 && C->getSExtValue() == Val; 1732} 1733 1734ALWAYS_INLINE static bool 1735CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1736 SDValue N, SelectionDAGISel &SDISel) { 1737 int64_t Val = MatcherTable[MatcherIndex++]; 1738 if (Val & 128) 1739 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1740 1741 if (N->getOpcode() != ISD::AND) return false; 1742 1743 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1744 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1745} 1746 1747ALWAYS_INLINE static bool 1748CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1749 SDValue N, SelectionDAGISel &SDISel) { 1750 int64_t Val = MatcherTable[MatcherIndex++]; 1751 if (Val & 128) 1752 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1753 1754 if (N->getOpcode() != ISD::OR) return false; 1755 1756 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1757 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1758} 1759 1760/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1761/// scope, evaluate the current node. If the current predicate is known to 1762/// fail, set Result=true and return anything. If the current predicate is 1763/// known to pass, set Result=false and return the MatcherIndex to continue 1764/// with. If the current predicate is unknown, set Result=false and return the 1765/// MatcherIndex to continue with. 1766static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1767 unsigned Index, SDValue N, 1768 bool &Result, SelectionDAGISel &SDISel, 1769 SmallVectorImpl<SDValue> &RecordedNodes){ 1770 switch (Table[Index++]) { 1771 default: 1772 Result = false; 1773 return Index-1; // Could not evaluate this predicate. 1774 case SelectionDAGISel::OPC_CheckSame: 1775 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1776 return Index; 1777 case SelectionDAGISel::OPC_CheckPatternPredicate: 1778 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1779 return Index; 1780 case SelectionDAGISel::OPC_CheckPredicate: 1781 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1782 return Index; 1783 case SelectionDAGISel::OPC_CheckOpcode: 1784 Result = !::CheckOpcode(Table, Index, N.getNode()); 1785 return Index; 1786 case SelectionDAGISel::OPC_CheckType: 1787 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1788 return Index; 1789 case SelectionDAGISel::OPC_CheckChild0Type: 1790 case SelectionDAGISel::OPC_CheckChild1Type: 1791 case SelectionDAGISel::OPC_CheckChild2Type: 1792 case SelectionDAGISel::OPC_CheckChild3Type: 1793 case SelectionDAGISel::OPC_CheckChild4Type: 1794 case SelectionDAGISel::OPC_CheckChild5Type: 1795 case SelectionDAGISel::OPC_CheckChild6Type: 1796 case SelectionDAGISel::OPC_CheckChild7Type: 1797 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1798 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1799 return Index; 1800 case SelectionDAGISel::OPC_CheckCondCode: 1801 Result = !::CheckCondCode(Table, Index, N); 1802 return Index; 1803 case SelectionDAGISel::OPC_CheckValueType: 1804 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1805 return Index; 1806 case SelectionDAGISel::OPC_CheckInteger: 1807 Result = !::CheckInteger(Table, Index, N); 1808 return Index; 1809 case SelectionDAGISel::OPC_CheckAndImm: 1810 Result = !::CheckAndImm(Table, Index, N, SDISel); 1811 return Index; 1812 case SelectionDAGISel::OPC_CheckOrImm: 1813 Result = !::CheckOrImm(Table, Index, N, SDISel); 1814 return Index; 1815 } 1816} 1817 1818namespace { 1819 1820struct MatchScope { 1821 /// FailIndex - If this match fails, this is the index to continue with. 1822 unsigned FailIndex; 1823 1824 /// NodeStack - The node stack when the scope was formed. 1825 SmallVector<SDValue, 4> NodeStack; 1826 1827 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1828 unsigned NumRecordedNodes; 1829 1830 /// NumMatchedMemRefs - The number of matched memref entries. 1831 unsigned NumMatchedMemRefs; 1832 1833 /// InputChain/InputFlag - The current chain/flag 1834 SDValue InputChain, InputFlag; 1835 1836 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1837 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1838}; 1839 1840} 1841 1842SDNode *SelectionDAGISel:: 1843SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1844 unsigned TableSize) { 1845 // FIXME: Should these even be selected? Handle these cases in the caller? 1846 switch (NodeToMatch->getOpcode()) { 1847 default: 1848 break; 1849 case ISD::EntryToken: // These nodes remain the same. 1850 case ISD::BasicBlock: 1851 case ISD::Register: 1852 //case ISD::VALUETYPE: 1853 //case ISD::CONDCODE: 1854 case ISD::HANDLENODE: 1855 case ISD::MDNODE_SDNODE: 1856 case ISD::TargetConstant: 1857 case ISD::TargetConstantFP: 1858 case ISD::TargetConstantPool: 1859 case ISD::TargetFrameIndex: 1860 case ISD::TargetExternalSymbol: 1861 case ISD::TargetBlockAddress: 1862 case ISD::TargetJumpTable: 1863 case ISD::TargetGlobalTLSAddress: 1864 case ISD::TargetGlobalAddress: 1865 case ISD::TokenFactor: 1866 case ISD::CopyFromReg: 1867 case ISD::CopyToReg: 1868 case ISD::EH_LABEL: 1869 NodeToMatch->setNodeId(-1); // Mark selected. 1870 return 0; 1871 case ISD::AssertSext: 1872 case ISD::AssertZext: 1873 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1874 NodeToMatch->getOperand(0)); 1875 return 0; 1876 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1877 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1878 } 1879 1880 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1881 1882 // Set up the node stack with NodeToMatch as the only node on the stack. 1883 SmallVector<SDValue, 8> NodeStack; 1884 SDValue N = SDValue(NodeToMatch, 0); 1885 NodeStack.push_back(N); 1886 1887 // MatchScopes - Scopes used when matching, if a match failure happens, this 1888 // indicates where to continue checking. 1889 SmallVector<MatchScope, 8> MatchScopes; 1890 1891 // RecordedNodes - This is the set of nodes that have been recorded by the 1892 // state machine. 1893 SmallVector<SDValue, 8> RecordedNodes; 1894 1895 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1896 // pattern. 1897 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1898 1899 // These are the current input chain and flag for use when generating nodes. 1900 // Various Emit operations change these. For example, emitting a copytoreg 1901 // uses and updates these. 1902 SDValue InputChain, InputFlag; 1903 1904 // ChainNodesMatched - If a pattern matches nodes that have input/output 1905 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1906 // which ones they are. The result is captured into this list so that we can 1907 // update the chain results when the pattern is complete. 1908 SmallVector<SDNode*, 3> ChainNodesMatched; 1909 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1910 1911 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1912 NodeToMatch->dump(CurDAG); 1913 errs() << '\n'); 1914 1915 // Determine where to start the interpreter. Normally we start at opcode #0, 1916 // but if the state machine starts with an OPC_SwitchOpcode, then we 1917 // accelerate the first lookup (which is guaranteed to be hot) with the 1918 // OpcodeOffset table. 1919 unsigned MatcherIndex = 0; 1920 1921 if (!OpcodeOffset.empty()) { 1922 // Already computed the OpcodeOffset table, just index into it. 1923 if (N.getOpcode() < OpcodeOffset.size()) 1924 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1925 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1926 1927 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1928 // Otherwise, the table isn't computed, but the state machine does start 1929 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1930 // is the first time we're selecting an instruction. 1931 unsigned Idx = 1; 1932 while (1) { 1933 // Get the size of this case. 1934 unsigned CaseSize = MatcherTable[Idx++]; 1935 if (CaseSize & 128) 1936 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1937 if (CaseSize == 0) break; 1938 1939 // Get the opcode, add the index to the table. 1940 uint16_t Opc = MatcherTable[Idx++]; 1941 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1942 if (Opc >= OpcodeOffset.size()) 1943 OpcodeOffset.resize((Opc+1)*2); 1944 OpcodeOffset[Opc] = Idx; 1945 Idx += CaseSize; 1946 } 1947 1948 // Okay, do the lookup for the first opcode. 1949 if (N.getOpcode() < OpcodeOffset.size()) 1950 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1951 } 1952 1953 while (1) { 1954 assert(MatcherIndex < TableSize && "Invalid index"); 1955#ifndef NDEBUG 1956 unsigned CurrentOpcodeIndex = MatcherIndex; 1957#endif 1958 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1959 switch (Opcode) { 1960 case OPC_Scope: { 1961 // Okay, the semantics of this operation are that we should push a scope 1962 // then evaluate the first child. However, pushing a scope only to have 1963 // the first check fail (which then pops it) is inefficient. If we can 1964 // determine immediately that the first check (or first several) will 1965 // immediately fail, don't even bother pushing a scope for them. 1966 unsigned FailIndex; 1967 1968 while (1) { 1969 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1970 if (NumToSkip & 128) 1971 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1972 // Found the end of the scope with no match. 1973 if (NumToSkip == 0) { 1974 FailIndex = 0; 1975 break; 1976 } 1977 1978 FailIndex = MatcherIndex+NumToSkip; 1979 1980 unsigned MatcherIndexOfPredicate = MatcherIndex; 1981 (void)MatcherIndexOfPredicate; // silence warning. 1982 1983 // If we can't evaluate this predicate without pushing a scope (e.g. if 1984 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1985 // push the scope and evaluate the full predicate chain. 1986 bool Result; 1987 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1988 Result, *this, RecordedNodes); 1989 if (!Result) 1990 break; 1991 1992 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1993 << "index " << MatcherIndexOfPredicate 1994 << ", continuing at " << FailIndex << "\n"); 1995 ++NumDAGIselRetries; 1996 1997 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1998 // move to the next case. 1999 MatcherIndex = FailIndex; 2000 } 2001 2002 // If the whole scope failed to match, bail. 2003 if (FailIndex == 0) break; 2004 2005 // Push a MatchScope which indicates where to go if the first child fails 2006 // to match. 2007 MatchScope NewEntry; 2008 NewEntry.FailIndex = FailIndex; 2009 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2010 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2011 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2012 NewEntry.InputChain = InputChain; 2013 NewEntry.InputFlag = InputFlag; 2014 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2015 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2016 MatchScopes.push_back(NewEntry); 2017 continue; 2018 } 2019 case OPC_RecordNode: 2020 // Remember this node, it may end up being an operand in the pattern. 2021 RecordedNodes.push_back(N); 2022 continue; 2023 2024 case OPC_RecordChild0: case OPC_RecordChild1: 2025 case OPC_RecordChild2: case OPC_RecordChild3: 2026 case OPC_RecordChild4: case OPC_RecordChild5: 2027 case OPC_RecordChild6: case OPC_RecordChild7: { 2028 unsigned ChildNo = Opcode-OPC_RecordChild0; 2029 if (ChildNo >= N.getNumOperands()) 2030 break; // Match fails if out of range child #. 2031 2032 RecordedNodes.push_back(N->getOperand(ChildNo)); 2033 continue; 2034 } 2035 case OPC_RecordMemRef: 2036 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2037 continue; 2038 2039 case OPC_CaptureFlagInput: 2040 // If the current node has an input flag, capture it in InputFlag. 2041 if (N->getNumOperands() != 0 && 2042 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2043 InputFlag = N->getOperand(N->getNumOperands()-1); 2044 continue; 2045 2046 case OPC_MoveChild: { 2047 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2048 if (ChildNo >= N.getNumOperands()) 2049 break; // Match fails if out of range child #. 2050 N = N.getOperand(ChildNo); 2051 NodeStack.push_back(N); 2052 continue; 2053 } 2054 2055 case OPC_MoveParent: 2056 // Pop the current node off the NodeStack. 2057 NodeStack.pop_back(); 2058 assert(!NodeStack.empty() && "Node stack imbalance!"); 2059 N = NodeStack.back(); 2060 continue; 2061 2062 case OPC_CheckSame: 2063 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2064 continue; 2065 case OPC_CheckPatternPredicate: 2066 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2067 continue; 2068 case OPC_CheckPredicate: 2069 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2070 N.getNode())) 2071 break; 2072 continue; 2073 case OPC_CheckComplexPat: { 2074 unsigned CPNum = MatcherTable[MatcherIndex++]; 2075 unsigned RecNo = MatcherTable[MatcherIndex++]; 2076 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2077 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2078 RecordedNodes)) 2079 break; 2080 continue; 2081 } 2082 case OPC_CheckOpcode: 2083 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2084 continue; 2085 2086 case OPC_CheckType: 2087 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2088 continue; 2089 2090 case OPC_SwitchOpcode: { 2091 unsigned CurNodeOpcode = N.getOpcode(); 2092 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2093 unsigned CaseSize; 2094 while (1) { 2095 // Get the size of this case. 2096 CaseSize = MatcherTable[MatcherIndex++]; 2097 if (CaseSize & 128) 2098 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2099 if (CaseSize == 0) break; 2100 2101 uint16_t Opc = MatcherTable[MatcherIndex++]; 2102 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2103 2104 // If the opcode matches, then we will execute this case. 2105 if (CurNodeOpcode == Opc) 2106 break; 2107 2108 // Otherwise, skip over this case. 2109 MatcherIndex += CaseSize; 2110 } 2111 2112 // If no cases matched, bail out. 2113 if (CaseSize == 0) break; 2114 2115 // Otherwise, execute the case we found. 2116 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2117 << " to " << MatcherIndex << "\n"); 2118 continue; 2119 } 2120 2121 case OPC_SwitchType: { 2122 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2123 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2124 unsigned CaseSize; 2125 while (1) { 2126 // Get the size of this case. 2127 CaseSize = MatcherTable[MatcherIndex++]; 2128 if (CaseSize & 128) 2129 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2130 if (CaseSize == 0) break; 2131 2132 MVT::SimpleValueType CaseVT = 2133 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2134 if (CaseVT == MVT::iPTR) 2135 CaseVT = TLI.getPointerTy().SimpleTy; 2136 2137 // If the VT matches, then we will execute this case. 2138 if (CurNodeVT == CaseVT) 2139 break; 2140 2141 // Otherwise, skip over this case. 2142 MatcherIndex += CaseSize; 2143 } 2144 2145 // If no cases matched, bail out. 2146 if (CaseSize == 0) break; 2147 2148 // Otherwise, execute the case we found. 2149 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2150 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2151 continue; 2152 } 2153 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2154 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2155 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2156 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2157 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2158 Opcode-OPC_CheckChild0Type)) 2159 break; 2160 continue; 2161 case OPC_CheckCondCode: 2162 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2163 continue; 2164 case OPC_CheckValueType: 2165 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2166 continue; 2167 case OPC_CheckInteger: 2168 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2169 continue; 2170 case OPC_CheckAndImm: 2171 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2172 continue; 2173 case OPC_CheckOrImm: 2174 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2175 continue; 2176 2177 case OPC_CheckFoldableChainNode: { 2178 assert(NodeStack.size() != 1 && "No parent node"); 2179 // Verify that all intermediate nodes between the root and this one have 2180 // a single use. 2181 bool HasMultipleUses = false; 2182 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2183 if (!NodeStack[i].hasOneUse()) { 2184 HasMultipleUses = true; 2185 break; 2186 } 2187 if (HasMultipleUses) break; 2188 2189 // Check to see that the target thinks this is profitable to fold and that 2190 // we can fold it without inducing cycles in the graph. 2191 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2192 NodeToMatch) || 2193 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2194 NodeToMatch, OptLevel, 2195 true/*We validate our own chains*/)) 2196 break; 2197 2198 continue; 2199 } 2200 case OPC_EmitInteger: { 2201 MVT::SimpleValueType VT = 2202 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2203 int64_t Val = MatcherTable[MatcherIndex++]; 2204 if (Val & 128) 2205 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2206 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2207 continue; 2208 } 2209 case OPC_EmitRegister: { 2210 MVT::SimpleValueType VT = 2211 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2212 unsigned RegNo = MatcherTable[MatcherIndex++]; 2213 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2214 continue; 2215 } 2216 2217 case OPC_EmitConvertToTarget: { 2218 // Convert from IMM/FPIMM to target version. 2219 unsigned RecNo = MatcherTable[MatcherIndex++]; 2220 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2221 SDValue Imm = RecordedNodes[RecNo]; 2222 2223 if (Imm->getOpcode() == ISD::Constant) { 2224 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2225 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2226 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2227 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2228 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2229 } 2230 2231 RecordedNodes.push_back(Imm); 2232 continue; 2233 } 2234 2235 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2236 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2237 // These are space-optimized forms of OPC_EmitMergeInputChains. 2238 assert(InputChain.getNode() == 0 && 2239 "EmitMergeInputChains should be the first chain producing node"); 2240 assert(ChainNodesMatched.empty() && 2241 "Should only have one EmitMergeInputChains per match"); 2242 2243 // Read all of the chained nodes. 2244 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2245 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2246 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2247 2248 // FIXME: What if other value results of the node have uses not matched 2249 // by this pattern? 2250 if (ChainNodesMatched.back() != NodeToMatch && 2251 !RecordedNodes[RecNo].hasOneUse()) { 2252 ChainNodesMatched.clear(); 2253 break; 2254 } 2255 2256 // Merge the input chains if they are not intra-pattern references. 2257 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2258 2259 if (InputChain.getNode() == 0) 2260 break; // Failed to merge. 2261 continue; 2262 } 2263 2264 case OPC_EmitMergeInputChains: { 2265 assert(InputChain.getNode() == 0 && 2266 "EmitMergeInputChains should be the first chain producing node"); 2267 // This node gets a list of nodes we matched in the input that have 2268 // chains. We want to token factor all of the input chains to these nodes 2269 // together. However, if any of the input chains is actually one of the 2270 // nodes matched in this pattern, then we have an intra-match reference. 2271 // Ignore these because the newly token factored chain should not refer to 2272 // the old nodes. 2273 unsigned NumChains = MatcherTable[MatcherIndex++]; 2274 assert(NumChains != 0 && "Can't TF zero chains"); 2275 2276 assert(ChainNodesMatched.empty() && 2277 "Should only have one EmitMergeInputChains per match"); 2278 2279 // Read all of the chained nodes. 2280 for (unsigned i = 0; i != NumChains; ++i) { 2281 unsigned RecNo = MatcherTable[MatcherIndex++]; 2282 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2283 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2284 2285 // FIXME: What if other value results of the node have uses not matched 2286 // by this pattern? 2287 if (ChainNodesMatched.back() != NodeToMatch && 2288 !RecordedNodes[RecNo].hasOneUse()) { 2289 ChainNodesMatched.clear(); 2290 break; 2291 } 2292 } 2293 2294 // If the inner loop broke out, the match fails. 2295 if (ChainNodesMatched.empty()) 2296 break; 2297 2298 // Merge the input chains if they are not intra-pattern references. 2299 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2300 2301 if (InputChain.getNode() == 0) 2302 break; // Failed to merge. 2303 2304 continue; 2305 } 2306 2307 case OPC_EmitCopyToReg: { 2308 unsigned RecNo = MatcherTable[MatcherIndex++]; 2309 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2310 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2311 2312 if (InputChain.getNode() == 0) 2313 InputChain = CurDAG->getEntryNode(); 2314 2315 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2316 DestPhysReg, RecordedNodes[RecNo], 2317 InputFlag); 2318 2319 InputFlag = InputChain.getValue(1); 2320 continue; 2321 } 2322 2323 case OPC_EmitNodeXForm: { 2324 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2325 unsigned RecNo = MatcherTable[MatcherIndex++]; 2326 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2327 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2328 continue; 2329 } 2330 2331 case OPC_EmitNode: 2332 case OPC_MorphNodeTo: { 2333 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2334 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2335 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2336 // Get the result VT list. 2337 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2338 SmallVector<EVT, 4> VTs; 2339 for (unsigned i = 0; i != NumVTs; ++i) { 2340 MVT::SimpleValueType VT = 2341 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2342 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2343 VTs.push_back(VT); 2344 } 2345 2346 if (EmitNodeInfo & OPFL_Chain) 2347 VTs.push_back(MVT::Other); 2348 if (EmitNodeInfo & OPFL_FlagOutput) 2349 VTs.push_back(MVT::Flag); 2350 2351 // This is hot code, so optimize the two most common cases of 1 and 2 2352 // results. 2353 SDVTList VTList; 2354 if (VTs.size() == 1) 2355 VTList = CurDAG->getVTList(VTs[0]); 2356 else if (VTs.size() == 2) 2357 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2358 else 2359 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2360 2361 // Get the operand list. 2362 unsigned NumOps = MatcherTable[MatcherIndex++]; 2363 SmallVector<SDValue, 8> Ops; 2364 for (unsigned i = 0; i != NumOps; ++i) { 2365 unsigned RecNo = MatcherTable[MatcherIndex++]; 2366 if (RecNo & 128) 2367 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2368 2369 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2370 Ops.push_back(RecordedNodes[RecNo]); 2371 } 2372 2373 // If there are variadic operands to add, handle them now. 2374 if (EmitNodeInfo & OPFL_VariadicInfo) { 2375 // Determine the start index to copy from. 2376 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2377 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2378 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2379 "Invalid variadic node"); 2380 // Copy all of the variadic operands, not including a potential flag 2381 // input. 2382 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2383 i != e; ++i) { 2384 SDValue V = NodeToMatch->getOperand(i); 2385 if (V.getValueType() == MVT::Flag) break; 2386 Ops.push_back(V); 2387 } 2388 } 2389 2390 // If this has chain/flag inputs, add them. 2391 if (EmitNodeInfo & OPFL_Chain) 2392 Ops.push_back(InputChain); 2393 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2394 Ops.push_back(InputFlag); 2395 2396 // Create the node. 2397 SDNode *Res = 0; 2398 if (Opcode != OPC_MorphNodeTo) { 2399 // If this is a normal EmitNode command, just create the new node and 2400 // add the results to the RecordedNodes list. 2401 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2402 VTList, Ops.data(), Ops.size()); 2403 2404 // Add all the non-flag/non-chain results to the RecordedNodes list. 2405 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2406 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2407 RecordedNodes.push_back(SDValue(Res, i)); 2408 } 2409 2410 } else { 2411 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2412 EmitNodeInfo); 2413 } 2414 2415 // If the node had chain/flag results, update our notion of the current 2416 // chain and flag. 2417 if (EmitNodeInfo & OPFL_FlagOutput) { 2418 InputFlag = SDValue(Res, VTs.size()-1); 2419 if (EmitNodeInfo & OPFL_Chain) 2420 InputChain = SDValue(Res, VTs.size()-2); 2421 } else if (EmitNodeInfo & OPFL_Chain) 2422 InputChain = SDValue(Res, VTs.size()-1); 2423 2424 // If the OPFL_MemRefs flag is set on this node, slap all of the 2425 // accumulated memrefs onto it. 2426 // 2427 // FIXME: This is vastly incorrect for patterns with multiple outputs 2428 // instructions that access memory and for ComplexPatterns that match 2429 // loads. 2430 if (EmitNodeInfo & OPFL_MemRefs) { 2431 MachineSDNode::mmo_iterator MemRefs = 2432 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2433 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2434 cast<MachineSDNode>(Res) 2435 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2436 } 2437 2438 DEBUG(errs() << " " 2439 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2440 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2441 2442 // If this was a MorphNodeTo then we're completely done! 2443 if (Opcode == OPC_MorphNodeTo) { 2444 // Update chain and flag uses. 2445 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2446 InputFlag, FlagResultNodesMatched, true); 2447 return Res; 2448 } 2449 2450 continue; 2451 } 2452 2453 case OPC_MarkFlagResults: { 2454 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2455 2456 // Read and remember all the flag-result nodes. 2457 for (unsigned i = 0; i != NumNodes; ++i) { 2458 unsigned RecNo = MatcherTable[MatcherIndex++]; 2459 if (RecNo & 128) 2460 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2461 2462 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2463 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2464 } 2465 continue; 2466 } 2467 2468 case OPC_CompleteMatch: { 2469 // The match has been completed, and any new nodes (if any) have been 2470 // created. Patch up references to the matched dag to use the newly 2471 // created nodes. 2472 unsigned NumResults = MatcherTable[MatcherIndex++]; 2473 2474 for (unsigned i = 0; i != NumResults; ++i) { 2475 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2476 if (ResSlot & 128) 2477 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2478 2479 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2480 SDValue Res = RecordedNodes[ResSlot]; 2481 2482 assert(i < NodeToMatch->getNumValues() && 2483 NodeToMatch->getValueType(i) != MVT::Other && 2484 NodeToMatch->getValueType(i) != MVT::Flag && 2485 "Invalid number of results to complete!"); 2486 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2487 NodeToMatch->getValueType(i) == MVT::iPTR || 2488 Res.getValueType() == MVT::iPTR || 2489 NodeToMatch->getValueType(i).getSizeInBits() == 2490 Res.getValueType().getSizeInBits()) && 2491 "invalid replacement"); 2492 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2493 } 2494 2495 // If the root node defines a flag, add it to the flag nodes to update 2496 // list. 2497 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2498 FlagResultNodesMatched.push_back(NodeToMatch); 2499 2500 // Update chain and flag uses. 2501 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2502 InputFlag, FlagResultNodesMatched, false); 2503 2504 assert(NodeToMatch->use_empty() && 2505 "Didn't replace all uses of the node?"); 2506 2507 // FIXME: We just return here, which interacts correctly with SelectRoot 2508 // above. We should fix this to not return an SDNode* anymore. 2509 return 0; 2510 } 2511 } 2512 2513 // If the code reached this point, then the match failed. See if there is 2514 // another child to try in the current 'Scope', otherwise pop it until we 2515 // find a case to check. 2516 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2517 ++NumDAGIselRetries; 2518 while (1) { 2519 if (MatchScopes.empty()) { 2520 CannotYetSelect(NodeToMatch); 2521 return 0; 2522 } 2523 2524 // Restore the interpreter state back to the point where the scope was 2525 // formed. 2526 MatchScope &LastScope = MatchScopes.back(); 2527 RecordedNodes.resize(LastScope.NumRecordedNodes); 2528 NodeStack.clear(); 2529 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2530 N = NodeStack.back(); 2531 2532 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2533 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2534 MatcherIndex = LastScope.FailIndex; 2535 2536 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2537 2538 InputChain = LastScope.InputChain; 2539 InputFlag = LastScope.InputFlag; 2540 if (!LastScope.HasChainNodesMatched) 2541 ChainNodesMatched.clear(); 2542 if (!LastScope.HasFlagResultNodesMatched) 2543 FlagResultNodesMatched.clear(); 2544 2545 // Check to see what the offset is at the new MatcherIndex. If it is zero 2546 // we have reached the end of this scope, otherwise we have another child 2547 // in the current scope to try. 2548 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2549 if (NumToSkip & 128) 2550 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2551 2552 // If we have another child in this scope to match, update FailIndex and 2553 // try it. 2554 if (NumToSkip != 0) { 2555 LastScope.FailIndex = MatcherIndex+NumToSkip; 2556 break; 2557 } 2558 2559 // End of this scope, pop it and try the next child in the containing 2560 // scope. 2561 MatchScopes.pop_back(); 2562 } 2563 } 2564} 2565 2566 2567 2568void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2569 std::string msg; 2570 raw_string_ostream Msg(msg); 2571 Msg << "Cannot yet select: "; 2572 2573 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2574 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2575 N->getOpcode() != ISD::INTRINSIC_VOID) { 2576 N->printrFull(Msg, CurDAG); 2577 } else { 2578 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2579 unsigned iid = 2580 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2581 if (iid < Intrinsic::num_intrinsics) 2582 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2583 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2584 Msg << "target intrinsic %" << TII->getName(iid); 2585 else 2586 Msg << "unknown intrinsic #" << iid; 2587 } 2588 report_fatal_error(Msg.str()); 2589} 2590 2591char SelectionDAGISel::ID = 0; 2592