SelectionDAGISel.cpp revision b9fccc41933648647e3f7669612c683eb5de0d58
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "llvm/Constants.h" 17#include "llvm/DerivedTypes.h" 18#include "llvm/Function.h" 19#include "llvm/Instructions.h" 20#include "llvm/Intrinsics.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SSARegMap.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetFrameInfo.h" 28#include "llvm/Target/TargetInstrInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include <map> 34#include <iostream> 35using namespace llvm; 36 37#ifndef _NDEBUG 38static cl::opt<bool> 39ViewDAGs("view-isel-dags", cl::Hidden, 40 cl::desc("Pop up a window to show isel dags as they are selected")); 41#else 42static const bool ViewDAGS = 0; 43#endif 44 45namespace llvm { 46 //===--------------------------------------------------------------------===// 47 /// FunctionLoweringInfo - This contains information that is global to a 48 /// function that is used when lowering a region of the function. 49 class FunctionLoweringInfo { 50 public: 51 TargetLowering &TLI; 52 Function &Fn; 53 MachineFunction &MF; 54 SSARegMap *RegMap; 55 56 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 57 58 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 59 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 60 61 /// ValueMap - Since we emit code for the function a basic block at a time, 62 /// we must remember which virtual registers hold the values for 63 /// cross-basic-block values. 64 std::map<const Value*, unsigned> ValueMap; 65 66 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 67 /// the entry block. This allows the allocas to be efficiently referenced 68 /// anywhere in the function. 69 std::map<const AllocaInst*, int> StaticAllocaMap; 70 71 /// BlockLocalArguments - If any arguments are only used in a single basic 72 /// block, and if the target can access the arguments without side-effects, 73 /// avoid emitting CopyToReg nodes for those arguments. This map keeps 74 /// track of which arguments are local to each BB. 75 std::multimap<BasicBlock*, std::pair<Argument*, 76 unsigned> > BlockLocalArguments; 77 78 79 unsigned MakeReg(MVT::ValueType VT) { 80 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 81 } 82 83 unsigned CreateRegForValue(const Value *V) { 84 MVT::ValueType VT = TLI.getValueType(V->getType()); 85 // The common case is that we will only create one register for this 86 // value. If we have that case, create and return the virtual register. 87 unsigned NV = TLI.getNumElements(VT); 88 if (NV == 1) { 89 // If we are promoting this value, pick the next largest supported type. 90 return MakeReg(TLI.getTypeToTransformTo(VT)); 91 } 92 93 // If this value is represented with multiple target registers, make sure 94 // to create enough consequtive registers of the right (smaller) type. 95 unsigned NT = VT-1; // Find the type to use. 96 while (TLI.getNumElements((MVT::ValueType)NT) != 1) 97 --NT; 98 99 unsigned R = MakeReg((MVT::ValueType)NT); 100 for (unsigned i = 1; i != NV; ++i) 101 MakeReg((MVT::ValueType)NT); 102 return R; 103 } 104 105 unsigned InitializeRegForValue(const Value *V) { 106 unsigned &R = ValueMap[V]; 107 assert(R == 0 && "Already initialized this value register!"); 108 return R = CreateRegForValue(V); 109 } 110 }; 111} 112 113/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 114/// PHI nodes or outside of the basic block that defines it. 115static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 116 if (isa<PHINode>(I)) return true; 117 BasicBlock *BB = I->getParent(); 118 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 119 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI)) 120 return true; 121 return false; 122} 123 124FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 125 Function &fn, MachineFunction &mf) 126 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 127 128 // Initialize the mapping of values to registers. This is only set up for 129 // instruction values that are used outside of the block that defines 130 // them. 131 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); AI != E; ++AI) 132 InitializeRegForValue(AI); 133 134 Function::iterator BB = Fn.begin(), E = Fn.end(); 135 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 136 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 137 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) { 138 const Type *Ty = AI->getAllocatedType(); 139 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty); 140 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 141 TySize *= CUI->getValue(); // Get total allocated size. 142 StaticAllocaMap[AI] = 143 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 144 } 145 146 for (; BB != E; ++BB) 147 for (BasicBlock::iterator I = BB->begin(), e = BB->end(); I != e; ++I) 148 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 149 if (!isa<AllocaInst>(I) || 150 !StaticAllocaMap.count(cast<AllocaInst>(I))) 151 InitializeRegForValue(I); 152 153 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 154 // also creates the initial PHI MachineInstrs, though none of the input 155 // operands are populated. 156 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 157 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 158 MBBMap[BB] = MBB; 159 MF.getBasicBlockList().push_back(MBB); 160 161 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 162 // appropriate. 163 PHINode *PN; 164 for (BasicBlock::iterator I = BB->begin(); 165 (PN = dyn_cast<PHINode>(I)); ++I) 166 if (!PN->use_empty()) { 167 unsigned NumElements = 168 TLI.getNumElements(TLI.getValueType(PN->getType())); 169 unsigned PHIReg = ValueMap[PN]; 170 assert(PHIReg &&"PHI node does not have an assigned virtual register!"); 171 for (unsigned i = 0; i != NumElements; ++i) 172 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i); 173 } 174 } 175} 176 177 178 179//===----------------------------------------------------------------------===// 180/// SelectionDAGLowering - This is the common target-independent lowering 181/// implementation that is parameterized by a TargetLowering object. 182/// Also, targets can overload any lowering method. 183/// 184namespace llvm { 185class SelectionDAGLowering { 186 MachineBasicBlock *CurMBB; 187 188 std::map<const Value*, SDOperand> NodeMap; 189 190 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 191 /// them up and then emit token factor nodes when possible. This allows us to 192 /// get simple disambiguation between loads without worrying about alias 193 /// analysis. 194 std::vector<SDOperand> PendingLoads; 195 196public: 197 // TLI - This is information that describes the available target features we 198 // need for lowering. This indicates when operations are unavailable, 199 // implemented with a libcall, etc. 200 TargetLowering &TLI; 201 SelectionDAG &DAG; 202 const TargetData &TD; 203 204 /// FuncInfo - Information about the function as a whole. 205 /// 206 FunctionLoweringInfo &FuncInfo; 207 208 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 209 FunctionLoweringInfo &funcinfo) 210 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 211 FuncInfo(funcinfo) { 212 } 213 214 /// getRoot - Return the current virtual root of the Selection DAG. 215 /// 216 SDOperand getRoot() { 217 if (PendingLoads.empty()) 218 return DAG.getRoot(); 219 220 if (PendingLoads.size() == 1) { 221 SDOperand Root = PendingLoads[0]; 222 DAG.setRoot(Root); 223 PendingLoads.clear(); 224 return Root; 225 } 226 227 // Otherwise, we have to make a token factor node. 228 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads); 229 PendingLoads.clear(); 230 DAG.setRoot(Root); 231 return Root; 232 } 233 234 void visit(Instruction &I) { visit(I.getOpcode(), I); } 235 236 void visit(unsigned Opcode, User &I) { 237 switch (Opcode) { 238 default: assert(0 && "Unknown instruction type encountered!"); 239 abort(); 240 // Build the switch statement using the Instruction.def file. 241#define HANDLE_INST(NUM, OPCODE, CLASS) \ 242 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 243#include "llvm/Instruction.def" 244 } 245 } 246 247 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 248 249 250 SDOperand getIntPtrConstant(uint64_t Val) { 251 return DAG.getConstant(Val, TLI.getPointerTy()); 252 } 253 254 SDOperand getValue(const Value *V) { 255 SDOperand &N = NodeMap[V]; 256 if (N.Val) return N; 257 258 MVT::ValueType VT = TLI.getValueType(V->getType()); 259 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) 260 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 261 visit(CE->getOpcode(), *CE); 262 assert(N.Val && "visit didn't populate the ValueMap!"); 263 return N; 264 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 265 return N = DAG.getGlobalAddress(GV, VT); 266 } else if (isa<ConstantPointerNull>(C)) { 267 return N = DAG.getConstant(0, TLI.getPointerTy()); 268 } else if (isa<UndefValue>(C)) { 269 /// FIXME: Implement UNDEFVALUE better. 270 if (MVT::isInteger(VT)) 271 return N = DAG.getConstant(0, VT); 272 else if (MVT::isFloatingPoint(VT)) 273 return N = DAG.getConstantFP(0, VT); 274 else 275 assert(0 && "Unknown value type!"); 276 277 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 278 return N = DAG.getConstantFP(CFP->getValue(), VT); 279 } else { 280 // Canonicalize all constant ints to be unsigned. 281 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT); 282 } 283 284 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 285 std::map<const AllocaInst*, int>::iterator SI = 286 FuncInfo.StaticAllocaMap.find(AI); 287 if (SI != FuncInfo.StaticAllocaMap.end()) 288 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 289 } 290 291 std::map<const Value*, unsigned>::const_iterator VMI = 292 FuncInfo.ValueMap.find(V); 293 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); 294 295 return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode()); 296 } 297 298 const SDOperand &setValue(const Value *V, SDOperand NewN) { 299 SDOperand &N = NodeMap[V]; 300 assert(N.Val == 0 && "Already set a value for this node!"); 301 return N = NewN; 302 } 303 304 // Terminator instructions. 305 void visitRet(ReturnInst &I); 306 void visitBr(BranchInst &I); 307 void visitUnreachable(UnreachableInst &I) { /* noop */ } 308 309 // These all get lowered before this pass. 310 void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); } 311 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); } 312 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); } 313 314 // 315 void visitBinary(User &I, unsigned Opcode); 316 void visitAdd(User &I) { visitBinary(I, ISD::ADD); } 317 void visitSub(User &I); 318 void visitMul(User &I) { visitBinary(I, ISD::MUL); } 319 void visitDiv(User &I) { 320 visitBinary(I, I.getType()->isUnsigned() ? ISD::UDIV : ISD::SDIV); 321 } 322 void visitRem(User &I) { 323 visitBinary(I, I.getType()->isUnsigned() ? ISD::UREM : ISD::SREM); 324 } 325 void visitAnd(User &I) { visitBinary(I, ISD::AND); } 326 void visitOr (User &I) { visitBinary(I, ISD::OR); } 327 void visitXor(User &I) { visitBinary(I, ISD::XOR); } 328 void visitShl(User &I) { visitBinary(I, ISD::SHL); } 329 void visitShr(User &I) { 330 visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA); 331 } 332 333 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc); 334 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); } 335 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); } 336 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); } 337 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); } 338 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); } 339 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); } 340 341 void visitGetElementPtr(User &I); 342 void visitCast(User &I); 343 void visitSelect(User &I); 344 // 345 346 void visitMalloc(MallocInst &I); 347 void visitFree(FreeInst &I); 348 void visitAlloca(AllocaInst &I); 349 void visitLoad(LoadInst &I); 350 void visitStore(StoreInst &I); 351 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 352 void visitCall(CallInst &I); 353 354 void visitVAStart(CallInst &I); 355 void visitVANext(VANextInst &I); 356 void visitVAArg(VAArgInst &I); 357 void visitVAEnd(CallInst &I); 358 void visitVACopy(CallInst &I); 359 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress); 360 361 void visitMemIntrinsic(CallInst &I, unsigned Op); 362 363 void visitUserOp1(Instruction &I) { 364 assert(0 && "UserOp1 should not exist at instruction selection time!"); 365 abort(); 366 } 367 void visitUserOp2(Instruction &I) { 368 assert(0 && "UserOp2 should not exist at instruction selection time!"); 369 abort(); 370 } 371}; 372} // end namespace llvm 373 374void SelectionDAGLowering::visitRet(ReturnInst &I) { 375 if (I.getNumOperands() == 0) { 376 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 377 return; 378 } 379 380 SDOperand Op1 = getValue(I.getOperand(0)); 381 MVT::ValueType TmpVT; 382 383 switch (Op1.getValueType()) { 384 default: assert(0 && "Unknown value type!"); 385 case MVT::i1: 386 case MVT::i8: 387 case MVT::i16: 388 case MVT::i32: 389 // If this is a machine where 32-bits is legal or expanded, promote to 390 // 32-bits, otherwise, promote to 64-bits. 391 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 392 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 393 else 394 TmpVT = MVT::i32; 395 396 // Extend integer types to result type. 397 if (I.getOperand(0)->getType()->isSigned()) 398 Op1 = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, Op1); 399 else 400 Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1); 401 break; 402 case MVT::f32: 403 // Extend float to double. 404 Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1); 405 break; 406 case MVT::i64: 407 case MVT::f64: 408 break; // No extension needed! 409 } 410 411 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot(), Op1)); 412} 413 414void SelectionDAGLowering::visitBr(BranchInst &I) { 415 // Update machine-CFG edges. 416 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 417 418 // Figure out which block is immediately after the current one. 419 MachineBasicBlock *NextBlock = 0; 420 MachineFunction::iterator BBI = CurMBB; 421 if (++BBI != CurMBB->getParent()->end()) 422 NextBlock = BBI; 423 424 if (I.isUnconditional()) { 425 // If this is not a fall-through branch, emit the branch. 426 if (Succ0MBB != NextBlock) 427 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 428 DAG.getBasicBlock(Succ0MBB))); 429 } else { 430 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 431 432 SDOperand Cond = getValue(I.getCondition()); 433 434 if (Succ1MBB == NextBlock) { 435 // If the condition is false, fall through. This means we should branch 436 // if the condition is true to Succ #0. 437 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 438 Cond, DAG.getBasicBlock(Succ0MBB))); 439 } else if (Succ0MBB == NextBlock) { 440 // If the condition is true, fall through. This means we should branch if 441 // the condition is false to Succ #1. Invert the condition first. 442 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 443 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 444 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 445 Cond, DAG.getBasicBlock(Succ1MBB))); 446 } else { 447 // Neither edge is a fall through. If the comparison is true, jump to 448 // Succ#0, otherwise branch unconditionally to succ #1. 449 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 450 Cond, DAG.getBasicBlock(Succ0MBB))); 451 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 452 DAG.getBasicBlock(Succ1MBB))); 453 } 454 } 455} 456 457void SelectionDAGLowering::visitSub(User &I) { 458 // -0.0 - X --> fneg 459 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 460 if (CFP->isExactlyValue(-0.0)) { 461 SDOperand Op2 = getValue(I.getOperand(1)); 462 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 463 return; 464 } 465 466 visitBinary(I, ISD::SUB); 467} 468 469void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) { 470 SDOperand Op1 = getValue(I.getOperand(0)); 471 SDOperand Op2 = getValue(I.getOperand(1)); 472 473 if (isa<ShiftInst>(I)) 474 Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2); 475 476 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 477} 478 479void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode, 480 ISD::CondCode UnsignedOpcode) { 481 SDOperand Op1 = getValue(I.getOperand(0)); 482 SDOperand Op2 = getValue(I.getOperand(1)); 483 ISD::CondCode Opcode = SignedOpcode; 484 if (I.getOperand(0)->getType()->isUnsigned()) 485 Opcode = UnsignedOpcode; 486 setValue(&I, DAG.getSetCC(Opcode, MVT::i1, Op1, Op2)); 487} 488 489void SelectionDAGLowering::visitSelect(User &I) { 490 SDOperand Cond = getValue(I.getOperand(0)); 491 SDOperand TrueVal = getValue(I.getOperand(1)); 492 SDOperand FalseVal = getValue(I.getOperand(2)); 493 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 494 TrueVal, FalseVal)); 495} 496 497void SelectionDAGLowering::visitCast(User &I) { 498 SDOperand N = getValue(I.getOperand(0)); 499 MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType()); 500 MVT::ValueType DestTy = TLI.getValueType(I.getType()); 501 502 if (N.getValueType() == DestTy) { 503 setValue(&I, N); // noop cast. 504 } else if (isInteger(SrcTy)) { 505 if (isInteger(DestTy)) { // Int -> Int cast 506 if (DestTy < SrcTy) // Truncating cast? 507 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N)); 508 else if (I.getOperand(0)->getType()->isSigned()) 509 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N)); 510 else 511 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N)); 512 } else { // Int -> FP cast 513 if (I.getOperand(0)->getType()->isSigned()) 514 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N)); 515 else 516 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N)); 517 } 518 } else { 519 assert(isFloatingPoint(SrcTy) && "Unknown value type!"); 520 if (isFloatingPoint(DestTy)) { // FP -> FP cast 521 if (DestTy < SrcTy) // Rounding cast? 522 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N)); 523 else 524 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N)); 525 } else { // FP -> Int cast. 526 if (I.getType()->isSigned()) 527 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N)); 528 else 529 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N)); 530 } 531 } 532} 533 534void SelectionDAGLowering::visitGetElementPtr(User &I) { 535 SDOperand N = getValue(I.getOperand(0)); 536 const Type *Ty = I.getOperand(0)->getType(); 537 const Type *UIntPtrTy = TD.getIntPtrType(); 538 539 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 540 OI != E; ++OI) { 541 Value *Idx = *OI; 542 if (const StructType *StTy = dyn_cast<StructType> (Ty)) { 543 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 544 if (Field) { 545 // N = N + Offset 546 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field]; 547 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 548 getIntPtrConstant(Offset)); 549 } 550 Ty = StTy->getElementType(Field); 551 } else { 552 Ty = cast<SequentialType>(Ty)->getElementType(); 553 if (!isa<Constant>(Idx) || !cast<Constant>(Idx)->isNullValue()) { 554 // N = N + Idx * ElementSize; 555 uint64_t ElementSize = TD.getTypeSize(Ty); 556 SDOperand IdxN = getValue(Idx), Scale = getIntPtrConstant(ElementSize); 557 558 // If the index is smaller or larger than intptr_t, truncate or extend 559 // it. 560 if (IdxN.getValueType() < Scale.getValueType()) { 561 if (Idx->getType()->isSigned()) 562 IdxN = DAG.getNode(ISD::SIGN_EXTEND, Scale.getValueType(), IdxN); 563 else 564 IdxN = DAG.getNode(ISD::ZERO_EXTEND, Scale.getValueType(), IdxN); 565 } else if (IdxN.getValueType() > Scale.getValueType()) 566 IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN); 567 568 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 569 570 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 571 } 572 } 573 } 574 setValue(&I, N); 575} 576 577void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 578 // If this is a fixed sized alloca in the entry block of the function, 579 // allocate it statically on the stack. 580 if (FuncInfo.StaticAllocaMap.count(&I)) 581 return; // getValue will auto-populate this. 582 583 const Type *Ty = I.getAllocatedType(); 584 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty); 585 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 586 587 SDOperand AllocSize = getValue(I.getArraySize()); 588 MVT::ValueType IntPtr = TLI.getPointerTy(); 589 if (IntPtr < AllocSize.getValueType()) 590 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 591 else if (IntPtr > AllocSize.getValueType()) 592 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 593 594 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 595 getIntPtrConstant(TySize)); 596 597 // Handle alignment. If the requested alignment is less than or equal to the 598 // stack alignment, ignore it and round the size of the allocation up to the 599 // stack alignment size. If the size is greater than the stack alignment, we 600 // note this in the DYNAMIC_STACKALLOC node. 601 unsigned StackAlign = 602 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 603 if (Align <= StackAlign) { 604 Align = 0; 605 // Add SA-1 to the size. 606 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 607 getIntPtrConstant(StackAlign-1)); 608 // Mask out the low bits for alignment purposes. 609 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 610 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 611 } 612 613 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, AllocSize.getValueType(), 614 getRoot(), AllocSize, 615 getIntPtrConstant(Align)); 616 DAG.setRoot(setValue(&I, DSA).getValue(1)); 617 618 // Inform the Frame Information that we have just allocated a variable-sized 619 // object. 620 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 621} 622 623 624void SelectionDAGLowering::visitLoad(LoadInst &I) { 625 SDOperand Ptr = getValue(I.getOperand(0)); 626 627 SDOperand Root; 628 if (I.isVolatile()) 629 Root = getRoot(); 630 else { 631 // Do not serialize non-volatile loads against each other. 632 Root = DAG.getRoot(); 633 } 634 635 SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr); 636 setValue(&I, L); 637 638 if (I.isVolatile()) 639 DAG.setRoot(L.getValue(1)); 640 else 641 PendingLoads.push_back(L.getValue(1)); 642} 643 644 645void SelectionDAGLowering::visitStore(StoreInst &I) { 646 Value *SrcV = I.getOperand(0); 647 SDOperand Src = getValue(SrcV); 648 SDOperand Ptr = getValue(I.getOperand(1)); 649 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr)); 650} 651 652void SelectionDAGLowering::visitCall(CallInst &I) { 653 const char *RenameFn = 0; 654 if (Function *F = I.getCalledFunction()) 655 switch (F->getIntrinsicID()) { 656 case 0: break; // Not an intrinsic. 657 case Intrinsic::vastart: visitVAStart(I); return; 658 case Intrinsic::vaend: visitVAEnd(I); return; 659 case Intrinsic::vacopy: visitVACopy(I); return; 660 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return; 661 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return; 662 default: 663 // FIXME: IMPLEMENT THESE. 664 // readport, writeport, readio, writeio 665 assert(0 && "This intrinsic is not implemented yet!"); 666 return; 667 case Intrinsic::setjmp: RenameFn = "setjmp"; break; 668 case Intrinsic::longjmp: RenameFn = "longjmp"; break; 669 case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return; 670 case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return; 671 case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return; 672 673 case Intrinsic::isunordered: 674 setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1, getValue(I.getOperand(1)), 675 getValue(I.getOperand(2)))); 676 return; 677 case Intrinsic::pcmarker: { 678 SDOperand Num = getValue(I.getOperand(1)); 679 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Num)); 680 return; 681 } 682 683 } 684 685 SDOperand Callee; 686 if (!RenameFn) 687 Callee = getValue(I.getOperand(0)); 688 else 689 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 690 std::vector<std::pair<SDOperand, const Type*> > Args; 691 692 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 693 Value *Arg = I.getOperand(i); 694 SDOperand ArgNode = getValue(Arg); 695 Args.push_back(std::make_pair(ArgNode, Arg->getType())); 696 } 697 698 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); 699 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 700 701 std::pair<SDOperand,SDOperand> Result = 702 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG); 703 if (I.getType() != Type::VoidTy) 704 setValue(&I, Result.first); 705 DAG.setRoot(Result.second); 706} 707 708void SelectionDAGLowering::visitMalloc(MallocInst &I) { 709 SDOperand Src = getValue(I.getOperand(0)); 710 711 MVT::ValueType IntPtr = TLI.getPointerTy(); 712 713 if (IntPtr < Src.getValueType()) 714 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 715 else if (IntPtr > Src.getValueType()) 716 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 717 718 // Scale the source by the type size. 719 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType()); 720 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 721 Src, getIntPtrConstant(ElementSize)); 722 723 std::vector<std::pair<SDOperand, const Type*> > Args; 724 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType())); 725 726 std::pair<SDOperand,SDOperand> Result = 727 TLI.LowerCallTo(getRoot(), I.getType(), false, 728 DAG.getExternalSymbol("malloc", IntPtr), 729 Args, DAG); 730 setValue(&I, Result.first); // Pointers always fit in registers 731 DAG.setRoot(Result.second); 732} 733 734void SelectionDAGLowering::visitFree(FreeInst &I) { 735 std::vector<std::pair<SDOperand, const Type*> > Args; 736 Args.push_back(std::make_pair(getValue(I.getOperand(0)), 737 TLI.getTargetData().getIntPtrType())); 738 MVT::ValueType IntPtr = TLI.getPointerTy(); 739 std::pair<SDOperand,SDOperand> Result = 740 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, 741 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 742 DAG.setRoot(Result.second); 743} 744 745std::pair<SDOperand, SDOperand> 746TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) { 747 // We have no sane default behavior, just emit a useful error message and bail 748 // out. 749 std::cerr << "Variable arguments handling not implemented on this target!\n"; 750 abort(); 751 return std::make_pair(SDOperand(), SDOperand()); 752} 753 754SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand L, 755 SelectionDAG &DAG) { 756 // Default to a noop. 757 return Chain; 758} 759 760std::pair<SDOperand,SDOperand> 761TargetLowering::LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG) { 762 // Default to returning the input list. 763 return std::make_pair(L, Chain); 764} 765 766std::pair<SDOperand,SDOperand> 767TargetLowering::LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList, 768 const Type *ArgTy, SelectionDAG &DAG) { 769 // We have no sane default behavior, just emit a useful error message and bail 770 // out. 771 std::cerr << "Variable arguments handling not implemented on this target!\n"; 772 abort(); 773 return std::make_pair(SDOperand(), SDOperand()); 774} 775 776 777void SelectionDAGLowering::visitVAStart(CallInst &I) { 778 std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG); 779 setValue(&I, Result.first); 780 DAG.setRoot(Result.second); 781} 782 783void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 784 std::pair<SDOperand,SDOperand> Result = 785 TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)), 786 I.getType(), DAG); 787 setValue(&I, Result.first); 788 DAG.setRoot(Result.second); 789} 790 791void SelectionDAGLowering::visitVANext(VANextInst &I) { 792 std::pair<SDOperand,SDOperand> Result = 793 TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)), 794 I.getArgType(), DAG); 795 setValue(&I, Result.first); 796 DAG.setRoot(Result.second); 797} 798 799void SelectionDAGLowering::visitVAEnd(CallInst &I) { 800 DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), DAG)); 801} 802 803void SelectionDAGLowering::visitVACopy(CallInst &I) { 804 std::pair<SDOperand,SDOperand> Result = 805 TLI.LowerVACopy(getRoot(), getValue(I.getOperand(1)), DAG); 806 setValue(&I, Result.first); 807 DAG.setRoot(Result.second); 808} 809 810 811// It is always conservatively correct for llvm.returnaddress and 812// llvm.frameaddress to return 0. 813std::pair<SDOperand, SDOperand> 814TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, 815 unsigned Depth, SelectionDAG &DAG) { 816 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain); 817} 818 819SDOperand TargetLowering::LowerOperation(SDOperand Op) { 820 assert(0 && "LowerOperation not implemented for this target!"); 821 abort(); 822 return SDOperand(); 823} 824 825void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) { 826 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue(); 827 std::pair<SDOperand,SDOperand> Result = 828 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG); 829 setValue(&I, Result.first); 830 DAG.setRoot(Result.second); 831} 832 833void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 834 std::vector<SDOperand> Ops; 835 Ops.push_back(getRoot()); 836 Ops.push_back(getValue(I.getOperand(1))); 837 Ops.push_back(getValue(I.getOperand(2))); 838 Ops.push_back(getValue(I.getOperand(3))); 839 Ops.push_back(getValue(I.getOperand(4))); 840 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops)); 841} 842 843//===----------------------------------------------------------------------===// 844// SelectionDAGISel code 845//===----------------------------------------------------------------------===// 846 847unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 848 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 849} 850 851 852 853bool SelectionDAGISel::runOnFunction(Function &Fn) { 854 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 855 RegMap = MF.getSSARegMap(); 856 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n"); 857 858 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 859 860 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 861 SelectBasicBlock(I, MF, FuncInfo); 862 863 return true; 864} 865 866 867SDOperand SelectionDAGISel:: 868CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) { 869 SelectionDAG &DAG = SDL.DAG; 870 SDOperand Op = SDL.getValue(V); 871 assert((Op.getOpcode() != ISD::CopyFromReg || 872 cast<RegSDNode>(Op)->getReg() != Reg) && 873 "Copy from a reg to the same reg!"); 874 return DAG.getCopyToReg(SDL.getRoot(), Op, Reg); 875} 876 877/// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a 878/// single basic block, return that block. Otherwise, return a null pointer. 879static BasicBlock *IsOnlyUsedInOneBasicBlock(Argument *A) { 880 if (A->use_empty()) return 0; 881 BasicBlock *BB = cast<Instruction>(A->use_back())->getParent(); 882 for (Argument::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; 883 ++UI) 884 if (isa<PHINode>(*UI) || cast<Instruction>(*UI)->getParent() != BB) 885 return 0; // Disagreement among the users? 886 887 // Okay, there is a single BB user. Only permit this optimization if this is 888 // the entry block, otherwise, we might sink argument loads into loops and 889 // stuff. Later, when we have global instruction selection, this won't be an 890 // issue clearly. 891 if (BB == BB->getParent()->begin()) 892 return BB; 893 return 0; 894} 895 896void SelectionDAGISel:: 897LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 898 std::vector<SDOperand> &UnorderedChains) { 899 // If this is the entry block, emit arguments. 900 Function &F = *BB->getParent(); 901 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 902 903 if (BB == &F.front()) { 904 SDOperand OldRoot = SDL.DAG.getRoot(); 905 906 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 907 908 // If there were side effects accessing the argument list, do not do 909 // anything special. 910 if (OldRoot != SDL.DAG.getRoot()) { 911 unsigned a = 0; 912 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 913 AI != E; ++AI,++a) 914 if (!AI->use_empty()) { 915 SDL.setValue(AI, Args[a]); 916 SDOperand Copy = 917 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 918 UnorderedChains.push_back(Copy); 919 } 920 } else { 921 // Otherwise, if any argument is only accessed in a single basic block, 922 // emit that argument only to that basic block. 923 unsigned a = 0; 924 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 925 AI != E; ++AI,++a) 926 if (!AI->use_empty()) { 927 if (BasicBlock *BBU = IsOnlyUsedInOneBasicBlock(AI)) { 928 FuncInfo.BlockLocalArguments.insert(std::make_pair(BBU, 929 std::make_pair(AI, a))); 930 } else { 931 SDL.setValue(AI, Args[a]); 932 SDOperand Copy = 933 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 934 UnorderedChains.push_back(Copy); 935 } 936 } 937 } 938 } 939 940 // See if there are any block-local arguments that need to be emitted in this 941 // block. 942 943 if (!FuncInfo.BlockLocalArguments.empty()) { 944 std::multimap<BasicBlock*, std::pair<Argument*, unsigned> >::iterator BLAI = 945 FuncInfo.BlockLocalArguments.lower_bound(BB); 946 if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) { 947 // Lower the arguments into this block. 948 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 949 950 // Set up the value mapping for the local arguments. 951 for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB; 952 ++BLAI) 953 SDL.setValue(BLAI->second.first, Args[BLAI->second.second]); 954 955 // Any dead arguments will just be ignored here. 956 } 957 } 958} 959 960 961void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 962 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 963 FunctionLoweringInfo &FuncInfo) { 964 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 965 966 std::vector<SDOperand> UnorderedChains; 967 968 // Lower any arguments needed in this block. 969 LowerArguments(LLVMBB, SDL, UnorderedChains); 970 971 BB = FuncInfo.MBBMap[LLVMBB]; 972 SDL.setCurrentBasicBlock(BB); 973 974 // Lower all of the non-terminator instructions. 975 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 976 I != E; ++I) 977 SDL.visit(*I); 978 979 // Ensure that all instructions which are used outside of their defining 980 // blocks are available as virtual registers. 981 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 982 if (!I->use_empty() && !isa<PHINode>(I)) { 983 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 984 if (VMI != FuncInfo.ValueMap.end()) 985 UnorderedChains.push_back( 986 CopyValueToVirtualRegister(SDL, I, VMI->second)); 987 } 988 989 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 990 // ensure constants are generated when needed. Remember the virtual registers 991 // that need to be added to the Machine PHI nodes as input. We cannot just 992 // directly add them, because expansion might result in multiple MBB's for one 993 // BB. As such, the start of the BB might correspond to a different MBB than 994 // the end. 995 // 996 997 // Emit constants only once even if used by multiple PHI nodes. 998 std::map<Constant*, unsigned> ConstantsOut; 999 1000 // Check successor nodes PHI nodes that expect a constant to be available from 1001 // this block. 1002 TerminatorInst *TI = LLVMBB->getTerminator(); 1003 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1004 BasicBlock *SuccBB = TI->getSuccessor(succ); 1005 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin(); 1006 PHINode *PN; 1007 1008 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1009 // nodes and Machine PHI nodes, but the incoming operands have not been 1010 // emitted yet. 1011 for (BasicBlock::iterator I = SuccBB->begin(); 1012 (PN = dyn_cast<PHINode>(I)); ++I) 1013 if (!PN->use_empty()) { 1014 unsigned Reg; 1015 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1016 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 1017 unsigned &RegOut = ConstantsOut[C]; 1018 if (RegOut == 0) { 1019 RegOut = FuncInfo.CreateRegForValue(C); 1020 UnorderedChains.push_back( 1021 CopyValueToVirtualRegister(SDL, C, RegOut)); 1022 } 1023 Reg = RegOut; 1024 } else { 1025 Reg = FuncInfo.ValueMap[PHIOp]; 1026 if (Reg == 0) { 1027 assert(isa<AllocaInst>(PHIOp) && 1028 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 1029 "Didn't codegen value into a register!??"); 1030 Reg = FuncInfo.CreateRegForValue(PHIOp); 1031 UnorderedChains.push_back( 1032 CopyValueToVirtualRegister(SDL, PHIOp, Reg)); 1033 } 1034 } 1035 1036 // Remember that this register needs to added to the machine PHI node as 1037 // the input for this MBB. 1038 unsigned NumElements = 1039 TLI.getNumElements(TLI.getValueType(PN->getType())); 1040 for (unsigned i = 0, e = NumElements; i != e; ++i) 1041 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 1042 } 1043 } 1044 ConstantsOut.clear(); 1045 1046 // Turn all of the unordered chains into one factored node. 1047 if (!UnorderedChains.empty()) { 1048 UnorderedChains.push_back(SDL.getRoot()); 1049 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains)); 1050 } 1051 1052 // Lower the terminator after the copies are emitted. 1053 SDL.visit(*LLVMBB->getTerminator()); 1054 1055 // Make sure the root of the DAG is up-to-date. 1056 DAG.setRoot(SDL.getRoot()); 1057} 1058 1059void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 1060 FunctionLoweringInfo &FuncInfo) { 1061 SelectionDAG DAG(TLI, MF); 1062 CurDAG = &DAG; 1063 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 1064 1065 // First step, lower LLVM code to some DAG. This DAG may use operations and 1066 // types that are not supported by the target. 1067 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 1068 1069 DEBUG(std::cerr << "Lowered selection DAG:\n"); 1070 DEBUG(DAG.dump()); 1071 1072 // Second step, hack on the DAG until it only uses operations and types that 1073 // the target supports. 1074 DAG.Legalize(); 1075 1076 DEBUG(std::cerr << "Legalized selection DAG:\n"); 1077 DEBUG(DAG.dump()); 1078 1079 // Third, instruction select all of the operations to machine code, adding the 1080 // code to the MachineBasicBlock. 1081 InstructionSelectBasicBlock(DAG); 1082 1083 if (ViewDAGs) DAG.viewGraph(); 1084 1085 DEBUG(std::cerr << "Selected machine code:\n"); 1086 DEBUG(BB->dump()); 1087 1088 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1089 // PHI nodes in successors. 1090 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 1091 MachineInstr *PHI = PHINodesToUpdate[i].first; 1092 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1093 "This is not a machine PHI node that we are updating!"); 1094 PHI->addRegOperand(PHINodesToUpdate[i].second); 1095 PHI->addMachineBasicBlockOperand(BB); 1096 } 1097 1098 // Finally, add the CFG edges from the last selected MBB to the successor 1099 // MBBs. 1100 TerminatorInst *TI = LLVMBB->getTerminator(); 1101 for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) { 1102 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[TI->getSuccessor(i)]; 1103 BB->addSuccessor(Succ0MBB); 1104 } 1105} 1106