SelectionDAGISel.cpp revision bd3ba461eb5578a81ba09ff7bd7eb271d1130196
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/Collector.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetData.h" 40#include "llvm/Target/TargetFrameInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetLowering.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/Timer.h" 49#include <algorithm> 50using namespace llvm; 51 52static cl::opt<bool> 53EnableValueProp("enable-value-prop", cl::Hidden); 54static cl::opt<bool> 55EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 56 57 58#ifndef NDEBUG 59static cl::opt<bool> 60ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 61 cl::desc("Pop up a window to show dags before the first " 62 "dag combine pass")); 63static cl::opt<bool> 64ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 65 cl::desc("Pop up a window to show dags before legalize types")); 66static cl::opt<bool> 67ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 68 cl::desc("Pop up a window to show dags before legalize")); 69static cl::opt<bool> 70ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before the second " 72 "dag combine pass")); 73static cl::opt<bool> 74ViewISelDAGs("view-isel-dags", cl::Hidden, 75 cl::desc("Pop up a window to show isel dags as they are selected")); 76static cl::opt<bool> 77ViewSchedDAGs("view-sched-dags", cl::Hidden, 78 cl::desc("Pop up a window to show sched dags as they are processed")); 79static cl::opt<bool> 80ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 81 cl::desc("Pop up a window to show SUnit dags after they are processed")); 82#else 83static const bool ViewDAGCombine1 = false, 84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 85 ViewDAGCombine2 = false, 86 ViewISelDAGs = false, ViewSchedDAGs = false, 87 ViewSUnitDAGs = false; 88#endif 89 90//===---------------------------------------------------------------------===// 91/// 92/// RegisterScheduler class - Track the registration of instruction schedulers. 93/// 94//===---------------------------------------------------------------------===// 95MachinePassRegistry RegisterScheduler::Registry; 96 97//===---------------------------------------------------------------------===// 98/// 99/// ISHeuristic command line option for instruction schedulers. 100/// 101//===---------------------------------------------------------------------===// 102static cl::opt<RegisterScheduler::FunctionPassCtor, false, 103 RegisterPassParser<RegisterScheduler> > 104ISHeuristic("pre-RA-sched", 105 cl::init(&createDefaultScheduler), 106 cl::desc("Instruction schedulers available (before register" 107 " allocation):")); 108 109static RegisterScheduler 110defaultListDAGScheduler("default", " Best scheduler for the target", 111 createDefaultScheduler); 112 113namespace { struct SDISelAsmOperandInfo; } 114 115/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence 116/// insertvalue or extractvalue indices that identify a member, return 117/// the linearized index of the start of the member. 118/// 119static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, 120 const unsigned *Indices, 121 const unsigned *IndicesEnd, 122 unsigned CurIndex = 0) { 123 // Base case: We're done. 124 if (Indices && Indices == IndicesEnd) 125 return CurIndex; 126 127 // Given a struct type, recursively traverse the elements. 128 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 129 for (StructType::element_iterator EB = STy->element_begin(), 130 EI = EB, 131 EE = STy->element_end(); 132 EI != EE; ++EI) { 133 if (Indices && *Indices == unsigned(EI - EB)) 134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex); 135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex); 136 } 137 } 138 // Given an array type, recursively traverse the elements. 139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 140 const Type *EltTy = ATy->getElementType(); 141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) { 142 if (Indices && *Indices == i) 143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex); 144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex); 145 } 146 } 147 // We haven't found the type we're looking for, so keep searching. 148 return CurIndex + 1; 149} 150 151/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of 152/// MVTs that represent all the individual underlying 153/// non-aggregate types that comprise it. 154/// 155/// If Offsets is non-null, it points to a vector to be filled in 156/// with the in-memory offsets of each of the individual values. 157/// 158static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, 159 SmallVectorImpl<MVT> &ValueVTs, 160 SmallVectorImpl<uint64_t> *Offsets = 0, 161 uint64_t StartingOffset = 0) { 162 // Given a struct type, recursively traverse the elements. 163 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); 165 for (StructType::element_iterator EB = STy->element_begin(), 166 EI = EB, 167 EE = STy->element_end(); 168 EI != EE; ++EI) 169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, 170 StartingOffset + SL->getElementOffset(EI - EB)); 171 return; 172 } 173 // Given an array type, recursively traverse the elements. 174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 175 const Type *EltTy = ATy->getElementType(); 176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy); 177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) 178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, 179 StartingOffset + i * EltSize); 180 return; 181 } 182 // Base case: we can get an MVT for this LLVM IR type. 183 ValueVTs.push_back(TLI.getValueType(Ty)); 184 if (Offsets) 185 Offsets->push_back(StartingOffset); 186} 187 188namespace { 189 /// RegsForValue - This struct represents the registers (physical or virtual) 190 /// that a particular set of values is assigned, and the type information about 191 /// the value. The most common situation is to represent one value at a time, 192 /// but struct or array values are handled element-wise as multiple values. 193 /// The splitting of aggregates is performed recursively, so that we never 194 /// have aggregate-typed registers. The values at this point do not necessarily 195 /// have legal types, so each value may require one or more registers of some 196 /// legal type. 197 /// 198 struct VISIBILITY_HIDDEN RegsForValue { 199 /// TLI - The TargetLowering object. 200 /// 201 const TargetLowering *TLI; 202 203 /// ValueVTs - The value types of the values, which may not be legal, and 204 /// may need be promoted or synthesized from one or more registers. 205 /// 206 SmallVector<MVT, 4> ValueVTs; 207 208 /// RegVTs - The value types of the registers. This is the same size as 209 /// ValueVTs and it records, for each value, what the type of the assigned 210 /// register or registers are. (Individual values are never synthesized 211 /// from more than one type of register.) 212 /// 213 /// With virtual registers, the contents of RegVTs is redundant with TLI's 214 /// getRegisterType member function, however when with physical registers 215 /// it is necessary to have a separate record of the types. 216 /// 217 SmallVector<MVT, 4> RegVTs; 218 219 /// Regs - This list holds the registers assigned to the values. 220 /// Each legal or promoted value requires one register, and each 221 /// expanded value requires multiple registers. 222 /// 223 SmallVector<unsigned, 4> Regs; 224 225 RegsForValue() : TLI(0) {} 226 227 RegsForValue(const TargetLowering &tli, 228 const SmallVector<unsigned, 4> ®s, 229 MVT regvt, MVT valuevt) 230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 231 RegsForValue(const TargetLowering &tli, 232 const SmallVector<unsigned, 4> ®s, 233 const SmallVector<MVT, 4> ®vts, 234 const SmallVector<MVT, 4> &valuevts) 235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 236 RegsForValue(const TargetLowering &tli, 237 unsigned Reg, const Type *Ty) : TLI(&tli) { 238 ComputeValueVTs(tli, Ty, ValueVTs); 239 240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 241 MVT ValueVT = ValueVTs[Value]; 242 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 243 MVT RegisterVT = TLI->getRegisterType(ValueVT); 244 for (unsigned i = 0; i != NumRegs; ++i) 245 Regs.push_back(Reg + i); 246 RegVTs.push_back(RegisterVT); 247 Reg += NumRegs; 248 } 249 } 250 251 /// append - Add the specified values to this one. 252 void append(const RegsForValue &RHS) { 253 TLI = RHS.TLI; 254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 256 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 257 } 258 259 260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 261 /// this value and returns the result as a ValueVTs value. This uses 262 /// Chain/Flag as the input and updates them for the output Chain/Flag. 263 /// If the Flag pointer is NULL, no flag is used. 264 SDValue getCopyFromRegs(SelectionDAG &DAG, 265 SDValue &Chain, SDValue *Flag) const; 266 267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 268 /// specified value into the registers specified by this object. This uses 269 /// Chain/Flag as the input and updates them for the output Chain/Flag. 270 /// If the Flag pointer is NULL, no flag is used. 271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, 272 SDValue &Chain, SDValue *Flag) const; 273 274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 275 /// operand list. This adds the code marker and includes the number of 276 /// values added into it. 277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 278 std::vector<SDValue> &Ops) const; 279 }; 280} 281 282namespace llvm { 283 //===--------------------------------------------------------------------===// 284 /// createDefaultScheduler - This creates an instruction scheduler appropriate 285 /// for the target. 286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 287 SelectionDAG *DAG, 288 MachineBasicBlock *BB, 289 bool Fast) { 290 TargetLowering &TLI = IS->getTargetLowering(); 291 292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 293 return createTDListDAGScheduler(IS, DAG, BB, Fast); 294 } else { 295 assert(TLI.getSchedulingPreference() == 296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 297 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 298 } 299 } 300 301 302 //===--------------------------------------------------------------------===// 303 /// FunctionLoweringInfo - This contains information that is global to a 304 /// function that is used when lowering a region of the function. 305 class FunctionLoweringInfo { 306 public: 307 TargetLowering &TLI; 308 Function &Fn; 309 MachineFunction &MF; 310 MachineRegisterInfo &RegInfo; 311 312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 313 314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 316 317 /// ValueMap - Since we emit code for the function a basic block at a time, 318 /// we must remember which virtual registers hold the values for 319 /// cross-basic-block values. 320 DenseMap<const Value*, unsigned> ValueMap; 321 322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 323 /// the entry block. This allows the allocas to be efficiently referenced 324 /// anywhere in the function. 325 std::map<const AllocaInst*, int> StaticAllocaMap; 326 327#ifndef NDEBUG 328 SmallSet<Instruction*, 8> CatchInfoLost; 329 SmallSet<Instruction*, 8> CatchInfoFound; 330#endif 331 332 unsigned MakeReg(MVT VT) { 333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); 334 } 335 336 /// isExportedInst - Return true if the specified value is an instruction 337 /// exported from its block. 338 bool isExportedInst(const Value *V) { 339 return ValueMap.count(V); 340 } 341 342 unsigned CreateRegForValue(const Value *V); 343 344 unsigned InitializeRegForValue(const Value *V) { 345 unsigned &R = ValueMap[V]; 346 assert(R == 0 && "Already initialized this value register!"); 347 return R = CreateRegForValue(V); 348 } 349 350 struct LiveOutInfo { 351 unsigned NumSignBits; 352 APInt KnownOne, KnownZero; 353 LiveOutInfo() : NumSignBits(0) {} 354 }; 355 356 /// LiveOutRegInfo - Information about live out vregs, indexed by their 357 /// register number offset by 'FirstVirtualRegister'. 358 std::vector<LiveOutInfo> LiveOutRegInfo; 359 }; 360} 361 362/// isSelector - Return true if this instruction is a call to the 363/// eh.selector intrinsic. 364static bool isSelector(Instruction *I) { 365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 367 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 368 return false; 369} 370 371/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 372/// PHI nodes or outside of the basic block that defines it, or used by a 373/// switch or atomic instruction, which may expand to multiple basic blocks. 374static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 375 if (isa<PHINode>(I)) return true; 376 BasicBlock *BB = I->getParent(); 377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 379 // FIXME: Remove switchinst special case. 380 isa<SwitchInst>(*UI)) 381 return true; 382 return false; 383} 384 385/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 386/// entry block, return true. This includes arguments used by switches, since 387/// the switch may expand into multiple basic blocks. 388static bool isOnlyUsedInEntryBlock(Argument *A) { 389 BasicBlock *Entry = A->getParent()->begin(); 390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 392 return false; // Use not in entry block. 393 return true; 394} 395 396FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 397 Function &fn, MachineFunction &mf) 398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { 399 400 // Create a vreg for each argument register that is not dead and is used 401 // outside of the entry block for the function. 402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 403 AI != E; ++AI) 404 if (!isOnlyUsedInEntryBlock(AI)) 405 InitializeRegForValue(AI); 406 407 // Initialize the mapping of values to registers. This is only set up for 408 // instruction values that are used outside of the block that defines 409 // them. 410 Function::iterator BB = Fn.begin(), EB = Fn.end(); 411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 414 const Type *Ty = AI->getAllocatedType(); 415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 416 unsigned Align = 417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 418 AI->getAlignment()); 419 420 TySize *= CUI->getZExtValue(); // Get total allocated size. 421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 422 StaticAllocaMap[AI] = 423 MF.getFrameInfo()->CreateStackObject(TySize, Align); 424 } 425 426 for (; BB != EB; ++BB) 427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 429 if (!isa<AllocaInst>(I) || 430 !StaticAllocaMap.count(cast<AllocaInst>(I))) 431 InitializeRegForValue(I); 432 433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 434 // also creates the initial PHI MachineInstrs, though none of the input 435 // operands are populated. 436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); 438 MBBMap[BB] = MBB; 439 MF.push_back(MBB); 440 441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 442 // appropriate. 443 PHINode *PN; 444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 445 if (PN->use_empty()) continue; 446 447 unsigned PHIReg = ValueMap[PN]; 448 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 449 450 SmallVector<MVT, 4> ValueVTs; 451 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 452 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 453 MVT VT = ValueVTs[vti]; 454 unsigned NumRegisters = TLI.getNumRegisters(VT); 455 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 456 for (unsigned i = 0; i != NumRegisters; ++i) 457 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 458 PHIReg += NumRegisters; 459 } 460 } 461 } 462} 463 464/// CreateRegForValue - Allocate the appropriate number of virtual registers of 465/// the correctly promoted or expanded types. Assign these registers 466/// consecutive vreg numbers and return the first assigned number. 467/// 468/// In the case that the given value has struct or array type, this function 469/// will assign registers for each member or element. 470/// 471unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 472 SmallVector<MVT, 4> ValueVTs; 473 ComputeValueVTs(TLI, V->getType(), ValueVTs); 474 475 unsigned FirstReg = 0; 476 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 477 MVT ValueVT = ValueVTs[Value]; 478 MVT RegisterVT = TLI.getRegisterType(ValueVT); 479 480 unsigned NumRegs = TLI.getNumRegisters(ValueVT); 481 for (unsigned i = 0; i != NumRegs; ++i) { 482 unsigned R = MakeReg(RegisterVT); 483 if (!FirstReg) FirstReg = R; 484 } 485 } 486 return FirstReg; 487} 488 489//===----------------------------------------------------------------------===// 490/// SelectionDAGLowering - This is the common target-independent lowering 491/// implementation that is parameterized by a TargetLowering object. 492/// Also, targets can overload any lowering method. 493/// 494namespace llvm { 495class SelectionDAGLowering { 496 MachineBasicBlock *CurMBB; 497 498 DenseMap<const Value*, SDValue> NodeMap; 499 500 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 501 /// them up and then emit token factor nodes when possible. This allows us to 502 /// get simple disambiguation between loads without worrying about alias 503 /// analysis. 504 SmallVector<SDValue, 8> PendingLoads; 505 506 /// PendingExports - CopyToReg nodes that copy values to virtual registers 507 /// for export to other blocks need to be emitted before any terminator 508 /// instruction, but they have no other ordering requirements. We bunch them 509 /// up and the emit a single tokenfactor for them just before terminator 510 /// instructions. 511 std::vector<SDValue> PendingExports; 512 513 /// Case - A struct to record the Value for a switch case, and the 514 /// case's target basic block. 515 struct Case { 516 Constant* Low; 517 Constant* High; 518 MachineBasicBlock* BB; 519 520 Case() : Low(0), High(0), BB(0) { } 521 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 522 Low(low), High(high), BB(bb) { } 523 uint64_t size() const { 524 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 525 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 526 return (rHigh - rLow + 1ULL); 527 } 528 }; 529 530 struct CaseBits { 531 uint64_t Mask; 532 MachineBasicBlock* BB; 533 unsigned Bits; 534 535 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 536 Mask(mask), BB(bb), Bits(bits) { } 537 }; 538 539 typedef std::vector<Case> CaseVector; 540 typedef std::vector<CaseBits> CaseBitsVector; 541 typedef CaseVector::iterator CaseItr; 542 typedef std::pair<CaseItr, CaseItr> CaseRange; 543 544 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 545 /// of conditional branches. 546 struct CaseRec { 547 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 548 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 549 550 /// CaseBB - The MBB in which to emit the compare and branch 551 MachineBasicBlock *CaseBB; 552 /// LT, GE - If nonzero, we know the current case value must be less-than or 553 /// greater-than-or-equal-to these Constants. 554 Constant *LT; 555 Constant *GE; 556 /// Range - A pair of iterators representing the range of case values to be 557 /// processed at this point in the binary search tree. 558 CaseRange Range; 559 }; 560 561 typedef std::vector<CaseRec> CaseRecVector; 562 563 /// The comparison function for sorting the switch case values in the vector. 564 /// WARNING: Case ranges should be disjoint! 565 struct CaseCmp { 566 bool operator () (const Case& C1, const Case& C2) { 567 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 568 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 569 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 570 return CI1->getValue().slt(CI2->getValue()); 571 } 572 }; 573 574 struct CaseBitsCmp { 575 bool operator () (const CaseBits& C1, const CaseBits& C2) { 576 return C1.Bits > C2.Bits; 577 } 578 }; 579 580 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 581 582public: 583 // TLI - This is information that describes the available target features we 584 // need for lowering. This indicates when operations are unavailable, 585 // implemented with a libcall, etc. 586 TargetLowering &TLI; 587 SelectionDAG &DAG; 588 const TargetData *TD; 589 AliasAnalysis &AA; 590 591 /// SwitchCases - Vector of CaseBlock structures used to communicate 592 /// SwitchInst code generation information. 593 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 594 /// JTCases - Vector of JumpTable structures used to communicate 595 /// SwitchInst code generation information. 596 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 597 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 598 599 /// FuncInfo - Information about the function as a whole. 600 /// 601 FunctionLoweringInfo &FuncInfo; 602 603 /// GCI - Garbage collection metadata for the function. 604 CollectorMetadata *GCI; 605 606 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 607 AliasAnalysis &aa, 608 FunctionLoweringInfo &funcinfo, 609 CollectorMetadata *gci) 610 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 611 FuncInfo(funcinfo), GCI(gci) { 612 } 613 614 /// getRoot - Return the current virtual root of the Selection DAG, 615 /// flushing any PendingLoad items. This must be done before emitting 616 /// a store or any other node that may need to be ordered after any 617 /// prior load instructions. 618 /// 619 SDValue getRoot() { 620 if (PendingLoads.empty()) 621 return DAG.getRoot(); 622 623 if (PendingLoads.size() == 1) { 624 SDValue Root = PendingLoads[0]; 625 DAG.setRoot(Root); 626 PendingLoads.clear(); 627 return Root; 628 } 629 630 // Otherwise, we have to make a token factor node. 631 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 632 &PendingLoads[0], PendingLoads.size()); 633 PendingLoads.clear(); 634 DAG.setRoot(Root); 635 return Root; 636 } 637 638 /// getControlRoot - Similar to getRoot, but instead of flushing all the 639 /// PendingLoad items, flush all the PendingExports items. It is necessary 640 /// to do this before emitting a terminator instruction. 641 /// 642 SDValue getControlRoot() { 643 SDValue Root = DAG.getRoot(); 644 645 if (PendingExports.empty()) 646 return Root; 647 648 // Turn all of the CopyToReg chains into one factored node. 649 if (Root.getOpcode() != ISD::EntryToken) { 650 unsigned i = 0, e = PendingExports.size(); 651 for (; i != e; ++i) { 652 assert(PendingExports[i].Val->getNumOperands() > 1); 653 if (PendingExports[i].Val->getOperand(0) == Root) 654 break; // Don't add the root if we already indirectly depend on it. 655 } 656 657 if (i == e) 658 PendingExports.push_back(Root); 659 } 660 661 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 662 &PendingExports[0], 663 PendingExports.size()); 664 PendingExports.clear(); 665 DAG.setRoot(Root); 666 return Root; 667 } 668 669 void CopyValueToVirtualRegister(Value *V, unsigned Reg); 670 671 void visit(Instruction &I) { visit(I.getOpcode(), I); } 672 673 void visit(unsigned Opcode, User &I) { 674 // Note: this doesn't use InstVisitor, because it has to work with 675 // ConstantExpr's in addition to instructions. 676 switch (Opcode) { 677 default: assert(0 && "Unknown instruction type encountered!"); 678 abort(); 679 // Build the switch statement using the Instruction.def file. 680#define HANDLE_INST(NUM, OPCODE, CLASS) \ 681 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 682#include "llvm/Instruction.def" 683 } 684 } 685 686 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 687 688 SDValue getValue(const Value *V); 689 690 void setValue(const Value *V, SDValue NewN) { 691 SDValue &N = NodeMap[V]; 692 assert(N.Val == 0 && "Already set a value for this node!"); 693 N = NewN; 694 } 695 696 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 697 std::set<unsigned> &OutputRegs, 698 std::set<unsigned> &InputRegs); 699 700 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 701 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 702 unsigned Opc); 703 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 704 void ExportFromCurrentBlock(Value *V); 705 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall, 706 MachineBasicBlock *LandingPad = NULL); 707 708 // Terminator instructions. 709 void visitRet(ReturnInst &I); 710 void visitBr(BranchInst &I); 711 void visitSwitch(SwitchInst &I); 712 void visitUnreachable(UnreachableInst &I) { /* noop */ } 713 714 // Helpers for visitSwitch 715 bool handleSmallSwitchRange(CaseRec& CR, 716 CaseRecVector& WorkList, 717 Value* SV, 718 MachineBasicBlock* Default); 719 bool handleJTSwitchCase(CaseRec& CR, 720 CaseRecVector& WorkList, 721 Value* SV, 722 MachineBasicBlock* Default); 723 bool handleBTSplitSwitchCase(CaseRec& CR, 724 CaseRecVector& WorkList, 725 Value* SV, 726 MachineBasicBlock* Default); 727 bool handleBitTestsSwitchCase(CaseRec& CR, 728 CaseRecVector& WorkList, 729 Value* SV, 730 MachineBasicBlock* Default); 731 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 732 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 733 void visitBitTestCase(MachineBasicBlock* NextMBB, 734 unsigned Reg, 735 SelectionDAGISel::BitTestCase &B); 736 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 737 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 738 SelectionDAGISel::JumpTableHeader &JTH); 739 740 // These all get lowered before this pass. 741 void visitInvoke(InvokeInst &I); 742 void visitUnwind(UnwindInst &I); 743 744 void visitBinary(User &I, unsigned OpCode); 745 void visitShift(User &I, unsigned Opcode); 746 void visitAdd(User &I) { 747 if (I.getType()->isFPOrFPVector()) 748 visitBinary(I, ISD::FADD); 749 else 750 visitBinary(I, ISD::ADD); 751 } 752 void visitSub(User &I); 753 void visitMul(User &I) { 754 if (I.getType()->isFPOrFPVector()) 755 visitBinary(I, ISD::FMUL); 756 else 757 visitBinary(I, ISD::MUL); 758 } 759 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 760 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 761 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 762 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 763 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 764 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 765 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 766 void visitOr (User &I) { visitBinary(I, ISD::OR); } 767 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 768 void visitShl (User &I) { visitShift(I, ISD::SHL); } 769 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 770 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 771 void visitICmp(User &I); 772 void visitFCmp(User &I); 773 void visitVICmp(User &I); 774 void visitVFCmp(User &I); 775 // Visit the conversion instructions 776 void visitTrunc(User &I); 777 void visitZExt(User &I); 778 void visitSExt(User &I); 779 void visitFPTrunc(User &I); 780 void visitFPExt(User &I); 781 void visitFPToUI(User &I); 782 void visitFPToSI(User &I); 783 void visitUIToFP(User &I); 784 void visitSIToFP(User &I); 785 void visitPtrToInt(User &I); 786 void visitIntToPtr(User &I); 787 void visitBitCast(User &I); 788 789 void visitExtractElement(User &I); 790 void visitInsertElement(User &I); 791 void visitShuffleVector(User &I); 792 793 void visitExtractValue(ExtractValueInst &I); 794 void visitInsertValue(InsertValueInst &I); 795 796 void visitGetElementPtr(User &I); 797 void visitSelect(User &I); 798 799 void visitMalloc(MallocInst &I); 800 void visitFree(FreeInst &I); 801 void visitAlloca(AllocaInst &I); 802 void visitLoad(LoadInst &I); 803 void visitStore(StoreInst &I); 804 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 805 void visitCall(CallInst &I); 806 void visitInlineAsm(CallSite CS); 807 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 808 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 809 810 void visitVAStart(CallInst &I); 811 void visitVAArg(VAArgInst &I); 812 void visitVAEnd(CallInst &I); 813 void visitVACopy(CallInst &I); 814 815 void visitUserOp1(Instruction &I) { 816 assert(0 && "UserOp1 should not exist at instruction selection time!"); 817 abort(); 818 } 819 void visitUserOp2(Instruction &I) { 820 assert(0 && "UserOp2 should not exist at instruction selection time!"); 821 abort(); 822 } 823 824private: 825 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); 826 827}; 828} // end namespace llvm 829 830 831/// getCopyFromParts - Create a value that contains the specified legal parts 832/// combined into the value they represent. If the parts combine to a type 833/// larger then ValueVT then AssertOp can be used to specify whether the extra 834/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 835/// (ISD::AssertSext). 836static SDValue getCopyFromParts(SelectionDAG &DAG, 837 const SDValue *Parts, 838 unsigned NumParts, 839 MVT PartVT, 840 MVT ValueVT, 841 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 842 assert(NumParts > 0 && "No parts to assemble!"); 843 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 844 SDValue Val = Parts[0]; 845 846 if (NumParts > 1) { 847 // Assemble the value from multiple parts. 848 if (!ValueVT.isVector()) { 849 unsigned PartBits = PartVT.getSizeInBits(); 850 unsigned ValueBits = ValueVT.getSizeInBits(); 851 852 // Assemble the power of 2 part. 853 unsigned RoundParts = NumParts & (NumParts - 1) ? 854 1 << Log2_32(NumParts) : NumParts; 855 unsigned RoundBits = PartBits * RoundParts; 856 MVT RoundVT = RoundBits == ValueBits ? 857 ValueVT : MVT::getIntegerVT(RoundBits); 858 SDValue Lo, Hi; 859 860 if (RoundParts > 2) { 861 MVT HalfVT = MVT::getIntegerVT(RoundBits/2); 862 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); 863 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, 864 PartVT, HalfVT); 865 } else { 866 Lo = Parts[0]; 867 Hi = Parts[1]; 868 } 869 if (TLI.isBigEndian()) 870 std::swap(Lo, Hi); 871 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); 872 873 if (RoundParts < NumParts) { 874 // Assemble the trailing non-power-of-2 part. 875 unsigned OddParts = NumParts - RoundParts; 876 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); 877 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); 878 879 // Combine the round and odd parts. 880 Lo = Val; 881 if (TLI.isBigEndian()) 882 std::swap(Lo, Hi); 883 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); 884 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); 885 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, 886 DAG.getConstant(Lo.getValueType().getSizeInBits(), 887 TLI.getShiftAmountTy())); 888 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); 889 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); 890 } 891 } else { 892 // Handle a multi-element vector. 893 MVT IntermediateVT, RegisterVT; 894 unsigned NumIntermediates; 895 unsigned NumRegs = 896 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 897 RegisterVT); 898 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 899 NumParts = NumRegs; // Silence a compiler warning. 900 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 901 assert(RegisterVT == Parts[0].getValueType() && 902 "Part type doesn't match part!"); 903 904 // Assemble the parts into intermediate operands. 905 SmallVector<SDValue, 8> Ops(NumIntermediates); 906 if (NumIntermediates == NumParts) { 907 // If the register was not expanded, truncate or copy the value, 908 // as appropriate. 909 for (unsigned i = 0; i != NumParts; ++i) 910 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 911 PartVT, IntermediateVT); 912 } else if (NumParts > 0) { 913 // If the intermediate type was expanded, build the intermediate operands 914 // from the parts. 915 assert(NumParts % NumIntermediates == 0 && 916 "Must expand into a divisible number of parts!"); 917 unsigned Factor = NumParts / NumIntermediates; 918 for (unsigned i = 0; i != NumIntermediates; ++i) 919 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 920 PartVT, IntermediateVT); 921 } 922 923 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 924 // operands. 925 Val = DAG.getNode(IntermediateVT.isVector() ? 926 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, 927 ValueVT, &Ops[0], NumIntermediates); 928 } 929 } 930 931 // There is now one part, held in Val. Correct it to match ValueVT. 932 PartVT = Val.getValueType(); 933 934 if (PartVT == ValueVT) 935 return Val; 936 937 if (PartVT.isVector()) { 938 assert(ValueVT.isVector() && "Unknown vector conversion!"); 939 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 940 } 941 942 if (ValueVT.isVector()) { 943 assert(ValueVT.getVectorElementType() == PartVT && 944 ValueVT.getVectorNumElements() == 1 && 945 "Only trivial scalar-to-vector conversions should get here!"); 946 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 947 } 948 949 if (PartVT.isInteger() && 950 ValueVT.isInteger()) { 951 if (ValueVT.bitsLT(PartVT)) { 952 // For a truncate, see if we have any information to 953 // indicate whether the truncated bits will always be 954 // zero or sign-extension. 955 if (AssertOp != ISD::DELETED_NODE) 956 Val = DAG.getNode(AssertOp, PartVT, Val, 957 DAG.getValueType(ValueVT)); 958 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 959 } else { 960 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 961 } 962 } 963 964 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 965 if (ValueVT.bitsLT(Val.getValueType())) 966 // FP_ROUND's are always exact here. 967 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, 968 DAG.getIntPtrConstant(1)); 969 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); 970 } 971 972 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 973 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 974 975 assert(0 && "Unknown mismatch!"); 976 return SDValue(); 977} 978 979/// getCopyToParts - Create a series of nodes that contain the specified value 980/// split into legal parts. If the parts contain more bits than Val, then, for 981/// integers, ExtendKind can be used to specify how to generate the extra bits. 982static void getCopyToParts(SelectionDAG &DAG, 983 SDValue Val, 984 SDValue *Parts, 985 unsigned NumParts, 986 MVT PartVT, 987 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 988 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 989 MVT PtrVT = TLI.getPointerTy(); 990 MVT ValueVT = Val.getValueType(); 991 unsigned PartBits = PartVT.getSizeInBits(); 992 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 993 994 if (!NumParts) 995 return; 996 997 if (!ValueVT.isVector()) { 998 if (PartVT == ValueVT) { 999 assert(NumParts == 1 && "No-op copy with multiple parts!"); 1000 Parts[0] = Val; 1001 return; 1002 } 1003 1004 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 1005 // If the parts cover more bits than the value has, promote the value. 1006 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 1007 assert(NumParts == 1 && "Do not know what to promote to!"); 1008 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 1009 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 1010 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1011 Val = DAG.getNode(ExtendKind, ValueVT, Val); 1012 } else { 1013 assert(0 && "Unknown mismatch!"); 1014 } 1015 } else if (PartBits == ValueVT.getSizeInBits()) { 1016 // Different types of the same size. 1017 assert(NumParts == 1 && PartVT != ValueVT); 1018 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1019 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 1020 // If the parts cover less bits than value has, truncate the value. 1021 if (PartVT.isInteger() && ValueVT.isInteger()) { 1022 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1023 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1024 } else { 1025 assert(0 && "Unknown mismatch!"); 1026 } 1027 } 1028 1029 // The value may have changed - recompute ValueVT. 1030 ValueVT = Val.getValueType(); 1031 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 1032 "Failed to tile the value with PartVT!"); 1033 1034 if (NumParts == 1) { 1035 assert(PartVT == ValueVT && "Type conversion failed!"); 1036 Parts[0] = Val; 1037 return; 1038 } 1039 1040 // Expand the value into multiple parts. 1041 if (NumParts & (NumParts - 1)) { 1042 // The number of parts is not a power of 2. Split off and copy the tail. 1043 assert(PartVT.isInteger() && ValueVT.isInteger() && 1044 "Do not know what to expand to!"); 1045 unsigned RoundParts = 1 << Log2_32(NumParts); 1046 unsigned RoundBits = RoundParts * PartBits; 1047 unsigned OddParts = NumParts - RoundParts; 1048 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, 1049 DAG.getConstant(RoundBits, 1050 TLI.getShiftAmountTy())); 1051 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); 1052 if (TLI.isBigEndian()) 1053 // The odd parts were reversed by getCopyToParts - unreverse them. 1054 std::reverse(Parts + RoundParts, Parts + NumParts); 1055 NumParts = RoundParts; 1056 ValueVT = MVT::getIntegerVT(NumParts * PartBits); 1057 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1058 } 1059 1060 // The number of parts is a power of 2. Repeatedly bisect the value using 1061 // EXTRACT_ELEMENT. 1062 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, 1063 MVT::getIntegerVT(ValueVT.getSizeInBits()), 1064 Val); 1065 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 1066 for (unsigned i = 0; i < NumParts; i += StepSize) { 1067 unsigned ThisBits = StepSize * PartBits / 2; 1068 MVT ThisVT = MVT::getIntegerVT (ThisBits); 1069 SDValue &Part0 = Parts[i]; 1070 SDValue &Part1 = Parts[i+StepSize/2]; 1071 1072 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1073 DAG.getConstant(1, PtrVT)); 1074 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, 1075 DAG.getConstant(0, PtrVT)); 1076 1077 if (ThisBits == PartBits && ThisVT != PartVT) { 1078 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0); 1079 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1); 1080 } 1081 } 1082 } 1083 1084 if (TLI.isBigEndian()) 1085 std::reverse(Parts, Parts + NumParts); 1086 1087 return; 1088 } 1089 1090 // Vector ValueVT. 1091 if (NumParts == 1) { 1092 if (PartVT != ValueVT) { 1093 if (PartVT.isVector()) { 1094 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 1095 } else { 1096 assert(ValueVT.getVectorElementType() == PartVT && 1097 ValueVT.getVectorNumElements() == 1 && 1098 "Only trivial vector-to-scalar conversions should get here!"); 1099 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 1100 DAG.getConstant(0, PtrVT)); 1101 } 1102 } 1103 1104 Parts[0] = Val; 1105 return; 1106 } 1107 1108 // Handle a multi-element vector. 1109 MVT IntermediateVT, RegisterVT; 1110 unsigned NumIntermediates; 1111 unsigned NumRegs = 1112 DAG.getTargetLoweringInfo() 1113 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 1114 RegisterVT); 1115 unsigned NumElements = ValueVT.getVectorNumElements(); 1116 1117 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 1118 NumParts = NumRegs; // Silence a compiler warning. 1119 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 1120 1121 // Split the vector into intermediate operands. 1122 SmallVector<SDValue, 8> Ops(NumIntermediates); 1123 for (unsigned i = 0; i != NumIntermediates; ++i) 1124 if (IntermediateVT.isVector()) 1125 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 1126 IntermediateVT, Val, 1127 DAG.getConstant(i * (NumElements / NumIntermediates), 1128 PtrVT)); 1129 else 1130 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 1131 IntermediateVT, Val, 1132 DAG.getConstant(i, PtrVT)); 1133 1134 // Split the intermediate operands into legal parts. 1135 if (NumParts == NumIntermediates) { 1136 // If the register was not expanded, promote or copy the value, 1137 // as appropriate. 1138 for (unsigned i = 0; i != NumParts; ++i) 1139 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 1140 } else if (NumParts > 0) { 1141 // If the intermediate type was expanded, split each the value into 1142 // legal parts. 1143 assert(NumParts % NumIntermediates == 0 && 1144 "Must expand into a divisible number of parts!"); 1145 unsigned Factor = NumParts / NumIntermediates; 1146 for (unsigned i = 0; i != NumIntermediates; ++i) 1147 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 1148 } 1149} 1150 1151 1152SDValue SelectionDAGLowering::getValue(const Value *V) { 1153 SDValue &N = NodeMap[V]; 1154 if (N.Val) return N; 1155 1156 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 1157 MVT VT = TLI.getValueType(V->getType(), true); 1158 1159 if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1160 return N = DAG.getConstant(CI->getValue(), VT); 1161 1162 if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1163 return N = DAG.getGlobalAddress(GV, VT); 1164 1165 if (isa<ConstantPointerNull>(C)) 1166 return N = DAG.getConstant(0, TLI.getPointerTy()); 1167 1168 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1169 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 1170 1171 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) && 1172 !V->getType()->isAggregateType()) 1173 return N = DAG.getNode(ISD::UNDEF, VT); 1174 1175 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1176 visit(CE->getOpcode(), *CE); 1177 SDValue N1 = NodeMap[V]; 1178 assert(N1.Val && "visit didn't populate the ValueMap!"); 1179 return N1; 1180 } 1181 1182 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1183 SmallVector<SDValue, 4> Constants; 1184 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1185 OI != OE; ++OI) { 1186 SDNode *Val = getValue(*OI).Val; 1187 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1188 Constants.push_back(SDValue(Val, i)); 1189 } 1190 return DAG.getMergeValues(&Constants[0], Constants.size()); 1191 } 1192 1193 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) { 1194 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1195 "Unknown struct or array constant!"); 1196 1197 SmallVector<MVT, 4> ValueVTs; 1198 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1199 unsigned NumElts = ValueVTs.size(); 1200 if (NumElts == 0) 1201 return SDValue(); // empty struct 1202 SmallVector<SDValue, 4> Constants(NumElts); 1203 for (unsigned i = 0; i != NumElts; ++i) { 1204 MVT EltVT = ValueVTs[i]; 1205 if (isa<UndefValue>(C)) 1206 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); 1207 else if (EltVT.isFloatingPoint()) 1208 Constants[i] = DAG.getConstantFP(0, EltVT); 1209 else 1210 Constants[i] = DAG.getConstant(0, EltVT); 1211 } 1212 return DAG.getMergeValues(&Constants[0], NumElts); 1213 } 1214 1215 const VectorType *VecTy = cast<VectorType>(V->getType()); 1216 unsigned NumElements = VecTy->getNumElements(); 1217 1218 // Now that we know the number and type of the elements, get that number of 1219 // elements into the Ops array based on what kind of constant it is. 1220 SmallVector<SDValue, 16> Ops; 1221 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1222 for (unsigned i = 0; i != NumElements; ++i) 1223 Ops.push_back(getValue(CP->getOperand(i))); 1224 } else { 1225 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1226 "Unknown vector constant!"); 1227 MVT EltVT = TLI.getValueType(VecTy->getElementType()); 1228 1229 SDValue Op; 1230 if (isa<UndefValue>(C)) 1231 Op = DAG.getNode(ISD::UNDEF, EltVT); 1232 else if (EltVT.isFloatingPoint()) 1233 Op = DAG.getConstantFP(0, EltVT); 1234 else 1235 Op = DAG.getConstant(0, EltVT); 1236 Ops.assign(NumElements, Op); 1237 } 1238 1239 // Create a BUILD_VECTOR node. 1240 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1241 } 1242 1243 // If this is a static alloca, generate it as the frameindex instead of 1244 // computation. 1245 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1246 std::map<const AllocaInst*, int>::iterator SI = 1247 FuncInfo.StaticAllocaMap.find(AI); 1248 if (SI != FuncInfo.StaticAllocaMap.end()) 1249 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1250 } 1251 1252 unsigned InReg = FuncInfo.ValueMap[V]; 1253 assert(InReg && "Value not in map!"); 1254 1255 RegsForValue RFV(TLI, InReg, V->getType()); 1256 SDValue Chain = DAG.getEntryNode(); 1257 return RFV.getCopyFromRegs(DAG, Chain, NULL); 1258} 1259 1260 1261void SelectionDAGLowering::visitRet(ReturnInst &I) { 1262 if (I.getNumOperands() == 0) { 1263 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot())); 1264 return; 1265 } 1266 1267 SmallVector<SDValue, 8> NewValues; 1268 NewValues.push_back(getControlRoot()); 1269 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 1270 SDValue RetOp = getValue(I.getOperand(i)); 1271 1272 SmallVector<MVT, 4> ValueVTs; 1273 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs); 1274 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) { 1275 MVT VT = ValueVTs[j]; 1276 1277 // FIXME: C calling convention requires the return type to be promoted to 1278 // at least 32-bit. But this is not necessary for non-C calling conventions. 1279 if (VT.isInteger()) { 1280 MVT MinVT = TLI.getRegisterType(MVT::i32); 1281 if (VT.bitsLT(MinVT)) 1282 VT = MinVT; 1283 } 1284 1285 unsigned NumParts = TLI.getNumRegisters(VT); 1286 MVT PartVT = TLI.getRegisterType(VT); 1287 SmallVector<SDValue, 4> Parts(NumParts); 1288 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1289 1290 const Function *F = I.getParent()->getParent(); 1291 if (F->paramHasAttr(0, ParamAttr::SExt)) 1292 ExtendKind = ISD::SIGN_EXTEND; 1293 else if (F->paramHasAttr(0, ParamAttr::ZExt)) 1294 ExtendKind = ISD::ZERO_EXTEND; 1295 1296 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j), 1297 &Parts[0], NumParts, PartVT, ExtendKind); 1298 1299 for (unsigned i = 0; i < NumParts; ++i) { 1300 NewValues.push_back(Parts[i]); 1301 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy())); 1302 } 1303 } 1304 } 1305 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 1306 &NewValues[0], NewValues.size())); 1307} 1308 1309/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1310/// the current basic block, add it to ValueMap now so that we'll get a 1311/// CopyTo/FromReg. 1312void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 1313 // No need to export constants. 1314 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1315 1316 // Already exported? 1317 if (FuncInfo.isExportedInst(V)) return; 1318 1319 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1320 CopyValueToVirtualRegister(V, Reg); 1321} 1322 1323bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 1324 const BasicBlock *FromBB) { 1325 // The operands of the setcc have to be in this block. We don't know 1326 // how to export them from some other block. 1327 if (Instruction *VI = dyn_cast<Instruction>(V)) { 1328 // Can export from current BB. 1329 if (VI->getParent() == FromBB) 1330 return true; 1331 1332 // Is already exported, noop. 1333 return FuncInfo.isExportedInst(V); 1334 } 1335 1336 // If this is an argument, we can export it if the BB is the entry block or 1337 // if it is already exported. 1338 if (isa<Argument>(V)) { 1339 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1340 return true; 1341 1342 // Otherwise, can only export this if it is already exported. 1343 return FuncInfo.isExportedInst(V); 1344 } 1345 1346 // Otherwise, constants can always be exported. 1347 return true; 1348} 1349 1350static bool InBlock(const Value *V, const BasicBlock *BB) { 1351 if (const Instruction *I = dyn_cast<Instruction>(V)) 1352 return I->getParent() == BB; 1353 return true; 1354} 1355 1356/// FindMergedConditions - If Cond is an expression like 1357void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1358 MachineBasicBlock *TBB, 1359 MachineBasicBlock *FBB, 1360 MachineBasicBlock *CurBB, 1361 unsigned Opc) { 1362 // If this node is not part of the or/and tree, emit it as a branch. 1363 Instruction *BOp = dyn_cast<Instruction>(Cond); 1364 1365 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1366 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1367 BOp->getParent() != CurBB->getBasicBlock() || 1368 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1369 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1370 const BasicBlock *BB = CurBB->getBasicBlock(); 1371 1372 // If the leaf of the tree is a comparison, merge the condition into 1373 // the caseblock. 1374 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1375 // The operands of the cmp have to be in this block. We don't know 1376 // how to export them from some other block. If this is the first block 1377 // of the sequence, no exporting is needed. 1378 (CurBB == CurMBB || 1379 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1380 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1381 BOp = cast<Instruction>(Cond); 1382 ISD::CondCode Condition; 1383 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1384 switch (IC->getPredicate()) { 1385 default: assert(0 && "Unknown icmp predicate opcode!"); 1386 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1387 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1388 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1389 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1390 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1391 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1392 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1393 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1394 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1395 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1396 } 1397 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1398 ISD::CondCode FPC, FOC; 1399 switch (FC->getPredicate()) { 1400 default: assert(0 && "Unknown fcmp predicate opcode!"); 1401 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1402 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1403 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1404 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1405 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1406 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1407 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1408 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 1409 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 1410 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1411 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1412 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1413 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1414 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1415 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1416 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1417 } 1418 if (FiniteOnlyFPMath()) 1419 Condition = FOC; 1420 else 1421 Condition = FPC; 1422 } else { 1423 Condition = ISD::SETEQ; // silence warning. 1424 assert(0 && "Unknown compare instruction"); 1425 } 1426 1427 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1428 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1429 SwitchCases.push_back(CB); 1430 return; 1431 } 1432 1433 // Create a CaseBlock record representing this branch. 1434 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1435 NULL, TBB, FBB, CurBB); 1436 SwitchCases.push_back(CB); 1437 return; 1438 } 1439 1440 1441 // Create TmpBB after CurBB. 1442 MachineFunction::iterator BBI = CurBB; 1443 MachineFunction &MF = DAG.getMachineFunction(); 1444 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1445 CurBB->getParent()->insert(++BBI, TmpBB); 1446 1447 if (Opc == Instruction::Or) { 1448 // Codegen X | Y as: 1449 // jmp_if_X TBB 1450 // jmp TmpBB 1451 // TmpBB: 1452 // jmp_if_Y TBB 1453 // jmp FBB 1454 // 1455 1456 // Emit the LHS condition. 1457 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1458 1459 // Emit the RHS condition into TmpBB. 1460 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1461 } else { 1462 assert(Opc == Instruction::And && "Unknown merge op!"); 1463 // Codegen X & Y as: 1464 // jmp_if_X TmpBB 1465 // jmp FBB 1466 // TmpBB: 1467 // jmp_if_Y TBB 1468 // jmp FBB 1469 // 1470 // This requires creation of TmpBB after CurBB. 1471 1472 // Emit the LHS condition. 1473 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1474 1475 // Emit the RHS condition into TmpBB. 1476 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1477 } 1478} 1479 1480/// If the set of cases should be emitted as a series of branches, return true. 1481/// If we should emit this as a bunch of and/or'd together conditions, return 1482/// false. 1483static bool 1484ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1485 if (Cases.size() != 2) return true; 1486 1487 // If this is two comparisons of the same values or'd or and'd together, they 1488 // will get folded into a single comparison, so don't emit two blocks. 1489 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1490 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1491 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1492 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1493 return false; 1494 } 1495 1496 return true; 1497} 1498 1499void SelectionDAGLowering::visitBr(BranchInst &I) { 1500 // Update machine-CFG edges. 1501 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1502 1503 // Figure out which block is immediately after the current one. 1504 MachineBasicBlock *NextBlock = 0; 1505 MachineFunction::iterator BBI = CurMBB; 1506 if (++BBI != CurMBB->getParent()->end()) 1507 NextBlock = BBI; 1508 1509 if (I.isUnconditional()) { 1510 // Update machine-CFG edges. 1511 CurMBB->addSuccessor(Succ0MBB); 1512 1513 // If this is not a fall-through branch, emit the branch. 1514 if (Succ0MBB != NextBlock) 1515 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1516 DAG.getBasicBlock(Succ0MBB))); 1517 return; 1518 } 1519 1520 // If this condition is one of the special cases we handle, do special stuff 1521 // now. 1522 Value *CondVal = I.getCondition(); 1523 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1524 1525 // If this is a series of conditions that are or'd or and'd together, emit 1526 // this as a sequence of branches instead of setcc's with and/or operations. 1527 // For example, instead of something like: 1528 // cmp A, B 1529 // C = seteq 1530 // cmp D, E 1531 // F = setle 1532 // or C, F 1533 // jnz foo 1534 // Emit: 1535 // cmp A, B 1536 // je foo 1537 // cmp D, E 1538 // jle foo 1539 // 1540 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1541 if (BOp->hasOneUse() && 1542 (BOp->getOpcode() == Instruction::And || 1543 BOp->getOpcode() == Instruction::Or)) { 1544 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1545 // If the compares in later blocks need to use values not currently 1546 // exported from this block, export them now. This block should always 1547 // be the first entry. 1548 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1549 1550 // Allow some cases to be rejected. 1551 if (ShouldEmitAsBranches(SwitchCases)) { 1552 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1553 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1554 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1555 } 1556 1557 // Emit the branch for this block. 1558 visitSwitchCase(SwitchCases[0]); 1559 SwitchCases.erase(SwitchCases.begin()); 1560 return; 1561 } 1562 1563 // Okay, we decided not to do this, remove any inserted MBB's and clear 1564 // SwitchCases. 1565 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1566 CurMBB->getParent()->erase(SwitchCases[i].ThisBB); 1567 1568 SwitchCases.clear(); 1569 } 1570 } 1571 1572 // Create a CaseBlock record representing this branch. 1573 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1574 NULL, Succ0MBB, Succ1MBB, CurMBB); 1575 // Use visitSwitchCase to actually insert the fast branch sequence for this 1576 // cond branch. 1577 visitSwitchCase(CB); 1578} 1579 1580/// visitSwitchCase - Emits the necessary code to represent a single node in 1581/// the binary search tree resulting from lowering a switch instruction. 1582void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1583 SDValue Cond; 1584 SDValue CondLHS = getValue(CB.CmpLHS); 1585 1586 // Build the setcc now. 1587 if (CB.CmpMHS == NULL) { 1588 // Fold "(X == true)" to X and "(X == false)" to !X to 1589 // handle common cases produced by branch lowering. 1590 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1591 Cond = CondLHS; 1592 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1593 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1594 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1595 } else 1596 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1597 } else { 1598 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1599 1600 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1601 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1602 1603 SDValue CmpOp = getValue(CB.CmpMHS); 1604 MVT VT = CmpOp.getValueType(); 1605 1606 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1607 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1608 } else { 1609 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1610 Cond = DAG.getSetCC(MVT::i1, SUB, 1611 DAG.getConstant(High-Low, VT), ISD::SETULE); 1612 } 1613 } 1614 1615 // Update successor info 1616 CurMBB->addSuccessor(CB.TrueBB); 1617 CurMBB->addSuccessor(CB.FalseBB); 1618 1619 // Set NextBlock to be the MBB immediately after the current one, if any. 1620 // This is used to avoid emitting unnecessary branches to the next block. 1621 MachineBasicBlock *NextBlock = 0; 1622 MachineFunction::iterator BBI = CurMBB; 1623 if (++BBI != CurMBB->getParent()->end()) 1624 NextBlock = BBI; 1625 1626 // If the lhs block is the next block, invert the condition so that we can 1627 // fall through to the lhs instead of the rhs block. 1628 if (CB.TrueBB == NextBlock) { 1629 std::swap(CB.TrueBB, CB.FalseBB); 1630 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1631 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1632 } 1633 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond, 1634 DAG.getBasicBlock(CB.TrueBB)); 1635 1636 // If the branch was constant folded, fix up the CFG. 1637 if (BrCond.getOpcode() == ISD::BR) { 1638 if (!DisableCorrectBranchFolding) 1639 CurMBB->removeSuccessor(CB.FalseBB); 1640 DAG.setRoot(BrCond); 1641 } else { 1642 // Otherwise, go ahead and insert the false branch. 1643 if (BrCond == getControlRoot()) 1644 if (!DisableCorrectBranchFolding) 1645 CurMBB->removeSuccessor(CB.TrueBB); 1646 1647 if (CB.FalseBB == NextBlock) 1648 DAG.setRoot(BrCond); 1649 else 1650 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1651 DAG.getBasicBlock(CB.FalseBB))); 1652 } 1653} 1654 1655/// visitJumpTable - Emit JumpTable node in the current MBB 1656void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1657 // Emit the code for the jump table 1658 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1659 MVT PTy = TLI.getPointerTy(); 1660 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); 1661 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1662 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1663 Table, Index)); 1664 return; 1665} 1666 1667/// visitJumpTableHeader - This function emits necessary code to produce index 1668/// in the JumpTable from switch case. 1669void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1670 SelectionDAGISel::JumpTableHeader &JTH) { 1671 // Subtract the lowest switch case value from the value being switched on 1672 // and conditional branch to default mbb if the result is greater than the 1673 // difference between smallest and largest cases. 1674 SDValue SwitchOp = getValue(JTH.SValue); 1675 MVT VT = SwitchOp.getValueType(); 1676 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1677 DAG.getConstant(JTH.First, VT)); 1678 1679 // The SDNode we just created, which holds the value being switched on 1680 // minus the the smallest case value, needs to be copied to a virtual 1681 // register so it can be used as an index into the jump table in a 1682 // subsequent basic block. This value may be smaller or larger than the 1683 // target's pointer type, and therefore require extension or truncating. 1684 if (VT.bitsGT(TLI.getPointerTy())) 1685 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1686 else 1687 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1688 1689 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1690 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); 1691 JT.Reg = JumpTableReg; 1692 1693 // Emit the range check for the jump table, and branch to the default 1694 // block for the switch statement if the value being switched on exceeds 1695 // the largest case in the switch. 1696 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1697 DAG.getConstant(JTH.Last-JTH.First,VT), 1698 ISD::SETUGT); 1699 1700 // Set NextBlock to be the MBB immediately after the current one, if any. 1701 // This is used to avoid emitting unnecessary branches to the next block. 1702 MachineBasicBlock *NextBlock = 0; 1703 MachineFunction::iterator BBI = CurMBB; 1704 if (++BBI != CurMBB->getParent()->end()) 1705 NextBlock = BBI; 1706 1707 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1708 DAG.getBasicBlock(JT.Default)); 1709 1710 if (JT.MBB == NextBlock) 1711 DAG.setRoot(BrCond); 1712 else 1713 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1714 DAG.getBasicBlock(JT.MBB))); 1715 1716 return; 1717} 1718 1719/// visitBitTestHeader - This function emits necessary code to produce value 1720/// suitable for "bit tests" 1721void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1722 // Subtract the minimum value 1723 SDValue SwitchOp = getValue(B.SValue); 1724 MVT VT = SwitchOp.getValueType(); 1725 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1726 DAG.getConstant(B.First, VT)); 1727 1728 // Check range 1729 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, 1730 DAG.getConstant(B.Range, VT), 1731 ISD::SETUGT); 1732 1733 SDValue ShiftOp; 1734 if (VT.bitsGT(TLI.getShiftAmountTy())) 1735 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1736 else 1737 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1738 1739 // Make desired shift 1740 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1741 DAG.getConstant(1, TLI.getPointerTy()), 1742 ShiftOp); 1743 1744 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1745 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); 1746 B.Reg = SwitchReg; 1747 1748 // Set NextBlock to be the MBB immediately after the current one, if any. 1749 // This is used to avoid emitting unnecessary branches to the next block. 1750 MachineBasicBlock *NextBlock = 0; 1751 MachineFunction::iterator BBI = CurMBB; 1752 if (++BBI != CurMBB->getParent()->end()) 1753 NextBlock = BBI; 1754 1755 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1756 1757 CurMBB->addSuccessor(B.Default); 1758 CurMBB->addSuccessor(MBB); 1759 1760 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1761 DAG.getBasicBlock(B.Default)); 1762 1763 if (MBB == NextBlock) 1764 DAG.setRoot(BrRange); 1765 else 1766 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1767 DAG.getBasicBlock(MBB))); 1768 1769 return; 1770} 1771 1772/// visitBitTestCase - this function produces one "bit test" 1773void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1774 unsigned Reg, 1775 SelectionDAGISel::BitTestCase &B) { 1776 // Emit bit tests and jumps 1777 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, 1778 TLI.getPointerTy()); 1779 1780 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, 1781 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1782 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, 1783 DAG.getConstant(0, TLI.getPointerTy()), 1784 ISD::SETNE); 1785 1786 CurMBB->addSuccessor(B.TargetBB); 1787 CurMBB->addSuccessor(NextMBB); 1788 1789 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), 1790 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1791 1792 // Set NextBlock to be the MBB immediately after the current one, if any. 1793 // This is used to avoid emitting unnecessary branches to the next block. 1794 MachineBasicBlock *NextBlock = 0; 1795 MachineFunction::iterator BBI = CurMBB; 1796 if (++BBI != CurMBB->getParent()->end()) 1797 NextBlock = BBI; 1798 1799 if (NextMBB == NextBlock) 1800 DAG.setRoot(BrAnd); 1801 else 1802 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1803 DAG.getBasicBlock(NextMBB))); 1804 1805 return; 1806} 1807 1808void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1809 // Retrieve successors. 1810 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1811 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1812 1813 if (isa<InlineAsm>(I.getCalledValue())) 1814 visitInlineAsm(&I); 1815 else 1816 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); 1817 1818 // If the value of the invoke is used outside of its defining block, make it 1819 // available as a virtual register. 1820 if (!I.use_empty()) { 1821 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1822 if (VMI != FuncInfo.ValueMap.end()) 1823 CopyValueToVirtualRegister(&I, VMI->second); 1824 } 1825 1826 // Update successor info 1827 CurMBB->addSuccessor(Return); 1828 CurMBB->addSuccessor(LandingPad); 1829 1830 // Drop into normal successor. 1831 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 1832 DAG.getBasicBlock(Return))); 1833} 1834 1835void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1836} 1837 1838/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1839/// small case ranges). 1840bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1841 CaseRecVector& WorkList, 1842 Value* SV, 1843 MachineBasicBlock* Default) { 1844 Case& BackCase = *(CR.Range.second-1); 1845 1846 // Size is the number of Cases represented by this range. 1847 unsigned Size = CR.Range.second - CR.Range.first; 1848 if (Size > 3) 1849 return false; 1850 1851 // Get the MachineFunction which holds the current MBB. This is used when 1852 // inserting any additional MBBs necessary to represent the switch. 1853 MachineFunction *CurMF = CurMBB->getParent(); 1854 1855 // Figure out which block is immediately after the current one. 1856 MachineBasicBlock *NextBlock = 0; 1857 MachineFunction::iterator BBI = CR.CaseBB; 1858 1859 if (++BBI != CurMBB->getParent()->end()) 1860 NextBlock = BBI; 1861 1862 // TODO: If any two of the cases has the same destination, and if one value 1863 // is the same as the other, but has one bit unset that the other has set, 1864 // use bit manipulation to do two compares at once. For example: 1865 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1866 1867 // Rearrange the case blocks so that the last one falls through if possible. 1868 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1869 // The last case block won't fall through into 'NextBlock' if we emit the 1870 // branches in this order. See if rearranging a case value would help. 1871 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1872 if (I->BB == NextBlock) { 1873 std::swap(*I, BackCase); 1874 break; 1875 } 1876 } 1877 } 1878 1879 // Create a CaseBlock record representing a conditional branch to 1880 // the Case's target mbb if the value being switched on SV is equal 1881 // to C. 1882 MachineBasicBlock *CurBlock = CR.CaseBB; 1883 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1884 MachineBasicBlock *FallThrough; 1885 if (I != E-1) { 1886 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1887 CurMF->insert(BBI, FallThrough); 1888 } else { 1889 // If the last case doesn't match, go to the default block. 1890 FallThrough = Default; 1891 } 1892 1893 Value *RHS, *LHS, *MHS; 1894 ISD::CondCode CC; 1895 if (I->High == I->Low) { 1896 // This is just small small case range :) containing exactly 1 case 1897 CC = ISD::SETEQ; 1898 LHS = SV; RHS = I->High; MHS = NULL; 1899 } else { 1900 CC = ISD::SETLE; 1901 LHS = I->Low; MHS = SV; RHS = I->High; 1902 } 1903 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1904 I->BB, FallThrough, CurBlock); 1905 1906 // If emitting the first comparison, just call visitSwitchCase to emit the 1907 // code into the current block. Otherwise, push the CaseBlock onto the 1908 // vector to be later processed by SDISel, and insert the node's MBB 1909 // before the next MBB. 1910 if (CurBlock == CurMBB) 1911 visitSwitchCase(CB); 1912 else 1913 SwitchCases.push_back(CB); 1914 1915 CurBlock = FallThrough; 1916 } 1917 1918 return true; 1919} 1920 1921static inline bool areJTsAllowed(const TargetLowering &TLI) { 1922 return !DisableJumpTables && 1923 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1924 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1925} 1926 1927/// handleJTSwitchCase - Emit jumptable for current switch case range 1928bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1929 CaseRecVector& WorkList, 1930 Value* SV, 1931 MachineBasicBlock* Default) { 1932 Case& FrontCase = *CR.Range.first; 1933 Case& BackCase = *(CR.Range.second-1); 1934 1935 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1936 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1937 1938 uint64_t TSize = 0; 1939 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1940 I!=E; ++I) 1941 TSize += I->size(); 1942 1943 if (!areJTsAllowed(TLI) || TSize <= 3) 1944 return false; 1945 1946 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1947 if (Density < 0.4) 1948 return false; 1949 1950 DOUT << "Lowering jump table\n" 1951 << "First entry: " << First << ". Last entry: " << Last << "\n" 1952 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1953 1954 // Get the MachineFunction which holds the current MBB. This is used when 1955 // inserting any additional MBBs necessary to represent the switch. 1956 MachineFunction *CurMF = CurMBB->getParent(); 1957 1958 // Figure out which block is immediately after the current one. 1959 MachineBasicBlock *NextBlock = 0; 1960 MachineFunction::iterator BBI = CR.CaseBB; 1961 1962 if (++BBI != CurMBB->getParent()->end()) 1963 NextBlock = BBI; 1964 1965 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1966 1967 // Create a new basic block to hold the code for loading the address 1968 // of the jump table, and jumping to it. Update successor information; 1969 // we will either branch to the default case for the switch, or the jump 1970 // table. 1971 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1972 CurMF->insert(BBI, JumpTableBB); 1973 CR.CaseBB->addSuccessor(Default); 1974 CR.CaseBB->addSuccessor(JumpTableBB); 1975 1976 // Build a vector of destination BBs, corresponding to each target 1977 // of the jump table. If the value of the jump table slot corresponds to 1978 // a case statement, push the case's BB onto the vector, otherwise, push 1979 // the default BB. 1980 std::vector<MachineBasicBlock*> DestBBs; 1981 int64_t TEI = First; 1982 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1983 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1984 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1985 1986 if ((Low <= TEI) && (TEI <= High)) { 1987 DestBBs.push_back(I->BB); 1988 if (TEI==High) 1989 ++I; 1990 } else { 1991 DestBBs.push_back(Default); 1992 } 1993 } 1994 1995 // Update successor info. Add one edge to each unique successor. 1996 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1997 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1998 E = DestBBs.end(); I != E; ++I) { 1999 if (!SuccsHandled[(*I)->getNumber()]) { 2000 SuccsHandled[(*I)->getNumber()] = true; 2001 JumpTableBB->addSuccessor(*I); 2002 } 2003 } 2004 2005 // Create a jump table index for this jump table, or return an existing 2006 // one. 2007 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 2008 2009 // Set the jump table information so that we can codegen it as a second 2010 // MachineBasicBlock 2011 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 2012 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 2013 (CR.CaseBB == CurMBB)); 2014 if (CR.CaseBB == CurMBB) 2015 visitJumpTableHeader(JT, JTH); 2016 2017 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 2018 2019 return true; 2020} 2021 2022/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2023/// 2 subtrees. 2024bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 2025 CaseRecVector& WorkList, 2026 Value* SV, 2027 MachineBasicBlock* Default) { 2028 // Get the MachineFunction which holds the current MBB. This is used when 2029 // inserting any additional MBBs necessary to represent the switch. 2030 MachineFunction *CurMF = CurMBB->getParent(); 2031 2032 // Figure out which block is immediately after the current one. 2033 MachineBasicBlock *NextBlock = 0; 2034 MachineFunction::iterator BBI = CR.CaseBB; 2035 2036 if (++BBI != CurMBB->getParent()->end()) 2037 NextBlock = BBI; 2038 2039 Case& FrontCase = *CR.Range.first; 2040 Case& BackCase = *(CR.Range.second-1); 2041 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2042 2043 // Size is the number of Cases represented by this range. 2044 unsigned Size = CR.Range.second - CR.Range.first; 2045 2046 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 2047 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 2048 double FMetric = 0; 2049 CaseItr Pivot = CR.Range.first + Size/2; 2050 2051 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2052 // (heuristically) allow us to emit JumpTable's later. 2053 uint64_t TSize = 0; 2054 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2055 I!=E; ++I) 2056 TSize += I->size(); 2057 2058 uint64_t LSize = FrontCase.size(); 2059 uint64_t RSize = TSize-LSize; 2060 DOUT << "Selecting best pivot: \n" 2061 << "First: " << First << ", Last: " << Last <<"\n" 2062 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 2063 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2064 J!=E; ++I, ++J) { 2065 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 2066 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 2067 assert((RBegin-LEnd>=1) && "Invalid case distance"); 2068 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 2069 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 2070 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 2071 // Should always split in some non-trivial place 2072 DOUT <<"=>Step\n" 2073 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 2074 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 2075 << "Metric: " << Metric << "\n"; 2076 if (FMetric < Metric) { 2077 Pivot = J; 2078 FMetric = Metric; 2079 DOUT << "Current metric set to: " << FMetric << "\n"; 2080 } 2081 2082 LSize += J->size(); 2083 RSize -= J->size(); 2084 } 2085 if (areJTsAllowed(TLI)) { 2086 // If our case is dense we *really* should handle it earlier! 2087 assert((FMetric > 0) && "Should handle dense range earlier!"); 2088 } else { 2089 Pivot = CR.Range.first + Size/2; 2090 } 2091 2092 CaseRange LHSR(CR.Range.first, Pivot); 2093 CaseRange RHSR(Pivot, CR.Range.second); 2094 Constant *C = Pivot->Low; 2095 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2096 2097 // We know that we branch to the LHS if the Value being switched on is 2098 // less than the Pivot value, C. We use this to optimize our binary 2099 // tree a bit, by recognizing that if SV is greater than or equal to the 2100 // LHS's Case Value, and that Case Value is exactly one less than the 2101 // Pivot's Value, then we can branch directly to the LHS's Target, 2102 // rather than creating a leaf node for it. 2103 if ((LHSR.second - LHSR.first) == 1 && 2104 LHSR.first->High == CR.GE && 2105 cast<ConstantInt>(C)->getSExtValue() == 2106 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 2107 TrueBB = LHSR.first->BB; 2108 } else { 2109 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2110 CurMF->insert(BBI, TrueBB); 2111 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2112 } 2113 2114 // Similar to the optimization above, if the Value being switched on is 2115 // known to be less than the Constant CR.LT, and the current Case Value 2116 // is CR.LT - 1, then we can branch directly to the target block for 2117 // the current Case Value, rather than emitting a RHS leaf node for it. 2118 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2119 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 2120 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 2121 FalseBB = RHSR.first->BB; 2122 } else { 2123 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2124 CurMF->insert(BBI, FalseBB); 2125 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2126 } 2127 2128 // Create a CaseBlock record representing a conditional branch to 2129 // the LHS node if the value being switched on SV is less than C. 2130 // Otherwise, branch to LHS. 2131 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 2132 TrueBB, FalseBB, CR.CaseBB); 2133 2134 if (CR.CaseBB == CurMBB) 2135 visitSwitchCase(CB); 2136 else 2137 SwitchCases.push_back(CB); 2138 2139 return true; 2140} 2141 2142/// handleBitTestsSwitchCase - if current case range has few destination and 2143/// range span less, than machine word bitwidth, encode case range into series 2144/// of masks and emit bit tests with these masks. 2145bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 2146 CaseRecVector& WorkList, 2147 Value* SV, 2148 MachineBasicBlock* Default){ 2149 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits(); 2150 2151 Case& FrontCase = *CR.Range.first; 2152 Case& BackCase = *(CR.Range.second-1); 2153 2154 // Get the MachineFunction which holds the current MBB. This is used when 2155 // inserting any additional MBBs necessary to represent the switch. 2156 MachineFunction *CurMF = CurMBB->getParent(); 2157 2158 unsigned numCmps = 0; 2159 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2160 I!=E; ++I) { 2161 // Single case counts one, case range - two. 2162 if (I->Low == I->High) 2163 numCmps +=1; 2164 else 2165 numCmps +=2; 2166 } 2167 2168 // Count unique destinations 2169 SmallSet<MachineBasicBlock*, 4> Dests; 2170 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2171 Dests.insert(I->BB); 2172 if (Dests.size() > 3) 2173 // Don't bother the code below, if there are too much unique destinations 2174 return false; 2175 } 2176 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 2177 << "Total number of comparisons: " << numCmps << "\n"; 2178 2179 // Compute span of values. 2180 Constant* minValue = FrontCase.Low; 2181 Constant* maxValue = BackCase.High; 2182 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 2183 cast<ConstantInt>(minValue)->getSExtValue(); 2184 DOUT << "Compare range: " << range << "\n" 2185 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 2186 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 2187 2188 if (range>=IntPtrBits || 2189 (!(Dests.size() == 1 && numCmps >= 3) && 2190 !(Dests.size() == 2 && numCmps >= 5) && 2191 !(Dests.size() >= 3 && numCmps >= 6))) 2192 return false; 2193 2194 DOUT << "Emitting bit tests\n"; 2195 int64_t lowBound = 0; 2196 2197 // Optimize the case where all the case values fit in a 2198 // word without having to subtract minValue. In this case, 2199 // we can optimize away the subtraction. 2200 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 2201 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 2202 range = cast<ConstantInt>(maxValue)->getSExtValue(); 2203 } else { 2204 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 2205 } 2206 2207 CaseBitsVector CasesBits; 2208 unsigned i, count = 0; 2209 2210 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2211 MachineBasicBlock* Dest = I->BB; 2212 for (i = 0; i < count; ++i) 2213 if (Dest == CasesBits[i].BB) 2214 break; 2215 2216 if (i == count) { 2217 assert((count < 3) && "Too much destinations to test!"); 2218 CasesBits.push_back(CaseBits(0, Dest, 0)); 2219 count++; 2220 } 2221 2222 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 2223 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 2224 2225 for (uint64_t j = lo; j <= hi; j++) { 2226 CasesBits[i].Mask |= 1ULL << j; 2227 CasesBits[i].Bits++; 2228 } 2229 2230 } 2231 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2232 2233 SelectionDAGISel::BitTestInfo BTC; 2234 2235 // Figure out which block is immediately after the current one. 2236 MachineFunction::iterator BBI = CR.CaseBB; 2237 ++BBI; 2238 2239 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2240 2241 DOUT << "Cases:\n"; 2242 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2243 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 2244 << ", BB: " << CasesBits[i].BB << "\n"; 2245 2246 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2247 CurMF->insert(BBI, CaseBB); 2248 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 2249 CaseBB, 2250 CasesBits[i].BB)); 2251 } 2252 2253 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 2254 -1U, (CR.CaseBB == CurMBB), 2255 CR.CaseBB, Default, BTC); 2256 2257 if (CR.CaseBB == CurMBB) 2258 visitBitTestHeader(BTB); 2259 2260 BitTestCases.push_back(BTB); 2261 2262 return true; 2263} 2264 2265 2266/// Clusterify - Transform simple list of Cases into list of CaseRange's 2267unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 2268 const SwitchInst& SI) { 2269 unsigned numCmps = 0; 2270 2271 // Start with "simple" cases 2272 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 2273 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2274 Cases.push_back(Case(SI.getSuccessorValue(i), 2275 SI.getSuccessorValue(i), 2276 SMBB)); 2277 } 2278 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2279 2280 // Merge case into clusters 2281 if (Cases.size()>=2) 2282 // Must recompute end() each iteration because it may be 2283 // invalidated by erase if we hold on to it 2284 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 2285 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 2286 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 2287 MachineBasicBlock* nextBB = J->BB; 2288 MachineBasicBlock* currentBB = I->BB; 2289 2290 // If the two neighboring cases go to the same destination, merge them 2291 // into a single case. 2292 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 2293 I->High = J->High; 2294 J = Cases.erase(J); 2295 } else { 2296 I = J++; 2297 } 2298 } 2299 2300 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2301 if (I->Low != I->High) 2302 // A range counts double, since it requires two compares. 2303 ++numCmps; 2304 } 2305 2306 return numCmps; 2307} 2308 2309void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 2310 // Figure out which block is immediately after the current one. 2311 MachineBasicBlock *NextBlock = 0; 2312 MachineFunction::iterator BBI = CurMBB; 2313 2314 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2315 2316 // If there is only the default destination, branch to it if it is not the 2317 // next basic block. Otherwise, just fall through. 2318 if (SI.getNumOperands() == 2) { 2319 // Update machine-CFG edges. 2320 2321 // If this is not a fall-through branch, emit the branch. 2322 CurMBB->addSuccessor(Default); 2323 if (Default != NextBlock) 2324 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), 2325 DAG.getBasicBlock(Default))); 2326 2327 return; 2328 } 2329 2330 // If there are any non-default case statements, create a vector of Cases 2331 // representing each one, and sort the vector so that we can efficiently 2332 // create a binary search tree from them. 2333 CaseVector Cases; 2334 unsigned numCmps = Clusterify(Cases, SI); 2335 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 2336 << ". Total compares: " << numCmps << "\n"; 2337 2338 // Get the Value to be switched on and default basic blocks, which will be 2339 // inserted into CaseBlock records, representing basic blocks in the binary 2340 // search tree. 2341 Value *SV = SI.getOperand(0); 2342 2343 // Push the initial CaseRec onto the worklist 2344 CaseRecVector WorkList; 2345 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 2346 2347 while (!WorkList.empty()) { 2348 // Grab a record representing a case range to process off the worklist 2349 CaseRec CR = WorkList.back(); 2350 WorkList.pop_back(); 2351 2352 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 2353 continue; 2354 2355 // If the range has few cases (two or less) emit a series of specific 2356 // tests. 2357 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2358 continue; 2359 2360 // If the switch has more than 5 blocks, and at least 40% dense, and the 2361 // target supports indirect branches, then emit a jump table rather than 2362 // lowering the switch to a binary tree of conditional branches. 2363 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2364 continue; 2365 2366 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2367 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2368 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2369 } 2370} 2371 2372 2373void SelectionDAGLowering::visitSub(User &I) { 2374 // -0.0 - X --> fneg 2375 const Type *Ty = I.getType(); 2376 if (isa<VectorType>(Ty)) { 2377 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2378 const VectorType *DestTy = cast<VectorType>(I.getType()); 2379 const Type *ElTy = DestTy->getElementType(); 2380 if (ElTy->isFloatingPoint()) { 2381 unsigned VL = DestTy->getNumElements(); 2382 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2383 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2384 if (CV == CNZ) { 2385 SDValue Op2 = getValue(I.getOperand(1)); 2386 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2387 return; 2388 } 2389 } 2390 } 2391 } 2392 if (Ty->isFloatingPoint()) { 2393 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2394 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2395 SDValue Op2 = getValue(I.getOperand(1)); 2396 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2397 return; 2398 } 2399 } 2400 2401 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2402} 2403 2404void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2405 SDValue Op1 = getValue(I.getOperand(0)); 2406 SDValue Op2 = getValue(I.getOperand(1)); 2407 2408 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2409} 2410 2411void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2412 SDValue Op1 = getValue(I.getOperand(0)); 2413 SDValue Op2 = getValue(I.getOperand(1)); 2414 if (!isa<VectorType>(I.getType())) { 2415 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) 2416 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2417 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) 2418 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2419 } 2420 2421 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2422} 2423 2424void SelectionDAGLowering::visitICmp(User &I) { 2425 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2426 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2427 predicate = IC->getPredicate(); 2428 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2429 predicate = ICmpInst::Predicate(IC->getPredicate()); 2430 SDValue Op1 = getValue(I.getOperand(0)); 2431 SDValue Op2 = getValue(I.getOperand(1)); 2432 ISD::CondCode Opcode; 2433 switch (predicate) { 2434 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2435 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2436 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2437 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2438 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2439 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2440 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2441 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2442 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2443 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2444 default: 2445 assert(!"Invalid ICmp predicate value"); 2446 Opcode = ISD::SETEQ; 2447 break; 2448 } 2449 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2450} 2451 2452void SelectionDAGLowering::visitFCmp(User &I) { 2453 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2454 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2455 predicate = FC->getPredicate(); 2456 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2457 predicate = FCmpInst::Predicate(FC->getPredicate()); 2458 SDValue Op1 = getValue(I.getOperand(0)); 2459 SDValue Op2 = getValue(I.getOperand(1)); 2460 ISD::CondCode Condition, FOC, FPC; 2461 switch (predicate) { 2462 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2463 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2464 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2465 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2466 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2467 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2468 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2469 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2470 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2471 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2472 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2473 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2474 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2475 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2476 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2477 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2478 default: 2479 assert(!"Invalid FCmp predicate value"); 2480 FOC = FPC = ISD::SETFALSE; 2481 break; 2482 } 2483 if (FiniteOnlyFPMath()) 2484 Condition = FOC; 2485 else 2486 Condition = FPC; 2487 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2488} 2489 2490void SelectionDAGLowering::visitVICmp(User &I) { 2491 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2492 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I)) 2493 predicate = IC->getPredicate(); 2494 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2495 predicate = ICmpInst::Predicate(IC->getPredicate()); 2496 SDValue Op1 = getValue(I.getOperand(0)); 2497 SDValue Op2 = getValue(I.getOperand(1)); 2498 ISD::CondCode Opcode; 2499 switch (predicate) { 2500 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2501 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2502 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2503 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2504 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2505 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2506 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2507 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2508 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2509 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2510 default: 2511 assert(!"Invalid ICmp predicate value"); 2512 Opcode = ISD::SETEQ; 2513 break; 2514 } 2515 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); 2516} 2517 2518void SelectionDAGLowering::visitVFCmp(User &I) { 2519 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2520 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I)) 2521 predicate = FC->getPredicate(); 2522 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2523 predicate = FCmpInst::Predicate(FC->getPredicate()); 2524 SDValue Op1 = getValue(I.getOperand(0)); 2525 SDValue Op2 = getValue(I.getOperand(1)); 2526 ISD::CondCode Condition, FOC, FPC; 2527 switch (predicate) { 2528 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2529 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2530 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2531 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2532 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2533 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2534 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2535 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 2536 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 2537 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2538 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2539 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2540 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2541 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2542 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2543 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2544 default: 2545 assert(!"Invalid VFCmp predicate value"); 2546 FOC = FPC = ISD::SETFALSE; 2547 break; 2548 } 2549 if (FiniteOnlyFPMath()) 2550 Condition = FOC; 2551 else 2552 Condition = FPC; 2553 2554 MVT DestVT = TLI.getValueType(I.getType()); 2555 2556 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); 2557} 2558 2559void SelectionDAGLowering::visitSelect(User &I) { 2560 SDValue Cond = getValue(I.getOperand(0)); 2561 SDValue TrueVal = getValue(I.getOperand(1)); 2562 SDValue FalseVal = getValue(I.getOperand(2)); 2563 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2564 TrueVal, FalseVal)); 2565} 2566 2567 2568void SelectionDAGLowering::visitTrunc(User &I) { 2569 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2570 SDValue N = getValue(I.getOperand(0)); 2571 MVT DestVT = TLI.getValueType(I.getType()); 2572 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2573} 2574 2575void SelectionDAGLowering::visitZExt(User &I) { 2576 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2577 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2578 SDValue N = getValue(I.getOperand(0)); 2579 MVT DestVT = TLI.getValueType(I.getType()); 2580 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2581} 2582 2583void SelectionDAGLowering::visitSExt(User &I) { 2584 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2585 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2586 SDValue N = getValue(I.getOperand(0)); 2587 MVT DestVT = TLI.getValueType(I.getType()); 2588 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2589} 2590 2591void SelectionDAGLowering::visitFPTrunc(User &I) { 2592 // FPTrunc is never a no-op cast, no need to check 2593 SDValue N = getValue(I.getOperand(0)); 2594 MVT DestVT = TLI.getValueType(I.getType()); 2595 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); 2596} 2597 2598void SelectionDAGLowering::visitFPExt(User &I){ 2599 // FPTrunc is never a no-op cast, no need to check 2600 SDValue N = getValue(I.getOperand(0)); 2601 MVT DestVT = TLI.getValueType(I.getType()); 2602 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2603} 2604 2605void SelectionDAGLowering::visitFPToUI(User &I) { 2606 // FPToUI is never a no-op cast, no need to check 2607 SDValue N = getValue(I.getOperand(0)); 2608 MVT DestVT = TLI.getValueType(I.getType()); 2609 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2610} 2611 2612void SelectionDAGLowering::visitFPToSI(User &I) { 2613 // FPToSI is never a no-op cast, no need to check 2614 SDValue N = getValue(I.getOperand(0)); 2615 MVT DestVT = TLI.getValueType(I.getType()); 2616 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2617} 2618 2619void SelectionDAGLowering::visitUIToFP(User &I) { 2620 // UIToFP is never a no-op cast, no need to check 2621 SDValue N = getValue(I.getOperand(0)); 2622 MVT DestVT = TLI.getValueType(I.getType()); 2623 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2624} 2625 2626void SelectionDAGLowering::visitSIToFP(User &I){ 2627 // UIToFP is never a no-op cast, no need to check 2628 SDValue N = getValue(I.getOperand(0)); 2629 MVT DestVT = TLI.getValueType(I.getType()); 2630 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2631} 2632 2633void SelectionDAGLowering::visitPtrToInt(User &I) { 2634 // What to do depends on the size of the integer and the size of the pointer. 2635 // We can either truncate, zero extend, or no-op, accordingly. 2636 SDValue N = getValue(I.getOperand(0)); 2637 MVT SrcVT = N.getValueType(); 2638 MVT DestVT = TLI.getValueType(I.getType()); 2639 SDValue Result; 2640 if (DestVT.bitsLT(SrcVT)) 2641 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2642 else 2643 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2644 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2645 setValue(&I, Result); 2646} 2647 2648void SelectionDAGLowering::visitIntToPtr(User &I) { 2649 // What to do depends on the size of the integer and the size of the pointer. 2650 // We can either truncate, zero extend, or no-op, accordingly. 2651 SDValue N = getValue(I.getOperand(0)); 2652 MVT SrcVT = N.getValueType(); 2653 MVT DestVT = TLI.getValueType(I.getType()); 2654 if (DestVT.bitsLT(SrcVT)) 2655 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2656 else 2657 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2658 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2659} 2660 2661void SelectionDAGLowering::visitBitCast(User &I) { 2662 SDValue N = getValue(I.getOperand(0)); 2663 MVT DestVT = TLI.getValueType(I.getType()); 2664 2665 // BitCast assures us that source and destination are the same size so this 2666 // is either a BIT_CONVERT or a no-op. 2667 if (DestVT != N.getValueType()) 2668 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2669 else 2670 setValue(&I, N); // noop cast. 2671} 2672 2673void SelectionDAGLowering::visitInsertElement(User &I) { 2674 SDValue InVec = getValue(I.getOperand(0)); 2675 SDValue InVal = getValue(I.getOperand(1)); 2676 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2677 getValue(I.getOperand(2))); 2678 2679 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2680 TLI.getValueType(I.getType()), 2681 InVec, InVal, InIdx)); 2682} 2683 2684void SelectionDAGLowering::visitExtractElement(User &I) { 2685 SDValue InVec = getValue(I.getOperand(0)); 2686 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2687 getValue(I.getOperand(1))); 2688 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2689 TLI.getValueType(I.getType()), InVec, InIdx)); 2690} 2691 2692void SelectionDAGLowering::visitShuffleVector(User &I) { 2693 SDValue V1 = getValue(I.getOperand(0)); 2694 SDValue V2 = getValue(I.getOperand(1)); 2695 SDValue Mask = getValue(I.getOperand(2)); 2696 2697 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2698 TLI.getValueType(I.getType()), 2699 V1, V2, Mask)); 2700} 2701 2702void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { 2703 const Value *Op0 = I.getOperand(0); 2704 const Value *Op1 = I.getOperand(1); 2705 const Type *AggTy = I.getType(); 2706 const Type *ValTy = Op1->getType(); 2707 bool IntoUndef = isa<UndefValue>(Op0); 2708 bool FromUndef = isa<UndefValue>(Op1); 2709 2710 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2711 I.idx_begin(), I.idx_end()); 2712 2713 SmallVector<MVT, 4> AggValueVTs; 2714 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2715 SmallVector<MVT, 4> ValValueVTs; 2716 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2717 2718 unsigned NumAggValues = AggValueVTs.size(); 2719 unsigned NumValValues = ValValueVTs.size(); 2720 SmallVector<SDValue, 4> Values(NumAggValues); 2721 2722 SDValue Agg = getValue(Op0); 2723 SDValue Val = getValue(Op1); 2724 unsigned i = 0; 2725 // Copy the beginning value(s) from the original aggregate. 2726 for (; i != LinearIndex; ++i) 2727 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2728 SDValue(Agg.Val, Agg.ResNo + i); 2729 // Copy values from the inserted value(s). 2730 for (; i != LinearIndex + NumValValues; ++i) 2731 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2732 SDValue(Val.Val, Val.ResNo + i - LinearIndex); 2733 // Copy remaining value(s) from the original aggregate. 2734 for (; i != NumAggValues; ++i) 2735 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : 2736 SDValue(Agg.Val, Agg.ResNo + i); 2737 2738 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues), 2739 &Values[0], NumAggValues)); 2740} 2741 2742void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { 2743 const Value *Op0 = I.getOperand(0); 2744 const Type *AggTy = Op0->getType(); 2745 const Type *ValTy = I.getType(); 2746 bool OutOfUndef = isa<UndefValue>(Op0); 2747 2748 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2749 I.idx_begin(), I.idx_end()); 2750 2751 SmallVector<MVT, 4> ValValueVTs; 2752 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2753 2754 unsigned NumValValues = ValValueVTs.size(); 2755 SmallVector<SDValue, 4> Values(NumValValues); 2756 2757 SDValue Agg = getValue(Op0); 2758 // Copy out the selected value(s). 2759 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2760 Values[i - LinearIndex] = 2761 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) : 2762 SDValue(Agg.Val, Agg.ResNo + i); 2763 2764 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues), 2765 &Values[0], NumValValues)); 2766} 2767 2768 2769void SelectionDAGLowering::visitGetElementPtr(User &I) { 2770 SDValue N = getValue(I.getOperand(0)); 2771 const Type *Ty = I.getOperand(0)->getType(); 2772 2773 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2774 OI != E; ++OI) { 2775 Value *Idx = *OI; 2776 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2777 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2778 if (Field) { 2779 // N = N + Offset 2780 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2781 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2782 DAG.getIntPtrConstant(Offset)); 2783 } 2784 Ty = StTy->getElementType(Field); 2785 } else { 2786 Ty = cast<SequentialType>(Ty)->getElementType(); 2787 2788 // If this is a constant subscript, handle it quickly. 2789 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2790 if (CI->getZExtValue() == 0) continue; 2791 uint64_t Offs = 2792 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2793 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2794 DAG.getIntPtrConstant(Offs)); 2795 continue; 2796 } 2797 2798 // N = N + Idx * ElementSize; 2799 uint64_t ElementSize = TD->getABITypeSize(Ty); 2800 SDValue IdxN = getValue(Idx); 2801 2802 // If the index is smaller or larger than intptr_t, truncate or extend 2803 // it. 2804 if (IdxN.getValueType().bitsLT(N.getValueType())) { 2805 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2806 } else if (IdxN.getValueType().bitsGT(N.getValueType())) 2807 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2808 2809 // If this is a multiply by a power of two, turn it into a shl 2810 // immediately. This is a very common case. 2811 if (isPowerOf2_64(ElementSize)) { 2812 unsigned Amt = Log2_64(ElementSize); 2813 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2814 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2815 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2816 continue; 2817 } 2818 2819 SDValue Scale = DAG.getIntPtrConstant(ElementSize); 2820 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2821 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2822 } 2823 } 2824 setValue(&I, N); 2825} 2826 2827void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2828 // If this is a fixed sized alloca in the entry block of the function, 2829 // allocate it statically on the stack. 2830 if (FuncInfo.StaticAllocaMap.count(&I)) 2831 return; // getValue will auto-populate this. 2832 2833 const Type *Ty = I.getAllocatedType(); 2834 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2835 unsigned Align = 2836 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2837 I.getAlignment()); 2838 2839 SDValue AllocSize = getValue(I.getArraySize()); 2840 MVT IntPtr = TLI.getPointerTy(); 2841 if (IntPtr.bitsLT(AllocSize.getValueType())) 2842 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2843 else if (IntPtr.bitsGT(AllocSize.getValueType())) 2844 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2845 2846 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2847 DAG.getIntPtrConstant(TySize)); 2848 2849 // Handle alignment. If the requested alignment is less than or equal to 2850 // the stack alignment, ignore it. If the size is greater than or equal to 2851 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2852 unsigned StackAlign = 2853 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2854 if (Align <= StackAlign) 2855 Align = 0; 2856 2857 // Round the size of the allocation up to the stack alignment size 2858 // by add SA-1 to the size. 2859 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2860 DAG.getIntPtrConstant(StackAlign-1)); 2861 // Mask out the low bits for alignment purposes. 2862 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2863 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2864 2865 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2866 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2867 MVT::Other); 2868 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2869 setValue(&I, DSA); 2870 DAG.setRoot(DSA.getValue(1)); 2871 2872 // Inform the Frame Information that we have just allocated a variable-sized 2873 // object. 2874 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2875} 2876 2877void SelectionDAGLowering::visitLoad(LoadInst &I) { 2878 const Value *SV = I.getOperand(0); 2879 SDValue Ptr = getValue(SV); 2880 2881 const Type *Ty = I.getType(); 2882 bool isVolatile = I.isVolatile(); 2883 unsigned Alignment = I.getAlignment(); 2884 2885 SmallVector<MVT, 4> ValueVTs; 2886 SmallVector<uint64_t, 4> Offsets; 2887 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2888 unsigned NumValues = ValueVTs.size(); 2889 if (NumValues == 0) 2890 return; 2891 2892 SDValue Root; 2893 bool ConstantMemory = false; 2894 if (I.isVolatile()) 2895 // Serialize volatile loads with other side effects. 2896 Root = getRoot(); 2897 else if (AA.pointsToConstantMemory(SV)) { 2898 // Do not serialize (non-volatile) loads of constant memory with anything. 2899 Root = DAG.getEntryNode(); 2900 ConstantMemory = true; 2901 } else { 2902 // Do not serialize non-volatile loads against each other. 2903 Root = DAG.getRoot(); 2904 } 2905 2906 SmallVector<SDValue, 4> Values(NumValues); 2907 SmallVector<SDValue, 4> Chains(NumValues); 2908 MVT PtrVT = Ptr.getValueType(); 2909 for (unsigned i = 0; i != NumValues; ++i) { 2910 SDValue L = DAG.getLoad(ValueVTs[i], Root, 2911 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2912 DAG.getConstant(Offsets[i], PtrVT)), 2913 SV, Offsets[i], 2914 isVolatile, Alignment); 2915 Values[i] = L; 2916 Chains[i] = L.getValue(1); 2917 } 2918 2919 if (!ConstantMemory) { 2920 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2921 &Chains[0], NumValues); 2922 if (isVolatile) 2923 DAG.setRoot(Chain); 2924 else 2925 PendingLoads.push_back(Chain); 2926 } 2927 2928 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), 2929 &Values[0], NumValues)); 2930} 2931 2932 2933void SelectionDAGLowering::visitStore(StoreInst &I) { 2934 Value *SrcV = I.getOperand(0); 2935 Value *PtrV = I.getOperand(1); 2936 2937 SmallVector<MVT, 4> ValueVTs; 2938 SmallVector<uint64_t, 4> Offsets; 2939 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2940 unsigned NumValues = ValueVTs.size(); 2941 if (NumValues == 0) 2942 return; 2943 2944 // Get the lowered operands. Note that we do this after 2945 // checking if NumResults is zero, because with zero results 2946 // the operands won't have values in the map. 2947 SDValue Src = getValue(SrcV); 2948 SDValue Ptr = getValue(PtrV); 2949 2950 SDValue Root = getRoot(); 2951 SmallVector<SDValue, 4> Chains(NumValues); 2952 MVT PtrVT = Ptr.getValueType(); 2953 bool isVolatile = I.isVolatile(); 2954 unsigned Alignment = I.getAlignment(); 2955 for (unsigned i = 0; i != NumValues; ++i) 2956 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i), 2957 DAG.getNode(ISD::ADD, PtrVT, Ptr, 2958 DAG.getConstant(Offsets[i], PtrVT)), 2959 PtrV, Offsets[i], 2960 isVolatile, Alignment); 2961 2962 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues)); 2963} 2964 2965/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2966/// node. 2967void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2968 unsigned Intrinsic) { 2969 bool HasChain = !I.doesNotAccessMemory(); 2970 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2971 2972 // Build the operand list. 2973 SmallVector<SDValue, 8> Ops; 2974 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2975 if (OnlyLoad) { 2976 // We don't need to serialize loads against other loads. 2977 Ops.push_back(DAG.getRoot()); 2978 } else { 2979 Ops.push_back(getRoot()); 2980 } 2981 } 2982 2983 // Add the intrinsic ID as an integer operand. 2984 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2985 2986 // Add all operands of the call to the operand list. 2987 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2988 SDValue Op = getValue(I.getOperand(i)); 2989 assert(TLI.isTypeLegal(Op.getValueType()) && 2990 "Intrinsic uses a non-legal type?"); 2991 Ops.push_back(Op); 2992 } 2993 2994 std::vector<MVT> VTs; 2995 if (I.getType() != Type::VoidTy) { 2996 MVT VT = TLI.getValueType(I.getType()); 2997 if (VT.isVector()) { 2998 const VectorType *DestTy = cast<VectorType>(I.getType()); 2999 MVT EltVT = TLI.getValueType(DestTy->getElementType()); 3000 3001 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); 3002 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 3003 } 3004 3005 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 3006 VTs.push_back(VT); 3007 } 3008 if (HasChain) 3009 VTs.push_back(MVT::Other); 3010 3011 const MVT *VTList = DAG.getNodeValueTypes(VTs); 3012 3013 // Create the node. 3014 SDValue Result; 3015 if (!HasChain) 3016 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 3017 &Ops[0], Ops.size()); 3018 else if (I.getType() != Type::VoidTy) 3019 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 3020 &Ops[0], Ops.size()); 3021 else 3022 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 3023 &Ops[0], Ops.size()); 3024 3025 if (HasChain) { 3026 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1); 3027 if (OnlyLoad) 3028 PendingLoads.push_back(Chain); 3029 else 3030 DAG.setRoot(Chain); 3031 } 3032 if (I.getType() != Type::VoidTy) { 3033 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3034 MVT VT = TLI.getValueType(PTy); 3035 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 3036 } 3037 setValue(&I, Result); 3038 } 3039} 3040 3041/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 3042static GlobalVariable *ExtractTypeInfo (Value *V) { 3043 V = V->stripPointerCasts(); 3044 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 3045 assert ((GV || isa<ConstantPointerNull>(V)) && 3046 "TypeInfo must be a global variable or NULL"); 3047 return GV; 3048} 3049 3050/// addCatchInfo - Extract the personality and type infos from an eh.selector 3051/// call, and add them to the specified machine basic block. 3052static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 3053 MachineBasicBlock *MBB) { 3054 // Inform the MachineModuleInfo of the personality for this landing pad. 3055 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 3056 assert(CE->getOpcode() == Instruction::BitCast && 3057 isa<Function>(CE->getOperand(0)) && 3058 "Personality should be a function"); 3059 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 3060 3061 // Gather all the type infos for this landing pad and pass them along to 3062 // MachineModuleInfo. 3063 std::vector<GlobalVariable *> TyInfo; 3064 unsigned N = I.getNumOperands(); 3065 3066 for (unsigned i = N - 1; i > 2; --i) { 3067 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 3068 unsigned FilterLength = CI->getZExtValue(); 3069 unsigned FirstCatch = i + FilterLength + !FilterLength; 3070 assert (FirstCatch <= N && "Invalid filter length"); 3071 3072 if (FirstCatch < N) { 3073 TyInfo.reserve(N - FirstCatch); 3074 for (unsigned j = FirstCatch; j < N; ++j) 3075 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3076 MMI->addCatchTypeInfo(MBB, TyInfo); 3077 TyInfo.clear(); 3078 } 3079 3080 if (!FilterLength) { 3081 // Cleanup. 3082 MMI->addCleanup(MBB); 3083 } else { 3084 // Filter. 3085 TyInfo.reserve(FilterLength - 1); 3086 for (unsigned j = i + 1; j < FirstCatch; ++j) 3087 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3088 MMI->addFilterTypeInfo(MBB, TyInfo); 3089 TyInfo.clear(); 3090 } 3091 3092 N = i; 3093 } 3094 } 3095 3096 if (N > 3) { 3097 TyInfo.reserve(N - 3); 3098 for (unsigned j = 3; j < N; ++j) 3099 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 3100 MMI->addCatchTypeInfo(MBB, TyInfo); 3101 } 3102} 3103 3104 3105/// Inlined utility function to implement binary input atomic intrinsics for 3106// visitIntrinsicCall: I is a call instruction 3107// Op is the associated NodeType for I 3108const char * 3109SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { 3110 SDValue Root = getRoot(); 3111 SDValue L = DAG.getAtomic(Op, Root, 3112 getValue(I.getOperand(1)), 3113 getValue(I.getOperand(2)), 3114 I.getOperand(1)); 3115 setValue(&I, L); 3116 DAG.setRoot(L.getValue(1)); 3117 return 0; 3118} 3119 3120/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3121/// we want to emit this as a call to a named external function, return the name 3122/// otherwise lower it and return null. 3123const char * 3124SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 3125 switch (Intrinsic) { 3126 default: 3127 // By default, turn this into a target intrinsic node. 3128 visitTargetIntrinsic(I, Intrinsic); 3129 return 0; 3130 case Intrinsic::vastart: visitVAStart(I); return 0; 3131 case Intrinsic::vaend: visitVAEnd(I); return 0; 3132 case Intrinsic::vacopy: visitVACopy(I); return 0; 3133 case Intrinsic::returnaddress: 3134 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 3135 getValue(I.getOperand(1)))); 3136 return 0; 3137 case Intrinsic::frameaddress: 3138 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 3139 getValue(I.getOperand(1)))); 3140 return 0; 3141 case Intrinsic::setjmp: 3142 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3143 break; 3144 case Intrinsic::longjmp: 3145 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3146 break; 3147 case Intrinsic::memcpy_i32: 3148 case Intrinsic::memcpy_i64: { 3149 SDValue Op1 = getValue(I.getOperand(1)); 3150 SDValue Op2 = getValue(I.getOperand(2)); 3151 SDValue Op3 = getValue(I.getOperand(3)); 3152 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3153 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3154 I.getOperand(1), 0, I.getOperand(2), 0)); 3155 return 0; 3156 } 3157 case Intrinsic::memset_i32: 3158 case Intrinsic::memset_i64: { 3159 SDValue Op1 = getValue(I.getOperand(1)); 3160 SDValue Op2 = getValue(I.getOperand(2)); 3161 SDValue Op3 = getValue(I.getOperand(3)); 3162 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3163 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, 3164 I.getOperand(1), 0)); 3165 return 0; 3166 } 3167 case Intrinsic::memmove_i32: 3168 case Intrinsic::memmove_i64: { 3169 SDValue Op1 = getValue(I.getOperand(1)); 3170 SDValue Op2 = getValue(I.getOperand(2)); 3171 SDValue Op3 = getValue(I.getOperand(3)); 3172 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3173 3174 // If the source and destination are known to not be aliases, we can 3175 // lower memmove as memcpy. 3176 uint64_t Size = -1ULL; 3177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3178 Size = C->getValue(); 3179 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3180 AliasAnalysis::NoAlias) { 3181 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, 3182 I.getOperand(1), 0, I.getOperand(2), 0)); 3183 return 0; 3184 } 3185 3186 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, 3187 I.getOperand(1), 0, I.getOperand(2), 0)); 3188 return 0; 3189 } 3190 case Intrinsic::dbg_stoppoint: { 3191 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3192 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 3193 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 3194 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 3195 assert(DD && "Not a debug information descriptor"); 3196 DAG.setRoot(DAG.getDbgStopPoint(getRoot(), 3197 SPI.getLine(), 3198 SPI.getColumn(), 3199 cast<CompileUnitDesc>(DD))); 3200 } 3201 3202 return 0; 3203 } 3204 case Intrinsic::dbg_region_start: { 3205 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3206 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 3207 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 3208 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 3209 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3210 } 3211 3212 return 0; 3213 } 3214 case Intrinsic::dbg_region_end: { 3215 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3216 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 3217 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 3218 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 3219 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); 3220 } 3221 3222 return 0; 3223 } 3224 case Intrinsic::dbg_func_start: { 3225 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3226 if (!MMI) return 0; 3227 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 3228 Value *SP = FSI.getSubprogram(); 3229 if (SP && MMI->Verify(SP)) { 3230 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 3231 // what (most?) gdb expects. 3232 DebugInfoDesc *DD = MMI->getDescFor(SP); 3233 assert(DD && "Not a debug information descriptor"); 3234 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 3235 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 3236 unsigned SrcFile = MMI->RecordSource(CompileUnit); 3237 // Record the source line but does create a label. It will be emitted 3238 // at asm emission time. 3239 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 3240 } 3241 3242 return 0; 3243 } 3244 case Intrinsic::dbg_declare: { 3245 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3246 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3247 Value *Variable = DI.getVariable(); 3248 if (MMI && Variable && MMI->Verify(Variable)) 3249 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), 3250 getValue(DI.getAddress()), getValue(Variable))); 3251 return 0; 3252 } 3253 3254 case Intrinsic::eh_exception: { 3255 if (!CurMBB->isLandingPad()) { 3256 // FIXME: Mark exception register as live in. Hack for PR1508. 3257 unsigned Reg = TLI.getExceptionAddressRegister(); 3258 if (Reg) CurMBB->addLiveIn(Reg); 3259 } 3260 // Insert the EXCEPTIONADDR instruction. 3261 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3262 SDValue Ops[1]; 3263 Ops[0] = DAG.getRoot(); 3264 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 3265 setValue(&I, Op); 3266 DAG.setRoot(Op.getValue(1)); 3267 return 0; 3268 } 3269 3270 case Intrinsic::eh_selector_i32: 3271 case Intrinsic::eh_selector_i64: { 3272 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3273 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 3274 MVT::i32 : MVT::i64); 3275 3276 if (MMI) { 3277 if (CurMBB->isLandingPad()) 3278 addCatchInfo(I, MMI, CurMBB); 3279 else { 3280#ifndef NDEBUG 3281 FuncInfo.CatchInfoLost.insert(&I); 3282#endif 3283 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3284 unsigned Reg = TLI.getExceptionSelectorRegister(); 3285 if (Reg) CurMBB->addLiveIn(Reg); 3286 } 3287 3288 // Insert the EHSELECTION instruction. 3289 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 3290 SDValue Ops[2]; 3291 Ops[0] = getValue(I.getOperand(1)); 3292 Ops[1] = getRoot(); 3293 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 3294 setValue(&I, Op); 3295 DAG.setRoot(Op.getValue(1)); 3296 } else { 3297 setValue(&I, DAG.getConstant(0, VT)); 3298 } 3299 3300 return 0; 3301 } 3302 3303 case Intrinsic::eh_typeid_for_i32: 3304 case Intrinsic::eh_typeid_for_i64: { 3305 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3306 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 3307 MVT::i32 : MVT::i64); 3308 3309 if (MMI) { 3310 // Find the type id for the given typeinfo. 3311 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3312 3313 unsigned TypeID = MMI->getTypeIDFor(GV); 3314 setValue(&I, DAG.getConstant(TypeID, VT)); 3315 } else { 3316 // Return something different to eh_selector. 3317 setValue(&I, DAG.getConstant(1, VT)); 3318 } 3319 3320 return 0; 3321 } 3322 3323 case Intrinsic::eh_return: { 3324 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3325 3326 if (MMI) { 3327 MMI->setCallsEHReturn(true); 3328 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 3329 MVT::Other, 3330 getControlRoot(), 3331 getValue(I.getOperand(1)), 3332 getValue(I.getOperand(2)))); 3333 } else { 3334 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 3335 } 3336 3337 return 0; 3338 } 3339 3340 case Intrinsic::eh_unwind_init: { 3341 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 3342 MMI->setCallsUnwindInit(true); 3343 } 3344 3345 return 0; 3346 } 3347 3348 case Intrinsic::eh_dwarf_cfa: { 3349 MVT VT = getValue(I.getOperand(1)).getValueType(); 3350 SDValue CfaArg; 3351 if (VT.bitsGT(TLI.getPointerTy())) 3352 CfaArg = DAG.getNode(ISD::TRUNCATE, 3353 TLI.getPointerTy(), getValue(I.getOperand(1))); 3354 else 3355 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 3356 TLI.getPointerTy(), getValue(I.getOperand(1))); 3357 3358 SDValue Offset = DAG.getNode(ISD::ADD, 3359 TLI.getPointerTy(), 3360 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 3361 TLI.getPointerTy()), 3362 CfaArg); 3363 setValue(&I, DAG.getNode(ISD::ADD, 3364 TLI.getPointerTy(), 3365 DAG.getNode(ISD::FRAMEADDR, 3366 TLI.getPointerTy(), 3367 DAG.getConstant(0, 3368 TLI.getPointerTy())), 3369 Offset)); 3370 return 0; 3371 } 3372 3373 case Intrinsic::sqrt: 3374 setValue(&I, DAG.getNode(ISD::FSQRT, 3375 getValue(I.getOperand(1)).getValueType(), 3376 getValue(I.getOperand(1)))); 3377 return 0; 3378 case Intrinsic::powi: 3379 setValue(&I, DAG.getNode(ISD::FPOWI, 3380 getValue(I.getOperand(1)).getValueType(), 3381 getValue(I.getOperand(1)), 3382 getValue(I.getOperand(2)))); 3383 return 0; 3384 case Intrinsic::sin: 3385 setValue(&I, DAG.getNode(ISD::FSIN, 3386 getValue(I.getOperand(1)).getValueType(), 3387 getValue(I.getOperand(1)))); 3388 return 0; 3389 case Intrinsic::cos: 3390 setValue(&I, DAG.getNode(ISD::FCOS, 3391 getValue(I.getOperand(1)).getValueType(), 3392 getValue(I.getOperand(1)))); 3393 return 0; 3394 case Intrinsic::pow: 3395 setValue(&I, DAG.getNode(ISD::FPOW, 3396 getValue(I.getOperand(1)).getValueType(), 3397 getValue(I.getOperand(1)), 3398 getValue(I.getOperand(2)))); 3399 return 0; 3400 case Intrinsic::pcmarker: { 3401 SDValue Tmp = getValue(I.getOperand(1)); 3402 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 3403 return 0; 3404 } 3405 case Intrinsic::readcyclecounter: { 3406 SDValue Op = getRoot(); 3407 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 3408 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 3409 &Op, 1); 3410 setValue(&I, Tmp); 3411 DAG.setRoot(Tmp.getValue(1)); 3412 return 0; 3413 } 3414 case Intrinsic::part_select: { 3415 // Currently not implemented: just abort 3416 assert(0 && "part_select intrinsic not implemented"); 3417 abort(); 3418 } 3419 case Intrinsic::part_set: { 3420 // Currently not implemented: just abort 3421 assert(0 && "part_set intrinsic not implemented"); 3422 abort(); 3423 } 3424 case Intrinsic::bswap: 3425 setValue(&I, DAG.getNode(ISD::BSWAP, 3426 getValue(I.getOperand(1)).getValueType(), 3427 getValue(I.getOperand(1)))); 3428 return 0; 3429 case Intrinsic::cttz: { 3430 SDValue Arg = getValue(I.getOperand(1)); 3431 MVT Ty = Arg.getValueType(); 3432 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg); 3433 setValue(&I, result); 3434 return 0; 3435 } 3436 case Intrinsic::ctlz: { 3437 SDValue Arg = getValue(I.getOperand(1)); 3438 MVT Ty = Arg.getValueType(); 3439 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg); 3440 setValue(&I, result); 3441 return 0; 3442 } 3443 case Intrinsic::ctpop: { 3444 SDValue Arg = getValue(I.getOperand(1)); 3445 MVT Ty = Arg.getValueType(); 3446 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg); 3447 setValue(&I, result); 3448 return 0; 3449 } 3450 case Intrinsic::stacksave: { 3451 SDValue Op = getRoot(); 3452 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, 3453 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 3454 setValue(&I, Tmp); 3455 DAG.setRoot(Tmp.getValue(1)); 3456 return 0; 3457 } 3458 case Intrinsic::stackrestore: { 3459 SDValue Tmp = getValue(I.getOperand(1)); 3460 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 3461 return 0; 3462 } 3463 case Intrinsic::var_annotation: 3464 // Discard annotate attributes 3465 return 0; 3466 3467 case Intrinsic::init_trampoline: { 3468 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 3469 3470 SDValue Ops[6]; 3471 Ops[0] = getRoot(); 3472 Ops[1] = getValue(I.getOperand(1)); 3473 Ops[2] = getValue(I.getOperand(2)); 3474 Ops[3] = getValue(I.getOperand(3)); 3475 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 3476 Ops[5] = DAG.getSrcValue(F); 3477 3478 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, 3479 DAG.getNodeValueTypes(TLI.getPointerTy(), 3480 MVT::Other), 2, 3481 Ops, 6); 3482 3483 setValue(&I, Tmp); 3484 DAG.setRoot(Tmp.getValue(1)); 3485 return 0; 3486 } 3487 3488 case Intrinsic::gcroot: 3489 if (GCI) { 3490 Value *Alloca = I.getOperand(1); 3491 Constant *TypeMap = cast<Constant>(I.getOperand(2)); 3492 3493 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val); 3494 GCI->addStackRoot(FI->getIndex(), TypeMap); 3495 } 3496 return 0; 3497 3498 case Intrinsic::gcread: 3499 case Intrinsic::gcwrite: 3500 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!"); 3501 return 0; 3502 3503 case Intrinsic::flt_rounds: { 3504 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); 3505 return 0; 3506 } 3507 3508 case Intrinsic::trap: { 3509 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); 3510 return 0; 3511 } 3512 case Intrinsic::prefetch: { 3513 SDValue Ops[4]; 3514 Ops[0] = getRoot(); 3515 Ops[1] = getValue(I.getOperand(1)); 3516 Ops[2] = getValue(I.getOperand(2)); 3517 Ops[3] = getValue(I.getOperand(3)); 3518 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4)); 3519 return 0; 3520 } 3521 3522 case Intrinsic::memory_barrier: { 3523 SDValue Ops[6]; 3524 Ops[0] = getRoot(); 3525 for (int x = 1; x < 6; ++x) 3526 Ops[x] = getValue(I.getOperand(x)); 3527 3528 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); 3529 return 0; 3530 } 3531 case Intrinsic::atomic_cmp_swap: { 3532 SDValue Root = getRoot(); 3533 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root, 3534 getValue(I.getOperand(1)), 3535 getValue(I.getOperand(2)), 3536 getValue(I.getOperand(3)), 3537 I.getOperand(1)); 3538 setValue(&I, L); 3539 DAG.setRoot(L.getValue(1)); 3540 return 0; 3541 } 3542 case Intrinsic::atomic_load_add: 3543 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 3544 case Intrinsic::atomic_load_sub: 3545 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 3546 case Intrinsic::atomic_load_and: 3547 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 3548 case Intrinsic::atomic_load_or: 3549 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 3550 case Intrinsic::atomic_load_xor: 3551 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 3552 case Intrinsic::atomic_load_nand: 3553 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 3554 case Intrinsic::atomic_load_min: 3555 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 3556 case Intrinsic::atomic_load_max: 3557 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 3558 case Intrinsic::atomic_load_umin: 3559 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 3560 case Intrinsic::atomic_load_umax: 3561 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 3562 case Intrinsic::atomic_swap: 3563 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 3564 } 3565} 3566 3567 3568void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, 3569 bool IsTailCall, 3570 MachineBasicBlock *LandingPad) { 3571 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 3572 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 3573 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 3574 unsigned BeginLabel = 0, EndLabel = 0; 3575 3576 TargetLowering::ArgListTy Args; 3577 TargetLowering::ArgListEntry Entry; 3578 Args.reserve(CS.arg_size()); 3579 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 3580 i != e; ++i) { 3581 SDValue ArgNode = getValue(*i); 3582 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 3583 3584 unsigned attrInd = i - CS.arg_begin() + 1; 3585 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt); 3586 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt); 3587 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg); 3588 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet); 3589 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest); 3590 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal); 3591 Entry.Alignment = CS.getParamAlignment(attrInd); 3592 Args.push_back(Entry); 3593 } 3594 3595 if (LandingPad && MMI) { 3596 // Insert a label before the invoke call to mark the try range. This can be 3597 // used to detect deletion of the invoke via the MachineModuleInfo. 3598 BeginLabel = MMI->NextLabelID(); 3599 // Both PendingLoads and PendingExports must be flushed here; 3600 // this call might not return. 3601 (void)getRoot(); 3602 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); 3603 } 3604 3605 std::pair<SDValue,SDValue> Result = 3606 TLI.LowerCallTo(getRoot(), CS.getType(), 3607 CS.paramHasAttr(0, ParamAttr::SExt), 3608 CS.paramHasAttr(0, ParamAttr::ZExt), 3609 FTy->isVarArg(), CS.getCallingConv(), IsTailCall, 3610 Callee, Args, DAG); 3611 if (CS.getType() != Type::VoidTy) 3612 setValue(CS.getInstruction(), Result.first); 3613 DAG.setRoot(Result.second); 3614 3615 if (LandingPad && MMI) { 3616 // Insert a label at the end of the invoke call to mark the try range. This 3617 // can be used to detect deletion of the invoke via the MachineModuleInfo. 3618 EndLabel = MMI->NextLabelID(); 3619 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); 3620 3621 // Inform MachineModuleInfo of range. 3622 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 3623 } 3624} 3625 3626 3627void SelectionDAGLowering::visitCall(CallInst &I) { 3628 const char *RenameFn = 0; 3629 if (Function *F = I.getCalledFunction()) { 3630 if (F->isDeclaration()) { 3631 if (unsigned IID = F->getIntrinsicID()) { 3632 RenameFn = visitIntrinsicCall(I, IID); 3633 if (!RenameFn) 3634 return; 3635 } 3636 } 3637 3638 // Check for well-known libc/libm calls. If the function is internal, it 3639 // can't be a library call. 3640 unsigned NameLen = F->getNameLen(); 3641 if (!F->hasInternalLinkage() && NameLen) { 3642 const char *NameStr = F->getNameStart(); 3643 if (NameStr[0] == 'c' && 3644 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3645 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3646 if (I.getNumOperands() == 3 && // Basic sanity checks. 3647 I.getOperand(1)->getType()->isFloatingPoint() && 3648 I.getType() == I.getOperand(1)->getType() && 3649 I.getType() == I.getOperand(2)->getType()) { 3650 SDValue LHS = getValue(I.getOperand(1)); 3651 SDValue RHS = getValue(I.getOperand(2)); 3652 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3653 LHS, RHS)); 3654 return; 3655 } 3656 } else if (NameStr[0] == 'f' && 3657 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3658 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3659 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3660 if (I.getNumOperands() == 2 && // Basic sanity checks. 3661 I.getOperand(1)->getType()->isFloatingPoint() && 3662 I.getType() == I.getOperand(1)->getType()) { 3663 SDValue Tmp = getValue(I.getOperand(1)); 3664 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3665 return; 3666 } 3667 } else if (NameStr[0] == 's' && 3668 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3669 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3670 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3671 if (I.getNumOperands() == 2 && // Basic sanity checks. 3672 I.getOperand(1)->getType()->isFloatingPoint() && 3673 I.getType() == I.getOperand(1)->getType()) { 3674 SDValue Tmp = getValue(I.getOperand(1)); 3675 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3676 return; 3677 } 3678 } else if (NameStr[0] == 'c' && 3679 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3680 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3681 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3682 if (I.getNumOperands() == 2 && // Basic sanity checks. 3683 I.getOperand(1)->getType()->isFloatingPoint() && 3684 I.getType() == I.getOperand(1)->getType()) { 3685 SDValue Tmp = getValue(I.getOperand(1)); 3686 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3687 return; 3688 } 3689 } 3690 } 3691 } else if (isa<InlineAsm>(I.getOperand(0))) { 3692 visitInlineAsm(&I); 3693 return; 3694 } 3695 3696 SDValue Callee; 3697 if (!RenameFn) 3698 Callee = getValue(I.getOperand(0)); 3699 else 3700 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3701 3702 LowerCallTo(&I, Callee, I.isTailCall()); 3703} 3704 3705 3706/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3707/// this value and returns the result as a ValueVT value. This uses 3708/// Chain/Flag as the input and updates them for the output Chain/Flag. 3709/// If the Flag pointer is NULL, no flag is used. 3710SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3711 SDValue &Chain, 3712 SDValue *Flag) const { 3713 // Assemble the legal parts into the final values. 3714 SmallVector<SDValue, 4> Values(ValueVTs.size()); 3715 SmallVector<SDValue, 8> Parts; 3716 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3717 // Copy the legal parts from the registers. 3718 MVT ValueVT = ValueVTs[Value]; 3719 unsigned NumRegs = TLI->getNumRegisters(ValueVT); 3720 MVT RegisterVT = RegVTs[Value]; 3721 3722 Parts.resize(NumRegs); 3723 for (unsigned i = 0; i != NumRegs; ++i) { 3724 SDValue P; 3725 if (Flag == 0) 3726 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); 3727 else { 3728 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); 3729 *Flag = P.getValue(2); 3730 } 3731 Chain = P.getValue(1); 3732 3733 // If the source register was virtual and if we know something about it, 3734 // add an assert node. 3735 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 3736 RegisterVT.isInteger() && !RegisterVT.isVector()) { 3737 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 3738 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 3739 if (FLI.LiveOutRegInfo.size() > SlotNo) { 3740 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 3741 3742 unsigned RegSize = RegisterVT.getSizeInBits(); 3743 unsigned NumSignBits = LOI.NumSignBits; 3744 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 3745 3746 // FIXME: We capture more information than the dag can represent. For 3747 // now, just use the tightest assertzext/assertsext possible. 3748 bool isSExt = true; 3749 MVT FromVT(MVT::Other); 3750 if (NumSignBits == RegSize) 3751 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 3752 else if (NumZeroBits >= RegSize-1) 3753 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 3754 else if (NumSignBits > RegSize-8) 3755 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 3756 else if (NumZeroBits >= RegSize-9) 3757 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 3758 else if (NumSignBits > RegSize-16) 3759 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 3760 else if (NumZeroBits >= RegSize-17) 3761 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 3762 else if (NumSignBits > RegSize-32) 3763 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 3764 else if (NumZeroBits >= RegSize-33) 3765 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 3766 3767 if (FromVT != MVT::Other) { 3768 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, 3769 RegisterVT, P, DAG.getValueType(FromVT)); 3770 3771 } 3772 } 3773 } 3774 3775 Parts[Part+i] = P; 3776 } 3777 3778 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT, 3779 ValueVT); 3780 Part += NumRegs; 3781 } 3782 3783 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 3784 &Values[0], ValueVTs.size()); 3785} 3786 3787/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3788/// specified value into the registers specified by this object. This uses 3789/// Chain/Flag as the input and updates them for the output Chain/Flag. 3790/// If the Flag pointer is NULL, no flag is used. 3791void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, 3792 SDValue &Chain, SDValue *Flag) const { 3793 // Get the list of the values's legal parts. 3794 unsigned NumRegs = Regs.size(); 3795 SmallVector<SDValue, 8> Parts(NumRegs); 3796 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 3797 MVT ValueVT = ValueVTs[Value]; 3798 unsigned NumParts = TLI->getNumRegisters(ValueVT); 3799 MVT RegisterVT = RegVTs[Value]; 3800 3801 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value), 3802 &Parts[Part], NumParts, RegisterVT); 3803 Part += NumParts; 3804 } 3805 3806 // Copy the parts into the registers. 3807 SmallVector<SDValue, 8> Chains(NumRegs); 3808 for (unsigned i = 0; i != NumRegs; ++i) { 3809 SDValue Part; 3810 if (Flag == 0) 3811 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3812 else { 3813 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); 3814 *Flag = Part.getValue(1); 3815 } 3816 Chains[i] = Part.getValue(0); 3817 } 3818 3819 if (NumRegs == 1 || Flag) 3820 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 3821 // flagged to it. That is the CopyToReg nodes and the user are considered 3822 // a single scheduling unit. If we create a TokenFactor and return it as 3823 // chain, then the TokenFactor is both a predecessor (operand) of the 3824 // user as well as a successor (the TF operands are flagged to the user). 3825 // c1, f1 = CopyToReg 3826 // c2, f2 = CopyToReg 3827 // c3 = TokenFactor c1, c2 3828 // ... 3829 // = op c3, ..., f2 3830 Chain = Chains[NumRegs-1]; 3831 else 3832 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 3833} 3834 3835/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3836/// operand list. This adds the code marker and includes the number of 3837/// values added into it. 3838void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3839 std::vector<SDValue> &Ops) const { 3840 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3841 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3842 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 3843 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); 3844 MVT RegisterVT = RegVTs[Value]; 3845 for (unsigned i = 0; i != NumRegs; ++i) 3846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 3847 } 3848} 3849 3850/// isAllocatableRegister - If the specified register is safe to allocate, 3851/// i.e. it isn't a stack pointer or some other special register, return the 3852/// register class for the register. Otherwise, return null. 3853static const TargetRegisterClass * 3854isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3855 const TargetLowering &TLI, 3856 const TargetRegisterInfo *TRI) { 3857 MVT FoundVT = MVT::Other; 3858 const TargetRegisterClass *FoundRC = 0; 3859 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 3860 E = TRI->regclass_end(); RCI != E; ++RCI) { 3861 MVT ThisVT = MVT::Other; 3862 3863 const TargetRegisterClass *RC = *RCI; 3864 // If none of the the value types for this register class are valid, we 3865 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3866 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3867 I != E; ++I) { 3868 if (TLI.isTypeLegal(*I)) { 3869 // If we have already found this register in a different register class, 3870 // choose the one with the largest VT specified. For example, on 3871 // PowerPC, we favor f64 register classes over f32. 3872 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 3873 ThisVT = *I; 3874 break; 3875 } 3876 } 3877 } 3878 3879 if (ThisVT == MVT::Other) continue; 3880 3881 // NOTE: This isn't ideal. In particular, this might allocate the 3882 // frame pointer in functions that need it (due to them not being taken 3883 // out of allocation, because a variable sized allocation hasn't been seen 3884 // yet). This is a slight code pessimization, but should still work. 3885 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3886 E = RC->allocation_order_end(MF); I != E; ++I) 3887 if (*I == Reg) { 3888 // We found a matching register class. Keep looking at others in case 3889 // we find one with larger registers that this physreg is also in. 3890 FoundRC = RC; 3891 FoundVT = ThisVT; 3892 break; 3893 } 3894 } 3895 return FoundRC; 3896} 3897 3898 3899namespace { 3900/// AsmOperandInfo - This contains information for each constraint that we are 3901/// lowering. 3902struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 3903 /// CallOperand - If this is the result output operand or a clobber 3904 /// this is null, otherwise it is the incoming operand to the CallInst. 3905 /// This gets modified as the asm is processed. 3906 SDValue CallOperand; 3907 3908 /// AssignedRegs - If this is a register or register class operand, this 3909 /// contains the set of register corresponding to the operand. 3910 RegsForValue AssignedRegs; 3911 3912 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3913 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 3914 } 3915 3916 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3917 /// busy in OutputRegs/InputRegs. 3918 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3919 std::set<unsigned> &OutputRegs, 3920 std::set<unsigned> &InputRegs, 3921 const TargetRegisterInfo &TRI) const { 3922 if (isOutReg) { 3923 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3924 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 3925 } 3926 if (isInReg) { 3927 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 3928 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 3929 } 3930 } 3931 3932private: 3933 /// MarkRegAndAliases - Mark the specified register and all aliases in the 3934 /// specified set. 3935 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 3936 const TargetRegisterInfo &TRI) { 3937 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 3938 Regs.insert(Reg); 3939 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 3940 for (; *Aliases; ++Aliases) 3941 Regs.insert(*Aliases); 3942 } 3943}; 3944} // end anon namespace. 3945 3946 3947/// GetRegistersForValue - Assign registers (virtual or physical) for the 3948/// specified operand. We prefer to assign virtual registers, to allow the 3949/// register allocator handle the assignment process. However, if the asm uses 3950/// features that we can't model on machineinstrs, we have SDISel do the 3951/// allocation. This produces generally horrible, but correct, code. 3952/// 3953/// OpInfo describes the operand. 3954/// HasEarlyClobber is true if there are any early clobber constraints (=&r) 3955/// or any explicitly clobbered registers. 3956/// Input and OutputRegs are the set of already allocated physical registers. 3957/// 3958void SelectionDAGLowering:: 3959GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, 3960 std::set<unsigned> &OutputRegs, 3961 std::set<unsigned> &InputRegs) { 3962 // Compute whether this value requires an input register, an output register, 3963 // or both. 3964 bool isOutReg = false; 3965 bool isInReg = false; 3966 switch (OpInfo.Type) { 3967 case InlineAsm::isOutput: 3968 isOutReg = true; 3969 3970 // If this is an early-clobber output, or if there is an input 3971 // constraint that matches this, we need to reserve the input register 3972 // so no other inputs allocate to it. 3973 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3974 break; 3975 case InlineAsm::isInput: 3976 isInReg = true; 3977 isOutReg = false; 3978 break; 3979 case InlineAsm::isClobber: 3980 isOutReg = true; 3981 isInReg = true; 3982 break; 3983 } 3984 3985 3986 MachineFunction &MF = DAG.getMachineFunction(); 3987 SmallVector<unsigned, 4> Regs; 3988 3989 // If this is a constraint for a single physreg, or a constraint for a 3990 // register class, find it. 3991 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3992 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3993 OpInfo.ConstraintVT); 3994 3995 unsigned NumRegs = 1; 3996 if (OpInfo.ConstraintVT != MVT::Other) 3997 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3998 MVT RegVT; 3999 MVT ValueVT = OpInfo.ConstraintVT; 4000 4001 4002 // If this is a constraint for a specific physical register, like {r17}, 4003 // assign it now. 4004 if (PhysReg.first) { 4005 if (OpInfo.ConstraintVT == MVT::Other) 4006 ValueVT = *PhysReg.second->vt_begin(); 4007 4008 // Get the actual register value type. This is important, because the user 4009 // may have asked for (e.g.) the AX register in i32 type. We need to 4010 // remember that AX is actually i16 to get the right extension. 4011 RegVT = *PhysReg.second->vt_begin(); 4012 4013 // This is a explicit reference to a physical register. 4014 Regs.push_back(PhysReg.first); 4015 4016 // If this is an expanded reference, add the rest of the regs to Regs. 4017 if (NumRegs != 1) { 4018 TargetRegisterClass::iterator I = PhysReg.second->begin(); 4019 for (; *I != PhysReg.first; ++I) 4020 assert(I != PhysReg.second->end() && "Didn't find reg!"); 4021 4022 // Already added the first reg. 4023 --NumRegs; ++I; 4024 for (; NumRegs; --NumRegs, ++I) { 4025 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); 4026 Regs.push_back(*I); 4027 } 4028 } 4029 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4030 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4031 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4032 return; 4033 } 4034 4035 // Otherwise, if this was a reference to an LLVM register class, create vregs 4036 // for this reference. 4037 std::vector<unsigned> RegClassRegs; 4038 const TargetRegisterClass *RC = PhysReg.second; 4039 if (RC) { 4040 // If this is an early clobber or tied register, our regalloc doesn't know 4041 // how to maintain the constraint. If it isn't, go ahead and create vreg 4042 // and let the regalloc do the right thing. 4043 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 4044 // If there is some other early clobber and this is an input register, 4045 // then we are forced to pre-allocate the input reg so it doesn't 4046 // conflict with the earlyclobber. 4047 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 4048 RegVT = *PhysReg.second->vt_begin(); 4049 4050 if (OpInfo.ConstraintVT == MVT::Other) 4051 ValueVT = RegVT; 4052 4053 // Create the appropriate number of virtual registers. 4054 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4055 for (; NumRegs; --NumRegs) 4056 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); 4057 4058 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 4059 return; 4060 } 4061 4062 // Otherwise, we can't allocate it. Let the code below figure out how to 4063 // maintain these constraints. 4064 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 4065 4066 } else { 4067 // This is a reference to a register class that doesn't directly correspond 4068 // to an LLVM register class. Allocate NumRegs consecutive, available, 4069 // registers from the class. 4070 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 4071 OpInfo.ConstraintVT); 4072 } 4073 4074 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4075 unsigned NumAllocated = 0; 4076 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 4077 unsigned Reg = RegClassRegs[i]; 4078 // See if this register is available. 4079 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 4080 (isInReg && InputRegs.count(Reg))) { // Already used. 4081 // Make sure we find consecutive registers. 4082 NumAllocated = 0; 4083 continue; 4084 } 4085 4086 // Check to see if this register is allocatable (i.e. don't give out the 4087 // stack pointer). 4088 if (RC == 0) { 4089 RC = isAllocatableRegister(Reg, MF, TLI, TRI); 4090 if (!RC) { // Couldn't allocate this register. 4091 // Reset NumAllocated to make sure we return consecutive registers. 4092 NumAllocated = 0; 4093 continue; 4094 } 4095 } 4096 4097 // Okay, this register is good, we can use it. 4098 ++NumAllocated; 4099 4100 // If we allocated enough consecutive registers, succeed. 4101 if (NumAllocated == NumRegs) { 4102 unsigned RegStart = (i-NumAllocated)+1; 4103 unsigned RegEnd = i+1; 4104 // Mark all of the allocated registers used. 4105 for (unsigned i = RegStart; i != RegEnd; ++i) 4106 Regs.push_back(RegClassRegs[i]); 4107 4108 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 4109 OpInfo.ConstraintVT); 4110 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 4111 return; 4112 } 4113 } 4114 4115 // Otherwise, we couldn't allocate enough registers for this. 4116} 4117 4118 4119/// visitInlineAsm - Handle a call to an InlineAsm object. 4120/// 4121void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 4122 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 4123 4124 /// ConstraintOperands - Information about all of the constraints. 4125 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 4126 4127 SDValue Chain = getRoot(); 4128 SDValue Flag; 4129 4130 std::set<unsigned> OutputRegs, InputRegs; 4131 4132 // Do a prepass over the constraints, canonicalizing them, and building up the 4133 // ConstraintOperands list. 4134 std::vector<InlineAsm::ConstraintInfo> 4135 ConstraintInfos = IA->ParseConstraints(); 4136 4137 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 4138 // constraint. If so, we can't let the register allocator allocate any input 4139 // registers, because it will not know to avoid the earlyclobbered output reg. 4140 bool SawEarlyClobber = false; 4141 4142 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 4143 unsigned ResNo = 0; // ResNo - The result number of the next output. 4144 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 4145 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 4146 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 4147 4148 MVT OpVT = MVT::Other; 4149 4150 // Compute the value type for each operand. 4151 switch (OpInfo.Type) { 4152 case InlineAsm::isOutput: 4153 // Indirect outputs just consume an argument. 4154 if (OpInfo.isIndirect) { 4155 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4156 break; 4157 } 4158 // The return value of the call is this value. As such, there is no 4159 // corresponding argument. 4160 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4161 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 4162 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 4163 } else { 4164 assert(ResNo == 0 && "Asm only has one result!"); 4165 OpVT = TLI.getValueType(CS.getType()); 4166 } 4167 ++ResNo; 4168 break; 4169 case InlineAsm::isInput: 4170 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 4171 break; 4172 case InlineAsm::isClobber: 4173 // Nothing to do. 4174 break; 4175 } 4176 4177 // If this is an input or an indirect output, process the call argument. 4178 // BasicBlocks are labels, currently appearing only in asm's. 4179 if (OpInfo.CallOperandVal) { 4180 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) 4181 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 4182 else { 4183 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 4184 const Type *OpTy = OpInfo.CallOperandVal->getType(); 4185 // If this is an indirect operand, the operand is a pointer to the 4186 // accessed type. 4187 if (OpInfo.isIndirect) 4188 OpTy = cast<PointerType>(OpTy)->getElementType(); 4189 4190 // If OpTy is not a single value, it may be a struct/union that we 4191 // can tile with integers. 4192 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4193 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4194 switch (BitSize) { 4195 default: break; 4196 case 1: 4197 case 8: 4198 case 16: 4199 case 32: 4200 case 64: 4201 OpTy = IntegerType::get(BitSize); 4202 break; 4203 } 4204 } 4205 4206 OpVT = TLI.getValueType(OpTy, true); 4207 } 4208 } 4209 4210 OpInfo.ConstraintVT = OpVT; 4211 4212 // Compute the constraint code and ConstraintType to use. 4213 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 4214 4215 // Keep track of whether we see an earlyclobber. 4216 SawEarlyClobber |= OpInfo.isEarlyClobber; 4217 4218 // If we see a clobber of a register, it is an early clobber. 4219 if (!SawEarlyClobber && 4220 OpInfo.Type == InlineAsm::isClobber && 4221 OpInfo.ConstraintType == TargetLowering::C_Register) { 4222 // Note that we want to ignore things that we don't trick here, like 4223 // dirflag, fpsr, flags, etc. 4224 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 4225 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 4226 OpInfo.ConstraintVT); 4227 if (PhysReg.first || PhysReg.second) { 4228 // This is a register we know of. 4229 SawEarlyClobber = true; 4230 } 4231 } 4232 4233 // If this is a memory input, and if the operand is not indirect, do what we 4234 // need to to provide an address for the memory input. 4235 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 4236 !OpInfo.isIndirect) { 4237 assert(OpInfo.Type == InlineAsm::isInput && 4238 "Can only indirectify direct input operands!"); 4239 4240 // Memory operands really want the address of the value. If we don't have 4241 // an indirect input, put it in the constpool if we can, otherwise spill 4242 // it to a stack slot. 4243 4244 // If the operand is a float, integer, or vector constant, spill to a 4245 // constant pool entry to get its address. 4246 Value *OpVal = OpInfo.CallOperandVal; 4247 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 4248 isa<ConstantVector>(OpVal)) { 4249 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 4250 TLI.getPointerTy()); 4251 } else { 4252 // Otherwise, create a stack slot and emit a store to it before the 4253 // asm. 4254 const Type *Ty = OpVal->getType(); 4255 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 4256 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 4257 MachineFunction &MF = DAG.getMachineFunction(); 4258 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 4259 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4260 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 4261 OpInfo.CallOperand = StackSlot; 4262 } 4263 4264 // There is no longer a Value* corresponding to this operand. 4265 OpInfo.CallOperandVal = 0; 4266 // It is now an indirect operand. 4267 OpInfo.isIndirect = true; 4268 } 4269 4270 // If this constraint is for a specific register, allocate it before 4271 // anything else. 4272 if (OpInfo.ConstraintType == TargetLowering::C_Register) 4273 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4274 } 4275 ConstraintInfos.clear(); 4276 4277 4278 // Second pass - Loop over all of the operands, assigning virtual or physregs 4279 // to registerclass operands. 4280 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4281 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4282 4283 // C_Register operands have already been allocated, Other/Memory don't need 4284 // to be. 4285 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 4286 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 4287 } 4288 4289 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 4290 std::vector<SDValue> AsmNodeOperands; 4291 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 4292 AsmNodeOperands.push_back( 4293 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 4294 4295 4296 // Loop over all of the inputs, copying the operand values into the 4297 // appropriate registers and processing the output regs. 4298 RegsForValue RetValRegs; 4299 4300 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 4301 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 4302 4303 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 4304 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 4305 4306 switch (OpInfo.Type) { 4307 case InlineAsm::isOutput: { 4308 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 4309 OpInfo.ConstraintType != TargetLowering::C_Register) { 4310 // Memory output, or 'other' output (e.g. 'X' constraint). 4311 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 4312 4313 // Add information to the INLINEASM node to know about this output. 4314 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4315 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4316 TLI.getPointerTy())); 4317 AsmNodeOperands.push_back(OpInfo.CallOperand); 4318 break; 4319 } 4320 4321 // Otherwise, this is a register or register class output. 4322 4323 // Copy the output from the appropriate register. Find a register that 4324 // we can use. 4325 if (OpInfo.AssignedRegs.Regs.empty()) { 4326 cerr << "Couldn't allocate output reg for constraint '" 4327 << OpInfo.ConstraintCode << "'!\n"; 4328 exit(1); 4329 } 4330 4331 // If this is an indirect operand, store through the pointer after the 4332 // asm. 4333 if (OpInfo.isIndirect) { 4334 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 4335 OpInfo.CallOperandVal)); 4336 } else { 4337 // This is the result value of the call. 4338 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 4339 // Concatenate this output onto the outputs list. 4340 RetValRegs.append(OpInfo.AssignedRegs); 4341 } 4342 4343 // Add information to the INLINEASM node to know that this register is 4344 // set. 4345 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 4346 AsmNodeOperands); 4347 break; 4348 } 4349 case InlineAsm::isInput: { 4350 SDValue InOperandVal = OpInfo.CallOperand; 4351 4352 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 4353 // If this is required to match an output register we have already set, 4354 // just use its register. 4355 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 4356 4357 // Scan until we find the definition we already emitted of this operand. 4358 // When we find it, create a RegsForValue operand. 4359 unsigned CurOp = 2; // The first operand. 4360 for (; OperandNo; --OperandNo) { 4361 // Advance to the next operand. 4362 unsigned NumOps = 4363 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4364 assert(((NumOps & 7) == 2 /*REGDEF*/ || 4365 (NumOps & 7) == 4 /*MEM*/) && 4366 "Skipped past definitions?"); 4367 CurOp += (NumOps>>3)+1; 4368 } 4369 4370 unsigned NumOps = 4371 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 4372 if ((NumOps & 7) == 2 /*REGDEF*/) { 4373 // Add NumOps>>3 registers to MatchedRegs. 4374 RegsForValue MatchedRegs; 4375 MatchedRegs.TLI = &TLI; 4376 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 4377 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType()); 4378 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 4379 unsigned Reg = 4380 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 4381 MatchedRegs.Regs.push_back(Reg); 4382 } 4383 4384 // Use the produced MatchedRegs object to 4385 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4386 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 4387 break; 4388 } else { 4389 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 4390 assert((NumOps >> 3) == 1 && "Unexpected number of operands"); 4391 // Add information to the INLINEASM node to know about this input. 4392 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4393 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4394 TLI.getPointerTy())); 4395 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 4396 break; 4397 } 4398 } 4399 4400 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 4401 assert(!OpInfo.isIndirect && 4402 "Don't know how to handle indirect other inputs yet!"); 4403 4404 std::vector<SDValue> Ops; 4405 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 4406 Ops, DAG); 4407 if (Ops.empty()) { 4408 cerr << "Invalid operand for inline asm constraint '" 4409 << OpInfo.ConstraintCode << "'!\n"; 4410 exit(1); 4411 } 4412 4413 // Add information to the INLINEASM node to know about this input. 4414 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 4415 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4416 TLI.getPointerTy())); 4417 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 4418 break; 4419 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 4420 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 4421 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 4422 "Memory operands expect pointer values"); 4423 4424 // Add information to the INLINEASM node to know about this input. 4425 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 4426 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 4427 TLI.getPointerTy())); 4428 AsmNodeOperands.push_back(InOperandVal); 4429 break; 4430 } 4431 4432 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 4433 OpInfo.ConstraintType == TargetLowering::C_Register) && 4434 "Unknown constraint type!"); 4435 assert(!OpInfo.isIndirect && 4436 "Don't know how to handle indirect register inputs yet!"); 4437 4438 // Copy the input into the appropriate registers. 4439 assert(!OpInfo.AssignedRegs.Regs.empty() && 4440 "Couldn't allocate input reg!"); 4441 4442 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 4443 4444 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 4445 AsmNodeOperands); 4446 break; 4447 } 4448 case InlineAsm::isClobber: { 4449 // Add the clobbered value to the operand list, so that the register 4450 // allocator is aware that the physreg got clobbered. 4451 if (!OpInfo.AssignedRegs.Regs.empty()) 4452 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 4453 AsmNodeOperands); 4454 break; 4455 } 4456 } 4457 } 4458 4459 // Finish up input operands. 4460 AsmNodeOperands[0] = Chain; 4461 if (Flag.Val) AsmNodeOperands.push_back(Flag); 4462 4463 Chain = DAG.getNode(ISD::INLINEASM, 4464 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 4465 &AsmNodeOperands[0], AsmNodeOperands.size()); 4466 Flag = Chain.getValue(1); 4467 4468 // If this asm returns a register value, copy the result from that register 4469 // and set it as the value of the call. 4470 if (!RetValRegs.Regs.empty()) { 4471 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 4472 4473 // If any of the results of the inline asm is a vector, it may have the 4474 // wrong width/num elts. This can happen for register classes that can 4475 // contain multiple different value types. The preg or vreg allocated may 4476 // not have the same VT as was expected. Convert it to the right type with 4477 // bit_convert. 4478 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) { 4479 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) { 4480 if (Val.Val->getValueType(i).isVector()) 4481 Val = DAG.getNode(ISD::BIT_CONVERT, 4482 TLI.getValueType(ResSTy->getElementType(i)), Val); 4483 } 4484 } else { 4485 if (Val.getValueType().isVector()) 4486 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()), 4487 Val); 4488 } 4489 4490 setValue(CS.getInstruction(), Val); 4491 } 4492 4493 std::vector<std::pair<SDValue, Value*> > StoresToEmit; 4494 4495 // Process indirect outputs, first output all of the flagged copies out of 4496 // physregs. 4497 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 4498 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 4499 Value *Ptr = IndirectStoresToEmit[i].second; 4500 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 4501 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 4502 } 4503 4504 // Emit the non-flagged stores from the physregs. 4505 SmallVector<SDValue, 8> OutChains; 4506 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 4507 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 4508 getValue(StoresToEmit[i].second), 4509 StoresToEmit[i].second, 0)); 4510 if (!OutChains.empty()) 4511 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4512 &OutChains[0], OutChains.size()); 4513 DAG.setRoot(Chain); 4514} 4515 4516 4517void SelectionDAGLowering::visitMalloc(MallocInst &I) { 4518 SDValue Src = getValue(I.getOperand(0)); 4519 4520 MVT IntPtr = TLI.getPointerTy(); 4521 4522 if (IntPtr.bitsLT(Src.getValueType())) 4523 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 4524 else if (IntPtr.bitsGT(Src.getValueType())) 4525 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 4526 4527 // Scale the source by the type size. 4528 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 4529 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 4530 Src, DAG.getIntPtrConstant(ElementSize)); 4531 4532 TargetLowering::ArgListTy Args; 4533 TargetLowering::ArgListEntry Entry; 4534 Entry.Node = Src; 4535 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4536 Args.push_back(Entry); 4537 4538 std::pair<SDValue,SDValue> Result = 4539 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C, 4540 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG); 4541 setValue(&I, Result.first); // Pointers always fit in registers 4542 DAG.setRoot(Result.second); 4543} 4544 4545void SelectionDAGLowering::visitFree(FreeInst &I) { 4546 TargetLowering::ArgListTy Args; 4547 TargetLowering::ArgListEntry Entry; 4548 Entry.Node = getValue(I.getOperand(0)); 4549 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 4550 Args.push_back(Entry); 4551 MVT IntPtr = TLI.getPointerTy(); 4552 std::pair<SDValue,SDValue> Result = 4553 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, 4554 CallingConv::C, true, 4555 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 4556 DAG.setRoot(Result.second); 4557} 4558 4559// EmitInstrWithCustomInserter - This method should be implemented by targets 4560// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 4561// instructions are special in various ways, which require special support to 4562// insert. The specified MachineInstr is created but not inserted into any 4563// basic blocks, and the scheduler passes ownership of it to this method. 4564MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4565 MachineBasicBlock *MBB) { 4566 cerr << "If a target marks an instruction with " 4567 << "'usesCustomDAGSchedInserter', it must implement " 4568 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 4569 abort(); 4570 return 0; 4571} 4572 4573void SelectionDAGLowering::visitVAStart(CallInst &I) { 4574 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 4575 getValue(I.getOperand(1)), 4576 DAG.getSrcValue(I.getOperand(1)))); 4577} 4578 4579void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 4580 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 4581 getValue(I.getOperand(0)), 4582 DAG.getSrcValue(I.getOperand(0))); 4583 setValue(&I, V); 4584 DAG.setRoot(V.getValue(1)); 4585} 4586 4587void SelectionDAGLowering::visitVAEnd(CallInst &I) { 4588 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 4589 getValue(I.getOperand(1)), 4590 DAG.getSrcValue(I.getOperand(1)))); 4591} 4592 4593void SelectionDAGLowering::visitVACopy(CallInst &I) { 4594 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 4595 getValue(I.getOperand(1)), 4596 getValue(I.getOperand(2)), 4597 DAG.getSrcValue(I.getOperand(1)), 4598 DAG.getSrcValue(I.getOperand(2)))); 4599} 4600 4601/// TargetLowering::LowerArguments - This is the default LowerArguments 4602/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 4603/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 4604/// integrated into SDISel. 4605void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, 4606 SmallVectorImpl<SDValue> &ArgValues) { 4607 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 4608 SmallVector<SDValue, 3+16> Ops; 4609 Ops.push_back(DAG.getRoot()); 4610 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 4611 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 4612 4613 // Add one result value for each formal argument. 4614 SmallVector<MVT, 16> RetVals; 4615 unsigned j = 1; 4616 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 4617 I != E; ++I, ++j) { 4618 SmallVector<MVT, 4> ValueVTs; 4619 ComputeValueVTs(*this, I->getType(), ValueVTs); 4620 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4621 Value != NumValues; ++Value) { 4622 MVT VT = ValueVTs[Value]; 4623 const Type *ArgTy = VT.getTypeForMVT(); 4624 ISD::ArgFlagsTy Flags; 4625 unsigned OriginalAlignment = 4626 getTargetData()->getABITypeAlignment(ArgTy); 4627 4628 if (F.paramHasAttr(j, ParamAttr::ZExt)) 4629 Flags.setZExt(); 4630 if (F.paramHasAttr(j, ParamAttr::SExt)) 4631 Flags.setSExt(); 4632 if (F.paramHasAttr(j, ParamAttr::InReg)) 4633 Flags.setInReg(); 4634 if (F.paramHasAttr(j, ParamAttr::StructRet)) 4635 Flags.setSRet(); 4636 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 4637 Flags.setByVal(); 4638 const PointerType *Ty = cast<PointerType>(I->getType()); 4639 const Type *ElementTy = Ty->getElementType(); 4640 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4641 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4642 // For ByVal, alignment should be passed from FE. BE will guess if 4643 // this info is not there but there are cases it cannot get right. 4644 if (F.getParamAlignment(j)) 4645 FrameAlign = F.getParamAlignment(j); 4646 Flags.setByValAlign(FrameAlign); 4647 Flags.setByValSize(FrameSize); 4648 } 4649 if (F.paramHasAttr(j, ParamAttr::Nest)) 4650 Flags.setNest(); 4651 Flags.setOrigAlign(OriginalAlignment); 4652 4653 MVT RegisterVT = getRegisterType(VT); 4654 unsigned NumRegs = getNumRegisters(VT); 4655 for (unsigned i = 0; i != NumRegs; ++i) { 4656 RetVals.push_back(RegisterVT); 4657 ISD::ArgFlagsTy MyFlags = Flags; 4658 if (NumRegs > 1 && i == 0) 4659 MyFlags.setSplit(); 4660 // if it isn't first piece, alignment must be 1 4661 else if (i > 0) 4662 MyFlags.setOrigAlign(1); 4663 Ops.push_back(DAG.getArgFlags(MyFlags)); 4664 } 4665 } 4666 } 4667 4668 RetVals.push_back(MVT::Other); 4669 4670 // Create the node. 4671 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 4672 DAG.getVTList(&RetVals[0], RetVals.size()), 4673 &Ops[0], Ops.size()).Val; 4674 4675 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but 4676 // allows exposing the loads that may be part of the argument access to the 4677 // first DAGCombiner pass. 4678 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG); 4679 4680 // The number of results should match up, except that the lowered one may have 4681 // an extra flag result. 4682 assert((Result->getNumValues() == TmpRes.Val->getNumValues() || 4683 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && 4684 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) 4685 && "Lowering produced unexpected number of results!"); 4686 4687 // The FORMAL_ARGUMENTS node itself is likely no longer needed. 4688 if (Result != TmpRes.Val && Result->use_empty()) { 4689 HandleSDNode Dummy(DAG.getRoot()); 4690 DAG.RemoveDeadNode(Result); 4691 } 4692 4693 Result = TmpRes.Val; 4694 4695 unsigned NumArgRegs = Result->getNumValues() - 1; 4696 DAG.setRoot(SDValue(Result, NumArgRegs)); 4697 4698 // Set up the return result vector. 4699 unsigned i = 0; 4700 unsigned Idx = 1; 4701 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 4702 ++I, ++Idx) { 4703 SmallVector<MVT, 4> ValueVTs; 4704 ComputeValueVTs(*this, I->getType(), ValueVTs); 4705 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4706 Value != NumValues; ++Value) { 4707 MVT VT = ValueVTs[Value]; 4708 MVT PartVT = getRegisterType(VT); 4709 4710 unsigned NumParts = getNumRegisters(VT); 4711 SmallVector<SDValue, 4> Parts(NumParts); 4712 for (unsigned j = 0; j != NumParts; ++j) 4713 Parts[j] = SDValue(Result, i++); 4714 4715 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4716 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 4717 AssertOp = ISD::AssertSext; 4718 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 4719 AssertOp = ISD::AssertZext; 4720 4721 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, 4722 AssertOp)); 4723 } 4724 } 4725 assert(i == NumArgRegs && "Argument register count mismatch!"); 4726} 4727 4728 4729/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4730/// implementation, which just inserts an ISD::CALL node, which is later custom 4731/// lowered by the target to something concrete. FIXME: When all targets are 4732/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4733std::pair<SDValue, SDValue> 4734TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 4735 bool RetSExt, bool RetZExt, bool isVarArg, 4736 unsigned CallingConv, bool isTailCall, 4737 SDValue Callee, 4738 ArgListTy &Args, SelectionDAG &DAG) { 4739 SmallVector<SDValue, 32> Ops; 4740 Ops.push_back(Chain); // Op#0 - Chain 4741 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4742 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4743 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4744 Ops.push_back(Callee); 4745 4746 // Handle all of the outgoing arguments. 4747 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4748 SmallVector<MVT, 4> ValueVTs; 4749 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 4750 for (unsigned Value = 0, NumValues = ValueVTs.size(); 4751 Value != NumValues; ++Value) { 4752 MVT VT = ValueVTs[Value]; 4753 const Type *ArgTy = VT.getTypeForMVT(); 4754 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value); 4755 ISD::ArgFlagsTy Flags; 4756 unsigned OriginalAlignment = 4757 getTargetData()->getABITypeAlignment(ArgTy); 4758 4759 if (Args[i].isZExt) 4760 Flags.setZExt(); 4761 if (Args[i].isSExt) 4762 Flags.setSExt(); 4763 if (Args[i].isInReg) 4764 Flags.setInReg(); 4765 if (Args[i].isSRet) 4766 Flags.setSRet(); 4767 if (Args[i].isByVal) { 4768 Flags.setByVal(); 4769 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4770 const Type *ElementTy = Ty->getElementType(); 4771 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 4772 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); 4773 // For ByVal, alignment should come from FE. BE will guess if this 4774 // info is not there but there are cases it cannot get right. 4775 if (Args[i].Alignment) 4776 FrameAlign = Args[i].Alignment; 4777 Flags.setByValAlign(FrameAlign); 4778 Flags.setByValSize(FrameSize); 4779 } 4780 if (Args[i].isNest) 4781 Flags.setNest(); 4782 Flags.setOrigAlign(OriginalAlignment); 4783 4784 MVT PartVT = getRegisterType(VT); 4785 unsigned NumParts = getNumRegisters(VT); 4786 SmallVector<SDValue, 4> Parts(NumParts); 4787 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 4788 4789 if (Args[i].isSExt) 4790 ExtendKind = ISD::SIGN_EXTEND; 4791 else if (Args[i].isZExt) 4792 ExtendKind = ISD::ZERO_EXTEND; 4793 4794 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); 4795 4796 for (unsigned i = 0; i != NumParts; ++i) { 4797 // if it isn't first piece, alignment must be 1 4798 ISD::ArgFlagsTy MyFlags = Flags; 4799 if (NumParts > 1 && i == 0) 4800 MyFlags.setSplit(); 4801 else if (i != 0) 4802 MyFlags.setOrigAlign(1); 4803 4804 Ops.push_back(Parts[i]); 4805 Ops.push_back(DAG.getArgFlags(MyFlags)); 4806 } 4807 } 4808 } 4809 4810 // Figure out the result value types. We start by making a list of 4811 // the potentially illegal return value types. 4812 SmallVector<MVT, 4> LoweredRetTys; 4813 SmallVector<MVT, 4> RetTys; 4814 ComputeValueVTs(*this, RetTy, RetTys); 4815 4816 // Then we translate that to a list of legal types. 4817 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4818 MVT VT = RetTys[I]; 4819 MVT RegisterVT = getRegisterType(VT); 4820 unsigned NumRegs = getNumRegisters(VT); 4821 for (unsigned i = 0; i != NumRegs; ++i) 4822 LoweredRetTys.push_back(RegisterVT); 4823 } 4824 4825 LoweredRetTys.push_back(MVT::Other); // Always has a chain. 4826 4827 // Create the CALL node. 4828 SDValue Res = DAG.getNode(ISD::CALL, 4829 DAG.getVTList(&LoweredRetTys[0], 4830 LoweredRetTys.size()), 4831 &Ops[0], Ops.size()); 4832 Chain = Res.getValue(LoweredRetTys.size() - 1); 4833 4834 // Gather up the call result into a single value. 4835 if (RetTy != Type::VoidTy) { 4836 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4837 4838 if (RetSExt) 4839 AssertOp = ISD::AssertSext; 4840 else if (RetZExt) 4841 AssertOp = ISD::AssertZext; 4842 4843 SmallVector<SDValue, 4> ReturnValues; 4844 unsigned RegNo = 0; 4845 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4846 MVT VT = RetTys[I]; 4847 MVT RegisterVT = getRegisterType(VT); 4848 unsigned NumRegs = getNumRegisters(VT); 4849 unsigned RegNoEnd = NumRegs + RegNo; 4850 SmallVector<SDValue, 4> Results; 4851 for (; RegNo != RegNoEnd; ++RegNo) 4852 Results.push_back(Res.getValue(RegNo)); 4853 SDValue ReturnValue = 4854 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, 4855 AssertOp); 4856 ReturnValues.push_back(ReturnValue); 4857 } 4858 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()), 4859 &ReturnValues[0], ReturnValues.size()); 4860 } 4861 4862 return std::make_pair(Res, Chain); 4863} 4864 4865SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 4866 assert(0 && "LowerOperation not implemented for this target!"); 4867 abort(); 4868 return SDValue(); 4869} 4870 4871 4872//===----------------------------------------------------------------------===// 4873// SelectionDAGISel code 4874//===----------------------------------------------------------------------===// 4875 4876unsigned SelectionDAGISel::MakeReg(MVT VT) { 4877 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 4878} 4879 4880void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4881 AU.addRequired<AliasAnalysis>(); 4882 AU.addRequired<CollectorModuleMetadata>(); 4883 AU.setPreservesAll(); 4884} 4885 4886bool SelectionDAGISel::runOnFunction(Function &Fn) { 4887 // Get alias analysis for load/store combining. 4888 AA = &getAnalysis<AliasAnalysis>(); 4889 4890 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4891 if (MF.getFunction()->hasCollector()) 4892 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction()); 4893 else 4894 GCI = 0; 4895 RegInfo = &MF.getRegInfo(); 4896 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4897 4898 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4899 4900 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4901 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4902 // Mark landing pad. 4903 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4904 4905 SelectAllBasicBlocks(Fn, MF, FuncInfo); 4906 4907 // Add function live-ins to entry block live-in set. 4908 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4909 BB = FuncInfo.MBBMap[EntryBB]; 4910 if (!RegInfo->livein_empty()) 4911 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 4912 E = RegInfo->livein_end(); I != E; ++I) 4913 BB->addLiveIn(I->first); 4914 4915#ifndef NDEBUG 4916 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4917 "Not all catch info was assigned to a landing pad!"); 4918#endif 4919 4920 return true; 4921} 4922 4923void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) { 4924 SDValue Op = getValue(V); 4925 assert((Op.getOpcode() != ISD::CopyFromReg || 4926 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4927 "Copy from a reg to the same reg!"); 4928 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 4929 4930 RegsForValue RFV(TLI, Reg, V->getType()); 4931 SDValue Chain = DAG.getEntryNode(); 4932 RFV.getCopyToRegs(Op, DAG, Chain, 0); 4933 PendingExports.push_back(Chain); 4934} 4935 4936void SelectionDAGISel:: 4937LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { 4938 // If this is the entry block, emit arguments. 4939 Function &F = *LLVMBB->getParent(); 4940 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4941 SDValue OldRoot = SDL.DAG.getRoot(); 4942 SmallVector<SDValue, 16> Args; 4943 TLI.LowerArguments(F, SDL.DAG, Args); 4944 4945 unsigned a = 0; 4946 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4947 AI != E; ++AI) { 4948 SmallVector<MVT, 4> ValueVTs; 4949 ComputeValueVTs(TLI, AI->getType(), ValueVTs); 4950 unsigned NumValues = ValueVTs.size(); 4951 if (!AI->use_empty()) { 4952 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues)); 4953 // If this argument is live outside of the entry block, insert a copy from 4954 // whereever we got it to the vreg that other BB's will reference it as. 4955 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4956 if (VMI != FuncInfo.ValueMap.end()) { 4957 SDL.CopyValueToVirtualRegister(AI, VMI->second); 4958 } 4959 } 4960 a += NumValues; 4961 } 4962 4963 // Finally, if the target has anything special to do, allow it to do so. 4964 // FIXME: this should insert code into the DAG! 4965 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4966} 4967 4968static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4969 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4970 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4971 if (isSelector(I)) { 4972 // Apply the catch info to DestBB. 4973 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4974#ifndef NDEBUG 4975 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4976 FLI.CatchInfoFound.insert(I); 4977#endif 4978 } 4979} 4980 4981/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 4982/// whether object offset >= 0. 4983static bool 4984IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 4985 if (!isa<FrameIndexSDNode>(Op)) return false; 4986 4987 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 4988 int FrameIdx = FrameIdxNode->getIndex(); 4989 return MFI->isFixedObjectIndex(FrameIdx) && 4990 MFI->getObjectOffset(FrameIdx) >= 0; 4991} 4992 4993/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 4994/// possibly be overwritten when lowering the outgoing arguments in a tail 4995/// call. Currently the implementation of this call is very conservative and 4996/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 4997/// virtual registers would be overwritten by direct lowering. 4998static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 4999 MachineFrameInfo * MFI) { 5000 RegisterSDNode * OpReg = NULL; 5001 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 5002 (Op.getOpcode()== ISD::CopyFromReg && 5003 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 5004 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 5005 (Op.getOpcode() == ISD::LOAD && 5006 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 5007 (Op.getOpcode() == ISD::MERGE_VALUES && 5008 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD && 5009 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo). 5010 getOperand(1)))) 5011 return true; 5012 return false; 5013} 5014 5015/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 5016/// DAG and fixes their tailcall attribute operand. 5017static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 5018 TargetLowering& TLI) { 5019 SDNode * Ret = NULL; 5020 SDValue Terminator = DAG.getRoot(); 5021 5022 // Find RET node. 5023 if (Terminator.getOpcode() == ISD::RET) { 5024 Ret = Terminator.Val; 5025 } 5026 5027 // Fix tail call attribute of CALL nodes. 5028 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 5029 BI = DAG.allnodes_end(); BI != BE; ) { 5030 --BI; 5031 if (BI->getOpcode() == ISD::CALL) { 5032 SDValue OpRet(Ret, 0); 5033 SDValue OpCall(BI, 0); 5034 bool isMarkedTailCall = 5035 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 5036 // If CALL node has tail call attribute set to true and the call is not 5037 // eligible (no RET or the target rejects) the attribute is fixed to 5038 // false. The TargetLowering::IsEligibleForTailCallOptimization function 5039 // must correctly identify tail call optimizable calls. 5040 if (!isMarkedTailCall) continue; 5041 if (Ret==NULL || 5042 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) { 5043 // Not eligible. Mark CALL node as non tail call. 5044 SmallVector<SDValue, 32> Ops; 5045 unsigned idx=0; 5046 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 5047 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5048 if (idx!=3) 5049 Ops.push_back(*I); 5050 else 5051 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 5052 } 5053 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5054 } else { 5055 // Look for tail call clobbered arguments. Emit a series of 5056 // copyto/copyfrom virtual register nodes to protect them. 5057 SmallVector<SDValue, 32> Ops; 5058 SDValue Chain = OpCall.getOperand(0), InFlag; 5059 unsigned idx=0; 5060 for(SDNode::op_iterator I = OpCall.Val->op_begin(), 5061 E = OpCall.Val->op_end(); I != E; I++, idx++) { 5062 SDValue Arg = *I; 5063 if (idx > 4 && (idx % 2)) { 5064 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))-> 5065 getArgFlags().isByVal(); 5066 MachineFunction &MF = DAG.getMachineFunction(); 5067 MachineFrameInfo *MFI = MF.getFrameInfo(); 5068 if (!isByVal && 5069 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 5070 MVT VT = Arg.getValueType(); 5071 unsigned VReg = MF.getRegInfo(). 5072 createVirtualRegister(TLI.getRegClassFor(VT)); 5073 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 5074 InFlag = Chain.getValue(1); 5075 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 5076 Chain = Arg.getValue(1); 5077 InFlag = Arg.getValue(2); 5078 } 5079 } 5080 Ops.push_back(Arg); 5081 } 5082 // Link in chain of CopyTo/CopyFromReg. 5083 Ops[0] = Chain; 5084 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 5085 } 5086 } 5087 } 5088} 5089 5090void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 5091 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 5092 FunctionLoweringInfo &FuncInfo) { 5093 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI); 5094 5095 // Lower any arguments needed in this block if this is the entry block. 5096 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 5097 LowerArguments(LLVMBB, SDL); 5098 5099 BB = FuncInfo.MBBMap[LLVMBB]; 5100 SDL.setCurrentBasicBlock(BB); 5101 5102 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 5103 5104 if (MMI && BB->isLandingPad()) { 5105 // Add a label to mark the beginning of the landing pad. Deletion of the 5106 // landing pad can thus be detected via the MachineModuleInfo. 5107 unsigned LabelID = MMI->addLandingPad(BB); 5108 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID)); 5109 5110 // Mark exception register as live in. 5111 unsigned Reg = TLI.getExceptionAddressRegister(); 5112 if (Reg) BB->addLiveIn(Reg); 5113 5114 // Mark exception selector register as live in. 5115 Reg = TLI.getExceptionSelectorRegister(); 5116 if (Reg) BB->addLiveIn(Reg); 5117 5118 // FIXME: Hack around an exception handling flaw (PR1508): the personality 5119 // function and list of typeids logically belong to the invoke (or, if you 5120 // like, the basic block containing the invoke), and need to be associated 5121 // with it in the dwarf exception handling tables. Currently however the 5122 // information is provided by an intrinsic (eh.selector) that can be moved 5123 // to unexpected places by the optimizers: if the unwind edge is critical, 5124 // then breaking it can result in the intrinsics being in the successor of 5125 // the landing pad, not the landing pad itself. This results in exceptions 5126 // not being caught because no typeids are associated with the invoke. 5127 // This may not be the only way things can go wrong, but it is the only way 5128 // we try to work around for the moment. 5129 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 5130 5131 if (Br && Br->isUnconditional()) { // Critical edge? 5132 BasicBlock::iterator I, E; 5133 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 5134 if (isSelector(I)) 5135 break; 5136 5137 if (I == E) 5138 // No catch info found - try to extract some from the successor. 5139 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 5140 } 5141 } 5142 5143 // Lower all of the non-terminator instructions. 5144 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 5145 I != E; ++I) 5146 SDL.visit(*I); 5147 5148 // Ensure that all instructions which are used outside of their defining 5149 // blocks are available as virtual registers. Invoke is handled elsewhere. 5150 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 5151 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 5152 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 5153 if (VMI != FuncInfo.ValueMap.end()) 5154 SDL.CopyValueToVirtualRegister(I, VMI->second); 5155 } 5156 5157 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 5158 // ensure constants are generated when needed. Remember the virtual registers 5159 // that need to be added to the Machine PHI nodes as input. We cannot just 5160 // directly add them, because expansion might result in multiple MBB's for one 5161 // BB. As such, the start of the BB might correspond to a different MBB than 5162 // the end. 5163 // 5164 TerminatorInst *TI = LLVMBB->getTerminator(); 5165 5166 // Emit constants only once even if used by multiple PHI nodes. 5167 std::map<Constant*, unsigned> ConstantsOut; 5168 5169 // Vector bool would be better, but vector<bool> is really slow. 5170 std::vector<unsigned char> SuccsHandled; 5171 if (TI->getNumSuccessors()) 5172 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 5173 5174 // Check successor nodes' PHI nodes that expect a constant to be available 5175 // from this block. 5176 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 5177 BasicBlock *SuccBB = TI->getSuccessor(succ); 5178 if (!isa<PHINode>(SuccBB->begin())) continue; 5179 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 5180 5181 // If this terminator has multiple identical successors (common for 5182 // switches), only handle each succ once. 5183 unsigned SuccMBBNo = SuccMBB->getNumber(); 5184 if (SuccsHandled[SuccMBBNo]) continue; 5185 SuccsHandled[SuccMBBNo] = true; 5186 5187 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 5188 PHINode *PN; 5189 5190 // At this point we know that there is a 1-1 correspondence between LLVM PHI 5191 // nodes and Machine PHI nodes, but the incoming operands have not been 5192 // emitted yet. 5193 for (BasicBlock::iterator I = SuccBB->begin(); 5194 (PN = dyn_cast<PHINode>(I)); ++I) { 5195 // Ignore dead phi's. 5196 if (PN->use_empty()) continue; 5197 5198 unsigned Reg; 5199 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 5200 5201 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 5202 unsigned &RegOut = ConstantsOut[C]; 5203 if (RegOut == 0) { 5204 RegOut = FuncInfo.CreateRegForValue(C); 5205 SDL.CopyValueToVirtualRegister(C, RegOut); 5206 } 5207 Reg = RegOut; 5208 } else { 5209 Reg = FuncInfo.ValueMap[PHIOp]; 5210 if (Reg == 0) { 5211 assert(isa<AllocaInst>(PHIOp) && 5212 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 5213 "Didn't codegen value into a register!??"); 5214 Reg = FuncInfo.CreateRegForValue(PHIOp); 5215 SDL.CopyValueToVirtualRegister(PHIOp, Reg); 5216 } 5217 } 5218 5219 // Remember that this register needs to added to the machine PHI node as 5220 // the input for this MBB. 5221 SmallVector<MVT, 4> ValueVTs; 5222 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 5223 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 5224 MVT VT = ValueVTs[vti]; 5225 unsigned NumRegisters = TLI.getNumRegisters(VT); 5226 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 5227 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 5228 Reg += NumRegisters; 5229 } 5230 } 5231 } 5232 ConstantsOut.clear(); 5233 5234 // Lower the terminator after the copies are emitted. 5235 SDL.visit(*LLVMBB->getTerminator()); 5236 5237 // Copy over any CaseBlock records that may now exist due to SwitchInst 5238 // lowering, as well as any jump table information. 5239 SwitchCases.clear(); 5240 SwitchCases = SDL.SwitchCases; 5241 JTCases.clear(); 5242 JTCases = SDL.JTCases; 5243 BitTestCases.clear(); 5244 BitTestCases = SDL.BitTestCases; 5245 5246 // Make sure the root of the DAG is up-to-date. 5247 DAG.setRoot(SDL.getControlRoot()); 5248 5249 // Check whether calls in this block are real tail calls. Fix up CALL nodes 5250 // with correct tailcall attribute so that the target can rely on the tailcall 5251 // attribute indicating whether the call is really eligible for tail call 5252 // optimization. 5253 CheckDAGForTailCallsAndFixThem(DAG, TLI); 5254} 5255 5256void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { 5257 SmallPtrSet<SDNode*, 128> VisitedNodes; 5258 SmallVector<SDNode*, 128> Worklist; 5259 5260 Worklist.push_back(DAG.getRoot().Val); 5261 5262 APInt Mask; 5263 APInt KnownZero; 5264 APInt KnownOne; 5265 5266 while (!Worklist.empty()) { 5267 SDNode *N = Worklist.back(); 5268 Worklist.pop_back(); 5269 5270 // If we've already seen this node, ignore it. 5271 if (!VisitedNodes.insert(N)) 5272 continue; 5273 5274 // Otherwise, add all chain operands to the worklist. 5275 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5276 if (N->getOperand(i).getValueType() == MVT::Other) 5277 Worklist.push_back(N->getOperand(i).Val); 5278 5279 // If this is a CopyToReg with a vreg dest, process it. 5280 if (N->getOpcode() != ISD::CopyToReg) 5281 continue; 5282 5283 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 5284 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 5285 continue; 5286 5287 // Ignore non-scalar or non-integer values. 5288 SDValue Src = N->getOperand(2); 5289 MVT SrcVT = Src.getValueType(); 5290 if (!SrcVT.isInteger() || SrcVT.isVector()) 5291 continue; 5292 5293 unsigned NumSignBits = DAG.ComputeNumSignBits(Src); 5294 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 5295 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 5296 5297 // Only install this information if it tells us something. 5298 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 5299 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 5300 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5301 if (DestReg >= FLI.LiveOutRegInfo.size()) 5302 FLI.LiveOutRegInfo.resize(DestReg+1); 5303 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 5304 LOI.NumSignBits = NumSignBits; 5305 LOI.KnownOne = NumSignBits; 5306 LOI.KnownZero = NumSignBits; 5307 } 5308 } 5309} 5310 5311void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 5312 std::string GroupName; 5313 if (TimePassesIsEnabled) 5314 GroupName = "Instruction Selection and Scheduling"; 5315 std::string BlockName; 5316 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 5317 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 5318 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' + 5319 BB->getBasicBlock()->getName(); 5320 5321 DOUT << "Initial selection DAG:\n"; 5322 DEBUG(DAG.dump()); 5323 5324 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName); 5325 5326 // Run the DAG combiner in pre-legalize mode. 5327 if (TimePassesIsEnabled) { 5328 NamedRegionTimer T("DAG Combining 1", GroupName); 5329 DAG.Combine(false, *AA); 5330 } else { 5331 DAG.Combine(false, *AA); 5332 } 5333 5334 DOUT << "Optimized lowered selection DAG:\n"; 5335 DEBUG(DAG.dump()); 5336 5337 // Second step, hack on the DAG until it only uses operations and types that 5338 // the target supports. 5339 if (EnableLegalizeTypes) {// Enable this some day. 5340 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " + 5341 BlockName); 5342 5343 if (TimePassesIsEnabled) { 5344 NamedRegionTimer T("Type Legalization", GroupName); 5345 DAG.LegalizeTypes(); 5346 } else { 5347 DAG.LegalizeTypes(); 5348 } 5349 5350 DOUT << "Type-legalized selection DAG:\n"; 5351 DEBUG(DAG.dump()); 5352 5353 // TODO: enable a dag combine pass here. 5354 } 5355 5356 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName); 5357 5358 if (TimePassesIsEnabled) { 5359 NamedRegionTimer T("DAG Legalization", GroupName); 5360 DAG.Legalize(); 5361 } else { 5362 DAG.Legalize(); 5363 } 5364 5365 DOUT << "Legalized selection DAG:\n"; 5366 DEBUG(DAG.dump()); 5367 5368 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName); 5369 5370 // Run the DAG combiner in post-legalize mode. 5371 if (TimePassesIsEnabled) { 5372 NamedRegionTimer T("DAG Combining 2", GroupName); 5373 DAG.Combine(true, *AA); 5374 } else { 5375 DAG.Combine(true, *AA); 5376 } 5377 5378 DOUT << "Optimized legalized selection DAG:\n"; 5379 DEBUG(DAG.dump()); 5380 5381 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName); 5382 5383 if (!FastISel && EnableValueProp) 5384 ComputeLiveOutVRegInfo(DAG); 5385 5386 // Third, instruction select all of the operations to machine code, adding the 5387 // code to the MachineBasicBlock. 5388 if (TimePassesIsEnabled) { 5389 NamedRegionTimer T("Instruction Selection", GroupName); 5390 InstructionSelect(DAG); 5391 } else { 5392 InstructionSelect(DAG); 5393 } 5394 5395 DOUT << "Selected selection DAG:\n"; 5396 DEBUG(DAG.dump()); 5397 5398 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName); 5399 5400 // Schedule machine code. 5401 ScheduleDAG *Scheduler; 5402 if (TimePassesIsEnabled) { 5403 NamedRegionTimer T("Instruction Scheduling", GroupName); 5404 Scheduler = Schedule(DAG); 5405 } else { 5406 Scheduler = Schedule(DAG); 5407 } 5408 5409 if (ViewSUnitDAGs) Scheduler->viewGraph(); 5410 5411 // Emit machine code to BB. This can change 'BB' to the last block being 5412 // inserted into. 5413 if (TimePassesIsEnabled) { 5414 NamedRegionTimer T("Instruction Creation", GroupName); 5415 BB = Scheduler->EmitSchedule(); 5416 } else { 5417 BB = Scheduler->EmitSchedule(); 5418 } 5419 5420 // Free the scheduler state. 5421 if (TimePassesIsEnabled) { 5422 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 5423 delete Scheduler; 5424 } else { 5425 delete Scheduler; 5426 } 5427 5428 // Perform target specific isel post processing. 5429 if (TimePassesIsEnabled) { 5430 NamedRegionTimer T("Instruction Selection Post Processing", GroupName); 5431 InstructionSelectPostProcessing(); 5432 } else { 5433 InstructionSelectPostProcessing(); 5434 } 5435 5436 DOUT << "Selected machine code:\n"; 5437 DEBUG(BB->dump()); 5438} 5439 5440void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 5441 FunctionLoweringInfo &FuncInfo) { 5442 // Define NodeAllocator here so that memory allocation is reused for 5443 // each basic block. 5444 NodeAllocatorType NodeAllocator; 5445 5446 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 5447 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator); 5448} 5449 5450void 5451SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 5452 FunctionLoweringInfo &FuncInfo, 5453 NodeAllocatorType &NodeAllocator) { 5454 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 5455 { 5456 SelectionDAG DAG(TLI, MF, FuncInfo, 5457 getAnalysisToUpdate<MachineModuleInfo>(), 5458 NodeAllocator); 5459 CurDAG = &DAG; 5460 5461 // First step, lower LLVM code to some DAG. This DAG may use operations and 5462 // types that are not supported by the target. 5463 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 5464 5465 // Second step, emit the lowered DAG as machine code. 5466 CodeGenAndEmitDAG(DAG); 5467 } 5468 5469 DOUT << "Total amount of phi nodes to update: " 5470 << PHINodesToUpdate.size() << "\n"; 5471 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 5472 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 5473 << ", " << PHINodesToUpdate[i].second << ")\n";); 5474 5475 // Next, now that we know what the last MBB the LLVM BB expanded is, update 5476 // PHI nodes in successors. 5477 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 5478 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5479 MachineInstr *PHI = PHINodesToUpdate[i].first; 5480 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5481 "This is not a machine PHI node that we are updating!"); 5482 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5483 false)); 5484 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5485 } 5486 return; 5487 } 5488 5489 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 5490 // Lower header first, if it wasn't already lowered 5491 if (!BitTestCases[i].Emitted) { 5492 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5493 getAnalysisToUpdate<MachineModuleInfo>(), 5494 NodeAllocator); 5495 CurDAG = &HSDAG; 5496 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5497 // Set the current basic block to the mbb we wish to insert the code into 5498 BB = BitTestCases[i].Parent; 5499 HSDL.setCurrentBasicBlock(BB); 5500 // Emit the code 5501 HSDL.visitBitTestHeader(BitTestCases[i]); 5502 HSDAG.setRoot(HSDL.getRoot()); 5503 CodeGenAndEmitDAG(HSDAG); 5504 } 5505 5506 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5507 SelectionDAG BSDAG(TLI, MF, FuncInfo, 5508 getAnalysisToUpdate<MachineModuleInfo>(), 5509 NodeAllocator); 5510 CurDAG = &BSDAG; 5511 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); 5512 // Set the current basic block to the mbb we wish to insert the code into 5513 BB = BitTestCases[i].Cases[j].ThisBB; 5514 BSDL.setCurrentBasicBlock(BB); 5515 // Emit the code 5516 if (j+1 != ej) 5517 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 5518 BitTestCases[i].Reg, 5519 BitTestCases[i].Cases[j]); 5520 else 5521 BSDL.visitBitTestCase(BitTestCases[i].Default, 5522 BitTestCases[i].Reg, 5523 BitTestCases[i].Cases[j]); 5524 5525 5526 BSDAG.setRoot(BSDL.getRoot()); 5527 CodeGenAndEmitDAG(BSDAG); 5528 } 5529 5530 // Update PHI Nodes 5531 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5532 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5533 MachineBasicBlock *PHIBB = PHI->getParent(); 5534 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5535 "This is not a machine PHI node that we are updating!"); 5536 // This is "default" BB. We have two jumps to it. From "header" BB and 5537 // from last "case" BB. 5538 if (PHIBB == BitTestCases[i].Default) { 5539 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5540 false)); 5541 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent)); 5542 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5543 false)); 5544 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases. 5545 back().ThisBB)); 5546 } 5547 // One of "cases" BB. 5548 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 5549 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 5550 if (cBB->succ_end() != 5551 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 5552 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5553 false)); 5554 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 5555 } 5556 } 5557 } 5558 } 5559 5560 // If the JumpTable record is filled in, then we need to emit a jump table. 5561 // Updating the PHI nodes is tricky in this case, since we need to determine 5562 // whether the PHI is a successor of the range check MBB or the jump table MBB 5563 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 5564 // Lower header first, if it wasn't already lowered 5565 if (!JTCases[i].first.Emitted) { 5566 SelectionDAG HSDAG(TLI, MF, FuncInfo, 5567 getAnalysisToUpdate<MachineModuleInfo>(), 5568 NodeAllocator); 5569 CurDAG = &HSDAG; 5570 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); 5571 // Set the current basic block to the mbb we wish to insert the code into 5572 BB = JTCases[i].first.HeaderBB; 5573 HSDL.setCurrentBasicBlock(BB); 5574 // Emit the code 5575 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 5576 HSDAG.setRoot(HSDL.getRoot()); 5577 CodeGenAndEmitDAG(HSDAG); 5578 } 5579 5580 SelectionDAG JSDAG(TLI, MF, FuncInfo, 5581 getAnalysisToUpdate<MachineModuleInfo>(), 5582 NodeAllocator); 5583 CurDAG = &JSDAG; 5584 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); 5585 // Set the current basic block to the mbb we wish to insert the code into 5586 BB = JTCases[i].second.MBB; 5587 JSDL.setCurrentBasicBlock(BB); 5588 // Emit the code 5589 JSDL.visitJumpTable(JTCases[i].second); 5590 JSDAG.setRoot(JSDL.getRoot()); 5591 CodeGenAndEmitDAG(JSDAG); 5592 5593 // Update PHI Nodes 5594 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 5595 MachineInstr *PHI = PHINodesToUpdate[pi].first; 5596 MachineBasicBlock *PHIBB = PHI->getParent(); 5597 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5598 "This is not a machine PHI node that we are updating!"); 5599 // "default" BB. We can go there only from header BB. 5600 if (PHIBB == JTCases[i].second.Default) { 5601 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5602 false)); 5603 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB)); 5604 } 5605 // JT BB. Just iterate over successors here 5606 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 5607 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second, 5608 false)); 5609 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5610 } 5611 } 5612 } 5613 5614 // If the switch block involved a branch to one of the actual successors, we 5615 // need to update PHI nodes in that block. 5616 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 5617 MachineInstr *PHI = PHINodesToUpdate[i].first; 5618 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 5619 "This is not a machine PHI node that we are updating!"); 5620 if (BB->isSuccessor(PHI->getParent())) { 5621 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second, 5622 false)); 5623 PHI->addOperand(MachineOperand::CreateMBB(BB)); 5624 } 5625 } 5626 5627 // If we generated any switch lowering information, build and codegen any 5628 // additional DAGs necessary. 5629 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 5630 SelectionDAG SDAG(TLI, MF, FuncInfo, 5631 getAnalysisToUpdate<MachineModuleInfo>(), 5632 NodeAllocator); 5633 CurDAG = &SDAG; 5634 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); 5635 5636 // Set the current basic block to the mbb we wish to insert the code into 5637 BB = SwitchCases[i].ThisBB; 5638 SDL.setCurrentBasicBlock(BB); 5639 5640 // Emit the code 5641 SDL.visitSwitchCase(SwitchCases[i]); 5642 SDAG.setRoot(SDL.getRoot()); 5643 CodeGenAndEmitDAG(SDAG); 5644 5645 // Handle any PHI nodes in successors of this chunk, as if we were coming 5646 // from the original BB before switch expansion. Note that PHI nodes can 5647 // occur multiple times in PHINodesToUpdate. We have to be very careful to 5648 // handle them the right number of times. 5649 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 5650 for (MachineBasicBlock::iterator Phi = BB->begin(); 5651 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 5652 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 5653 for (unsigned pn = 0; ; ++pn) { 5654 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 5655 if (PHINodesToUpdate[pn].first == Phi) { 5656 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn]. 5657 second, false)); 5658 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB)); 5659 break; 5660 } 5661 } 5662 } 5663 5664 // Don't process RHS if same block as LHS. 5665 if (BB == SwitchCases[i].FalseBB) 5666 SwitchCases[i].FalseBB = 0; 5667 5668 // If we haven't handled the RHS, do so now. Otherwise, we're done. 5669 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 5670 SwitchCases[i].FalseBB = 0; 5671 } 5672 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 5673 } 5674} 5675 5676 5677/// Schedule - Pick a safe ordering for instructions for each 5678/// target node in the graph. 5679/// 5680ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { 5681 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 5682 5683 if (!Ctor) { 5684 Ctor = ISHeuristic; 5685 RegisterScheduler::setDefault(Ctor); 5686 } 5687 5688 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); 5689 Scheduler->Run(); 5690 5691 return Scheduler; 5692} 5693 5694 5695HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 5696 return new HazardRecognizer(); 5697} 5698 5699//===----------------------------------------------------------------------===// 5700// Helper functions used by the generated instruction selector. 5701//===----------------------------------------------------------------------===// 5702// Calls to these methods are generated by tblgen. 5703 5704/// CheckAndMask - The isel is trying to match something like (and X, 255). If 5705/// the dag combiner simplified the 255, we still want to match. RHS is the 5706/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 5707/// specified in the .td file (e.g. 255). 5708bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 5709 int64_t DesiredMaskS) const { 5710 const APInt &ActualMask = RHS->getAPIntValue(); 5711 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5712 5713 // If the actual mask exactly matches, success! 5714 if (ActualMask == DesiredMask) 5715 return true; 5716 5717 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5718 if (ActualMask.intersects(~DesiredMask)) 5719 return false; 5720 5721 // Otherwise, the DAG Combiner may have proven that the value coming in is 5722 // either already zero or is not demanded. Check for known zero input bits. 5723 APInt NeededMask = DesiredMask & ~ActualMask; 5724 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5725 return true; 5726 5727 // TODO: check to see if missing bits are just not demanded. 5728 5729 // Otherwise, this pattern doesn't match. 5730 return false; 5731} 5732 5733/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5734/// the dag combiner simplified the 255, we still want to match. RHS is the 5735/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5736/// specified in the .td file (e.g. 255). 5737bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 5738 int64_t DesiredMaskS) const { 5739 const APInt &ActualMask = RHS->getAPIntValue(); 5740 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 5741 5742 // If the actual mask exactly matches, success! 5743 if (ActualMask == DesiredMask) 5744 return true; 5745 5746 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5747 if (ActualMask.intersects(~DesiredMask)) 5748 return false; 5749 5750 // Otherwise, the DAG Combiner may have proven that the value coming in is 5751 // either already zero or is not demanded. Check for known zero input bits. 5752 APInt NeededMask = DesiredMask & ~ActualMask; 5753 5754 APInt KnownZero, KnownOne; 5755 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5756 5757 // If all the missing bits in the or are already known to be set, match! 5758 if ((NeededMask & KnownOne) == NeededMask) 5759 return true; 5760 5761 // TODO: check to see if missing bits are just not demanded. 5762 5763 // Otherwise, this pattern doesn't match. 5764 return false; 5765} 5766 5767 5768/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5769/// by tblgen. Others should not call it. 5770void SelectionDAGISel:: 5771SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) { 5772 std::vector<SDValue> InOps; 5773 std::swap(InOps, Ops); 5774 5775 Ops.push_back(InOps[0]); // input chain. 5776 Ops.push_back(InOps[1]); // input asm string. 5777 5778 unsigned i = 2, e = InOps.size(); 5779 if (InOps[e-1].getValueType() == MVT::Flag) 5780 --e; // Don't process a flag operand if it is here. 5781 5782 while (i != e) { 5783 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5784 if ((Flags & 7) != 4 /*MEM*/) { 5785 // Just skip over this operand, copying the operands verbatim. 5786 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5787 i += (Flags >> 3) + 1; 5788 } else { 5789 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5790 // Otherwise, this is a memory operand. Ask the target to select it. 5791 std::vector<SDValue> SelOps; 5792 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5793 cerr << "Could not match memory address. Inline asm failure!\n"; 5794 exit(1); 5795 } 5796 5797 // Add this to the output node. 5798 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5799 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5800 IntPtrTy)); 5801 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5802 i += 2; 5803 } 5804 } 5805 5806 // Add the flag input back if present. 5807 if (e != InOps.size()) 5808 Ops.push_back(InOps.back()); 5809} 5810 5811char SelectionDAGISel::ID = 0; 5812