SelectionDAGISel.cpp revision c105a2b5b7d8969e78bd4b203e980dced8a1c689
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(tm, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 184 AU.addRequired<AliasAnalysis>(); 185 AU.addPreserved<AliasAnalysis>(); 186 AU.addRequired<GCModuleInfo>(); 187 AU.addPreserved<GCModuleInfo>(); 188 MachineFunctionPass::getAnalysisUsage(AU); 189} 190 191bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 192 // Do some sanity-checking on the command-line options. 193 assert((!EnableFastISelVerbose || EnableFastISel) && 194 "-fast-isel-verbose requires -fast-isel"); 195 assert((!EnableFastISelAbort || EnableFastISel) && 196 "-fast-isel-abort requires -fast-isel"); 197 198 const Function &Fn = *mf.getFunction(); 199 const TargetInstrInfo &TII = *TM.getInstrInfo(); 200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 201 202 MF = &mf; 203 RegInfo = &MF->getRegInfo(); 204 AA = &getAnalysis<AliasAnalysis>(); 205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 206 207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 208 209 CurDAG->init(*MF); 210 FuncInfo->set(Fn, *MF, EnableFastISel); 211 SDB->init(GFI, *AA); 212 213 SelectAllBasicBlocks(Fn); 214 215 // Release function-specific state. SDB and CurDAG are already cleared 216 // at this point. 217 FuncInfo->clear(); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224 return true; 225} 226 227MachineBasicBlock * 228SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 229 const BasicBlock *LLVMBB, 230 BasicBlock::const_iterator Begin, 231 BasicBlock::const_iterator End, 232 bool &HadTailCall) { 233 // Lower all of the non-terminator instructions. If a call is emitted 234 // as a tail call, cease emitting nodes for this block. Terminators 235 // are handled below. 236 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 237 SDB->visit(*I); 238 239 // Make sure the root of the DAG is up-to-date. 240 CurDAG->setRoot(SDB->getControlRoot()); 241 242 // Final step, emit the lowered DAG as machine code. 243 BB = CodeGenAndEmitDAG(BB); 244 HadTailCall = SDB->HasTailCall; 245 SDB->clear(); 246 return BB; 247} 248 249namespace { 250/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 251/// nodes from the worklist. 252class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 253 SmallVector<SDNode*, 128> &Worklist; 254 SmallPtrSet<SDNode*, 128> &InWorklist; 255public: 256 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 257 SmallPtrSet<SDNode*, 128> &inwl) 258 : Worklist(wl), InWorklist(inwl) {} 259 260 void RemoveFromWorklist(SDNode *N) { 261 if (!InWorklist.erase(N)) return; 262 263 SmallVector<SDNode*, 128>::iterator I = 264 std::find(Worklist.begin(), Worklist.end(), N); 265 assert(I != Worklist.end() && "Not in worklist"); 266 267 *I = Worklist.back(); 268 Worklist.pop_back(); 269 } 270 271 virtual void NodeDeleted(SDNode *N, SDNode *E) { 272 RemoveFromWorklist(N); 273 } 274 275 virtual void NodeUpdated(SDNode *N) { 276 // Ignore updates. 277 } 278}; 279} 280 281/// TrivialTruncElim - Eliminate some trivial nops that can result from 282/// ShrinkDemandedOps: (trunc (ext n)) -> n. 283static bool TrivialTruncElim(SDValue Op, 284 TargetLowering::TargetLoweringOpt &TLO) { 285 SDValue N0 = Op.getOperand(0); 286 EVT VT = Op.getValueType(); 287 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 288 N0.getOpcode() == ISD::SIGN_EXTEND || 289 N0.getOpcode() == ISD::ANY_EXTEND) && 290 N0.getOperand(0).getValueType() == VT) { 291 return TLO.CombineTo(Op, N0.getOperand(0)); 292 } 293 return false; 294} 295 296/// ShrinkDemandedOps - A late transformation pass that shrink expressions 297/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 298/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 299void SelectionDAGISel::ShrinkDemandedOps() { 300 SmallVector<SDNode*, 128> Worklist; 301 SmallPtrSet<SDNode*, 128> InWorklist; 302 303 // Add all the dag nodes to the worklist. 304 Worklist.reserve(CurDAG->allnodes_size()); 305 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 306 E = CurDAG->allnodes_end(); I != E; ++I) { 307 Worklist.push_back(I); 308 InWorklist.insert(I); 309 } 310 311 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 312 while (!Worklist.empty()) { 313 SDNode *N = Worklist.pop_back_val(); 314 InWorklist.erase(N); 315 316 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 317 // Deleting this node may make its operands dead, add them to the worklist 318 // if they aren't already there. 319 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 320 if (InWorklist.insert(N->getOperand(i).getNode())) 321 Worklist.push_back(N->getOperand(i).getNode()); 322 323 CurDAG->DeleteNode(N); 324 continue; 325 } 326 327 // Run ShrinkDemandedOp on scalar binary operations. 328 if (N->getNumValues() != 1 || 329 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 330 continue; 331 332 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 333 APInt Demanded = APInt::getAllOnesValue(BitWidth); 334 APInt KnownZero, KnownOne; 335 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 336 KnownZero, KnownOne, TLO) && 337 (N->getOpcode() != ISD::TRUNCATE || 338 !TrivialTruncElim(SDValue(N, 0), TLO))) 339 continue; 340 341 // Revisit the node. 342 assert(!InWorklist.count(N) && "Already in worklist"); 343 Worklist.push_back(N); 344 InWorklist.insert(N); 345 346 // Replace the old value with the new one. 347 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 348 TLO.Old.getNode()->dump(CurDAG); 349 errs() << "\nWith: "; 350 TLO.New.getNode()->dump(CurDAG); 351 errs() << '\n'); 352 353 if (InWorklist.insert(TLO.New.getNode())) 354 Worklist.push_back(TLO.New.getNode()); 355 356 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 357 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 358 359 if (!TLO.Old.getNode()->use_empty()) continue; 360 361 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 362 i != e; ++i) { 363 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 364 if (OpNode->hasOneUse()) { 365 // Add OpNode to the end of the list to revisit. 366 DeadNodes.RemoveFromWorklist(OpNode); 367 Worklist.push_back(OpNode); 368 InWorklist.insert(OpNode); 369 } 370 } 371 372 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 373 CurDAG->DeleteNode(TLO.Old.getNode()); 374 } 375} 376 377void SelectionDAGISel::ComputeLiveOutVRegInfo() { 378 SmallPtrSet<SDNode*, 128> VisitedNodes; 379 SmallVector<SDNode*, 128> Worklist; 380 381 Worklist.push_back(CurDAG->getRoot().getNode()); 382 383 APInt Mask; 384 APInt KnownZero; 385 APInt KnownOne; 386 387 do { 388 SDNode *N = Worklist.pop_back_val(); 389 390 // If we've already seen this node, ignore it. 391 if (!VisitedNodes.insert(N)) 392 continue; 393 394 // Otherwise, add all chain operands to the worklist. 395 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 396 if (N->getOperand(i).getValueType() == MVT::Other) 397 Worklist.push_back(N->getOperand(i).getNode()); 398 399 // If this is a CopyToReg with a vreg dest, process it. 400 if (N->getOpcode() != ISD::CopyToReg) 401 continue; 402 403 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 404 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 405 continue; 406 407 // Ignore non-scalar or non-integer values. 408 SDValue Src = N->getOperand(2); 409 EVT SrcVT = Src.getValueType(); 410 if (!SrcVT.isInteger() || SrcVT.isVector()) 411 continue; 412 413 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 414 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 415 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 416 417 // Only install this information if it tells us something. 418 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 419 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 420 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 421 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 422 FunctionLoweringInfo::LiveOutInfo &LOI = 423 FuncInfo->LiveOutRegInfo[DestReg]; 424 LOI.NumSignBits = NumSignBits; 425 LOI.KnownOne = KnownOne; 426 LOI.KnownZero = KnownZero; 427 } 428 } while (!Worklist.empty()); 429} 430 431MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 432 std::string GroupName; 433 if (TimePassesIsEnabled) 434 GroupName = "Instruction Selection and Scheduling"; 435 std::string BlockName; 436 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 437 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 438 ViewSUnitDAGs) 439 BlockName = MF->getFunction()->getNameStr() + ":" + 440 BB->getBasicBlock()->getNameStr(); 441 442 DEBUG(dbgs() << "Initial selection DAG:\n"); 443 DEBUG(CurDAG->dump()); 444 445 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 446 447 // Run the DAG combiner in pre-legalize mode. 448 if (TimePassesIsEnabled) { 449 NamedRegionTimer T("DAG Combining 1", GroupName); 450 CurDAG->Combine(Unrestricted, *AA, OptLevel); 451 } else { 452 CurDAG->Combine(Unrestricted, *AA, OptLevel); 453 } 454 455 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 456 DEBUG(CurDAG->dump()); 457 458 // Second step, hack on the DAG until it only uses operations and types that 459 // the target supports. 460 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 461 BlockName); 462 463 bool Changed; 464 if (TimePassesIsEnabled) { 465 NamedRegionTimer T("Type Legalization", GroupName); 466 Changed = CurDAG->LegalizeTypes(); 467 } else { 468 Changed = CurDAG->LegalizeTypes(); 469 } 470 471 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 472 DEBUG(CurDAG->dump()); 473 474 if (Changed) { 475 if (ViewDAGCombineLT) 476 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 477 478 // Run the DAG combiner in post-type-legalize mode. 479 if (TimePassesIsEnabled) { 480 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 481 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 482 } else { 483 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 484 } 485 486 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 487 DEBUG(CurDAG->dump()); 488 } 489 490 if (TimePassesIsEnabled) { 491 NamedRegionTimer T("Vector Legalization", GroupName); 492 Changed = CurDAG->LegalizeVectors(); 493 } else { 494 Changed = CurDAG->LegalizeVectors(); 495 } 496 497 if (Changed) { 498 if (TimePassesIsEnabled) { 499 NamedRegionTimer T("Type Legalization 2", GroupName); 500 CurDAG->LegalizeTypes(); 501 } else { 502 CurDAG->LegalizeTypes(); 503 } 504 505 if (ViewDAGCombineLT) 506 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 507 508 // Run the DAG combiner in post-type-legalize mode. 509 if (TimePassesIsEnabled) { 510 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 511 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 512 } else { 513 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 514 } 515 516 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 517 DEBUG(CurDAG->dump()); 518 } 519 520 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 521 522 if (TimePassesIsEnabled) { 523 NamedRegionTimer T("DAG Legalization", GroupName); 524 CurDAG->Legalize(OptLevel); 525 } else { 526 CurDAG->Legalize(OptLevel); 527 } 528 529 DEBUG(dbgs() << "Legalized selection DAG:\n"); 530 DEBUG(CurDAG->dump()); 531 532 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 533 534 // Run the DAG combiner in post-legalize mode. 535 if (TimePassesIsEnabled) { 536 NamedRegionTimer T("DAG Combining 2", GroupName); 537 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 538 } else { 539 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 540 } 541 542 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 543 DEBUG(CurDAG->dump()); 544 545 if (OptLevel != CodeGenOpt::None) { 546 ShrinkDemandedOps(); 547 ComputeLiveOutVRegInfo(); 548 } 549 550 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 551 552 // Third, instruction select all of the operations to machine code, adding the 553 // code to the MachineBasicBlock. 554 if (TimePassesIsEnabled) { 555 NamedRegionTimer T("Instruction Selection", GroupName); 556 DoInstructionSelection(); 557 } else { 558 DoInstructionSelection(); 559 } 560 561 DEBUG(dbgs() << "Selected selection DAG:\n"); 562 DEBUG(CurDAG->dump()); 563 564 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 565 566 // Schedule machine code. 567 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 568 if (TimePassesIsEnabled) { 569 NamedRegionTimer T("Instruction Scheduling", GroupName); 570 Scheduler->Run(CurDAG, BB, BB->end()); 571 } else { 572 Scheduler->Run(CurDAG, BB, BB->end()); 573 } 574 575 if (ViewSUnitDAGs) Scheduler->viewGraph(); 576 577 // Emit machine code to BB. This can change 'BB' to the last block being 578 // inserted into. 579 if (TimePassesIsEnabled) { 580 NamedRegionTimer T("Instruction Creation", GroupName); 581 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 582 } else { 583 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 584 } 585 586 // Free the scheduler state. 587 if (TimePassesIsEnabled) { 588 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 589 delete Scheduler; 590 } else { 591 delete Scheduler; 592 } 593 594 return BB; 595} 596 597void SelectionDAGISel::DoInstructionSelection() { 598 DEBUG(errs() << "===== Instruction selection begins:\n"); 599 600 PreprocessISelDAG(); 601 602 // Select target instructions for the DAG. 603 { 604 // Number all nodes with a topological order and set DAGSize. 605 DAGSize = CurDAG->AssignTopologicalOrder(); 606 607 // Create a dummy node (which is not added to allnodes), that adds 608 // a reference to the root node, preventing it from being deleted, 609 // and tracking any changes of the root. 610 HandleSDNode Dummy(CurDAG->getRoot()); 611 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 612 ++ISelPosition; 613 614 // The AllNodes list is now topological-sorted. Visit the 615 // nodes by starting at the end of the list (the root of the 616 // graph) and preceding back toward the beginning (the entry 617 // node). 618 while (ISelPosition != CurDAG->allnodes_begin()) { 619 SDNode *Node = --ISelPosition; 620 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 621 // but there are currently some corner cases that it misses. Also, this 622 // makes it theoretically possible to disable the DAGCombiner. 623 if (Node->use_empty()) 624 continue; 625 626 SDNode *ResNode = Select(Node); 627 628 // FIXME: This is pretty gross. 'Select' should be changed to not return 629 // anything at all and this code should be nuked with a tactical strike. 630 631 // If node should not be replaced, continue with the next one. 632 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 633 continue; 634 // Replace node. 635 if (ResNode) 636 ReplaceUses(Node, ResNode); 637 638 // If after the replacement this node is not used any more, 639 // remove this dead node. 640 if (Node->use_empty()) { // Don't delete EntryToken, etc. 641 ISelUpdater ISU(ISelPosition); 642 CurDAG->RemoveDeadNode(Node, &ISU); 643 } 644 } 645 646 CurDAG->setRoot(Dummy.getValue()); 647 } 648 DEBUG(errs() << "===== Instruction selection ends:\n"); 649 650 PostprocessISelDAG(); 651} 652 653/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 654/// do other setup for EH landing-pad blocks. 655void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 656 // Add a label to mark the beginning of the landing pad. Deletion of the 657 // landing pad can thus be detected via the MachineModuleInfo. 658 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 659 660 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 661 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 662 663 // Mark exception register as live in. 664 unsigned Reg = TLI.getExceptionAddressRegister(); 665 if (Reg) BB->addLiveIn(Reg); 666 667 // Mark exception selector register as live in. 668 Reg = TLI.getExceptionSelectorRegister(); 669 if (Reg) BB->addLiveIn(Reg); 670 671 // FIXME: Hack around an exception handling flaw (PR1508): the personality 672 // function and list of typeids logically belong to the invoke (or, if you 673 // like, the basic block containing the invoke), and need to be associated 674 // with it in the dwarf exception handling tables. Currently however the 675 // information is provided by an intrinsic (eh.selector) that can be moved 676 // to unexpected places by the optimizers: if the unwind edge is critical, 677 // then breaking it can result in the intrinsics being in the successor of 678 // the landing pad, not the landing pad itself. This results 679 // in exceptions not being caught because no typeids are associated with 680 // the invoke. This may not be the only way things can go wrong, but it 681 // is the only way we try to work around for the moment. 682 const BasicBlock *LLVMBB = BB->getBasicBlock(); 683 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 684 685 if (Br && Br->isUnconditional()) { // Critical edge? 686 BasicBlock::const_iterator I, E; 687 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 688 if (isa<EHSelectorInst>(I)) 689 break; 690 691 if (I == E) 692 // No catch info found - try to extract some from the successor. 693 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 694 } 695} 696 697void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 698 // Initialize the Fast-ISel state, if needed. 699 FastISel *FastIS = 0; 700 if (EnableFastISel) 701 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 702 FuncInfo->StaticAllocaMap, 703 FuncInfo->PHINodesToUpdate 704#ifndef NDEBUG 705 , FuncInfo->CatchInfoLost 706#endif 707 ); 708 709 // Iterate over all basic blocks in the function. 710 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 711 const BasicBlock *LLVMBB = &*I; 712 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 713 714 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 715 BasicBlock::const_iterator const End = LLVMBB->end(); 716 BasicBlock::const_iterator BI = Begin; 717 718 // Lower any arguments needed in this block if this is the entry block. 719 bool SuppressFastISel = false; 720 if (LLVMBB == &Fn.getEntryBlock()) { 721 LowerArguments(LLVMBB); 722 723 // If any of the arguments has the byval attribute, forgo 724 // fast-isel in the entry block. 725 if (FastIS) { 726 unsigned j = 1; 727 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 728 I != E; ++I, ++j) 729 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 730 if (EnableFastISelVerbose || EnableFastISelAbort) 731 dbgs() << "FastISel skips entry block due to byval argument\n"; 732 SuppressFastISel = true; 733 break; 734 } 735 } 736 } 737 738 // Setup an EH landing-pad block. 739 if (BB->isLandingPad()) 740 PrepareEHLandingPad(BB); 741 742 // Before doing SelectionDAG ISel, see if FastISel has been requested. 743 if (FastIS && !SuppressFastISel) { 744 // Emit code for any incoming arguments. This must happen before 745 // beginning FastISel on the entry block. 746 if (LLVMBB == &Fn.getEntryBlock()) { 747 CurDAG->setRoot(SDB->getControlRoot()); 748 BB = CodeGenAndEmitDAG(BB); 749 SDB->clear(); 750 } 751 FastIS->startNewBlock(BB); 752 // Do FastISel on as many instructions as possible. 753 for (; BI != End; ++BI) { 754 // Just before the terminator instruction, insert instructions to 755 // feed PHI nodes in successor blocks. 756 if (isa<TerminatorInst>(BI)) 757 if (!FastIS->HandlePHINodesInSuccessorBlocks(LLVMBB)) { 758 ++NumFastIselFailures; 759 if (EnableFastISelVerbose || EnableFastISelAbort) { 760 dbgs() << "FastISel miss: "; 761 BI->dump(); 762 } 763 assert(!EnableFastISelAbort && 764 "FastISel didn't handle a PHI in a successor"); 765 break; 766 } 767 768 // Try to select the instruction with FastISel. 769 if (FastIS->SelectInstruction(BI)) 770 continue; 771 772 // Then handle certain instructions as single-LLVM-Instruction blocks. 773 if (isa<CallInst>(BI)) { 774 ++NumFastIselFailures; 775 if (EnableFastISelVerbose || EnableFastISelAbort) { 776 dbgs() << "FastISel missed call: "; 777 BI->dump(); 778 } 779 780 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 781 unsigned &R = FuncInfo->ValueMap[BI]; 782 if (!R) 783 R = FuncInfo->CreateRegForValue(BI); 784 } 785 786 bool HadTailCall = false; 787 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 788 789 // If the call was emitted as a tail call, we're done with the block. 790 if (HadTailCall) { 791 BI = End; 792 break; 793 } 794 795 // If the instruction was codegen'd with multiple blocks, 796 // inform the FastISel object where to resume inserting. 797 FastIS->setCurrentBlock(BB); 798 continue; 799 } 800 801 // Otherwise, give up on FastISel for the rest of the block. 802 // For now, be a little lenient about non-branch terminators. 803 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 804 ++NumFastIselFailures; 805 if (EnableFastISelVerbose || EnableFastISelAbort) { 806 dbgs() << "FastISel miss: "; 807 BI->dump(); 808 } 809 if (EnableFastISelAbort) 810 // The "fast" selector couldn't handle something and bailed. 811 // For the purpose of debugging, just abort. 812 llvm_unreachable("FastISel didn't select the entire block"); 813 } 814 break; 815 } 816 } 817 818 // Run SelectionDAG instruction selection on the remainder of the block 819 // not handled by FastISel. If FastISel is not run, this is the entire 820 // block. 821 if (BI != End) { 822 bool HadTailCall; 823 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 824 } 825 826 FinishBasicBlock(BB); 827 FuncInfo->PHINodesToUpdate.clear(); 828 } 829 830 delete FastIS; 831} 832 833void 834SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 835 836 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 837 DEBUG(BB->dump()); 838 839 DEBUG(dbgs() << "Total amount of phi nodes to update: " 840 << FuncInfo->PHINodesToUpdate.size() << "\n"); 841 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 842 dbgs() << "Node " << i << " : (" 843 << FuncInfo->PHINodesToUpdate[i].first 844 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 845 846 // Next, now that we know what the last MBB the LLVM BB expanded is, update 847 // PHI nodes in successors. 848 if (SDB->SwitchCases.empty() && 849 SDB->JTCases.empty() && 850 SDB->BitTestCases.empty()) { 851 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 852 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 853 assert(PHI->isPHI() && 854 "This is not a machine PHI node that we are updating!"); 855 if (!BB->isSuccessor(PHI->getParent())) 856 continue; 857 PHI->addOperand( 858 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 859 PHI->addOperand(MachineOperand::CreateMBB(BB)); 860 } 861 return; 862 } 863 864 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 865 // Lower header first, if it wasn't already lowered 866 if (!SDB->BitTestCases[i].Emitted) { 867 // Set the current basic block to the mbb we wish to insert the code into 868 BB = SDB->BitTestCases[i].Parent; 869 // Emit the code 870 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 871 CurDAG->setRoot(SDB->getRoot()); 872 BB = CodeGenAndEmitDAG(BB); 873 SDB->clear(); 874 } 875 876 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 877 // Set the current basic block to the mbb we wish to insert the code into 878 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 879 // Emit the code 880 if (j+1 != ej) 881 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 882 SDB->BitTestCases[i].Reg, 883 SDB->BitTestCases[i].Cases[j], 884 BB); 885 else 886 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 887 SDB->BitTestCases[i].Reg, 888 SDB->BitTestCases[i].Cases[j], 889 BB); 890 891 892 CurDAG->setRoot(SDB->getRoot()); 893 BB = CodeGenAndEmitDAG(BB); 894 SDB->clear(); 895 } 896 897 // Update PHI Nodes 898 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 899 pi != pe; ++pi) { 900 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 901 MachineBasicBlock *PHIBB = PHI->getParent(); 902 assert(PHI->isPHI() && 903 "This is not a machine PHI node that we are updating!"); 904 // This is "default" BB. We have two jumps to it. From "header" BB and 905 // from last "case" BB. 906 if (PHIBB == SDB->BitTestCases[i].Default) { 907 PHI->addOperand(MachineOperand:: 908 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 909 false)); 910 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 911 PHI->addOperand(MachineOperand:: 912 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 913 false)); 914 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 915 back().ThisBB)); 916 } 917 // One of "cases" BB. 918 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 919 j != ej; ++j) { 920 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 921 if (cBB->isSuccessor(PHIBB)) { 922 PHI->addOperand(MachineOperand:: 923 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 924 false)); 925 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 926 } 927 } 928 } 929 } 930 SDB->BitTestCases.clear(); 931 932 // If the JumpTable record is filled in, then we need to emit a jump table. 933 // Updating the PHI nodes is tricky in this case, since we need to determine 934 // whether the PHI is a successor of the range check MBB or the jump table MBB 935 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 936 // Lower header first, if it wasn't already lowered 937 if (!SDB->JTCases[i].first.Emitted) { 938 // Set the current basic block to the mbb we wish to insert the code into 939 BB = SDB->JTCases[i].first.HeaderBB; 940 // Emit the code 941 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 942 BB); 943 CurDAG->setRoot(SDB->getRoot()); 944 BB = CodeGenAndEmitDAG(BB); 945 SDB->clear(); 946 } 947 948 // Set the current basic block to the mbb we wish to insert the code into 949 BB = SDB->JTCases[i].second.MBB; 950 // Emit the code 951 SDB->visitJumpTable(SDB->JTCases[i].second); 952 CurDAG->setRoot(SDB->getRoot()); 953 BB = CodeGenAndEmitDAG(BB); 954 SDB->clear(); 955 956 // Update PHI Nodes 957 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 958 pi != pe; ++pi) { 959 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 960 MachineBasicBlock *PHIBB = PHI->getParent(); 961 assert(PHI->isPHI() && 962 "This is not a machine PHI node that we are updating!"); 963 // "default" BB. We can go there only from header BB. 964 if (PHIBB == SDB->JTCases[i].second.Default) { 965 PHI->addOperand 966 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 967 false)); 968 PHI->addOperand 969 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 970 } 971 // JT BB. Just iterate over successors here 972 if (BB->isSuccessor(PHIBB)) { 973 PHI->addOperand 974 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 975 false)); 976 PHI->addOperand(MachineOperand::CreateMBB(BB)); 977 } 978 } 979 } 980 SDB->JTCases.clear(); 981 982 // If the switch block involved a branch to one of the actual successors, we 983 // need to update PHI nodes in that block. 984 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 985 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 986 assert(PHI->isPHI() && 987 "This is not a machine PHI node that we are updating!"); 988 if (BB->isSuccessor(PHI->getParent())) { 989 PHI->addOperand( 990 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 991 PHI->addOperand(MachineOperand::CreateMBB(BB)); 992 } 993 } 994 995 // If we generated any switch lowering information, build and codegen any 996 // additional DAGs necessary. 997 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 998 // Set the current basic block to the mbb we wish to insert the code into 999 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1000 1001 // Emit the code 1002 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1003 CurDAG->setRoot(SDB->getRoot()); 1004 BB = CodeGenAndEmitDAG(BB); 1005 1006 // Handle any PHI nodes in successors of this chunk, as if we were coming 1007 // from the original BB before switch expansion. Note that PHI nodes can 1008 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1009 // handle them the right number of times. 1010 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1011 // If new BB's are created during scheduling, the edges may have been 1012 // updated. That is, the edge from ThisBB to BB may have been split and 1013 // BB's predecessor is now another block. 1014 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1015 SDB->EdgeMapping.find(BB); 1016 if (EI != SDB->EdgeMapping.end()) 1017 ThisBB = EI->second; 1018 1019 // BB may have been removed from the CFG if a branch was constant folded. 1020 if (ThisBB->isSuccessor(BB)) { 1021 for (MachineBasicBlock::iterator Phi = BB->begin(); 1022 Phi != BB->end() && Phi->isPHI(); 1023 ++Phi) { 1024 // This value for this PHI node is recorded in PHINodesToUpdate. 1025 for (unsigned pn = 0; ; ++pn) { 1026 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1027 "Didn't find PHI entry!"); 1028 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1029 Phi->addOperand(MachineOperand:: 1030 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1031 false)); 1032 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1033 break; 1034 } 1035 } 1036 } 1037 } 1038 1039 // Don't process RHS if same block as LHS. 1040 if (BB == SDB->SwitchCases[i].FalseBB) 1041 SDB->SwitchCases[i].FalseBB = 0; 1042 1043 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1044 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1045 SDB->SwitchCases[i].FalseBB = 0; 1046 } 1047 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1048 SDB->clear(); 1049 } 1050 SDB->SwitchCases.clear(); 1051} 1052 1053 1054/// Create the scheduler. If a specific scheduler was specified 1055/// via the SchedulerRegistry, use it, otherwise select the 1056/// one preferred by the target. 1057/// 1058ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1059 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1060 1061 if (!Ctor) { 1062 Ctor = ISHeuristic; 1063 RegisterScheduler::setDefault(Ctor); 1064 } 1065 1066 return Ctor(this, OptLevel); 1067} 1068 1069ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1070 return new ScheduleHazardRecognizer(); 1071} 1072 1073//===----------------------------------------------------------------------===// 1074// Helper functions used by the generated instruction selector. 1075//===----------------------------------------------------------------------===// 1076// Calls to these methods are generated by tblgen. 1077 1078/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1079/// the dag combiner simplified the 255, we still want to match. RHS is the 1080/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1081/// specified in the .td file (e.g. 255). 1082bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1083 int64_t DesiredMaskS) const { 1084 const APInt &ActualMask = RHS->getAPIntValue(); 1085 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1086 1087 // If the actual mask exactly matches, success! 1088 if (ActualMask == DesiredMask) 1089 return true; 1090 1091 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1092 if (ActualMask.intersects(~DesiredMask)) 1093 return false; 1094 1095 // Otherwise, the DAG Combiner may have proven that the value coming in is 1096 // either already zero or is not demanded. Check for known zero input bits. 1097 APInt NeededMask = DesiredMask & ~ActualMask; 1098 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1099 return true; 1100 1101 // TODO: check to see if missing bits are just not demanded. 1102 1103 // Otherwise, this pattern doesn't match. 1104 return false; 1105} 1106 1107/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1108/// the dag combiner simplified the 255, we still want to match. RHS is the 1109/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1110/// specified in the .td file (e.g. 255). 1111bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1112 int64_t DesiredMaskS) const { 1113 const APInt &ActualMask = RHS->getAPIntValue(); 1114 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1115 1116 // If the actual mask exactly matches, success! 1117 if (ActualMask == DesiredMask) 1118 return true; 1119 1120 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1121 if (ActualMask.intersects(~DesiredMask)) 1122 return false; 1123 1124 // Otherwise, the DAG Combiner may have proven that the value coming in is 1125 // either already zero or is not demanded. Check for known zero input bits. 1126 APInt NeededMask = DesiredMask & ~ActualMask; 1127 1128 APInt KnownZero, KnownOne; 1129 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1130 1131 // If all the missing bits in the or are already known to be set, match! 1132 if ((NeededMask & KnownOne) == NeededMask) 1133 return true; 1134 1135 // TODO: check to see if missing bits are just not demanded. 1136 1137 // Otherwise, this pattern doesn't match. 1138 return false; 1139} 1140 1141 1142/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1143/// by tblgen. Others should not call it. 1144void SelectionDAGISel:: 1145SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1146 std::vector<SDValue> InOps; 1147 std::swap(InOps, Ops); 1148 1149 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1150 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1151 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1152 1153 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1154 if (InOps[e-1].getValueType() == MVT::Flag) 1155 --e; // Don't process a flag operand if it is here. 1156 1157 while (i != e) { 1158 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1159 if (!InlineAsm::isMemKind(Flags)) { 1160 // Just skip over this operand, copying the operands verbatim. 1161 Ops.insert(Ops.end(), InOps.begin()+i, 1162 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1163 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1164 } else { 1165 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1166 "Memory operand with multiple values?"); 1167 // Otherwise, this is a memory operand. Ask the target to select it. 1168 std::vector<SDValue> SelOps; 1169 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1170 report_fatal_error("Could not match memory address. Inline asm" 1171 " failure!"); 1172 1173 // Add this to the output node. 1174 unsigned NewFlags = 1175 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1176 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1177 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1178 i += 2; 1179 } 1180 } 1181 1182 // Add the flag input back if present. 1183 if (e != InOps.size()) 1184 Ops.push_back(InOps.back()); 1185} 1186 1187/// findFlagUse - Return use of EVT::Flag value produced by the specified 1188/// SDNode. 1189/// 1190static SDNode *findFlagUse(SDNode *N) { 1191 unsigned FlagResNo = N->getNumValues()-1; 1192 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1193 SDUse &Use = I.getUse(); 1194 if (Use.getResNo() == FlagResNo) 1195 return Use.getUser(); 1196 } 1197 return NULL; 1198} 1199 1200/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1201/// This function recursively traverses up the operand chain, ignoring 1202/// certain nodes. 1203static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1204 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1205 bool IgnoreChains) { 1206 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1207 // greater than all of its (recursive) operands. If we scan to a point where 1208 // 'use' is smaller than the node we're scanning for, then we know we will 1209 // never find it. 1210 // 1211 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1212 // happen because we scan down to newly selected nodes in the case of flag 1213 // uses. 1214 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1215 return false; 1216 1217 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1218 // won't fail if we scan it again. 1219 if (!Visited.insert(Use)) 1220 return false; 1221 1222 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1223 // Ignore chain uses, they are validated by HandleMergeInputChains. 1224 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1225 continue; 1226 1227 SDNode *N = Use->getOperand(i).getNode(); 1228 if (N == Def) { 1229 if (Use == ImmedUse || Use == Root) 1230 continue; // We are not looking for immediate use. 1231 assert(N != Root); 1232 return true; 1233 } 1234 1235 // Traverse up the operand chain. 1236 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1237 return true; 1238 } 1239 return false; 1240} 1241 1242/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1243/// operand node N of U during instruction selection that starts at Root. 1244bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1245 SDNode *Root) const { 1246 if (OptLevel == CodeGenOpt::None) return false; 1247 return N.hasOneUse(); 1248} 1249 1250/// IsLegalToFold - Returns true if the specific operand node N of 1251/// U can be folded during instruction selection that starts at Root. 1252bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1253 CodeGenOpt::Level OptLevel, 1254 bool IgnoreChains) { 1255 if (OptLevel == CodeGenOpt::None) return false; 1256 1257 // If Root use can somehow reach N through a path that that doesn't contain 1258 // U then folding N would create a cycle. e.g. In the following 1259 // diagram, Root can reach N through X. If N is folded into into Root, then 1260 // X is both a predecessor and a successor of U. 1261 // 1262 // [N*] // 1263 // ^ ^ // 1264 // / \ // 1265 // [U*] [X]? // 1266 // ^ ^ // 1267 // \ / // 1268 // \ / // 1269 // [Root*] // 1270 // 1271 // * indicates nodes to be folded together. 1272 // 1273 // If Root produces a flag, then it gets (even more) interesting. Since it 1274 // will be "glued" together with its flag use in the scheduler, we need to 1275 // check if it might reach N. 1276 // 1277 // [N*] // 1278 // ^ ^ // 1279 // / \ // 1280 // [U*] [X]? // 1281 // ^ ^ // 1282 // \ \ // 1283 // \ | // 1284 // [Root*] | // 1285 // ^ | // 1286 // f | // 1287 // | / // 1288 // [Y] / // 1289 // ^ / // 1290 // f / // 1291 // | / // 1292 // [FU] // 1293 // 1294 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1295 // (call it Fold), then X is a predecessor of FU and a successor of 1296 // Fold. But since Fold and FU are flagged together, this will create 1297 // a cycle in the scheduling graph. 1298 1299 // If the node has flags, walk down the graph to the "lowest" node in the 1300 // flagged set. 1301 EVT VT = Root->getValueType(Root->getNumValues()-1); 1302 while (VT == MVT::Flag) { 1303 SDNode *FU = findFlagUse(Root); 1304 if (FU == NULL) 1305 break; 1306 Root = FU; 1307 VT = Root->getValueType(Root->getNumValues()-1); 1308 1309 // If our query node has a flag result with a use, we've walked up it. If 1310 // the user (which has already been selected) has a chain or indirectly uses 1311 // the chain, our WalkChainUsers predicate will not consider it. Because of 1312 // this, we cannot ignore chains in this predicate. 1313 IgnoreChains = false; 1314 } 1315 1316 1317 SmallPtrSet<SDNode*, 16> Visited; 1318 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1319} 1320 1321SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1322 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1323 SelectInlineAsmMemoryOperands(Ops); 1324 1325 std::vector<EVT> VTs; 1326 VTs.push_back(MVT::Other); 1327 VTs.push_back(MVT::Flag); 1328 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1329 VTs, &Ops[0], Ops.size()); 1330 New->setNodeId(-1); 1331 return New.getNode(); 1332} 1333 1334SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1335 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1336} 1337 1338/// GetVBR - decode a vbr encoding whose top bit is set. 1339ALWAYS_INLINE static uint64_t 1340GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1341 assert(Val >= 128 && "Not a VBR"); 1342 Val &= 127; // Remove first vbr bit. 1343 1344 unsigned Shift = 7; 1345 uint64_t NextBits; 1346 do { 1347 NextBits = MatcherTable[Idx++]; 1348 Val |= (NextBits&127) << Shift; 1349 Shift += 7; 1350 } while (NextBits & 128); 1351 1352 return Val; 1353} 1354 1355 1356/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1357/// interior flag and chain results to use the new flag and chain results. 1358void SelectionDAGISel:: 1359UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1360 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1361 SDValue InputFlag, 1362 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1363 bool isMorphNodeTo) { 1364 SmallVector<SDNode*, 4> NowDeadNodes; 1365 1366 ISelUpdater ISU(ISelPosition); 1367 1368 // Now that all the normal results are replaced, we replace the chain and 1369 // flag results if present. 1370 if (!ChainNodesMatched.empty()) { 1371 assert(InputChain.getNode() != 0 && 1372 "Matched input chains but didn't produce a chain"); 1373 // Loop over all of the nodes we matched that produced a chain result. 1374 // Replace all the chain results with the final chain we ended up with. 1375 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1376 SDNode *ChainNode = ChainNodesMatched[i]; 1377 1378 // If this node was already deleted, don't look at it. 1379 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1380 continue; 1381 1382 // Don't replace the results of the root node if we're doing a 1383 // MorphNodeTo. 1384 if (ChainNode == NodeToMatch && isMorphNodeTo) 1385 continue; 1386 1387 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1388 if (ChainVal.getValueType() == MVT::Flag) 1389 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1390 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1391 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1392 1393 // If the node became dead and we haven't already seen it, delete it. 1394 if (ChainNode->use_empty() && 1395 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1396 NowDeadNodes.push_back(ChainNode); 1397 } 1398 } 1399 1400 // If the result produces a flag, update any flag results in the matched 1401 // pattern with the flag result. 1402 if (InputFlag.getNode() != 0) { 1403 // Handle any interior nodes explicitly marked. 1404 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1405 SDNode *FRN = FlagResultNodesMatched[i]; 1406 1407 // If this node was already deleted, don't look at it. 1408 if (FRN->getOpcode() == ISD::DELETED_NODE) 1409 continue; 1410 1411 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1412 "Doesn't have a flag result"); 1413 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1414 InputFlag, &ISU); 1415 1416 // If the node became dead and we haven't already seen it, delete it. 1417 if (FRN->use_empty() && 1418 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1419 NowDeadNodes.push_back(FRN); 1420 } 1421 } 1422 1423 if (!NowDeadNodes.empty()) 1424 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1425 1426 DEBUG(errs() << "ISEL: Match complete!\n"); 1427} 1428 1429enum ChainResult { 1430 CR_Simple, 1431 CR_InducesCycle, 1432 CR_LeadsToInteriorNode 1433}; 1434 1435/// WalkChainUsers - Walk down the users of the specified chained node that is 1436/// part of the pattern we're matching, looking at all of the users we find. 1437/// This determines whether something is an interior node, whether we have a 1438/// non-pattern node in between two pattern nodes (which prevent folding because 1439/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1440/// between pattern nodes (in which case the TF becomes part of the pattern). 1441/// 1442/// The walk we do here is guaranteed to be small because we quickly get down to 1443/// already selected nodes "below" us. 1444static ChainResult 1445WalkChainUsers(SDNode *ChainedNode, 1446 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1447 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1448 ChainResult Result = CR_Simple; 1449 1450 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1451 E = ChainedNode->use_end(); UI != E; ++UI) { 1452 // Make sure the use is of the chain, not some other value we produce. 1453 if (UI.getUse().getValueType() != MVT::Other) continue; 1454 1455 SDNode *User = *UI; 1456 1457 // If we see an already-selected machine node, then we've gone beyond the 1458 // pattern that we're selecting down into the already selected chunk of the 1459 // DAG. 1460 if (User->isMachineOpcode() || 1461 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1462 continue; 1463 1464 if (User->getOpcode() == ISD::CopyToReg || 1465 User->getOpcode() == ISD::CopyFromReg || 1466 User->getOpcode() == ISD::INLINEASM || 1467 User->getOpcode() == ISD::EH_LABEL) { 1468 // If their node ID got reset to -1 then they've already been selected. 1469 // Treat them like a MachineOpcode. 1470 if (User->getNodeId() == -1) 1471 continue; 1472 } 1473 1474 // If we have a TokenFactor, we handle it specially. 1475 if (User->getOpcode() != ISD::TokenFactor) { 1476 // If the node isn't a token factor and isn't part of our pattern, then it 1477 // must be a random chained node in between two nodes we're selecting. 1478 // This happens when we have something like: 1479 // x = load ptr 1480 // call 1481 // y = x+4 1482 // store y -> ptr 1483 // Because we structurally match the load/store as a read/modify/write, 1484 // but the call is chained between them. We cannot fold in this case 1485 // because it would induce a cycle in the graph. 1486 if (!std::count(ChainedNodesInPattern.begin(), 1487 ChainedNodesInPattern.end(), User)) 1488 return CR_InducesCycle; 1489 1490 // Otherwise we found a node that is part of our pattern. For example in: 1491 // x = load ptr 1492 // y = x+4 1493 // store y -> ptr 1494 // This would happen when we're scanning down from the load and see the 1495 // store as a user. Record that there is a use of ChainedNode that is 1496 // part of the pattern and keep scanning uses. 1497 Result = CR_LeadsToInteriorNode; 1498 InteriorChainedNodes.push_back(User); 1499 continue; 1500 } 1501 1502 // If we found a TokenFactor, there are two cases to consider: first if the 1503 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1504 // uses of the TF are in our pattern) we just want to ignore it. Second, 1505 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1506 // [Load chain] 1507 // ^ 1508 // | 1509 // [Load] 1510 // ^ ^ 1511 // | \ DAG's like cheese 1512 // / \ do you? 1513 // / | 1514 // [TokenFactor] [Op] 1515 // ^ ^ 1516 // | | 1517 // \ / 1518 // \ / 1519 // [Store] 1520 // 1521 // In this case, the TokenFactor becomes part of our match and we rewrite it 1522 // as a new TokenFactor. 1523 // 1524 // To distinguish these two cases, do a recursive walk down the uses. 1525 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1526 case CR_Simple: 1527 // If the uses of the TokenFactor are just already-selected nodes, ignore 1528 // it, it is "below" our pattern. 1529 continue; 1530 case CR_InducesCycle: 1531 // If the uses of the TokenFactor lead to nodes that are not part of our 1532 // pattern that are not selected, folding would turn this into a cycle, 1533 // bail out now. 1534 return CR_InducesCycle; 1535 case CR_LeadsToInteriorNode: 1536 break; // Otherwise, keep processing. 1537 } 1538 1539 // Okay, we know we're in the interesting interior case. The TokenFactor 1540 // is now going to be considered part of the pattern so that we rewrite its 1541 // uses (it may have uses that are not part of the pattern) with the 1542 // ultimate chain result of the generated code. We will also add its chain 1543 // inputs as inputs to the ultimate TokenFactor we create. 1544 Result = CR_LeadsToInteriorNode; 1545 ChainedNodesInPattern.push_back(User); 1546 InteriorChainedNodes.push_back(User); 1547 continue; 1548 } 1549 1550 return Result; 1551} 1552 1553/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1554/// operation for when the pattern matched at least one node with a chains. The 1555/// input vector contains a list of all of the chained nodes that we match. We 1556/// must determine if this is a valid thing to cover (i.e. matching it won't 1557/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1558/// be used as the input node chain for the generated nodes. 1559static SDValue 1560HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1561 SelectionDAG *CurDAG) { 1562 // Walk all of the chained nodes we've matched, recursively scanning down the 1563 // users of the chain result. This adds any TokenFactor nodes that are caught 1564 // in between chained nodes to the chained and interior nodes list. 1565 SmallVector<SDNode*, 3> InteriorChainedNodes; 1566 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1567 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1568 InteriorChainedNodes) == CR_InducesCycle) 1569 return SDValue(); // Would induce a cycle. 1570 } 1571 1572 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1573 // that we are interested in. Form our input TokenFactor node. 1574 SmallVector<SDValue, 3> InputChains; 1575 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1576 // Add the input chain of this node to the InputChains list (which will be 1577 // the operands of the generated TokenFactor) if it's not an interior node. 1578 SDNode *N = ChainNodesMatched[i]; 1579 if (N->getOpcode() != ISD::TokenFactor) { 1580 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1581 continue; 1582 1583 // Otherwise, add the input chain. 1584 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1585 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1586 InputChains.push_back(InChain); 1587 continue; 1588 } 1589 1590 // If we have a token factor, we want to add all inputs of the token factor 1591 // that are not part of the pattern we're matching. 1592 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1593 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1594 N->getOperand(op).getNode())) 1595 InputChains.push_back(N->getOperand(op)); 1596 } 1597 } 1598 1599 SDValue Res; 1600 if (InputChains.size() == 1) 1601 return InputChains[0]; 1602 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1603 MVT::Other, &InputChains[0], InputChains.size()); 1604} 1605 1606/// MorphNode - Handle morphing a node in place for the selector. 1607SDNode *SelectionDAGISel:: 1608MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1609 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1610 // It is possible we're using MorphNodeTo to replace a node with no 1611 // normal results with one that has a normal result (or we could be 1612 // adding a chain) and the input could have flags and chains as well. 1613 // In this case we need to shift the operands down. 1614 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1615 // than the old isel though. 1616 int OldFlagResultNo = -1, OldChainResultNo = -1; 1617 1618 unsigned NTMNumResults = Node->getNumValues(); 1619 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1620 OldFlagResultNo = NTMNumResults-1; 1621 if (NTMNumResults != 1 && 1622 Node->getValueType(NTMNumResults-2) == MVT::Other) 1623 OldChainResultNo = NTMNumResults-2; 1624 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1625 OldChainResultNo = NTMNumResults-1; 1626 1627 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1628 // that this deletes operands of the old node that become dead. 1629 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1630 1631 // MorphNodeTo can operate in two ways: if an existing node with the 1632 // specified operands exists, it can just return it. Otherwise, it 1633 // updates the node in place to have the requested operands. 1634 if (Res == Node) { 1635 // If we updated the node in place, reset the node ID. To the isel, 1636 // this should be just like a newly allocated machine node. 1637 Res->setNodeId(-1); 1638 } 1639 1640 unsigned ResNumResults = Res->getNumValues(); 1641 // Move the flag if needed. 1642 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1643 (unsigned)OldFlagResultNo != ResNumResults-1) 1644 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1645 SDValue(Res, ResNumResults-1)); 1646 1647 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1648 --ResNumResults; 1649 1650 // Move the chain reference if needed. 1651 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1652 (unsigned)OldChainResultNo != ResNumResults-1) 1653 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1654 SDValue(Res, ResNumResults-1)); 1655 1656 // Otherwise, no replacement happened because the node already exists. Replace 1657 // Uses of the old node with the new one. 1658 if (Res != Node) 1659 CurDAG->ReplaceAllUsesWith(Node, Res); 1660 1661 return Res; 1662} 1663 1664/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1665ALWAYS_INLINE static bool 1666CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1667 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1668 // Accept if it is exactly the same as a previously recorded node. 1669 unsigned RecNo = MatcherTable[MatcherIndex++]; 1670 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1671 return N == RecordedNodes[RecNo]; 1672} 1673 1674/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1675ALWAYS_INLINE static bool 1676CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1677 SelectionDAGISel &SDISel) { 1678 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1679} 1680 1681/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1682ALWAYS_INLINE static bool 1683CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1684 SelectionDAGISel &SDISel, SDNode *N) { 1685 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1686} 1687 1688ALWAYS_INLINE static bool 1689CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1690 SDNode *N) { 1691 uint16_t Opc = MatcherTable[MatcherIndex++]; 1692 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1693 return N->getOpcode() == Opc; 1694} 1695 1696ALWAYS_INLINE static bool 1697CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1698 SDValue N, const TargetLowering &TLI) { 1699 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1700 if (N.getValueType() == VT) return true; 1701 1702 // Handle the case when VT is iPTR. 1703 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1704} 1705 1706ALWAYS_INLINE static bool 1707CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1708 SDValue N, const TargetLowering &TLI, 1709 unsigned ChildNo) { 1710 if (ChildNo >= N.getNumOperands()) 1711 return false; // Match fails if out of range child #. 1712 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1713} 1714 1715 1716ALWAYS_INLINE static bool 1717CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1718 SDValue N) { 1719 return cast<CondCodeSDNode>(N)->get() == 1720 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1721} 1722 1723ALWAYS_INLINE static bool 1724CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1725 SDValue N, const TargetLowering &TLI) { 1726 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1727 if (cast<VTSDNode>(N)->getVT() == VT) 1728 return true; 1729 1730 // Handle the case when VT is iPTR. 1731 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1732} 1733 1734ALWAYS_INLINE static bool 1735CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1736 SDValue N) { 1737 int64_t Val = MatcherTable[MatcherIndex++]; 1738 if (Val & 128) 1739 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1740 1741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1742 return C != 0 && C->getSExtValue() == Val; 1743} 1744 1745ALWAYS_INLINE static bool 1746CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1747 SDValue N, SelectionDAGISel &SDISel) { 1748 int64_t Val = MatcherTable[MatcherIndex++]; 1749 if (Val & 128) 1750 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1751 1752 if (N->getOpcode() != ISD::AND) return false; 1753 1754 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1755 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1756} 1757 1758ALWAYS_INLINE static bool 1759CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1760 SDValue N, SelectionDAGISel &SDISel) { 1761 int64_t Val = MatcherTable[MatcherIndex++]; 1762 if (Val & 128) 1763 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1764 1765 if (N->getOpcode() != ISD::OR) return false; 1766 1767 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1768 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1769} 1770 1771/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1772/// scope, evaluate the current node. If the current predicate is known to 1773/// fail, set Result=true and return anything. If the current predicate is 1774/// known to pass, set Result=false and return the MatcherIndex to continue 1775/// with. If the current predicate is unknown, set Result=false and return the 1776/// MatcherIndex to continue with. 1777static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1778 unsigned Index, SDValue N, 1779 bool &Result, SelectionDAGISel &SDISel, 1780 SmallVectorImpl<SDValue> &RecordedNodes){ 1781 switch (Table[Index++]) { 1782 default: 1783 Result = false; 1784 return Index-1; // Could not evaluate this predicate. 1785 case SelectionDAGISel::OPC_CheckSame: 1786 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1787 return Index; 1788 case SelectionDAGISel::OPC_CheckPatternPredicate: 1789 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1790 return Index; 1791 case SelectionDAGISel::OPC_CheckPredicate: 1792 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1793 return Index; 1794 case SelectionDAGISel::OPC_CheckOpcode: 1795 Result = !::CheckOpcode(Table, Index, N.getNode()); 1796 return Index; 1797 case SelectionDAGISel::OPC_CheckType: 1798 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1799 return Index; 1800 case SelectionDAGISel::OPC_CheckChild0Type: 1801 case SelectionDAGISel::OPC_CheckChild1Type: 1802 case SelectionDAGISel::OPC_CheckChild2Type: 1803 case SelectionDAGISel::OPC_CheckChild3Type: 1804 case SelectionDAGISel::OPC_CheckChild4Type: 1805 case SelectionDAGISel::OPC_CheckChild5Type: 1806 case SelectionDAGISel::OPC_CheckChild6Type: 1807 case SelectionDAGISel::OPC_CheckChild7Type: 1808 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1809 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1810 return Index; 1811 case SelectionDAGISel::OPC_CheckCondCode: 1812 Result = !::CheckCondCode(Table, Index, N); 1813 return Index; 1814 case SelectionDAGISel::OPC_CheckValueType: 1815 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1816 return Index; 1817 case SelectionDAGISel::OPC_CheckInteger: 1818 Result = !::CheckInteger(Table, Index, N); 1819 return Index; 1820 case SelectionDAGISel::OPC_CheckAndImm: 1821 Result = !::CheckAndImm(Table, Index, N, SDISel); 1822 return Index; 1823 case SelectionDAGISel::OPC_CheckOrImm: 1824 Result = !::CheckOrImm(Table, Index, N, SDISel); 1825 return Index; 1826 } 1827} 1828 1829namespace { 1830 1831struct MatchScope { 1832 /// FailIndex - If this match fails, this is the index to continue with. 1833 unsigned FailIndex; 1834 1835 /// NodeStack - The node stack when the scope was formed. 1836 SmallVector<SDValue, 4> NodeStack; 1837 1838 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1839 unsigned NumRecordedNodes; 1840 1841 /// NumMatchedMemRefs - The number of matched memref entries. 1842 unsigned NumMatchedMemRefs; 1843 1844 /// InputChain/InputFlag - The current chain/flag 1845 SDValue InputChain, InputFlag; 1846 1847 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1848 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1849}; 1850 1851} 1852 1853SDNode *SelectionDAGISel:: 1854SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1855 unsigned TableSize) { 1856 // FIXME: Should these even be selected? Handle these cases in the caller? 1857 switch (NodeToMatch->getOpcode()) { 1858 default: 1859 break; 1860 case ISD::EntryToken: // These nodes remain the same. 1861 case ISD::BasicBlock: 1862 case ISD::Register: 1863 //case ISD::VALUETYPE: 1864 //case ISD::CONDCODE: 1865 case ISD::HANDLENODE: 1866 case ISD::MDNODE_SDNODE: 1867 case ISD::TargetConstant: 1868 case ISD::TargetConstantFP: 1869 case ISD::TargetConstantPool: 1870 case ISD::TargetFrameIndex: 1871 case ISD::TargetExternalSymbol: 1872 case ISD::TargetBlockAddress: 1873 case ISD::TargetJumpTable: 1874 case ISD::TargetGlobalTLSAddress: 1875 case ISD::TargetGlobalAddress: 1876 case ISD::TokenFactor: 1877 case ISD::CopyFromReg: 1878 case ISD::CopyToReg: 1879 case ISD::EH_LABEL: 1880 NodeToMatch->setNodeId(-1); // Mark selected. 1881 return 0; 1882 case ISD::AssertSext: 1883 case ISD::AssertZext: 1884 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1885 NodeToMatch->getOperand(0)); 1886 return 0; 1887 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1888 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1889 } 1890 1891 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1892 1893 // Set up the node stack with NodeToMatch as the only node on the stack. 1894 SmallVector<SDValue, 8> NodeStack; 1895 SDValue N = SDValue(NodeToMatch, 0); 1896 NodeStack.push_back(N); 1897 1898 // MatchScopes - Scopes used when matching, if a match failure happens, this 1899 // indicates where to continue checking. 1900 SmallVector<MatchScope, 8> MatchScopes; 1901 1902 // RecordedNodes - This is the set of nodes that have been recorded by the 1903 // state machine. 1904 SmallVector<SDValue, 8> RecordedNodes; 1905 1906 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1907 // pattern. 1908 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1909 1910 // These are the current input chain and flag for use when generating nodes. 1911 // Various Emit operations change these. For example, emitting a copytoreg 1912 // uses and updates these. 1913 SDValue InputChain, InputFlag; 1914 1915 // ChainNodesMatched - If a pattern matches nodes that have input/output 1916 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1917 // which ones they are. The result is captured into this list so that we can 1918 // update the chain results when the pattern is complete. 1919 SmallVector<SDNode*, 3> ChainNodesMatched; 1920 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1921 1922 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1923 NodeToMatch->dump(CurDAG); 1924 errs() << '\n'); 1925 1926 // Determine where to start the interpreter. Normally we start at opcode #0, 1927 // but if the state machine starts with an OPC_SwitchOpcode, then we 1928 // accelerate the first lookup (which is guaranteed to be hot) with the 1929 // OpcodeOffset table. 1930 unsigned MatcherIndex = 0; 1931 1932 if (!OpcodeOffset.empty()) { 1933 // Already computed the OpcodeOffset table, just index into it. 1934 if (N.getOpcode() < OpcodeOffset.size()) 1935 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1936 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1937 1938 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1939 // Otherwise, the table isn't computed, but the state machine does start 1940 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1941 // is the first time we're selecting an instruction. 1942 unsigned Idx = 1; 1943 while (1) { 1944 // Get the size of this case. 1945 unsigned CaseSize = MatcherTable[Idx++]; 1946 if (CaseSize & 128) 1947 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1948 if (CaseSize == 0) break; 1949 1950 // Get the opcode, add the index to the table. 1951 uint16_t Opc = MatcherTable[Idx++]; 1952 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1953 if (Opc >= OpcodeOffset.size()) 1954 OpcodeOffset.resize((Opc+1)*2); 1955 OpcodeOffset[Opc] = Idx; 1956 Idx += CaseSize; 1957 } 1958 1959 // Okay, do the lookup for the first opcode. 1960 if (N.getOpcode() < OpcodeOffset.size()) 1961 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1962 } 1963 1964 while (1) { 1965 assert(MatcherIndex < TableSize && "Invalid index"); 1966#ifndef NDEBUG 1967 unsigned CurrentOpcodeIndex = MatcherIndex; 1968#endif 1969 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1970 switch (Opcode) { 1971 case OPC_Scope: { 1972 // Okay, the semantics of this operation are that we should push a scope 1973 // then evaluate the first child. However, pushing a scope only to have 1974 // the first check fail (which then pops it) is inefficient. If we can 1975 // determine immediately that the first check (or first several) will 1976 // immediately fail, don't even bother pushing a scope for them. 1977 unsigned FailIndex; 1978 1979 while (1) { 1980 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1981 if (NumToSkip & 128) 1982 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1983 // Found the end of the scope with no match. 1984 if (NumToSkip == 0) { 1985 FailIndex = 0; 1986 break; 1987 } 1988 1989 FailIndex = MatcherIndex+NumToSkip; 1990 1991 unsigned MatcherIndexOfPredicate = MatcherIndex; 1992 (void)MatcherIndexOfPredicate; // silence warning. 1993 1994 // If we can't evaluate this predicate without pushing a scope (e.g. if 1995 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1996 // push the scope and evaluate the full predicate chain. 1997 bool Result; 1998 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1999 Result, *this, RecordedNodes); 2000 if (!Result) 2001 break; 2002 2003 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2004 << "index " << MatcherIndexOfPredicate 2005 << ", continuing at " << FailIndex << "\n"); 2006 ++NumDAGIselRetries; 2007 2008 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2009 // move to the next case. 2010 MatcherIndex = FailIndex; 2011 } 2012 2013 // If the whole scope failed to match, bail. 2014 if (FailIndex == 0) break; 2015 2016 // Push a MatchScope which indicates where to go if the first child fails 2017 // to match. 2018 MatchScope NewEntry; 2019 NewEntry.FailIndex = FailIndex; 2020 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2021 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2022 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2023 NewEntry.InputChain = InputChain; 2024 NewEntry.InputFlag = InputFlag; 2025 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2026 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2027 MatchScopes.push_back(NewEntry); 2028 continue; 2029 } 2030 case OPC_RecordNode: 2031 // Remember this node, it may end up being an operand in the pattern. 2032 RecordedNodes.push_back(N); 2033 continue; 2034 2035 case OPC_RecordChild0: case OPC_RecordChild1: 2036 case OPC_RecordChild2: case OPC_RecordChild3: 2037 case OPC_RecordChild4: case OPC_RecordChild5: 2038 case OPC_RecordChild6: case OPC_RecordChild7: { 2039 unsigned ChildNo = Opcode-OPC_RecordChild0; 2040 if (ChildNo >= N.getNumOperands()) 2041 break; // Match fails if out of range child #. 2042 2043 RecordedNodes.push_back(N->getOperand(ChildNo)); 2044 continue; 2045 } 2046 case OPC_RecordMemRef: 2047 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2048 continue; 2049 2050 case OPC_CaptureFlagInput: 2051 // If the current node has an input flag, capture it in InputFlag. 2052 if (N->getNumOperands() != 0 && 2053 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2054 InputFlag = N->getOperand(N->getNumOperands()-1); 2055 continue; 2056 2057 case OPC_MoveChild: { 2058 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2059 if (ChildNo >= N.getNumOperands()) 2060 break; // Match fails if out of range child #. 2061 N = N.getOperand(ChildNo); 2062 NodeStack.push_back(N); 2063 continue; 2064 } 2065 2066 case OPC_MoveParent: 2067 // Pop the current node off the NodeStack. 2068 NodeStack.pop_back(); 2069 assert(!NodeStack.empty() && "Node stack imbalance!"); 2070 N = NodeStack.back(); 2071 continue; 2072 2073 case OPC_CheckSame: 2074 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2075 continue; 2076 case OPC_CheckPatternPredicate: 2077 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2078 continue; 2079 case OPC_CheckPredicate: 2080 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2081 N.getNode())) 2082 break; 2083 continue; 2084 case OPC_CheckComplexPat: { 2085 unsigned CPNum = MatcherTable[MatcherIndex++]; 2086 unsigned RecNo = MatcherTable[MatcherIndex++]; 2087 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2088 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2089 RecordedNodes)) 2090 break; 2091 continue; 2092 } 2093 case OPC_CheckOpcode: 2094 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2095 continue; 2096 2097 case OPC_CheckType: 2098 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2099 continue; 2100 2101 case OPC_SwitchOpcode: { 2102 unsigned CurNodeOpcode = N.getOpcode(); 2103 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2104 unsigned CaseSize; 2105 while (1) { 2106 // Get the size of this case. 2107 CaseSize = MatcherTable[MatcherIndex++]; 2108 if (CaseSize & 128) 2109 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2110 if (CaseSize == 0) break; 2111 2112 uint16_t Opc = MatcherTable[MatcherIndex++]; 2113 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2114 2115 // If the opcode matches, then we will execute this case. 2116 if (CurNodeOpcode == Opc) 2117 break; 2118 2119 // Otherwise, skip over this case. 2120 MatcherIndex += CaseSize; 2121 } 2122 2123 // If no cases matched, bail out. 2124 if (CaseSize == 0) break; 2125 2126 // Otherwise, execute the case we found. 2127 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2128 << " to " << MatcherIndex << "\n"); 2129 continue; 2130 } 2131 2132 case OPC_SwitchType: { 2133 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2134 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2135 unsigned CaseSize; 2136 while (1) { 2137 // Get the size of this case. 2138 CaseSize = MatcherTable[MatcherIndex++]; 2139 if (CaseSize & 128) 2140 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2141 if (CaseSize == 0) break; 2142 2143 MVT::SimpleValueType CaseVT = 2144 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2145 if (CaseVT == MVT::iPTR) 2146 CaseVT = TLI.getPointerTy().SimpleTy; 2147 2148 // If the VT matches, then we will execute this case. 2149 if (CurNodeVT == CaseVT) 2150 break; 2151 2152 // Otherwise, skip over this case. 2153 MatcherIndex += CaseSize; 2154 } 2155 2156 // If no cases matched, bail out. 2157 if (CaseSize == 0) break; 2158 2159 // Otherwise, execute the case we found. 2160 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2161 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2162 continue; 2163 } 2164 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2165 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2166 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2167 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2168 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2169 Opcode-OPC_CheckChild0Type)) 2170 break; 2171 continue; 2172 case OPC_CheckCondCode: 2173 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2174 continue; 2175 case OPC_CheckValueType: 2176 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2177 continue; 2178 case OPC_CheckInteger: 2179 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2180 continue; 2181 case OPC_CheckAndImm: 2182 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2183 continue; 2184 case OPC_CheckOrImm: 2185 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2186 continue; 2187 2188 case OPC_CheckFoldableChainNode: { 2189 assert(NodeStack.size() != 1 && "No parent node"); 2190 // Verify that all intermediate nodes between the root and this one have 2191 // a single use. 2192 bool HasMultipleUses = false; 2193 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2194 if (!NodeStack[i].hasOneUse()) { 2195 HasMultipleUses = true; 2196 break; 2197 } 2198 if (HasMultipleUses) break; 2199 2200 // Check to see that the target thinks this is profitable to fold and that 2201 // we can fold it without inducing cycles in the graph. 2202 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2203 NodeToMatch) || 2204 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2205 NodeToMatch, OptLevel, 2206 true/*We validate our own chains*/)) 2207 break; 2208 2209 continue; 2210 } 2211 case OPC_EmitInteger: { 2212 MVT::SimpleValueType VT = 2213 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2214 int64_t Val = MatcherTable[MatcherIndex++]; 2215 if (Val & 128) 2216 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2217 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2218 continue; 2219 } 2220 case OPC_EmitRegister: { 2221 MVT::SimpleValueType VT = 2222 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2223 unsigned RegNo = MatcherTable[MatcherIndex++]; 2224 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2225 continue; 2226 } 2227 2228 case OPC_EmitConvertToTarget: { 2229 // Convert from IMM/FPIMM to target version. 2230 unsigned RecNo = MatcherTable[MatcherIndex++]; 2231 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2232 SDValue Imm = RecordedNodes[RecNo]; 2233 2234 if (Imm->getOpcode() == ISD::Constant) { 2235 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2236 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2237 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2238 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2239 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2240 } 2241 2242 RecordedNodes.push_back(Imm); 2243 continue; 2244 } 2245 2246 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2247 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2248 // These are space-optimized forms of OPC_EmitMergeInputChains. 2249 assert(InputChain.getNode() == 0 && 2250 "EmitMergeInputChains should be the first chain producing node"); 2251 assert(ChainNodesMatched.empty() && 2252 "Should only have one EmitMergeInputChains per match"); 2253 2254 // Read all of the chained nodes. 2255 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2256 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2257 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2258 2259 // FIXME: What if other value results of the node have uses not matched 2260 // by this pattern? 2261 if (ChainNodesMatched.back() != NodeToMatch && 2262 !RecordedNodes[RecNo].hasOneUse()) { 2263 ChainNodesMatched.clear(); 2264 break; 2265 } 2266 2267 // Merge the input chains if they are not intra-pattern references. 2268 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2269 2270 if (InputChain.getNode() == 0) 2271 break; // Failed to merge. 2272 continue; 2273 } 2274 2275 case OPC_EmitMergeInputChains: { 2276 assert(InputChain.getNode() == 0 && 2277 "EmitMergeInputChains should be the first chain producing node"); 2278 // This node gets a list of nodes we matched in the input that have 2279 // chains. We want to token factor all of the input chains to these nodes 2280 // together. However, if any of the input chains is actually one of the 2281 // nodes matched in this pattern, then we have an intra-match reference. 2282 // Ignore these because the newly token factored chain should not refer to 2283 // the old nodes. 2284 unsigned NumChains = MatcherTable[MatcherIndex++]; 2285 assert(NumChains != 0 && "Can't TF zero chains"); 2286 2287 assert(ChainNodesMatched.empty() && 2288 "Should only have one EmitMergeInputChains per match"); 2289 2290 // Read all of the chained nodes. 2291 for (unsigned i = 0; i != NumChains; ++i) { 2292 unsigned RecNo = MatcherTable[MatcherIndex++]; 2293 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2294 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2295 2296 // FIXME: What if other value results of the node have uses not matched 2297 // by this pattern? 2298 if (ChainNodesMatched.back() != NodeToMatch && 2299 !RecordedNodes[RecNo].hasOneUse()) { 2300 ChainNodesMatched.clear(); 2301 break; 2302 } 2303 } 2304 2305 // If the inner loop broke out, the match fails. 2306 if (ChainNodesMatched.empty()) 2307 break; 2308 2309 // Merge the input chains if they are not intra-pattern references. 2310 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2311 2312 if (InputChain.getNode() == 0) 2313 break; // Failed to merge. 2314 2315 continue; 2316 } 2317 2318 case OPC_EmitCopyToReg: { 2319 unsigned RecNo = MatcherTable[MatcherIndex++]; 2320 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2321 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2322 2323 if (InputChain.getNode() == 0) 2324 InputChain = CurDAG->getEntryNode(); 2325 2326 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2327 DestPhysReg, RecordedNodes[RecNo], 2328 InputFlag); 2329 2330 InputFlag = InputChain.getValue(1); 2331 continue; 2332 } 2333 2334 case OPC_EmitNodeXForm: { 2335 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2336 unsigned RecNo = MatcherTable[MatcherIndex++]; 2337 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2338 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2339 continue; 2340 } 2341 2342 case OPC_EmitNode: 2343 case OPC_MorphNodeTo: { 2344 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2345 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2346 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2347 // Get the result VT list. 2348 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2349 SmallVector<EVT, 4> VTs; 2350 for (unsigned i = 0; i != NumVTs; ++i) { 2351 MVT::SimpleValueType VT = 2352 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2353 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2354 VTs.push_back(VT); 2355 } 2356 2357 if (EmitNodeInfo & OPFL_Chain) 2358 VTs.push_back(MVT::Other); 2359 if (EmitNodeInfo & OPFL_FlagOutput) 2360 VTs.push_back(MVT::Flag); 2361 2362 // This is hot code, so optimize the two most common cases of 1 and 2 2363 // results. 2364 SDVTList VTList; 2365 if (VTs.size() == 1) 2366 VTList = CurDAG->getVTList(VTs[0]); 2367 else if (VTs.size() == 2) 2368 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2369 else 2370 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2371 2372 // Get the operand list. 2373 unsigned NumOps = MatcherTable[MatcherIndex++]; 2374 SmallVector<SDValue, 8> Ops; 2375 for (unsigned i = 0; i != NumOps; ++i) { 2376 unsigned RecNo = MatcherTable[MatcherIndex++]; 2377 if (RecNo & 128) 2378 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2379 2380 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2381 Ops.push_back(RecordedNodes[RecNo]); 2382 } 2383 2384 // If there are variadic operands to add, handle them now. 2385 if (EmitNodeInfo & OPFL_VariadicInfo) { 2386 // Determine the start index to copy from. 2387 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2388 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2389 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2390 "Invalid variadic node"); 2391 // Copy all of the variadic operands, not including a potential flag 2392 // input. 2393 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2394 i != e; ++i) { 2395 SDValue V = NodeToMatch->getOperand(i); 2396 if (V.getValueType() == MVT::Flag) break; 2397 Ops.push_back(V); 2398 } 2399 } 2400 2401 // If this has chain/flag inputs, add them. 2402 if (EmitNodeInfo & OPFL_Chain) 2403 Ops.push_back(InputChain); 2404 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2405 Ops.push_back(InputFlag); 2406 2407 // Create the node. 2408 SDNode *Res = 0; 2409 if (Opcode != OPC_MorphNodeTo) { 2410 // If this is a normal EmitNode command, just create the new node and 2411 // add the results to the RecordedNodes list. 2412 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2413 VTList, Ops.data(), Ops.size()); 2414 2415 // Add all the non-flag/non-chain results to the RecordedNodes list. 2416 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2417 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2418 RecordedNodes.push_back(SDValue(Res, i)); 2419 } 2420 2421 } else { 2422 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2423 EmitNodeInfo); 2424 } 2425 2426 // If the node had chain/flag results, update our notion of the current 2427 // chain and flag. 2428 if (EmitNodeInfo & OPFL_FlagOutput) { 2429 InputFlag = SDValue(Res, VTs.size()-1); 2430 if (EmitNodeInfo & OPFL_Chain) 2431 InputChain = SDValue(Res, VTs.size()-2); 2432 } else if (EmitNodeInfo & OPFL_Chain) 2433 InputChain = SDValue(Res, VTs.size()-1); 2434 2435 // If the OPFL_MemRefs flag is set on this node, slap all of the 2436 // accumulated memrefs onto it. 2437 // 2438 // FIXME: This is vastly incorrect for patterns with multiple outputs 2439 // instructions that access memory and for ComplexPatterns that match 2440 // loads. 2441 if (EmitNodeInfo & OPFL_MemRefs) { 2442 MachineSDNode::mmo_iterator MemRefs = 2443 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2444 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2445 cast<MachineSDNode>(Res) 2446 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2447 } 2448 2449 DEBUG(errs() << " " 2450 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2451 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2452 2453 // If this was a MorphNodeTo then we're completely done! 2454 if (Opcode == OPC_MorphNodeTo) { 2455 // Update chain and flag uses. 2456 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2457 InputFlag, FlagResultNodesMatched, true); 2458 return Res; 2459 } 2460 2461 continue; 2462 } 2463 2464 case OPC_MarkFlagResults: { 2465 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2466 2467 // Read and remember all the flag-result nodes. 2468 for (unsigned i = 0; i != NumNodes; ++i) { 2469 unsigned RecNo = MatcherTable[MatcherIndex++]; 2470 if (RecNo & 128) 2471 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2472 2473 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2474 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2475 } 2476 continue; 2477 } 2478 2479 case OPC_CompleteMatch: { 2480 // The match has been completed, and any new nodes (if any) have been 2481 // created. Patch up references to the matched dag to use the newly 2482 // created nodes. 2483 unsigned NumResults = MatcherTable[MatcherIndex++]; 2484 2485 for (unsigned i = 0; i != NumResults; ++i) { 2486 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2487 if (ResSlot & 128) 2488 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2489 2490 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2491 SDValue Res = RecordedNodes[ResSlot]; 2492 2493 assert(i < NodeToMatch->getNumValues() && 2494 NodeToMatch->getValueType(i) != MVT::Other && 2495 NodeToMatch->getValueType(i) != MVT::Flag && 2496 "Invalid number of results to complete!"); 2497 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2498 NodeToMatch->getValueType(i) == MVT::iPTR || 2499 Res.getValueType() == MVT::iPTR || 2500 NodeToMatch->getValueType(i).getSizeInBits() == 2501 Res.getValueType().getSizeInBits()) && 2502 "invalid replacement"); 2503 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2504 } 2505 2506 // If the root node defines a flag, add it to the flag nodes to update 2507 // list. 2508 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2509 FlagResultNodesMatched.push_back(NodeToMatch); 2510 2511 // Update chain and flag uses. 2512 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2513 InputFlag, FlagResultNodesMatched, false); 2514 2515 assert(NodeToMatch->use_empty() && 2516 "Didn't replace all uses of the node?"); 2517 2518 // FIXME: We just return here, which interacts correctly with SelectRoot 2519 // above. We should fix this to not return an SDNode* anymore. 2520 return 0; 2521 } 2522 } 2523 2524 // If the code reached this point, then the match failed. See if there is 2525 // another child to try in the current 'Scope', otherwise pop it until we 2526 // find a case to check. 2527 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2528 ++NumDAGIselRetries; 2529 while (1) { 2530 if (MatchScopes.empty()) { 2531 CannotYetSelect(NodeToMatch); 2532 return 0; 2533 } 2534 2535 // Restore the interpreter state back to the point where the scope was 2536 // formed. 2537 MatchScope &LastScope = MatchScopes.back(); 2538 RecordedNodes.resize(LastScope.NumRecordedNodes); 2539 NodeStack.clear(); 2540 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2541 N = NodeStack.back(); 2542 2543 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2544 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2545 MatcherIndex = LastScope.FailIndex; 2546 2547 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2548 2549 InputChain = LastScope.InputChain; 2550 InputFlag = LastScope.InputFlag; 2551 if (!LastScope.HasChainNodesMatched) 2552 ChainNodesMatched.clear(); 2553 if (!LastScope.HasFlagResultNodesMatched) 2554 FlagResultNodesMatched.clear(); 2555 2556 // Check to see what the offset is at the new MatcherIndex. If it is zero 2557 // we have reached the end of this scope, otherwise we have another child 2558 // in the current scope to try. 2559 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2560 if (NumToSkip & 128) 2561 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2562 2563 // If we have another child in this scope to match, update FailIndex and 2564 // try it. 2565 if (NumToSkip != 0) { 2566 LastScope.FailIndex = MatcherIndex+NumToSkip; 2567 break; 2568 } 2569 2570 // End of this scope, pop it and try the next child in the containing 2571 // scope. 2572 MatchScopes.pop_back(); 2573 } 2574 } 2575} 2576 2577 2578 2579void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2580 std::string msg; 2581 raw_string_ostream Msg(msg); 2582 Msg << "Cannot yet select: "; 2583 2584 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2585 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2586 N->getOpcode() != ISD::INTRINSIC_VOID) { 2587 N->printrFull(Msg, CurDAG); 2588 } else { 2589 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2590 unsigned iid = 2591 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2592 if (iid < Intrinsic::num_intrinsics) 2593 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2594 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2595 Msg << "target intrinsic %" << TII->getName(iid); 2596 else 2597 Msg << "unknown intrinsic #" << iid; 2598 } 2599 report_fatal_error(Msg.str()); 2600} 2601 2602char SelectionDAGISel::ID = 0; 2603