SelectionDAGISel.cpp revision c66764c00756d800aede2fd32d55658a236b1912
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
15#include "llvm/CodeGen/SelectionDAGISel.h"
16#include "llvm/CodeGen/ScheduleDAG.h"
17#include "llvm/CallingConv.h"
18#include "llvm/Constants.h"
19#include "llvm/DerivedTypes.h"
20#include "llvm/Function.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/InlineAsm.h"
23#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/IntrinsicInst.h"
26#include "llvm/CodeGen/IntrinsicLowering.h"
27#include "llvm/CodeGen/MachineDebugInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineJumpTableInfo.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/SchedulerRegistry.h"
33#include "llvm/CodeGen/SelectionDAG.h"
34#include "llvm/CodeGen/SSARegMap.h"
35#include "llvm/Target/MRegisterInfo.h"
36#include "llvm/Target/TargetData.h"
37#include "llvm/Target/TargetFrameInfo.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetLowering.h"
40#include "llvm/Target/TargetMachine.h"
41#include "llvm/Target/TargetOptions.h"
42#include "llvm/Transforms/Utils/BasicBlockUtils.h"
43#include "llvm/Support/MathExtras.h"
44#include "llvm/Support/Debug.h"
45#include "llvm/Support/Compiler.h"
46#include <map>
47#include <set>
48#include <iostream>
49#include <algorithm>
50using namespace llvm;
51
52#ifndef NDEBUG
53static cl::opt<bool>
54ViewISelDAGs("view-isel-dags", cl::Hidden,
55          cl::desc("Pop up a window to show isel dags as they are selected"));
56static cl::opt<bool>
57ViewSchedDAGs("view-sched-dags", cl::Hidden,
58          cl::desc("Pop up a window to show sched dags as they are processed"));
59#else
60static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
61#endif
62
63
64//===---------------------------------------------------------------------===//
65///
66/// RegisterScheduler class - Track the registration of instruction schedulers.
67///
68//===---------------------------------------------------------------------===//
69MachinePassRegistry RegisterScheduler::Registry;
70
71//===---------------------------------------------------------------------===//
72///
73/// ISHeuristic command line option for instruction schedulers.
74///
75//===---------------------------------------------------------------------===//
76namespace {
77  cl::opt<RegisterScheduler::FunctionPassCtor, false,
78          RegisterPassParser<RegisterScheduler> >
79  ISHeuristic("sched",
80              cl::init(&createDefaultScheduler),
81              cl::desc("Instruction schedulers available:"));
82
83  static RegisterScheduler
84  defaultListDAGScheduler("default", "  Best scheduler for the target",
85                          createDefaultScheduler);
86} // namespace
87
88namespace {
89  /// RegsForValue - This struct represents the physical registers that a
90  /// particular value is assigned and the type information about the value.
91  /// This is needed because values can be promoted into larger registers and
92  /// expanded into multiple smaller registers than the value.
93  struct VISIBILITY_HIDDEN RegsForValue {
94    /// Regs - This list hold the register (for legal and promoted values)
95    /// or register set (for expanded values) that the value should be assigned
96    /// to.
97    std::vector<unsigned> Regs;
98
99    /// RegVT - The value type of each register.
100    ///
101    MVT::ValueType RegVT;
102
103    /// ValueVT - The value type of the LLVM value, which may be promoted from
104    /// RegVT or made from merging the two expanded parts.
105    MVT::ValueType ValueVT;
106
107    RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
108
109    RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
110      : RegVT(regvt), ValueVT(valuevt) {
111        Regs.push_back(Reg);
112    }
113    RegsForValue(const std::vector<unsigned> &regs,
114                 MVT::ValueType regvt, MVT::ValueType valuevt)
115      : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
116    }
117
118    /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
119    /// this value and returns the result as a ValueVT value.  This uses
120    /// Chain/Flag as the input and updates them for the output Chain/Flag.
121    SDOperand getCopyFromRegs(SelectionDAG &DAG,
122                              SDOperand &Chain, SDOperand &Flag) const;
123
124    /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125    /// specified value into the registers specified by this object.  This uses
126    /// Chain/Flag as the input and updates them for the output Chain/Flag.
127    void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
128                       SDOperand &Chain, SDOperand &Flag,
129                       MVT::ValueType PtrVT) const;
130
131    /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132    /// operand list.  This adds the code marker and includes the number of
133    /// values added into it.
134    void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
135                              std::vector<SDOperand> &Ops) const;
136  };
137}
138
139namespace llvm {
140  //===--------------------------------------------------------------------===//
141  /// createDefaultScheduler - This creates an instruction scheduler appropriate
142  /// for the target.
143  ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
144                                      SelectionDAG *DAG,
145                                      MachineBasicBlock *BB) {
146    TargetLowering &TLI = IS->getTargetLowering();
147
148    if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149      return createTDListDAGScheduler(IS, DAG, BB);
150    } else {
151      assert(TLI.getSchedulingPreference() ==
152           TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153      return createBURRListDAGScheduler(IS, DAG, BB);
154    }
155  }
156
157
158  //===--------------------------------------------------------------------===//
159  /// FunctionLoweringInfo - This contains information that is global to a
160  /// function that is used when lowering a region of the function.
161  class FunctionLoweringInfo {
162  public:
163    TargetLowering &TLI;
164    Function &Fn;
165    MachineFunction &MF;
166    SSARegMap *RegMap;
167
168    FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
169
170    /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171    std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
172
173    /// ValueMap - Since we emit code for the function a basic block at a time,
174    /// we must remember which virtual registers hold the values for
175    /// cross-basic-block values.
176    std::map<const Value*, unsigned> ValueMap;
177
178    /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179    /// the entry block.  This allows the allocas to be efficiently referenced
180    /// anywhere in the function.
181    std::map<const AllocaInst*, int> StaticAllocaMap;
182
183    unsigned MakeReg(MVT::ValueType VT) {
184      return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
185    }
186
187    unsigned CreateRegForValue(const Value *V);
188
189    unsigned InitializeRegForValue(const Value *V) {
190      unsigned &R = ValueMap[V];
191      assert(R == 0 && "Already initialized this value register!");
192      return R = CreateRegForValue(V);
193    }
194  };
195}
196
197/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
198/// PHI nodes or outside of the basic block that defines it, or used by a
199/// switch instruction, which may expand to multiple basic blocks.
200static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
201  if (isa<PHINode>(I)) return true;
202  BasicBlock *BB = I->getParent();
203  for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
204    if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
205        isa<SwitchInst>(*UI))
206      return true;
207  return false;
208}
209
210/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
211/// entry block, return true.  This includes arguments used by switches, since
212/// the switch may expand into multiple basic blocks.
213static bool isOnlyUsedInEntryBlock(Argument *A) {
214  BasicBlock *Entry = A->getParent()->begin();
215  for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
216    if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
217      return false;  // Use not in entry block.
218  return true;
219}
220
221FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
222                                           Function &fn, MachineFunction &mf)
223    : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
224
225  // Create a vreg for each argument register that is not dead and is used
226  // outside of the entry block for the function.
227  for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
228       AI != E; ++AI)
229    if (!isOnlyUsedInEntryBlock(AI))
230      InitializeRegForValue(AI);
231
232  // Initialize the mapping of values to registers.  This is only set up for
233  // instruction values that are used outside of the block that defines
234  // them.
235  Function::iterator BB = Fn.begin(), EB = Fn.end();
236  for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
237    if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
238      if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
239        const Type *Ty = AI->getAllocatedType();
240        uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
241        unsigned Align =
242          std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
243                   AI->getAlignment());
244
245        // If the alignment of the value is smaller than the size of the value,
246        // and if the size of the value is particularly small (<= 8 bytes),
247        // round up to the size of the value for potentially better performance.
248        //
249        // FIXME: This could be made better with a preferred alignment hook in
250        // TargetData.  It serves primarily to 8-byte align doubles for X86.
251        if (Align < TySize && TySize <= 8) Align = TySize;
252        TySize *= CUI->getValue();   // Get total allocated size.
253        if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
254        StaticAllocaMap[AI] =
255          MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
256      }
257
258  for (; BB != EB; ++BB)
259    for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
260      if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
261        if (!isa<AllocaInst>(I) ||
262            !StaticAllocaMap.count(cast<AllocaInst>(I)))
263          InitializeRegForValue(I);
264
265  // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
266  // also creates the initial PHI MachineInstrs, though none of the input
267  // operands are populated.
268  for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
269    MachineBasicBlock *MBB = new MachineBasicBlock(BB);
270    MBBMap[BB] = MBB;
271    MF.getBasicBlockList().push_back(MBB);
272
273    // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
274    // appropriate.
275    PHINode *PN;
276    for (BasicBlock::iterator I = BB->begin();
277         (PN = dyn_cast<PHINode>(I)); ++I)
278      if (!PN->use_empty()) {
279        MVT::ValueType VT = TLI.getValueType(PN->getType());
280        unsigned NumElements;
281        if (VT != MVT::Vector)
282          NumElements = TLI.getNumElements(VT);
283        else {
284          MVT::ValueType VT1,VT2;
285          NumElements =
286            TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
287                                       VT1, VT2);
288        }
289        unsigned PHIReg = ValueMap[PN];
290        assert(PHIReg &&"PHI node does not have an assigned virtual register!");
291        for (unsigned i = 0; i != NumElements; ++i)
292          BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
293      }
294  }
295}
296
297/// CreateRegForValue - Allocate the appropriate number of virtual registers of
298/// the correctly promoted or expanded types.  Assign these registers
299/// consecutive vreg numbers and return the first assigned number.
300unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
301  MVT::ValueType VT = TLI.getValueType(V->getType());
302
303  // The number of multiples of registers that we need, to, e.g., split up
304  // a <2 x int64> -> 4 x i32 registers.
305  unsigned NumVectorRegs = 1;
306
307  // If this is a packed type, figure out what type it will decompose into
308  // and how many of the elements it will use.
309  if (VT == MVT::Vector) {
310    const PackedType *PTy = cast<PackedType>(V->getType());
311    unsigned NumElts = PTy->getNumElements();
312    MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
313
314    // Divide the input until we get to a supported size.  This will always
315    // end with a scalar if the target doesn't support vectors.
316    while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
317      NumElts >>= 1;
318      NumVectorRegs <<= 1;
319    }
320    if (NumElts == 1)
321      VT = EltTy;
322    else
323      VT = getVectorType(EltTy, NumElts);
324  }
325
326  // The common case is that we will only create one register for this
327  // value.  If we have that case, create and return the virtual register.
328  unsigned NV = TLI.getNumElements(VT);
329  if (NV == 1) {
330    // If we are promoting this value, pick the next largest supported type.
331    MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
332    unsigned Reg = MakeReg(PromotedType);
333    // If this is a vector of supported or promoted types (e.g. 4 x i16),
334    // create all of the registers.
335    for (unsigned i = 1; i != NumVectorRegs; ++i)
336      MakeReg(PromotedType);
337    return Reg;
338  }
339
340  // If this value is represented with multiple target registers, make sure
341  // to create enough consecutive registers of the right (smaller) type.
342  unsigned NT = VT-1;  // Find the type to use.
343  while (TLI.getNumElements((MVT::ValueType)NT) != 1)
344    --NT;
345
346  unsigned R = MakeReg((MVT::ValueType)NT);
347  for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348    MakeReg((MVT::ValueType)NT);
349  return R;
350}
351
352//===----------------------------------------------------------------------===//
353/// SelectionDAGLowering - This is the common target-independent lowering
354/// implementation that is parameterized by a TargetLowering object.
355/// Also, targets can overload any lowering method.
356///
357namespace llvm {
358class SelectionDAGLowering {
359  MachineBasicBlock *CurMBB;
360
361  std::map<const Value*, SDOperand> NodeMap;
362
363  /// PendingLoads - Loads are not emitted to the program immediately.  We bunch
364  /// them up and then emit token factor nodes when possible.  This allows us to
365  /// get simple disambiguation between loads without worrying about alias
366  /// analysis.
367  std::vector<SDOperand> PendingLoads;
368
369  /// Case - A pair of values to record the Value for a switch case, and the
370  /// case's target basic block.
371  typedef std::pair<Constant*, MachineBasicBlock*> Case;
372  typedef std::vector<Case>::iterator              CaseItr;
373  typedef std::pair<CaseItr, CaseItr>              CaseRange;
374
375  /// CaseRec - A struct with ctor used in lowering switches to a binary tree
376  /// of conditional branches.
377  struct CaseRec {
378    CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
379    CaseBB(bb), LT(lt), GE(ge), Range(r) {}
380
381    /// CaseBB - The MBB in which to emit the compare and branch
382    MachineBasicBlock *CaseBB;
383    /// LT, GE - If nonzero, we know the current case value must be less-than or
384    /// greater-than-or-equal-to these Constants.
385    Constant *LT;
386    Constant *GE;
387    /// Range - A pair of iterators representing the range of case values to be
388    /// processed at this point in the binary search tree.
389    CaseRange Range;
390  };
391
392  /// The comparison function for sorting Case values.
393  struct CaseCmp {
394    bool operator () (const Case& C1, const Case& C2) {
395      if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
396        return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
397
398      const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
399      return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
400    }
401  };
402
403public:
404  // TLI - This is information that describes the available target features we
405  // need for lowering.  This indicates when operations are unavailable,
406  // implemented with a libcall, etc.
407  TargetLowering &TLI;
408  SelectionDAG &DAG;
409  const TargetData *TD;
410
411  /// SwitchCases - Vector of CaseBlock structures used to communicate
412  /// SwitchInst code generation information.
413  std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
414  SelectionDAGISel::JumpTable JT;
415
416  /// FuncInfo - Information about the function as a whole.
417  ///
418  FunctionLoweringInfo &FuncInfo;
419
420  SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
421                       FunctionLoweringInfo &funcinfo)
422    : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
423      JT(0,0,0,0), FuncInfo(funcinfo) {
424  }
425
426  /// getRoot - Return the current virtual root of the Selection DAG.
427  ///
428  SDOperand getRoot() {
429    if (PendingLoads.empty())
430      return DAG.getRoot();
431
432    if (PendingLoads.size() == 1) {
433      SDOperand Root = PendingLoads[0];
434      DAG.setRoot(Root);
435      PendingLoads.clear();
436      return Root;
437    }
438
439    // Otherwise, we have to make a token factor node.
440    SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
441                                 &PendingLoads[0], PendingLoads.size());
442    PendingLoads.clear();
443    DAG.setRoot(Root);
444    return Root;
445  }
446
447  void visit(Instruction &I) { visit(I.getOpcode(), I); }
448
449  void visit(unsigned Opcode, User &I) {
450    switch (Opcode) {
451    default: assert(0 && "Unknown instruction type encountered!");
452             abort();
453      // Build the switch statement using the Instruction.def file.
454#define HANDLE_INST(NUM, OPCODE, CLASS) \
455    case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
456#include "llvm/Instruction.def"
457    }
458  }
459
460  void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
461
462  SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
463                        SDOperand SrcValue, SDOperand Root,
464                        bool isVolatile);
465
466  SDOperand getIntPtrConstant(uint64_t Val) {
467    return DAG.getConstant(Val, TLI.getPointerTy());
468  }
469
470  SDOperand getValue(const Value *V);
471
472  const SDOperand &setValue(const Value *V, SDOperand NewN) {
473    SDOperand &N = NodeMap[V];
474    assert(N.Val == 0 && "Already set a value for this node!");
475    return N = NewN;
476  }
477
478  RegsForValue GetRegistersForValue(const std::string &ConstrCode,
479                                    MVT::ValueType VT,
480                                    bool OutReg, bool InReg,
481                                    std::set<unsigned> &OutputRegs,
482                                    std::set<unsigned> &InputRegs);
483
484  // Terminator instructions.
485  void visitRet(ReturnInst &I);
486  void visitBr(BranchInst &I);
487  void visitSwitch(SwitchInst &I);
488  void visitUnreachable(UnreachableInst &I) { /* noop */ }
489
490  // Helper for visitSwitch
491  void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
492  void visitJumpTable(SelectionDAGISel::JumpTable &JT);
493
494  // These all get lowered before this pass.
495  void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
496  void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
497
498  void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
499  void visitShift(User &I, unsigned Opcode);
500  void visitAdd(User &I) {
501    visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
502  }
503  void visitSub(User &I);
504  void visitMul(User &I) {
505    visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
506  }
507  void visitDiv(User &I) {
508    const Type *Ty = I.getType();
509    visitBinary(I,
510                Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
511                Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
512  }
513  void visitRem(User &I) {
514    const Type *Ty = I.getType();
515    visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
516  }
517  void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
518  void visitOr (User &I) { visitBinary(I, ISD::OR,  0, ISD::VOR); }
519  void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
520  void visitShl(User &I) { visitShift(I, ISD::SHL); }
521  void visitShr(User &I) {
522    visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
523  }
524
525  void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
526                  ISD::CondCode FPOpc);
527  void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
528                                        ISD::SETOEQ); }
529  void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
530                                        ISD::SETUNE); }
531  void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
532                                        ISD::SETOLE); }
533  void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
534                                        ISD::SETOGE); }
535  void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
536                                        ISD::SETOLT); }
537  void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
538                                        ISD::SETOGT); }
539
540  void visitExtractElement(User &I);
541  void visitInsertElement(User &I);
542  void visitShuffleVector(User &I);
543
544  void visitGetElementPtr(User &I);
545  void visitCast(User &I);
546  void visitSelect(User &I);
547
548  void visitMalloc(MallocInst &I);
549  void visitFree(FreeInst &I);
550  void visitAlloca(AllocaInst &I);
551  void visitLoad(LoadInst &I);
552  void visitStore(StoreInst &I);
553  void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
554  void visitCall(CallInst &I);
555  void visitInlineAsm(CallInst &I);
556  const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
557  void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
558
559  void visitVAStart(CallInst &I);
560  void visitVAArg(VAArgInst &I);
561  void visitVAEnd(CallInst &I);
562  void visitVACopy(CallInst &I);
563  void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
564
565  void visitMemIntrinsic(CallInst &I, unsigned Op);
566
567  void visitUserOp1(Instruction &I) {
568    assert(0 && "UserOp1 should not exist at instruction selection time!");
569    abort();
570  }
571  void visitUserOp2(Instruction &I) {
572    assert(0 && "UserOp2 should not exist at instruction selection time!");
573    abort();
574  }
575};
576} // end namespace llvm
577
578SDOperand SelectionDAGLowering::getValue(const Value *V) {
579  SDOperand &N = NodeMap[V];
580  if (N.Val) return N;
581
582  const Type *VTy = V->getType();
583  MVT::ValueType VT = TLI.getValueType(VTy);
584  if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
585    if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
586      visit(CE->getOpcode(), *CE);
587      assert(N.Val && "visit didn't populate the ValueMap!");
588      return N;
589    } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
590      return N = DAG.getGlobalAddress(GV, VT);
591    } else if (isa<ConstantPointerNull>(C)) {
592      return N = DAG.getConstant(0, TLI.getPointerTy());
593    } else if (isa<UndefValue>(C)) {
594      if (!isa<PackedType>(VTy))
595        return N = DAG.getNode(ISD::UNDEF, VT);
596
597      // Create a VBUILD_VECTOR of undef nodes.
598      const PackedType *PTy = cast<PackedType>(VTy);
599      unsigned NumElements = PTy->getNumElements();
600      MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
601
602      SmallVector<SDOperand, 8> Ops;
603      Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
604
605      // Create a VConstant node with generic Vector type.
606      Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
607      Ops.push_back(DAG.getValueType(PVT));
608      return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
609                             &Ops[0], Ops.size());
610    } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
611      return N = DAG.getConstantFP(CFP->getValue(), VT);
612    } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
613      unsigned NumElements = PTy->getNumElements();
614      MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
615
616      // Now that we know the number and type of the elements, push a
617      // Constant or ConstantFP node onto the ops list for each element of
618      // the packed constant.
619      SmallVector<SDOperand, 8> Ops;
620      if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
621        for (unsigned i = 0; i != NumElements; ++i)
622          Ops.push_back(getValue(CP->getOperand(i)));
623      } else {
624        assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
625        SDOperand Op;
626        if (MVT::isFloatingPoint(PVT))
627          Op = DAG.getConstantFP(0, PVT);
628        else
629          Op = DAG.getConstant(0, PVT);
630        Ops.assign(NumElements, Op);
631      }
632
633      // Create a VBUILD_VECTOR node with generic Vector type.
634      Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
635      Ops.push_back(DAG.getValueType(PVT));
636      return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
637    } else {
638      // Canonicalize all constant ints to be unsigned.
639      return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
640    }
641  }
642
643  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
644    std::map<const AllocaInst*, int>::iterator SI =
645    FuncInfo.StaticAllocaMap.find(AI);
646    if (SI != FuncInfo.StaticAllocaMap.end())
647      return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
648  }
649
650  std::map<const Value*, unsigned>::const_iterator VMI =
651      FuncInfo.ValueMap.find(V);
652  assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
653
654  unsigned InReg = VMI->second;
655
656  // If this type is not legal, make it so now.
657  if (VT != MVT::Vector) {
658    MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
659
660    N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
661    if (DestVT < VT) {
662      // Source must be expanded.  This input value is actually coming from the
663      // register pair VMI->second and VMI->second+1.
664      N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
665                      DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
666    } else if (DestVT > VT) { // Promotion case
667      if (MVT::isFloatingPoint(VT))
668        N = DAG.getNode(ISD::FP_ROUND, VT, N);
669      else
670        N = DAG.getNode(ISD::TRUNCATE, VT, N);
671    }
672  } else {
673    // Otherwise, if this is a vector, make it available as a generic vector
674    // here.
675    MVT::ValueType PTyElementVT, PTyLegalElementVT;
676    const PackedType *PTy = cast<PackedType>(VTy);
677    unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
678                                             PTyLegalElementVT);
679
680    // Build a VBUILD_VECTOR with the input registers.
681    SmallVector<SDOperand, 8> Ops;
682    if (PTyElementVT == PTyLegalElementVT) {
683      // If the value types are legal, just VBUILD the CopyFromReg nodes.
684      for (unsigned i = 0; i != NE; ++i)
685        Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
686                                         PTyElementVT));
687    } else if (PTyElementVT < PTyLegalElementVT) {
688      // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
689      for (unsigned i = 0; i != NE; ++i) {
690        SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
691                                          PTyElementVT);
692        if (MVT::isFloatingPoint(PTyElementVT))
693          Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
694        else
695          Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
696        Ops.push_back(Op);
697      }
698    } else {
699      // If the register was expanded, use BUILD_PAIR.
700      assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
701      for (unsigned i = 0; i != NE/2; ++i) {
702        SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
703                                           PTyElementVT);
704        SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
705                                           PTyElementVT);
706        Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
707      }
708    }
709
710    Ops.push_back(DAG.getConstant(NE, MVT::i32));
711    Ops.push_back(DAG.getValueType(PTyLegalElementVT));
712    N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
713
714    // Finally, use a VBIT_CONVERT to make this available as the appropriate
715    // vector type.
716    N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
717                    DAG.getConstant(PTy->getNumElements(),
718                                    MVT::i32),
719                    DAG.getValueType(TLI.getValueType(PTy->getElementType())));
720  }
721
722  return N;
723}
724
725
726void SelectionDAGLowering::visitRet(ReturnInst &I) {
727  if (I.getNumOperands() == 0) {
728    DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
729    return;
730  }
731  SmallVector<SDOperand, 8> NewValues;
732  NewValues.push_back(getRoot());
733  for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
734    SDOperand RetOp = getValue(I.getOperand(i));
735    bool isSigned = I.getOperand(i)->getType()->isSigned();
736
737    // If this is an integer return value, we need to promote it ourselves to
738    // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
739    // than sign/zero.
740    // FIXME: C calling convention requires the return type to be promoted to
741    // at least 32-bit. But this is not necessary for non-C calling conventions.
742    if (MVT::isInteger(RetOp.getValueType()) &&
743        RetOp.getValueType() < MVT::i64) {
744      MVT::ValueType TmpVT;
745      if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
746        TmpVT = TLI.getTypeToTransformTo(MVT::i32);
747      else
748        TmpVT = MVT::i32;
749
750      if (isSigned)
751        RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
752      else
753        RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
754    }
755    NewValues.push_back(RetOp);
756    NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
757  }
758  DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
759                          &NewValues[0], NewValues.size()));
760}
761
762void SelectionDAGLowering::visitBr(BranchInst &I) {
763  // Update machine-CFG edges.
764  MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
765  CurMBB->addSuccessor(Succ0MBB);
766
767  // Figure out which block is immediately after the current one.
768  MachineBasicBlock *NextBlock = 0;
769  MachineFunction::iterator BBI = CurMBB;
770  if (++BBI != CurMBB->getParent()->end())
771    NextBlock = BBI;
772
773  if (I.isUnconditional()) {
774    // If this is not a fall-through branch, emit the branch.
775    if (Succ0MBB != NextBlock)
776      DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
777                              DAG.getBasicBlock(Succ0MBB)));
778  } else {
779    MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
780    CurMBB->addSuccessor(Succ1MBB);
781
782    SDOperand Cond = getValue(I.getCondition());
783    if (Succ1MBB == NextBlock) {
784      // If the condition is false, fall through.  This means we should branch
785      // if the condition is true to Succ #0.
786      DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
787                              Cond, DAG.getBasicBlock(Succ0MBB)));
788    } else if (Succ0MBB == NextBlock) {
789      // If the condition is true, fall through.  This means we should branch if
790      // the condition is false to Succ #1.  Invert the condition first.
791      SDOperand True = DAG.getConstant(1, Cond.getValueType());
792      Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
793      DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
794                              Cond, DAG.getBasicBlock(Succ1MBB)));
795    } else {
796      std::vector<SDOperand> Ops;
797      Ops.push_back(getRoot());
798      // If the false case is the current basic block, then this is a self
799      // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
800      // adds an extra instruction in the loop.  Instead, invert the
801      // condition and emit "Loop: ... br!cond Loop; br Out.
802      if (CurMBB == Succ1MBB) {
803        std::swap(Succ0MBB, Succ1MBB);
804        SDOperand True = DAG.getConstant(1, Cond.getValueType());
805        Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
806      }
807      SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
808                                   DAG.getBasicBlock(Succ0MBB));
809      DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
810                              DAG.getBasicBlock(Succ1MBB)));
811    }
812  }
813}
814
815/// visitSwitchCase - Emits the necessary code to represent a single node in
816/// the binary search tree resulting from lowering a switch instruction.
817void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
818  SDOperand SwitchOp = getValue(CB.SwitchV);
819  SDOperand CaseOp = getValue(CB.CaseC);
820  SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
821
822  // Set NextBlock to be the MBB immediately after the current one, if any.
823  // This is used to avoid emitting unnecessary branches to the next block.
824  MachineBasicBlock *NextBlock = 0;
825  MachineFunction::iterator BBI = CurMBB;
826  if (++BBI != CurMBB->getParent()->end())
827    NextBlock = BBI;
828
829  // If the lhs block is the next block, invert the condition so that we can
830  // fall through to the lhs instead of the rhs block.
831  if (CB.LHSBB == NextBlock) {
832    std::swap(CB.LHSBB, CB.RHSBB);
833    SDOperand True = DAG.getConstant(1, Cond.getValueType());
834    Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
835  }
836  SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
837                                 DAG.getBasicBlock(CB.LHSBB));
838  if (CB.RHSBB == NextBlock)
839    DAG.setRoot(BrCond);
840  else
841    DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
842                            DAG.getBasicBlock(CB.RHSBB)));
843  // Update successor info
844  CurMBB->addSuccessor(CB.LHSBB);
845  CurMBB->addSuccessor(CB.RHSBB);
846}
847
848/// visitSwitchCase - Emits the necessary code to represent a single node in
849/// the binary search tree resulting from lowering a switch instruction.
850void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
851  // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
852  // we need to add the address of the jump table to the value loaded, since
853  // the entries in the jump table will be differences rather than absolute
854  // addresses.
855
856  // Emit the code for the jump table
857  MVT::ValueType PTy = TLI.getPointerTy();
858  assert((PTy == MVT::i32 || PTy == MVT::i64) &&
859         "Jump table entries are 32-bit values");
860  // PIC jump table entries are 32-bit values.
861  unsigned EntrySize =
862    (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_)
863    ? 4 : MVT::getSizeInBits(PTy)/8;
864  SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
865  SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
866                              DAG.getConstant(EntrySize, PTy));
867  SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
868  SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
869  SDOperand LD  = DAG.getLoad(MVT::i32, Copy.getValue(1), ADD,
870                              DAG.getSrcValue(0));
871  if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
872    ADD = DAG.getNode(ISD::ADD, PTy,
873        ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), TAB);
874    DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
875  } else {
876    DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
877  }
878}
879
880void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
881  // Figure out which block is immediately after the current one.
882  MachineBasicBlock *NextBlock = 0;
883  MachineFunction::iterator BBI = CurMBB;
884  if (++BBI != CurMBB->getParent()->end())
885    NextBlock = BBI;
886
887  // If there is only the default destination, branch to it if it is not the
888  // next basic block.  Otherwise, just fall through.
889  if (I.getNumOperands() == 2) {
890    // Update machine-CFG edges.
891    MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
892    // If this is not a fall-through branch, emit the branch.
893    if (DefaultMBB != NextBlock)
894      DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
895                              DAG.getBasicBlock(DefaultMBB)));
896    CurMBB->addSuccessor(DefaultMBB);
897    return;
898  }
899
900  // If there are any non-default case statements, create a vector of Cases
901  // representing each one, and sort the vector so that we can efficiently
902  // create a binary search tree from them.
903  std::vector<Case> Cases;
904  for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
905    MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
906    Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
907  }
908  std::sort(Cases.begin(), Cases.end(), CaseCmp());
909
910  // Get the Value to be switched on and default basic blocks, which will be
911  // inserted into CaseBlock records, representing basic blocks in the binary
912  // search tree.
913  Value *SV = I.getOperand(0);
914  MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
915
916  // Get the MachineFunction which holds the current MBB.  This is used during
917  // emission of jump tables, and when inserting any additional MBBs necessary
918  // to represent the switch.
919  MachineFunction *CurMF = CurMBB->getParent();
920  const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
921
922  // If the switch has more than 5 blocks, and at least 31.25% dense, and the
923  // target supports indirect branches, then emit a jump table rather than
924  // lowering the switch to a binary tree of conditional branches.
925  if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
926      Cases.size() > 5) {
927    uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
928    uint64_t Last  = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
929    double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
930
931    if (Density >= 0.3125) {
932      // Create a new basic block to hold the code for loading the address
933      // of the jump table, and jumping to it.  Update successor information;
934      // we will either branch to the default case for the switch, or the jump
935      // table.
936      MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
937      CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
938      CurMBB->addSuccessor(Default);
939      CurMBB->addSuccessor(JumpTableBB);
940
941      // Subtract the lowest switch case value from the value being switched on
942      // and conditional branch to default mbb if the result is greater than the
943      // difference between smallest and largest cases.
944      SDOperand SwitchOp = getValue(SV);
945      MVT::ValueType VT = SwitchOp.getValueType();
946      SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
947                                  DAG.getConstant(First, VT));
948
949      // The SDNode we just created, which holds the value being switched on
950      // minus the the smallest case value, needs to be copied to a virtual
951      // register so it can be used as an index into the jump table in a
952      // subsequent basic block.  This value may be smaller or larger than the
953      // target's pointer type, and therefore require extension or truncating.
954      if (VT > TLI.getPointerTy())
955        SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
956      else
957        SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
958      unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
959      SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
960
961      // Emit the range check for the jump table, and branch to the default
962      // block for the switch statement if the value being switched on exceeds
963      // the largest case in the switch.
964      SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
965                                   DAG.getConstant(Last-First,VT), ISD::SETUGT);
966      DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
967                              DAG.getBasicBlock(Default)));
968
969      // Build a vector of destination BBs, corresponding to each target
970      // of the jump table.  If the value of the jump table slot corresponds to
971      // a case statement, push the case's BB onto the vector, otherwise, push
972      // the default BB.
973      std::vector<MachineBasicBlock*> DestBBs;
974      uint64_t TEI = First;
975      for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
976        if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
977          DestBBs.push_back(ii->second);
978          ++ii;
979        } else {
980          DestBBs.push_back(Default);
981        }
982      }
983
984      // Update successor info
985      for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
986           E = DestBBs.end(); I != E; ++I)
987        JumpTableBB->addSuccessor(*I);
988
989      // Create a jump table index for this jump table, or return an existing
990      // one.
991      unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
992
993      // Set the jump table information so that we can codegen it as a second
994      // MachineBasicBlock
995      JT.Reg = JumpTableReg;
996      JT.JTI = JTI;
997      JT.MBB = JumpTableBB;
998      JT.Default = Default;
999      return;
1000    }
1001  }
1002
1003  // Push the initial CaseRec onto the worklist
1004  std::vector<CaseRec> CaseVec;
1005  CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1006
1007  while (!CaseVec.empty()) {
1008    // Grab a record representing a case range to process off the worklist
1009    CaseRec CR = CaseVec.back();
1010    CaseVec.pop_back();
1011
1012    // Size is the number of Cases represented by this range.  If Size is 1,
1013    // then we are processing a leaf of the binary search tree.  Otherwise,
1014    // we need to pick a pivot, and push left and right ranges onto the
1015    // worklist.
1016    unsigned Size = CR.Range.second - CR.Range.first;
1017
1018    if (Size == 1) {
1019      // Create a CaseBlock record representing a conditional branch to
1020      // the Case's target mbb if the value being switched on SV is equal
1021      // to C.  Otherwise, branch to default.
1022      Constant *C = CR.Range.first->first;
1023      MachineBasicBlock *Target = CR.Range.first->second;
1024      SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1025                                     CR.CaseBB);
1026      // If the MBB representing the leaf node is the current MBB, then just
1027      // call visitSwitchCase to emit the code into the current block.
1028      // Otherwise, push the CaseBlock onto the vector to be later processed
1029      // by SDISel, and insert the node's MBB before the next MBB.
1030      if (CR.CaseBB == CurMBB)
1031        visitSwitchCase(CB);
1032      else {
1033        SwitchCases.push_back(CB);
1034        CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1035      }
1036    } else {
1037      // split case range at pivot
1038      CaseItr Pivot = CR.Range.first + (Size / 2);
1039      CaseRange LHSR(CR.Range.first, Pivot);
1040      CaseRange RHSR(Pivot, CR.Range.second);
1041      Constant *C = Pivot->first;
1042      MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1043      // We know that we branch to the LHS if the Value being switched on is
1044      // less than the Pivot value, C.  We use this to optimize our binary
1045      // tree a bit, by recognizing that if SV is greater than or equal to the
1046      // LHS's Case Value, and that Case Value is exactly one less than the
1047      // Pivot's Value, then we can branch directly to the LHS's Target,
1048      // rather than creating a leaf node for it.
1049      if ((LHSR.second - LHSR.first) == 1 &&
1050          LHSR.first->first == CR.GE &&
1051          cast<ConstantIntegral>(C)->getRawValue() ==
1052          (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1053        LHSBB = LHSR.first->second;
1054      } else {
1055        LHSBB = new MachineBasicBlock(LLVMBB);
1056        CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1057      }
1058      // Similar to the optimization above, if the Value being switched on is
1059      // known to be less than the Constant CR.LT, and the current Case Value
1060      // is CR.LT - 1, then we can branch directly to the target block for
1061      // the current Case Value, rather than emitting a RHS leaf node for it.
1062      if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1063          cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1064          (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1065        RHSBB = RHSR.first->second;
1066      } else {
1067        RHSBB = new MachineBasicBlock(LLVMBB);
1068        CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1069      }
1070      // Create a CaseBlock record representing a conditional branch to
1071      // the LHS node if the value being switched on SV is less than C.
1072      // Otherwise, branch to LHS.
1073      ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1074      SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1075      if (CR.CaseBB == CurMBB)
1076        visitSwitchCase(CB);
1077      else {
1078        SwitchCases.push_back(CB);
1079        CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1080      }
1081    }
1082  }
1083}
1084
1085void SelectionDAGLowering::visitSub(User &I) {
1086  // -0.0 - X --> fneg
1087  if (I.getType()->isFloatingPoint()) {
1088    if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1089      if (CFP->isExactlyValue(-0.0)) {
1090        SDOperand Op2 = getValue(I.getOperand(1));
1091        setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1092        return;
1093      }
1094  }
1095  visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1096}
1097
1098void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1099                                       unsigned VecOp) {
1100  const Type *Ty = I.getType();
1101  SDOperand Op1 = getValue(I.getOperand(0));
1102  SDOperand Op2 = getValue(I.getOperand(1));
1103
1104  if (Ty->isIntegral()) {
1105    setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1106  } else if (Ty->isFloatingPoint()) {
1107    setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1108  } else {
1109    const PackedType *PTy = cast<PackedType>(Ty);
1110    SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1111    SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1112    setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1113  }
1114}
1115
1116void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1117  SDOperand Op1 = getValue(I.getOperand(0));
1118  SDOperand Op2 = getValue(I.getOperand(1));
1119
1120  Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1121
1122  setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1123}
1124
1125void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1126                                      ISD::CondCode UnsignedOpcode,
1127                                      ISD::CondCode FPOpcode) {
1128  SDOperand Op1 = getValue(I.getOperand(0));
1129  SDOperand Op2 = getValue(I.getOperand(1));
1130  ISD::CondCode Opcode = SignedOpcode;
1131  if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1132    Opcode = FPOpcode;
1133  else if (I.getOperand(0)->getType()->isUnsigned())
1134    Opcode = UnsignedOpcode;
1135  setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1136}
1137
1138void SelectionDAGLowering::visitSelect(User &I) {
1139  SDOperand Cond     = getValue(I.getOperand(0));
1140  SDOperand TrueVal  = getValue(I.getOperand(1));
1141  SDOperand FalseVal = getValue(I.getOperand(2));
1142  if (!isa<PackedType>(I.getType())) {
1143    setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1144                             TrueVal, FalseVal));
1145  } else {
1146    setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1147                             *(TrueVal.Val->op_end()-2),
1148                             *(TrueVal.Val->op_end()-1)));
1149  }
1150}
1151
1152void SelectionDAGLowering::visitCast(User &I) {
1153  SDOperand N = getValue(I.getOperand(0));
1154  MVT::ValueType SrcVT = N.getValueType();
1155  MVT::ValueType DestVT = TLI.getValueType(I.getType());
1156
1157  if (DestVT == MVT::Vector) {
1158    // This is a cast to a vector from something else.  This is always a bit
1159    // convert.  Get information about the input vector.
1160    const PackedType *DestTy = cast<PackedType>(I.getType());
1161    MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1162    setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1163                             DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1164                             DAG.getValueType(EltVT)));
1165  } else if (SrcVT == DestVT) {
1166    setValue(&I, N);  // noop cast.
1167  } else if (DestVT == MVT::i1) {
1168    // Cast to bool is a comparison against zero, not truncation to zero.
1169    SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1170                                       DAG.getConstantFP(0.0, N.getValueType());
1171    setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1172  } else if (isInteger(SrcVT)) {
1173    if (isInteger(DestVT)) {        // Int -> Int cast
1174      if (DestVT < SrcVT)   // Truncating cast?
1175        setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1176      else if (I.getOperand(0)->getType()->isSigned())
1177        setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1178      else
1179        setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1180    } else if (isFloatingPoint(DestVT)) {           // Int -> FP cast
1181      if (I.getOperand(0)->getType()->isSigned())
1182        setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1183      else
1184        setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1185    } else {
1186      assert(0 && "Unknown cast!");
1187    }
1188  } else if (isFloatingPoint(SrcVT)) {
1189    if (isFloatingPoint(DestVT)) {  // FP -> FP cast
1190      if (DestVT < SrcVT)   // Rounding cast?
1191        setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1192      else
1193        setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1194    } else if (isInteger(DestVT)) {        // FP -> Int cast.
1195      if (I.getType()->isSigned())
1196        setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1197      else
1198        setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1199    } else {
1200      assert(0 && "Unknown cast!");
1201    }
1202  } else {
1203    assert(SrcVT == MVT::Vector && "Unknown cast!");
1204    assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1205    // This is a cast from a vector to something else.  This is always a bit
1206    // convert.  Get information about the input vector.
1207    setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1208  }
1209}
1210
1211void SelectionDAGLowering::visitInsertElement(User &I) {
1212  SDOperand InVec = getValue(I.getOperand(0));
1213  SDOperand InVal = getValue(I.getOperand(1));
1214  SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1215                                getValue(I.getOperand(2)));
1216
1217  SDOperand Num = *(InVec.Val->op_end()-2);
1218  SDOperand Typ = *(InVec.Val->op_end()-1);
1219  setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1220                           InVec, InVal, InIdx, Num, Typ));
1221}
1222
1223void SelectionDAGLowering::visitExtractElement(User &I) {
1224  SDOperand InVec = getValue(I.getOperand(0));
1225  SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1226                                getValue(I.getOperand(1)));
1227  SDOperand Typ = *(InVec.Val->op_end()-1);
1228  setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1229                           TLI.getValueType(I.getType()), InVec, InIdx));
1230}
1231
1232void SelectionDAGLowering::visitShuffleVector(User &I) {
1233  SDOperand V1   = getValue(I.getOperand(0));
1234  SDOperand V2   = getValue(I.getOperand(1));
1235  SDOperand Mask = getValue(I.getOperand(2));
1236
1237  SDOperand Num = *(V1.Val->op_end()-2);
1238  SDOperand Typ = *(V2.Val->op_end()-1);
1239  setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1240                           V1, V2, Mask, Num, Typ));
1241}
1242
1243
1244void SelectionDAGLowering::visitGetElementPtr(User &I) {
1245  SDOperand N = getValue(I.getOperand(0));
1246  const Type *Ty = I.getOperand(0)->getType();
1247
1248  for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1249       OI != E; ++OI) {
1250    Value *Idx = *OI;
1251    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1252      unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1253      if (Field) {
1254        // N = N + Offset
1255        uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1256        N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1257                        getIntPtrConstant(Offset));
1258      }
1259      Ty = StTy->getElementType(Field);
1260    } else {
1261      Ty = cast<SequentialType>(Ty)->getElementType();
1262
1263      // If this is a constant subscript, handle it quickly.
1264      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1265        if (CI->getRawValue() == 0) continue;
1266
1267        uint64_t Offs;
1268        if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1269          Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1270        else
1271          Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1272        N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1273        continue;
1274      }
1275
1276      // N = N + Idx * ElementSize;
1277      uint64_t ElementSize = TD->getTypeSize(Ty);
1278      SDOperand IdxN = getValue(Idx);
1279
1280      // If the index is smaller or larger than intptr_t, truncate or extend
1281      // it.
1282      if (IdxN.getValueType() < N.getValueType()) {
1283        if (Idx->getType()->isSigned())
1284          IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1285        else
1286          IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1287      } else if (IdxN.getValueType() > N.getValueType())
1288        IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1289
1290      // If this is a multiply by a power of two, turn it into a shl
1291      // immediately.  This is a very common case.
1292      if (isPowerOf2_64(ElementSize)) {
1293        unsigned Amt = Log2_64(ElementSize);
1294        IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1295                           DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1296        N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1297        continue;
1298      }
1299
1300      SDOperand Scale = getIntPtrConstant(ElementSize);
1301      IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1302      N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1303    }
1304  }
1305  setValue(&I, N);
1306}
1307
1308void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1309  // If this is a fixed sized alloca in the entry block of the function,
1310  // allocate it statically on the stack.
1311  if (FuncInfo.StaticAllocaMap.count(&I))
1312    return;   // getValue will auto-populate this.
1313
1314  const Type *Ty = I.getAllocatedType();
1315  uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1316  unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1317                            I.getAlignment());
1318
1319  SDOperand AllocSize = getValue(I.getArraySize());
1320  MVT::ValueType IntPtr = TLI.getPointerTy();
1321  if (IntPtr < AllocSize.getValueType())
1322    AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1323  else if (IntPtr > AllocSize.getValueType())
1324    AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1325
1326  AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1327                          getIntPtrConstant(TySize));
1328
1329  // Handle alignment.  If the requested alignment is less than or equal to the
1330  // stack alignment, ignore it and round the size of the allocation up to the
1331  // stack alignment size.  If the size is greater than the stack alignment, we
1332  // note this in the DYNAMIC_STACKALLOC node.
1333  unsigned StackAlign =
1334    TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1335  if (Align <= StackAlign) {
1336    Align = 0;
1337    // Add SA-1 to the size.
1338    AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1339                            getIntPtrConstant(StackAlign-1));
1340    // Mask out the low bits for alignment purposes.
1341    AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1342                            getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1343  }
1344
1345  SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1346  const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1347                                                    MVT::Other);
1348  SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1349  DAG.setRoot(setValue(&I, DSA).getValue(1));
1350
1351  // Inform the Frame Information that we have just allocated a variable-sized
1352  // object.
1353  CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1354}
1355
1356void SelectionDAGLowering::visitLoad(LoadInst &I) {
1357  SDOperand Ptr = getValue(I.getOperand(0));
1358
1359  SDOperand Root;
1360  if (I.isVolatile())
1361    Root = getRoot();
1362  else {
1363    // Do not serialize non-volatile loads against each other.
1364    Root = DAG.getRoot();
1365  }
1366
1367  setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1368                           Root, I.isVolatile()));
1369}
1370
1371SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1372                                            SDOperand SrcValue, SDOperand Root,
1373                                            bool isVolatile) {
1374  SDOperand L;
1375  if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1376    MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1377    L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1378  } else {
1379    L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1380  }
1381
1382  if (isVolatile)
1383    DAG.setRoot(L.getValue(1));
1384  else
1385    PendingLoads.push_back(L.getValue(1));
1386
1387  return L;
1388}
1389
1390
1391void SelectionDAGLowering::visitStore(StoreInst &I) {
1392  Value *SrcV = I.getOperand(0);
1393  SDOperand Src = getValue(SrcV);
1394  SDOperand Ptr = getValue(I.getOperand(1));
1395  DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1396                          DAG.getSrcValue(I.getOperand(1))));
1397}
1398
1399/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1400/// access memory and has no other side effects at all.
1401static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1402#define GET_NO_MEMORY_INTRINSICS
1403#include "llvm/Intrinsics.gen"
1404#undef GET_NO_MEMORY_INTRINSICS
1405  return false;
1406}
1407
1408// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1409// have any side-effects or if it only reads memory.
1410static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1411#define GET_SIDE_EFFECT_INFO
1412#include "llvm/Intrinsics.gen"
1413#undef GET_SIDE_EFFECT_INFO
1414  return false;
1415}
1416
1417/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1418/// node.
1419void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1420                                                unsigned Intrinsic) {
1421  bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1422  bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1423
1424  // Build the operand list.
1425  SmallVector<SDOperand, 8> Ops;
1426  if (HasChain) {  // If this intrinsic has side-effects, chainify it.
1427    if (OnlyLoad) {
1428      // We don't need to serialize loads against other loads.
1429      Ops.push_back(DAG.getRoot());
1430    } else {
1431      Ops.push_back(getRoot());
1432    }
1433  }
1434
1435  // Add the intrinsic ID as an integer operand.
1436  Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1437
1438  // Add all operands of the call to the operand list.
1439  for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1440    SDOperand Op = getValue(I.getOperand(i));
1441
1442    // If this is a vector type, force it to the right packed type.
1443    if (Op.getValueType() == MVT::Vector) {
1444      const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1445      MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1446
1447      MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1448      assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1449      Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1450    }
1451
1452    assert(TLI.isTypeLegal(Op.getValueType()) &&
1453           "Intrinsic uses a non-legal type?");
1454    Ops.push_back(Op);
1455  }
1456
1457  std::vector<MVT::ValueType> VTs;
1458  if (I.getType() != Type::VoidTy) {
1459    MVT::ValueType VT = TLI.getValueType(I.getType());
1460    if (VT == MVT::Vector) {
1461      const PackedType *DestTy = cast<PackedType>(I.getType());
1462      MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1463
1464      VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1465      assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1466    }
1467
1468    assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1469    VTs.push_back(VT);
1470  }
1471  if (HasChain)
1472    VTs.push_back(MVT::Other);
1473
1474  const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1475
1476  // Create the node.
1477  SDOperand Result;
1478  if (!HasChain)
1479    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1480                         &Ops[0], Ops.size());
1481  else if (I.getType() != Type::VoidTy)
1482    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1483                         &Ops[0], Ops.size());
1484  else
1485    Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1486                         &Ops[0], Ops.size());
1487
1488  if (HasChain) {
1489    SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1490    if (OnlyLoad)
1491      PendingLoads.push_back(Chain);
1492    else
1493      DAG.setRoot(Chain);
1494  }
1495  if (I.getType() != Type::VoidTy) {
1496    if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1497      MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1498      Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1499                           DAG.getConstant(PTy->getNumElements(), MVT::i32),
1500                           DAG.getValueType(EVT));
1501    }
1502    setValue(&I, Result);
1503  }
1504}
1505
1506/// visitIntrinsicCall - Lower the call to the specified intrinsic function.  If
1507/// we want to emit this as a call to a named external function, return the name
1508/// otherwise lower it and return null.
1509const char *
1510SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1511  switch (Intrinsic) {
1512  default:
1513    // By default, turn this into a target intrinsic node.
1514    visitTargetIntrinsic(I, Intrinsic);
1515    return 0;
1516  case Intrinsic::vastart:  visitVAStart(I); return 0;
1517  case Intrinsic::vaend:    visitVAEnd(I); return 0;
1518  case Intrinsic::vacopy:   visitVACopy(I); return 0;
1519  case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1520  case Intrinsic::frameaddress:  visitFrameReturnAddress(I, true); return 0;
1521  case Intrinsic::setjmp:
1522    return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1523    break;
1524  case Intrinsic::longjmp:
1525    return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1526    break;
1527  case Intrinsic::memcpy_i32:
1528  case Intrinsic::memcpy_i64:
1529    visitMemIntrinsic(I, ISD::MEMCPY);
1530    return 0;
1531  case Intrinsic::memset_i32:
1532  case Intrinsic::memset_i64:
1533    visitMemIntrinsic(I, ISD::MEMSET);
1534    return 0;
1535  case Intrinsic::memmove_i32:
1536  case Intrinsic::memmove_i64:
1537    visitMemIntrinsic(I, ISD::MEMMOVE);
1538    return 0;
1539
1540  case Intrinsic::dbg_stoppoint: {
1541    MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1542    DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1543    if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1544      SDOperand Ops[5];
1545
1546      Ops[0] = getRoot();
1547      Ops[1] = getValue(SPI.getLineValue());
1548      Ops[2] = getValue(SPI.getColumnValue());
1549
1550      DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1551      assert(DD && "Not a debug information descriptor");
1552      CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1553
1554      Ops[3] = DAG.getString(CompileUnit->getFileName());
1555      Ops[4] = DAG.getString(CompileUnit->getDirectory());
1556
1557      DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1558    }
1559
1560    return 0;
1561  }
1562  case Intrinsic::dbg_region_start: {
1563    MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1564    DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1565    if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1566      unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1567      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1568                              DAG.getConstant(LabelID, MVT::i32)));
1569    }
1570
1571    return 0;
1572  }
1573  case Intrinsic::dbg_region_end: {
1574    MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1575    DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1576    if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1577      unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1578      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1579                              getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1580    }
1581
1582    return 0;
1583  }
1584  case Intrinsic::dbg_func_start: {
1585    MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1586    DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1587    if (DebugInfo && FSI.getSubprogram() &&
1588        DebugInfo->Verify(FSI.getSubprogram())) {
1589      unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1590      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1591                  getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1592    }
1593
1594    return 0;
1595  }
1596  case Intrinsic::dbg_declare: {
1597    MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1598    DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1599    if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1600      SDOperand AddressOp  = getValue(DI.getAddress());
1601      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
1602        DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1603    }
1604
1605    return 0;
1606  }
1607
1608  case Intrinsic::isunordered_f32:
1609  case Intrinsic::isunordered_f64:
1610    setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1611                              getValue(I.getOperand(2)), ISD::SETUO));
1612    return 0;
1613
1614  case Intrinsic::sqrt_f32:
1615  case Intrinsic::sqrt_f64:
1616    setValue(&I, DAG.getNode(ISD::FSQRT,
1617                             getValue(I.getOperand(1)).getValueType(),
1618                             getValue(I.getOperand(1))));
1619    return 0;
1620  case Intrinsic::powi_f32:
1621  case Intrinsic::powi_f64:
1622    setValue(&I, DAG.getNode(ISD::FPOWI,
1623                             getValue(I.getOperand(1)).getValueType(),
1624                             getValue(I.getOperand(1)),
1625                             getValue(I.getOperand(2))));
1626    return 0;
1627  case Intrinsic::pcmarker: {
1628    SDOperand Tmp = getValue(I.getOperand(1));
1629    DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1630    return 0;
1631  }
1632  case Intrinsic::readcyclecounter: {
1633    SDOperand Op = getRoot();
1634    SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
1635                                DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
1636                                &Op, 1);
1637    setValue(&I, Tmp);
1638    DAG.setRoot(Tmp.getValue(1));
1639    return 0;
1640  }
1641  case Intrinsic::bswap_i16:
1642  case Intrinsic::bswap_i32:
1643  case Intrinsic::bswap_i64:
1644    setValue(&I, DAG.getNode(ISD::BSWAP,
1645                             getValue(I.getOperand(1)).getValueType(),
1646                             getValue(I.getOperand(1))));
1647    return 0;
1648  case Intrinsic::cttz_i8:
1649  case Intrinsic::cttz_i16:
1650  case Intrinsic::cttz_i32:
1651  case Intrinsic::cttz_i64:
1652    setValue(&I, DAG.getNode(ISD::CTTZ,
1653                             getValue(I.getOperand(1)).getValueType(),
1654                             getValue(I.getOperand(1))));
1655    return 0;
1656  case Intrinsic::ctlz_i8:
1657  case Intrinsic::ctlz_i16:
1658  case Intrinsic::ctlz_i32:
1659  case Intrinsic::ctlz_i64:
1660    setValue(&I, DAG.getNode(ISD::CTLZ,
1661                             getValue(I.getOperand(1)).getValueType(),
1662                             getValue(I.getOperand(1))));
1663    return 0;
1664  case Intrinsic::ctpop_i8:
1665  case Intrinsic::ctpop_i16:
1666  case Intrinsic::ctpop_i32:
1667  case Intrinsic::ctpop_i64:
1668    setValue(&I, DAG.getNode(ISD::CTPOP,
1669                             getValue(I.getOperand(1)).getValueType(),
1670                             getValue(I.getOperand(1))));
1671    return 0;
1672  case Intrinsic::stacksave: {
1673    SDOperand Op = getRoot();
1674    SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
1675              DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
1676    setValue(&I, Tmp);
1677    DAG.setRoot(Tmp.getValue(1));
1678    return 0;
1679  }
1680  case Intrinsic::stackrestore: {
1681    SDOperand Tmp = getValue(I.getOperand(1));
1682    DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1683    return 0;
1684  }
1685  case Intrinsic::prefetch:
1686    // FIXME: Currently discarding prefetches.
1687    return 0;
1688  }
1689}
1690
1691
1692void SelectionDAGLowering::visitCall(CallInst &I) {
1693  const char *RenameFn = 0;
1694  if (Function *F = I.getCalledFunction()) {
1695    if (F->isExternal())
1696      if (unsigned IID = F->getIntrinsicID()) {
1697        RenameFn = visitIntrinsicCall(I, IID);
1698        if (!RenameFn)
1699          return;
1700      } else {    // Not an LLVM intrinsic.
1701        const std::string &Name = F->getName();
1702        if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1703          if (I.getNumOperands() == 3 &&   // Basic sanity checks.
1704              I.getOperand(1)->getType()->isFloatingPoint() &&
1705              I.getType() == I.getOperand(1)->getType() &&
1706              I.getType() == I.getOperand(2)->getType()) {
1707            SDOperand LHS = getValue(I.getOperand(1));
1708            SDOperand RHS = getValue(I.getOperand(2));
1709            setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1710                                     LHS, RHS));
1711            return;
1712          }
1713        } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1714          if (I.getNumOperands() == 2 &&   // Basic sanity checks.
1715              I.getOperand(1)->getType()->isFloatingPoint() &&
1716              I.getType() == I.getOperand(1)->getType()) {
1717            SDOperand Tmp = getValue(I.getOperand(1));
1718            setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1719            return;
1720          }
1721        } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1722          if (I.getNumOperands() == 2 &&   // Basic sanity checks.
1723              I.getOperand(1)->getType()->isFloatingPoint() &&
1724              I.getType() == I.getOperand(1)->getType()) {
1725            SDOperand Tmp = getValue(I.getOperand(1));
1726            setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1727            return;
1728          }
1729        } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1730          if (I.getNumOperands() == 2 &&   // Basic sanity checks.
1731              I.getOperand(1)->getType()->isFloatingPoint() &&
1732              I.getType() == I.getOperand(1)->getType()) {
1733            SDOperand Tmp = getValue(I.getOperand(1));
1734            setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1735            return;
1736          }
1737        }
1738      }
1739  } else if (isa<InlineAsm>(I.getOperand(0))) {
1740    visitInlineAsm(I);
1741    return;
1742  }
1743
1744  SDOperand Callee;
1745  if (!RenameFn)
1746    Callee = getValue(I.getOperand(0));
1747  else
1748    Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1749  std::vector<std::pair<SDOperand, const Type*> > Args;
1750  Args.reserve(I.getNumOperands());
1751  for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1752    Value *Arg = I.getOperand(i);
1753    SDOperand ArgNode = getValue(Arg);
1754    Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1755  }
1756
1757  const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1758  const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1759
1760  std::pair<SDOperand,SDOperand> Result =
1761    TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1762                    I.isTailCall(), Callee, Args, DAG);
1763  if (I.getType() != Type::VoidTy)
1764    setValue(&I, Result.first);
1765  DAG.setRoot(Result.second);
1766}
1767
1768SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1769                                        SDOperand &Chain, SDOperand &Flag)const{
1770  SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1771  Chain = Val.getValue(1);
1772  Flag  = Val.getValue(2);
1773
1774  // If the result was expanded, copy from the top part.
1775  if (Regs.size() > 1) {
1776    assert(Regs.size() == 2 &&
1777           "Cannot expand to more than 2 elts yet!");
1778    SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1779    Chain = Val.getValue(1);
1780    Flag  = Val.getValue(2);
1781    if (DAG.getTargetLoweringInfo().isLittleEndian())
1782      return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1783    else
1784      return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1785  }
1786
1787  // Otherwise, if the return value was promoted or extended, truncate it to the
1788  // appropriate type.
1789  if (RegVT == ValueVT)
1790    return Val;
1791
1792  if (MVT::isInteger(RegVT)) {
1793    if (ValueVT < RegVT)
1794      return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1795    else
1796      return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1797  } else {
1798    return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1799  }
1800}
1801
1802/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1803/// specified value into the registers specified by this object.  This uses
1804/// Chain/Flag as the input and updates them for the output Chain/Flag.
1805void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1806                                 SDOperand &Chain, SDOperand &Flag,
1807                                 MVT::ValueType PtrVT) const {
1808  if (Regs.size() == 1) {
1809    // If there is a single register and the types differ, this must be
1810    // a promotion.
1811    if (RegVT != ValueVT) {
1812      if (MVT::isInteger(RegVT)) {
1813        if (RegVT < ValueVT)
1814          Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1815        else
1816          Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1817      } else
1818        Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1819    }
1820    Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1821    Flag = Chain.getValue(1);
1822  } else {
1823    std::vector<unsigned> R(Regs);
1824    if (!DAG.getTargetLoweringInfo().isLittleEndian())
1825      std::reverse(R.begin(), R.end());
1826
1827    for (unsigned i = 0, e = R.size(); i != e; ++i) {
1828      SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1829                                   DAG.getConstant(i, PtrVT));
1830      Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1831      Flag = Chain.getValue(1);
1832    }
1833  }
1834}
1835
1836/// AddInlineAsmOperands - Add this value to the specified inlineasm node
1837/// operand list.  This adds the code marker and includes the number of
1838/// values added into it.
1839void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1840                                        std::vector<SDOperand> &Ops) const {
1841  Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1842  for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1843    Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1844}
1845
1846/// isAllocatableRegister - If the specified register is safe to allocate,
1847/// i.e. it isn't a stack pointer or some other special register, return the
1848/// register class for the register.  Otherwise, return null.
1849static const TargetRegisterClass *
1850isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1851                      const TargetLowering &TLI, const MRegisterInfo *MRI) {
1852  MVT::ValueType FoundVT = MVT::Other;
1853  const TargetRegisterClass *FoundRC = 0;
1854  for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1855       E = MRI->regclass_end(); RCI != E; ++RCI) {
1856    MVT::ValueType ThisVT = MVT::Other;
1857
1858    const TargetRegisterClass *RC = *RCI;
1859    // If none of the the value types for this register class are valid, we
1860    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
1861    for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1862         I != E; ++I) {
1863      if (TLI.isTypeLegal(*I)) {
1864        // If we have already found this register in a different register class,
1865        // choose the one with the largest VT specified.  For example, on
1866        // PowerPC, we favor f64 register classes over f32.
1867        if (FoundVT == MVT::Other ||
1868            MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1869          ThisVT = *I;
1870          break;
1871        }
1872      }
1873    }
1874
1875    if (ThisVT == MVT::Other) continue;
1876
1877    // NOTE: This isn't ideal.  In particular, this might allocate the
1878    // frame pointer in functions that need it (due to them not being taken
1879    // out of allocation, because a variable sized allocation hasn't been seen
1880    // yet).  This is a slight code pessimization, but should still work.
1881    for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1882         E = RC->allocation_order_end(MF); I != E; ++I)
1883      if (*I == Reg) {
1884        // We found a matching register class.  Keep looking at others in case
1885        // we find one with larger registers that this physreg is also in.
1886        FoundRC = RC;
1887        FoundVT = ThisVT;
1888        break;
1889      }
1890  }
1891  return FoundRC;
1892}
1893
1894RegsForValue SelectionDAGLowering::
1895GetRegistersForValue(const std::string &ConstrCode,
1896                     MVT::ValueType VT, bool isOutReg, bool isInReg,
1897                     std::set<unsigned> &OutputRegs,
1898                     std::set<unsigned> &InputRegs) {
1899  std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1900    TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1901  std::vector<unsigned> Regs;
1902
1903  unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1904  MVT::ValueType RegVT;
1905  MVT::ValueType ValueVT = VT;
1906
1907  if (PhysReg.first) {
1908    if (VT == MVT::Other)
1909      ValueVT = *PhysReg.second->vt_begin();
1910
1911    // Get the actual register value type.  This is important, because the user
1912    // may have asked for (e.g.) the AX register in i32 type.  We need to
1913    // remember that AX is actually i16 to get the right extension.
1914    RegVT = *PhysReg.second->vt_begin();
1915
1916    // This is a explicit reference to a physical register.
1917    Regs.push_back(PhysReg.first);
1918
1919    // If this is an expanded reference, add the rest of the regs to Regs.
1920    if (NumRegs != 1) {
1921      TargetRegisterClass::iterator I = PhysReg.second->begin();
1922      TargetRegisterClass::iterator E = PhysReg.second->end();
1923      for (; *I != PhysReg.first; ++I)
1924        assert(I != E && "Didn't find reg!");
1925
1926      // Already added the first reg.
1927      --NumRegs; ++I;
1928      for (; NumRegs; --NumRegs, ++I) {
1929        assert(I != E && "Ran out of registers to allocate!");
1930        Regs.push_back(*I);
1931      }
1932    }
1933    return RegsForValue(Regs, RegVT, ValueVT);
1934  }
1935
1936  // This is a reference to a register class.  Allocate NumRegs consecutive,
1937  // available, registers from the class.
1938  std::vector<unsigned> RegClassRegs =
1939    TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1940
1941  const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1942  MachineFunction &MF = *CurMBB->getParent();
1943  unsigned NumAllocated = 0;
1944  for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1945    unsigned Reg = RegClassRegs[i];
1946    // See if this register is available.
1947    if ((isOutReg && OutputRegs.count(Reg)) ||   // Already used.
1948        (isInReg  && InputRegs.count(Reg))) {    // Already used.
1949      // Make sure we find consecutive registers.
1950      NumAllocated = 0;
1951      continue;
1952    }
1953
1954    // Check to see if this register is allocatable (i.e. don't give out the
1955    // stack pointer).
1956    const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1957    if (!RC) {
1958      // Make sure we find consecutive registers.
1959      NumAllocated = 0;
1960      continue;
1961    }
1962
1963    // Okay, this register is good, we can use it.
1964    ++NumAllocated;
1965
1966    // If we allocated enough consecutive
1967    if (NumAllocated == NumRegs) {
1968      unsigned RegStart = (i-NumAllocated)+1;
1969      unsigned RegEnd   = i+1;
1970      // Mark all of the allocated registers used.
1971      for (unsigned i = RegStart; i != RegEnd; ++i) {
1972        unsigned Reg = RegClassRegs[i];
1973        Regs.push_back(Reg);
1974        if (isOutReg) OutputRegs.insert(Reg);    // Mark reg used.
1975        if (isInReg)  InputRegs.insert(Reg);     // Mark reg used.
1976      }
1977
1978      return RegsForValue(Regs, *RC->vt_begin(), VT);
1979    }
1980  }
1981
1982  // Otherwise, we couldn't allocate enough registers for this.
1983  return RegsForValue();
1984}
1985
1986
1987/// visitInlineAsm - Handle a call to an InlineAsm object.
1988///
1989void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1990  InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1991
1992  SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1993                                                 MVT::Other);
1994
1995  // Note, we treat inline asms both with and without side-effects as the same.
1996  // If an inline asm doesn't have side effects and doesn't access memory, we
1997  // could not choose to not chain it.
1998  bool hasSideEffects = IA->hasSideEffects();
1999
2000  std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2001  std::vector<MVT::ValueType> ConstraintVTs;
2002
2003  /// AsmNodeOperands - A list of pairs.  The first element is a register, the
2004  /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2005  /// if it is a def of that register.
2006  std::vector<SDOperand> AsmNodeOperands;
2007  AsmNodeOperands.push_back(SDOperand());  // reserve space for input chain
2008  AsmNodeOperands.push_back(AsmStr);
2009
2010  SDOperand Chain = getRoot();
2011  SDOperand Flag;
2012
2013  // We fully assign registers here at isel time.  This is not optimal, but
2014  // should work.  For register classes that correspond to LLVM classes, we
2015  // could let the LLVM RA do its thing, but we currently don't.  Do a prepass
2016  // over the constraints, collecting fixed registers that we know we can't use.
2017  std::set<unsigned> OutputRegs, InputRegs;
2018  unsigned OpNum = 1;
2019  for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2020    assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2021    std::string &ConstraintCode = Constraints[i].Codes[0];
2022
2023    MVT::ValueType OpVT;
2024
2025    // Compute the value type for each operand and add it to ConstraintVTs.
2026    switch (Constraints[i].Type) {
2027    case InlineAsm::isOutput:
2028      if (!Constraints[i].isIndirectOutput) {
2029        assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2030        OpVT = TLI.getValueType(I.getType());
2031      } else {
2032        const Type *OpTy = I.getOperand(OpNum)->getType();
2033        OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2034        OpNum++;  // Consumes a call operand.
2035      }
2036      break;
2037    case InlineAsm::isInput:
2038      OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2039      OpNum++;  // Consumes a call operand.
2040      break;
2041    case InlineAsm::isClobber:
2042      OpVT = MVT::Other;
2043      break;
2044    }
2045
2046    ConstraintVTs.push_back(OpVT);
2047
2048    if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2049      continue;  // Not assigned a fixed reg.
2050
2051    // Build a list of regs that this operand uses.  This always has a single
2052    // element for promoted/expanded operands.
2053    RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2054                                             false, false,
2055                                             OutputRegs, InputRegs);
2056
2057    switch (Constraints[i].Type) {
2058    case InlineAsm::isOutput:
2059      // We can't assign any other output to this register.
2060      OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2061      // If this is an early-clobber output, it cannot be assigned to the same
2062      // value as the input reg.
2063      if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2064        InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2065      break;
2066    case InlineAsm::isInput:
2067      // We can't assign any other input to this register.
2068      InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2069      break;
2070    case InlineAsm::isClobber:
2071      // Clobbered regs cannot be used as inputs or outputs.
2072      InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2073      OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2074      break;
2075    }
2076  }
2077
2078  // Loop over all of the inputs, copying the operand values into the
2079  // appropriate registers and processing the output regs.
2080  RegsForValue RetValRegs;
2081  std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2082  OpNum = 1;
2083
2084  for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2085    assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2086    std::string &ConstraintCode = Constraints[i].Codes[0];
2087
2088    switch (Constraints[i].Type) {
2089    case InlineAsm::isOutput: {
2090      TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2091      if (ConstraintCode.size() == 1)   // not a physreg name.
2092        CTy = TLI.getConstraintType(ConstraintCode[0]);
2093
2094      if (CTy == TargetLowering::C_Memory) {
2095        // Memory output.
2096        SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2097
2098        // Check that the operand (the address to store to) isn't a float.
2099        if (!MVT::isInteger(InOperandVal.getValueType()))
2100          assert(0 && "MATCH FAIL!");
2101
2102        if (!Constraints[i].isIndirectOutput)
2103          assert(0 && "MATCH FAIL!");
2104
2105        OpNum++;  // Consumes a call operand.
2106
2107        // Extend/truncate to the right pointer type if needed.
2108        MVT::ValueType PtrType = TLI.getPointerTy();
2109        if (InOperandVal.getValueType() < PtrType)
2110          InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2111        else if (InOperandVal.getValueType() > PtrType)
2112          InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2113
2114        // Add information to the INLINEASM node to know about this output.
2115        unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2116        AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2117        AsmNodeOperands.push_back(InOperandVal);
2118        break;
2119      }
2120
2121      // Otherwise, this is a register output.
2122      assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2123
2124      // If this is an early-clobber output, or if there is an input
2125      // constraint that matches this, we need to reserve the input register
2126      // so no other inputs allocate to it.
2127      bool UsesInputRegister = false;
2128      if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2129        UsesInputRegister = true;
2130
2131      // Copy the output from the appropriate register.  Find a register that
2132      // we can use.
2133      RegsForValue Regs =
2134        GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2135                             true, UsesInputRegister,
2136                             OutputRegs, InputRegs);
2137      assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2138
2139      if (!Constraints[i].isIndirectOutput) {
2140        assert(RetValRegs.Regs.empty() &&
2141               "Cannot have multiple output constraints yet!");
2142        assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2143        RetValRegs = Regs;
2144      } else {
2145        IndirectStoresToEmit.push_back(std::make_pair(Regs,
2146                                                      I.getOperand(OpNum)));
2147        OpNum++;  // Consumes a call operand.
2148      }
2149
2150      // Add information to the INLINEASM node to know that this register is
2151      // set.
2152      Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2153      break;
2154    }
2155    case InlineAsm::isInput: {
2156      SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2157      OpNum++;  // Consumes a call operand.
2158
2159      if (isdigit(ConstraintCode[0])) {    // Matching constraint?
2160        // If this is required to match an output register we have already set,
2161        // just use its register.
2162        unsigned OperandNo = atoi(ConstraintCode.c_str());
2163
2164        // Scan until we find the definition we already emitted of this operand.
2165        // When we find it, create a RegsForValue operand.
2166        unsigned CurOp = 2;  // The first operand.
2167        for (; OperandNo; --OperandNo) {
2168          // Advance to the next operand.
2169          unsigned NumOps =
2170            cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2171          assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2172                  (NumOps & 7) == 4 /*MEM*/) &&
2173                 "Skipped past definitions?");
2174          CurOp += (NumOps>>3)+1;
2175        }
2176
2177        unsigned NumOps =
2178          cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2179        assert((NumOps & 7) == 2 /*REGDEF*/ &&
2180               "Skipped past definitions?");
2181
2182        // Add NumOps>>3 registers to MatchedRegs.
2183        RegsForValue MatchedRegs;
2184        MatchedRegs.ValueVT = InOperandVal.getValueType();
2185        MatchedRegs.RegVT   = AsmNodeOperands[CurOp+1].getValueType();
2186        for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2187          unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2188          MatchedRegs.Regs.push_back(Reg);
2189        }
2190
2191        // Use the produced MatchedRegs object to
2192        MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2193                                  TLI.getPointerTy());
2194        MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2195        break;
2196      }
2197
2198      TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2199      if (ConstraintCode.size() == 1)   // not a physreg name.
2200        CTy = TLI.getConstraintType(ConstraintCode[0]);
2201
2202      if (CTy == TargetLowering::C_Other) {
2203        if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2204          assert(0 && "MATCH FAIL!");
2205
2206        // Add information to the INLINEASM node to know about this input.
2207        unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2208        AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2209        AsmNodeOperands.push_back(InOperandVal);
2210        break;
2211      } else if (CTy == TargetLowering::C_Memory) {
2212        // Memory input.
2213
2214        // Check that the operand isn't a float.
2215        if (!MVT::isInteger(InOperandVal.getValueType()))
2216          assert(0 && "MATCH FAIL!");
2217
2218        // Extend/truncate to the right pointer type if needed.
2219        MVT::ValueType PtrType = TLI.getPointerTy();
2220        if (InOperandVal.getValueType() < PtrType)
2221          InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2222        else if (InOperandVal.getValueType() > PtrType)
2223          InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2224
2225        // Add information to the INLINEASM node to know about this input.
2226        unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2227        AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2228        AsmNodeOperands.push_back(InOperandVal);
2229        break;
2230      }
2231
2232      assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2233
2234      // Copy the input into the appropriate registers.
2235      RegsForValue InRegs =
2236        GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2237                             false, true, OutputRegs, InputRegs);
2238      // FIXME: should be match fail.
2239      assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2240
2241      InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2242
2243      InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2244      break;
2245    }
2246    case InlineAsm::isClobber: {
2247      RegsForValue ClobberedRegs =
2248        GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2249                             OutputRegs, InputRegs);
2250      // Add the clobbered value to the operand list, so that the register
2251      // allocator is aware that the physreg got clobbered.
2252      if (!ClobberedRegs.Regs.empty())
2253        ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2254      break;
2255    }
2256    }
2257  }
2258
2259  // Finish up input operands.
2260  AsmNodeOperands[0] = Chain;
2261  if (Flag.Val) AsmNodeOperands.push_back(Flag);
2262
2263  Chain = DAG.getNode(ISD::INLINEASM,
2264                      DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2265                      &AsmNodeOperands[0], AsmNodeOperands.size());
2266  Flag = Chain.getValue(1);
2267
2268  // If this asm returns a register value, copy the result from that register
2269  // and set it as the value of the call.
2270  if (!RetValRegs.Regs.empty())
2271    setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2272
2273  std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2274
2275  // Process indirect outputs, first output all of the flagged copies out of
2276  // physregs.
2277  for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2278    RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2279    Value *Ptr = IndirectStoresToEmit[i].second;
2280    SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2281    StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2282  }
2283
2284  // Emit the non-flagged stores from the physregs.
2285  SmallVector<SDOperand, 8> OutChains;
2286  for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2287    OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2288                                    StoresToEmit[i].first,
2289                                    getValue(StoresToEmit[i].second),
2290                                    DAG.getSrcValue(StoresToEmit[i].second)));
2291  if (!OutChains.empty())
2292    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2293                        &OutChains[0], OutChains.size());
2294  DAG.setRoot(Chain);
2295}
2296
2297
2298void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2299  SDOperand Src = getValue(I.getOperand(0));
2300
2301  MVT::ValueType IntPtr = TLI.getPointerTy();
2302
2303  if (IntPtr < Src.getValueType())
2304    Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2305  else if (IntPtr > Src.getValueType())
2306    Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2307
2308  // Scale the source by the type size.
2309  uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2310  Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2311                    Src, getIntPtrConstant(ElementSize));
2312
2313  std::vector<std::pair<SDOperand, const Type*> > Args;
2314  Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2315
2316  std::pair<SDOperand,SDOperand> Result =
2317    TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2318                    DAG.getExternalSymbol("malloc", IntPtr),
2319                    Args, DAG);
2320  setValue(&I, Result.first);  // Pointers always fit in registers
2321  DAG.setRoot(Result.second);
2322}
2323
2324void SelectionDAGLowering::visitFree(FreeInst &I) {
2325  std::vector<std::pair<SDOperand, const Type*> > Args;
2326  Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2327                                TLI.getTargetData()->getIntPtrType()));
2328  MVT::ValueType IntPtr = TLI.getPointerTy();
2329  std::pair<SDOperand,SDOperand> Result =
2330    TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2331                    DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2332  DAG.setRoot(Result.second);
2333}
2334
2335// InsertAtEndOfBasicBlock - This method should be implemented by targets that
2336// mark instructions with the 'usesCustomDAGSchedInserter' flag.  These
2337// instructions are special in various ways, which require special support to
2338// insert.  The specified MachineInstr is created but not inserted into any
2339// basic blocks, and the scheduler passes ownership of it to this method.
2340MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2341                                                       MachineBasicBlock *MBB) {
2342  std::cerr << "If a target marks an instruction with "
2343               "'usesCustomDAGSchedInserter', it must implement "
2344               "TargetLowering::InsertAtEndOfBasicBlock!\n";
2345  abort();
2346  return 0;
2347}
2348
2349void SelectionDAGLowering::visitVAStart(CallInst &I) {
2350  DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2351                          getValue(I.getOperand(1)),
2352                          DAG.getSrcValue(I.getOperand(1))));
2353}
2354
2355void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2356  SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2357                             getValue(I.getOperand(0)),
2358                             DAG.getSrcValue(I.getOperand(0)));
2359  setValue(&I, V);
2360  DAG.setRoot(V.getValue(1));
2361}
2362
2363void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2364  DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2365                          getValue(I.getOperand(1)),
2366                          DAG.getSrcValue(I.getOperand(1))));
2367}
2368
2369void SelectionDAGLowering::visitVACopy(CallInst &I) {
2370  DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2371                          getValue(I.getOperand(1)),
2372                          getValue(I.getOperand(2)),
2373                          DAG.getSrcValue(I.getOperand(1)),
2374                          DAG.getSrcValue(I.getOperand(2))));
2375}
2376
2377/// TargetLowering::LowerArguments - This is the default LowerArguments
2378/// implementation, which just inserts a FORMAL_ARGUMENTS node.  FIXME: When all
2379/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2380/// integrated into SDISel.
2381std::vector<SDOperand>
2382TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2383  // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2384  std::vector<SDOperand> Ops;
2385  Ops.push_back(DAG.getRoot());
2386  Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2387  Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2388
2389  // Add one result value for each formal argument.
2390  std::vector<MVT::ValueType> RetVals;
2391  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2392    MVT::ValueType VT = getValueType(I->getType());
2393
2394    switch (getTypeAction(VT)) {
2395    default: assert(0 && "Unknown type action!");
2396    case Legal:
2397      RetVals.push_back(VT);
2398      break;
2399    case Promote:
2400      RetVals.push_back(getTypeToTransformTo(VT));
2401      break;
2402    case Expand:
2403      if (VT != MVT::Vector) {
2404        // If this is a large integer, it needs to be broken up into small
2405        // integers.  Figure out what the destination type is and how many small
2406        // integers it turns into.
2407        MVT::ValueType NVT = getTypeToTransformTo(VT);
2408        unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2409        for (unsigned i = 0; i != NumVals; ++i)
2410          RetVals.push_back(NVT);
2411      } else {
2412        // Otherwise, this is a vector type.  We only support legal vectors
2413        // right now.
2414        unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2415        const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2416
2417        // Figure out if there is a Packed type corresponding to this Vector
2418        // type.  If so, convert to the packed type.
2419        MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2420        if (TVT != MVT::Other && isTypeLegal(TVT)) {
2421          RetVals.push_back(TVT);
2422        } else {
2423          assert(0 && "Don't support illegal by-val vector arguments yet!");
2424        }
2425      }
2426      break;
2427    }
2428  }
2429
2430  RetVals.push_back(MVT::Other);
2431
2432  // Create the node.
2433  SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2434                               DAG.getNodeValueTypes(RetVals), RetVals.size(),
2435                               &Ops[0], Ops.size()).Val;
2436
2437  DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2438
2439  // Set up the return result vector.
2440  Ops.clear();
2441  unsigned i = 0;
2442  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2443    MVT::ValueType VT = getValueType(I->getType());
2444
2445    switch (getTypeAction(VT)) {
2446    default: assert(0 && "Unknown type action!");
2447    case Legal:
2448      Ops.push_back(SDOperand(Result, i++));
2449      break;
2450    case Promote: {
2451      SDOperand Op(Result, i++);
2452      if (MVT::isInteger(VT)) {
2453        unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2454                                                     : ISD::AssertZext;
2455        Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2456        Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2457      } else {
2458        assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2459        Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2460      }
2461      Ops.push_back(Op);
2462      break;
2463    }
2464    case Expand:
2465      if (VT != MVT::Vector) {
2466        // If this is a large integer, it needs to be reassembled from small
2467        // integers.  Figure out what the source elt type is and how many small
2468        // integers it is.
2469        MVT::ValueType NVT = getTypeToTransformTo(VT);
2470        unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2471        if (NumVals == 2) {
2472          SDOperand Lo = SDOperand(Result, i++);
2473          SDOperand Hi = SDOperand(Result, i++);
2474
2475          if (!isLittleEndian())
2476            std::swap(Lo, Hi);
2477
2478          Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2479        } else {
2480          // Value scalarized into many values.  Unimp for now.
2481          assert(0 && "Cannot expand i64 -> i16 yet!");
2482        }
2483      } else {
2484        // Otherwise, this is a vector type.  We only support legal vectors
2485        // right now.
2486        const PackedType *PTy = cast<PackedType>(I->getType());
2487        unsigned NumElems = PTy->getNumElements();
2488        const Type *EltTy = PTy->getElementType();
2489
2490        // Figure out if there is a Packed type corresponding to this Vector
2491        // type.  If so, convert to the packed type.
2492        MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2493        if (TVT != MVT::Other && isTypeLegal(TVT)) {
2494          SDOperand N = SDOperand(Result, i++);
2495          // Handle copies from generic vectors to registers.
2496          N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2497                          DAG.getConstant(NumElems, MVT::i32),
2498                          DAG.getValueType(getValueType(EltTy)));
2499          Ops.push_back(N);
2500        } else {
2501          assert(0 && "Don't support illegal by-val vector arguments yet!");
2502          abort();
2503        }
2504      }
2505      break;
2506    }
2507  }
2508  return Ops;
2509}
2510
2511
2512/// TargetLowering::LowerCallTo - This is the default LowerCallTo
2513/// implementation, which just inserts an ISD::CALL node, which is later custom
2514/// lowered by the target to something concrete.  FIXME: When all targets are
2515/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2516std::pair<SDOperand, SDOperand>
2517TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2518                            unsigned CallingConv, bool isTailCall,
2519                            SDOperand Callee,
2520                            ArgListTy &Args, SelectionDAG &DAG) {
2521  SmallVector<SDOperand, 32> Ops;
2522  Ops.push_back(Chain);   // Op#0 - Chain
2523  Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2524  Ops.push_back(DAG.getConstant(isVarArg, getPointerTy()));    // Op#2 - VarArg
2525  Ops.push_back(DAG.getConstant(isTailCall, getPointerTy()));  // Op#3 - Tail
2526  Ops.push_back(Callee);
2527
2528  // Handle all of the outgoing arguments.
2529  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2530    MVT::ValueType VT = getValueType(Args[i].second);
2531    SDOperand Op = Args[i].first;
2532    bool isSigned = Args[i].second->isSigned();
2533    switch (getTypeAction(VT)) {
2534    default: assert(0 && "Unknown type action!");
2535    case Legal:
2536      Ops.push_back(Op);
2537      Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2538      break;
2539    case Promote:
2540      if (MVT::isInteger(VT)) {
2541        unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2542        Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2543      } else {
2544        assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2545        Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2546      }
2547      Ops.push_back(Op);
2548      Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2549      break;
2550    case Expand:
2551      if (VT != MVT::Vector) {
2552        // If this is a large integer, it needs to be broken down into small
2553        // integers.  Figure out what the source elt type is and how many small
2554        // integers it is.
2555        MVT::ValueType NVT = getTypeToTransformTo(VT);
2556        unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2557        if (NumVals == 2) {
2558          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2559                                     DAG.getConstant(0, getPointerTy()));
2560          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2561                                     DAG.getConstant(1, getPointerTy()));
2562          if (!isLittleEndian())
2563            std::swap(Lo, Hi);
2564
2565          Ops.push_back(Lo);
2566          Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2567          Ops.push_back(Hi);
2568          Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2569        } else {
2570          // Value scalarized into many values.  Unimp for now.
2571          assert(0 && "Cannot expand i64 -> i16 yet!");
2572        }
2573      } else {
2574        // Otherwise, this is a vector type.  We only support legal vectors
2575        // right now.
2576        const PackedType *PTy = cast<PackedType>(Args[i].second);
2577        unsigned NumElems = PTy->getNumElements();
2578        const Type *EltTy = PTy->getElementType();
2579
2580        // Figure out if there is a Packed type corresponding to this Vector
2581        // type.  If so, convert to the packed type.
2582        MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2583        if (TVT != MVT::Other && isTypeLegal(TVT)) {
2584          // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2585          Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2586          Ops.push_back(Op);
2587          Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2588        } else {
2589          assert(0 && "Don't support illegal by-val vector call args yet!");
2590          abort();
2591        }
2592      }
2593      break;
2594    }
2595  }
2596
2597  // Figure out the result value types.
2598  SmallVector<MVT::ValueType, 4> RetTys;
2599
2600  if (RetTy != Type::VoidTy) {
2601    MVT::ValueType VT = getValueType(RetTy);
2602    switch (getTypeAction(VT)) {
2603    default: assert(0 && "Unknown type action!");
2604    case Legal:
2605      RetTys.push_back(VT);
2606      break;
2607    case Promote:
2608      RetTys.push_back(getTypeToTransformTo(VT));
2609      break;
2610    case Expand:
2611      if (VT != MVT::Vector) {
2612        // If this is a large integer, it needs to be reassembled from small
2613        // integers.  Figure out what the source elt type is and how many small
2614        // integers it is.
2615        MVT::ValueType NVT = getTypeToTransformTo(VT);
2616        unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2617        for (unsigned i = 0; i != NumVals; ++i)
2618          RetTys.push_back(NVT);
2619      } else {
2620        // Otherwise, this is a vector type.  We only support legal vectors
2621        // right now.
2622        const PackedType *PTy = cast<PackedType>(RetTy);
2623        unsigned NumElems = PTy->getNumElements();
2624        const Type *EltTy = PTy->getElementType();
2625
2626        // Figure out if there is a Packed type corresponding to this Vector
2627        // type.  If so, convert to the packed type.
2628        MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2629        if (TVT != MVT::Other && isTypeLegal(TVT)) {
2630          RetTys.push_back(TVT);
2631        } else {
2632          assert(0 && "Don't support illegal by-val vector call results yet!");
2633          abort();
2634        }
2635      }
2636    }
2637  }
2638
2639  RetTys.push_back(MVT::Other);  // Always has a chain.
2640
2641  // Finally, create the CALL node.
2642  SDOperand Res = DAG.getNode(ISD::CALL,
2643                              DAG.getVTList(&RetTys[0], RetTys.size()),
2644                              &Ops[0], Ops.size());
2645
2646  // This returns a pair of operands.  The first element is the
2647  // return value for the function (if RetTy is not VoidTy).  The second
2648  // element is the outgoing token chain.
2649  SDOperand ResVal;
2650  if (RetTys.size() != 1) {
2651    MVT::ValueType VT = getValueType(RetTy);
2652    if (RetTys.size() == 2) {
2653      ResVal = Res;
2654
2655      // If this value was promoted, truncate it down.
2656      if (ResVal.getValueType() != VT) {
2657        if (VT == MVT::Vector) {
2658          // Insert a VBITCONVERT to convert from the packed result type to the
2659          // MVT::Vector type.
2660          unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2661          const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2662
2663          // Figure out if there is a Packed type corresponding to this Vector
2664          // type.  If so, convert to the packed type.
2665          MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2666          if (TVT != MVT::Other && isTypeLegal(TVT)) {
2667            // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2668            // "N x PTyElementVT" MVT::Vector type.
2669            ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2670                                 DAG.getConstant(NumElems, MVT::i32),
2671                                 DAG.getValueType(getValueType(EltTy)));
2672          } else {
2673            abort();
2674          }
2675        } else if (MVT::isInteger(VT)) {
2676          unsigned AssertOp = RetTy->isSigned() ?
2677                                  ISD::AssertSext : ISD::AssertZext;
2678          ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2679                               DAG.getValueType(VT));
2680          ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2681        } else {
2682          assert(MVT::isFloatingPoint(VT));
2683          ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2684        }
2685      }
2686    } else if (RetTys.size() == 3) {
2687      ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2688                           Res.getValue(0), Res.getValue(1));
2689
2690    } else {
2691      assert(0 && "Case not handled yet!");
2692    }
2693  }
2694
2695  return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2696}
2697
2698
2699
2700// It is always conservatively correct for llvm.returnaddress and
2701// llvm.frameaddress to return 0.
2702//
2703// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2704// expanded to 0 if the target wants.
2705std::pair<SDOperand, SDOperand>
2706TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2707                                        unsigned Depth, SelectionDAG &DAG) {
2708  return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2709}
2710
2711SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2712  assert(0 && "LowerOperation not implemented for this target!");
2713  abort();
2714  return SDOperand();
2715}
2716
2717SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2718                                                 SelectionDAG &DAG) {
2719  assert(0 && "CustomPromoteOperation not implemented for this target!");
2720  abort();
2721  return SDOperand();
2722}
2723
2724void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2725  unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2726  std::pair<SDOperand,SDOperand> Result =
2727    TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2728  setValue(&I, Result.first);
2729  DAG.setRoot(Result.second);
2730}
2731
2732/// getMemsetValue - Vectorized representation of the memset value
2733/// operand.
2734static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2735                                SelectionDAG &DAG) {
2736  MVT::ValueType CurVT = VT;
2737  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2738    uint64_t Val   = C->getValue() & 255;
2739    unsigned Shift = 8;
2740    while (CurVT != MVT::i8) {
2741      Val = (Val << Shift) | Val;
2742      Shift <<= 1;
2743      CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2744    }
2745    return DAG.getConstant(Val, VT);
2746  } else {
2747    Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2748    unsigned Shift = 8;
2749    while (CurVT != MVT::i8) {
2750      Value =
2751        DAG.getNode(ISD::OR, VT,
2752                    DAG.getNode(ISD::SHL, VT, Value,
2753                                DAG.getConstant(Shift, MVT::i8)), Value);
2754      Shift <<= 1;
2755      CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2756    }
2757
2758    return Value;
2759  }
2760}
2761
2762/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2763/// used when a memcpy is turned into a memset when the source is a constant
2764/// string ptr.
2765static SDOperand getMemsetStringVal(MVT::ValueType VT,
2766                                    SelectionDAG &DAG, TargetLowering &TLI,
2767                                    std::string &Str, unsigned Offset) {
2768  MVT::ValueType CurVT = VT;
2769  uint64_t Val = 0;
2770  unsigned MSB = getSizeInBits(VT) / 8;
2771  if (TLI.isLittleEndian())
2772    Offset = Offset + MSB - 1;
2773  for (unsigned i = 0; i != MSB; ++i) {
2774    Val = (Val << 8) | Str[Offset];
2775    Offset += TLI.isLittleEndian() ? -1 : 1;
2776  }
2777  return DAG.getConstant(Val, VT);
2778}
2779
2780/// getMemBasePlusOffset - Returns base and offset node for the
2781static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2782                                      SelectionDAG &DAG, TargetLowering &TLI) {
2783  MVT::ValueType VT = Base.getValueType();
2784  return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2785}
2786
2787/// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2788/// to replace the memset / memcpy is below the threshold. It also returns the
2789/// types of the sequence of  memory ops to perform memset / memcpy.
2790static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2791                                     unsigned Limit, uint64_t Size,
2792                                     unsigned Align, TargetLowering &TLI) {
2793  MVT::ValueType VT;
2794
2795  if (TLI.allowsUnalignedMemoryAccesses()) {
2796    VT = MVT::i64;
2797  } else {
2798    switch (Align & 7) {
2799    case 0:
2800      VT = MVT::i64;
2801      break;
2802    case 4:
2803      VT = MVT::i32;
2804      break;
2805    case 2:
2806      VT = MVT::i16;
2807      break;
2808    default:
2809      VT = MVT::i8;
2810      break;
2811    }
2812  }
2813
2814  MVT::ValueType LVT = MVT::i64;
2815  while (!TLI.isTypeLegal(LVT))
2816    LVT = (MVT::ValueType)((unsigned)LVT - 1);
2817  assert(MVT::isInteger(LVT));
2818
2819  if (VT > LVT)
2820    VT = LVT;
2821
2822  unsigned NumMemOps = 0;
2823  while (Size != 0) {
2824    unsigned VTSize = getSizeInBits(VT) / 8;
2825    while (VTSize > Size) {
2826      VT = (MVT::ValueType)((unsigned)VT - 1);
2827      VTSize >>= 1;
2828    }
2829    assert(MVT::isInteger(VT));
2830
2831    if (++NumMemOps > Limit)
2832      return false;
2833    MemOps.push_back(VT);
2834    Size -= VTSize;
2835  }
2836
2837  return true;
2838}
2839
2840void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2841  SDOperand Op1 = getValue(I.getOperand(1));
2842  SDOperand Op2 = getValue(I.getOperand(2));
2843  SDOperand Op3 = getValue(I.getOperand(3));
2844  SDOperand Op4 = getValue(I.getOperand(4));
2845  unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2846  if (Align == 0) Align = 1;
2847
2848  if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2849    std::vector<MVT::ValueType> MemOps;
2850
2851    // Expand memset / memcpy to a series of load / store ops
2852    // if the size operand falls below a certain threshold.
2853    SmallVector<SDOperand, 8> OutChains;
2854    switch (Op) {
2855    default: break;  // Do nothing for now.
2856    case ISD::MEMSET: {
2857      if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2858                                   Size->getValue(), Align, TLI)) {
2859        unsigned NumMemOps = MemOps.size();
2860        unsigned Offset = 0;
2861        for (unsigned i = 0; i < NumMemOps; i++) {
2862          MVT::ValueType VT = MemOps[i];
2863          unsigned VTSize = getSizeInBits(VT) / 8;
2864          SDOperand Value = getMemsetValue(Op2, VT, DAG);
2865          SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2866                                        Value,
2867                                    getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2868                                      DAG.getSrcValue(I.getOperand(1), Offset));
2869          OutChains.push_back(Store);
2870          Offset += VTSize;
2871        }
2872      }
2873      break;
2874    }
2875    case ISD::MEMCPY: {
2876      if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2877                                   Size->getValue(), Align, TLI)) {
2878        unsigned NumMemOps = MemOps.size();
2879        unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2880        GlobalAddressSDNode *G = NULL;
2881        std::string Str;
2882        bool CopyFromStr = false;
2883
2884        if (Op2.getOpcode() == ISD::GlobalAddress)
2885          G = cast<GlobalAddressSDNode>(Op2);
2886        else if (Op2.getOpcode() == ISD::ADD &&
2887                 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2888                 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2889          G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2890          SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2891        }
2892        if (G) {
2893          GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2894          if (GV) {
2895            Str = GV->getStringValue(false);
2896            if (!Str.empty()) {
2897              CopyFromStr = true;
2898              SrcOff += SrcDelta;
2899            }
2900          }
2901        }
2902
2903        for (unsigned i = 0; i < NumMemOps; i++) {
2904          MVT::ValueType VT = MemOps[i];
2905          unsigned VTSize = getSizeInBits(VT) / 8;
2906          SDOperand Value, Chain, Store;
2907
2908          if (CopyFromStr) {
2909            Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2910            Chain = getRoot();
2911            Store =
2912              DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2913                          getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2914                          DAG.getSrcValue(I.getOperand(1), DstOff));
2915          } else {
2916            Value = DAG.getLoad(VT, getRoot(),
2917                        getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2918                        DAG.getSrcValue(I.getOperand(2), SrcOff));
2919            Chain = Value.getValue(1);
2920            Store =
2921              DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2922                          getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2923                          DAG.getSrcValue(I.getOperand(1), DstOff));
2924          }
2925          OutChains.push_back(Store);
2926          SrcOff += VTSize;
2927          DstOff += VTSize;
2928        }
2929      }
2930      break;
2931    }
2932    }
2933
2934    if (!OutChains.empty()) {
2935      DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
2936                  &OutChains[0], OutChains.size()));
2937      return;
2938    }
2939  }
2940
2941  DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
2942}
2943
2944//===----------------------------------------------------------------------===//
2945// SelectionDAGISel code
2946//===----------------------------------------------------------------------===//
2947
2948unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2949  return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2950}
2951
2952void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2953  // FIXME: we only modify the CFG to split critical edges.  This
2954  // updates dom and loop info.
2955}
2956
2957
2958/// OptimizeNoopCopyExpression - We have determined that the specified cast
2959/// instruction is a noop copy (e.g. it's casting from one pointer type to
2960/// another, int->uint, or int->sbyte on PPC.
2961///
2962/// Return true if any changes are made.
2963static bool OptimizeNoopCopyExpression(CastInst *CI) {
2964  BasicBlock *DefBB = CI->getParent();
2965
2966  /// InsertedCasts - Only insert a cast in each block once.
2967  std::map<BasicBlock*, CastInst*> InsertedCasts;
2968
2969  bool MadeChange = false;
2970  for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2971       UI != E; ) {
2972    Use &TheUse = UI.getUse();
2973    Instruction *User = cast<Instruction>(*UI);
2974
2975    // Figure out which BB this cast is used in.  For PHI's this is the
2976    // appropriate predecessor block.
2977    BasicBlock *UserBB = User->getParent();
2978    if (PHINode *PN = dyn_cast<PHINode>(User)) {
2979      unsigned OpVal = UI.getOperandNo()/2;
2980      UserBB = PN->getIncomingBlock(OpVal);
2981    }
2982
2983    // Preincrement use iterator so we don't invalidate it.
2984    ++UI;
2985
2986    // If this user is in the same block as the cast, don't change the cast.
2987    if (UserBB == DefBB) continue;
2988
2989    // If we have already inserted a cast into this block, use it.
2990    CastInst *&InsertedCast = InsertedCasts[UserBB];
2991
2992    if (!InsertedCast) {
2993      BasicBlock::iterator InsertPt = UserBB->begin();
2994      while (isa<PHINode>(InsertPt)) ++InsertPt;
2995
2996      InsertedCast =
2997        new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2998      MadeChange = true;
2999    }
3000
3001    // Replace a use of the cast with a use of the new casat.
3002    TheUse = InsertedCast;
3003  }
3004
3005  // If we removed all uses, nuke the cast.
3006  if (CI->use_empty())
3007    CI->eraseFromParent();
3008
3009  return MadeChange;
3010}
3011
3012/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3013/// casting to the type of GEPI.
3014static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3015                                         Instruction *GEPI, Value *Ptr,
3016                                         Value *PtrOffset) {
3017  if (V) return V;   // Already computed.
3018
3019  BasicBlock::iterator InsertPt;
3020  if (BB == GEPI->getParent()) {
3021    // If insert into the GEP's block, insert right after the GEP.
3022    InsertPt = GEPI;
3023    ++InsertPt;
3024  } else {
3025    // Otherwise, insert at the top of BB, after any PHI nodes
3026    InsertPt = BB->begin();
3027    while (isa<PHINode>(InsertPt)) ++InsertPt;
3028  }
3029
3030  // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3031  // BB so that there is only one value live across basic blocks (the cast
3032  // operand).
3033  if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3034    if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3035      Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3036
3037  // Add the offset, cast it to the right type.
3038  Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3039  return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3040}
3041
3042/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3043/// compute its value.  The RepPtr value can be computed with Ptr+PtrOffset. One
3044/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3045/// block, then ReplaceAllUsesWith'ing everything.  However, we would prefer to
3046/// sink PtrOffset into user blocks where doing so will likely allow us to fold
3047/// the constant add into a load or store instruction.  Additionally, if a user
3048/// is a pointer-pointer cast, we look through it to find its users.
3049static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3050                                 Constant *PtrOffset, BasicBlock *DefBB,
3051                                 GetElementPtrInst *GEPI,
3052                           std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3053  while (!RepPtr->use_empty()) {
3054    Instruction *User = cast<Instruction>(RepPtr->use_back());
3055
3056    // If the user is a Pointer-Pointer cast, recurse.
3057    if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3058      ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3059
3060      // Drop the use of RepPtr. The cast is dead.  Don't delete it now, else we
3061      // could invalidate an iterator.
3062      User->setOperand(0, UndefValue::get(RepPtr->getType()));
3063      continue;
3064    }
3065
3066    // If this is a load of the pointer, or a store through the pointer, emit
3067    // the increment into the load/store block.
3068    Instruction *NewVal;
3069    if (isa<LoadInst>(User) ||
3070        (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3071      NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3072                                    User->getParent(), GEPI,
3073                                    Ptr, PtrOffset);
3074    } else {
3075      // If this use is not foldable into the addressing mode, use a version
3076      // emitted in the GEP block.
3077      NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3078                                    Ptr, PtrOffset);
3079    }
3080
3081    if (GEPI->getType() != RepPtr->getType()) {
3082      BasicBlock::iterator IP = NewVal;
3083      ++IP;
3084      NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3085    }
3086    User->replaceUsesOfWith(RepPtr, NewVal);
3087  }
3088}
3089
3090
3091/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3092/// selection, we want to be a bit careful about some things.  In particular, if
3093/// we have a GEP instruction that is used in a different block than it is
3094/// defined, the addressing expression of the GEP cannot be folded into loads or
3095/// stores that use it.  In this case, decompose the GEP and move constant
3096/// indices into blocks that use it.
3097static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3098                                  const TargetData *TD) {
3099  // If this GEP is only used inside the block it is defined in, there is no
3100  // need to rewrite it.
3101  bool isUsedOutsideDefBB = false;
3102  BasicBlock *DefBB = GEPI->getParent();
3103  for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3104       UI != E; ++UI) {
3105    if (cast<Instruction>(*UI)->getParent() != DefBB) {
3106      isUsedOutsideDefBB = true;
3107      break;
3108    }
3109  }
3110  if (!isUsedOutsideDefBB) return false;
3111
3112  // If this GEP has no non-zero constant indices, there is nothing we can do,
3113  // ignore it.
3114  bool hasConstantIndex = false;
3115  bool hasVariableIndex = false;
3116  for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3117       E = GEPI->op_end(); OI != E; ++OI) {
3118    if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3119      if (CI->getRawValue()) {
3120        hasConstantIndex = true;
3121        break;
3122      }
3123    } else {
3124      hasVariableIndex = true;
3125    }
3126  }
3127
3128  // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3129  if (!hasConstantIndex && !hasVariableIndex) {
3130    Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3131                             GEPI->getName(), GEPI);
3132    GEPI->replaceAllUsesWith(NC);
3133    GEPI->eraseFromParent();
3134    return true;
3135  }
3136
3137  // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3138  if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3139    return false;
3140
3141  // Otherwise, decompose the GEP instruction into multiplies and adds.  Sum the
3142  // constant offset (which we now know is non-zero) and deal with it later.
3143  uint64_t ConstantOffset = 0;
3144  const Type *UIntPtrTy = TD->getIntPtrType();
3145  Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3146  const Type *Ty = GEPI->getOperand(0)->getType();
3147
3148  for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3149       E = GEPI->op_end(); OI != E; ++OI) {
3150    Value *Idx = *OI;
3151    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3152      unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3153      if (Field)
3154        ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3155      Ty = StTy->getElementType(Field);
3156    } else {
3157      Ty = cast<SequentialType>(Ty)->getElementType();
3158
3159      // Handle constant subscripts.
3160      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3161        if (CI->getRawValue() == 0) continue;
3162
3163        if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3164          ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3165        else
3166          ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3167        continue;
3168      }
3169
3170      // Ptr = Ptr + Idx * ElementSize;
3171
3172      // Cast Idx to UIntPtrTy if needed.
3173      Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3174
3175      uint64_t ElementSize = TD->getTypeSize(Ty);
3176      // Mask off bits that should not be set.
3177      ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3178      Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3179
3180      // Multiply by the element size and add to the base.
3181      Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3182      Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3183    }
3184  }
3185
3186  // Make sure that the offset fits in uintptr_t.
3187  ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3188  Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3189
3190  // Okay, we have now emitted all of the variable index parts to the BB that
3191  // the GEP is defined in.  Loop over all of the using instructions, inserting
3192  // an "add Ptr, ConstantOffset" into each block that uses it and update the
3193  // instruction to use the newly computed value, making GEPI dead.  When the
3194  // user is a load or store instruction address, we emit the add into the user
3195  // block, otherwise we use a canonical version right next to the gep (these
3196  // won't be foldable as addresses, so we might as well share the computation).
3197
3198  std::map<BasicBlock*,Instruction*> InsertedExprs;
3199  ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3200
3201  // Finally, the GEP is dead, remove it.
3202  GEPI->eraseFromParent();
3203
3204  return true;
3205}
3206
3207bool SelectionDAGISel::runOnFunction(Function &Fn) {
3208  MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3209  RegMap = MF.getSSARegMap();
3210  DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3211
3212  // First, split all critical edges for PHI nodes with incoming values that are
3213  // constants, this way the load of the constant into a vreg will not be placed
3214  // into MBBs that are used some other way.
3215  //
3216  // In this pass we also look for GEP and cast instructions that are used
3217  // across basic blocks and rewrite them to improve basic-block-at-a-time
3218  // selection.
3219  //
3220  //
3221  bool MadeChange = true;
3222  while (MadeChange) {
3223    MadeChange = false;
3224  for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3225    PHINode *PN;
3226    BasicBlock::iterator BBI;
3227    for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3228      for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3229        if (isa<Constant>(PN->getIncomingValue(i)))
3230          SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3231
3232    for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3233      Instruction *I = BBI++;
3234      if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3235        MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3236      } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3237        // If this is a noop copy, sink it into user blocks to reduce the number
3238        // of virtual registers that must be created and coallesced.
3239        MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3240        MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3241
3242        // This is an fp<->int conversion?
3243        if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3244          continue;
3245
3246        // If this is an extension, it will be a zero or sign extension, which
3247        // isn't a noop.
3248        if (SrcVT < DstVT) continue;
3249
3250        // If these values will be promoted, find out what they will be promoted
3251        // to.  This helps us consider truncates on PPC as noop copies when they
3252        // are.
3253        if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3254          SrcVT = TLI.getTypeToTransformTo(SrcVT);
3255        if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3256          DstVT = TLI.getTypeToTransformTo(DstVT);
3257
3258        // If, after promotion, these are the same types, this is a noop copy.
3259        if (SrcVT == DstVT)
3260          MadeChange |= OptimizeNoopCopyExpression(CI);
3261      }
3262    }
3263  }
3264  }
3265
3266  FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3267
3268  for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3269    SelectBasicBlock(I, MF, FuncInfo);
3270
3271  return true;
3272}
3273
3274
3275SDOperand SelectionDAGISel::
3276CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3277  SDOperand Op = SDL.getValue(V);
3278  assert((Op.getOpcode() != ISD::CopyFromReg ||
3279          cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3280         "Copy from a reg to the same reg!");
3281
3282  // If this type is not legal, we must make sure to not create an invalid
3283  // register use.
3284  MVT::ValueType SrcVT = Op.getValueType();
3285  MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3286  SelectionDAG &DAG = SDL.DAG;
3287  if (SrcVT == DestVT) {
3288    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3289  } else if (SrcVT == MVT::Vector) {
3290    // Handle copies from generic vectors to registers.
3291    MVT::ValueType PTyElementVT, PTyLegalElementVT;
3292    unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3293                                             PTyElementVT, PTyLegalElementVT);
3294
3295    // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3296    // MVT::Vector type.
3297    Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3298                     DAG.getConstant(NE, MVT::i32),
3299                     DAG.getValueType(PTyElementVT));
3300
3301    // Loop over all of the elements of the resultant vector,
3302    // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3303    // copying them into output registers.
3304    SmallVector<SDOperand, 8> OutChains;
3305    SDOperand Root = SDL.getRoot();
3306    for (unsigned i = 0; i != NE; ++i) {
3307      SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3308                                  Op, DAG.getConstant(i, TLI.getPointerTy()));
3309      if (PTyElementVT == PTyLegalElementVT) {
3310        // Elements are legal.
3311        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3312      } else if (PTyLegalElementVT > PTyElementVT) {
3313        // Elements are promoted.
3314        if (MVT::isFloatingPoint(PTyLegalElementVT))
3315          Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3316        else
3317          Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3318        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3319      } else {
3320        // Elements are expanded.
3321        // The src value is expanded into multiple registers.
3322        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3323                                   Elt, DAG.getConstant(0, TLI.getPointerTy()));
3324        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3325                                   Elt, DAG.getConstant(1, TLI.getPointerTy()));
3326        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3327        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3328      }
3329    }
3330    return DAG.getNode(ISD::TokenFactor, MVT::Other,
3331                       &OutChains[0], OutChains.size());
3332  } else if (SrcVT < DestVT) {
3333    // The src value is promoted to the register.
3334    if (MVT::isFloatingPoint(SrcVT))
3335      Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3336    else
3337      Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3338    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3339  } else  {
3340    // The src value is expanded into multiple registers.
3341    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3342                               Op, DAG.getConstant(0, TLI.getPointerTy()));
3343    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3344                               Op, DAG.getConstant(1, TLI.getPointerTy()));
3345    Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3346    return DAG.getCopyToReg(Op, Reg+1, Hi);
3347  }
3348}
3349
3350void SelectionDAGISel::
3351LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3352               std::vector<SDOperand> &UnorderedChains) {
3353  // If this is the entry block, emit arguments.
3354  Function &F = *BB->getParent();
3355  FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3356  SDOperand OldRoot = SDL.DAG.getRoot();
3357  std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3358
3359  unsigned a = 0;
3360  for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3361       AI != E; ++AI, ++a)
3362    if (!AI->use_empty()) {
3363      SDL.setValue(AI, Args[a]);
3364
3365      // If this argument is live outside of the entry block, insert a copy from
3366      // whereever we got it to the vreg that other BB's will reference it as.
3367      if (FuncInfo.ValueMap.count(AI)) {
3368        SDOperand Copy =
3369          CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3370        UnorderedChains.push_back(Copy);
3371      }
3372    }
3373
3374  // Finally, if the target has anything special to do, allow it to do so.
3375  // FIXME: this should insert code into the DAG!
3376  EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3377}
3378
3379void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3380       std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3381                                         FunctionLoweringInfo &FuncInfo) {
3382  SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3383
3384  std::vector<SDOperand> UnorderedChains;
3385
3386  // Lower any arguments needed in this block if this is the entry block.
3387  if (LLVMBB == &LLVMBB->getParent()->front())
3388    LowerArguments(LLVMBB, SDL, UnorderedChains);
3389
3390  BB = FuncInfo.MBBMap[LLVMBB];
3391  SDL.setCurrentBasicBlock(BB);
3392
3393  // Lower all of the non-terminator instructions.
3394  for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3395       I != E; ++I)
3396    SDL.visit(*I);
3397
3398  // Ensure that all instructions which are used outside of their defining
3399  // blocks are available as virtual registers.
3400  for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3401    if (!I->use_empty() && !isa<PHINode>(I)) {
3402      std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3403      if (VMI != FuncInfo.ValueMap.end())
3404        UnorderedChains.push_back(
3405                           CopyValueToVirtualRegister(SDL, I, VMI->second));
3406    }
3407
3408  // Handle PHI nodes in successor blocks.  Emit code into the SelectionDAG to
3409  // ensure constants are generated when needed.  Remember the virtual registers
3410  // that need to be added to the Machine PHI nodes as input.  We cannot just
3411  // directly add them, because expansion might result in multiple MBB's for one
3412  // BB.  As such, the start of the BB might correspond to a different MBB than
3413  // the end.
3414  //
3415
3416  // Emit constants only once even if used by multiple PHI nodes.
3417  std::map<Constant*, unsigned> ConstantsOut;
3418
3419  // Check successor nodes PHI nodes that expect a constant to be available from
3420  // this block.
3421  TerminatorInst *TI = LLVMBB->getTerminator();
3422  for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3423    BasicBlock *SuccBB = TI->getSuccessor(succ);
3424    if (!isa<PHINode>(SuccBB->begin())) continue;
3425
3426    MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3427    PHINode *PN;
3428
3429    // At this point we know that there is a 1-1 correspondence between LLVM PHI
3430    // nodes and Machine PHI nodes, but the incoming operands have not been
3431    // emitted yet.
3432    for (BasicBlock::iterator I = SuccBB->begin();
3433         (PN = dyn_cast<PHINode>(I)); ++I)
3434      if (!PN->use_empty()) {
3435        unsigned Reg;
3436        Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3437        if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3438          unsigned &RegOut = ConstantsOut[C];
3439          if (RegOut == 0) {
3440            RegOut = FuncInfo.CreateRegForValue(C);
3441            UnorderedChains.push_back(
3442                             CopyValueToVirtualRegister(SDL, C, RegOut));
3443          }
3444          Reg = RegOut;
3445        } else {
3446          Reg = FuncInfo.ValueMap[PHIOp];
3447          if (Reg == 0) {
3448            assert(isa<AllocaInst>(PHIOp) &&
3449                   FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3450                   "Didn't codegen value into a register!??");
3451            Reg = FuncInfo.CreateRegForValue(PHIOp);
3452            UnorderedChains.push_back(
3453                             CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3454          }
3455        }
3456
3457        // Remember that this register needs to added to the machine PHI node as
3458        // the input for this MBB.
3459        MVT::ValueType VT = TLI.getValueType(PN->getType());
3460        unsigned NumElements;
3461        if (VT != MVT::Vector)
3462          NumElements = TLI.getNumElements(VT);
3463        else {
3464          MVT::ValueType VT1,VT2;
3465          NumElements =
3466            TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3467                                       VT1, VT2);
3468        }
3469        for (unsigned i = 0, e = NumElements; i != e; ++i)
3470          PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3471      }
3472  }
3473  ConstantsOut.clear();
3474
3475  // Turn all of the unordered chains into one factored node.
3476  if (!UnorderedChains.empty()) {
3477    SDOperand Root = SDL.getRoot();
3478    if (Root.getOpcode() != ISD::EntryToken) {
3479      unsigned i = 0, e = UnorderedChains.size();
3480      for (; i != e; ++i) {
3481        assert(UnorderedChains[i].Val->getNumOperands() > 1);
3482        if (UnorderedChains[i].Val->getOperand(0) == Root)
3483          break;  // Don't add the root if we already indirectly depend on it.
3484      }
3485
3486      if (i == e)
3487        UnorderedChains.push_back(Root);
3488    }
3489    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3490                            &UnorderedChains[0], UnorderedChains.size()));
3491  }
3492
3493  // Lower the terminator after the copies are emitted.
3494  SDL.visit(*LLVMBB->getTerminator());
3495
3496  // Copy over any CaseBlock records that may now exist due to SwitchInst
3497  // lowering, as well as any jump table information.
3498  SwitchCases.clear();
3499  SwitchCases = SDL.SwitchCases;
3500  JT = SDL.JT;
3501
3502  // Make sure the root of the DAG is up-to-date.
3503  DAG.setRoot(SDL.getRoot());
3504}
3505
3506void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3507  // Run the DAG combiner in pre-legalize mode.
3508  DAG.Combine(false);
3509
3510  DEBUG(std::cerr << "Lowered selection DAG:\n");
3511  DEBUG(DAG.dump());
3512
3513  // Second step, hack on the DAG until it only uses operations and types that
3514  // the target supports.
3515  DAG.Legalize();
3516
3517  DEBUG(std::cerr << "Legalized selection DAG:\n");
3518  DEBUG(DAG.dump());
3519
3520  // Run the DAG combiner in post-legalize mode.
3521  DAG.Combine(true);
3522
3523  if (ViewISelDAGs) DAG.viewGraph();
3524
3525  // Third, instruction select all of the operations to machine code, adding the
3526  // code to the MachineBasicBlock.
3527  InstructionSelectBasicBlock(DAG);
3528
3529  DEBUG(std::cerr << "Selected machine code:\n");
3530  DEBUG(BB->dump());
3531}
3532
3533void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3534                                        FunctionLoweringInfo &FuncInfo) {
3535  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3536  {
3537    SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3538    CurDAG = &DAG;
3539
3540    // First step, lower LLVM code to some DAG.  This DAG may use operations and
3541    // types that are not supported by the target.
3542    BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3543
3544    // Second step, emit the lowered DAG as machine code.
3545    CodeGenAndEmitDAG(DAG);
3546  }
3547
3548  // Next, now that we know what the last MBB the LLVM BB expanded is, update
3549  // PHI nodes in successors.
3550  if (SwitchCases.empty() && JT.Reg == 0) {
3551    for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3552      MachineInstr *PHI = PHINodesToUpdate[i].first;
3553      assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3554             "This is not a machine PHI node that we are updating!");
3555      PHI->addRegOperand(PHINodesToUpdate[i].second, false);
3556      PHI->addMachineBasicBlockOperand(BB);
3557    }
3558    return;
3559  }
3560
3561  // If the JumpTable record is filled in, then we need to emit a jump table.
3562  // Updating the PHI nodes is tricky in this case, since we need to determine
3563  // whether the PHI is a successor of the range check MBB or the jump table MBB
3564  if (JT.Reg) {
3565    assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3566    SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3567    CurDAG = &SDAG;
3568    SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3569    MachineBasicBlock *RangeBB = BB;
3570    // Set the current basic block to the mbb we wish to insert the code into
3571    BB = JT.MBB;
3572    SDL.setCurrentBasicBlock(BB);
3573    // Emit the code
3574    SDL.visitJumpTable(JT);
3575    SDAG.setRoot(SDL.getRoot());
3576    CodeGenAndEmitDAG(SDAG);
3577    // Update PHI Nodes
3578    for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3579      MachineInstr *PHI = PHINodesToUpdate[pi].first;
3580      MachineBasicBlock *PHIBB = PHI->getParent();
3581      assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3582             "This is not a machine PHI node that we are updating!");
3583      if (PHIBB == JT.Default) {
3584        PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3585        PHI->addMachineBasicBlockOperand(RangeBB);
3586      }
3587      if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3588        PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3589        PHI->addMachineBasicBlockOperand(BB);
3590      }
3591    }
3592    return;
3593  }
3594
3595  // If we generated any switch lowering information, build and codegen any
3596  // additional DAGs necessary.
3597  for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3598    SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3599    CurDAG = &SDAG;
3600    SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3601
3602    // Set the current basic block to the mbb we wish to insert the code into
3603    BB = SwitchCases[i].ThisBB;
3604    SDL.setCurrentBasicBlock(BB);
3605
3606    // Emit the code
3607    SDL.visitSwitchCase(SwitchCases[i]);
3608    SDAG.setRoot(SDL.getRoot());
3609    CodeGenAndEmitDAG(SDAG);
3610
3611    // Handle any PHI nodes in successors of this chunk, as if we were coming
3612    // from the original BB before switch expansion.  Note that PHI nodes can
3613    // occur multiple times in PHINodesToUpdate.  We have to be very careful to
3614    // handle them the right number of times.
3615    while ((BB = SwitchCases[i].LHSBB)) {  // Handle LHS and RHS.
3616      for (MachineBasicBlock::iterator Phi = BB->begin();
3617           Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
3618        // This value for this PHI node is recorded in PHINodesToUpdate, get it.
3619        for (unsigned pn = 0; ; ++pn) {
3620          assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
3621          if (PHINodesToUpdate[pn].first == Phi) {
3622            Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
3623            Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
3624            break;
3625          }
3626        }
3627      }
3628
3629      // Don't process RHS if same block as LHS.
3630      if (BB == SwitchCases[i].RHSBB)
3631        SwitchCases[i].RHSBB = 0;
3632
3633      // If we haven't handled the RHS, do so now.  Otherwise, we're done.
3634      SwitchCases[i].LHSBB = SwitchCases[i].RHSBB;
3635      SwitchCases[i].RHSBB = 0;
3636    }
3637    assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0);
3638  }
3639}
3640
3641
3642//===----------------------------------------------------------------------===//
3643/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3644/// target node in the graph.
3645void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3646  if (ViewSchedDAGs) DAG.viewGraph();
3647
3648  RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
3649
3650  if (!Ctor) {
3651    Ctor = ISHeuristic;
3652    RegisterScheduler::setDefault(Ctor);
3653  }
3654
3655  ScheduleDAG *SL = Ctor(this, &DAG, BB);
3656  BB = SL->Run();
3657  delete SL;
3658}
3659
3660
3661HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3662  return new HazardRecognizer();
3663}
3664
3665
3666/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3667/// by tblgen.  Others should not call it.
3668void SelectionDAGISel::
3669SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3670  std::vector<SDOperand> InOps;
3671  std::swap(InOps, Ops);
3672
3673  Ops.push_back(InOps[0]);  // input chain.
3674  Ops.push_back(InOps[1]);  // input asm string.
3675
3676  unsigned i = 2, e = InOps.size();
3677  if (InOps[e-1].getValueType() == MVT::Flag)
3678    --e;  // Don't process a flag operand if it is here.
3679
3680  while (i != e) {
3681    unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3682    if ((Flags & 7) != 4 /*MEM*/) {
3683      // Just skip over this operand, copying the operands verbatim.
3684      Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3685      i += (Flags >> 3) + 1;
3686    } else {
3687      assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3688      // Otherwise, this is a memory operand.  Ask the target to select it.
3689      std::vector<SDOperand> SelOps;
3690      if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3691        std::cerr << "Could not match memory address.  Inline asm failure!\n";
3692        exit(1);
3693      }
3694
3695      // Add this to the output node.
3696      Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3697      Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3698      i += 2;
3699    }
3700  }
3701
3702  // Add the flag input back if present.
3703  if (e != InOps.size())
3704    Ops.push_back(InOps.back());
3705}
3706