SelectionDAGISel.cpp revision c6f00e701e744fdf73508d47ff0cc75817ba8474
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322MachineBasicBlock * 323SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 324 const BasicBlock *LLVMBB, 325 BasicBlock::const_iterator Begin, 326 BasicBlock::const_iterator End, 327 bool &HadTailCall) { 328 // Lower all of the non-terminator instructions. If a call is emitted 329 // as a tail call, cease emitting nodes for this block. Terminators 330 // are handled below. 331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 332 SDB->visit(*I); 333 334 // Make sure the root of the DAG is up-to-date. 335 CurDAG->setRoot(SDB->getControlRoot()); 336 HadTailCall = SDB->HasTailCall; 337 SDB->clear(); 338 339 // Final step, emit the lowered DAG as machine code. 340 return CodeGenAndEmitDAG(BB); 341} 342 343namespace { 344/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 345/// nodes from the worklist. 346class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 347 SmallVector<SDNode*, 128> &Worklist; 348 SmallPtrSet<SDNode*, 128> &InWorklist; 349public: 350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 351 SmallPtrSet<SDNode*, 128> &inwl) 352 : Worklist(wl), InWorklist(inwl) {} 353 354 void RemoveFromWorklist(SDNode *N) { 355 if (!InWorklist.erase(N)) return; 356 357 SmallVector<SDNode*, 128>::iterator I = 358 std::find(Worklist.begin(), Worklist.end(), N); 359 assert(I != Worklist.end() && "Not in worklist"); 360 361 *I = Worklist.back(); 362 Worklist.pop_back(); 363 } 364 365 virtual void NodeDeleted(SDNode *N, SDNode *E) { 366 RemoveFromWorklist(N); 367 } 368 369 virtual void NodeUpdated(SDNode *N) { 370 // Ignore updates. 371 } 372}; 373} 374 375void SelectionDAGISel::ComputeLiveOutVRegInfo() { 376 SmallPtrSet<SDNode*, 128> VisitedNodes; 377 SmallVector<SDNode*, 128> Worklist; 378 379 Worklist.push_back(CurDAG->getRoot().getNode()); 380 381 APInt Mask; 382 APInt KnownZero; 383 APInt KnownOne; 384 385 do { 386 SDNode *N = Worklist.pop_back_val(); 387 388 // If we've already seen this node, ignore it. 389 if (!VisitedNodes.insert(N)) 390 continue; 391 392 // Otherwise, add all chain operands to the worklist. 393 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 394 if (N->getOperand(i).getValueType() == MVT::Other) 395 Worklist.push_back(N->getOperand(i).getNode()); 396 397 // If this is a CopyToReg with a vreg dest, process it. 398 if (N->getOpcode() != ISD::CopyToReg) 399 continue; 400 401 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 402 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 403 continue; 404 405 // Ignore non-scalar or non-integer values. 406 SDValue Src = N->getOperand(2); 407 EVT SrcVT = Src.getValueType(); 408 if (!SrcVT.isInteger() || SrcVT.isVector()) 409 continue; 410 411 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 412 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 413 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 414 415 // Only install this information if it tells us something. 416 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 417 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 418 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 419 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 420 FunctionLoweringInfo::LiveOutInfo &LOI = 421 FuncInfo->LiveOutRegInfo[DestReg]; 422 LOI.NumSignBits = NumSignBits; 423 LOI.KnownOne = KnownOne; 424 LOI.KnownZero = KnownZero; 425 } 426 } while (!Worklist.empty()); 427} 428 429MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 430 std::string GroupName; 431 if (TimePassesIsEnabled) 432 GroupName = "Instruction Selection and Scheduling"; 433 std::string BlockName; 434 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 435 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 436 ViewSUnitDAGs) 437 BlockName = MF->getFunction()->getNameStr() + ":" + 438 BB->getBasicBlock()->getNameStr(); 439 440 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 441 442 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 443 444 // Run the DAG combiner in pre-legalize mode. 445 { 446 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 447 CurDAG->Combine(Unrestricted, *AA, OptLevel); 448 } 449 450 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 451 452 // Second step, hack on the DAG until it only uses operations and types that 453 // the target supports. 454 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 455 BlockName); 456 457 bool Changed; 458 { 459 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 460 Changed = CurDAG->LegalizeTypes(); 461 } 462 463 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 464 465 if (Changed) { 466 if (ViewDAGCombineLT) 467 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 468 469 // Run the DAG combiner in post-type-legalize mode. 470 { 471 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 472 TimePassesIsEnabled); 473 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 474 } 475 476 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 477 CurDAG->dump()); 478 } 479 480 { 481 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 482 Changed = CurDAG->LegalizeVectors(); 483 } 484 485 if (Changed) { 486 { 487 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 488 CurDAG->LegalizeTypes(); 489 } 490 491 if (ViewDAGCombineLT) 492 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 493 494 // Run the DAG combiner in post-type-legalize mode. 495 { 496 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 497 TimePassesIsEnabled); 498 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 499 } 500 501 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 502 CurDAG->dump()); 503 } 504 505 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 506 507 { 508 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 509 CurDAG->Legalize(OptLevel); 510 } 511 512 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 513 514 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 515 516 // Run the DAG combiner in post-legalize mode. 517 { 518 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 519 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 520 } 521 522 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 523 524 if (OptLevel != CodeGenOpt::None) 525 ComputeLiveOutVRegInfo(); 526 527 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 528 529 // Third, instruction select all of the operations to machine code, adding the 530 // code to the MachineBasicBlock. 531 { 532 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 533 DoInstructionSelection(); 534 } 535 536 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 537 538 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 539 540 // Schedule machine code. 541 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 542 { 543 NamedRegionTimer T("Instruction Scheduling", GroupName, 544 TimePassesIsEnabled); 545 Scheduler->Run(CurDAG, BB, BB->end()); 546 } 547 548 if (ViewSUnitDAGs) Scheduler->viewGraph(); 549 550 // Emit machine code to BB. This can change 'BB' to the last block being 551 // inserted into. 552 { 553 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 554 BB = Scheduler->EmitSchedule(); 555 } 556 557 // Free the scheduler state. 558 { 559 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 560 TimePassesIsEnabled); 561 delete Scheduler; 562 } 563 564 // Free the SelectionDAG state, now that we're finished with it. 565 CurDAG->clear(); 566 567 return BB; 568} 569 570void SelectionDAGISel::DoInstructionSelection() { 571 DEBUG(errs() << "===== Instruction selection begins:\n"); 572 573 PreprocessISelDAG(); 574 575 // Select target instructions for the DAG. 576 { 577 // Number all nodes with a topological order and set DAGSize. 578 DAGSize = CurDAG->AssignTopologicalOrder(); 579 580 // Create a dummy node (which is not added to allnodes), that adds 581 // a reference to the root node, preventing it from being deleted, 582 // and tracking any changes of the root. 583 HandleSDNode Dummy(CurDAG->getRoot()); 584 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 585 ++ISelPosition; 586 587 // The AllNodes list is now topological-sorted. Visit the 588 // nodes by starting at the end of the list (the root of the 589 // graph) and preceding back toward the beginning (the entry 590 // node). 591 while (ISelPosition != CurDAG->allnodes_begin()) { 592 SDNode *Node = --ISelPosition; 593 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 594 // but there are currently some corner cases that it misses. Also, this 595 // makes it theoretically possible to disable the DAGCombiner. 596 if (Node->use_empty()) 597 continue; 598 599 SDNode *ResNode = Select(Node); 600 601 // FIXME: This is pretty gross. 'Select' should be changed to not return 602 // anything at all and this code should be nuked with a tactical strike. 603 604 // If node should not be replaced, continue with the next one. 605 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 606 continue; 607 // Replace node. 608 if (ResNode) 609 ReplaceUses(Node, ResNode); 610 611 // If after the replacement this node is not used any more, 612 // remove this dead node. 613 if (Node->use_empty()) { // Don't delete EntryToken, etc. 614 ISelUpdater ISU(ISelPosition); 615 CurDAG->RemoveDeadNode(Node, &ISU); 616 } 617 } 618 619 CurDAG->setRoot(Dummy.getValue()); 620 } 621 622 DEBUG(errs() << "===== Instruction selection ends:\n"); 623 624 PostprocessISelDAG(); 625} 626 627/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 628/// do other setup for EH landing-pad blocks. 629void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 630 // Add a label to mark the beginning of the landing pad. Deletion of the 631 // landing pad can thus be detected via the MachineModuleInfo. 632 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 633 634 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 635 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 636 637 // Mark exception register as live in. 638 unsigned Reg = TLI.getExceptionAddressRegister(); 639 if (Reg) BB->addLiveIn(Reg); 640 641 // Mark exception selector register as live in. 642 Reg = TLI.getExceptionSelectorRegister(); 643 if (Reg) BB->addLiveIn(Reg); 644 645 // FIXME: Hack around an exception handling flaw (PR1508): the personality 646 // function and list of typeids logically belong to the invoke (or, if you 647 // like, the basic block containing the invoke), and need to be associated 648 // with it in the dwarf exception handling tables. Currently however the 649 // information is provided by an intrinsic (eh.selector) that can be moved 650 // to unexpected places by the optimizers: if the unwind edge is critical, 651 // then breaking it can result in the intrinsics being in the successor of 652 // the landing pad, not the landing pad itself. This results 653 // in exceptions not being caught because no typeids are associated with 654 // the invoke. This may not be the only way things can go wrong, but it 655 // is the only way we try to work around for the moment. 656 const BasicBlock *LLVMBB = BB->getBasicBlock(); 657 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 658 659 if (Br && Br->isUnconditional()) { // Critical edge? 660 BasicBlock::const_iterator I, E; 661 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 662 if (isa<EHSelectorInst>(I)) 663 break; 664 665 if (I == E) 666 // No catch info found - try to extract some from the successor. 667 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 668 } 669} 670 671void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 672 // Initialize the Fast-ISel state, if needed. 673 FastISel *FastIS = 0; 674 if (EnableFastISel) 675 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 676 FuncInfo->StaticAllocaMap, 677 FuncInfo->PHINodesToUpdate 678#ifndef NDEBUG 679 , FuncInfo->CatchInfoLost 680#endif 681 ); 682 683 // Iterate over all basic blocks in the function. 684 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 685 const BasicBlock *LLVMBB = &*I; 686 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 687 688 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 689 BasicBlock::const_iterator const End = LLVMBB->end(); 690 BasicBlock::const_iterator BI = Begin; 691 692 // Lower any arguments needed in this block if this is the entry block. 693 if (LLVMBB == &Fn.getEntryBlock()) 694 LowerArguments(LLVMBB); 695 696 // Setup an EH landing-pad block. 697 if (BB->isLandingPad()) 698 PrepareEHLandingPad(BB); 699 700 // Before doing SelectionDAG ISel, see if FastISel has been requested. 701 if (FastIS) { 702 // Emit code for any incoming arguments. This must happen before 703 // beginning FastISel on the entry block. 704 if (LLVMBB == &Fn.getEntryBlock()) { 705 CurDAG->setRoot(SDB->getControlRoot()); 706 SDB->clear(); 707 BB = CodeGenAndEmitDAG(BB); 708 } 709 FastIS->startNewBlock(BB); 710 // Do FastISel on as many instructions as possible. 711 for (; BI != End; ++BI) { 712 // Defer instructions with no side effects; they'll be emitted 713 // on-demand later. 714 if (BI->isSafeToSpeculativelyExecute() && 715 !FuncInfo->isExportedInst(BI)) 716 continue; 717 718 // Try to select the instruction with FastISel. 719 if (FastIS->SelectInstruction(BI)) 720 continue; 721 722 // Then handle certain instructions as single-LLVM-Instruction blocks. 723 if (isa<CallInst>(BI)) { 724 ++NumFastIselFailures; 725 if (EnableFastISelVerbose || EnableFastISelAbort) { 726 dbgs() << "FastISel missed call: "; 727 BI->dump(); 728 } 729 730 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 731 unsigned &R = FuncInfo->ValueMap[BI]; 732 if (!R) 733 R = FuncInfo->CreateReg(BI->getType()); 734 } 735 736 bool HadTailCall = false; 737 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 738 739 // If the call was emitted as a tail call, we're done with the block. 740 if (HadTailCall) { 741 BI = End; 742 break; 743 } 744 745 // If the instruction was codegen'd with multiple blocks, 746 // inform the FastISel object where to resume inserting. 747 FastIS->setCurrentBlock(BB); 748 continue; 749 } 750 751 // Otherwise, give up on FastISel for the rest of the block. 752 // For now, be a little lenient about non-branch terminators. 753 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 754 ++NumFastIselFailures; 755 if (EnableFastISelVerbose || EnableFastISelAbort) { 756 dbgs() << "FastISel miss: "; 757 BI->dump(); 758 } 759 if (EnableFastISelAbort) 760 // The "fast" selector couldn't handle something and bailed. 761 // For the purpose of debugging, just abort. 762 llvm_unreachable("FastISel didn't select the entire block"); 763 } 764 break; 765 } 766 } 767 768 // Run SelectionDAG instruction selection on the remainder of the block 769 // not handled by FastISel. If FastISel is not run, this is the entire 770 // block. 771 if (BI != End) { 772 bool HadTailCall; 773 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 774 } 775 776 FinishBasicBlock(BB); 777 FuncInfo->PHINodesToUpdate.clear(); 778 } 779 780 delete FastIS; 781} 782 783void 784SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 785 786 DEBUG(dbgs() << "Total amount of phi nodes to update: " 787 << FuncInfo->PHINodesToUpdate.size() << "\n"; 788 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 789 dbgs() << "Node " << i << " : (" 790 << FuncInfo->PHINodesToUpdate[i].first 791 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 792 793 // Next, now that we know what the last MBB the LLVM BB expanded is, update 794 // PHI nodes in successors. 795 if (SDB->SwitchCases.empty() && 796 SDB->JTCases.empty() && 797 SDB->BitTestCases.empty()) { 798 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 799 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 800 assert(PHI->isPHI() && 801 "This is not a machine PHI node that we are updating!"); 802 if (!BB->isSuccessor(PHI->getParent())) 803 continue; 804 PHI->addOperand( 805 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 806 PHI->addOperand(MachineOperand::CreateMBB(BB)); 807 } 808 return; 809 } 810 811 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 812 // Lower header first, if it wasn't already lowered 813 if (!SDB->BitTestCases[i].Emitted) { 814 // Set the current basic block to the mbb we wish to insert the code into 815 BB = SDB->BitTestCases[i].Parent; 816 // Emit the code 817 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 818 CurDAG->setRoot(SDB->getRoot()); 819 SDB->clear(); 820 BB = CodeGenAndEmitDAG(BB); 821 } 822 823 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 824 // Set the current basic block to the mbb we wish to insert the code into 825 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 826 // Emit the code 827 if (j+1 != ej) 828 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 829 SDB->BitTestCases[i].Reg, 830 SDB->BitTestCases[i].Cases[j], 831 BB); 832 else 833 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 834 SDB->BitTestCases[i].Reg, 835 SDB->BitTestCases[i].Cases[j], 836 BB); 837 838 839 CurDAG->setRoot(SDB->getRoot()); 840 SDB->clear(); 841 BB = CodeGenAndEmitDAG(BB); 842 } 843 844 // Update PHI Nodes 845 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 846 pi != pe; ++pi) { 847 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 848 MachineBasicBlock *PHIBB = PHI->getParent(); 849 assert(PHI->isPHI() && 850 "This is not a machine PHI node that we are updating!"); 851 // This is "default" BB. We have two jumps to it. From "header" BB and 852 // from last "case" BB. 853 if (PHIBB == SDB->BitTestCases[i].Default) { 854 PHI->addOperand(MachineOperand:: 855 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 856 false)); 857 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 858 PHI->addOperand(MachineOperand:: 859 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 860 false)); 861 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 862 back().ThisBB)); 863 } 864 // One of "cases" BB. 865 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 866 j != ej; ++j) { 867 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 868 if (cBB->isSuccessor(PHIBB)) { 869 PHI->addOperand(MachineOperand:: 870 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 871 false)); 872 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 873 } 874 } 875 } 876 } 877 SDB->BitTestCases.clear(); 878 879 // If the JumpTable record is filled in, then we need to emit a jump table. 880 // Updating the PHI nodes is tricky in this case, since we need to determine 881 // whether the PHI is a successor of the range check MBB or the jump table MBB 882 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 883 // Lower header first, if it wasn't already lowered 884 if (!SDB->JTCases[i].first.Emitted) { 885 // Set the current basic block to the mbb we wish to insert the code into 886 BB = SDB->JTCases[i].first.HeaderBB; 887 // Emit the code 888 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 889 BB); 890 CurDAG->setRoot(SDB->getRoot()); 891 SDB->clear(); 892 BB = CodeGenAndEmitDAG(BB); 893 } 894 895 // Set the current basic block to the mbb we wish to insert the code into 896 BB = SDB->JTCases[i].second.MBB; 897 // Emit the code 898 SDB->visitJumpTable(SDB->JTCases[i].second); 899 CurDAG->setRoot(SDB->getRoot()); 900 SDB->clear(); 901 BB = CodeGenAndEmitDAG(BB); 902 903 // Update PHI Nodes 904 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 905 pi != pe; ++pi) { 906 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 907 MachineBasicBlock *PHIBB = PHI->getParent(); 908 assert(PHI->isPHI() && 909 "This is not a machine PHI node that we are updating!"); 910 // "default" BB. We can go there only from header BB. 911 if (PHIBB == SDB->JTCases[i].second.Default) { 912 PHI->addOperand 913 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 914 false)); 915 PHI->addOperand 916 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 917 } 918 // JT BB. Just iterate over successors here 919 if (BB->isSuccessor(PHIBB)) { 920 PHI->addOperand 921 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 922 false)); 923 PHI->addOperand(MachineOperand::CreateMBB(BB)); 924 } 925 } 926 } 927 SDB->JTCases.clear(); 928 929 // If the switch block involved a branch to one of the actual successors, we 930 // need to update PHI nodes in that block. 931 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 932 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 933 assert(PHI->isPHI() && 934 "This is not a machine PHI node that we are updating!"); 935 if (BB->isSuccessor(PHI->getParent())) { 936 PHI->addOperand( 937 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 938 PHI->addOperand(MachineOperand::CreateMBB(BB)); 939 } 940 } 941 942 // If we generated any switch lowering information, build and codegen any 943 // additional DAGs necessary. 944 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 945 // Set the current basic block to the mbb we wish to insert the code into 946 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 947 948 // Determine the unique successors. 949 SmallVector<MachineBasicBlock *, 2> Succs; 950 Succs.push_back(SDB->SwitchCases[i].TrueBB); 951 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 952 Succs.push_back(SDB->SwitchCases[i].FalseBB); 953 954 // Emit the code. Note that this could result in ThisBB being split, so 955 // we need to check for updates. 956 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 957 CurDAG->setRoot(SDB->getRoot()); 958 SDB->clear(); 959 ThisBB = CodeGenAndEmitDAG(BB); 960 961 // Handle any PHI nodes in successors of this chunk, as if we were coming 962 // from the original BB before switch expansion. Note that PHI nodes can 963 // occur multiple times in PHINodesToUpdate. We have to be very careful to 964 // handle them the right number of times. 965 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 966 BB = Succs[i]; 967 // BB may have been removed from the CFG if a branch was constant folded. 968 if (ThisBB->isSuccessor(BB)) { 969 for (MachineBasicBlock::iterator Phi = BB->begin(); 970 Phi != BB->end() && Phi->isPHI(); 971 ++Phi) { 972 // This value for this PHI node is recorded in PHINodesToUpdate. 973 for (unsigned pn = 0; ; ++pn) { 974 assert(pn != FuncInfo->PHINodesToUpdate.size() && 975 "Didn't find PHI entry!"); 976 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 977 Phi->addOperand(MachineOperand:: 978 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 979 false)); 980 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 981 break; 982 } 983 } 984 } 985 } 986 } 987 } 988 SDB->SwitchCases.clear(); 989} 990 991 992/// Create the scheduler. If a specific scheduler was specified 993/// via the SchedulerRegistry, use it, otherwise select the 994/// one preferred by the target. 995/// 996ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 997 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 998 999 if (!Ctor) { 1000 Ctor = ISHeuristic; 1001 RegisterScheduler::setDefault(Ctor); 1002 } 1003 1004 return Ctor(this, OptLevel); 1005} 1006 1007ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1008 return new ScheduleHazardRecognizer(); 1009} 1010 1011//===----------------------------------------------------------------------===// 1012// Helper functions used by the generated instruction selector. 1013//===----------------------------------------------------------------------===// 1014// Calls to these methods are generated by tblgen. 1015 1016/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1017/// the dag combiner simplified the 255, we still want to match. RHS is the 1018/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1019/// specified in the .td file (e.g. 255). 1020bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1021 int64_t DesiredMaskS) const { 1022 const APInt &ActualMask = RHS->getAPIntValue(); 1023 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1024 1025 // If the actual mask exactly matches, success! 1026 if (ActualMask == DesiredMask) 1027 return true; 1028 1029 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1030 if (ActualMask.intersects(~DesiredMask)) 1031 return false; 1032 1033 // Otherwise, the DAG Combiner may have proven that the value coming in is 1034 // either already zero or is not demanded. Check for known zero input bits. 1035 APInt NeededMask = DesiredMask & ~ActualMask; 1036 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1037 return true; 1038 1039 // TODO: check to see if missing bits are just not demanded. 1040 1041 // Otherwise, this pattern doesn't match. 1042 return false; 1043} 1044 1045/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1046/// the dag combiner simplified the 255, we still want to match. RHS is the 1047/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1048/// specified in the .td file (e.g. 255). 1049bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1050 int64_t DesiredMaskS) const { 1051 const APInt &ActualMask = RHS->getAPIntValue(); 1052 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1053 1054 // If the actual mask exactly matches, success! 1055 if (ActualMask == DesiredMask) 1056 return true; 1057 1058 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1059 if (ActualMask.intersects(~DesiredMask)) 1060 return false; 1061 1062 // Otherwise, the DAG Combiner may have proven that the value coming in is 1063 // either already zero or is not demanded. Check for known zero input bits. 1064 APInt NeededMask = DesiredMask & ~ActualMask; 1065 1066 APInt KnownZero, KnownOne; 1067 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1068 1069 // If all the missing bits in the or are already known to be set, match! 1070 if ((NeededMask & KnownOne) == NeededMask) 1071 return true; 1072 1073 // TODO: check to see if missing bits are just not demanded. 1074 1075 // Otherwise, this pattern doesn't match. 1076 return false; 1077} 1078 1079 1080/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1081/// by tblgen. Others should not call it. 1082void SelectionDAGISel:: 1083SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1084 std::vector<SDValue> InOps; 1085 std::swap(InOps, Ops); 1086 1087 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1088 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1089 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1090 1091 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1092 if (InOps[e-1].getValueType() == MVT::Flag) 1093 --e; // Don't process a flag operand if it is here. 1094 1095 while (i != e) { 1096 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1097 if (!InlineAsm::isMemKind(Flags)) { 1098 // Just skip over this operand, copying the operands verbatim. 1099 Ops.insert(Ops.end(), InOps.begin()+i, 1100 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1101 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1102 } else { 1103 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1104 "Memory operand with multiple values?"); 1105 // Otherwise, this is a memory operand. Ask the target to select it. 1106 std::vector<SDValue> SelOps; 1107 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1108 report_fatal_error("Could not match memory address. Inline asm" 1109 " failure!"); 1110 1111 // Add this to the output node. 1112 unsigned NewFlags = 1113 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1114 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1115 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1116 i += 2; 1117 } 1118 } 1119 1120 // Add the flag input back if present. 1121 if (e != InOps.size()) 1122 Ops.push_back(InOps.back()); 1123} 1124 1125/// findFlagUse - Return use of EVT::Flag value produced by the specified 1126/// SDNode. 1127/// 1128static SDNode *findFlagUse(SDNode *N) { 1129 unsigned FlagResNo = N->getNumValues()-1; 1130 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1131 SDUse &Use = I.getUse(); 1132 if (Use.getResNo() == FlagResNo) 1133 return Use.getUser(); 1134 } 1135 return NULL; 1136} 1137 1138/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1139/// This function recursively traverses up the operand chain, ignoring 1140/// certain nodes. 1141static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1142 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1143 bool IgnoreChains) { 1144 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1145 // greater than all of its (recursive) operands. If we scan to a point where 1146 // 'use' is smaller than the node we're scanning for, then we know we will 1147 // never find it. 1148 // 1149 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1150 // happen because we scan down to newly selected nodes in the case of flag 1151 // uses. 1152 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1153 return false; 1154 1155 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1156 // won't fail if we scan it again. 1157 if (!Visited.insert(Use)) 1158 return false; 1159 1160 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1161 // Ignore chain uses, they are validated by HandleMergeInputChains. 1162 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1163 continue; 1164 1165 SDNode *N = Use->getOperand(i).getNode(); 1166 if (N == Def) { 1167 if (Use == ImmedUse || Use == Root) 1168 continue; // We are not looking for immediate use. 1169 assert(N != Root); 1170 return true; 1171 } 1172 1173 // Traverse up the operand chain. 1174 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1175 return true; 1176 } 1177 return false; 1178} 1179 1180/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1181/// operand node N of U during instruction selection that starts at Root. 1182bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1183 SDNode *Root) const { 1184 if (OptLevel == CodeGenOpt::None) return false; 1185 return N.hasOneUse(); 1186} 1187 1188/// IsLegalToFold - Returns true if the specific operand node N of 1189/// U can be folded during instruction selection that starts at Root. 1190bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1191 CodeGenOpt::Level OptLevel, 1192 bool IgnoreChains) { 1193 if (OptLevel == CodeGenOpt::None) return false; 1194 1195 // If Root use can somehow reach N through a path that that doesn't contain 1196 // U then folding N would create a cycle. e.g. In the following 1197 // diagram, Root can reach N through X. If N is folded into into Root, then 1198 // X is both a predecessor and a successor of U. 1199 // 1200 // [N*] // 1201 // ^ ^ // 1202 // / \ // 1203 // [U*] [X]? // 1204 // ^ ^ // 1205 // \ / // 1206 // \ / // 1207 // [Root*] // 1208 // 1209 // * indicates nodes to be folded together. 1210 // 1211 // If Root produces a flag, then it gets (even more) interesting. Since it 1212 // will be "glued" together with its flag use in the scheduler, we need to 1213 // check if it might reach N. 1214 // 1215 // [N*] // 1216 // ^ ^ // 1217 // / \ // 1218 // [U*] [X]? // 1219 // ^ ^ // 1220 // \ \ // 1221 // \ | // 1222 // [Root*] | // 1223 // ^ | // 1224 // f | // 1225 // | / // 1226 // [Y] / // 1227 // ^ / // 1228 // f / // 1229 // | / // 1230 // [FU] // 1231 // 1232 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1233 // (call it Fold), then X is a predecessor of FU and a successor of 1234 // Fold. But since Fold and FU are flagged together, this will create 1235 // a cycle in the scheduling graph. 1236 1237 // If the node has flags, walk down the graph to the "lowest" node in the 1238 // flagged set. 1239 EVT VT = Root->getValueType(Root->getNumValues()-1); 1240 while (VT == MVT::Flag) { 1241 SDNode *FU = findFlagUse(Root); 1242 if (FU == NULL) 1243 break; 1244 Root = FU; 1245 VT = Root->getValueType(Root->getNumValues()-1); 1246 1247 // If our query node has a flag result with a use, we've walked up it. If 1248 // the user (which has already been selected) has a chain or indirectly uses 1249 // the chain, our WalkChainUsers predicate will not consider it. Because of 1250 // this, we cannot ignore chains in this predicate. 1251 IgnoreChains = false; 1252 } 1253 1254 1255 SmallPtrSet<SDNode*, 16> Visited; 1256 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1257} 1258 1259SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1260 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1261 SelectInlineAsmMemoryOperands(Ops); 1262 1263 std::vector<EVT> VTs; 1264 VTs.push_back(MVT::Other); 1265 VTs.push_back(MVT::Flag); 1266 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1267 VTs, &Ops[0], Ops.size()); 1268 New->setNodeId(-1); 1269 return New.getNode(); 1270} 1271 1272SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1273 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1274} 1275 1276/// GetVBR - decode a vbr encoding whose top bit is set. 1277ALWAYS_INLINE static uint64_t 1278GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1279 assert(Val >= 128 && "Not a VBR"); 1280 Val &= 127; // Remove first vbr bit. 1281 1282 unsigned Shift = 7; 1283 uint64_t NextBits; 1284 do { 1285 NextBits = MatcherTable[Idx++]; 1286 Val |= (NextBits&127) << Shift; 1287 Shift += 7; 1288 } while (NextBits & 128); 1289 1290 return Val; 1291} 1292 1293 1294/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1295/// interior flag and chain results to use the new flag and chain results. 1296void SelectionDAGISel:: 1297UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1298 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1299 SDValue InputFlag, 1300 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1301 bool isMorphNodeTo) { 1302 SmallVector<SDNode*, 4> NowDeadNodes; 1303 1304 ISelUpdater ISU(ISelPosition); 1305 1306 // Now that all the normal results are replaced, we replace the chain and 1307 // flag results if present. 1308 if (!ChainNodesMatched.empty()) { 1309 assert(InputChain.getNode() != 0 && 1310 "Matched input chains but didn't produce a chain"); 1311 // Loop over all of the nodes we matched that produced a chain result. 1312 // Replace all the chain results with the final chain we ended up with. 1313 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1314 SDNode *ChainNode = ChainNodesMatched[i]; 1315 1316 // If this node was already deleted, don't look at it. 1317 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1318 continue; 1319 1320 // Don't replace the results of the root node if we're doing a 1321 // MorphNodeTo. 1322 if (ChainNode == NodeToMatch && isMorphNodeTo) 1323 continue; 1324 1325 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1326 if (ChainVal.getValueType() == MVT::Flag) 1327 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1328 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1329 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1330 1331 // If the node became dead and we haven't already seen it, delete it. 1332 if (ChainNode->use_empty() && 1333 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1334 NowDeadNodes.push_back(ChainNode); 1335 } 1336 } 1337 1338 // If the result produces a flag, update any flag results in the matched 1339 // pattern with the flag result. 1340 if (InputFlag.getNode() != 0) { 1341 // Handle any interior nodes explicitly marked. 1342 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1343 SDNode *FRN = FlagResultNodesMatched[i]; 1344 1345 // If this node was already deleted, don't look at it. 1346 if (FRN->getOpcode() == ISD::DELETED_NODE) 1347 continue; 1348 1349 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1350 "Doesn't have a flag result"); 1351 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1352 InputFlag, &ISU); 1353 1354 // If the node became dead and we haven't already seen it, delete it. 1355 if (FRN->use_empty() && 1356 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1357 NowDeadNodes.push_back(FRN); 1358 } 1359 } 1360 1361 if (!NowDeadNodes.empty()) 1362 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1363 1364 DEBUG(errs() << "ISEL: Match complete!\n"); 1365} 1366 1367enum ChainResult { 1368 CR_Simple, 1369 CR_InducesCycle, 1370 CR_LeadsToInteriorNode 1371}; 1372 1373/// WalkChainUsers - Walk down the users of the specified chained node that is 1374/// part of the pattern we're matching, looking at all of the users we find. 1375/// This determines whether something is an interior node, whether we have a 1376/// non-pattern node in between two pattern nodes (which prevent folding because 1377/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1378/// between pattern nodes (in which case the TF becomes part of the pattern). 1379/// 1380/// The walk we do here is guaranteed to be small because we quickly get down to 1381/// already selected nodes "below" us. 1382static ChainResult 1383WalkChainUsers(SDNode *ChainedNode, 1384 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1385 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1386 ChainResult Result = CR_Simple; 1387 1388 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1389 E = ChainedNode->use_end(); UI != E; ++UI) { 1390 // Make sure the use is of the chain, not some other value we produce. 1391 if (UI.getUse().getValueType() != MVT::Other) continue; 1392 1393 SDNode *User = *UI; 1394 1395 // If we see an already-selected machine node, then we've gone beyond the 1396 // pattern that we're selecting down into the already selected chunk of the 1397 // DAG. 1398 if (User->isMachineOpcode() || 1399 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1400 continue; 1401 1402 if (User->getOpcode() == ISD::CopyToReg || 1403 User->getOpcode() == ISD::CopyFromReg || 1404 User->getOpcode() == ISD::INLINEASM || 1405 User->getOpcode() == ISD::EH_LABEL) { 1406 // If their node ID got reset to -1 then they've already been selected. 1407 // Treat them like a MachineOpcode. 1408 if (User->getNodeId() == -1) 1409 continue; 1410 } 1411 1412 // If we have a TokenFactor, we handle it specially. 1413 if (User->getOpcode() != ISD::TokenFactor) { 1414 // If the node isn't a token factor and isn't part of our pattern, then it 1415 // must be a random chained node in between two nodes we're selecting. 1416 // This happens when we have something like: 1417 // x = load ptr 1418 // call 1419 // y = x+4 1420 // store y -> ptr 1421 // Because we structurally match the load/store as a read/modify/write, 1422 // but the call is chained between them. We cannot fold in this case 1423 // because it would induce a cycle in the graph. 1424 if (!std::count(ChainedNodesInPattern.begin(), 1425 ChainedNodesInPattern.end(), User)) 1426 return CR_InducesCycle; 1427 1428 // Otherwise we found a node that is part of our pattern. For example in: 1429 // x = load ptr 1430 // y = x+4 1431 // store y -> ptr 1432 // This would happen when we're scanning down from the load and see the 1433 // store as a user. Record that there is a use of ChainedNode that is 1434 // part of the pattern and keep scanning uses. 1435 Result = CR_LeadsToInteriorNode; 1436 InteriorChainedNodes.push_back(User); 1437 continue; 1438 } 1439 1440 // If we found a TokenFactor, there are two cases to consider: first if the 1441 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1442 // uses of the TF are in our pattern) we just want to ignore it. Second, 1443 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1444 // [Load chain] 1445 // ^ 1446 // | 1447 // [Load] 1448 // ^ ^ 1449 // | \ DAG's like cheese 1450 // / \ do you? 1451 // / | 1452 // [TokenFactor] [Op] 1453 // ^ ^ 1454 // | | 1455 // \ / 1456 // \ / 1457 // [Store] 1458 // 1459 // In this case, the TokenFactor becomes part of our match and we rewrite it 1460 // as a new TokenFactor. 1461 // 1462 // To distinguish these two cases, do a recursive walk down the uses. 1463 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1464 case CR_Simple: 1465 // If the uses of the TokenFactor are just already-selected nodes, ignore 1466 // it, it is "below" our pattern. 1467 continue; 1468 case CR_InducesCycle: 1469 // If the uses of the TokenFactor lead to nodes that are not part of our 1470 // pattern that are not selected, folding would turn this into a cycle, 1471 // bail out now. 1472 return CR_InducesCycle; 1473 case CR_LeadsToInteriorNode: 1474 break; // Otherwise, keep processing. 1475 } 1476 1477 // Okay, we know we're in the interesting interior case. The TokenFactor 1478 // is now going to be considered part of the pattern so that we rewrite its 1479 // uses (it may have uses that are not part of the pattern) with the 1480 // ultimate chain result of the generated code. We will also add its chain 1481 // inputs as inputs to the ultimate TokenFactor we create. 1482 Result = CR_LeadsToInteriorNode; 1483 ChainedNodesInPattern.push_back(User); 1484 InteriorChainedNodes.push_back(User); 1485 continue; 1486 } 1487 1488 return Result; 1489} 1490 1491/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1492/// operation for when the pattern matched at least one node with a chains. The 1493/// input vector contains a list of all of the chained nodes that we match. We 1494/// must determine if this is a valid thing to cover (i.e. matching it won't 1495/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1496/// be used as the input node chain for the generated nodes. 1497static SDValue 1498HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1499 SelectionDAG *CurDAG) { 1500 // Walk all of the chained nodes we've matched, recursively scanning down the 1501 // users of the chain result. This adds any TokenFactor nodes that are caught 1502 // in between chained nodes to the chained and interior nodes list. 1503 SmallVector<SDNode*, 3> InteriorChainedNodes; 1504 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1505 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1506 InteriorChainedNodes) == CR_InducesCycle) 1507 return SDValue(); // Would induce a cycle. 1508 } 1509 1510 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1511 // that we are interested in. Form our input TokenFactor node. 1512 SmallVector<SDValue, 3> InputChains; 1513 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1514 // Add the input chain of this node to the InputChains list (which will be 1515 // the operands of the generated TokenFactor) if it's not an interior node. 1516 SDNode *N = ChainNodesMatched[i]; 1517 if (N->getOpcode() != ISD::TokenFactor) { 1518 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1519 continue; 1520 1521 // Otherwise, add the input chain. 1522 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1523 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1524 InputChains.push_back(InChain); 1525 continue; 1526 } 1527 1528 // If we have a token factor, we want to add all inputs of the token factor 1529 // that are not part of the pattern we're matching. 1530 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1531 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1532 N->getOperand(op).getNode())) 1533 InputChains.push_back(N->getOperand(op)); 1534 } 1535 } 1536 1537 SDValue Res; 1538 if (InputChains.size() == 1) 1539 return InputChains[0]; 1540 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1541 MVT::Other, &InputChains[0], InputChains.size()); 1542} 1543 1544/// MorphNode - Handle morphing a node in place for the selector. 1545SDNode *SelectionDAGISel:: 1546MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1547 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1548 // It is possible we're using MorphNodeTo to replace a node with no 1549 // normal results with one that has a normal result (or we could be 1550 // adding a chain) and the input could have flags and chains as well. 1551 // In this case we need to shift the operands down. 1552 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1553 // than the old isel though. 1554 int OldFlagResultNo = -1, OldChainResultNo = -1; 1555 1556 unsigned NTMNumResults = Node->getNumValues(); 1557 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1558 OldFlagResultNo = NTMNumResults-1; 1559 if (NTMNumResults != 1 && 1560 Node->getValueType(NTMNumResults-2) == MVT::Other) 1561 OldChainResultNo = NTMNumResults-2; 1562 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1563 OldChainResultNo = NTMNumResults-1; 1564 1565 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1566 // that this deletes operands of the old node that become dead. 1567 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1568 1569 // MorphNodeTo can operate in two ways: if an existing node with the 1570 // specified operands exists, it can just return it. Otherwise, it 1571 // updates the node in place to have the requested operands. 1572 if (Res == Node) { 1573 // If we updated the node in place, reset the node ID. To the isel, 1574 // this should be just like a newly allocated machine node. 1575 Res->setNodeId(-1); 1576 } 1577 1578 unsigned ResNumResults = Res->getNumValues(); 1579 // Move the flag if needed. 1580 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1581 (unsigned)OldFlagResultNo != ResNumResults-1) 1582 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1583 SDValue(Res, ResNumResults-1)); 1584 1585 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1586 --ResNumResults; 1587 1588 // Move the chain reference if needed. 1589 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1590 (unsigned)OldChainResultNo != ResNumResults-1) 1591 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1592 SDValue(Res, ResNumResults-1)); 1593 1594 // Otherwise, no replacement happened because the node already exists. Replace 1595 // Uses of the old node with the new one. 1596 if (Res != Node) 1597 CurDAG->ReplaceAllUsesWith(Node, Res); 1598 1599 return Res; 1600} 1601 1602/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1603ALWAYS_INLINE static bool 1604CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1605 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1606 // Accept if it is exactly the same as a previously recorded node. 1607 unsigned RecNo = MatcherTable[MatcherIndex++]; 1608 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1609 return N == RecordedNodes[RecNo]; 1610} 1611 1612/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1613ALWAYS_INLINE static bool 1614CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1615 SelectionDAGISel &SDISel) { 1616 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1617} 1618 1619/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1620ALWAYS_INLINE static bool 1621CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1622 SelectionDAGISel &SDISel, SDNode *N) { 1623 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1624} 1625 1626ALWAYS_INLINE static bool 1627CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1628 SDNode *N) { 1629 uint16_t Opc = MatcherTable[MatcherIndex++]; 1630 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1631 return N->getOpcode() == Opc; 1632} 1633 1634ALWAYS_INLINE static bool 1635CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1636 SDValue N, const TargetLowering &TLI) { 1637 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1638 if (N.getValueType() == VT) return true; 1639 1640 // Handle the case when VT is iPTR. 1641 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1642} 1643 1644ALWAYS_INLINE static bool 1645CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1646 SDValue N, const TargetLowering &TLI, 1647 unsigned ChildNo) { 1648 if (ChildNo >= N.getNumOperands()) 1649 return false; // Match fails if out of range child #. 1650 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1651} 1652 1653 1654ALWAYS_INLINE static bool 1655CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1656 SDValue N) { 1657 return cast<CondCodeSDNode>(N)->get() == 1658 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1659} 1660 1661ALWAYS_INLINE static bool 1662CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1663 SDValue N, const TargetLowering &TLI) { 1664 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1665 if (cast<VTSDNode>(N)->getVT() == VT) 1666 return true; 1667 1668 // Handle the case when VT is iPTR. 1669 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1670} 1671 1672ALWAYS_INLINE static bool 1673CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1674 SDValue N) { 1675 int64_t Val = MatcherTable[MatcherIndex++]; 1676 if (Val & 128) 1677 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1678 1679 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1680 return C != 0 && C->getSExtValue() == Val; 1681} 1682 1683ALWAYS_INLINE static bool 1684CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1685 SDValue N, SelectionDAGISel &SDISel) { 1686 int64_t Val = MatcherTable[MatcherIndex++]; 1687 if (Val & 128) 1688 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1689 1690 if (N->getOpcode() != ISD::AND) return false; 1691 1692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1693 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1694} 1695 1696ALWAYS_INLINE static bool 1697CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1698 SDValue N, SelectionDAGISel &SDISel) { 1699 int64_t Val = MatcherTable[MatcherIndex++]; 1700 if (Val & 128) 1701 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1702 1703 if (N->getOpcode() != ISD::OR) return false; 1704 1705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1706 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1707} 1708 1709/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1710/// scope, evaluate the current node. If the current predicate is known to 1711/// fail, set Result=true and return anything. If the current predicate is 1712/// known to pass, set Result=false and return the MatcherIndex to continue 1713/// with. If the current predicate is unknown, set Result=false and return the 1714/// MatcherIndex to continue with. 1715static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1716 unsigned Index, SDValue N, 1717 bool &Result, SelectionDAGISel &SDISel, 1718 SmallVectorImpl<SDValue> &RecordedNodes){ 1719 switch (Table[Index++]) { 1720 default: 1721 Result = false; 1722 return Index-1; // Could not evaluate this predicate. 1723 case SelectionDAGISel::OPC_CheckSame: 1724 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1725 return Index; 1726 case SelectionDAGISel::OPC_CheckPatternPredicate: 1727 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1728 return Index; 1729 case SelectionDAGISel::OPC_CheckPredicate: 1730 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1731 return Index; 1732 case SelectionDAGISel::OPC_CheckOpcode: 1733 Result = !::CheckOpcode(Table, Index, N.getNode()); 1734 return Index; 1735 case SelectionDAGISel::OPC_CheckType: 1736 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1737 return Index; 1738 case SelectionDAGISel::OPC_CheckChild0Type: 1739 case SelectionDAGISel::OPC_CheckChild1Type: 1740 case SelectionDAGISel::OPC_CheckChild2Type: 1741 case SelectionDAGISel::OPC_CheckChild3Type: 1742 case SelectionDAGISel::OPC_CheckChild4Type: 1743 case SelectionDAGISel::OPC_CheckChild5Type: 1744 case SelectionDAGISel::OPC_CheckChild6Type: 1745 case SelectionDAGISel::OPC_CheckChild7Type: 1746 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1747 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1748 return Index; 1749 case SelectionDAGISel::OPC_CheckCondCode: 1750 Result = !::CheckCondCode(Table, Index, N); 1751 return Index; 1752 case SelectionDAGISel::OPC_CheckValueType: 1753 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1754 return Index; 1755 case SelectionDAGISel::OPC_CheckInteger: 1756 Result = !::CheckInteger(Table, Index, N); 1757 return Index; 1758 case SelectionDAGISel::OPC_CheckAndImm: 1759 Result = !::CheckAndImm(Table, Index, N, SDISel); 1760 return Index; 1761 case SelectionDAGISel::OPC_CheckOrImm: 1762 Result = !::CheckOrImm(Table, Index, N, SDISel); 1763 return Index; 1764 } 1765} 1766 1767namespace { 1768 1769struct MatchScope { 1770 /// FailIndex - If this match fails, this is the index to continue with. 1771 unsigned FailIndex; 1772 1773 /// NodeStack - The node stack when the scope was formed. 1774 SmallVector<SDValue, 4> NodeStack; 1775 1776 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1777 unsigned NumRecordedNodes; 1778 1779 /// NumMatchedMemRefs - The number of matched memref entries. 1780 unsigned NumMatchedMemRefs; 1781 1782 /// InputChain/InputFlag - The current chain/flag 1783 SDValue InputChain, InputFlag; 1784 1785 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1786 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1787}; 1788 1789} 1790 1791SDNode *SelectionDAGISel:: 1792SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1793 unsigned TableSize) { 1794 // FIXME: Should these even be selected? Handle these cases in the caller? 1795 switch (NodeToMatch->getOpcode()) { 1796 default: 1797 break; 1798 case ISD::EntryToken: // These nodes remain the same. 1799 case ISD::BasicBlock: 1800 case ISD::Register: 1801 //case ISD::VALUETYPE: 1802 //case ISD::CONDCODE: 1803 case ISD::HANDLENODE: 1804 case ISD::MDNODE_SDNODE: 1805 case ISD::TargetConstant: 1806 case ISD::TargetConstantFP: 1807 case ISD::TargetConstantPool: 1808 case ISD::TargetFrameIndex: 1809 case ISD::TargetExternalSymbol: 1810 case ISD::TargetBlockAddress: 1811 case ISD::TargetJumpTable: 1812 case ISD::TargetGlobalTLSAddress: 1813 case ISD::TargetGlobalAddress: 1814 case ISD::TokenFactor: 1815 case ISD::CopyFromReg: 1816 case ISD::CopyToReg: 1817 case ISD::EH_LABEL: 1818 NodeToMatch->setNodeId(-1); // Mark selected. 1819 return 0; 1820 case ISD::AssertSext: 1821 case ISD::AssertZext: 1822 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1823 NodeToMatch->getOperand(0)); 1824 return 0; 1825 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1826 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1827 } 1828 1829 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1830 1831 // Set up the node stack with NodeToMatch as the only node on the stack. 1832 SmallVector<SDValue, 8> NodeStack; 1833 SDValue N = SDValue(NodeToMatch, 0); 1834 NodeStack.push_back(N); 1835 1836 // MatchScopes - Scopes used when matching, if a match failure happens, this 1837 // indicates where to continue checking. 1838 SmallVector<MatchScope, 8> MatchScopes; 1839 1840 // RecordedNodes - This is the set of nodes that have been recorded by the 1841 // state machine. 1842 SmallVector<SDValue, 8> RecordedNodes; 1843 1844 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1845 // pattern. 1846 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1847 1848 // These are the current input chain and flag for use when generating nodes. 1849 // Various Emit operations change these. For example, emitting a copytoreg 1850 // uses and updates these. 1851 SDValue InputChain, InputFlag; 1852 1853 // ChainNodesMatched - If a pattern matches nodes that have input/output 1854 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1855 // which ones they are. The result is captured into this list so that we can 1856 // update the chain results when the pattern is complete. 1857 SmallVector<SDNode*, 3> ChainNodesMatched; 1858 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1859 1860 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1861 NodeToMatch->dump(CurDAG); 1862 errs() << '\n'); 1863 1864 // Determine where to start the interpreter. Normally we start at opcode #0, 1865 // but if the state machine starts with an OPC_SwitchOpcode, then we 1866 // accelerate the first lookup (which is guaranteed to be hot) with the 1867 // OpcodeOffset table. 1868 unsigned MatcherIndex = 0; 1869 1870 if (!OpcodeOffset.empty()) { 1871 // Already computed the OpcodeOffset table, just index into it. 1872 if (N.getOpcode() < OpcodeOffset.size()) 1873 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1874 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1875 1876 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1877 // Otherwise, the table isn't computed, but the state machine does start 1878 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1879 // is the first time we're selecting an instruction. 1880 unsigned Idx = 1; 1881 while (1) { 1882 // Get the size of this case. 1883 unsigned CaseSize = MatcherTable[Idx++]; 1884 if (CaseSize & 128) 1885 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1886 if (CaseSize == 0) break; 1887 1888 // Get the opcode, add the index to the table. 1889 uint16_t Opc = MatcherTable[Idx++]; 1890 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1891 if (Opc >= OpcodeOffset.size()) 1892 OpcodeOffset.resize((Opc+1)*2); 1893 OpcodeOffset[Opc] = Idx; 1894 Idx += CaseSize; 1895 } 1896 1897 // Okay, do the lookup for the first opcode. 1898 if (N.getOpcode() < OpcodeOffset.size()) 1899 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1900 } 1901 1902 while (1) { 1903 assert(MatcherIndex < TableSize && "Invalid index"); 1904#ifndef NDEBUG 1905 unsigned CurrentOpcodeIndex = MatcherIndex; 1906#endif 1907 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1908 switch (Opcode) { 1909 case OPC_Scope: { 1910 // Okay, the semantics of this operation are that we should push a scope 1911 // then evaluate the first child. However, pushing a scope only to have 1912 // the first check fail (which then pops it) is inefficient. If we can 1913 // determine immediately that the first check (or first several) will 1914 // immediately fail, don't even bother pushing a scope for them. 1915 unsigned FailIndex; 1916 1917 while (1) { 1918 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1919 if (NumToSkip & 128) 1920 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1921 // Found the end of the scope with no match. 1922 if (NumToSkip == 0) { 1923 FailIndex = 0; 1924 break; 1925 } 1926 1927 FailIndex = MatcherIndex+NumToSkip; 1928 1929 unsigned MatcherIndexOfPredicate = MatcherIndex; 1930 (void)MatcherIndexOfPredicate; // silence warning. 1931 1932 // If we can't evaluate this predicate without pushing a scope (e.g. if 1933 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1934 // push the scope and evaluate the full predicate chain. 1935 bool Result; 1936 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1937 Result, *this, RecordedNodes); 1938 if (!Result) 1939 break; 1940 1941 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1942 << "index " << MatcherIndexOfPredicate 1943 << ", continuing at " << FailIndex << "\n"); 1944 ++NumDAGIselRetries; 1945 1946 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1947 // move to the next case. 1948 MatcherIndex = FailIndex; 1949 } 1950 1951 // If the whole scope failed to match, bail. 1952 if (FailIndex == 0) break; 1953 1954 // Push a MatchScope which indicates where to go if the first child fails 1955 // to match. 1956 MatchScope NewEntry; 1957 NewEntry.FailIndex = FailIndex; 1958 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1959 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1960 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1961 NewEntry.InputChain = InputChain; 1962 NewEntry.InputFlag = InputFlag; 1963 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1964 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1965 MatchScopes.push_back(NewEntry); 1966 continue; 1967 } 1968 case OPC_RecordNode: 1969 // Remember this node, it may end up being an operand in the pattern. 1970 RecordedNodes.push_back(N); 1971 continue; 1972 1973 case OPC_RecordChild0: case OPC_RecordChild1: 1974 case OPC_RecordChild2: case OPC_RecordChild3: 1975 case OPC_RecordChild4: case OPC_RecordChild5: 1976 case OPC_RecordChild6: case OPC_RecordChild7: { 1977 unsigned ChildNo = Opcode-OPC_RecordChild0; 1978 if (ChildNo >= N.getNumOperands()) 1979 break; // Match fails if out of range child #. 1980 1981 RecordedNodes.push_back(N->getOperand(ChildNo)); 1982 continue; 1983 } 1984 case OPC_RecordMemRef: 1985 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 1986 continue; 1987 1988 case OPC_CaptureFlagInput: 1989 // If the current node has an input flag, capture it in InputFlag. 1990 if (N->getNumOperands() != 0 && 1991 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 1992 InputFlag = N->getOperand(N->getNumOperands()-1); 1993 continue; 1994 1995 case OPC_MoveChild: { 1996 unsigned ChildNo = MatcherTable[MatcherIndex++]; 1997 if (ChildNo >= N.getNumOperands()) 1998 break; // Match fails if out of range child #. 1999 N = N.getOperand(ChildNo); 2000 NodeStack.push_back(N); 2001 continue; 2002 } 2003 2004 case OPC_MoveParent: 2005 // Pop the current node off the NodeStack. 2006 NodeStack.pop_back(); 2007 assert(!NodeStack.empty() && "Node stack imbalance!"); 2008 N = NodeStack.back(); 2009 continue; 2010 2011 case OPC_CheckSame: 2012 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2013 continue; 2014 case OPC_CheckPatternPredicate: 2015 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2016 continue; 2017 case OPC_CheckPredicate: 2018 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2019 N.getNode())) 2020 break; 2021 continue; 2022 case OPC_CheckComplexPat: { 2023 unsigned CPNum = MatcherTable[MatcherIndex++]; 2024 unsigned RecNo = MatcherTable[MatcherIndex++]; 2025 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2026 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2027 RecordedNodes)) 2028 break; 2029 continue; 2030 } 2031 case OPC_CheckOpcode: 2032 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2033 continue; 2034 2035 case OPC_CheckType: 2036 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2037 continue; 2038 2039 case OPC_SwitchOpcode: { 2040 unsigned CurNodeOpcode = N.getOpcode(); 2041 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2042 unsigned CaseSize; 2043 while (1) { 2044 // Get the size of this case. 2045 CaseSize = MatcherTable[MatcherIndex++]; 2046 if (CaseSize & 128) 2047 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2048 if (CaseSize == 0) break; 2049 2050 uint16_t Opc = MatcherTable[MatcherIndex++]; 2051 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2052 2053 // If the opcode matches, then we will execute this case. 2054 if (CurNodeOpcode == Opc) 2055 break; 2056 2057 // Otherwise, skip over this case. 2058 MatcherIndex += CaseSize; 2059 } 2060 2061 // If no cases matched, bail out. 2062 if (CaseSize == 0) break; 2063 2064 // Otherwise, execute the case we found. 2065 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2066 << " to " << MatcherIndex << "\n"); 2067 continue; 2068 } 2069 2070 case OPC_SwitchType: { 2071 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2072 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2073 unsigned CaseSize; 2074 while (1) { 2075 // Get the size of this case. 2076 CaseSize = MatcherTable[MatcherIndex++]; 2077 if (CaseSize & 128) 2078 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2079 if (CaseSize == 0) break; 2080 2081 MVT::SimpleValueType CaseVT = 2082 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2083 if (CaseVT == MVT::iPTR) 2084 CaseVT = TLI.getPointerTy().SimpleTy; 2085 2086 // If the VT matches, then we will execute this case. 2087 if (CurNodeVT == CaseVT) 2088 break; 2089 2090 // Otherwise, skip over this case. 2091 MatcherIndex += CaseSize; 2092 } 2093 2094 // If no cases matched, bail out. 2095 if (CaseSize == 0) break; 2096 2097 // Otherwise, execute the case we found. 2098 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2099 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2100 continue; 2101 } 2102 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2103 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2104 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2105 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2106 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2107 Opcode-OPC_CheckChild0Type)) 2108 break; 2109 continue; 2110 case OPC_CheckCondCode: 2111 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2112 continue; 2113 case OPC_CheckValueType: 2114 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2115 continue; 2116 case OPC_CheckInteger: 2117 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2118 continue; 2119 case OPC_CheckAndImm: 2120 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2121 continue; 2122 case OPC_CheckOrImm: 2123 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2124 continue; 2125 2126 case OPC_CheckFoldableChainNode: { 2127 assert(NodeStack.size() != 1 && "No parent node"); 2128 // Verify that all intermediate nodes between the root and this one have 2129 // a single use. 2130 bool HasMultipleUses = false; 2131 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2132 if (!NodeStack[i].hasOneUse()) { 2133 HasMultipleUses = true; 2134 break; 2135 } 2136 if (HasMultipleUses) break; 2137 2138 // Check to see that the target thinks this is profitable to fold and that 2139 // we can fold it without inducing cycles in the graph. 2140 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2141 NodeToMatch) || 2142 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2143 NodeToMatch, OptLevel, 2144 true/*We validate our own chains*/)) 2145 break; 2146 2147 continue; 2148 } 2149 case OPC_EmitInteger: { 2150 MVT::SimpleValueType VT = 2151 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2152 int64_t Val = MatcherTable[MatcherIndex++]; 2153 if (Val & 128) 2154 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2155 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2156 continue; 2157 } 2158 case OPC_EmitRegister: { 2159 MVT::SimpleValueType VT = 2160 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2161 unsigned RegNo = MatcherTable[MatcherIndex++]; 2162 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2163 continue; 2164 } 2165 2166 case OPC_EmitConvertToTarget: { 2167 // Convert from IMM/FPIMM to target version. 2168 unsigned RecNo = MatcherTable[MatcherIndex++]; 2169 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2170 SDValue Imm = RecordedNodes[RecNo]; 2171 2172 if (Imm->getOpcode() == ISD::Constant) { 2173 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2174 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2175 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2176 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2177 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2178 } 2179 2180 RecordedNodes.push_back(Imm); 2181 continue; 2182 } 2183 2184 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2185 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2186 // These are space-optimized forms of OPC_EmitMergeInputChains. 2187 assert(InputChain.getNode() == 0 && 2188 "EmitMergeInputChains should be the first chain producing node"); 2189 assert(ChainNodesMatched.empty() && 2190 "Should only have one EmitMergeInputChains per match"); 2191 2192 // Read all of the chained nodes. 2193 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2194 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2195 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2196 2197 // FIXME: What if other value results of the node have uses not matched 2198 // by this pattern? 2199 if (ChainNodesMatched.back() != NodeToMatch && 2200 !RecordedNodes[RecNo].hasOneUse()) { 2201 ChainNodesMatched.clear(); 2202 break; 2203 } 2204 2205 // Merge the input chains if they are not intra-pattern references. 2206 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2207 2208 if (InputChain.getNode() == 0) 2209 break; // Failed to merge. 2210 continue; 2211 } 2212 2213 case OPC_EmitMergeInputChains: { 2214 assert(InputChain.getNode() == 0 && 2215 "EmitMergeInputChains should be the first chain producing node"); 2216 // This node gets a list of nodes we matched in the input that have 2217 // chains. We want to token factor all of the input chains to these nodes 2218 // together. However, if any of the input chains is actually one of the 2219 // nodes matched in this pattern, then we have an intra-match reference. 2220 // Ignore these because the newly token factored chain should not refer to 2221 // the old nodes. 2222 unsigned NumChains = MatcherTable[MatcherIndex++]; 2223 assert(NumChains != 0 && "Can't TF zero chains"); 2224 2225 assert(ChainNodesMatched.empty() && 2226 "Should only have one EmitMergeInputChains per match"); 2227 2228 // Read all of the chained nodes. 2229 for (unsigned i = 0; i != NumChains; ++i) { 2230 unsigned RecNo = MatcherTable[MatcherIndex++]; 2231 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2232 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2233 2234 // FIXME: What if other value results of the node have uses not matched 2235 // by this pattern? 2236 if (ChainNodesMatched.back() != NodeToMatch && 2237 !RecordedNodes[RecNo].hasOneUse()) { 2238 ChainNodesMatched.clear(); 2239 break; 2240 } 2241 } 2242 2243 // If the inner loop broke out, the match fails. 2244 if (ChainNodesMatched.empty()) 2245 break; 2246 2247 // Merge the input chains if they are not intra-pattern references. 2248 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2249 2250 if (InputChain.getNode() == 0) 2251 break; // Failed to merge. 2252 2253 continue; 2254 } 2255 2256 case OPC_EmitCopyToReg: { 2257 unsigned RecNo = MatcherTable[MatcherIndex++]; 2258 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2259 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2260 2261 if (InputChain.getNode() == 0) 2262 InputChain = CurDAG->getEntryNode(); 2263 2264 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2265 DestPhysReg, RecordedNodes[RecNo], 2266 InputFlag); 2267 2268 InputFlag = InputChain.getValue(1); 2269 continue; 2270 } 2271 2272 case OPC_EmitNodeXForm: { 2273 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2274 unsigned RecNo = MatcherTable[MatcherIndex++]; 2275 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2276 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2277 continue; 2278 } 2279 2280 case OPC_EmitNode: 2281 case OPC_MorphNodeTo: { 2282 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2283 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2284 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2285 // Get the result VT list. 2286 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2287 SmallVector<EVT, 4> VTs; 2288 for (unsigned i = 0; i != NumVTs; ++i) { 2289 MVT::SimpleValueType VT = 2290 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2291 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2292 VTs.push_back(VT); 2293 } 2294 2295 if (EmitNodeInfo & OPFL_Chain) 2296 VTs.push_back(MVT::Other); 2297 if (EmitNodeInfo & OPFL_FlagOutput) 2298 VTs.push_back(MVT::Flag); 2299 2300 // This is hot code, so optimize the two most common cases of 1 and 2 2301 // results. 2302 SDVTList VTList; 2303 if (VTs.size() == 1) 2304 VTList = CurDAG->getVTList(VTs[0]); 2305 else if (VTs.size() == 2) 2306 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2307 else 2308 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2309 2310 // Get the operand list. 2311 unsigned NumOps = MatcherTable[MatcherIndex++]; 2312 SmallVector<SDValue, 8> Ops; 2313 for (unsigned i = 0; i != NumOps; ++i) { 2314 unsigned RecNo = MatcherTable[MatcherIndex++]; 2315 if (RecNo & 128) 2316 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2317 2318 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2319 Ops.push_back(RecordedNodes[RecNo]); 2320 } 2321 2322 // If there are variadic operands to add, handle them now. 2323 if (EmitNodeInfo & OPFL_VariadicInfo) { 2324 // Determine the start index to copy from. 2325 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2326 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2327 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2328 "Invalid variadic node"); 2329 // Copy all of the variadic operands, not including a potential flag 2330 // input. 2331 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2332 i != e; ++i) { 2333 SDValue V = NodeToMatch->getOperand(i); 2334 if (V.getValueType() == MVT::Flag) break; 2335 Ops.push_back(V); 2336 } 2337 } 2338 2339 // If this has chain/flag inputs, add them. 2340 if (EmitNodeInfo & OPFL_Chain) 2341 Ops.push_back(InputChain); 2342 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2343 Ops.push_back(InputFlag); 2344 2345 // Create the node. 2346 SDNode *Res = 0; 2347 if (Opcode != OPC_MorphNodeTo) { 2348 // If this is a normal EmitNode command, just create the new node and 2349 // add the results to the RecordedNodes list. 2350 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2351 VTList, Ops.data(), Ops.size()); 2352 2353 // Add all the non-flag/non-chain results to the RecordedNodes list. 2354 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2355 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2356 RecordedNodes.push_back(SDValue(Res, i)); 2357 } 2358 2359 } else { 2360 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2361 EmitNodeInfo); 2362 } 2363 2364 // If the node had chain/flag results, update our notion of the current 2365 // chain and flag. 2366 if (EmitNodeInfo & OPFL_FlagOutput) { 2367 InputFlag = SDValue(Res, VTs.size()-1); 2368 if (EmitNodeInfo & OPFL_Chain) 2369 InputChain = SDValue(Res, VTs.size()-2); 2370 } else if (EmitNodeInfo & OPFL_Chain) 2371 InputChain = SDValue(Res, VTs.size()-1); 2372 2373 // If the OPFL_MemRefs flag is set on this node, slap all of the 2374 // accumulated memrefs onto it. 2375 // 2376 // FIXME: This is vastly incorrect for patterns with multiple outputs 2377 // instructions that access memory and for ComplexPatterns that match 2378 // loads. 2379 if (EmitNodeInfo & OPFL_MemRefs) { 2380 MachineSDNode::mmo_iterator MemRefs = 2381 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2382 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2383 cast<MachineSDNode>(Res) 2384 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2385 } 2386 2387 DEBUG(errs() << " " 2388 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2389 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2390 2391 // If this was a MorphNodeTo then we're completely done! 2392 if (Opcode == OPC_MorphNodeTo) { 2393 // Update chain and flag uses. 2394 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2395 InputFlag, FlagResultNodesMatched, true); 2396 return Res; 2397 } 2398 2399 continue; 2400 } 2401 2402 case OPC_MarkFlagResults: { 2403 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2404 2405 // Read and remember all the flag-result nodes. 2406 for (unsigned i = 0; i != NumNodes; ++i) { 2407 unsigned RecNo = MatcherTable[MatcherIndex++]; 2408 if (RecNo & 128) 2409 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2410 2411 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2412 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2413 } 2414 continue; 2415 } 2416 2417 case OPC_CompleteMatch: { 2418 // The match has been completed, and any new nodes (if any) have been 2419 // created. Patch up references to the matched dag to use the newly 2420 // created nodes. 2421 unsigned NumResults = MatcherTable[MatcherIndex++]; 2422 2423 for (unsigned i = 0; i != NumResults; ++i) { 2424 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2425 if (ResSlot & 128) 2426 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2427 2428 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2429 SDValue Res = RecordedNodes[ResSlot]; 2430 2431 assert(i < NodeToMatch->getNumValues() && 2432 NodeToMatch->getValueType(i) != MVT::Other && 2433 NodeToMatch->getValueType(i) != MVT::Flag && 2434 "Invalid number of results to complete!"); 2435 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2436 NodeToMatch->getValueType(i) == MVT::iPTR || 2437 Res.getValueType() == MVT::iPTR || 2438 NodeToMatch->getValueType(i).getSizeInBits() == 2439 Res.getValueType().getSizeInBits()) && 2440 "invalid replacement"); 2441 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2442 } 2443 2444 // If the root node defines a flag, add it to the flag nodes to update 2445 // list. 2446 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2447 FlagResultNodesMatched.push_back(NodeToMatch); 2448 2449 // Update chain and flag uses. 2450 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2451 InputFlag, FlagResultNodesMatched, false); 2452 2453 assert(NodeToMatch->use_empty() && 2454 "Didn't replace all uses of the node?"); 2455 2456 // FIXME: We just return here, which interacts correctly with SelectRoot 2457 // above. We should fix this to not return an SDNode* anymore. 2458 return 0; 2459 } 2460 } 2461 2462 // If the code reached this point, then the match failed. See if there is 2463 // another child to try in the current 'Scope', otherwise pop it until we 2464 // find a case to check. 2465 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2466 ++NumDAGIselRetries; 2467 while (1) { 2468 if (MatchScopes.empty()) { 2469 CannotYetSelect(NodeToMatch); 2470 return 0; 2471 } 2472 2473 // Restore the interpreter state back to the point where the scope was 2474 // formed. 2475 MatchScope &LastScope = MatchScopes.back(); 2476 RecordedNodes.resize(LastScope.NumRecordedNodes); 2477 NodeStack.clear(); 2478 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2479 N = NodeStack.back(); 2480 2481 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2482 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2483 MatcherIndex = LastScope.FailIndex; 2484 2485 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2486 2487 InputChain = LastScope.InputChain; 2488 InputFlag = LastScope.InputFlag; 2489 if (!LastScope.HasChainNodesMatched) 2490 ChainNodesMatched.clear(); 2491 if (!LastScope.HasFlagResultNodesMatched) 2492 FlagResultNodesMatched.clear(); 2493 2494 // Check to see what the offset is at the new MatcherIndex. If it is zero 2495 // we have reached the end of this scope, otherwise we have another child 2496 // in the current scope to try. 2497 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2498 if (NumToSkip & 128) 2499 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2500 2501 // If we have another child in this scope to match, update FailIndex and 2502 // try it. 2503 if (NumToSkip != 0) { 2504 LastScope.FailIndex = MatcherIndex+NumToSkip; 2505 break; 2506 } 2507 2508 // End of this scope, pop it and try the next child in the containing 2509 // scope. 2510 MatchScopes.pop_back(); 2511 } 2512 } 2513} 2514 2515 2516 2517void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2518 std::string msg; 2519 raw_string_ostream Msg(msg); 2520 Msg << "Cannot yet select: "; 2521 2522 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2523 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2524 N->getOpcode() != ISD::INTRINSIC_VOID) { 2525 N->printrFull(Msg, CurDAG); 2526 } else { 2527 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2528 unsigned iid = 2529 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2530 if (iid < Intrinsic::num_intrinsics) 2531 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2532 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2533 Msg << "target intrinsic %" << TII->getName(iid); 2534 else 2535 Msg << "unknown intrinsic #" << iid; 2536 } 2537 report_fatal_error(Msg.str()); 2538} 2539 2540char SelectionDAGISel::ID = 0; 2541