SelectionDAGISel.cpp revision c7c3f110eda0ff8040e4bd99e38d3112b910810f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/Analysis/AliasAnalysis.h" 16#include "llvm/CodeGen/SelectionDAGISel.h" 17#include "llvm/CodeGen/ScheduleDAG.h" 18#include "llvm/CallingConv.h" 19#include "llvm/Constants.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/GlobalVariable.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/IntrinsicLowering.h" 28#include "llvm/CodeGen/MachineDebugInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/CodeGen/SSARegMap.h" 36#include "llvm/Target/MRegisterInfo.h" 37#include "llvm/Target/TargetData.h" 38#include "llvm/Target/TargetFrameInfo.h" 39#include "llvm/Target/TargetInstrInfo.h" 40#include "llvm/Target/TargetLowering.h" 41#include "llvm/Target/TargetMachine.h" 42#include "llvm/Target/TargetOptions.h" 43#include "llvm/Transforms/Utils/BasicBlockUtils.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <map> 48#include <set> 49#include <iostream> 50#include <algorithm> 51using namespace llvm; 52 53#ifndef NDEBUG 54static cl::opt<bool> 55ViewISelDAGs("view-isel-dags", cl::Hidden, 56 cl::desc("Pop up a window to show isel dags as they are selected")); 57static cl::opt<bool> 58ViewSchedDAGs("view-sched-dags", cl::Hidden, 59 cl::desc("Pop up a window to show sched dags as they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 62#endif 63 64 65//===---------------------------------------------------------------------===// 66/// 67/// RegisterScheduler class - Track the registration of instruction schedulers. 68/// 69//===---------------------------------------------------------------------===// 70MachinePassRegistry RegisterScheduler::Registry; 71 72//===---------------------------------------------------------------------===// 73/// 74/// ISHeuristic command line option for instruction schedulers. 75/// 76//===---------------------------------------------------------------------===// 77namespace { 78 cl::opt<RegisterScheduler::FunctionPassCtor, false, 79 RegisterPassParser<RegisterScheduler> > 80 ISHeuristic("sched", 81 cl::init(&createDefaultScheduler), 82 cl::desc("Instruction schedulers available:")); 83 84 static RegisterScheduler 85 defaultListDAGScheduler("default", " Best scheduler for the target", 86 createDefaultScheduler); 87} // namespace 88 89namespace { 90 /// RegsForValue - This struct represents the physical registers that a 91 /// particular value is assigned and the type information about the value. 92 /// This is needed because values can be promoted into larger registers and 93 /// expanded into multiple smaller registers than the value. 94 struct VISIBILITY_HIDDEN RegsForValue { 95 /// Regs - This list hold the register (for legal and promoted values) 96 /// or register set (for expanded values) that the value should be assigned 97 /// to. 98 std::vector<unsigned> Regs; 99 100 /// RegVT - The value type of each register. 101 /// 102 MVT::ValueType RegVT; 103 104 /// ValueVT - The value type of the LLVM value, which may be promoted from 105 /// RegVT or made from merging the two expanded parts. 106 MVT::ValueType ValueVT; 107 108 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 109 110 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 111 : RegVT(regvt), ValueVT(valuevt) { 112 Regs.push_back(Reg); 113 } 114 RegsForValue(const std::vector<unsigned> ®s, 115 MVT::ValueType regvt, MVT::ValueType valuevt) 116 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 117 } 118 119 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 120 /// this value and returns the result as a ValueVT value. This uses 121 /// Chain/Flag as the input and updates them for the output Chain/Flag. 122 SDOperand getCopyFromRegs(SelectionDAG &DAG, 123 SDOperand &Chain, SDOperand &Flag) const; 124 125 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 126 /// specified value into the registers specified by this object. This uses 127 /// Chain/Flag as the input and updates them for the output Chain/Flag. 128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 129 SDOperand &Chain, SDOperand &Flag, 130 MVT::ValueType PtrVT) const; 131 132 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 133 /// operand list. This adds the code marker and includes the number of 134 /// values added into it. 135 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 136 std::vector<SDOperand> &Ops) const; 137 }; 138} 139 140namespace llvm { 141 //===--------------------------------------------------------------------===// 142 /// createDefaultScheduler - This creates an instruction scheduler appropriate 143 /// for the target. 144 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 145 SelectionDAG *DAG, 146 MachineBasicBlock *BB) { 147 TargetLowering &TLI = IS->getTargetLowering(); 148 149 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 150 return createTDListDAGScheduler(IS, DAG, BB); 151 } else { 152 assert(TLI.getSchedulingPreference() == 153 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 154 return createBURRListDAGScheduler(IS, DAG, BB); 155 } 156 } 157 158 159 //===--------------------------------------------------------------------===// 160 /// FunctionLoweringInfo - This contains information that is global to a 161 /// function that is used when lowering a region of the function. 162 class FunctionLoweringInfo { 163 public: 164 TargetLowering &TLI; 165 Function &Fn; 166 MachineFunction &MF; 167 SSARegMap *RegMap; 168 169 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 170 171 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 172 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 173 174 /// ValueMap - Since we emit code for the function a basic block at a time, 175 /// we must remember which virtual registers hold the values for 176 /// cross-basic-block values. 177 std::map<const Value*, unsigned> ValueMap; 178 179 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 180 /// the entry block. This allows the allocas to be efficiently referenced 181 /// anywhere in the function. 182 std::map<const AllocaInst*, int> StaticAllocaMap; 183 184 unsigned MakeReg(MVT::ValueType VT) { 185 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 186 } 187 188 unsigned CreateRegForValue(const Value *V); 189 190 unsigned InitializeRegForValue(const Value *V) { 191 unsigned &R = ValueMap[V]; 192 assert(R == 0 && "Already initialized this value register!"); 193 return R = CreateRegForValue(V); 194 } 195 }; 196} 197 198/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 199/// PHI nodes or outside of the basic block that defines it, or used by a 200/// switch instruction, which may expand to multiple basic blocks. 201static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 202 if (isa<PHINode>(I)) return true; 203 BasicBlock *BB = I->getParent(); 204 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 205 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 206 isa<SwitchInst>(*UI)) 207 return true; 208 return false; 209} 210 211/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 212/// entry block, return true. This includes arguments used by switches, since 213/// the switch may expand into multiple basic blocks. 214static bool isOnlyUsedInEntryBlock(Argument *A) { 215 BasicBlock *Entry = A->getParent()->begin(); 216 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 217 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 218 return false; // Use not in entry block. 219 return true; 220} 221 222FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 223 Function &fn, MachineFunction &mf) 224 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 225 226 // Create a vreg for each argument register that is not dead and is used 227 // outside of the entry block for the function. 228 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 229 AI != E; ++AI) 230 if (!isOnlyUsedInEntryBlock(AI)) 231 InitializeRegForValue(AI); 232 233 // Initialize the mapping of values to registers. This is only set up for 234 // instruction values that are used outside of the block that defines 235 // them. 236 Function::iterator BB = Fn.begin(), EB = Fn.end(); 237 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 238 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 239 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) { 240 const Type *Ty = AI->getAllocatedType(); 241 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 242 unsigned Align = 243 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 244 AI->getAlignment()); 245 246 // If the alignment of the value is smaller than the size of the value, 247 // and if the size of the value is particularly small (<= 8 bytes), 248 // round up to the size of the value for potentially better performance. 249 // 250 // FIXME: This could be made better with a preferred alignment hook in 251 // TargetData. It serves primarily to 8-byte align doubles for X86. 252 if (Align < TySize && TySize <= 8) Align = TySize; 253 TySize *= CUI->getValue(); // Get total allocated size. 254 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 255 StaticAllocaMap[AI] = 256 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 257 } 258 259 for (; BB != EB; ++BB) 260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 261 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 262 if (!isa<AllocaInst>(I) || 263 !StaticAllocaMap.count(cast<AllocaInst>(I))) 264 InitializeRegForValue(I); 265 266 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 267 // also creates the initial PHI MachineInstrs, though none of the input 268 // operands are populated. 269 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 270 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 271 MBBMap[BB] = MBB; 272 MF.getBasicBlockList().push_back(MBB); 273 274 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 275 // appropriate. 276 PHINode *PN; 277 for (BasicBlock::iterator I = BB->begin(); 278 (PN = dyn_cast<PHINode>(I)); ++I) 279 if (!PN->use_empty()) { 280 MVT::ValueType VT = TLI.getValueType(PN->getType()); 281 unsigned NumElements; 282 if (VT != MVT::Vector) 283 NumElements = TLI.getNumElements(VT); 284 else { 285 MVT::ValueType VT1,VT2; 286 NumElements = 287 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 288 VT1, VT2); 289 } 290 unsigned PHIReg = ValueMap[PN]; 291 assert(PHIReg &&"PHI node does not have an assigned virtual register!"); 292 for (unsigned i = 0; i != NumElements; ++i) 293 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i); 294 } 295 } 296} 297 298/// CreateRegForValue - Allocate the appropriate number of virtual registers of 299/// the correctly promoted or expanded types. Assign these registers 300/// consecutive vreg numbers and return the first assigned number. 301unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 302 MVT::ValueType VT = TLI.getValueType(V->getType()); 303 304 // The number of multiples of registers that we need, to, e.g., split up 305 // a <2 x int64> -> 4 x i32 registers. 306 unsigned NumVectorRegs = 1; 307 308 // If this is a packed type, figure out what type it will decompose into 309 // and how many of the elements it will use. 310 if (VT == MVT::Vector) { 311 const PackedType *PTy = cast<PackedType>(V->getType()); 312 unsigned NumElts = PTy->getNumElements(); 313 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 314 315 // Divide the input until we get to a supported size. This will always 316 // end with a scalar if the target doesn't support vectors. 317 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { 318 NumElts >>= 1; 319 NumVectorRegs <<= 1; 320 } 321 if (NumElts == 1) 322 VT = EltTy; 323 else 324 VT = getVectorType(EltTy, NumElts); 325 } 326 327 // The common case is that we will only create one register for this 328 // value. If we have that case, create and return the virtual register. 329 unsigned NV = TLI.getNumElements(VT); 330 if (NV == 1) { 331 // If we are promoting this value, pick the next largest supported type. 332 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 333 unsigned Reg = MakeReg(PromotedType); 334 // If this is a vector of supported or promoted types (e.g. 4 x i16), 335 // create all of the registers. 336 for (unsigned i = 1; i != NumVectorRegs; ++i) 337 MakeReg(PromotedType); 338 return Reg; 339 } 340 341 // If this value is represented with multiple target registers, make sure 342 // to create enough consecutive registers of the right (smaller) type. 343 unsigned NT = VT-1; // Find the type to use. 344 while (TLI.getNumElements((MVT::ValueType)NT) != 1) 345 --NT; 346 347 unsigned R = MakeReg((MVT::ValueType)NT); 348 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 349 MakeReg((MVT::ValueType)NT); 350 return R; 351} 352 353//===----------------------------------------------------------------------===// 354/// SelectionDAGLowering - This is the common target-independent lowering 355/// implementation that is parameterized by a TargetLowering object. 356/// Also, targets can overload any lowering method. 357/// 358namespace llvm { 359class SelectionDAGLowering { 360 MachineBasicBlock *CurMBB; 361 362 std::map<const Value*, SDOperand> NodeMap; 363 364 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 365 /// them up and then emit token factor nodes when possible. This allows us to 366 /// get simple disambiguation between loads without worrying about alias 367 /// analysis. 368 std::vector<SDOperand> PendingLoads; 369 370 /// Case - A pair of values to record the Value for a switch case, and the 371 /// case's target basic block. 372 typedef std::pair<Constant*, MachineBasicBlock*> Case; 373 typedef std::vector<Case>::iterator CaseItr; 374 typedef std::pair<CaseItr, CaseItr> CaseRange; 375 376 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 377 /// of conditional branches. 378 struct CaseRec { 379 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 380 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 381 382 /// CaseBB - The MBB in which to emit the compare and branch 383 MachineBasicBlock *CaseBB; 384 /// LT, GE - If nonzero, we know the current case value must be less-than or 385 /// greater-than-or-equal-to these Constants. 386 Constant *LT; 387 Constant *GE; 388 /// Range - A pair of iterators representing the range of case values to be 389 /// processed at this point in the binary search tree. 390 CaseRange Range; 391 }; 392 393 /// The comparison function for sorting Case values. 394 struct CaseCmp { 395 bool operator () (const Case& C1, const Case& C2) { 396 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first)) 397 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue(); 398 399 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first); 400 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue(); 401 } 402 }; 403 404public: 405 // TLI - This is information that describes the available target features we 406 // need for lowering. This indicates when operations are unavailable, 407 // implemented with a libcall, etc. 408 TargetLowering &TLI; 409 SelectionDAG &DAG; 410 const TargetData *TD; 411 412 /// SwitchCases - Vector of CaseBlock structures used to communicate 413 /// SwitchInst code generation information. 414 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 415 SelectionDAGISel::JumpTable JT; 416 417 /// FuncInfo - Information about the function as a whole. 418 /// 419 FunctionLoweringInfo &FuncInfo; 420 421 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 422 FunctionLoweringInfo &funcinfo) 423 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 424 JT(0,0,0,0), FuncInfo(funcinfo) { 425 } 426 427 /// getRoot - Return the current virtual root of the Selection DAG. 428 /// 429 SDOperand getRoot() { 430 if (PendingLoads.empty()) 431 return DAG.getRoot(); 432 433 if (PendingLoads.size() == 1) { 434 SDOperand Root = PendingLoads[0]; 435 DAG.setRoot(Root); 436 PendingLoads.clear(); 437 return Root; 438 } 439 440 // Otherwise, we have to make a token factor node. 441 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 442 &PendingLoads[0], PendingLoads.size()); 443 PendingLoads.clear(); 444 DAG.setRoot(Root); 445 return Root; 446 } 447 448 void visit(Instruction &I) { visit(I.getOpcode(), I); } 449 450 void visit(unsigned Opcode, User &I) { 451 switch (Opcode) { 452 default: assert(0 && "Unknown instruction type encountered!"); 453 abort(); 454 // Build the switch statement using the Instruction.def file. 455#define HANDLE_INST(NUM, OPCODE, CLASS) \ 456 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 457#include "llvm/Instruction.def" 458 } 459 } 460 461 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 462 463 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 464 const Value *SV, SDOperand Root, 465 bool isVolatile); 466 467 SDOperand getIntPtrConstant(uint64_t Val) { 468 return DAG.getConstant(Val, TLI.getPointerTy()); 469 } 470 471 SDOperand getValue(const Value *V); 472 473 const SDOperand &setValue(const Value *V, SDOperand NewN) { 474 SDOperand &N = NodeMap[V]; 475 assert(N.Val == 0 && "Already set a value for this node!"); 476 return N = NewN; 477 } 478 479 RegsForValue GetRegistersForValue(const std::string &ConstrCode, 480 MVT::ValueType VT, 481 bool OutReg, bool InReg, 482 std::set<unsigned> &OutputRegs, 483 std::set<unsigned> &InputRegs); 484 485 // Terminator instructions. 486 void visitRet(ReturnInst &I); 487 void visitBr(BranchInst &I); 488 void visitSwitch(SwitchInst &I); 489 void visitUnreachable(UnreachableInst &I) { /* noop */ } 490 491 // Helper for visitSwitch 492 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 493 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 494 495 // These all get lowered before this pass. 496 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); } 497 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); } 498 499 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp); 500 void visitShift(User &I, unsigned Opcode); 501 void visitAdd(User &I) { 502 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD); 503 } 504 void visitSub(User &I); 505 void visitMul(User &I) { 506 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL); 507 } 508 void visitDiv(User &I) { 509 const Type *Ty = I.getType(); 510 visitBinary(I, 511 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV, 512 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV); 513 } 514 void visitRem(User &I) { 515 const Type *Ty = I.getType(); 516 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0); 517 } 518 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); } 519 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); } 520 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); } 521 void visitShl(User &I) { visitShift(I, ISD::SHL); } 522 void visitShr(User &I) { 523 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA); 524 } 525 526 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc, 527 ISD::CondCode FPOpc); 528 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ, 529 ISD::SETOEQ); } 530 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE, 531 ISD::SETUNE); } 532 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE, 533 ISD::SETOLE); } 534 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE, 535 ISD::SETOGE); } 536 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT, 537 ISD::SETOLT); } 538 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT, 539 ISD::SETOGT); } 540 541 void visitExtractElement(User &I); 542 void visitInsertElement(User &I); 543 void visitShuffleVector(User &I); 544 545 void visitGetElementPtr(User &I); 546 void visitCast(User &I); 547 void visitSelect(User &I); 548 549 void visitMalloc(MallocInst &I); 550 void visitFree(FreeInst &I); 551 void visitAlloca(AllocaInst &I); 552 void visitLoad(LoadInst &I); 553 void visitStore(StoreInst &I); 554 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 555 void visitCall(CallInst &I); 556 void visitInlineAsm(CallInst &I); 557 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 558 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 559 560 void visitVAStart(CallInst &I); 561 void visitVAArg(VAArgInst &I); 562 void visitVAEnd(CallInst &I); 563 void visitVACopy(CallInst &I); 564 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress); 565 566 void visitMemIntrinsic(CallInst &I, unsigned Op); 567 568 void visitUserOp1(Instruction &I) { 569 assert(0 && "UserOp1 should not exist at instruction selection time!"); 570 abort(); 571 } 572 void visitUserOp2(Instruction &I) { 573 assert(0 && "UserOp2 should not exist at instruction selection time!"); 574 abort(); 575 } 576}; 577} // end namespace llvm 578 579SDOperand SelectionDAGLowering::getValue(const Value *V) { 580 SDOperand &N = NodeMap[V]; 581 if (N.Val) return N; 582 583 const Type *VTy = V->getType(); 584 MVT::ValueType VT = TLI.getValueType(VTy); 585 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 586 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 587 visit(CE->getOpcode(), *CE); 588 assert(N.Val && "visit didn't populate the ValueMap!"); 589 return N; 590 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 591 return N = DAG.getGlobalAddress(GV, VT); 592 } else if (isa<ConstantPointerNull>(C)) { 593 return N = DAG.getConstant(0, TLI.getPointerTy()); 594 } else if (isa<UndefValue>(C)) { 595 if (!isa<PackedType>(VTy)) 596 return N = DAG.getNode(ISD::UNDEF, VT); 597 598 // Create a VBUILD_VECTOR of undef nodes. 599 const PackedType *PTy = cast<PackedType>(VTy); 600 unsigned NumElements = PTy->getNumElements(); 601 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 602 603 SmallVector<SDOperand, 8> Ops; 604 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 605 606 // Create a VConstant node with generic Vector type. 607 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 608 Ops.push_back(DAG.getValueType(PVT)); 609 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 610 &Ops[0], Ops.size()); 611 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 612 return N = DAG.getConstantFP(CFP->getValue(), VT); 613 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) { 614 unsigned NumElements = PTy->getNumElements(); 615 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 616 617 // Now that we know the number and type of the elements, push a 618 // Constant or ConstantFP node onto the ops list for each element of 619 // the packed constant. 620 SmallVector<SDOperand, 8> Ops; 621 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) { 622 for (unsigned i = 0; i != NumElements; ++i) 623 Ops.push_back(getValue(CP->getOperand(i))); 624 } else { 625 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 626 SDOperand Op; 627 if (MVT::isFloatingPoint(PVT)) 628 Op = DAG.getConstantFP(0, PVT); 629 else 630 Op = DAG.getConstant(0, PVT); 631 Ops.assign(NumElements, Op); 632 } 633 634 // Create a VBUILD_VECTOR node with generic Vector type. 635 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 636 Ops.push_back(DAG.getValueType(PVT)); 637 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size()); 638 } else { 639 // Canonicalize all constant ints to be unsigned. 640 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT); 641 } 642 } 643 644 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 645 std::map<const AllocaInst*, int>::iterator SI = 646 FuncInfo.StaticAllocaMap.find(AI); 647 if (SI != FuncInfo.StaticAllocaMap.end()) 648 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 649 } 650 651 std::map<const Value*, unsigned>::const_iterator VMI = 652 FuncInfo.ValueMap.find(V); 653 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); 654 655 unsigned InReg = VMI->second; 656 657 // If this type is not legal, make it so now. 658 if (VT != MVT::Vector) { 659 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 660 661 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 662 if (DestVT < VT) { 663 // Source must be expanded. This input value is actually coming from the 664 // register pair VMI->second and VMI->second+1. 665 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 666 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 667 } else if (DestVT > VT) { // Promotion case 668 if (MVT::isFloatingPoint(VT)) 669 N = DAG.getNode(ISD::FP_ROUND, VT, N); 670 else 671 N = DAG.getNode(ISD::TRUNCATE, VT, N); 672 } 673 } else { 674 // Otherwise, if this is a vector, make it available as a generic vector 675 // here. 676 MVT::ValueType PTyElementVT, PTyLegalElementVT; 677 const PackedType *PTy = cast<PackedType>(VTy); 678 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT, 679 PTyLegalElementVT); 680 681 // Build a VBUILD_VECTOR with the input registers. 682 SmallVector<SDOperand, 8> Ops; 683 if (PTyElementVT == PTyLegalElementVT) { 684 // If the value types are legal, just VBUILD the CopyFromReg nodes. 685 for (unsigned i = 0; i != NE; ++i) 686 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 687 PTyElementVT)); 688 } else if (PTyElementVT < PTyLegalElementVT) { 689 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate. 690 for (unsigned i = 0; i != NE; ++i) { 691 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 692 PTyElementVT); 693 if (MVT::isFloatingPoint(PTyElementVT)) 694 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 695 else 696 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 697 Ops.push_back(Op); 698 } 699 } else { 700 // If the register was expanded, use BUILD_PAIR. 701 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 702 for (unsigned i = 0; i != NE/2; ++i) { 703 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 704 PTyElementVT); 705 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 706 PTyElementVT); 707 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); 708 } 709 } 710 711 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 712 Ops.push_back(DAG.getValueType(PTyLegalElementVT)); 713 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 714 715 // Finally, use a VBIT_CONVERT to make this available as the appropriate 716 // vector type. 717 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 718 DAG.getConstant(PTy->getNumElements(), 719 MVT::i32), 720 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 721 } 722 723 return N; 724} 725 726 727void SelectionDAGLowering::visitRet(ReturnInst &I) { 728 if (I.getNumOperands() == 0) { 729 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 730 return; 731 } 732 SmallVector<SDOperand, 8> NewValues; 733 NewValues.push_back(getRoot()); 734 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 735 SDOperand RetOp = getValue(I.getOperand(i)); 736 bool isSigned = I.getOperand(i)->getType()->isSigned(); 737 738 // If this is an integer return value, we need to promote it ourselves to 739 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 740 // than sign/zero. 741 // FIXME: C calling convention requires the return type to be promoted to 742 // at least 32-bit. But this is not necessary for non-C calling conventions. 743 if (MVT::isInteger(RetOp.getValueType()) && 744 RetOp.getValueType() < MVT::i64) { 745 MVT::ValueType TmpVT; 746 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 747 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 748 else 749 TmpVT = MVT::i32; 750 751 if (isSigned) 752 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp); 753 else 754 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp); 755 } 756 NewValues.push_back(RetOp); 757 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32)); 758 } 759 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 760 &NewValues[0], NewValues.size())); 761} 762 763void SelectionDAGLowering::visitBr(BranchInst &I) { 764 // Update machine-CFG edges. 765 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 766 CurMBB->addSuccessor(Succ0MBB); 767 768 // Figure out which block is immediately after the current one. 769 MachineBasicBlock *NextBlock = 0; 770 MachineFunction::iterator BBI = CurMBB; 771 if (++BBI != CurMBB->getParent()->end()) 772 NextBlock = BBI; 773 774 if (I.isUnconditional()) { 775 // If this is not a fall-through branch, emit the branch. 776 if (Succ0MBB != NextBlock) 777 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 778 DAG.getBasicBlock(Succ0MBB))); 779 } else { 780 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 781 CurMBB->addSuccessor(Succ1MBB); 782 783 SDOperand Cond = getValue(I.getCondition()); 784 if (Succ1MBB == NextBlock) { 785 // If the condition is false, fall through. This means we should branch 786 // if the condition is true to Succ #0. 787 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 788 Cond, DAG.getBasicBlock(Succ0MBB))); 789 } else if (Succ0MBB == NextBlock) { 790 // If the condition is true, fall through. This means we should branch if 791 // the condition is false to Succ #1. Invert the condition first. 792 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 793 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 794 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 795 Cond, DAG.getBasicBlock(Succ1MBB))); 796 } else { 797 std::vector<SDOperand> Ops; 798 Ops.push_back(getRoot()); 799 // If the false case is the current basic block, then this is a self 800 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it 801 // adds an extra instruction in the loop. Instead, invert the 802 // condition and emit "Loop: ... br!cond Loop; br Out. 803 if (CurMBB == Succ1MBB) { 804 std::swap(Succ0MBB, Succ1MBB); 805 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 806 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 807 } 808 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 809 DAG.getBasicBlock(Succ0MBB)); 810 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True, 811 DAG.getBasicBlock(Succ1MBB))); 812 } 813 } 814} 815 816/// visitSwitchCase - Emits the necessary code to represent a single node in 817/// the binary search tree resulting from lowering a switch instruction. 818void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 819 SDOperand SwitchOp = getValue(CB.SwitchV); 820 SDOperand CaseOp = getValue(CB.CaseC); 821 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC); 822 823 // Set NextBlock to be the MBB immediately after the current one, if any. 824 // This is used to avoid emitting unnecessary branches to the next block. 825 MachineBasicBlock *NextBlock = 0; 826 MachineFunction::iterator BBI = CurMBB; 827 if (++BBI != CurMBB->getParent()->end()) 828 NextBlock = BBI; 829 830 // If the lhs block is the next block, invert the condition so that we can 831 // fall through to the lhs instead of the rhs block. 832 if (CB.LHSBB == NextBlock) { 833 std::swap(CB.LHSBB, CB.RHSBB); 834 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 835 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 836 } 837 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 838 DAG.getBasicBlock(CB.LHSBB)); 839 if (CB.RHSBB == NextBlock) 840 DAG.setRoot(BrCond); 841 else 842 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 843 DAG.getBasicBlock(CB.RHSBB))); 844 // Update successor info 845 CurMBB->addSuccessor(CB.LHSBB); 846 CurMBB->addSuccessor(CB.RHSBB); 847} 848 849void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 850 // Emit the code for the jump table 851 MVT::ValueType PTy = TLI.getPointerTy(); 852 assert((PTy == MVT::i32 || PTy == MVT::i64) && 853 "Jump table entries are 32-bit values"); 854 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_; 855 // PIC jump table entries are 32-bit values. 856 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8; 857 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 858 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy, 859 DAG.getConstant(EntrySize, PTy)); 860 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy); 861 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB); 862 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD, 863 NULL, 0); 864 if (isPIC) { 865 // For Pic, the sequence is: 866 // BRIND(load(Jumptable + index) + RelocBase) 867 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 868 SDOperand Reloc; 869 if (TLI.usesGlobalOffsetTable()) 870 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 871 else 872 Reloc = TAB; 873 ADD = DAG.getNode(ISD::ADD, PTy, 874 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), Reloc); 875 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD)); 876 } else { 877 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD)); 878 } 879} 880 881void SelectionDAGLowering::visitSwitch(SwitchInst &I) { 882 // Figure out which block is immediately after the current one. 883 MachineBasicBlock *NextBlock = 0; 884 MachineFunction::iterator BBI = CurMBB; 885 if (++BBI != CurMBB->getParent()->end()) 886 NextBlock = BBI; 887 888 // If there is only the default destination, branch to it if it is not the 889 // next basic block. Otherwise, just fall through. 890 if (I.getNumOperands() == 2) { 891 // Update machine-CFG edges. 892 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()]; 893 // If this is not a fall-through branch, emit the branch. 894 if (DefaultMBB != NextBlock) 895 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 896 DAG.getBasicBlock(DefaultMBB))); 897 CurMBB->addSuccessor(DefaultMBB); 898 return; 899 } 900 901 // If there are any non-default case statements, create a vector of Cases 902 // representing each one, and sort the vector so that we can efficiently 903 // create a binary search tree from them. 904 std::vector<Case> Cases; 905 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) { 906 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)]; 907 Cases.push_back(Case(I.getSuccessorValue(i), SMBB)); 908 } 909 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 910 911 // Get the Value to be switched on and default basic blocks, which will be 912 // inserted into CaseBlock records, representing basic blocks in the binary 913 // search tree. 914 Value *SV = I.getOperand(0); 915 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()]; 916 917 // Get the MachineFunction which holds the current MBB. This is used during 918 // emission of jump tables, and when inserting any additional MBBs necessary 919 // to represent the switch. 920 MachineFunction *CurMF = CurMBB->getParent(); 921 const BasicBlock *LLVMBB = CurMBB->getBasicBlock(); 922 923 // If the switch has more than 5 blocks, and at least 31.25% dense, and the 924 // target supports indirect branches, then emit a jump table rather than 925 // lowering the switch to a binary tree of conditional branches. 926 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) && 927 Cases.size() > 5) { 928 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue(); 929 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue(); 930 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL); 931 932 if (Density >= 0.3125) { 933 // Create a new basic block to hold the code for loading the address 934 // of the jump table, and jumping to it. Update successor information; 935 // we will either branch to the default case for the switch, or the jump 936 // table. 937 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 938 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 939 CurMBB->addSuccessor(Default); 940 CurMBB->addSuccessor(JumpTableBB); 941 942 // Subtract the lowest switch case value from the value being switched on 943 // and conditional branch to default mbb if the result is greater than the 944 // difference between smallest and largest cases. 945 SDOperand SwitchOp = getValue(SV); 946 MVT::ValueType VT = SwitchOp.getValueType(); 947 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 948 DAG.getConstant(First, VT)); 949 950 // The SDNode we just created, which holds the value being switched on 951 // minus the the smallest case value, needs to be copied to a virtual 952 // register so it can be used as an index into the jump table in a 953 // subsequent basic block. This value may be smaller or larger than the 954 // target's pointer type, and therefore require extension or truncating. 955 if (VT > TLI.getPointerTy()) 956 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 957 else 958 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 959 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 960 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 961 962 // Emit the range check for the jump table, and branch to the default 963 // block for the switch statement if the value being switched on exceeds 964 // the largest case in the switch. 965 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 966 DAG.getConstant(Last-First,VT), ISD::SETUGT); 967 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 968 DAG.getBasicBlock(Default))); 969 970 // Build a vector of destination BBs, corresponding to each target 971 // of the jump table. If the value of the jump table slot corresponds to 972 // a case statement, push the case's BB onto the vector, otherwise, push 973 // the default BB. 974 std::vector<MachineBasicBlock*> DestBBs; 975 uint64_t TEI = First; 976 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) { 977 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) { 978 DestBBs.push_back(ii->second); 979 ++ii; 980 } else { 981 DestBBs.push_back(Default); 982 } 983 } 984 985 // Update successor info 986 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 987 E = DestBBs.end(); I != E; ++I) 988 JumpTableBB->addSuccessor(*I); 989 990 // Create a jump table index for this jump table, or return an existing 991 // one. 992 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 993 994 // Set the jump table information so that we can codegen it as a second 995 // MachineBasicBlock 996 JT.Reg = JumpTableReg; 997 JT.JTI = JTI; 998 JT.MBB = JumpTableBB; 999 JT.Default = Default; 1000 return; 1001 } 1002 } 1003 1004 // Push the initial CaseRec onto the worklist 1005 std::vector<CaseRec> CaseVec; 1006 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1007 1008 while (!CaseVec.empty()) { 1009 // Grab a record representing a case range to process off the worklist 1010 CaseRec CR = CaseVec.back(); 1011 CaseVec.pop_back(); 1012 1013 // Size is the number of Cases represented by this range. If Size is 1, 1014 // then we are processing a leaf of the binary search tree. Otherwise, 1015 // we need to pick a pivot, and push left and right ranges onto the 1016 // worklist. 1017 unsigned Size = CR.Range.second - CR.Range.first; 1018 1019 if (Size == 1) { 1020 // Create a CaseBlock record representing a conditional branch to 1021 // the Case's target mbb if the value being switched on SV is equal 1022 // to C. Otherwise, branch to default. 1023 Constant *C = CR.Range.first->first; 1024 MachineBasicBlock *Target = CR.Range.first->second; 1025 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default, 1026 CR.CaseBB); 1027 // If the MBB representing the leaf node is the current MBB, then just 1028 // call visitSwitchCase to emit the code into the current block. 1029 // Otherwise, push the CaseBlock onto the vector to be later processed 1030 // by SDISel, and insert the node's MBB before the next MBB. 1031 if (CR.CaseBB == CurMBB) 1032 visitSwitchCase(CB); 1033 else { 1034 SwitchCases.push_back(CB); 1035 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB); 1036 } 1037 } else { 1038 // split case range at pivot 1039 CaseItr Pivot = CR.Range.first + (Size / 2); 1040 CaseRange LHSR(CR.Range.first, Pivot); 1041 CaseRange RHSR(Pivot, CR.Range.second); 1042 Constant *C = Pivot->first; 1043 MachineBasicBlock *RHSBB = 0, *LHSBB = 0; 1044 // We know that we branch to the LHS if the Value being switched on is 1045 // less than the Pivot value, C. We use this to optimize our binary 1046 // tree a bit, by recognizing that if SV is greater than or equal to the 1047 // LHS's Case Value, and that Case Value is exactly one less than the 1048 // Pivot's Value, then we can branch directly to the LHS's Target, 1049 // rather than creating a leaf node for it. 1050 if ((LHSR.second - LHSR.first) == 1 && 1051 LHSR.first->first == CR.GE && 1052 cast<ConstantIntegral>(C)->getRawValue() == 1053 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) { 1054 LHSBB = LHSR.first->second; 1055 } else { 1056 LHSBB = new MachineBasicBlock(LLVMBB); 1057 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR)); 1058 } 1059 // Similar to the optimization above, if the Value being switched on is 1060 // known to be less than the Constant CR.LT, and the current Case Value 1061 // is CR.LT - 1, then we can branch directly to the target block for 1062 // the current Case Value, rather than emitting a RHS leaf node for it. 1063 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1064 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() == 1065 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) { 1066 RHSBB = RHSR.first->second; 1067 } else { 1068 RHSBB = new MachineBasicBlock(LLVMBB); 1069 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR)); 1070 } 1071 // Create a CaseBlock record representing a conditional branch to 1072 // the LHS node if the value being switched on SV is less than C. 1073 // Otherwise, branch to LHS. 1074 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT; 1075 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB); 1076 if (CR.CaseBB == CurMBB) 1077 visitSwitchCase(CB); 1078 else { 1079 SwitchCases.push_back(CB); 1080 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB); 1081 } 1082 } 1083 } 1084} 1085 1086void SelectionDAGLowering::visitSub(User &I) { 1087 // -0.0 - X --> fneg 1088 if (I.getType()->isFloatingPoint()) { 1089 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1090 if (CFP->isExactlyValue(-0.0)) { 1091 SDOperand Op2 = getValue(I.getOperand(1)); 1092 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1093 return; 1094 } 1095 } 1096 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB); 1097} 1098 1099void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp, 1100 unsigned VecOp) { 1101 const Type *Ty = I.getType(); 1102 SDOperand Op1 = getValue(I.getOperand(0)); 1103 SDOperand Op2 = getValue(I.getOperand(1)); 1104 1105 if (Ty->isIntegral()) { 1106 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2)); 1107 } else if (Ty->isFloatingPoint()) { 1108 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2)); 1109 } else { 1110 const PackedType *PTy = cast<PackedType>(Ty); 1111 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32); 1112 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType())); 1113 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ)); 1114 } 1115} 1116 1117void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1118 SDOperand Op1 = getValue(I.getOperand(0)); 1119 SDOperand Op2 = getValue(I.getOperand(1)); 1120 1121 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1122 1123 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1124} 1125 1126void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode, 1127 ISD::CondCode UnsignedOpcode, 1128 ISD::CondCode FPOpcode) { 1129 SDOperand Op1 = getValue(I.getOperand(0)); 1130 SDOperand Op2 = getValue(I.getOperand(1)); 1131 ISD::CondCode Opcode = SignedOpcode; 1132 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint()) 1133 Opcode = FPOpcode; 1134 else if (I.getOperand(0)->getType()->isUnsigned()) 1135 Opcode = UnsignedOpcode; 1136 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1137} 1138 1139void SelectionDAGLowering::visitSelect(User &I) { 1140 SDOperand Cond = getValue(I.getOperand(0)); 1141 SDOperand TrueVal = getValue(I.getOperand(1)); 1142 SDOperand FalseVal = getValue(I.getOperand(2)); 1143 if (!isa<PackedType>(I.getType())) { 1144 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 1145 TrueVal, FalseVal)); 1146 } else { 1147 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 1148 *(TrueVal.Val->op_end()-2), 1149 *(TrueVal.Val->op_end()-1))); 1150 } 1151} 1152 1153void SelectionDAGLowering::visitCast(User &I) { 1154 SDOperand N = getValue(I.getOperand(0)); 1155 MVT::ValueType SrcVT = N.getValueType(); 1156 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1157 1158 if (DestVT == MVT::Vector) { 1159 // This is a cast to a vector from something else. This is always a bit 1160 // convert. Get information about the input vector. 1161 const PackedType *DestTy = cast<PackedType>(I.getType()); 1162 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1163 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 1164 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 1165 DAG.getValueType(EltVT))); 1166 } else if (SrcVT == DestVT) { 1167 setValue(&I, N); // noop cast. 1168 } else if (DestVT == MVT::i1) { 1169 // Cast to bool is a comparison against zero, not truncation to zero. 1170 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) : 1171 DAG.getConstantFP(0.0, N.getValueType()); 1172 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE)); 1173 } else if (isInteger(SrcVT)) { 1174 if (isInteger(DestVT)) { // Int -> Int cast 1175 if (DestVT < SrcVT) // Truncating cast? 1176 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 1177 else if (I.getOperand(0)->getType()->isSigned()) 1178 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 1179 else 1180 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 1181 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast 1182 if (I.getOperand(0)->getType()->isSigned()) 1183 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 1184 else 1185 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 1186 } else { 1187 assert(0 && "Unknown cast!"); 1188 } 1189 } else if (isFloatingPoint(SrcVT)) { 1190 if (isFloatingPoint(DestVT)) { // FP -> FP cast 1191 if (DestVT < SrcVT) // Rounding cast? 1192 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 1193 else 1194 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 1195 } else if (isInteger(DestVT)) { // FP -> Int cast. 1196 if (I.getType()->isSigned()) 1197 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 1198 else 1199 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 1200 } else { 1201 assert(0 && "Unknown cast!"); 1202 } 1203 } else { 1204 assert(SrcVT == MVT::Vector && "Unknown cast!"); 1205 assert(DestVT != MVT::Vector && "Casts to vector already handled!"); 1206 // This is a cast from a vector to something else. This is always a bit 1207 // convert. Get information about the input vector. 1208 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 1209 } 1210} 1211 1212void SelectionDAGLowering::visitInsertElement(User &I) { 1213 SDOperand InVec = getValue(I.getOperand(0)); 1214 SDOperand InVal = getValue(I.getOperand(1)); 1215 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1216 getValue(I.getOperand(2))); 1217 1218 SDOperand Num = *(InVec.Val->op_end()-2); 1219 SDOperand Typ = *(InVec.Val->op_end()-1); 1220 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 1221 InVec, InVal, InIdx, Num, Typ)); 1222} 1223 1224void SelectionDAGLowering::visitExtractElement(User &I) { 1225 SDOperand InVec = getValue(I.getOperand(0)); 1226 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1227 getValue(I.getOperand(1))); 1228 SDOperand Typ = *(InVec.Val->op_end()-1); 1229 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 1230 TLI.getValueType(I.getType()), InVec, InIdx)); 1231} 1232 1233void SelectionDAGLowering::visitShuffleVector(User &I) { 1234 SDOperand V1 = getValue(I.getOperand(0)); 1235 SDOperand V2 = getValue(I.getOperand(1)); 1236 SDOperand Mask = getValue(I.getOperand(2)); 1237 1238 SDOperand Num = *(V1.Val->op_end()-2); 1239 SDOperand Typ = *(V2.Val->op_end()-1); 1240 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 1241 V1, V2, Mask, Num, Typ)); 1242} 1243 1244 1245void SelectionDAGLowering::visitGetElementPtr(User &I) { 1246 SDOperand N = getValue(I.getOperand(0)); 1247 const Type *Ty = I.getOperand(0)->getType(); 1248 1249 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 1250 OI != E; ++OI) { 1251 Value *Idx = *OI; 1252 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 1253 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 1254 if (Field) { 1255 // N = N + Offset 1256 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field]; 1257 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 1258 getIntPtrConstant(Offset)); 1259 } 1260 Ty = StTy->getElementType(Field); 1261 } else { 1262 Ty = cast<SequentialType>(Ty)->getElementType(); 1263 1264 // If this is a constant subscript, handle it quickly. 1265 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 1266 if (CI->getRawValue() == 0) continue; 1267 1268 uint64_t Offs; 1269 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI)) 1270 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); 1271 else 1272 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue(); 1273 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 1274 continue; 1275 } 1276 1277 // N = N + Idx * ElementSize; 1278 uint64_t ElementSize = TD->getTypeSize(Ty); 1279 SDOperand IdxN = getValue(Idx); 1280 1281 // If the index is smaller or larger than intptr_t, truncate or extend 1282 // it. 1283 if (IdxN.getValueType() < N.getValueType()) { 1284 if (Idx->getType()->isSigned()) 1285 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 1286 else 1287 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN); 1288 } else if (IdxN.getValueType() > N.getValueType()) 1289 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 1290 1291 // If this is a multiply by a power of two, turn it into a shl 1292 // immediately. This is a very common case. 1293 if (isPowerOf2_64(ElementSize)) { 1294 unsigned Amt = Log2_64(ElementSize); 1295 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 1296 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 1297 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1298 continue; 1299 } 1300 1301 SDOperand Scale = getIntPtrConstant(ElementSize); 1302 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 1303 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1304 } 1305 } 1306 setValue(&I, N); 1307} 1308 1309void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 1310 // If this is a fixed sized alloca in the entry block of the function, 1311 // allocate it statically on the stack. 1312 if (FuncInfo.StaticAllocaMap.count(&I)) 1313 return; // getValue will auto-populate this. 1314 1315 const Type *Ty = I.getAllocatedType(); 1316 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 1317 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 1318 I.getAlignment()); 1319 1320 SDOperand AllocSize = getValue(I.getArraySize()); 1321 MVT::ValueType IntPtr = TLI.getPointerTy(); 1322 if (IntPtr < AllocSize.getValueType()) 1323 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 1324 else if (IntPtr > AllocSize.getValueType()) 1325 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 1326 1327 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 1328 getIntPtrConstant(TySize)); 1329 1330 // Handle alignment. If the requested alignment is less than or equal to the 1331 // stack alignment, ignore it and round the size of the allocation up to the 1332 // stack alignment size. If the size is greater than the stack alignment, we 1333 // note this in the DYNAMIC_STACKALLOC node. 1334 unsigned StackAlign = 1335 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1336 if (Align <= StackAlign) { 1337 Align = 0; 1338 // Add SA-1 to the size. 1339 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 1340 getIntPtrConstant(StackAlign-1)); 1341 // Mask out the low bits for alignment purposes. 1342 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 1343 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 1344 } 1345 1346 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 1347 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 1348 MVT::Other); 1349 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 1350 DAG.setRoot(setValue(&I, DSA).getValue(1)); 1351 1352 // Inform the Frame Information that we have just allocated a variable-sized 1353 // object. 1354 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 1355} 1356 1357void SelectionDAGLowering::visitLoad(LoadInst &I) { 1358 SDOperand Ptr = getValue(I.getOperand(0)); 1359 1360 SDOperand Root; 1361 if (I.isVolatile()) 1362 Root = getRoot(); 1363 else { 1364 // Do not serialize non-volatile loads against each other. 1365 Root = DAG.getRoot(); 1366 } 1367 1368 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 1369 Root, I.isVolatile())); 1370} 1371 1372SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 1373 const Value *SV, SDOperand Root, 1374 bool isVolatile) { 1375 SDOperand L; 1376 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) { 1377 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 1378 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, 1379 DAG.getSrcValue(SV)); 1380 } else { 1381 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile); 1382 } 1383 1384 if (isVolatile) 1385 DAG.setRoot(L.getValue(1)); 1386 else 1387 PendingLoads.push_back(L.getValue(1)); 1388 1389 return L; 1390} 1391 1392 1393void SelectionDAGLowering::visitStore(StoreInst &I) { 1394 Value *SrcV = I.getOperand(0); 1395 SDOperand Src = getValue(SrcV); 1396 SDOperand Ptr = getValue(I.getOperand(1)); 1397 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 1398 I.isVolatile())); 1399} 1400 1401/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 1402/// access memory and has no other side effects at all. 1403static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 1404#define GET_NO_MEMORY_INTRINSICS 1405#include "llvm/Intrinsics.gen" 1406#undef GET_NO_MEMORY_INTRINSICS 1407 return false; 1408} 1409 1410// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 1411// have any side-effects or if it only reads memory. 1412static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 1413#define GET_SIDE_EFFECT_INFO 1414#include "llvm/Intrinsics.gen" 1415#undef GET_SIDE_EFFECT_INFO 1416 return false; 1417} 1418 1419/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 1420/// node. 1421void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 1422 unsigned Intrinsic) { 1423 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 1424 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 1425 1426 // Build the operand list. 1427 SmallVector<SDOperand, 8> Ops; 1428 if (HasChain) { // If this intrinsic has side-effects, chainify it. 1429 if (OnlyLoad) { 1430 // We don't need to serialize loads against other loads. 1431 Ops.push_back(DAG.getRoot()); 1432 } else { 1433 Ops.push_back(getRoot()); 1434 } 1435 } 1436 1437 // Add the intrinsic ID as an integer operand. 1438 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 1439 1440 // Add all operands of the call to the operand list. 1441 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1442 SDOperand Op = getValue(I.getOperand(i)); 1443 1444 // If this is a vector type, force it to the right packed type. 1445 if (Op.getValueType() == MVT::Vector) { 1446 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType()); 1447 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 1448 1449 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 1450 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 1451 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 1452 } 1453 1454 assert(TLI.isTypeLegal(Op.getValueType()) && 1455 "Intrinsic uses a non-legal type?"); 1456 Ops.push_back(Op); 1457 } 1458 1459 std::vector<MVT::ValueType> VTs; 1460 if (I.getType() != Type::VoidTy) { 1461 MVT::ValueType VT = TLI.getValueType(I.getType()); 1462 if (VT == MVT::Vector) { 1463 const PackedType *DestTy = cast<PackedType>(I.getType()); 1464 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1465 1466 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 1467 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 1468 } 1469 1470 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 1471 VTs.push_back(VT); 1472 } 1473 if (HasChain) 1474 VTs.push_back(MVT::Other); 1475 1476 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 1477 1478 // Create the node. 1479 SDOperand Result; 1480 if (!HasChain) 1481 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 1482 &Ops[0], Ops.size()); 1483 else if (I.getType() != Type::VoidTy) 1484 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 1485 &Ops[0], Ops.size()); 1486 else 1487 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 1488 &Ops[0], Ops.size()); 1489 1490 if (HasChain) { 1491 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 1492 if (OnlyLoad) 1493 PendingLoads.push_back(Chain); 1494 else 1495 DAG.setRoot(Chain); 1496 } 1497 if (I.getType() != Type::VoidTy) { 1498 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) { 1499 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 1500 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 1501 DAG.getConstant(PTy->getNumElements(), MVT::i32), 1502 DAG.getValueType(EVT)); 1503 } 1504 setValue(&I, Result); 1505 } 1506} 1507 1508/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 1509/// we want to emit this as a call to a named external function, return the name 1510/// otherwise lower it and return null. 1511const char * 1512SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 1513 switch (Intrinsic) { 1514 default: 1515 // By default, turn this into a target intrinsic node. 1516 visitTargetIntrinsic(I, Intrinsic); 1517 return 0; 1518 case Intrinsic::vastart: visitVAStart(I); return 0; 1519 case Intrinsic::vaend: visitVAEnd(I); return 0; 1520 case Intrinsic::vacopy: visitVACopy(I); return 0; 1521 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0; 1522 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0; 1523 case Intrinsic::setjmp: 1524 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 1525 break; 1526 case Intrinsic::longjmp: 1527 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 1528 break; 1529 case Intrinsic::memcpy_i32: 1530 case Intrinsic::memcpy_i64: 1531 visitMemIntrinsic(I, ISD::MEMCPY); 1532 return 0; 1533 case Intrinsic::memset_i32: 1534 case Intrinsic::memset_i64: 1535 visitMemIntrinsic(I, ISD::MEMSET); 1536 return 0; 1537 case Intrinsic::memmove_i32: 1538 case Intrinsic::memmove_i64: 1539 visitMemIntrinsic(I, ISD::MEMMOVE); 1540 return 0; 1541 1542 case Intrinsic::dbg_stoppoint: { 1543 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1544 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 1545 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) { 1546 SDOperand Ops[5]; 1547 1548 Ops[0] = getRoot(); 1549 Ops[1] = getValue(SPI.getLineValue()); 1550 Ops[2] = getValue(SPI.getColumnValue()); 1551 1552 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext()); 1553 assert(DD && "Not a debug information descriptor"); 1554 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 1555 1556 Ops[3] = DAG.getString(CompileUnit->getFileName()); 1557 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 1558 1559 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 1560 } 1561 1562 return 0; 1563 } 1564 case Intrinsic::dbg_region_start: { 1565 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1566 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 1567 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) { 1568 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext()); 1569 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(), 1570 DAG.getConstant(LabelID, MVT::i32))); 1571 } 1572 1573 return 0; 1574 } 1575 case Intrinsic::dbg_region_end: { 1576 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1577 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 1578 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) { 1579 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext()); 1580 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, 1581 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 1582 } 1583 1584 return 0; 1585 } 1586 case Intrinsic::dbg_func_start: { 1587 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1588 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 1589 if (DebugInfo && FSI.getSubprogram() && 1590 DebugInfo->Verify(FSI.getSubprogram())) { 1591 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram()); 1592 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, 1593 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 1594 } 1595 1596 return 0; 1597 } 1598 case Intrinsic::dbg_declare: { 1599 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 1600 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 1601 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) { 1602 SDOperand AddressOp = getValue(DI.getAddress()); 1603 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 1604 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex()); 1605 } 1606 1607 return 0; 1608 } 1609 1610 case Intrinsic::isunordered_f32: 1611 case Intrinsic::isunordered_f64: 1612 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)), 1613 getValue(I.getOperand(2)), ISD::SETUO)); 1614 return 0; 1615 1616 case Intrinsic::sqrt_f32: 1617 case Intrinsic::sqrt_f64: 1618 setValue(&I, DAG.getNode(ISD::FSQRT, 1619 getValue(I.getOperand(1)).getValueType(), 1620 getValue(I.getOperand(1)))); 1621 return 0; 1622 case Intrinsic::powi_f32: 1623 case Intrinsic::powi_f64: 1624 setValue(&I, DAG.getNode(ISD::FPOWI, 1625 getValue(I.getOperand(1)).getValueType(), 1626 getValue(I.getOperand(1)), 1627 getValue(I.getOperand(2)))); 1628 return 0; 1629 case Intrinsic::pcmarker: { 1630 SDOperand Tmp = getValue(I.getOperand(1)); 1631 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 1632 return 0; 1633 } 1634 case Intrinsic::readcyclecounter: { 1635 SDOperand Op = getRoot(); 1636 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 1637 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 1638 &Op, 1); 1639 setValue(&I, Tmp); 1640 DAG.setRoot(Tmp.getValue(1)); 1641 return 0; 1642 } 1643 case Intrinsic::bswap_i16: 1644 case Intrinsic::bswap_i32: 1645 case Intrinsic::bswap_i64: 1646 setValue(&I, DAG.getNode(ISD::BSWAP, 1647 getValue(I.getOperand(1)).getValueType(), 1648 getValue(I.getOperand(1)))); 1649 return 0; 1650 case Intrinsic::cttz_i8: 1651 case Intrinsic::cttz_i16: 1652 case Intrinsic::cttz_i32: 1653 case Intrinsic::cttz_i64: 1654 setValue(&I, DAG.getNode(ISD::CTTZ, 1655 getValue(I.getOperand(1)).getValueType(), 1656 getValue(I.getOperand(1)))); 1657 return 0; 1658 case Intrinsic::ctlz_i8: 1659 case Intrinsic::ctlz_i16: 1660 case Intrinsic::ctlz_i32: 1661 case Intrinsic::ctlz_i64: 1662 setValue(&I, DAG.getNode(ISD::CTLZ, 1663 getValue(I.getOperand(1)).getValueType(), 1664 getValue(I.getOperand(1)))); 1665 return 0; 1666 case Intrinsic::ctpop_i8: 1667 case Intrinsic::ctpop_i16: 1668 case Intrinsic::ctpop_i32: 1669 case Intrinsic::ctpop_i64: 1670 setValue(&I, DAG.getNode(ISD::CTPOP, 1671 getValue(I.getOperand(1)).getValueType(), 1672 getValue(I.getOperand(1)))); 1673 return 0; 1674 case Intrinsic::stacksave: { 1675 SDOperand Op = getRoot(); 1676 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 1677 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 1678 setValue(&I, Tmp); 1679 DAG.setRoot(Tmp.getValue(1)); 1680 return 0; 1681 } 1682 case Intrinsic::stackrestore: { 1683 SDOperand Tmp = getValue(I.getOperand(1)); 1684 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 1685 return 0; 1686 } 1687 case Intrinsic::prefetch: 1688 // FIXME: Currently discarding prefetches. 1689 return 0; 1690 } 1691} 1692 1693 1694void SelectionDAGLowering::visitCall(CallInst &I) { 1695 const char *RenameFn = 0; 1696 if (Function *F = I.getCalledFunction()) { 1697 if (F->isExternal()) 1698 if (unsigned IID = F->getIntrinsicID()) { 1699 RenameFn = visitIntrinsicCall(I, IID); 1700 if (!RenameFn) 1701 return; 1702 } else { // Not an LLVM intrinsic. 1703 const std::string &Name = F->getName(); 1704 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 1705 if (I.getNumOperands() == 3 && // Basic sanity checks. 1706 I.getOperand(1)->getType()->isFloatingPoint() && 1707 I.getType() == I.getOperand(1)->getType() && 1708 I.getType() == I.getOperand(2)->getType()) { 1709 SDOperand LHS = getValue(I.getOperand(1)); 1710 SDOperand RHS = getValue(I.getOperand(2)); 1711 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 1712 LHS, RHS)); 1713 return; 1714 } 1715 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 1716 if (I.getNumOperands() == 2 && // Basic sanity checks. 1717 I.getOperand(1)->getType()->isFloatingPoint() && 1718 I.getType() == I.getOperand(1)->getType()) { 1719 SDOperand Tmp = getValue(I.getOperand(1)); 1720 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 1721 return; 1722 } 1723 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 1724 if (I.getNumOperands() == 2 && // Basic sanity checks. 1725 I.getOperand(1)->getType()->isFloatingPoint() && 1726 I.getType() == I.getOperand(1)->getType()) { 1727 SDOperand Tmp = getValue(I.getOperand(1)); 1728 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 1729 return; 1730 } 1731 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 1732 if (I.getNumOperands() == 2 && // Basic sanity checks. 1733 I.getOperand(1)->getType()->isFloatingPoint() && 1734 I.getType() == I.getOperand(1)->getType()) { 1735 SDOperand Tmp = getValue(I.getOperand(1)); 1736 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 1737 return; 1738 } 1739 } 1740 } 1741 } else if (isa<InlineAsm>(I.getOperand(0))) { 1742 visitInlineAsm(I); 1743 return; 1744 } 1745 1746 SDOperand Callee; 1747 if (!RenameFn) 1748 Callee = getValue(I.getOperand(0)); 1749 else 1750 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 1751 std::vector<std::pair<SDOperand, const Type*> > Args; 1752 Args.reserve(I.getNumOperands()); 1753 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1754 Value *Arg = I.getOperand(i); 1755 SDOperand ArgNode = getValue(Arg); 1756 Args.push_back(std::make_pair(ArgNode, Arg->getType())); 1757 } 1758 1759 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); 1760 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1761 1762 std::pair<SDOperand,SDOperand> Result = 1763 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(), 1764 I.isTailCall(), Callee, Args, DAG); 1765 if (I.getType() != Type::VoidTy) 1766 setValue(&I, Result.first); 1767 DAG.setRoot(Result.second); 1768} 1769 1770SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 1771 SDOperand &Chain, SDOperand &Flag)const{ 1772 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 1773 Chain = Val.getValue(1); 1774 Flag = Val.getValue(2); 1775 1776 // If the result was expanded, copy from the top part. 1777 if (Regs.size() > 1) { 1778 assert(Regs.size() == 2 && 1779 "Cannot expand to more than 2 elts yet!"); 1780 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 1781 Chain = Hi.getValue(1); 1782 Flag = Hi.getValue(2); 1783 if (DAG.getTargetLoweringInfo().isLittleEndian()) 1784 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 1785 else 1786 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 1787 } 1788 1789 // Otherwise, if the return value was promoted or extended, truncate it to the 1790 // appropriate type. 1791 if (RegVT == ValueVT) 1792 return Val; 1793 1794 if (MVT::isInteger(RegVT)) { 1795 if (ValueVT < RegVT) 1796 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 1797 else 1798 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 1799 } else { 1800 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 1801 } 1802} 1803 1804/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 1805/// specified value into the registers specified by this object. This uses 1806/// Chain/Flag as the input and updates them for the output Chain/Flag. 1807void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 1808 SDOperand &Chain, SDOperand &Flag, 1809 MVT::ValueType PtrVT) const { 1810 if (Regs.size() == 1) { 1811 // If there is a single register and the types differ, this must be 1812 // a promotion. 1813 if (RegVT != ValueVT) { 1814 if (MVT::isInteger(RegVT)) { 1815 if (RegVT < ValueVT) 1816 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 1817 else 1818 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 1819 } else 1820 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 1821 } 1822 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 1823 Flag = Chain.getValue(1); 1824 } else { 1825 std::vector<unsigned> R(Regs); 1826 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 1827 std::reverse(R.begin(), R.end()); 1828 1829 for (unsigned i = 0, e = R.size(); i != e; ++i) { 1830 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 1831 DAG.getConstant(i, PtrVT)); 1832 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 1833 Flag = Chain.getValue(1); 1834 } 1835 } 1836} 1837 1838/// AddInlineAsmOperands - Add this value to the specified inlineasm node 1839/// operand list. This adds the code marker and includes the number of 1840/// values added into it. 1841void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 1842 std::vector<SDOperand> &Ops) const { 1843 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32)); 1844 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 1845 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 1846} 1847 1848/// isAllocatableRegister - If the specified register is safe to allocate, 1849/// i.e. it isn't a stack pointer or some other special register, return the 1850/// register class for the register. Otherwise, return null. 1851static const TargetRegisterClass * 1852isAllocatableRegister(unsigned Reg, MachineFunction &MF, 1853 const TargetLowering &TLI, const MRegisterInfo *MRI) { 1854 MVT::ValueType FoundVT = MVT::Other; 1855 const TargetRegisterClass *FoundRC = 0; 1856 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 1857 E = MRI->regclass_end(); RCI != E; ++RCI) { 1858 MVT::ValueType ThisVT = MVT::Other; 1859 1860 const TargetRegisterClass *RC = *RCI; 1861 // If none of the the value types for this register class are valid, we 1862 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1863 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1864 I != E; ++I) { 1865 if (TLI.isTypeLegal(*I)) { 1866 // If we have already found this register in a different register class, 1867 // choose the one with the largest VT specified. For example, on 1868 // PowerPC, we favor f64 register classes over f32. 1869 if (FoundVT == MVT::Other || 1870 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 1871 ThisVT = *I; 1872 break; 1873 } 1874 } 1875 } 1876 1877 if (ThisVT == MVT::Other) continue; 1878 1879 // NOTE: This isn't ideal. In particular, this might allocate the 1880 // frame pointer in functions that need it (due to them not being taken 1881 // out of allocation, because a variable sized allocation hasn't been seen 1882 // yet). This is a slight code pessimization, but should still work. 1883 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 1884 E = RC->allocation_order_end(MF); I != E; ++I) 1885 if (*I == Reg) { 1886 // We found a matching register class. Keep looking at others in case 1887 // we find one with larger registers that this physreg is also in. 1888 FoundRC = RC; 1889 FoundVT = ThisVT; 1890 break; 1891 } 1892 } 1893 return FoundRC; 1894} 1895 1896RegsForValue SelectionDAGLowering:: 1897GetRegistersForValue(const std::string &ConstrCode, 1898 MVT::ValueType VT, bool isOutReg, bool isInReg, 1899 std::set<unsigned> &OutputRegs, 1900 std::set<unsigned> &InputRegs) { 1901 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 1902 TLI.getRegForInlineAsmConstraint(ConstrCode, VT); 1903 std::vector<unsigned> Regs; 1904 1905 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1; 1906 MVT::ValueType RegVT; 1907 MVT::ValueType ValueVT = VT; 1908 1909 if (PhysReg.first) { 1910 if (VT == MVT::Other) 1911 ValueVT = *PhysReg.second->vt_begin(); 1912 1913 // Get the actual register value type. This is important, because the user 1914 // may have asked for (e.g.) the AX register in i32 type. We need to 1915 // remember that AX is actually i16 to get the right extension. 1916 RegVT = *PhysReg.second->vt_begin(); 1917 1918 // This is a explicit reference to a physical register. 1919 Regs.push_back(PhysReg.first); 1920 1921 // If this is an expanded reference, add the rest of the regs to Regs. 1922 if (NumRegs != 1) { 1923 TargetRegisterClass::iterator I = PhysReg.second->begin(); 1924 TargetRegisterClass::iterator E = PhysReg.second->end(); 1925 for (; *I != PhysReg.first; ++I) 1926 assert(I != E && "Didn't find reg!"); 1927 1928 // Already added the first reg. 1929 --NumRegs; ++I; 1930 for (; NumRegs; --NumRegs, ++I) { 1931 assert(I != E && "Ran out of registers to allocate!"); 1932 Regs.push_back(*I); 1933 } 1934 } 1935 return RegsForValue(Regs, RegVT, ValueVT); 1936 } 1937 1938 // This is a reference to a register class. Allocate NumRegs consecutive, 1939 // available, registers from the class. 1940 std::vector<unsigned> RegClassRegs = 1941 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT); 1942 1943 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 1944 MachineFunction &MF = *CurMBB->getParent(); 1945 unsigned NumAllocated = 0; 1946 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 1947 unsigned Reg = RegClassRegs[i]; 1948 // See if this register is available. 1949 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 1950 (isInReg && InputRegs.count(Reg))) { // Already used. 1951 // Make sure we find consecutive registers. 1952 NumAllocated = 0; 1953 continue; 1954 } 1955 1956 // Check to see if this register is allocatable (i.e. don't give out the 1957 // stack pointer). 1958 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 1959 if (!RC) { 1960 // Make sure we find consecutive registers. 1961 NumAllocated = 0; 1962 continue; 1963 } 1964 1965 // Okay, this register is good, we can use it. 1966 ++NumAllocated; 1967 1968 // If we allocated enough consecutive 1969 if (NumAllocated == NumRegs) { 1970 unsigned RegStart = (i-NumAllocated)+1; 1971 unsigned RegEnd = i+1; 1972 // Mark all of the allocated registers used. 1973 for (unsigned i = RegStart; i != RegEnd; ++i) { 1974 unsigned Reg = RegClassRegs[i]; 1975 Regs.push_back(Reg); 1976 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used. 1977 if (isInReg) InputRegs.insert(Reg); // Mark reg used. 1978 } 1979 1980 return RegsForValue(Regs, *RC->vt_begin(), VT); 1981 } 1982 } 1983 1984 // Otherwise, we couldn't allocate enough registers for this. 1985 return RegsForValue(); 1986} 1987 1988 1989/// visitInlineAsm - Handle a call to an InlineAsm object. 1990/// 1991void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 1992 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 1993 1994 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 1995 MVT::Other); 1996 1997 // Note, we treat inline asms both with and without side-effects as the same. 1998 // If an inline asm doesn't have side effects and doesn't access memory, we 1999 // could not choose to not chain it. 2000 bool hasSideEffects = IA->hasSideEffects(); 2001 2002 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 2003 std::vector<MVT::ValueType> ConstraintVTs; 2004 2005 /// AsmNodeOperands - A list of pairs. The first element is a register, the 2006 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set 2007 /// if it is a def of that register. 2008 std::vector<SDOperand> AsmNodeOperands; 2009 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 2010 AsmNodeOperands.push_back(AsmStr); 2011 2012 SDOperand Chain = getRoot(); 2013 SDOperand Flag; 2014 2015 // We fully assign registers here at isel time. This is not optimal, but 2016 // should work. For register classes that correspond to LLVM classes, we 2017 // could let the LLVM RA do its thing, but we currently don't. Do a prepass 2018 // over the constraints, collecting fixed registers that we know we can't use. 2019 std::set<unsigned> OutputRegs, InputRegs; 2020 unsigned OpNum = 1; 2021 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2022 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2023 std::string &ConstraintCode = Constraints[i].Codes[0]; 2024 2025 MVT::ValueType OpVT; 2026 2027 // Compute the value type for each operand and add it to ConstraintVTs. 2028 switch (Constraints[i].Type) { 2029 case InlineAsm::isOutput: 2030 if (!Constraints[i].isIndirectOutput) { 2031 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2032 OpVT = TLI.getValueType(I.getType()); 2033 } else { 2034 const Type *OpTy = I.getOperand(OpNum)->getType(); 2035 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType()); 2036 OpNum++; // Consumes a call operand. 2037 } 2038 break; 2039 case InlineAsm::isInput: 2040 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType()); 2041 OpNum++; // Consumes a call operand. 2042 break; 2043 case InlineAsm::isClobber: 2044 OpVT = MVT::Other; 2045 break; 2046 } 2047 2048 ConstraintVTs.push_back(OpVT); 2049 2050 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0) 2051 continue; // Not assigned a fixed reg. 2052 2053 // Build a list of regs that this operand uses. This always has a single 2054 // element for promoted/expanded operands. 2055 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT, 2056 false, false, 2057 OutputRegs, InputRegs); 2058 2059 switch (Constraints[i].Type) { 2060 case InlineAsm::isOutput: 2061 // We can't assign any other output to this register. 2062 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2063 // If this is an early-clobber output, it cannot be assigned to the same 2064 // value as the input reg. 2065 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2066 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2067 break; 2068 case InlineAsm::isInput: 2069 // We can't assign any other input to this register. 2070 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2071 break; 2072 case InlineAsm::isClobber: 2073 // Clobbered regs cannot be used as inputs or outputs. 2074 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2075 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2076 break; 2077 } 2078 } 2079 2080 // Loop over all of the inputs, copying the operand values into the 2081 // appropriate registers and processing the output regs. 2082 RegsForValue RetValRegs; 2083 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 2084 OpNum = 1; 2085 2086 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2087 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2088 std::string &ConstraintCode = Constraints[i].Codes[0]; 2089 2090 switch (Constraints[i].Type) { 2091 case InlineAsm::isOutput: { 2092 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2093 if (ConstraintCode.size() == 1) // not a physreg name. 2094 CTy = TLI.getConstraintType(ConstraintCode[0]); 2095 2096 if (CTy == TargetLowering::C_Memory) { 2097 // Memory output. 2098 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2099 2100 // Check that the operand (the address to store to) isn't a float. 2101 if (!MVT::isInteger(InOperandVal.getValueType())) 2102 assert(0 && "MATCH FAIL!"); 2103 2104 if (!Constraints[i].isIndirectOutput) 2105 assert(0 && "MATCH FAIL!"); 2106 2107 OpNum++; // Consumes a call operand. 2108 2109 // Extend/truncate to the right pointer type if needed. 2110 MVT::ValueType PtrType = TLI.getPointerTy(); 2111 if (InOperandVal.getValueType() < PtrType) 2112 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2113 else if (InOperandVal.getValueType() > PtrType) 2114 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2115 2116 // Add information to the INLINEASM node to know about this output. 2117 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2118 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2119 AsmNodeOperands.push_back(InOperandVal); 2120 break; 2121 } 2122 2123 // Otherwise, this is a register output. 2124 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2125 2126 // If this is an early-clobber output, or if there is an input 2127 // constraint that matches this, we need to reserve the input register 2128 // so no other inputs allocate to it. 2129 bool UsesInputRegister = false; 2130 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2131 UsesInputRegister = true; 2132 2133 // Copy the output from the appropriate register. Find a register that 2134 // we can use. 2135 RegsForValue Regs = 2136 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2137 true, UsesInputRegister, 2138 OutputRegs, InputRegs); 2139 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!"); 2140 2141 if (!Constraints[i].isIndirectOutput) { 2142 assert(RetValRegs.Regs.empty() && 2143 "Cannot have multiple output constraints yet!"); 2144 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2145 RetValRegs = Regs; 2146 } else { 2147 IndirectStoresToEmit.push_back(std::make_pair(Regs, 2148 I.getOperand(OpNum))); 2149 OpNum++; // Consumes a call operand. 2150 } 2151 2152 // Add information to the INLINEASM node to know that this register is 2153 // set. 2154 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands); 2155 break; 2156 } 2157 case InlineAsm::isInput: { 2158 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2159 OpNum++; // Consumes a call operand. 2160 2161 if (isdigit(ConstraintCode[0])) { // Matching constraint? 2162 // If this is required to match an output register we have already set, 2163 // just use its register. 2164 unsigned OperandNo = atoi(ConstraintCode.c_str()); 2165 2166 // Scan until we find the definition we already emitted of this operand. 2167 // When we find it, create a RegsForValue operand. 2168 unsigned CurOp = 2; // The first operand. 2169 for (; OperandNo; --OperandNo) { 2170 // Advance to the next operand. 2171 unsigned NumOps = 2172 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2173 assert(((NumOps & 7) == 2 /*REGDEF*/ || 2174 (NumOps & 7) == 4 /*MEM*/) && 2175 "Skipped past definitions?"); 2176 CurOp += (NumOps>>3)+1; 2177 } 2178 2179 unsigned NumOps = 2180 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2181 assert((NumOps & 7) == 2 /*REGDEF*/ && 2182 "Skipped past definitions?"); 2183 2184 // Add NumOps>>3 registers to MatchedRegs. 2185 RegsForValue MatchedRegs; 2186 MatchedRegs.ValueVT = InOperandVal.getValueType(); 2187 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 2188 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 2189 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 2190 MatchedRegs.Regs.push_back(Reg); 2191 } 2192 2193 // Use the produced MatchedRegs object to 2194 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 2195 TLI.getPointerTy()); 2196 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 2197 break; 2198 } 2199 2200 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2201 if (ConstraintCode.size() == 1) // not a physreg name. 2202 CTy = TLI.getConstraintType(ConstraintCode[0]); 2203 2204 if (CTy == TargetLowering::C_Other) { 2205 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0])) 2206 assert(0 && "MATCH FAIL!"); 2207 2208 // Add information to the INLINEASM node to know about this input. 2209 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 2210 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2211 AsmNodeOperands.push_back(InOperandVal); 2212 break; 2213 } else if (CTy == TargetLowering::C_Memory) { 2214 // Memory input. 2215 2216 // Check that the operand isn't a float. 2217 if (!MVT::isInteger(InOperandVal.getValueType())) 2218 assert(0 && "MATCH FAIL!"); 2219 2220 // Extend/truncate to the right pointer type if needed. 2221 MVT::ValueType PtrType = TLI.getPointerTy(); 2222 if (InOperandVal.getValueType() < PtrType) 2223 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2224 else if (InOperandVal.getValueType() > PtrType) 2225 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2226 2227 // Add information to the INLINEASM node to know about this input. 2228 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2229 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2230 AsmNodeOperands.push_back(InOperandVal); 2231 break; 2232 } 2233 2234 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2235 2236 // Copy the input into the appropriate registers. 2237 RegsForValue InRegs = 2238 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2239 false, true, OutputRegs, InputRegs); 2240 // FIXME: should be match fail. 2241 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!"); 2242 2243 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy()); 2244 2245 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); 2246 break; 2247 } 2248 case InlineAsm::isClobber: { 2249 RegsForValue ClobberedRegs = 2250 GetRegistersForValue(ConstraintCode, MVT::Other, false, false, 2251 OutputRegs, InputRegs); 2252 // Add the clobbered value to the operand list, so that the register 2253 // allocator is aware that the physreg got clobbered. 2254 if (!ClobberedRegs.Regs.empty()) 2255 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands); 2256 break; 2257 } 2258 } 2259 } 2260 2261 // Finish up input operands. 2262 AsmNodeOperands[0] = Chain; 2263 if (Flag.Val) AsmNodeOperands.push_back(Flag); 2264 2265 Chain = DAG.getNode(ISD::INLINEASM, 2266 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 2267 &AsmNodeOperands[0], AsmNodeOperands.size()); 2268 Flag = Chain.getValue(1); 2269 2270 // If this asm returns a register value, copy the result from that register 2271 // and set it as the value of the call. 2272 if (!RetValRegs.Regs.empty()) 2273 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag)); 2274 2275 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 2276 2277 // Process indirect outputs, first output all of the flagged copies out of 2278 // physregs. 2279 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 2280 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 2281 Value *Ptr = IndirectStoresToEmit[i].second; 2282 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 2283 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 2284 } 2285 2286 // Emit the non-flagged stores from the physregs. 2287 SmallVector<SDOperand, 8> OutChains; 2288 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 2289 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 2290 getValue(StoresToEmit[i].second), 2291 StoresToEmit[i].second, 0)); 2292 if (!OutChains.empty()) 2293 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2294 &OutChains[0], OutChains.size()); 2295 DAG.setRoot(Chain); 2296} 2297 2298 2299void SelectionDAGLowering::visitMalloc(MallocInst &I) { 2300 SDOperand Src = getValue(I.getOperand(0)); 2301 2302 MVT::ValueType IntPtr = TLI.getPointerTy(); 2303 2304 if (IntPtr < Src.getValueType()) 2305 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 2306 else if (IntPtr > Src.getValueType()) 2307 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 2308 2309 // Scale the source by the type size. 2310 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 2311 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 2312 Src, getIntPtrConstant(ElementSize)); 2313 2314 std::vector<std::pair<SDOperand, const Type*> > Args; 2315 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType())); 2316 2317 std::pair<SDOperand,SDOperand> Result = 2318 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true, 2319 DAG.getExternalSymbol("malloc", IntPtr), 2320 Args, DAG); 2321 setValue(&I, Result.first); // Pointers always fit in registers 2322 DAG.setRoot(Result.second); 2323} 2324 2325void SelectionDAGLowering::visitFree(FreeInst &I) { 2326 std::vector<std::pair<SDOperand, const Type*> > Args; 2327 Args.push_back(std::make_pair(getValue(I.getOperand(0)), 2328 TLI.getTargetData()->getIntPtrType())); 2329 MVT::ValueType IntPtr = TLI.getPointerTy(); 2330 std::pair<SDOperand,SDOperand> Result = 2331 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true, 2332 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 2333 DAG.setRoot(Result.second); 2334} 2335 2336// InsertAtEndOfBasicBlock - This method should be implemented by targets that 2337// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 2338// instructions are special in various ways, which require special support to 2339// insert. The specified MachineInstr is created but not inserted into any 2340// basic blocks, and the scheduler passes ownership of it to this method. 2341MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2342 MachineBasicBlock *MBB) { 2343 std::cerr << "If a target marks an instruction with " 2344 "'usesCustomDAGSchedInserter', it must implement " 2345 "TargetLowering::InsertAtEndOfBasicBlock!\n"; 2346 abort(); 2347 return 0; 2348} 2349 2350void SelectionDAGLowering::visitVAStart(CallInst &I) { 2351 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 2352 getValue(I.getOperand(1)), 2353 DAG.getSrcValue(I.getOperand(1)))); 2354} 2355 2356void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 2357 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 2358 getValue(I.getOperand(0)), 2359 DAG.getSrcValue(I.getOperand(0))); 2360 setValue(&I, V); 2361 DAG.setRoot(V.getValue(1)); 2362} 2363 2364void SelectionDAGLowering::visitVAEnd(CallInst &I) { 2365 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 2366 getValue(I.getOperand(1)), 2367 DAG.getSrcValue(I.getOperand(1)))); 2368} 2369 2370void SelectionDAGLowering::visitVACopy(CallInst &I) { 2371 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 2372 getValue(I.getOperand(1)), 2373 getValue(I.getOperand(2)), 2374 DAG.getSrcValue(I.getOperand(1)), 2375 DAG.getSrcValue(I.getOperand(2)))); 2376} 2377 2378/// TargetLowering::LowerArguments - This is the default LowerArguments 2379/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 2380/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 2381/// integrated into SDISel. 2382std::vector<SDOperand> 2383TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 2384 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 2385 std::vector<SDOperand> Ops; 2386 Ops.push_back(DAG.getRoot()); 2387 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 2388 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 2389 2390 // Add one result value for each formal argument. 2391 std::vector<MVT::ValueType> RetVals; 2392 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2393 MVT::ValueType VT = getValueType(I->getType()); 2394 2395 switch (getTypeAction(VT)) { 2396 default: assert(0 && "Unknown type action!"); 2397 case Legal: 2398 RetVals.push_back(VT); 2399 break; 2400 case Promote: 2401 RetVals.push_back(getTypeToTransformTo(VT)); 2402 break; 2403 case Expand: 2404 if (VT != MVT::Vector) { 2405 // If this is a large integer, it needs to be broken up into small 2406 // integers. Figure out what the destination type is and how many small 2407 // integers it turns into. 2408 MVT::ValueType NVT = getTypeToTransformTo(VT); 2409 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2410 for (unsigned i = 0; i != NumVals; ++i) 2411 RetVals.push_back(NVT); 2412 } else { 2413 // Otherwise, this is a vector type. We only support legal vectors 2414 // right now. 2415 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements(); 2416 const Type *EltTy = cast<PackedType>(I->getType())->getElementType(); 2417 2418 // Figure out if there is a Packed type corresponding to this Vector 2419 // type. If so, convert to the packed type. 2420 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2421 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2422 RetVals.push_back(TVT); 2423 } else { 2424 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2425 } 2426 } 2427 break; 2428 } 2429 } 2430 2431 RetVals.push_back(MVT::Other); 2432 2433 // Create the node. 2434 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 2435 DAG.getNodeValueTypes(RetVals), RetVals.size(), 2436 &Ops[0], Ops.size()).Val; 2437 2438 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 2439 2440 // Set up the return result vector. 2441 Ops.clear(); 2442 unsigned i = 0; 2443 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2444 MVT::ValueType VT = getValueType(I->getType()); 2445 2446 switch (getTypeAction(VT)) { 2447 default: assert(0 && "Unknown type action!"); 2448 case Legal: 2449 Ops.push_back(SDOperand(Result, i++)); 2450 break; 2451 case Promote: { 2452 SDOperand Op(Result, i++); 2453 if (MVT::isInteger(VT)) { 2454 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 2455 : ISD::AssertZext; 2456 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT)); 2457 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2458 } else { 2459 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2460 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 2461 } 2462 Ops.push_back(Op); 2463 break; 2464 } 2465 case Expand: 2466 if (VT != MVT::Vector) { 2467 // If this is a large integer, it needs to be reassembled from small 2468 // integers. Figure out what the source elt type is and how many small 2469 // integers it is. 2470 MVT::ValueType NVT = getTypeToTransformTo(VT); 2471 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2472 if (NumVals == 2) { 2473 SDOperand Lo = SDOperand(Result, i++); 2474 SDOperand Hi = SDOperand(Result, i++); 2475 2476 if (!isLittleEndian()) 2477 std::swap(Lo, Hi); 2478 2479 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi)); 2480 } else { 2481 // Value scalarized into many values. Unimp for now. 2482 assert(0 && "Cannot expand i64 -> i16 yet!"); 2483 } 2484 } else { 2485 // Otherwise, this is a vector type. We only support legal vectors 2486 // right now. 2487 const PackedType *PTy = cast<PackedType>(I->getType()); 2488 unsigned NumElems = PTy->getNumElements(); 2489 const Type *EltTy = PTy->getElementType(); 2490 2491 // Figure out if there is a Packed type corresponding to this Vector 2492 // type. If so, convert to the packed type. 2493 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2494 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2495 SDOperand N = SDOperand(Result, i++); 2496 // Handle copies from generic vectors to registers. 2497 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 2498 DAG.getConstant(NumElems, MVT::i32), 2499 DAG.getValueType(getValueType(EltTy))); 2500 Ops.push_back(N); 2501 } else { 2502 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2503 abort(); 2504 } 2505 } 2506 break; 2507 } 2508 } 2509 return Ops; 2510} 2511 2512 2513/// TargetLowering::LowerCallTo - This is the default LowerCallTo 2514/// implementation, which just inserts an ISD::CALL node, which is later custom 2515/// lowered by the target to something concrete. FIXME: When all targets are 2516/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 2517std::pair<SDOperand, SDOperand> 2518TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 2519 unsigned CallingConv, bool isTailCall, 2520 SDOperand Callee, 2521 ArgListTy &Args, SelectionDAG &DAG) { 2522 SmallVector<SDOperand, 32> Ops; 2523 Ops.push_back(Chain); // Op#0 - Chain 2524 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 2525 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 2526 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 2527 Ops.push_back(Callee); 2528 2529 // Handle all of the outgoing arguments. 2530 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 2531 MVT::ValueType VT = getValueType(Args[i].second); 2532 SDOperand Op = Args[i].first; 2533 bool isSigned = Args[i].second->isSigned(); 2534 switch (getTypeAction(VT)) { 2535 default: assert(0 && "Unknown type action!"); 2536 case Legal: 2537 Ops.push_back(Op); 2538 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2539 break; 2540 case Promote: 2541 if (MVT::isInteger(VT)) { 2542 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 2543 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 2544 } else { 2545 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2546 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 2547 } 2548 Ops.push_back(Op); 2549 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2550 break; 2551 case Expand: 2552 if (VT != MVT::Vector) { 2553 // If this is a large integer, it needs to be broken down into small 2554 // integers. Figure out what the source elt type is and how many small 2555 // integers it is. 2556 MVT::ValueType NVT = getTypeToTransformTo(VT); 2557 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2558 if (NumVals == 2) { 2559 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, 2560 DAG.getConstant(0, getPointerTy())); 2561 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, 2562 DAG.getConstant(1, getPointerTy())); 2563 if (!isLittleEndian()) 2564 std::swap(Lo, Hi); 2565 2566 Ops.push_back(Lo); 2567 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2568 Ops.push_back(Hi); 2569 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2570 } else { 2571 // Value scalarized into many values. Unimp for now. 2572 assert(0 && "Cannot expand i64 -> i16 yet!"); 2573 } 2574 } else { 2575 // Otherwise, this is a vector type. We only support legal vectors 2576 // right now. 2577 const PackedType *PTy = cast<PackedType>(Args[i].second); 2578 unsigned NumElems = PTy->getNumElements(); 2579 const Type *EltTy = PTy->getElementType(); 2580 2581 // Figure out if there is a Packed type corresponding to this Vector 2582 // type. If so, convert to the packed type. 2583 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2584 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2585 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. 2586 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 2587 Ops.push_back(Op); 2588 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 2589 } else { 2590 assert(0 && "Don't support illegal by-val vector call args yet!"); 2591 abort(); 2592 } 2593 } 2594 break; 2595 } 2596 } 2597 2598 // Figure out the result value types. 2599 SmallVector<MVT::ValueType, 4> RetTys; 2600 2601 if (RetTy != Type::VoidTy) { 2602 MVT::ValueType VT = getValueType(RetTy); 2603 switch (getTypeAction(VT)) { 2604 default: assert(0 && "Unknown type action!"); 2605 case Legal: 2606 RetTys.push_back(VT); 2607 break; 2608 case Promote: 2609 RetTys.push_back(getTypeToTransformTo(VT)); 2610 break; 2611 case Expand: 2612 if (VT != MVT::Vector) { 2613 // If this is a large integer, it needs to be reassembled from small 2614 // integers. Figure out what the source elt type is and how many small 2615 // integers it is. 2616 MVT::ValueType NVT = getTypeToTransformTo(VT); 2617 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); 2618 for (unsigned i = 0; i != NumVals; ++i) 2619 RetTys.push_back(NVT); 2620 } else { 2621 // Otherwise, this is a vector type. We only support legal vectors 2622 // right now. 2623 const PackedType *PTy = cast<PackedType>(RetTy); 2624 unsigned NumElems = PTy->getNumElements(); 2625 const Type *EltTy = PTy->getElementType(); 2626 2627 // Figure out if there is a Packed type corresponding to this Vector 2628 // type. If so, convert to the packed type. 2629 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2630 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2631 RetTys.push_back(TVT); 2632 } else { 2633 assert(0 && "Don't support illegal by-val vector call results yet!"); 2634 abort(); 2635 } 2636 } 2637 } 2638 } 2639 2640 RetTys.push_back(MVT::Other); // Always has a chain. 2641 2642 // Finally, create the CALL node. 2643 SDOperand Res = DAG.getNode(ISD::CALL, 2644 DAG.getVTList(&RetTys[0], RetTys.size()), 2645 &Ops[0], Ops.size()); 2646 2647 // This returns a pair of operands. The first element is the 2648 // return value for the function (if RetTy is not VoidTy). The second 2649 // element is the outgoing token chain. 2650 SDOperand ResVal; 2651 if (RetTys.size() != 1) { 2652 MVT::ValueType VT = getValueType(RetTy); 2653 if (RetTys.size() == 2) { 2654 ResVal = Res; 2655 2656 // If this value was promoted, truncate it down. 2657 if (ResVal.getValueType() != VT) { 2658 if (VT == MVT::Vector) { 2659 // Insert a VBITCONVERT to convert from the packed result type to the 2660 // MVT::Vector type. 2661 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements(); 2662 const Type *EltTy = cast<PackedType>(RetTy)->getElementType(); 2663 2664 // Figure out if there is a Packed type corresponding to this Vector 2665 // type. If so, convert to the packed type. 2666 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2667 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2668 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 2669 // "N x PTyElementVT" MVT::Vector type. 2670 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 2671 DAG.getConstant(NumElems, MVT::i32), 2672 DAG.getValueType(getValueType(EltTy))); 2673 } else { 2674 abort(); 2675 } 2676 } else if (MVT::isInteger(VT)) { 2677 unsigned AssertOp = RetTy->isSigned() ? 2678 ISD::AssertSext : ISD::AssertZext; 2679 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 2680 DAG.getValueType(VT)); 2681 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 2682 } else { 2683 assert(MVT::isFloatingPoint(VT)); 2684 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 2685 } 2686 } 2687 } else if (RetTys.size() == 3) { 2688 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 2689 Res.getValue(0), Res.getValue(1)); 2690 2691 } else { 2692 assert(0 && "Case not handled yet!"); 2693 } 2694 } 2695 2696 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 2697} 2698 2699 2700 2701// It is always conservatively correct for llvm.returnaddress and 2702// llvm.frameaddress to return 0. 2703// 2704// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be 2705// expanded to 0 if the target wants. 2706std::pair<SDOperand, SDOperand> 2707TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, 2708 unsigned Depth, SelectionDAG &DAG) { 2709 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain); 2710} 2711 2712SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2713 assert(0 && "LowerOperation not implemented for this target!"); 2714 abort(); 2715 return SDOperand(); 2716} 2717 2718SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 2719 SelectionDAG &DAG) { 2720 assert(0 && "CustomPromoteOperation not implemented for this target!"); 2721 abort(); 2722 return SDOperand(); 2723} 2724 2725void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) { 2726 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue(); 2727 std::pair<SDOperand,SDOperand> Result = 2728 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG); 2729 setValue(&I, Result.first); 2730 DAG.setRoot(Result.second); 2731} 2732 2733/// getMemsetValue - Vectorized representation of the memset value 2734/// operand. 2735static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 2736 SelectionDAG &DAG) { 2737 MVT::ValueType CurVT = VT; 2738 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2739 uint64_t Val = C->getValue() & 255; 2740 unsigned Shift = 8; 2741 while (CurVT != MVT::i8) { 2742 Val = (Val << Shift) | Val; 2743 Shift <<= 1; 2744 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 2745 } 2746 return DAG.getConstant(Val, VT); 2747 } else { 2748 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2749 unsigned Shift = 8; 2750 while (CurVT != MVT::i8) { 2751 Value = 2752 DAG.getNode(ISD::OR, VT, 2753 DAG.getNode(ISD::SHL, VT, Value, 2754 DAG.getConstant(Shift, MVT::i8)), Value); 2755 Shift <<= 1; 2756 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 2757 } 2758 2759 return Value; 2760 } 2761} 2762 2763/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2764/// used when a memcpy is turned into a memset when the source is a constant 2765/// string ptr. 2766static SDOperand getMemsetStringVal(MVT::ValueType VT, 2767 SelectionDAG &DAG, TargetLowering &TLI, 2768 std::string &Str, unsigned Offset) { 2769 MVT::ValueType CurVT = VT; 2770 uint64_t Val = 0; 2771 unsigned MSB = getSizeInBits(VT) / 8; 2772 if (TLI.isLittleEndian()) 2773 Offset = Offset + MSB - 1; 2774 for (unsigned i = 0; i != MSB; ++i) { 2775 Val = (Val << 8) | Str[Offset]; 2776 Offset += TLI.isLittleEndian() ? -1 : 1; 2777 } 2778 return DAG.getConstant(Val, VT); 2779} 2780 2781/// getMemBasePlusOffset - Returns base and offset node for the 2782static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 2783 SelectionDAG &DAG, TargetLowering &TLI) { 2784 MVT::ValueType VT = Base.getValueType(); 2785 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2786} 2787 2788/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2789/// to replace the memset / memcpy is below the threshold. It also returns the 2790/// types of the sequence of memory ops to perform memset / memcpy. 2791static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 2792 unsigned Limit, uint64_t Size, 2793 unsigned Align, TargetLowering &TLI) { 2794 MVT::ValueType VT; 2795 2796 if (TLI.allowsUnalignedMemoryAccesses()) { 2797 VT = MVT::i64; 2798 } else { 2799 switch (Align & 7) { 2800 case 0: 2801 VT = MVT::i64; 2802 break; 2803 case 4: 2804 VT = MVT::i32; 2805 break; 2806 case 2: 2807 VT = MVT::i16; 2808 break; 2809 default: 2810 VT = MVT::i8; 2811 break; 2812 } 2813 } 2814 2815 MVT::ValueType LVT = MVT::i64; 2816 while (!TLI.isTypeLegal(LVT)) 2817 LVT = (MVT::ValueType)((unsigned)LVT - 1); 2818 assert(MVT::isInteger(LVT)); 2819 2820 if (VT > LVT) 2821 VT = LVT; 2822 2823 unsigned NumMemOps = 0; 2824 while (Size != 0) { 2825 unsigned VTSize = getSizeInBits(VT) / 8; 2826 while (VTSize > Size) { 2827 VT = (MVT::ValueType)((unsigned)VT - 1); 2828 VTSize >>= 1; 2829 } 2830 assert(MVT::isInteger(VT)); 2831 2832 if (++NumMemOps > Limit) 2833 return false; 2834 MemOps.push_back(VT); 2835 Size -= VTSize; 2836 } 2837 2838 return true; 2839} 2840 2841void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 2842 SDOperand Op1 = getValue(I.getOperand(1)); 2843 SDOperand Op2 = getValue(I.getOperand(2)); 2844 SDOperand Op3 = getValue(I.getOperand(3)); 2845 SDOperand Op4 = getValue(I.getOperand(4)); 2846 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 2847 if (Align == 0) Align = 1; 2848 2849 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 2850 std::vector<MVT::ValueType> MemOps; 2851 2852 // Expand memset / memcpy to a series of load / store ops 2853 // if the size operand falls below a certain threshold. 2854 SmallVector<SDOperand, 8> OutChains; 2855 switch (Op) { 2856 default: break; // Do nothing for now. 2857 case ISD::MEMSET: { 2858 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 2859 Size->getValue(), Align, TLI)) { 2860 unsigned NumMemOps = MemOps.size(); 2861 unsigned Offset = 0; 2862 for (unsigned i = 0; i < NumMemOps; i++) { 2863 MVT::ValueType VT = MemOps[i]; 2864 unsigned VTSize = getSizeInBits(VT) / 8; 2865 SDOperand Value = getMemsetValue(Op2, VT, DAG); 2866 SDOperand Store = DAG.getStore(getRoot(), Value, 2867 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 2868 I.getOperand(1), Offset); 2869 OutChains.push_back(Store); 2870 Offset += VTSize; 2871 } 2872 } 2873 break; 2874 } 2875 case ISD::MEMCPY: { 2876 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 2877 Size->getValue(), Align, TLI)) { 2878 unsigned NumMemOps = MemOps.size(); 2879 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 2880 GlobalAddressSDNode *G = NULL; 2881 std::string Str; 2882 bool CopyFromStr = false; 2883 2884 if (Op2.getOpcode() == ISD::GlobalAddress) 2885 G = cast<GlobalAddressSDNode>(Op2); 2886 else if (Op2.getOpcode() == ISD::ADD && 2887 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 2888 Op2.getOperand(1).getOpcode() == ISD::Constant) { 2889 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 2890 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 2891 } 2892 if (G) { 2893 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2894 if (GV) { 2895 Str = GV->getStringValue(false); 2896 if (!Str.empty()) { 2897 CopyFromStr = true; 2898 SrcOff += SrcDelta; 2899 } 2900 } 2901 } 2902 2903 for (unsigned i = 0; i < NumMemOps; i++) { 2904 MVT::ValueType VT = MemOps[i]; 2905 unsigned VTSize = getSizeInBits(VT) / 8; 2906 SDOperand Value, Chain, Store; 2907 2908 if (CopyFromStr) { 2909 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2910 Chain = getRoot(); 2911 Store = 2912 DAG.getStore(Chain, Value, 2913 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 2914 I.getOperand(1), DstOff); 2915 } else { 2916 Value = DAG.getLoad(VT, getRoot(), 2917 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 2918 I.getOperand(2), SrcOff); 2919 Chain = Value.getValue(1); 2920 Store = 2921 DAG.getStore(Chain, Value, 2922 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 2923 I.getOperand(1), DstOff); 2924 } 2925 OutChains.push_back(Store); 2926 SrcOff += VTSize; 2927 DstOff += VTSize; 2928 } 2929 } 2930 break; 2931 } 2932 } 2933 2934 if (!OutChains.empty()) { 2935 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 2936 &OutChains[0], OutChains.size())); 2937 return; 2938 } 2939 } 2940 2941 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 2942} 2943 2944//===----------------------------------------------------------------------===// 2945// SelectionDAGISel code 2946//===----------------------------------------------------------------------===// 2947 2948unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 2949 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 2950} 2951 2952void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 2953 // FIXME: we only modify the CFG to split critical edges. This 2954 // updates dom and loop info. 2955 AU.addRequired<AliasAnalysis>(); 2956} 2957 2958 2959/// OptimizeNoopCopyExpression - We have determined that the specified cast 2960/// instruction is a noop copy (e.g. it's casting from one pointer type to 2961/// another, int->uint, or int->sbyte on PPC. 2962/// 2963/// Return true if any changes are made. 2964static bool OptimizeNoopCopyExpression(CastInst *CI) { 2965 BasicBlock *DefBB = CI->getParent(); 2966 2967 /// InsertedCasts - Only insert a cast in each block once. 2968 std::map<BasicBlock*, CastInst*> InsertedCasts; 2969 2970 bool MadeChange = false; 2971 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); 2972 UI != E; ) { 2973 Use &TheUse = UI.getUse(); 2974 Instruction *User = cast<Instruction>(*UI); 2975 2976 // Figure out which BB this cast is used in. For PHI's this is the 2977 // appropriate predecessor block. 2978 BasicBlock *UserBB = User->getParent(); 2979 if (PHINode *PN = dyn_cast<PHINode>(User)) { 2980 unsigned OpVal = UI.getOperandNo()/2; 2981 UserBB = PN->getIncomingBlock(OpVal); 2982 } 2983 2984 // Preincrement use iterator so we don't invalidate it. 2985 ++UI; 2986 2987 // If this user is in the same block as the cast, don't change the cast. 2988 if (UserBB == DefBB) continue; 2989 2990 // If we have already inserted a cast into this block, use it. 2991 CastInst *&InsertedCast = InsertedCasts[UserBB]; 2992 2993 if (!InsertedCast) { 2994 BasicBlock::iterator InsertPt = UserBB->begin(); 2995 while (isa<PHINode>(InsertPt)) ++InsertPt; 2996 2997 InsertedCast = 2998 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); 2999 MadeChange = true; 3000 } 3001 3002 // Replace a use of the cast with a use of the new casat. 3003 TheUse = InsertedCast; 3004 } 3005 3006 // If we removed all uses, nuke the cast. 3007 if (CI->use_empty()) 3008 CI->eraseFromParent(); 3009 3010 return MadeChange; 3011} 3012 3013/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, 3014/// casting to the type of GEPI. 3015static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB, 3016 Instruction *GEPI, Value *Ptr, 3017 Value *PtrOffset) { 3018 if (V) return V; // Already computed. 3019 3020 BasicBlock::iterator InsertPt; 3021 if (BB == GEPI->getParent()) { 3022 // If insert into the GEP's block, insert right after the GEP. 3023 InsertPt = GEPI; 3024 ++InsertPt; 3025 } else { 3026 // Otherwise, insert at the top of BB, after any PHI nodes 3027 InsertPt = BB->begin(); 3028 while (isa<PHINode>(InsertPt)) ++InsertPt; 3029 } 3030 3031 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into 3032 // BB so that there is only one value live across basic blocks (the cast 3033 // operand). 3034 if (CastInst *CI = dyn_cast<CastInst>(Ptr)) 3035 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType())) 3036 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); 3037 3038 // Add the offset, cast it to the right type. 3039 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); 3040 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt); 3041} 3042 3043/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to 3044/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One 3045/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's 3046/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to 3047/// sink PtrOffset into user blocks where doing so will likely allow us to fold 3048/// the constant add into a load or store instruction. Additionally, if a user 3049/// is a pointer-pointer cast, we look through it to find its users. 3050static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr, 3051 Constant *PtrOffset, BasicBlock *DefBB, 3052 GetElementPtrInst *GEPI, 3053 std::map<BasicBlock*,Instruction*> &InsertedExprs) { 3054 while (!RepPtr->use_empty()) { 3055 Instruction *User = cast<Instruction>(RepPtr->use_back()); 3056 3057 // If the user is a Pointer-Pointer cast, recurse. 3058 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) { 3059 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3060 3061 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we 3062 // could invalidate an iterator. 3063 User->setOperand(0, UndefValue::get(RepPtr->getType())); 3064 continue; 3065 } 3066 3067 // If this is a load of the pointer, or a store through the pointer, emit 3068 // the increment into the load/store block. 3069 Instruction *NewVal; 3070 if (isa<LoadInst>(User) || 3071 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) { 3072 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], 3073 User->getParent(), GEPI, 3074 Ptr, PtrOffset); 3075 } else { 3076 // If this use is not foldable into the addressing mode, use a version 3077 // emitted in the GEP block. 3078 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI, 3079 Ptr, PtrOffset); 3080 } 3081 3082 if (GEPI->getType() != RepPtr->getType()) { 3083 BasicBlock::iterator IP = NewVal; 3084 ++IP; 3085 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP); 3086 } 3087 User->replaceUsesOfWith(RepPtr, NewVal); 3088 } 3089} 3090 3091 3092/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction 3093/// selection, we want to be a bit careful about some things. In particular, if 3094/// we have a GEP instruction that is used in a different block than it is 3095/// defined, the addressing expression of the GEP cannot be folded into loads or 3096/// stores that use it. In this case, decompose the GEP and move constant 3097/// indices into blocks that use it. 3098static bool OptimizeGEPExpression(GetElementPtrInst *GEPI, 3099 const TargetData *TD) { 3100 // If this GEP is only used inside the block it is defined in, there is no 3101 // need to rewrite it. 3102 bool isUsedOutsideDefBB = false; 3103 BasicBlock *DefBB = GEPI->getParent(); 3104 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end(); 3105 UI != E; ++UI) { 3106 if (cast<Instruction>(*UI)->getParent() != DefBB) { 3107 isUsedOutsideDefBB = true; 3108 break; 3109 } 3110 } 3111 if (!isUsedOutsideDefBB) return false; 3112 3113 // If this GEP has no non-zero constant indices, there is nothing we can do, 3114 // ignore it. 3115 bool hasConstantIndex = false; 3116 bool hasVariableIndex = false; 3117 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3118 E = GEPI->op_end(); OI != E; ++OI) { 3119 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) { 3120 if (CI->getRawValue()) { 3121 hasConstantIndex = true; 3122 break; 3123 } 3124 } else { 3125 hasVariableIndex = true; 3126 } 3127 } 3128 3129 // If this is a "GEP X, 0, 0, 0", turn this into a cast. 3130 if (!hasConstantIndex && !hasVariableIndex) { 3131 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(), 3132 GEPI->getName(), GEPI); 3133 GEPI->replaceAllUsesWith(NC); 3134 GEPI->eraseFromParent(); 3135 return true; 3136 } 3137 3138 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses. 3139 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) 3140 return false; 3141 3142 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the 3143 // constant offset (which we now know is non-zero) and deal with it later. 3144 uint64_t ConstantOffset = 0; 3145 const Type *UIntPtrTy = TD->getIntPtrType(); 3146 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI); 3147 const Type *Ty = GEPI->getOperand(0)->getType(); 3148 3149 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3150 E = GEPI->op_end(); OI != E; ++OI) { 3151 Value *Idx = *OI; 3152 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 3153 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 3154 if (Field) 3155 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field]; 3156 Ty = StTy->getElementType(Field); 3157 } else { 3158 Ty = cast<SequentialType>(Ty)->getElementType(); 3159 3160 // Handle constant subscripts. 3161 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3162 if (CI->getRawValue() == 0) continue; 3163 3164 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI)) 3165 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); 3166 else 3167 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue(); 3168 continue; 3169 } 3170 3171 // Ptr = Ptr + Idx * ElementSize; 3172 3173 // Cast Idx to UIntPtrTy if needed. 3174 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI); 3175 3176 uint64_t ElementSize = TD->getTypeSize(Ty); 3177 // Mask off bits that should not be set. 3178 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3179 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize); 3180 3181 // Multiply by the element size and add to the base. 3182 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI); 3183 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI); 3184 } 3185 } 3186 3187 // Make sure that the offset fits in uintptr_t. 3188 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3189 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset); 3190 3191 // Okay, we have now emitted all of the variable index parts to the BB that 3192 // the GEP is defined in. Loop over all of the using instructions, inserting 3193 // an "add Ptr, ConstantOffset" into each block that uses it and update the 3194 // instruction to use the newly computed value, making GEPI dead. When the 3195 // user is a load or store instruction address, we emit the add into the user 3196 // block, otherwise we use a canonical version right next to the gep (these 3197 // won't be foldable as addresses, so we might as well share the computation). 3198 3199 std::map<BasicBlock*,Instruction*> InsertedExprs; 3200 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3201 3202 // Finally, the GEP is dead, remove it. 3203 GEPI->eraseFromParent(); 3204 3205 return true; 3206} 3207 3208/// SplitCritEdgesForPHIConstants - If this block has any PHI nodes with 3209/// constant operands, and if any of the edges feeding the PHI node are 3210/// critical, split them so that the assignments of a constant to a register 3211/// will not be executed on a path that isn't relevant. 3212void SelectionDAGISel::SplitCritEdgesForPHIConstants(BasicBlock *BB) { 3213 // The most common case is that this is a PHI node with two incoming 3214 // successors handle this case efficiently, because it is simple. 3215 PHINode *PN = cast<PHINode>(BB->begin()); 3216 if (PN->getNumIncomingValues() == 2) { 3217 // If neither edge is critical, we never need to split. 3218 if (PN->getIncomingBlock(0)->getTerminator()->getNumSuccessors() == 1 && 3219 PN->getIncomingBlock(1)->getTerminator()->getNumSuccessors() == 1) 3220 return; 3221 3222 BasicBlock::iterator BBI = BB->begin(); 3223 while ((PN = dyn_cast<PHINode>(BBI++))) { 3224 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) 3225 if (isa<Constant>(PN->getIncomingValue(i))) 3226 SplitCriticalEdge(PN->getIncomingBlock(i), BB); 3227 } 3228 return; 3229 } 3230 3231 // Otherwise, things are a bit trickier. 3232 3233 // BE SMART HERE. 3234 3235 BasicBlock::iterator BBI = BB->begin(); 3236 while ((PN = dyn_cast<PHINode>(BBI++))) { 3237 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) 3238 if (isa<Constant>(PN->getIncomingValue(i))) 3239 SplitCriticalEdge(PN->getIncomingBlock(i), BB); 3240 } 3241} 3242 3243 3244bool SelectionDAGISel::runOnFunction(Function &Fn) { 3245 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 3246 RegMap = MF.getSSARegMap(); 3247 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n"); 3248 3249 // First, split all critical edges for PHI nodes with incoming values that are 3250 // constants, this way the load of the constant into a vreg will not be placed 3251 // into MBBs that are used some other way. 3252 // 3253 // In this pass we also look for GEP and cast instructions that are used 3254 // across basic blocks and rewrite them to improve basic-block-at-a-time 3255 // selection. 3256 // 3257 // 3258 bool MadeChange = true; 3259 while (MadeChange) { 3260 MadeChange = false; 3261 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 3262 // If this block has any PHI nodes with constant operands, and if any of the 3263 // edges feeding the PHI node are critical, split them. 3264 if (isa<PHINode>(BB->begin())) 3265 SplitCritEdgesForPHIConstants(BB); 3266 3267 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) { 3268 Instruction *I = BBI++; 3269 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) { 3270 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData()); 3271 } else if (CastInst *CI = dyn_cast<CastInst>(I)) { 3272 // If the source of the cast is a constant, then this should have 3273 // already been constant folded. The only reason NOT to constant fold 3274 // it is if something (e.g. LSR) was careful to place the constant 3275 // evaluation in a block other than then one that uses it (e.g. to hoist 3276 // the address of globals out of a loop). If this is the case, we don't 3277 // want to forward-subst the cast. 3278 if (isa<Constant>(CI->getOperand(0))) 3279 continue; 3280 3281 // If this is a noop copy, sink it into user blocks to reduce the number 3282 // of virtual registers that must be created and coallesced. 3283 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); 3284 MVT::ValueType DstVT = TLI.getValueType(CI->getType()); 3285 3286 // This is an fp<->int conversion? 3287 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT)) 3288 continue; 3289 3290 // If this is an extension, it will be a zero or sign extension, which 3291 // isn't a noop. 3292 if (SrcVT < DstVT) continue; 3293 3294 // If these values will be promoted, find out what they will be promoted 3295 // to. This helps us consider truncates on PPC as noop copies when they 3296 // are. 3297 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) 3298 SrcVT = TLI.getTypeToTransformTo(SrcVT); 3299 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) 3300 DstVT = TLI.getTypeToTransformTo(DstVT); 3301 3302 // If, after promotion, these are the same types, this is a noop copy. 3303 if (SrcVT == DstVT) 3304 MadeChange |= OptimizeNoopCopyExpression(CI); 3305 } 3306 } 3307 } 3308 } 3309 3310 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 3311 3312 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 3313 SelectBasicBlock(I, MF, FuncInfo); 3314 3315 return true; 3316} 3317 3318 3319SDOperand SelectionDAGISel:: 3320CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) { 3321 SDOperand Op = SDL.getValue(V); 3322 assert((Op.getOpcode() != ISD::CopyFromReg || 3323 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 3324 "Copy from a reg to the same reg!"); 3325 3326 // If this type is not legal, we must make sure to not create an invalid 3327 // register use. 3328 MVT::ValueType SrcVT = Op.getValueType(); 3329 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 3330 SelectionDAG &DAG = SDL.DAG; 3331 if (SrcVT == DestVT) { 3332 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 3333 } else if (SrcVT == MVT::Vector) { 3334 // Handle copies from generic vectors to registers. 3335 MVT::ValueType PTyElementVT, PTyLegalElementVT; 3336 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()), 3337 PTyElementVT, PTyLegalElementVT); 3338 3339 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 3340 // MVT::Vector type. 3341 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 3342 DAG.getConstant(NE, MVT::i32), 3343 DAG.getValueType(PTyElementVT)); 3344 3345 // Loop over all of the elements of the resultant vector, 3346 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 3347 // copying them into output registers. 3348 SmallVector<SDOperand, 8> OutChains; 3349 SDOperand Root = SDL.getRoot(); 3350 for (unsigned i = 0; i != NE; ++i) { 3351 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 3352 Op, DAG.getConstant(i, TLI.getPointerTy())); 3353 if (PTyElementVT == PTyLegalElementVT) { 3354 // Elements are legal. 3355 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3356 } else if (PTyLegalElementVT > PTyElementVT) { 3357 // Elements are promoted. 3358 if (MVT::isFloatingPoint(PTyLegalElementVT)) 3359 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 3360 else 3361 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 3362 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3363 } else { 3364 // Elements are expanded. 3365 // The src value is expanded into multiple registers. 3366 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3367 Elt, DAG.getConstant(0, TLI.getPointerTy())); 3368 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3369 Elt, DAG.getConstant(1, TLI.getPointerTy())); 3370 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 3371 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 3372 } 3373 } 3374 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3375 &OutChains[0], OutChains.size()); 3376 } else if (SrcVT < DestVT) { 3377 // The src value is promoted to the register. 3378 if (MVT::isFloatingPoint(SrcVT)) 3379 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 3380 else 3381 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 3382 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 3383 } else { 3384 // The src value is expanded into multiple registers. 3385 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3386 Op, DAG.getConstant(0, TLI.getPointerTy())); 3387 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3388 Op, DAG.getConstant(1, TLI.getPointerTy())); 3389 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo); 3390 return DAG.getCopyToReg(Op, Reg+1, Hi); 3391 } 3392} 3393 3394void SelectionDAGISel:: 3395LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 3396 std::vector<SDOperand> &UnorderedChains) { 3397 // If this is the entry block, emit arguments. 3398 Function &F = *BB->getParent(); 3399 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 3400 SDOperand OldRoot = SDL.DAG.getRoot(); 3401 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 3402 3403 unsigned a = 0; 3404 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 3405 AI != E; ++AI, ++a) 3406 if (!AI->use_empty()) { 3407 SDL.setValue(AI, Args[a]); 3408 3409 // If this argument is live outside of the entry block, insert a copy from 3410 // whereever we got it to the vreg that other BB's will reference it as. 3411 if (FuncInfo.ValueMap.count(AI)) { 3412 SDOperand Copy = 3413 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 3414 UnorderedChains.push_back(Copy); 3415 } 3416 } 3417 3418 // Finally, if the target has anything special to do, allow it to do so. 3419 // FIXME: this should insert code into the DAG! 3420 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 3421} 3422 3423void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 3424 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 3425 FunctionLoweringInfo &FuncInfo) { 3426 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 3427 3428 std::vector<SDOperand> UnorderedChains; 3429 3430 // Lower any arguments needed in this block if this is the entry block. 3431 if (LLVMBB == &LLVMBB->getParent()->front()) 3432 LowerArguments(LLVMBB, SDL, UnorderedChains); 3433 3434 BB = FuncInfo.MBBMap[LLVMBB]; 3435 SDL.setCurrentBasicBlock(BB); 3436 3437 // Lower all of the non-terminator instructions. 3438 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 3439 I != E; ++I) 3440 SDL.visit(*I); 3441 3442 // Ensure that all instructions which are used outside of their defining 3443 // blocks are available as virtual registers. 3444 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 3445 if (!I->use_empty() && !isa<PHINode>(I)) { 3446 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 3447 if (VMI != FuncInfo.ValueMap.end()) 3448 UnorderedChains.push_back( 3449 CopyValueToVirtualRegister(SDL, I, VMI->second)); 3450 } 3451 3452 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 3453 // ensure constants are generated when needed. Remember the virtual registers 3454 // that need to be added to the Machine PHI nodes as input. We cannot just 3455 // directly add them, because expansion might result in multiple MBB's for one 3456 // BB. As such, the start of the BB might correspond to a different MBB than 3457 // the end. 3458 // 3459 3460 // Emit constants only once even if used by multiple PHI nodes. 3461 std::map<Constant*, unsigned> ConstantsOut; 3462 3463 // Check successor nodes PHI nodes that expect a constant to be available from 3464 // this block. 3465 TerminatorInst *TI = LLVMBB->getTerminator(); 3466 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 3467 BasicBlock *SuccBB = TI->getSuccessor(succ); 3468 if (!isa<PHINode>(SuccBB->begin())) continue; 3469 3470 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin(); 3471 PHINode *PN; 3472 3473 // At this point we know that there is a 1-1 correspondence between LLVM PHI 3474 // nodes and Machine PHI nodes, but the incoming operands have not been 3475 // emitted yet. 3476 for (BasicBlock::iterator I = SuccBB->begin(); 3477 (PN = dyn_cast<PHINode>(I)); ++I) 3478 if (!PN->use_empty()) { 3479 unsigned Reg; 3480 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 3481 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 3482 unsigned &RegOut = ConstantsOut[C]; 3483 if (RegOut == 0) { 3484 RegOut = FuncInfo.CreateRegForValue(C); 3485 UnorderedChains.push_back( 3486 CopyValueToVirtualRegister(SDL, C, RegOut)); 3487 } 3488 Reg = RegOut; 3489 } else { 3490 Reg = FuncInfo.ValueMap[PHIOp]; 3491 if (Reg == 0) { 3492 assert(isa<AllocaInst>(PHIOp) && 3493 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 3494 "Didn't codegen value into a register!??"); 3495 Reg = FuncInfo.CreateRegForValue(PHIOp); 3496 UnorderedChains.push_back( 3497 CopyValueToVirtualRegister(SDL, PHIOp, Reg)); 3498 } 3499 } 3500 3501 // Remember that this register needs to added to the machine PHI node as 3502 // the input for this MBB. 3503 MVT::ValueType VT = TLI.getValueType(PN->getType()); 3504 unsigned NumElements; 3505 if (VT != MVT::Vector) 3506 NumElements = TLI.getNumElements(VT); 3507 else { 3508 MVT::ValueType VT1,VT2; 3509 NumElements = 3510 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 3511 VT1, VT2); 3512 } 3513 for (unsigned i = 0, e = NumElements; i != e; ++i) 3514 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 3515 } 3516 } 3517 ConstantsOut.clear(); 3518 3519 // Turn all of the unordered chains into one factored node. 3520 if (!UnorderedChains.empty()) { 3521 SDOperand Root = SDL.getRoot(); 3522 if (Root.getOpcode() != ISD::EntryToken) { 3523 unsigned i = 0, e = UnorderedChains.size(); 3524 for (; i != e; ++i) { 3525 assert(UnorderedChains[i].Val->getNumOperands() > 1); 3526 if (UnorderedChains[i].Val->getOperand(0) == Root) 3527 break; // Don't add the root if we already indirectly depend on it. 3528 } 3529 3530 if (i == e) 3531 UnorderedChains.push_back(Root); 3532 } 3533 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 3534 &UnorderedChains[0], UnorderedChains.size())); 3535 } 3536 3537 // Lower the terminator after the copies are emitted. 3538 SDL.visit(*LLVMBB->getTerminator()); 3539 3540 // Copy over any CaseBlock records that may now exist due to SwitchInst 3541 // lowering, as well as any jump table information. 3542 SwitchCases.clear(); 3543 SwitchCases = SDL.SwitchCases; 3544 JT = SDL.JT; 3545 3546 // Make sure the root of the DAG is up-to-date. 3547 DAG.setRoot(SDL.getRoot()); 3548} 3549 3550void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 3551 // Get alias analysis for load/store combining. 3552 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 3553 3554 // Run the DAG combiner in pre-legalize mode. 3555 DAG.Combine(false, AA); 3556 3557 DEBUG(std::cerr << "Lowered selection DAG:\n"); 3558 DEBUG(DAG.dump()); 3559 3560 // Second step, hack on the DAG until it only uses operations and types that 3561 // the target supports. 3562 DAG.Legalize(); 3563 3564 DEBUG(std::cerr << "Legalized selection DAG:\n"); 3565 DEBUG(DAG.dump()); 3566 3567 // Run the DAG combiner in post-legalize mode. 3568 DAG.Combine(true, AA); 3569 3570 if (ViewISelDAGs) DAG.viewGraph(); 3571 3572 // Third, instruction select all of the operations to machine code, adding the 3573 // code to the MachineBasicBlock. 3574 InstructionSelectBasicBlock(DAG); 3575 3576 DEBUG(std::cerr << "Selected machine code:\n"); 3577 DEBUG(BB->dump()); 3578} 3579 3580void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 3581 FunctionLoweringInfo &FuncInfo) { 3582 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 3583 { 3584 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3585 CurDAG = &DAG; 3586 3587 // First step, lower LLVM code to some DAG. This DAG may use operations and 3588 // types that are not supported by the target. 3589 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 3590 3591 // Second step, emit the lowered DAG as machine code. 3592 CodeGenAndEmitDAG(DAG); 3593 } 3594 3595 // Next, now that we know what the last MBB the LLVM BB expanded is, update 3596 // PHI nodes in successors. 3597 if (SwitchCases.empty() && JT.Reg == 0) { 3598 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 3599 MachineInstr *PHI = PHINodesToUpdate[i].first; 3600 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3601 "This is not a machine PHI node that we are updating!"); 3602 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 3603 PHI->addMachineBasicBlockOperand(BB); 3604 } 3605 return; 3606 } 3607 3608 // If the JumpTable record is filled in, then we need to emit a jump table. 3609 // Updating the PHI nodes is tricky in this case, since we need to determine 3610 // whether the PHI is a successor of the range check MBB or the jump table MBB 3611 if (JT.Reg) { 3612 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch"); 3613 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3614 CurDAG = &SDAG; 3615 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 3616 MachineBasicBlock *RangeBB = BB; 3617 // Set the current basic block to the mbb we wish to insert the code into 3618 BB = JT.MBB; 3619 SDL.setCurrentBasicBlock(BB); 3620 // Emit the code 3621 SDL.visitJumpTable(JT); 3622 SDAG.setRoot(SDL.getRoot()); 3623 CodeGenAndEmitDAG(SDAG); 3624 // Update PHI Nodes 3625 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 3626 MachineInstr *PHI = PHINodesToUpdate[pi].first; 3627 MachineBasicBlock *PHIBB = PHI->getParent(); 3628 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 3629 "This is not a machine PHI node that we are updating!"); 3630 if (PHIBB == JT.Default) { 3631 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 3632 PHI->addMachineBasicBlockOperand(RangeBB); 3633 } 3634 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 3635 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 3636 PHI->addMachineBasicBlockOperand(BB); 3637 } 3638 } 3639 return; 3640 } 3641 3642 // If we generated any switch lowering information, build and codegen any 3643 // additional DAGs necessary. 3644 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 3645 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 3646 CurDAG = &SDAG; 3647 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 3648 3649 // Set the current basic block to the mbb we wish to insert the code into 3650 BB = SwitchCases[i].ThisBB; 3651 SDL.setCurrentBasicBlock(BB); 3652 3653 // Emit the code 3654 SDL.visitSwitchCase(SwitchCases[i]); 3655 SDAG.setRoot(SDL.getRoot()); 3656 CodeGenAndEmitDAG(SDAG); 3657 3658 // Handle any PHI nodes in successors of this chunk, as if we were coming 3659 // from the original BB before switch expansion. Note that PHI nodes can 3660 // occur multiple times in PHINodesToUpdate. We have to be very careful to 3661 // handle them the right number of times. 3662 while ((BB = SwitchCases[i].LHSBB)) { // Handle LHS and RHS. 3663 for (MachineBasicBlock::iterator Phi = BB->begin(); 3664 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 3665 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 3666 for (unsigned pn = 0; ; ++pn) { 3667 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 3668 if (PHINodesToUpdate[pn].first == Phi) { 3669 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 3670 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 3671 break; 3672 } 3673 } 3674 } 3675 3676 // Don't process RHS if same block as LHS. 3677 if (BB == SwitchCases[i].RHSBB) 3678 SwitchCases[i].RHSBB = 0; 3679 3680 // If we haven't handled the RHS, do so now. Otherwise, we're done. 3681 SwitchCases[i].LHSBB = SwitchCases[i].RHSBB; 3682 SwitchCases[i].RHSBB = 0; 3683 } 3684 assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0); 3685 } 3686} 3687 3688 3689//===----------------------------------------------------------------------===// 3690/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 3691/// target node in the graph. 3692void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 3693 if (ViewSchedDAGs) DAG.viewGraph(); 3694 3695 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 3696 3697 if (!Ctor) { 3698 Ctor = ISHeuristic; 3699 RegisterScheduler::setDefault(Ctor); 3700 } 3701 3702 ScheduleDAG *SL = Ctor(this, &DAG, BB); 3703 BB = SL->Run(); 3704 delete SL; 3705} 3706 3707 3708HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 3709 return new HazardRecognizer(); 3710} 3711 3712//===----------------------------------------------------------------------===// 3713// Helper functions used by the generated instruction selector. 3714//===----------------------------------------------------------------------===// 3715// Calls to these methods are generated by tblgen. 3716 3717/// CheckAndMask - The isel is trying to match something like (and X, 255). If 3718/// the dag combiner simplified the 255, we still want to match. RHS is the 3719/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 3720/// specified in the .td file (e.g. 255). 3721bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 3722 int64_t DesiredMaskS) { 3723 uint64_t ActualMask = RHS->getValue(); 3724 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 3725 3726 // If the actual mask exactly matches, success! 3727 if (ActualMask == DesiredMask) 3728 return true; 3729 3730 // If the actual AND mask is allowing unallowed bits, this doesn't match. 3731 if (ActualMask & ~DesiredMask) 3732 return false; 3733 3734 // Otherwise, the DAG Combiner may have proven that the value coming in is 3735 // either already zero or is not demanded. Check for known zero input bits. 3736 uint64_t NeededMask = DesiredMask & ~ActualMask; 3737 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask)) 3738 return true; 3739 3740 // TODO: check to see if missing bits are just not demanded. 3741 3742 // Otherwise, this pattern doesn't match. 3743 return false; 3744} 3745 3746/// CheckOrMask - The isel is trying to match something like (or X, 255). If 3747/// the dag combiner simplified the 255, we still want to match. RHS is the 3748/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 3749/// specified in the .td file (e.g. 255). 3750bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 3751 int64_t DesiredMaskS) { 3752 uint64_t ActualMask = RHS->getValue(); 3753 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 3754 3755 // If the actual mask exactly matches, success! 3756 if (ActualMask == DesiredMask) 3757 return true; 3758 3759 // If the actual AND mask is allowing unallowed bits, this doesn't match. 3760 if (ActualMask & ~DesiredMask) 3761 return false; 3762 3763 // Otherwise, the DAG Combiner may have proven that the value coming in is 3764 // either already zero or is not demanded. Check for known zero input bits. 3765 uint64_t NeededMask = DesiredMask & ~ActualMask; 3766 3767 uint64_t KnownZero, KnownOne; 3768 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 3769 3770 // If all the missing bits in the or are already known to be set, match! 3771 if ((NeededMask & KnownOne) == NeededMask) 3772 return true; 3773 3774 // TODO: check to see if missing bits are just not demanded. 3775 3776 // Otherwise, this pattern doesn't match. 3777 return false; 3778} 3779 3780 3781/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 3782/// by tblgen. Others should not call it. 3783void SelectionDAGISel:: 3784SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 3785 std::vector<SDOperand> InOps; 3786 std::swap(InOps, Ops); 3787 3788 Ops.push_back(InOps[0]); // input chain. 3789 Ops.push_back(InOps[1]); // input asm string. 3790 3791 unsigned i = 2, e = InOps.size(); 3792 if (InOps[e-1].getValueType() == MVT::Flag) 3793 --e; // Don't process a flag operand if it is here. 3794 3795 while (i != e) { 3796 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 3797 if ((Flags & 7) != 4 /*MEM*/) { 3798 // Just skip over this operand, copying the operands verbatim. 3799 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 3800 i += (Flags >> 3) + 1; 3801 } else { 3802 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 3803 // Otherwise, this is a memory operand. Ask the target to select it. 3804 std::vector<SDOperand> SelOps; 3805 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 3806 std::cerr << "Could not match memory address. Inline asm failure!\n"; 3807 exit(1); 3808 } 3809 3810 // Add this to the output node. 3811 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32)); 3812 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 3813 i += 2; 3814 } 3815 } 3816 3817 // Add the flag input back if present. 3818 if (e != InOps.size()) 3819 Ops.push_back(InOps.back()); 3820} 3821