SelectionDAGISel.cpp revision caa8870fe09f5526e611434b6bb9f7040c7dfa60
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include "llvm/ADT/Statistic.h" 60#include <algorithm> 61using namespace llvm; 62 63STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 64 65static cl::opt<bool> 66EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 67 cl::desc("Enable verbose messages in the \"fast\" " 68 "instruction selector")); 69static cl::opt<bool> 70EnableFastISelAbort("fast-isel-abort", cl::Hidden, 71 cl::desc("Enable abort calls when \"fast\" instruction fails")); 72static cl::opt<bool> 73SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 74 cl::desc("Schedule copies of livein registers"), 75 cl::init(false)); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createFastDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 assert(TLI.getSchedulingPreference() == 150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 151 return createBURRListDAGScheduler(IS, OptLevel); 152 } 153} 154 155// EmitInstrWithCustomInserter - This method should be implemented by targets 156// that mark instructions with the 'usesCustomInserter' flag. These 157// instructions are special in various ways, which require special support to 158// insert. The specified MachineInstr is created but not inserted into any 159// basic blocks, and this method is called to expand it into a sequence of 160// instructions, potentially also creating new basic blocks and control flow. 161// When new basic blocks are inserted and the edges from MBB to its successors 162// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 163// DenseMap. 164MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 165 MachineBasicBlock *MBB, 166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 167#ifndef NDEBUG 168 dbgs() << "If a target marks an instruction with " 169 "'usesCustomInserter', it must implement " 170 "TargetLowering::EmitInstrWithCustomInserter!"; 171#endif 172 llvm_unreachable(0); 173 return 0; 174} 175 176/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 177/// physical register has only a single copy use, then coalesced the copy 178/// if possible. 179static void EmitLiveInCopy(MachineBasicBlock *MBB, 180 MachineBasicBlock::iterator &InsertPos, 181 unsigned VirtReg, unsigned PhysReg, 182 const TargetRegisterClass *RC, 183 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 184 const MachineRegisterInfo &MRI, 185 const TargetRegisterInfo &TRI, 186 const TargetInstrInfo &TII) { 187 unsigned NumUses = 0; 188 MachineInstr *UseMI = NULL; 189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 190 UE = MRI.use_end(); UI != UE; ++UI) { 191 UseMI = &*UI; 192 if (++NumUses > 1) 193 break; 194 } 195 196 // If the number of uses is not one, or the use is not a move instruction, 197 // don't coalesce. Also, only coalesce away a virtual register to virtual 198 // register copy. 199 bool Coalesced = false; 200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 201 if (NumUses == 1 && 202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 203 TargetRegisterInfo::isVirtualRegister(DstReg)) { 204 VirtReg = DstReg; 205 Coalesced = true; 206 } 207 208 // Now find an ideal location to insert the copy. 209 MachineBasicBlock::iterator Pos = InsertPos; 210 while (Pos != MBB->begin()) { 211 MachineInstr *PrevMI = prior(Pos); 212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 213 // copyRegToReg might emit multiple instructions to do a copy. 214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 216 // This is what the BB looks like right now: 217 // r1024 = mov r0 218 // ... 219 // r1 = mov r1024 220 // 221 // We want to insert "r1025 = mov r1". Inserting this copy below the 222 // move to r1024 makes it impossible for that move to be coalesced. 223 // 224 // r1025 = mov r1 225 // r1024 = mov r0 226 // ... 227 // r1 = mov 1024 228 // r2 = mov 1025 229 break; // Woot! Found a good location. 230 --Pos; 231 } 232 233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 234 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 235 (void) Emitted; 236 237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 238 if (Coalesced) { 239 if (&*InsertPos == UseMI) ++InsertPos; 240 MBB->erase(UseMI); 241 } 242} 243 244/// EmitLiveInCopies - If this is the first basic block in the function, 245/// and if it has live ins that need to be copied into vregs, emit the 246/// copies into the block. 247static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 248 const MachineRegisterInfo &MRI, 249 const TargetRegisterInfo &TRI, 250 const TargetInstrInfo &TII) { 251 if (SchedLiveInCopies) { 252 // Emit the copies at a heuristically-determined location in the block. 253 DenseMap<MachineInstr*, unsigned> CopyRegMap; 254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 256 E = MRI.livein_end(); LI != E; ++LI) 257 if (LI->second) { 258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 260 RC, CopyRegMap, MRI, TRI, TII); 261 } 262 } else { 263 // Emit the copies into the top of the block. 264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 265 E = MRI.livein_end(); LI != E; ++LI) 266 if (LI->second) { 267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 269 LI->second, LI->first, RC, RC); 270 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 271 (void) Emitted; 272 } 273 } 274} 275 276//===----------------------------------------------------------------------===// 277// SelectionDAGISel code 278//===----------------------------------------------------------------------===// 279 280SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 282 FuncInfo(new FunctionLoweringInfo(TLI)), 283 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) 288{} 289 290SelectionDAGISel::~SelectionDAGISel() { 291 delete SDB; 292 delete CurDAG; 293 delete FuncInfo; 294} 295 296unsigned SelectionDAGISel::MakeReg(EVT VT) { 297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<DwarfWriter>(); 306 AU.addPreserved<DwarfWriter>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 311 Function &Fn = *mf.getFunction(); 312 313 // Do some sanity-checking on the command-line options. 314 assert((!EnableFastISelVerbose || EnableFastISel) && 315 "-fast-isel-verbose requires -fast-isel"); 316 assert((!EnableFastISelAbort || EnableFastISel) && 317 "-fast-isel-abort requires -fast-isel"); 318 319 // Get alias analysis for load/store combining. 320 AA = &getAnalysis<AliasAnalysis>(); 321 322 MF = &mf; 323 const TargetInstrInfo &TII = *TM.getInstrInfo(); 324 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 325 326 if (Fn.hasGC()) 327 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 328 else 329 GFI = 0; 330 RegInfo = &MF->getRegInfo(); 331 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 332 333 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 334 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 335 CurDAG->init(*MF, MMI, DW); 336 FuncInfo->set(Fn, *MF, EnableFastISel); 337 SDB->init(GFI, *AA); 338 339 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 340 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 341 // Mark landing pad. 342 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 343 344 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 345 346 // If the first basic block in the function has live ins that need to be 347 // copied into vregs, emit the copies into the top of the block before 348 // emitting the code for the block. 349 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 350 351 // Add function live-ins to entry block live-in set. 352 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 353 E = RegInfo->livein_end(); I != E; ++I) 354 MF->begin()->addLiveIn(I->first); 355 356#ifndef NDEBUG 357 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 358 "Not all catch info was assigned to a landing pad!"); 359#endif 360 361 FuncInfo->clear(); 362 363 return true; 364} 365 366/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 367/// attached with this instruction. 368static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 369 SelectionDAGBuilder *SDB, 370 FastISel *FastIS, MachineFunction *MF) { 371 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 372 DILocation DILoc(Dbg); 373 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 374 375 SDB->setCurDebugLoc(Loc); 376 377 if (FastIS) 378 FastIS->setCurDebugLoc(Loc); 379 380 // If the function doesn't have a default debug location yet, set 381 // it. This is kind of a hack. 382 if (MF->getDefaultDebugLoc().isUnknown()) 383 MF->setDefaultDebugLoc(Loc); 384 } 385} 386 387/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 388static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 389 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 390 if (FastIS) 391 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 392} 393 394void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 395 BasicBlock::iterator Begin, 396 BasicBlock::iterator End, 397 bool &HadTailCall) { 398 SDB->setCurrentBasicBlock(BB); 399 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 400 401 // Lower all of the non-terminator instructions. If a call is emitted 402 // as a tail call, cease emitting nodes for this block. 403 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 404 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 405 406 if (!isa<TerminatorInst>(I)) { 407 SDB->visit(*I); 408 409 // Set the current debug location back to "unknown" so that it doesn't 410 // spuriously apply to subsequent instructions. 411 ResetDebugLoc(SDB, 0); 412 } 413 } 414 415 if (!SDB->HasTailCall) { 416 // Ensure that all instructions which are used outside of their defining 417 // blocks are available as virtual registers. Invoke is handled elsewhere. 418 for (BasicBlock::iterator I = Begin; I != End; ++I) 419 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 420 SDB->CopyToExportRegsIfNeeded(I); 421 422 // Handle PHI nodes in successor blocks. 423 if (End == LLVMBB->end()) { 424 HandlePHINodesInSuccessorBlocks(LLVMBB); 425 426 // Lower the terminator after the copies are emitted. 427 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 428 SDB->visit(*LLVMBB->getTerminator()); 429 ResetDebugLoc(SDB, 0); 430 } 431 } 432 433 // Make sure the root of the DAG is up-to-date. 434 CurDAG->setRoot(SDB->getControlRoot()); 435 436 // Final step, emit the lowered DAG as machine code. 437 CodeGenAndEmitDAG(); 438 HadTailCall = SDB->HasTailCall; 439 SDB->clear(); 440} 441 442namespace { 443/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 444/// nodes from the worklist. 445class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 446 SmallVector<SDNode*, 128> &Worklist; 447 SmallPtrSet<SDNode*, 128> &InWorklist; 448public: 449 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 450 SmallPtrSet<SDNode*, 128> &inwl) 451 : Worklist(wl), InWorklist(inwl) {} 452 453 void RemoveFromWorklist(SDNode *N) { 454 if (!InWorklist.erase(N)) return; 455 456 SmallVector<SDNode*, 128>::iterator I = 457 std::find(Worklist.begin(), Worklist.end(), N); 458 assert(I != Worklist.end() && "Not in worklist"); 459 460 *I = Worklist.back(); 461 Worklist.pop_back(); 462 } 463 464 virtual void NodeDeleted(SDNode *N, SDNode *E) { 465 RemoveFromWorklist(N); 466 } 467 468 virtual void NodeUpdated(SDNode *N) { 469 // Ignore updates. 470 } 471}; 472} 473 474/// TrivialTruncElim - Eliminate some trivial nops that can result from 475/// ShrinkDemandedOps: (trunc (ext n)) -> n. 476static bool TrivialTruncElim(SDValue Op, 477 TargetLowering::TargetLoweringOpt &TLO) { 478 SDValue N0 = Op.getOperand(0); 479 EVT VT = Op.getValueType(); 480 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 481 N0.getOpcode() == ISD::SIGN_EXTEND || 482 N0.getOpcode() == ISD::ANY_EXTEND) && 483 N0.getOperand(0).getValueType() == VT) { 484 return TLO.CombineTo(Op, N0.getOperand(0)); 485 } 486 return false; 487} 488 489/// ShrinkDemandedOps - A late transformation pass that shrink expressions 490/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 491/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 492void SelectionDAGISel::ShrinkDemandedOps() { 493 SmallVector<SDNode*, 128> Worklist; 494 SmallPtrSet<SDNode*, 128> InWorklist; 495 496 // Add all the dag nodes to the worklist. 497 Worklist.reserve(CurDAG->allnodes_size()); 498 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 499 E = CurDAG->allnodes_end(); I != E; ++I) { 500 Worklist.push_back(I); 501 InWorklist.insert(I); 502 } 503 504 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 505 while (!Worklist.empty()) { 506 SDNode *N = Worklist.pop_back_val(); 507 InWorklist.erase(N); 508 509 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 510 // Deleting this node may make its operands dead, add them to the worklist 511 // if they aren't already there. 512 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 513 if (InWorklist.insert(N->getOperand(i).getNode())) 514 Worklist.push_back(N->getOperand(i).getNode()); 515 516 CurDAG->DeleteNode(N); 517 continue; 518 } 519 520 // Run ShrinkDemandedOp on scalar binary operations. 521 if (N->getNumValues() != 1 || 522 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 523 continue; 524 525 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 526 APInt Demanded = APInt::getAllOnesValue(BitWidth); 527 APInt KnownZero, KnownOne; 528 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 529 KnownZero, KnownOne, TLO) && 530 (N->getOpcode() != ISD::TRUNCATE || 531 !TrivialTruncElim(SDValue(N, 0), TLO))) 532 continue; 533 534 // Revisit the node. 535 assert(!InWorklist.count(N) && "Already in worklist"); 536 Worklist.push_back(N); 537 InWorklist.insert(N); 538 539 // Replace the old value with the new one. 540 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 541 TLO.Old.getNode()->dump(CurDAG); 542 errs() << "\nWith: "; 543 TLO.New.getNode()->dump(CurDAG); 544 errs() << '\n'); 545 546 if (InWorklist.insert(TLO.New.getNode())) 547 Worklist.push_back(TLO.New.getNode()); 548 549 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 550 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 551 552 if (!TLO.Old.getNode()->use_empty()) continue; 553 554 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 555 i != e; ++i) { 556 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 557 if (OpNode->hasOneUse()) { 558 // Add OpNode to the end of the list to revisit. 559 DeadNodes.RemoveFromWorklist(OpNode); 560 Worklist.push_back(OpNode); 561 InWorklist.insert(OpNode); 562 } 563 } 564 565 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 566 CurDAG->DeleteNode(TLO.Old.getNode()); 567 } 568} 569 570void SelectionDAGISel::ComputeLiveOutVRegInfo() { 571 SmallPtrSet<SDNode*, 128> VisitedNodes; 572 SmallVector<SDNode*, 128> Worklist; 573 574 Worklist.push_back(CurDAG->getRoot().getNode()); 575 576 APInt Mask; 577 APInt KnownZero; 578 APInt KnownOne; 579 580 do { 581 SDNode *N = Worklist.pop_back_val(); 582 583 // If we've already seen this node, ignore it. 584 if (!VisitedNodes.insert(N)) 585 continue; 586 587 // Otherwise, add all chain operands to the worklist. 588 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 589 if (N->getOperand(i).getValueType() == MVT::Other) 590 Worklist.push_back(N->getOperand(i).getNode()); 591 592 // If this is a CopyToReg with a vreg dest, process it. 593 if (N->getOpcode() != ISD::CopyToReg) 594 continue; 595 596 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 597 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 598 continue; 599 600 // Ignore non-scalar or non-integer values. 601 SDValue Src = N->getOperand(2); 602 EVT SrcVT = Src.getValueType(); 603 if (!SrcVT.isInteger() || SrcVT.isVector()) 604 continue; 605 606 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 607 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 608 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 609 610 // Only install this information if it tells us something. 611 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 612 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 613 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 614 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 615 FunctionLoweringInfo::LiveOutInfo &LOI = 616 FuncInfo->LiveOutRegInfo[DestReg]; 617 LOI.NumSignBits = NumSignBits; 618 LOI.KnownOne = KnownOne; 619 LOI.KnownZero = KnownZero; 620 } 621 } while (!Worklist.empty()); 622} 623 624void SelectionDAGISel::CodeGenAndEmitDAG() { 625 std::string GroupName; 626 if (TimePassesIsEnabled) 627 GroupName = "Instruction Selection and Scheduling"; 628 std::string BlockName; 629 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 630 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 631 ViewSUnitDAGs) 632 BlockName = MF->getFunction()->getNameStr() + ":" + 633 BB->getBasicBlock()->getNameStr(); 634 635 DEBUG(dbgs() << "Initial selection DAG:\n"); 636 DEBUG(CurDAG->dump()); 637 638 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 639 640 // Run the DAG combiner in pre-legalize mode. 641 if (TimePassesIsEnabled) { 642 NamedRegionTimer T("DAG Combining 1", GroupName); 643 CurDAG->Combine(Unrestricted, *AA, OptLevel); 644 } else { 645 CurDAG->Combine(Unrestricted, *AA, OptLevel); 646 } 647 648 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 649 DEBUG(CurDAG->dump()); 650 651 // Second step, hack on the DAG until it only uses operations and types that 652 // the target supports. 653 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 654 BlockName); 655 656 bool Changed; 657 if (TimePassesIsEnabled) { 658 NamedRegionTimer T("Type Legalization", GroupName); 659 Changed = CurDAG->LegalizeTypes(); 660 } else { 661 Changed = CurDAG->LegalizeTypes(); 662 } 663 664 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 665 DEBUG(CurDAG->dump()); 666 667 if (Changed) { 668 if (ViewDAGCombineLT) 669 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 670 671 // Run the DAG combiner in post-type-legalize mode. 672 if (TimePassesIsEnabled) { 673 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 674 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 675 } else { 676 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 677 } 678 679 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 680 DEBUG(CurDAG->dump()); 681 } 682 683 if (TimePassesIsEnabled) { 684 NamedRegionTimer T("Vector Legalization", GroupName); 685 Changed = CurDAG->LegalizeVectors(); 686 } else { 687 Changed = CurDAG->LegalizeVectors(); 688 } 689 690 if (Changed) { 691 if (TimePassesIsEnabled) { 692 NamedRegionTimer T("Type Legalization 2", GroupName); 693 CurDAG->LegalizeTypes(); 694 } else { 695 CurDAG->LegalizeTypes(); 696 } 697 698 if (ViewDAGCombineLT) 699 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 700 701 // Run the DAG combiner in post-type-legalize mode. 702 if (TimePassesIsEnabled) { 703 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 704 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 705 } else { 706 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 707 } 708 709 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 710 DEBUG(CurDAG->dump()); 711 } 712 713 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 714 715 if (TimePassesIsEnabled) { 716 NamedRegionTimer T("DAG Legalization", GroupName); 717 CurDAG->Legalize(OptLevel); 718 } else { 719 CurDAG->Legalize(OptLevel); 720 } 721 722 DEBUG(dbgs() << "Legalized selection DAG:\n"); 723 DEBUG(CurDAG->dump()); 724 725 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 726 727 // Run the DAG combiner in post-legalize mode. 728 if (TimePassesIsEnabled) { 729 NamedRegionTimer T("DAG Combining 2", GroupName); 730 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 731 } else { 732 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 733 } 734 735 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 736 DEBUG(CurDAG->dump()); 737 738 if (OptLevel != CodeGenOpt::None) { 739 ShrinkDemandedOps(); 740 ComputeLiveOutVRegInfo(); 741 } 742 743 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 744 745 // Third, instruction select all of the operations to machine code, adding the 746 // code to the MachineBasicBlock. 747 if (TimePassesIsEnabled) { 748 NamedRegionTimer T("Instruction Selection", GroupName); 749 DoInstructionSelection(); 750 } else { 751 DoInstructionSelection(); 752 } 753 754 DEBUG(dbgs() << "Selected selection DAG:\n"); 755 DEBUG(CurDAG->dump()); 756 757 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 758 759 // Schedule machine code. 760 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 761 if (TimePassesIsEnabled) { 762 NamedRegionTimer T("Instruction Scheduling", GroupName); 763 Scheduler->Run(CurDAG, BB, BB->end()); 764 } else { 765 Scheduler->Run(CurDAG, BB, BB->end()); 766 } 767 768 if (ViewSUnitDAGs) Scheduler->viewGraph(); 769 770 // Emit machine code to BB. This can change 'BB' to the last block being 771 // inserted into. 772 if (TimePassesIsEnabled) { 773 NamedRegionTimer T("Instruction Creation", GroupName); 774 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 775 } else { 776 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 777 } 778 779 // Free the scheduler state. 780 if (TimePassesIsEnabled) { 781 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 782 delete Scheduler; 783 } else { 784 delete Scheduler; 785 } 786 787 DEBUG(dbgs() << "Selected machine code:\n"); 788 DEBUG(BB->dump()); 789} 790 791void SelectionDAGISel::DoInstructionSelection() { 792 DEBUG(errs() << "===== Instruction selection begins:\n"); 793 794 PreprocessISelDAG(); 795 796 // Select target instructions for the DAG. 797 { 798 // Number all nodes with a topological order and set DAGSize. 799 DAGSize = CurDAG->AssignTopologicalOrder(); 800 801 // Create a dummy node (which is not added to allnodes), that adds 802 // a reference to the root node, preventing it from being deleted, 803 // and tracking any changes of the root. 804 HandleSDNode Dummy(CurDAG->getRoot()); 805 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 806 ++ISelPosition; 807 808 // The AllNodes list is now topological-sorted. Visit the 809 // nodes by starting at the end of the list (the root of the 810 // graph) and preceding back toward the beginning (the entry 811 // node). 812 while (ISelPosition != CurDAG->allnodes_begin()) { 813 SDNode *Node = --ISelPosition; 814 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 815 // but there are currently some corner cases that it misses. Also, this 816 // makes it theoretically possible to disable the DAGCombiner. 817 if (Node->use_empty()) 818 continue; 819 820 SDNode *ResNode = Select(Node); 821 822 // FIXME: This is pretty gross. 'Select' should be changed to not return 823 // anything at all and this code should be nuked with a tactical strike. 824 825 // If node should not be replaced, continue with the next one. 826 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 827 continue; 828 // Replace node. 829 if (ResNode) 830 ReplaceUses(Node, ResNode); 831 832 // If after the replacement this node is not used any more, 833 // remove this dead node. 834 if (Node->use_empty()) { // Don't delete EntryToken, etc. 835 ISelUpdater ISU(ISelPosition); 836 CurDAG->RemoveDeadNode(Node, &ISU); 837 } 838 } 839 840 CurDAG->setRoot(Dummy.getValue()); 841 } 842 DEBUG(errs() << "===== Instruction selection ends:\n"); 843 844 PostprocessISelDAG(); 845} 846 847 848void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 849 MachineFunction &MF, 850 MachineModuleInfo *MMI, 851 DwarfWriter *DW, 852 const TargetInstrInfo &TII) { 853 // Initialize the Fast-ISel state, if needed. 854 FastISel *FastIS = 0; 855 if (EnableFastISel) 856 FastIS = TLI.createFastISel(MF, MMI, DW, 857 FuncInfo->ValueMap, 858 FuncInfo->MBBMap, 859 FuncInfo->StaticAllocaMap 860#ifndef NDEBUG 861 , FuncInfo->CatchInfoLost 862#endif 863 ); 864 865 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 866 867 // Iterate over all basic blocks in the function. 868 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 869 BasicBlock *LLVMBB = &*I; 870 BB = FuncInfo->MBBMap[LLVMBB]; 871 872 BasicBlock::iterator const Begin = LLVMBB->begin(); 873 BasicBlock::iterator const End = LLVMBB->end(); 874 BasicBlock::iterator BI = Begin; 875 876 // Lower any arguments needed in this block if this is the entry block. 877 bool SuppressFastISel = false; 878 if (LLVMBB == &Fn.getEntryBlock()) { 879 LowerArguments(LLVMBB); 880 881 // If any of the arguments has the byval attribute, forgo 882 // fast-isel in the entry block. 883 if (FastIS) { 884 unsigned j = 1; 885 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 886 I != E; ++I, ++j) 887 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 888 if (EnableFastISelVerbose || EnableFastISelAbort) 889 dbgs() << "FastISel skips entry block due to byval argument\n"; 890 SuppressFastISel = true; 891 break; 892 } 893 } 894 } 895 896 if (MMI && BB->isLandingPad()) { 897 // Add a label to mark the beginning of the landing pad. Deletion of the 898 // landing pad can thus be detected via the MachineModuleInfo. 899 MCSymbol *Label = MMI->addLandingPad(BB); 900 901 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 902 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 903 904 // Mark exception register as live in. 905 unsigned Reg = TLI.getExceptionAddressRegister(); 906 if (Reg) BB->addLiveIn(Reg); 907 908 // Mark exception selector register as live in. 909 Reg = TLI.getExceptionSelectorRegister(); 910 if (Reg) BB->addLiveIn(Reg); 911 912 // FIXME: Hack around an exception handling flaw (PR1508): the personality 913 // function and list of typeids logically belong to the invoke (or, if you 914 // like, the basic block containing the invoke), and need to be associated 915 // with it in the dwarf exception handling tables. Currently however the 916 // information is provided by an intrinsic (eh.selector) that can be moved 917 // to unexpected places by the optimizers: if the unwind edge is critical, 918 // then breaking it can result in the intrinsics being in the successor of 919 // the landing pad, not the landing pad itself. This results 920 // in exceptions not being caught because no typeids are associated with 921 // the invoke. This may not be the only way things can go wrong, but it 922 // is the only way we try to work around for the moment. 923 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 924 925 if (Br && Br->isUnconditional()) { // Critical edge? 926 BasicBlock::iterator I, E; 927 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 928 if (isa<EHSelectorInst>(I)) 929 break; 930 931 if (I == E) 932 // No catch info found - try to extract some from the successor. 933 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 934 } 935 } 936 937 // Before doing SelectionDAG ISel, see if FastISel has been requested. 938 if (FastIS && !SuppressFastISel) { 939 // Emit code for any incoming arguments. This must happen before 940 // beginning FastISel on the entry block. 941 if (LLVMBB == &Fn.getEntryBlock()) { 942 CurDAG->setRoot(SDB->getControlRoot()); 943 CodeGenAndEmitDAG(); 944 SDB->clear(); 945 } 946 FastIS->startNewBlock(BB); 947 // Do FastISel on as many instructions as possible. 948 for (; BI != End; ++BI) { 949 // Just before the terminator instruction, insert instructions to 950 // feed PHI nodes in successor blocks. 951 if (isa<TerminatorInst>(BI)) 952 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 953 ++NumFastIselFailures; 954 ResetDebugLoc(SDB, FastIS); 955 if (EnableFastISelVerbose || EnableFastISelAbort) { 956 dbgs() << "FastISel miss: "; 957 BI->dump(); 958 } 959 assert(!EnableFastISelAbort && 960 "FastISel didn't handle a PHI in a successor"); 961 break; 962 } 963 964 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 965 966 // Try to select the instruction with FastISel. 967 if (FastIS->SelectInstruction(BI)) { 968 ResetDebugLoc(SDB, FastIS); 969 continue; 970 } 971 972 // Clear out the debug location so that it doesn't carry over to 973 // unrelated instructions. 974 ResetDebugLoc(SDB, FastIS); 975 976 // Then handle certain instructions as single-LLVM-Instruction blocks. 977 if (isa<CallInst>(BI)) { 978 ++NumFastIselFailures; 979 if (EnableFastISelVerbose || EnableFastISelAbort) { 980 dbgs() << "FastISel missed call: "; 981 BI->dump(); 982 } 983 984 if (!BI->getType()->isVoidTy()) { 985 unsigned &R = FuncInfo->ValueMap[BI]; 986 if (!R) 987 R = FuncInfo->CreateRegForValue(BI); 988 } 989 990 bool HadTailCall = false; 991 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 992 993 // If the call was emitted as a tail call, we're done with the block. 994 if (HadTailCall) { 995 BI = End; 996 break; 997 } 998 999 // If the instruction was codegen'd with multiple blocks, 1000 // inform the FastISel object where to resume inserting. 1001 FastIS->setCurrentBlock(BB); 1002 continue; 1003 } 1004 1005 // Otherwise, give up on FastISel for the rest of the block. 1006 // For now, be a little lenient about non-branch terminators. 1007 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 1008 ++NumFastIselFailures; 1009 if (EnableFastISelVerbose || EnableFastISelAbort) { 1010 dbgs() << "FastISel miss: "; 1011 BI->dump(); 1012 } 1013 if (EnableFastISelAbort) 1014 // The "fast" selector couldn't handle something and bailed. 1015 // For the purpose of debugging, just abort. 1016 llvm_unreachable("FastISel didn't select the entire block"); 1017 } 1018 break; 1019 } 1020 } 1021 1022 // Run SelectionDAG instruction selection on the remainder of the block 1023 // not handled by FastISel. If FastISel is not run, this is the entire 1024 // block. 1025 if (BI != End) { 1026 bool HadTailCall; 1027 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1028 } 1029 1030 FinishBasicBlock(); 1031 } 1032 1033 delete FastIS; 1034} 1035 1036void 1037SelectionDAGISel::FinishBasicBlock() { 1038 1039 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1040 DEBUG(BB->dump()); 1041 1042 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1043 << SDB->PHINodesToUpdate.size() << "\n"); 1044 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1045 dbgs() << "Node " << i << " : (" 1046 << SDB->PHINodesToUpdate[i].first 1047 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1048 1049 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1050 // PHI nodes in successors. 1051 if (SDB->SwitchCases.empty() && 1052 SDB->JTCases.empty() && 1053 SDB->BitTestCases.empty()) { 1054 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1055 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1056 assert(PHI->isPHI() && 1057 "This is not a machine PHI node that we are updating!"); 1058 if (!BB->isSuccessor(PHI->getParent())) 1059 continue; 1060 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1061 false)); 1062 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1063 } 1064 SDB->PHINodesToUpdate.clear(); 1065 return; 1066 } 1067 1068 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1069 // Lower header first, if it wasn't already lowered 1070 if (!SDB->BitTestCases[i].Emitted) { 1071 // Set the current basic block to the mbb we wish to insert the code into 1072 BB = SDB->BitTestCases[i].Parent; 1073 SDB->setCurrentBasicBlock(BB); 1074 // Emit the code 1075 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1076 CurDAG->setRoot(SDB->getRoot()); 1077 CodeGenAndEmitDAG(); 1078 SDB->clear(); 1079 } 1080 1081 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1082 // Set the current basic block to the mbb we wish to insert the code into 1083 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1084 SDB->setCurrentBasicBlock(BB); 1085 // Emit the code 1086 if (j+1 != ej) 1087 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1088 SDB->BitTestCases[i].Reg, 1089 SDB->BitTestCases[i].Cases[j]); 1090 else 1091 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1092 SDB->BitTestCases[i].Reg, 1093 SDB->BitTestCases[i].Cases[j]); 1094 1095 1096 CurDAG->setRoot(SDB->getRoot()); 1097 CodeGenAndEmitDAG(); 1098 SDB->clear(); 1099 } 1100 1101 // Update PHI Nodes 1102 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1103 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1104 MachineBasicBlock *PHIBB = PHI->getParent(); 1105 assert(PHI->isPHI() && 1106 "This is not a machine PHI node that we are updating!"); 1107 // This is "default" BB. We have two jumps to it. From "header" BB and 1108 // from last "case" BB. 1109 if (PHIBB == SDB->BitTestCases[i].Default) { 1110 PHI->addOperand(MachineOperand:: 1111 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1112 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1113 PHI->addOperand(MachineOperand:: 1114 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1115 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1116 back().ThisBB)); 1117 } 1118 // One of "cases" BB. 1119 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1120 j != ej; ++j) { 1121 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1122 if (cBB->isSuccessor(PHIBB)) { 1123 PHI->addOperand(MachineOperand:: 1124 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1125 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1126 } 1127 } 1128 } 1129 } 1130 SDB->BitTestCases.clear(); 1131 1132 // If the JumpTable record is filled in, then we need to emit a jump table. 1133 // Updating the PHI nodes is tricky in this case, since we need to determine 1134 // whether the PHI is a successor of the range check MBB or the jump table MBB 1135 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1136 // Lower header first, if it wasn't already lowered 1137 if (!SDB->JTCases[i].first.Emitted) { 1138 // Set the current basic block to the mbb we wish to insert the code into 1139 BB = SDB->JTCases[i].first.HeaderBB; 1140 SDB->setCurrentBasicBlock(BB); 1141 // Emit the code 1142 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1143 CurDAG->setRoot(SDB->getRoot()); 1144 CodeGenAndEmitDAG(); 1145 SDB->clear(); 1146 } 1147 1148 // Set the current basic block to the mbb we wish to insert the code into 1149 BB = SDB->JTCases[i].second.MBB; 1150 SDB->setCurrentBasicBlock(BB); 1151 // Emit the code 1152 SDB->visitJumpTable(SDB->JTCases[i].second); 1153 CurDAG->setRoot(SDB->getRoot()); 1154 CodeGenAndEmitDAG(); 1155 SDB->clear(); 1156 1157 // Update PHI Nodes 1158 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1159 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1160 MachineBasicBlock *PHIBB = PHI->getParent(); 1161 assert(PHI->isPHI() && 1162 "This is not a machine PHI node that we are updating!"); 1163 // "default" BB. We can go there only from header BB. 1164 if (PHIBB == SDB->JTCases[i].second.Default) { 1165 PHI->addOperand 1166 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1167 PHI->addOperand 1168 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1169 } 1170 // JT BB. Just iterate over successors here 1171 if (BB->isSuccessor(PHIBB)) { 1172 PHI->addOperand 1173 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1174 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1175 } 1176 } 1177 } 1178 SDB->JTCases.clear(); 1179 1180 // If the switch block involved a branch to one of the actual successors, we 1181 // need to update PHI nodes in that block. 1182 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1183 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1184 assert(PHI->isPHI() && 1185 "This is not a machine PHI node that we are updating!"); 1186 if (BB->isSuccessor(PHI->getParent())) { 1187 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1188 false)); 1189 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1190 } 1191 } 1192 1193 // If we generated any switch lowering information, build and codegen any 1194 // additional DAGs necessary. 1195 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1196 // Set the current basic block to the mbb we wish to insert the code into 1197 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1198 SDB->setCurrentBasicBlock(BB); 1199 1200 // Emit the code 1201 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1202 CurDAG->setRoot(SDB->getRoot()); 1203 CodeGenAndEmitDAG(); 1204 1205 // Handle any PHI nodes in successors of this chunk, as if we were coming 1206 // from the original BB before switch expansion. Note that PHI nodes can 1207 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1208 // handle them the right number of times. 1209 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1210 // If new BB's are created during scheduling, the edges may have been 1211 // updated. That is, the edge from ThisBB to BB may have been split and 1212 // BB's predecessor is now another block. 1213 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1214 SDB->EdgeMapping.find(BB); 1215 if (EI != SDB->EdgeMapping.end()) 1216 ThisBB = EI->second; 1217 1218 // BB may have been removed from the CFG if a branch was constant folded. 1219 if (ThisBB->isSuccessor(BB)) { 1220 for (MachineBasicBlock::iterator Phi = BB->begin(); 1221 Phi != BB->end() && Phi->isPHI(); 1222 ++Phi) { 1223 // This value for this PHI node is recorded in PHINodesToUpdate. 1224 for (unsigned pn = 0; ; ++pn) { 1225 assert(pn != SDB->PHINodesToUpdate.size() && 1226 "Didn't find PHI entry!"); 1227 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1228 Phi->addOperand(MachineOperand:: 1229 CreateReg(SDB->PHINodesToUpdate[pn].second, 1230 false)); 1231 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1232 break; 1233 } 1234 } 1235 } 1236 } 1237 1238 // Don't process RHS if same block as LHS. 1239 if (BB == SDB->SwitchCases[i].FalseBB) 1240 SDB->SwitchCases[i].FalseBB = 0; 1241 1242 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1243 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1244 SDB->SwitchCases[i].FalseBB = 0; 1245 } 1246 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1247 SDB->clear(); 1248 } 1249 SDB->SwitchCases.clear(); 1250 1251 SDB->PHINodesToUpdate.clear(); 1252} 1253 1254 1255/// Create the scheduler. If a specific scheduler was specified 1256/// via the SchedulerRegistry, use it, otherwise select the 1257/// one preferred by the target. 1258/// 1259ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1260 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1261 1262 if (!Ctor) { 1263 Ctor = ISHeuristic; 1264 RegisterScheduler::setDefault(Ctor); 1265 } 1266 1267 return Ctor(this, OptLevel); 1268} 1269 1270ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1271 return new ScheduleHazardRecognizer(); 1272} 1273 1274//===----------------------------------------------------------------------===// 1275// Helper functions used by the generated instruction selector. 1276//===----------------------------------------------------------------------===// 1277// Calls to these methods are generated by tblgen. 1278 1279/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1280/// the dag combiner simplified the 255, we still want to match. RHS is the 1281/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1282/// specified in the .td file (e.g. 255). 1283bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1284 int64_t DesiredMaskS) const { 1285 const APInt &ActualMask = RHS->getAPIntValue(); 1286 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1287 1288 // If the actual mask exactly matches, success! 1289 if (ActualMask == DesiredMask) 1290 return true; 1291 1292 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1293 if (ActualMask.intersects(~DesiredMask)) 1294 return false; 1295 1296 // Otherwise, the DAG Combiner may have proven that the value coming in is 1297 // either already zero or is not demanded. Check for known zero input bits. 1298 APInt NeededMask = DesiredMask & ~ActualMask; 1299 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1300 return true; 1301 1302 // TODO: check to see if missing bits are just not demanded. 1303 1304 // Otherwise, this pattern doesn't match. 1305 return false; 1306} 1307 1308/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1309/// the dag combiner simplified the 255, we still want to match. RHS is the 1310/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1311/// specified in the .td file (e.g. 255). 1312bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1313 int64_t DesiredMaskS) const { 1314 const APInt &ActualMask = RHS->getAPIntValue(); 1315 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1316 1317 // If the actual mask exactly matches, success! 1318 if (ActualMask == DesiredMask) 1319 return true; 1320 1321 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1322 if (ActualMask.intersects(~DesiredMask)) 1323 return false; 1324 1325 // Otherwise, the DAG Combiner may have proven that the value coming in is 1326 // either already zero or is not demanded. Check for known zero input bits. 1327 APInt NeededMask = DesiredMask & ~ActualMask; 1328 1329 APInt KnownZero, KnownOne; 1330 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1331 1332 // If all the missing bits in the or are already known to be set, match! 1333 if ((NeededMask & KnownOne) == NeededMask) 1334 return true; 1335 1336 // TODO: check to see if missing bits are just not demanded. 1337 1338 // Otherwise, this pattern doesn't match. 1339 return false; 1340} 1341 1342 1343/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1344/// by tblgen. Others should not call it. 1345void SelectionDAGISel:: 1346SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1347 std::vector<SDValue> InOps; 1348 std::swap(InOps, Ops); 1349 1350 Ops.push_back(InOps[0]); // input chain. 1351 Ops.push_back(InOps[1]); // input asm string. 1352 1353 unsigned i = 2, e = InOps.size(); 1354 if (InOps[e-1].getValueType() == MVT::Flag) 1355 --e; // Don't process a flag operand if it is here. 1356 1357 while (i != e) { 1358 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1359 if ((Flags & 7) != 4 /*MEM*/) { 1360 // Just skip over this operand, copying the operands verbatim. 1361 Ops.insert(Ops.end(), InOps.begin()+i, 1362 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1363 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1364 } else { 1365 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1366 "Memory operand with multiple values?"); 1367 // Otherwise, this is a memory operand. Ask the target to select it. 1368 std::vector<SDValue> SelOps; 1369 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1370 llvm_report_error("Could not match memory address. Inline asm" 1371 " failure!"); 1372 } 1373 1374 // Add this to the output node. 1375 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1376 MVT::i32)); 1377 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1378 i += 2; 1379 } 1380 } 1381 1382 // Add the flag input back if present. 1383 if (e != InOps.size()) 1384 Ops.push_back(InOps.back()); 1385} 1386 1387/// findFlagUse - Return use of EVT::Flag value produced by the specified 1388/// SDNode. 1389/// 1390static SDNode *findFlagUse(SDNode *N) { 1391 unsigned FlagResNo = N->getNumValues()-1; 1392 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1393 SDUse &Use = I.getUse(); 1394 if (Use.getResNo() == FlagResNo) 1395 return Use.getUser(); 1396 } 1397 return NULL; 1398} 1399 1400/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1401/// This function recursively traverses up the operand chain, ignoring 1402/// certain nodes. 1403static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1404 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1405 bool IgnoreChains) { 1406 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1407 // greater than all of its (recursive) operands. If we scan to a point where 1408 // 'use' is smaller than the node we're scanning for, then we know we will 1409 // never find it. 1410 // 1411 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1412 // happen because we scan down to newly selected nodes in the case of flag 1413 // uses. 1414 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1415 return false; 1416 1417 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1418 // won't fail if we scan it again. 1419 if (!Visited.insert(Use)) 1420 return false; 1421 1422 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1423 // Ignore chain uses, they are validated by HandleMergeInputChains. 1424 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1425 continue; 1426 1427 SDNode *N = Use->getOperand(i).getNode(); 1428 if (N == Def) { 1429 if (Use == ImmedUse || Use == Root) 1430 continue; // We are not looking for immediate use. 1431 assert(N != Root); 1432 return true; 1433 } 1434 1435 // Traverse up the operand chain. 1436 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1437 return true; 1438 } 1439 return false; 1440} 1441 1442/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1443/// operand node N of U during instruction selection that starts at Root. 1444bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1445 SDNode *Root) const { 1446 if (OptLevel == CodeGenOpt::None) return false; 1447 return N.hasOneUse(); 1448} 1449 1450/// IsLegalToFold - Returns true if the specific operand node N of 1451/// U can be folded during instruction selection that starts at Root. 1452bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1453 bool IgnoreChains) const { 1454 if (OptLevel == CodeGenOpt::None) return false; 1455 1456 // If Root use can somehow reach N through a path that that doesn't contain 1457 // U then folding N would create a cycle. e.g. In the following 1458 // diagram, Root can reach N through X. If N is folded into into Root, then 1459 // X is both a predecessor and a successor of U. 1460 // 1461 // [N*] // 1462 // ^ ^ // 1463 // / \ // 1464 // [U*] [X]? // 1465 // ^ ^ // 1466 // \ / // 1467 // \ / // 1468 // [Root*] // 1469 // 1470 // * indicates nodes to be folded together. 1471 // 1472 // If Root produces a flag, then it gets (even more) interesting. Since it 1473 // will be "glued" together with its flag use in the scheduler, we need to 1474 // check if it might reach N. 1475 // 1476 // [N*] // 1477 // ^ ^ // 1478 // / \ // 1479 // [U*] [X]? // 1480 // ^ ^ // 1481 // \ \ // 1482 // \ | // 1483 // [Root*] | // 1484 // ^ | // 1485 // f | // 1486 // | / // 1487 // [Y] / // 1488 // ^ / // 1489 // f / // 1490 // | / // 1491 // [FU] // 1492 // 1493 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1494 // (call it Fold), then X is a predecessor of FU and a successor of 1495 // Fold. But since Fold and FU are flagged together, this will create 1496 // a cycle in the scheduling graph. 1497 1498 // If the node has flags, walk down the graph to the "lowest" node in the 1499 // flagged set. 1500 EVT VT = Root->getValueType(Root->getNumValues()-1); 1501 while (VT == MVT::Flag) { 1502 SDNode *FU = findFlagUse(Root); 1503 if (FU == NULL) 1504 break; 1505 Root = FU; 1506 VT = Root->getValueType(Root->getNumValues()-1); 1507 1508 // If our query node has a flag result with a use, we've walked up it. If 1509 // the user (which has already been selected) has a chain or indirectly uses 1510 // the chain, our WalkChainUsers predicate will not consider it. Because of 1511 // this, we cannot ignore chains in this predicate. 1512 IgnoreChains = false; 1513 } 1514 1515 1516 SmallPtrSet<SDNode*, 16> Visited; 1517 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1518} 1519 1520SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1521 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1522 SelectInlineAsmMemoryOperands(Ops); 1523 1524 std::vector<EVT> VTs; 1525 VTs.push_back(MVT::Other); 1526 VTs.push_back(MVT::Flag); 1527 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1528 VTs, &Ops[0], Ops.size()); 1529 New->setNodeId(-1); 1530 return New.getNode(); 1531} 1532 1533SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1534 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1535} 1536 1537/// GetVBR - decode a vbr encoding whose top bit is set. 1538ALWAYS_INLINE static uint64_t 1539GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1540 assert(Val >= 128 && "Not a VBR"); 1541 Val &= 127; // Remove first vbr bit. 1542 1543 unsigned Shift = 7; 1544 uint64_t NextBits; 1545 do { 1546 NextBits = MatcherTable[Idx++]; 1547 Val |= (NextBits&127) << Shift; 1548 Shift += 7; 1549 } while (NextBits & 128); 1550 1551 return Val; 1552} 1553 1554 1555/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1556/// interior flag and chain results to use the new flag and chain results. 1557void SelectionDAGISel:: 1558UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1559 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1560 SDValue InputFlag, 1561 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1562 bool isMorphNodeTo) { 1563 SmallVector<SDNode*, 4> NowDeadNodes; 1564 1565 ISelUpdater ISU(ISelPosition); 1566 1567 // Now that all the normal results are replaced, we replace the chain and 1568 // flag results if present. 1569 if (!ChainNodesMatched.empty()) { 1570 assert(InputChain.getNode() != 0 && 1571 "Matched input chains but didn't produce a chain"); 1572 // Loop over all of the nodes we matched that produced a chain result. 1573 // Replace all the chain results with the final chain we ended up with. 1574 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1575 SDNode *ChainNode = ChainNodesMatched[i]; 1576 1577 // If this node was already deleted, don't look at it. 1578 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1579 continue; 1580 1581 // Don't replace the results of the root node if we're doing a 1582 // MorphNodeTo. 1583 if (ChainNode == NodeToMatch && isMorphNodeTo) 1584 continue; 1585 1586 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1587 if (ChainVal.getValueType() == MVT::Flag) 1588 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1589 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1590 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1591 1592 // If the node became dead and we haven't already seen it, delete it. 1593 if (ChainNode->use_empty() && 1594 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1595 NowDeadNodes.push_back(ChainNode); 1596 } 1597 } 1598 1599 // If the result produces a flag, update any flag results in the matched 1600 // pattern with the flag result. 1601 if (InputFlag.getNode() != 0) { 1602 // Handle any interior nodes explicitly marked. 1603 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1604 SDNode *FRN = FlagResultNodesMatched[i]; 1605 1606 // If this node was already deleted, don't look at it. 1607 if (FRN->getOpcode() == ISD::DELETED_NODE) 1608 continue; 1609 1610 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1611 "Doesn't have a flag result"); 1612 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1613 InputFlag, &ISU); 1614 1615 // If the node became dead and we haven't already seen it, delete it. 1616 if (FRN->use_empty() && 1617 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1618 NowDeadNodes.push_back(FRN); 1619 } 1620 } 1621 1622 if (!NowDeadNodes.empty()) 1623 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1624 1625 DEBUG(errs() << "ISEL: Match complete!\n"); 1626} 1627 1628enum ChainResult { 1629 CR_Simple, 1630 CR_InducesCycle, 1631 CR_LeadsToInteriorNode 1632}; 1633 1634/// WalkChainUsers - Walk down the users of the specified chained node that is 1635/// part of the pattern we're matching, looking at all of the users we find. 1636/// This determines whether something is an interior node, whether we have a 1637/// non-pattern node in between two pattern nodes (which prevent folding because 1638/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1639/// between pattern nodes (in which case the TF becomes part of the pattern). 1640/// 1641/// The walk we do here is guaranteed to be small because we quickly get down to 1642/// already selected nodes "below" us. 1643static ChainResult 1644WalkChainUsers(SDNode *ChainedNode, 1645 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1646 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1647 ChainResult Result = CR_Simple; 1648 1649 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1650 E = ChainedNode->use_end(); UI != E; ++UI) { 1651 // Make sure the use is of the chain, not some other value we produce. 1652 if (UI.getUse().getValueType() != MVT::Other) continue; 1653 1654 SDNode *User = *UI; 1655 1656 // If we see an already-selected machine node, then we've gone beyond the 1657 // pattern that we're selecting down into the already selected chunk of the 1658 // DAG. 1659 if (User->isMachineOpcode() || 1660 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1661 continue; 1662 1663 if (User->getOpcode() == ISD::CopyToReg || 1664 User->getOpcode() == ISD::CopyFromReg || 1665 User->getOpcode() == ISD::INLINEASM || 1666 User->getOpcode() == ISD::EH_LABEL) { 1667 // If their node ID got reset to -1 then they've already been selected. 1668 // Treat them like a MachineOpcode. 1669 if (User->getNodeId() == -1) 1670 continue; 1671 } 1672 1673 // If we have a TokenFactor, we handle it specially. 1674 if (User->getOpcode() != ISD::TokenFactor) { 1675 // If the node isn't a token factor and isn't part of our pattern, then it 1676 // must be a random chained node in between two nodes we're selecting. 1677 // This happens when we have something like: 1678 // x = load ptr 1679 // call 1680 // y = x+4 1681 // store y -> ptr 1682 // Because we structurally match the load/store as a read/modify/write, 1683 // but the call is chained between them. We cannot fold in this case 1684 // because it would induce a cycle in the graph. 1685 if (!std::count(ChainedNodesInPattern.begin(), 1686 ChainedNodesInPattern.end(), User)) 1687 return CR_InducesCycle; 1688 1689 // Otherwise we found a node that is part of our pattern. For example in: 1690 // x = load ptr 1691 // y = x+4 1692 // store y -> ptr 1693 // This would happen when we're scanning down from the load and see the 1694 // store as a user. Record that there is a use of ChainedNode that is 1695 // part of the pattern and keep scanning uses. 1696 Result = CR_LeadsToInteriorNode; 1697 InteriorChainedNodes.push_back(User); 1698 continue; 1699 } 1700 1701 // If we found a TokenFactor, there are two cases to consider: first if the 1702 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1703 // uses of the TF are in our pattern) we just want to ignore it. Second, 1704 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1705 // [Load chain] 1706 // ^ 1707 // | 1708 // [Load] 1709 // ^ ^ 1710 // | \ DAG's like cheese 1711 // / \ do you? 1712 // / | 1713 // [TokenFactor] [Op] 1714 // ^ ^ 1715 // | | 1716 // \ / 1717 // \ / 1718 // [Store] 1719 // 1720 // In this case, the TokenFactor becomes part of our match and we rewrite it 1721 // as a new TokenFactor. 1722 // 1723 // To distinguish these two cases, do a recursive walk down the uses. 1724 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1725 case CR_Simple: 1726 // If the uses of the TokenFactor are just already-selected nodes, ignore 1727 // it, it is "below" our pattern. 1728 continue; 1729 case CR_InducesCycle: 1730 // If the uses of the TokenFactor lead to nodes that are not part of our 1731 // pattern that are not selected, folding would turn this into a cycle, 1732 // bail out now. 1733 return CR_InducesCycle; 1734 case CR_LeadsToInteriorNode: 1735 break; // Otherwise, keep processing. 1736 } 1737 1738 // Okay, we know we're in the interesting interior case. The TokenFactor 1739 // is now going to be considered part of the pattern so that we rewrite its 1740 // uses (it may have uses that are not part of the pattern) with the 1741 // ultimate chain result of the generated code. We will also add its chain 1742 // inputs as inputs to the ultimate TokenFactor we create. 1743 Result = CR_LeadsToInteriorNode; 1744 ChainedNodesInPattern.push_back(User); 1745 InteriorChainedNodes.push_back(User); 1746 continue; 1747 } 1748 1749 return Result; 1750} 1751 1752/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1753/// operation for when the pattern matched at least one node with a chains. The 1754/// input vector contains a list of all of the chained nodes that we match. We 1755/// must determine if this is a valid thing to cover (i.e. matching it won't 1756/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1757/// be used as the input node chain for the generated nodes. 1758static SDValue 1759HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1760 SelectionDAG *CurDAG) { 1761 // Walk all of the chained nodes we've matched, recursively scanning down the 1762 // users of the chain result. This adds any TokenFactor nodes that are caught 1763 // in between chained nodes to the chained and interior nodes list. 1764 SmallVector<SDNode*, 3> InteriorChainedNodes; 1765 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1766 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1767 InteriorChainedNodes) == CR_InducesCycle) 1768 return SDValue(); // Would induce a cycle. 1769 } 1770 1771 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1772 // that we are interested in. Form our input TokenFactor node. 1773 SmallVector<SDValue, 3> InputChains; 1774 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1775 // Add the input chain of this node to the InputChains list (which will be 1776 // the operands of the generated TokenFactor) if it's not an interior node. 1777 SDNode *N = ChainNodesMatched[i]; 1778 if (N->getOpcode() != ISD::TokenFactor) { 1779 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1780 continue; 1781 1782 // Otherwise, add the input chain. 1783 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1784 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1785 InputChains.push_back(InChain); 1786 continue; 1787 } 1788 1789 // If we have a token factor, we want to add all inputs of the token factor 1790 // that are not part of the pattern we're matching. 1791 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1792 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1793 N->getOperand(op).getNode())) 1794 InputChains.push_back(N->getOperand(op)); 1795 } 1796 } 1797 1798 SDValue Res; 1799 if (InputChains.size() == 1) 1800 return InputChains[0]; 1801 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1802 MVT::Other, &InputChains[0], InputChains.size()); 1803} 1804 1805/// MorphNode - Handle morphing a node in place for the selector. 1806SDNode *SelectionDAGISel:: 1807MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1808 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1809 // It is possible we're using MorphNodeTo to replace a node with no 1810 // normal results with one that has a normal result (or we could be 1811 // adding a chain) and the input could have flags and chains as well. 1812 // In this case we need to shift the operands down. 1813 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1814 // than the old isel though. 1815 int OldFlagResultNo = -1, OldChainResultNo = -1; 1816 1817 unsigned NTMNumResults = Node->getNumValues(); 1818 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1819 OldFlagResultNo = NTMNumResults-1; 1820 if (NTMNumResults != 1 && 1821 Node->getValueType(NTMNumResults-2) == MVT::Other) 1822 OldChainResultNo = NTMNumResults-2; 1823 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1824 OldChainResultNo = NTMNumResults-1; 1825 1826 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1827 // that this deletes operands of the old node that become dead. 1828 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1829 1830 // MorphNodeTo can operate in two ways: if an existing node with the 1831 // specified operands exists, it can just return it. Otherwise, it 1832 // updates the node in place to have the requested operands. 1833 if (Res == Node) { 1834 // If we updated the node in place, reset the node ID. To the isel, 1835 // this should be just like a newly allocated machine node. 1836 Res->setNodeId(-1); 1837 } 1838 1839 unsigned ResNumResults = Res->getNumValues(); 1840 // Move the flag if needed. 1841 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1842 (unsigned)OldFlagResultNo != ResNumResults-1) 1843 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1844 SDValue(Res, ResNumResults-1)); 1845 1846 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1847 --ResNumResults; 1848 1849 // Move the chain reference if needed. 1850 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1851 (unsigned)OldChainResultNo != ResNumResults-1) 1852 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1853 SDValue(Res, ResNumResults-1)); 1854 1855 // Otherwise, no replacement happened because the node already exists. Replace 1856 // Uses of the old node with the new one. 1857 if (Res != Node) 1858 CurDAG->ReplaceAllUsesWith(Node, Res); 1859 1860 return Res; 1861} 1862 1863/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1864ALWAYS_INLINE static bool 1865CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1866 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1867 // Accept if it is exactly the same as a previously recorded node. 1868 unsigned RecNo = MatcherTable[MatcherIndex++]; 1869 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1870 return N == RecordedNodes[RecNo]; 1871} 1872 1873/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1874ALWAYS_INLINE static bool 1875CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1876 SelectionDAGISel &SDISel) { 1877 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1878} 1879 1880/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1881ALWAYS_INLINE static bool 1882CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1883 SelectionDAGISel &SDISel, SDNode *N) { 1884 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1885} 1886 1887ALWAYS_INLINE static bool 1888CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1889 SDNode *N) { 1890 uint16_t Opc = MatcherTable[MatcherIndex++]; 1891 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1892 return N->getOpcode() == Opc; 1893} 1894 1895ALWAYS_INLINE static bool 1896CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1897 SDValue N, const TargetLowering &TLI) { 1898 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1899 if (N.getValueType() == VT) return true; 1900 1901 // Handle the case when VT is iPTR. 1902 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1903} 1904 1905ALWAYS_INLINE static bool 1906CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1907 SDValue N, const TargetLowering &TLI, 1908 unsigned ChildNo) { 1909 if (ChildNo >= N.getNumOperands()) 1910 return false; // Match fails if out of range child #. 1911 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1912} 1913 1914 1915ALWAYS_INLINE static bool 1916CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1917 SDValue N) { 1918 return cast<CondCodeSDNode>(N)->get() == 1919 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1920} 1921 1922ALWAYS_INLINE static bool 1923CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1924 SDValue N, const TargetLowering &TLI) { 1925 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1926 if (cast<VTSDNode>(N)->getVT() == VT) 1927 return true; 1928 1929 // Handle the case when VT is iPTR. 1930 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1931} 1932 1933ALWAYS_INLINE static bool 1934CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1935 SDValue N) { 1936 int64_t Val = MatcherTable[MatcherIndex++]; 1937 if (Val & 128) 1938 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1939 1940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1941 return C != 0 && C->getSExtValue() == Val; 1942} 1943 1944ALWAYS_INLINE static bool 1945CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1946 SDValue N, SelectionDAGISel &SDISel) { 1947 int64_t Val = MatcherTable[MatcherIndex++]; 1948 if (Val & 128) 1949 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1950 1951 if (N->getOpcode() != ISD::AND) return false; 1952 1953 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1954 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1955} 1956 1957ALWAYS_INLINE static bool 1958CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1959 SDValue N, SelectionDAGISel &SDISel) { 1960 int64_t Val = MatcherTable[MatcherIndex++]; 1961 if (Val & 128) 1962 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1963 1964 if (N->getOpcode() != ISD::OR) return false; 1965 1966 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1967 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1968} 1969 1970/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1971/// scope, evaluate the current node. If the current predicate is known to 1972/// fail, set Result=true and return anything. If the current predicate is 1973/// known to pass, set Result=false and return the MatcherIndex to continue 1974/// with. If the current predicate is unknown, set Result=false and return the 1975/// MatcherIndex to continue with. 1976static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1977 unsigned Index, SDValue N, 1978 bool &Result, SelectionDAGISel &SDISel, 1979 SmallVectorImpl<SDValue> &RecordedNodes){ 1980 switch (Table[Index++]) { 1981 default: 1982 Result = false; 1983 return Index-1; // Could not evaluate this predicate. 1984 case SelectionDAGISel::OPC_CheckSame: 1985 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1986 return Index; 1987 case SelectionDAGISel::OPC_CheckPatternPredicate: 1988 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1989 return Index; 1990 case SelectionDAGISel::OPC_CheckPredicate: 1991 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1992 return Index; 1993 case SelectionDAGISel::OPC_CheckOpcode: 1994 Result = !::CheckOpcode(Table, Index, N.getNode()); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckType: 1997 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckChild0Type: 2000 case SelectionDAGISel::OPC_CheckChild1Type: 2001 case SelectionDAGISel::OPC_CheckChild2Type: 2002 case SelectionDAGISel::OPC_CheckChild3Type: 2003 case SelectionDAGISel::OPC_CheckChild4Type: 2004 case SelectionDAGISel::OPC_CheckChild5Type: 2005 case SelectionDAGISel::OPC_CheckChild6Type: 2006 case SelectionDAGISel::OPC_CheckChild7Type: 2007 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2008 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2009 return Index; 2010 case SelectionDAGISel::OPC_CheckCondCode: 2011 Result = !::CheckCondCode(Table, Index, N); 2012 return Index; 2013 case SelectionDAGISel::OPC_CheckValueType: 2014 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2015 return Index; 2016 case SelectionDAGISel::OPC_CheckInteger: 2017 Result = !::CheckInteger(Table, Index, N); 2018 return Index; 2019 case SelectionDAGISel::OPC_CheckAndImm: 2020 Result = !::CheckAndImm(Table, Index, N, SDISel); 2021 return Index; 2022 case SelectionDAGISel::OPC_CheckOrImm: 2023 Result = !::CheckOrImm(Table, Index, N, SDISel); 2024 return Index; 2025 } 2026} 2027 2028 2029struct MatchScope { 2030 /// FailIndex - If this match fails, this is the index to continue with. 2031 unsigned FailIndex; 2032 2033 /// NodeStack - The node stack when the scope was formed. 2034 SmallVector<SDValue, 4> NodeStack; 2035 2036 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2037 unsigned NumRecordedNodes; 2038 2039 /// NumMatchedMemRefs - The number of matched memref entries. 2040 unsigned NumMatchedMemRefs; 2041 2042 /// InputChain/InputFlag - The current chain/flag 2043 SDValue InputChain, InputFlag; 2044 2045 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2046 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2047}; 2048 2049SDNode *SelectionDAGISel:: 2050SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2051 unsigned TableSize) { 2052 // FIXME: Should these even be selected? Handle these cases in the caller? 2053 switch (NodeToMatch->getOpcode()) { 2054 default: 2055 break; 2056 case ISD::EntryToken: // These nodes remain the same. 2057 case ISD::BasicBlock: 2058 case ISD::Register: 2059 //case ISD::VALUETYPE: 2060 //case ISD::CONDCODE: 2061 case ISD::HANDLENODE: 2062 case ISD::TargetConstant: 2063 case ISD::TargetConstantFP: 2064 case ISD::TargetConstantPool: 2065 case ISD::TargetFrameIndex: 2066 case ISD::TargetExternalSymbol: 2067 case ISD::TargetBlockAddress: 2068 case ISD::TargetJumpTable: 2069 case ISD::TargetGlobalTLSAddress: 2070 case ISD::TargetGlobalAddress: 2071 case ISD::TokenFactor: 2072 case ISD::CopyFromReg: 2073 case ISD::CopyToReg: 2074 case ISD::EH_LABEL: 2075 NodeToMatch->setNodeId(-1); // Mark selected. 2076 return 0; 2077 case ISD::AssertSext: 2078 case ISD::AssertZext: 2079 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2080 NodeToMatch->getOperand(0)); 2081 return 0; 2082 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2083 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2084 } 2085 2086 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2087 2088 // Set up the node stack with NodeToMatch as the only node on the stack. 2089 SmallVector<SDValue, 8> NodeStack; 2090 SDValue N = SDValue(NodeToMatch, 0); 2091 NodeStack.push_back(N); 2092 2093 // MatchScopes - Scopes used when matching, if a match failure happens, this 2094 // indicates where to continue checking. 2095 SmallVector<MatchScope, 8> MatchScopes; 2096 2097 // RecordedNodes - This is the set of nodes that have been recorded by the 2098 // state machine. 2099 SmallVector<SDValue, 8> RecordedNodes; 2100 2101 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2102 // pattern. 2103 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2104 2105 // These are the current input chain and flag for use when generating nodes. 2106 // Various Emit operations change these. For example, emitting a copytoreg 2107 // uses and updates these. 2108 SDValue InputChain, InputFlag; 2109 2110 // ChainNodesMatched - If a pattern matches nodes that have input/output 2111 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2112 // which ones they are. The result is captured into this list so that we can 2113 // update the chain results when the pattern is complete. 2114 SmallVector<SDNode*, 3> ChainNodesMatched; 2115 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2116 2117 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2118 NodeToMatch->dump(CurDAG); 2119 errs() << '\n'); 2120 2121 // Determine where to start the interpreter. Normally we start at opcode #0, 2122 // but if the state machine starts with an OPC_SwitchOpcode, then we 2123 // accelerate the first lookup (which is guaranteed to be hot) with the 2124 // OpcodeOffset table. 2125 unsigned MatcherIndex = 0; 2126 2127 if (!OpcodeOffset.empty()) { 2128 // Already computed the OpcodeOffset table, just index into it. 2129 if (N.getOpcode() < OpcodeOffset.size()) 2130 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2131 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2132 2133 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2134 // Otherwise, the table isn't computed, but the state machine does start 2135 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2136 // is the first time we're selecting an instruction. 2137 unsigned Idx = 1; 2138 while (1) { 2139 // Get the size of this case. 2140 unsigned CaseSize = MatcherTable[Idx++]; 2141 if (CaseSize & 128) 2142 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2143 if (CaseSize == 0) break; 2144 2145 // Get the opcode, add the index to the table. 2146 uint16_t Opc = MatcherTable[Idx++]; 2147 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2148 if (Opc >= OpcodeOffset.size()) 2149 OpcodeOffset.resize((Opc+1)*2); 2150 OpcodeOffset[Opc] = Idx; 2151 Idx += CaseSize; 2152 } 2153 2154 // Okay, do the lookup for the first opcode. 2155 if (N.getOpcode() < OpcodeOffset.size()) 2156 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2157 } 2158 2159 while (1) { 2160 assert(MatcherIndex < TableSize && "Invalid index"); 2161#ifndef NDEBUG 2162 unsigned CurrentOpcodeIndex = MatcherIndex; 2163#endif 2164 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2165 switch (Opcode) { 2166 case OPC_Scope: { 2167 // Okay, the semantics of this operation are that we should push a scope 2168 // then evaluate the first child. However, pushing a scope only to have 2169 // the first check fail (which then pops it) is inefficient. If we can 2170 // determine immediately that the first check (or first several) will 2171 // immediately fail, don't even bother pushing a scope for them. 2172 unsigned FailIndex; 2173 2174 while (1) { 2175 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2176 if (NumToSkip & 128) 2177 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2178 // Found the end of the scope with no match. 2179 if (NumToSkip == 0) { 2180 FailIndex = 0; 2181 break; 2182 } 2183 2184 FailIndex = MatcherIndex+NumToSkip; 2185 2186 unsigned MatcherIndexOfPredicate = MatcherIndex; 2187 (void)MatcherIndexOfPredicate; // silence warning. 2188 2189 // If we can't evaluate this predicate without pushing a scope (e.g. if 2190 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2191 // push the scope and evaluate the full predicate chain. 2192 bool Result; 2193 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2194 Result, *this, RecordedNodes); 2195 if (!Result) 2196 break; 2197 2198 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2199 << "index " << MatcherIndexOfPredicate 2200 << ", continuing at " << FailIndex << "\n"); 2201 2202 2203 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2204 // move to the next case. 2205 MatcherIndex = FailIndex; 2206 } 2207 2208 // If the whole scope failed to match, bail. 2209 if (FailIndex == 0) break; 2210 2211 // Push a MatchScope which indicates where to go if the first child fails 2212 // to match. 2213 MatchScope NewEntry; 2214 NewEntry.FailIndex = FailIndex; 2215 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2216 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2217 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2218 NewEntry.InputChain = InputChain; 2219 NewEntry.InputFlag = InputFlag; 2220 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2221 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2222 MatchScopes.push_back(NewEntry); 2223 continue; 2224 } 2225 case OPC_RecordNode: 2226 // Remember this node, it may end up being an operand in the pattern. 2227 RecordedNodes.push_back(N); 2228 continue; 2229 2230 case OPC_RecordChild0: case OPC_RecordChild1: 2231 case OPC_RecordChild2: case OPC_RecordChild3: 2232 case OPC_RecordChild4: case OPC_RecordChild5: 2233 case OPC_RecordChild6: case OPC_RecordChild7: { 2234 unsigned ChildNo = Opcode-OPC_RecordChild0; 2235 if (ChildNo >= N.getNumOperands()) 2236 break; // Match fails if out of range child #. 2237 2238 RecordedNodes.push_back(N->getOperand(ChildNo)); 2239 continue; 2240 } 2241 case OPC_RecordMemRef: 2242 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2243 continue; 2244 2245 case OPC_CaptureFlagInput: 2246 // If the current node has an input flag, capture it in InputFlag. 2247 if (N->getNumOperands() != 0 && 2248 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2249 InputFlag = N->getOperand(N->getNumOperands()-1); 2250 continue; 2251 2252 case OPC_MoveChild: { 2253 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2254 if (ChildNo >= N.getNumOperands()) 2255 break; // Match fails if out of range child #. 2256 N = N.getOperand(ChildNo); 2257 NodeStack.push_back(N); 2258 continue; 2259 } 2260 2261 case OPC_MoveParent: 2262 // Pop the current node off the NodeStack. 2263 NodeStack.pop_back(); 2264 assert(!NodeStack.empty() && "Node stack imbalance!"); 2265 N = NodeStack.back(); 2266 continue; 2267 2268 case OPC_CheckSame: 2269 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2270 continue; 2271 case OPC_CheckPatternPredicate: 2272 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2273 continue; 2274 case OPC_CheckPredicate: 2275 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2276 N.getNode())) 2277 break; 2278 continue; 2279 case OPC_CheckComplexPat: { 2280 unsigned CPNum = MatcherTable[MatcherIndex++]; 2281 unsigned RecNo = MatcherTable[MatcherIndex++]; 2282 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2283 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2284 RecordedNodes)) 2285 break; 2286 continue; 2287 } 2288 case OPC_CheckOpcode: 2289 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2290 continue; 2291 2292 case OPC_CheckType: 2293 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2294 continue; 2295 2296 case OPC_SwitchOpcode: { 2297 unsigned CurNodeOpcode = N.getOpcode(); 2298 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2299 unsigned CaseSize; 2300 while (1) { 2301 // Get the size of this case. 2302 CaseSize = MatcherTable[MatcherIndex++]; 2303 if (CaseSize & 128) 2304 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2305 if (CaseSize == 0) break; 2306 2307 uint16_t Opc = MatcherTable[MatcherIndex++]; 2308 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2309 2310 // If the opcode matches, then we will execute this case. 2311 if (CurNodeOpcode == Opc) 2312 break; 2313 2314 // Otherwise, skip over this case. 2315 MatcherIndex += CaseSize; 2316 } 2317 2318 // If no cases matched, bail out. 2319 if (CaseSize == 0) break; 2320 2321 // Otherwise, execute the case we found. 2322 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2323 << " to " << MatcherIndex << "\n"); 2324 continue; 2325 } 2326 2327 case OPC_SwitchType: { 2328 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2329 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2330 unsigned CaseSize; 2331 while (1) { 2332 // Get the size of this case. 2333 CaseSize = MatcherTable[MatcherIndex++]; 2334 if (CaseSize & 128) 2335 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2336 if (CaseSize == 0) break; 2337 2338 MVT::SimpleValueType CaseVT = 2339 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2340 if (CaseVT == MVT::iPTR) 2341 CaseVT = TLI.getPointerTy().SimpleTy; 2342 2343 // If the VT matches, then we will execute this case. 2344 if (CurNodeVT == CaseVT) 2345 break; 2346 2347 // Otherwise, skip over this case. 2348 MatcherIndex += CaseSize; 2349 } 2350 2351 // If no cases matched, bail out. 2352 if (CaseSize == 0) break; 2353 2354 // Otherwise, execute the case we found. 2355 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2356 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2357 continue; 2358 } 2359 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2360 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2361 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2362 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2363 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2364 Opcode-OPC_CheckChild0Type)) 2365 break; 2366 continue; 2367 case OPC_CheckCondCode: 2368 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2369 continue; 2370 case OPC_CheckValueType: 2371 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2372 continue; 2373 case OPC_CheckInteger: 2374 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2375 continue; 2376 case OPC_CheckAndImm: 2377 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2378 continue; 2379 case OPC_CheckOrImm: 2380 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2381 continue; 2382 2383 case OPC_CheckFoldableChainNode: { 2384 assert(NodeStack.size() != 1 && "No parent node"); 2385 // Verify that all intermediate nodes between the root and this one have 2386 // a single use. 2387 bool HasMultipleUses = false; 2388 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2389 if (!NodeStack[i].hasOneUse()) { 2390 HasMultipleUses = true; 2391 break; 2392 } 2393 if (HasMultipleUses) break; 2394 2395 // Check to see that the target thinks this is profitable to fold and that 2396 // we can fold it without inducing cycles in the graph. 2397 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2398 NodeToMatch) || 2399 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2400 NodeToMatch, true/*We validate our own chains*/)) 2401 break; 2402 2403 continue; 2404 } 2405 case OPC_EmitInteger: { 2406 MVT::SimpleValueType VT = 2407 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2408 int64_t Val = MatcherTable[MatcherIndex++]; 2409 if (Val & 128) 2410 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2411 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2412 continue; 2413 } 2414 case OPC_EmitRegister: { 2415 MVT::SimpleValueType VT = 2416 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2417 unsigned RegNo = MatcherTable[MatcherIndex++]; 2418 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2419 continue; 2420 } 2421 2422 case OPC_EmitConvertToTarget: { 2423 // Convert from IMM/FPIMM to target version. 2424 unsigned RecNo = MatcherTable[MatcherIndex++]; 2425 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2426 SDValue Imm = RecordedNodes[RecNo]; 2427 2428 if (Imm->getOpcode() == ISD::Constant) { 2429 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2430 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2431 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2432 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2433 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2434 } 2435 2436 RecordedNodes.push_back(Imm); 2437 continue; 2438 } 2439 2440 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2441 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2442 // These are space-optimized forms of OPC_EmitMergeInputChains. 2443 assert(InputChain.getNode() == 0 && 2444 "EmitMergeInputChains should be the first chain producing node"); 2445 assert(ChainNodesMatched.empty() && 2446 "Should only have one EmitMergeInputChains per match"); 2447 2448 // Read all of the chained nodes. 2449 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2450 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2451 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2452 2453 // FIXME: What if other value results of the node have uses not matched 2454 // by this pattern? 2455 if (ChainNodesMatched.back() != NodeToMatch && 2456 !RecordedNodes[RecNo].hasOneUse()) { 2457 ChainNodesMatched.clear(); 2458 break; 2459 } 2460 2461 // Merge the input chains if they are not intra-pattern references. 2462 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2463 2464 if (InputChain.getNode() == 0) 2465 break; // Failed to merge. 2466 continue; 2467 } 2468 2469 case OPC_EmitMergeInputChains: { 2470 assert(InputChain.getNode() == 0 && 2471 "EmitMergeInputChains should be the first chain producing node"); 2472 // This node gets a list of nodes we matched in the input that have 2473 // chains. We want to token factor all of the input chains to these nodes 2474 // together. However, if any of the input chains is actually one of the 2475 // nodes matched in this pattern, then we have an intra-match reference. 2476 // Ignore these because the newly token factored chain should not refer to 2477 // the old nodes. 2478 unsigned NumChains = MatcherTable[MatcherIndex++]; 2479 assert(NumChains != 0 && "Can't TF zero chains"); 2480 2481 assert(ChainNodesMatched.empty() && 2482 "Should only have one EmitMergeInputChains per match"); 2483 2484 // Read all of the chained nodes. 2485 for (unsigned i = 0; i != NumChains; ++i) { 2486 unsigned RecNo = MatcherTable[MatcherIndex++]; 2487 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2488 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2489 2490 // FIXME: What if other value results of the node have uses not matched 2491 // by this pattern? 2492 if (ChainNodesMatched.back() != NodeToMatch && 2493 !RecordedNodes[RecNo].hasOneUse()) { 2494 ChainNodesMatched.clear(); 2495 break; 2496 } 2497 } 2498 2499 // If the inner loop broke out, the match fails. 2500 if (ChainNodesMatched.empty()) 2501 break; 2502 2503 // Merge the input chains if they are not intra-pattern references. 2504 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2505 2506 if (InputChain.getNode() == 0) 2507 break; // Failed to merge. 2508 2509 continue; 2510 } 2511 2512 case OPC_EmitCopyToReg: { 2513 unsigned RecNo = MatcherTable[MatcherIndex++]; 2514 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2515 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2516 2517 if (InputChain.getNode() == 0) 2518 InputChain = CurDAG->getEntryNode(); 2519 2520 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2521 DestPhysReg, RecordedNodes[RecNo], 2522 InputFlag); 2523 2524 InputFlag = InputChain.getValue(1); 2525 continue; 2526 } 2527 2528 case OPC_EmitNodeXForm: { 2529 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2530 unsigned RecNo = MatcherTable[MatcherIndex++]; 2531 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2532 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2533 continue; 2534 } 2535 2536 case OPC_EmitNode: 2537 case OPC_MorphNodeTo: { 2538 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2539 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2540 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2541 // Get the result VT list. 2542 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2543 SmallVector<EVT, 4> VTs; 2544 for (unsigned i = 0; i != NumVTs; ++i) { 2545 MVT::SimpleValueType VT = 2546 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2547 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2548 VTs.push_back(VT); 2549 } 2550 2551 if (EmitNodeInfo & OPFL_Chain) 2552 VTs.push_back(MVT::Other); 2553 if (EmitNodeInfo & OPFL_FlagOutput) 2554 VTs.push_back(MVT::Flag); 2555 2556 // This is hot code, so optimize the two most common cases of 1 and 2 2557 // results. 2558 SDVTList VTList; 2559 if (VTs.size() == 1) 2560 VTList = CurDAG->getVTList(VTs[0]); 2561 else if (VTs.size() == 2) 2562 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2563 else 2564 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2565 2566 // Get the operand list. 2567 unsigned NumOps = MatcherTable[MatcherIndex++]; 2568 SmallVector<SDValue, 8> Ops; 2569 for (unsigned i = 0; i != NumOps; ++i) { 2570 unsigned RecNo = MatcherTable[MatcherIndex++]; 2571 if (RecNo & 128) 2572 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2573 2574 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2575 Ops.push_back(RecordedNodes[RecNo]); 2576 } 2577 2578 // If there are variadic operands to add, handle them now. 2579 if (EmitNodeInfo & OPFL_VariadicInfo) { 2580 // Determine the start index to copy from. 2581 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2582 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2583 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2584 "Invalid variadic node"); 2585 // Copy all of the variadic operands, not including a potential flag 2586 // input. 2587 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2588 i != e; ++i) { 2589 SDValue V = NodeToMatch->getOperand(i); 2590 if (V.getValueType() == MVT::Flag) break; 2591 Ops.push_back(V); 2592 } 2593 } 2594 2595 // If this has chain/flag inputs, add them. 2596 if (EmitNodeInfo & OPFL_Chain) 2597 Ops.push_back(InputChain); 2598 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2599 Ops.push_back(InputFlag); 2600 2601 // Create the node. 2602 SDNode *Res = 0; 2603 if (Opcode != OPC_MorphNodeTo) { 2604 // If this is a normal EmitNode command, just create the new node and 2605 // add the results to the RecordedNodes list. 2606 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2607 VTList, Ops.data(), Ops.size()); 2608 2609 // Add all the non-flag/non-chain results to the RecordedNodes list. 2610 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2611 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2612 RecordedNodes.push_back(SDValue(Res, i)); 2613 } 2614 2615 } else { 2616 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2617 EmitNodeInfo); 2618 } 2619 2620 // If the node had chain/flag results, update our notion of the current 2621 // chain and flag. 2622 if (EmitNodeInfo & OPFL_FlagOutput) { 2623 InputFlag = SDValue(Res, VTs.size()-1); 2624 if (EmitNodeInfo & OPFL_Chain) 2625 InputChain = SDValue(Res, VTs.size()-2); 2626 } else if (EmitNodeInfo & OPFL_Chain) 2627 InputChain = SDValue(Res, VTs.size()-1); 2628 2629 // If the OPFL_MemRefs flag is set on this node, slap all of the 2630 // accumulated memrefs onto it. 2631 // 2632 // FIXME: This is vastly incorrect for patterns with multiple outputs 2633 // instructions that access memory and for ComplexPatterns that match 2634 // loads. 2635 if (EmitNodeInfo & OPFL_MemRefs) { 2636 MachineSDNode::mmo_iterator MemRefs = 2637 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2638 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2639 cast<MachineSDNode>(Res) 2640 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2641 } 2642 2643 DEBUG(errs() << " " 2644 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2645 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2646 2647 // If this was a MorphNodeTo then we're completely done! 2648 if (Opcode == OPC_MorphNodeTo) { 2649 // Update chain and flag uses. 2650 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2651 InputFlag, FlagResultNodesMatched, true); 2652 return Res; 2653 } 2654 2655 continue; 2656 } 2657 2658 case OPC_MarkFlagResults: { 2659 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2660 2661 // Read and remember all the flag-result nodes. 2662 for (unsigned i = 0; i != NumNodes; ++i) { 2663 unsigned RecNo = MatcherTable[MatcherIndex++]; 2664 if (RecNo & 128) 2665 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2666 2667 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2668 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2669 } 2670 continue; 2671 } 2672 2673 case OPC_CompleteMatch: { 2674 // The match has been completed, and any new nodes (if any) have been 2675 // created. Patch up references to the matched dag to use the newly 2676 // created nodes. 2677 unsigned NumResults = MatcherTable[MatcherIndex++]; 2678 2679 for (unsigned i = 0; i != NumResults; ++i) { 2680 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2681 if (ResSlot & 128) 2682 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2683 2684 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2685 SDValue Res = RecordedNodes[ResSlot]; 2686 2687 assert(i < NodeToMatch->getNumValues() && 2688 NodeToMatch->getValueType(i) != MVT::Other && 2689 NodeToMatch->getValueType(i) != MVT::Flag && 2690 "Invalid number of results to complete!"); 2691 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2692 NodeToMatch->getValueType(i) == MVT::iPTR || 2693 Res.getValueType() == MVT::iPTR || 2694 NodeToMatch->getValueType(i).getSizeInBits() == 2695 Res.getValueType().getSizeInBits()) && 2696 "invalid replacement"); 2697 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2698 } 2699 2700 // If the root node defines a flag, add it to the flag nodes to update 2701 // list. 2702 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2703 FlagResultNodesMatched.push_back(NodeToMatch); 2704 2705 // Update chain and flag uses. 2706 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2707 InputFlag, FlagResultNodesMatched, false); 2708 2709 assert(NodeToMatch->use_empty() && 2710 "Didn't replace all uses of the node?"); 2711 2712 // FIXME: We just return here, which interacts correctly with SelectRoot 2713 // above. We should fix this to not return an SDNode* anymore. 2714 return 0; 2715 } 2716 } 2717 2718 // If the code reached this point, then the match failed. See if there is 2719 // another child to try in the current 'Scope', otherwise pop it until we 2720 // find a case to check. 2721 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2722 while (1) { 2723 if (MatchScopes.empty()) { 2724 CannotYetSelect(NodeToMatch); 2725 return 0; 2726 } 2727 2728 // Restore the interpreter state back to the point where the scope was 2729 // formed. 2730 MatchScope &LastScope = MatchScopes.back(); 2731 RecordedNodes.resize(LastScope.NumRecordedNodes); 2732 NodeStack.clear(); 2733 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2734 N = NodeStack.back(); 2735 2736 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2737 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2738 MatcherIndex = LastScope.FailIndex; 2739 2740 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2741 2742 InputChain = LastScope.InputChain; 2743 InputFlag = LastScope.InputFlag; 2744 if (!LastScope.HasChainNodesMatched) 2745 ChainNodesMatched.clear(); 2746 if (!LastScope.HasFlagResultNodesMatched) 2747 FlagResultNodesMatched.clear(); 2748 2749 // Check to see what the offset is at the new MatcherIndex. If it is zero 2750 // we have reached the end of this scope, otherwise we have another child 2751 // in the current scope to try. 2752 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2753 if (NumToSkip & 128) 2754 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2755 2756 // If we have another child in this scope to match, update FailIndex and 2757 // try it. 2758 if (NumToSkip != 0) { 2759 LastScope.FailIndex = MatcherIndex+NumToSkip; 2760 break; 2761 } 2762 2763 // End of this scope, pop it and try the next child in the containing 2764 // scope. 2765 MatchScopes.pop_back(); 2766 } 2767 } 2768} 2769 2770 2771 2772void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2773 std::string msg; 2774 raw_string_ostream Msg(msg); 2775 Msg << "Cannot yet select: "; 2776 2777 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2778 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2779 N->getOpcode() != ISD::INTRINSIC_VOID) { 2780 N->printrFull(Msg, CurDAG); 2781 } else { 2782 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2783 unsigned iid = 2784 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2785 if (iid < Intrinsic::num_intrinsics) 2786 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2787 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2788 Msg << "target intrinsic %" << TII->getName(iid); 2789 else 2790 Msg << "unknown intrinsic #" << iid; 2791 } 2792 llvm_report_error(Msg.str()); 2793} 2794 2795char SelectionDAGISel::ID = 0; 2796