SelectionDAGISel.cpp revision cbe762b5d165c565feb98b745e93b71d208a1e36
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322MachineBasicBlock * 323SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 324 const BasicBlock *LLVMBB, 325 BasicBlock::const_iterator Begin, 326 BasicBlock::const_iterator End, 327 bool &HadTailCall) { 328 // Lower all of the non-terminator instructions. If a call is emitted 329 // as a tail call, cease emitting nodes for this block. Terminators 330 // are handled below. 331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 332 SDB->visit(*I); 333 334 // Make sure the root of the DAG is up-to-date. 335 CurDAG->setRoot(SDB->getControlRoot()); 336 HadTailCall = SDB->HasTailCall; 337 SDB->clear(); 338 339 // Final step, emit the lowered DAG as machine code. 340 return CodeGenAndEmitDAG(BB); 341} 342 343namespace { 344/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 345/// nodes from the worklist. 346class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 347 SmallVector<SDNode*, 128> &Worklist; 348 SmallPtrSet<SDNode*, 128> &InWorklist; 349public: 350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 351 SmallPtrSet<SDNode*, 128> &inwl) 352 : Worklist(wl), InWorklist(inwl) {} 353 354 void RemoveFromWorklist(SDNode *N) { 355 if (!InWorklist.erase(N)) return; 356 357 SmallVector<SDNode*, 128>::iterator I = 358 std::find(Worklist.begin(), Worklist.end(), N); 359 assert(I != Worklist.end() && "Not in worklist"); 360 361 *I = Worklist.back(); 362 Worklist.pop_back(); 363 } 364 365 virtual void NodeDeleted(SDNode *N, SDNode *E) { 366 RemoveFromWorklist(N); 367 } 368 369 virtual void NodeUpdated(SDNode *N) { 370 // Ignore updates. 371 } 372}; 373} 374 375/// TrivialTruncElim - Eliminate some trivial nops that can result from 376/// ShrinkDemandedOps: (trunc (ext n)) -> n. 377static bool TrivialTruncElim(SDValue Op, 378 TargetLowering::TargetLoweringOpt &TLO) { 379 SDValue N0 = Op.getOperand(0); 380 EVT VT = Op.getValueType(); 381 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 382 N0.getOpcode() == ISD::SIGN_EXTEND || 383 N0.getOpcode() == ISD::ANY_EXTEND) && 384 N0.getOperand(0).getValueType() == VT) { 385 return TLO.CombineTo(Op, N0.getOperand(0)); 386 } 387 return false; 388} 389 390/// ShrinkDemandedOps - A late transformation pass that shrink expressions 391/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 392/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 393void SelectionDAGISel::ShrinkDemandedOps() { 394 SmallVector<SDNode*, 128> Worklist; 395 SmallPtrSet<SDNode*, 128> InWorklist; 396 397 // Add all the dag nodes to the worklist. 398 Worklist.reserve(CurDAG->allnodes_size()); 399 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 400 E = CurDAG->allnodes_end(); I != E; ++I) { 401 Worklist.push_back(I); 402 InWorklist.insert(I); 403 } 404 405 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 406 while (!Worklist.empty()) { 407 SDNode *N = Worklist.pop_back_val(); 408 InWorklist.erase(N); 409 410 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 411 // Deleting this node may make its operands dead, add them to the worklist 412 // if they aren't already there. 413 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 414 if (InWorklist.insert(N->getOperand(i).getNode())) 415 Worklist.push_back(N->getOperand(i).getNode()); 416 417 CurDAG->DeleteNode(N); 418 continue; 419 } 420 421 // Run ShrinkDemandedOp on scalar binary operations. 422 if (N->getNumValues() != 1 || 423 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 424 continue; 425 426 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 427 APInt Demanded = APInt::getAllOnesValue(BitWidth); 428 APInt KnownZero, KnownOne; 429 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 430 KnownZero, KnownOne, TLO) && 431 (N->getOpcode() != ISD::TRUNCATE || 432 !TrivialTruncElim(SDValue(N, 0), TLO))) 433 continue; 434 435 // Revisit the node. 436 assert(!InWorklist.count(N) && "Already in worklist"); 437 Worklist.push_back(N); 438 InWorklist.insert(N); 439 440 // Replace the old value with the new one. 441 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 442 TLO.Old.getNode()->dump(CurDAG); 443 errs() << "\nWith: "; 444 TLO.New.getNode()->dump(CurDAG); 445 errs() << '\n'); 446 447 if (InWorklist.insert(TLO.New.getNode())) 448 Worklist.push_back(TLO.New.getNode()); 449 450 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 451 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 452 453 if (!TLO.Old.getNode()->use_empty()) continue; 454 455 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 456 i != e; ++i) { 457 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 458 if (OpNode->hasOneUse()) { 459 // Add OpNode to the end of the list to revisit. 460 DeadNodes.RemoveFromWorklist(OpNode); 461 Worklist.push_back(OpNode); 462 InWorklist.insert(OpNode); 463 } 464 } 465 466 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 467 CurDAG->DeleteNode(TLO.Old.getNode()); 468 } 469} 470 471void SelectionDAGISel::ComputeLiveOutVRegInfo() { 472 SmallPtrSet<SDNode*, 128> VisitedNodes; 473 SmallVector<SDNode*, 128> Worklist; 474 475 Worklist.push_back(CurDAG->getRoot().getNode()); 476 477 APInt Mask; 478 APInt KnownZero; 479 APInt KnownOne; 480 481 do { 482 SDNode *N = Worklist.pop_back_val(); 483 484 // If we've already seen this node, ignore it. 485 if (!VisitedNodes.insert(N)) 486 continue; 487 488 // Otherwise, add all chain operands to the worklist. 489 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 490 if (N->getOperand(i).getValueType() == MVT::Other) 491 Worklist.push_back(N->getOperand(i).getNode()); 492 493 // If this is a CopyToReg with a vreg dest, process it. 494 if (N->getOpcode() != ISD::CopyToReg) 495 continue; 496 497 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 498 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 499 continue; 500 501 // Ignore non-scalar or non-integer values. 502 SDValue Src = N->getOperand(2); 503 EVT SrcVT = Src.getValueType(); 504 if (!SrcVT.isInteger() || SrcVT.isVector()) 505 continue; 506 507 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 508 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 509 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 510 511 // Only install this information if it tells us something. 512 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 513 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 514 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 515 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 516 FunctionLoweringInfo::LiveOutInfo &LOI = 517 FuncInfo->LiveOutRegInfo[DestReg]; 518 LOI.NumSignBits = NumSignBits; 519 LOI.KnownOne = KnownOne; 520 LOI.KnownZero = KnownZero; 521 } 522 } while (!Worklist.empty()); 523} 524 525MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 526 std::string GroupName; 527 if (TimePassesIsEnabled) 528 GroupName = "Instruction Selection and Scheduling"; 529 std::string BlockName; 530 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 531 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 532 ViewSUnitDAGs) 533 BlockName = MF->getFunction()->getNameStr() + ":" + 534 BB->getBasicBlock()->getNameStr(); 535 536 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 537 538 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 539 540 // Run the DAG combiner in pre-legalize mode. 541 { 542 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 543 CurDAG->Combine(Unrestricted, *AA, OptLevel); 544 } 545 546 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 547 548 // Second step, hack on the DAG until it only uses operations and types that 549 // the target supports. 550 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 551 BlockName); 552 553 bool Changed; 554 { 555 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 556 Changed = CurDAG->LegalizeTypes(); 557 } 558 559 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 560 561 if (Changed) { 562 if (ViewDAGCombineLT) 563 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 564 565 // Run the DAG combiner in post-type-legalize mode. 566 { 567 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 568 TimePassesIsEnabled); 569 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 570 } 571 572 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 573 CurDAG->dump()); 574 } 575 576 { 577 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 578 Changed = CurDAG->LegalizeVectors(); 579 } 580 581 if (Changed) { 582 { 583 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 584 CurDAG->LegalizeTypes(); 585 } 586 587 if (ViewDAGCombineLT) 588 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 589 590 // Run the DAG combiner in post-type-legalize mode. 591 { 592 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 593 TimePassesIsEnabled); 594 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 595 } 596 597 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 598 CurDAG->dump()); 599 } 600 601 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 602 603 { 604 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 605 CurDAG->Legalize(OptLevel); 606 } 607 608 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 609 610 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 611 612 // Run the DAG combiner in post-legalize mode. 613 { 614 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 615 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 616 } 617 618 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 619 620 if (OptLevel != CodeGenOpt::None) { 621 ShrinkDemandedOps(); 622 ComputeLiveOutVRegInfo(); 623 } 624 625 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 626 627 // Third, instruction select all of the operations to machine code, adding the 628 // code to the MachineBasicBlock. 629 { 630 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 631 DoInstructionSelection(); 632 } 633 634 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 635 636 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 637 638 // Schedule machine code. 639 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 640 { 641 NamedRegionTimer T("Instruction Scheduling", GroupName, 642 TimePassesIsEnabled); 643 Scheduler->Run(CurDAG, BB, BB->end()); 644 } 645 646 if (ViewSUnitDAGs) Scheduler->viewGraph(); 647 648 // Emit machine code to BB. This can change 'BB' to the last block being 649 // inserted into. 650 { 651 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 652 BB = Scheduler->EmitSchedule(); 653 } 654 655 // Free the scheduler state. 656 { 657 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 658 TimePassesIsEnabled); 659 delete Scheduler; 660 } 661 662 // Free the SelectionDAG state, now that we're finished with it. 663 CurDAG->clear(); 664 665 return BB; 666} 667 668void SelectionDAGISel::DoInstructionSelection() { 669 DEBUG(errs() << "===== Instruction selection begins:\n"); 670 671 PreprocessISelDAG(); 672 673 // Select target instructions for the DAG. 674 { 675 // Number all nodes with a topological order and set DAGSize. 676 DAGSize = CurDAG->AssignTopologicalOrder(); 677 678 // Create a dummy node (which is not added to allnodes), that adds 679 // a reference to the root node, preventing it from being deleted, 680 // and tracking any changes of the root. 681 HandleSDNode Dummy(CurDAG->getRoot()); 682 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 683 ++ISelPosition; 684 685 // The AllNodes list is now topological-sorted. Visit the 686 // nodes by starting at the end of the list (the root of the 687 // graph) and preceding back toward the beginning (the entry 688 // node). 689 while (ISelPosition != CurDAG->allnodes_begin()) { 690 SDNode *Node = --ISelPosition; 691 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 692 // but there are currently some corner cases that it misses. Also, this 693 // makes it theoretically possible to disable the DAGCombiner. 694 if (Node->use_empty()) 695 continue; 696 697 SDNode *ResNode = Select(Node); 698 699 // FIXME: This is pretty gross. 'Select' should be changed to not return 700 // anything at all and this code should be nuked with a tactical strike. 701 702 // If node should not be replaced, continue with the next one. 703 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 704 continue; 705 // Replace node. 706 if (ResNode) 707 ReplaceUses(Node, ResNode); 708 709 // If after the replacement this node is not used any more, 710 // remove this dead node. 711 if (Node->use_empty()) { // Don't delete EntryToken, etc. 712 ISelUpdater ISU(ISelPosition); 713 CurDAG->RemoveDeadNode(Node, &ISU); 714 } 715 } 716 717 CurDAG->setRoot(Dummy.getValue()); 718 } 719 720 DEBUG(errs() << "===== Instruction selection ends:\n"); 721 722 PostprocessISelDAG(); 723} 724 725/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 726/// do other setup for EH landing-pad blocks. 727void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 728 // Add a label to mark the beginning of the landing pad. Deletion of the 729 // landing pad can thus be detected via the MachineModuleInfo. 730 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 731 732 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 733 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 734 735 // Mark exception register as live in. 736 unsigned Reg = TLI.getExceptionAddressRegister(); 737 if (Reg) BB->addLiveIn(Reg); 738 739 // Mark exception selector register as live in. 740 Reg = TLI.getExceptionSelectorRegister(); 741 if (Reg) BB->addLiveIn(Reg); 742 743 // FIXME: Hack around an exception handling flaw (PR1508): the personality 744 // function and list of typeids logically belong to the invoke (or, if you 745 // like, the basic block containing the invoke), and need to be associated 746 // with it in the dwarf exception handling tables. Currently however the 747 // information is provided by an intrinsic (eh.selector) that can be moved 748 // to unexpected places by the optimizers: if the unwind edge is critical, 749 // then breaking it can result in the intrinsics being in the successor of 750 // the landing pad, not the landing pad itself. This results 751 // in exceptions not being caught because no typeids are associated with 752 // the invoke. This may not be the only way things can go wrong, but it 753 // is the only way we try to work around for the moment. 754 const BasicBlock *LLVMBB = BB->getBasicBlock(); 755 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 756 757 if (Br && Br->isUnconditional()) { // Critical edge? 758 BasicBlock::const_iterator I, E; 759 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 760 if (isa<EHSelectorInst>(I)) 761 break; 762 763 if (I == E) 764 // No catch info found - try to extract some from the successor. 765 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 766 } 767} 768 769void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 770 // Initialize the Fast-ISel state, if needed. 771 FastISel *FastIS = 0; 772 if (EnableFastISel) 773 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 774 FuncInfo->StaticAllocaMap, 775 FuncInfo->PHINodesToUpdate 776#ifndef NDEBUG 777 , FuncInfo->CatchInfoLost 778#endif 779 ); 780 781 // Iterate over all basic blocks in the function. 782 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 783 const BasicBlock *LLVMBB = &*I; 784 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 785 786 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 787 BasicBlock::const_iterator const End = LLVMBB->end(); 788 BasicBlock::const_iterator BI = Begin; 789 790 // Lower any arguments needed in this block if this is the entry block. 791 if (LLVMBB == &Fn.getEntryBlock()) 792 LowerArguments(LLVMBB); 793 794 // Setup an EH landing-pad block. 795 if (BB->isLandingPad()) 796 PrepareEHLandingPad(BB); 797 798 // Before doing SelectionDAG ISel, see if FastISel has been requested. 799 if (FastIS) { 800 // Emit code for any incoming arguments. This must happen before 801 // beginning FastISel on the entry block. 802 if (LLVMBB == &Fn.getEntryBlock()) { 803 CurDAG->setRoot(SDB->getControlRoot()); 804 SDB->clear(); 805 BB = CodeGenAndEmitDAG(BB); 806 } 807 FastIS->startNewBlock(BB); 808 // Do FastISel on as many instructions as possible. 809 for (; BI != End; ++BI) { 810 // Try to select the instruction with FastISel. 811 if (FastIS->SelectInstruction(BI)) 812 continue; 813 814 // Then handle certain instructions as single-LLVM-Instruction blocks. 815 if (isa<CallInst>(BI)) { 816 ++NumFastIselFailures; 817 if (EnableFastISelVerbose || EnableFastISelAbort) { 818 dbgs() << "FastISel missed call: "; 819 BI->dump(); 820 } 821 822 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 823 unsigned &R = FuncInfo->ValueMap[BI]; 824 if (!R) 825 R = FuncInfo->CreateRegForValue(BI); 826 } 827 828 bool HadTailCall = false; 829 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 830 831 // If the call was emitted as a tail call, we're done with the block. 832 if (HadTailCall) { 833 BI = End; 834 break; 835 } 836 837 // If the instruction was codegen'd with multiple blocks, 838 // inform the FastISel object where to resume inserting. 839 FastIS->setCurrentBlock(BB); 840 continue; 841 } 842 843 // Otherwise, give up on FastISel for the rest of the block. 844 // For now, be a little lenient about non-branch terminators. 845 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 846 ++NumFastIselFailures; 847 if (EnableFastISelVerbose || EnableFastISelAbort) { 848 dbgs() << "FastISel miss: "; 849 BI->dump(); 850 } 851 if (EnableFastISelAbort) 852 // The "fast" selector couldn't handle something and bailed. 853 // For the purpose of debugging, just abort. 854 llvm_unreachable("FastISel didn't select the entire block"); 855 } 856 break; 857 } 858 } 859 860 // Run SelectionDAG instruction selection on the remainder of the block 861 // not handled by FastISel. If FastISel is not run, this is the entire 862 // block. 863 if (BI != End) { 864 bool HadTailCall; 865 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 866 } 867 868 FinishBasicBlock(BB); 869 FuncInfo->PHINodesToUpdate.clear(); 870 } 871 872 delete FastIS; 873} 874 875void 876SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 877 878 DEBUG(dbgs() << "Total amount of phi nodes to update: " 879 << FuncInfo->PHINodesToUpdate.size() << "\n"; 880 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 881 dbgs() << "Node " << i << " : (" 882 << FuncInfo->PHINodesToUpdate[i].first 883 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 884 885 // Next, now that we know what the last MBB the LLVM BB expanded is, update 886 // PHI nodes in successors. 887 if (SDB->SwitchCases.empty() && 888 SDB->JTCases.empty() && 889 SDB->BitTestCases.empty()) { 890 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 891 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 892 assert(PHI->isPHI() && 893 "This is not a machine PHI node that we are updating!"); 894 if (!BB->isSuccessor(PHI->getParent())) 895 continue; 896 PHI->addOperand( 897 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 898 PHI->addOperand(MachineOperand::CreateMBB(BB)); 899 } 900 return; 901 } 902 903 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 904 // Lower header first, if it wasn't already lowered 905 if (!SDB->BitTestCases[i].Emitted) { 906 // Set the current basic block to the mbb we wish to insert the code into 907 BB = SDB->BitTestCases[i].Parent; 908 // Emit the code 909 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 910 CurDAG->setRoot(SDB->getRoot()); 911 SDB->clear(); 912 BB = CodeGenAndEmitDAG(BB); 913 } 914 915 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 916 // Set the current basic block to the mbb we wish to insert the code into 917 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 918 // Emit the code 919 if (j+1 != ej) 920 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 921 SDB->BitTestCases[i].Reg, 922 SDB->BitTestCases[i].Cases[j], 923 BB); 924 else 925 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 926 SDB->BitTestCases[i].Reg, 927 SDB->BitTestCases[i].Cases[j], 928 BB); 929 930 931 CurDAG->setRoot(SDB->getRoot()); 932 SDB->clear(); 933 BB = CodeGenAndEmitDAG(BB); 934 } 935 936 // Update PHI Nodes 937 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 938 pi != pe; ++pi) { 939 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 940 MachineBasicBlock *PHIBB = PHI->getParent(); 941 assert(PHI->isPHI() && 942 "This is not a machine PHI node that we are updating!"); 943 // This is "default" BB. We have two jumps to it. From "header" BB and 944 // from last "case" BB. 945 if (PHIBB == SDB->BitTestCases[i].Default) { 946 PHI->addOperand(MachineOperand:: 947 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 948 false)); 949 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 950 PHI->addOperand(MachineOperand:: 951 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 952 false)); 953 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 954 back().ThisBB)); 955 } 956 // One of "cases" BB. 957 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 958 j != ej; ++j) { 959 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 960 if (cBB->isSuccessor(PHIBB)) { 961 PHI->addOperand(MachineOperand:: 962 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 963 false)); 964 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 965 } 966 } 967 } 968 } 969 SDB->BitTestCases.clear(); 970 971 // If the JumpTable record is filled in, then we need to emit a jump table. 972 // Updating the PHI nodes is tricky in this case, since we need to determine 973 // whether the PHI is a successor of the range check MBB or the jump table MBB 974 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 975 // Lower header first, if it wasn't already lowered 976 if (!SDB->JTCases[i].first.Emitted) { 977 // Set the current basic block to the mbb we wish to insert the code into 978 BB = SDB->JTCases[i].first.HeaderBB; 979 // Emit the code 980 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 981 BB); 982 CurDAG->setRoot(SDB->getRoot()); 983 SDB->clear(); 984 BB = CodeGenAndEmitDAG(BB); 985 } 986 987 // Set the current basic block to the mbb we wish to insert the code into 988 BB = SDB->JTCases[i].second.MBB; 989 // Emit the code 990 SDB->visitJumpTable(SDB->JTCases[i].second); 991 CurDAG->setRoot(SDB->getRoot()); 992 SDB->clear(); 993 BB = CodeGenAndEmitDAG(BB); 994 995 // Update PHI Nodes 996 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 997 pi != pe; ++pi) { 998 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 999 MachineBasicBlock *PHIBB = PHI->getParent(); 1000 assert(PHI->isPHI() && 1001 "This is not a machine PHI node that we are updating!"); 1002 // "default" BB. We can go there only from header BB. 1003 if (PHIBB == SDB->JTCases[i].second.Default) { 1004 PHI->addOperand 1005 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1006 false)); 1007 PHI->addOperand 1008 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1009 } 1010 // JT BB. Just iterate over successors here 1011 if (BB->isSuccessor(PHIBB)) { 1012 PHI->addOperand 1013 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1014 false)); 1015 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1016 } 1017 } 1018 } 1019 SDB->JTCases.clear(); 1020 1021 // If the switch block involved a branch to one of the actual successors, we 1022 // need to update PHI nodes in that block. 1023 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1024 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1025 assert(PHI->isPHI() && 1026 "This is not a machine PHI node that we are updating!"); 1027 if (BB->isSuccessor(PHI->getParent())) { 1028 PHI->addOperand( 1029 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1030 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1031 } 1032 } 1033 1034 // If we generated any switch lowering information, build and codegen any 1035 // additional DAGs necessary. 1036 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1037 // Set the current basic block to the mbb we wish to insert the code into 1038 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1039 1040 // Determine the unique successors. 1041 SmallVector<MachineBasicBlock *, 2> Succs; 1042 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1043 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1044 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1045 1046 // Emit the code. Note that this could result in ThisBB being split, so 1047 // we need to check for updates. 1048 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1049 CurDAG->setRoot(SDB->getRoot()); 1050 SDB->clear(); 1051 ThisBB = CodeGenAndEmitDAG(BB); 1052 1053 // Handle any PHI nodes in successors of this chunk, as if we were coming 1054 // from the original BB before switch expansion. Note that PHI nodes can 1055 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1056 // handle them the right number of times. 1057 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1058 BB = Succs[i]; 1059 // BB may have been removed from the CFG if a branch was constant folded. 1060 if (ThisBB->isSuccessor(BB)) { 1061 for (MachineBasicBlock::iterator Phi = BB->begin(); 1062 Phi != BB->end() && Phi->isPHI(); 1063 ++Phi) { 1064 // This value for this PHI node is recorded in PHINodesToUpdate. 1065 for (unsigned pn = 0; ; ++pn) { 1066 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1067 "Didn't find PHI entry!"); 1068 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1069 Phi->addOperand(MachineOperand:: 1070 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1071 false)); 1072 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1073 break; 1074 } 1075 } 1076 } 1077 } 1078 } 1079 } 1080 SDB->SwitchCases.clear(); 1081} 1082 1083 1084/// Create the scheduler. If a specific scheduler was specified 1085/// via the SchedulerRegistry, use it, otherwise select the 1086/// one preferred by the target. 1087/// 1088ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1089 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1090 1091 if (!Ctor) { 1092 Ctor = ISHeuristic; 1093 RegisterScheduler::setDefault(Ctor); 1094 } 1095 1096 return Ctor(this, OptLevel); 1097} 1098 1099ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1100 return new ScheduleHazardRecognizer(); 1101} 1102 1103//===----------------------------------------------------------------------===// 1104// Helper functions used by the generated instruction selector. 1105//===----------------------------------------------------------------------===// 1106// Calls to these methods are generated by tblgen. 1107 1108/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1109/// the dag combiner simplified the 255, we still want to match. RHS is the 1110/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1111/// specified in the .td file (e.g. 255). 1112bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1113 int64_t DesiredMaskS) const { 1114 const APInt &ActualMask = RHS->getAPIntValue(); 1115 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1116 1117 // If the actual mask exactly matches, success! 1118 if (ActualMask == DesiredMask) 1119 return true; 1120 1121 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1122 if (ActualMask.intersects(~DesiredMask)) 1123 return false; 1124 1125 // Otherwise, the DAG Combiner may have proven that the value coming in is 1126 // either already zero or is not demanded. Check for known zero input bits. 1127 APInt NeededMask = DesiredMask & ~ActualMask; 1128 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1129 return true; 1130 1131 // TODO: check to see if missing bits are just not demanded. 1132 1133 // Otherwise, this pattern doesn't match. 1134 return false; 1135} 1136 1137/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1138/// the dag combiner simplified the 255, we still want to match. RHS is the 1139/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1140/// specified in the .td file (e.g. 255). 1141bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1142 int64_t DesiredMaskS) const { 1143 const APInt &ActualMask = RHS->getAPIntValue(); 1144 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1145 1146 // If the actual mask exactly matches, success! 1147 if (ActualMask == DesiredMask) 1148 return true; 1149 1150 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1151 if (ActualMask.intersects(~DesiredMask)) 1152 return false; 1153 1154 // Otherwise, the DAG Combiner may have proven that the value coming in is 1155 // either already zero or is not demanded. Check for known zero input bits. 1156 APInt NeededMask = DesiredMask & ~ActualMask; 1157 1158 APInt KnownZero, KnownOne; 1159 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1160 1161 // If all the missing bits in the or are already known to be set, match! 1162 if ((NeededMask & KnownOne) == NeededMask) 1163 return true; 1164 1165 // TODO: check to see if missing bits are just not demanded. 1166 1167 // Otherwise, this pattern doesn't match. 1168 return false; 1169} 1170 1171 1172/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1173/// by tblgen. Others should not call it. 1174void SelectionDAGISel:: 1175SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1176 std::vector<SDValue> InOps; 1177 std::swap(InOps, Ops); 1178 1179 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1180 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1181 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1182 1183 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1184 if (InOps[e-1].getValueType() == MVT::Flag) 1185 --e; // Don't process a flag operand if it is here. 1186 1187 while (i != e) { 1188 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1189 if (!InlineAsm::isMemKind(Flags)) { 1190 // Just skip over this operand, copying the operands verbatim. 1191 Ops.insert(Ops.end(), InOps.begin()+i, 1192 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1193 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1194 } else { 1195 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1196 "Memory operand with multiple values?"); 1197 // Otherwise, this is a memory operand. Ask the target to select it. 1198 std::vector<SDValue> SelOps; 1199 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1200 report_fatal_error("Could not match memory address. Inline asm" 1201 " failure!"); 1202 1203 // Add this to the output node. 1204 unsigned NewFlags = 1205 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1206 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1207 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1208 i += 2; 1209 } 1210 } 1211 1212 // Add the flag input back if present. 1213 if (e != InOps.size()) 1214 Ops.push_back(InOps.back()); 1215} 1216 1217/// findFlagUse - Return use of EVT::Flag value produced by the specified 1218/// SDNode. 1219/// 1220static SDNode *findFlagUse(SDNode *N) { 1221 unsigned FlagResNo = N->getNumValues()-1; 1222 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1223 SDUse &Use = I.getUse(); 1224 if (Use.getResNo() == FlagResNo) 1225 return Use.getUser(); 1226 } 1227 return NULL; 1228} 1229 1230/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1231/// This function recursively traverses up the operand chain, ignoring 1232/// certain nodes. 1233static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1234 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1235 bool IgnoreChains) { 1236 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1237 // greater than all of its (recursive) operands. If we scan to a point where 1238 // 'use' is smaller than the node we're scanning for, then we know we will 1239 // never find it. 1240 // 1241 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1242 // happen because we scan down to newly selected nodes in the case of flag 1243 // uses. 1244 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1245 return false; 1246 1247 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1248 // won't fail if we scan it again. 1249 if (!Visited.insert(Use)) 1250 return false; 1251 1252 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1253 // Ignore chain uses, they are validated by HandleMergeInputChains. 1254 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1255 continue; 1256 1257 SDNode *N = Use->getOperand(i).getNode(); 1258 if (N == Def) { 1259 if (Use == ImmedUse || Use == Root) 1260 continue; // We are not looking for immediate use. 1261 assert(N != Root); 1262 return true; 1263 } 1264 1265 // Traverse up the operand chain. 1266 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1267 return true; 1268 } 1269 return false; 1270} 1271 1272/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1273/// operand node N of U during instruction selection that starts at Root. 1274bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1275 SDNode *Root) const { 1276 if (OptLevel == CodeGenOpt::None) return false; 1277 return N.hasOneUse(); 1278} 1279 1280/// IsLegalToFold - Returns true if the specific operand node N of 1281/// U can be folded during instruction selection that starts at Root. 1282bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1283 CodeGenOpt::Level OptLevel, 1284 bool IgnoreChains) { 1285 if (OptLevel == CodeGenOpt::None) return false; 1286 1287 // If Root use can somehow reach N through a path that that doesn't contain 1288 // U then folding N would create a cycle. e.g. In the following 1289 // diagram, Root can reach N through X. If N is folded into into Root, then 1290 // X is both a predecessor and a successor of U. 1291 // 1292 // [N*] // 1293 // ^ ^ // 1294 // / \ // 1295 // [U*] [X]? // 1296 // ^ ^ // 1297 // \ / // 1298 // \ / // 1299 // [Root*] // 1300 // 1301 // * indicates nodes to be folded together. 1302 // 1303 // If Root produces a flag, then it gets (even more) interesting. Since it 1304 // will be "glued" together with its flag use in the scheduler, we need to 1305 // check if it might reach N. 1306 // 1307 // [N*] // 1308 // ^ ^ // 1309 // / \ // 1310 // [U*] [X]? // 1311 // ^ ^ // 1312 // \ \ // 1313 // \ | // 1314 // [Root*] | // 1315 // ^ | // 1316 // f | // 1317 // | / // 1318 // [Y] / // 1319 // ^ / // 1320 // f / // 1321 // | / // 1322 // [FU] // 1323 // 1324 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1325 // (call it Fold), then X is a predecessor of FU and a successor of 1326 // Fold. But since Fold and FU are flagged together, this will create 1327 // a cycle in the scheduling graph. 1328 1329 // If the node has flags, walk down the graph to the "lowest" node in the 1330 // flagged set. 1331 EVT VT = Root->getValueType(Root->getNumValues()-1); 1332 while (VT == MVT::Flag) { 1333 SDNode *FU = findFlagUse(Root); 1334 if (FU == NULL) 1335 break; 1336 Root = FU; 1337 VT = Root->getValueType(Root->getNumValues()-1); 1338 1339 // If our query node has a flag result with a use, we've walked up it. If 1340 // the user (which has already been selected) has a chain or indirectly uses 1341 // the chain, our WalkChainUsers predicate will not consider it. Because of 1342 // this, we cannot ignore chains in this predicate. 1343 IgnoreChains = false; 1344 } 1345 1346 1347 SmallPtrSet<SDNode*, 16> Visited; 1348 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1349} 1350 1351SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1352 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1353 SelectInlineAsmMemoryOperands(Ops); 1354 1355 std::vector<EVT> VTs; 1356 VTs.push_back(MVT::Other); 1357 VTs.push_back(MVT::Flag); 1358 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1359 VTs, &Ops[0], Ops.size()); 1360 New->setNodeId(-1); 1361 return New.getNode(); 1362} 1363 1364SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1365 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1366} 1367 1368/// GetVBR - decode a vbr encoding whose top bit is set. 1369ALWAYS_INLINE static uint64_t 1370GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1371 assert(Val >= 128 && "Not a VBR"); 1372 Val &= 127; // Remove first vbr bit. 1373 1374 unsigned Shift = 7; 1375 uint64_t NextBits; 1376 do { 1377 NextBits = MatcherTable[Idx++]; 1378 Val |= (NextBits&127) << Shift; 1379 Shift += 7; 1380 } while (NextBits & 128); 1381 1382 return Val; 1383} 1384 1385 1386/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1387/// interior flag and chain results to use the new flag and chain results. 1388void SelectionDAGISel:: 1389UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1390 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1391 SDValue InputFlag, 1392 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1393 bool isMorphNodeTo) { 1394 SmallVector<SDNode*, 4> NowDeadNodes; 1395 1396 ISelUpdater ISU(ISelPosition); 1397 1398 // Now that all the normal results are replaced, we replace the chain and 1399 // flag results if present. 1400 if (!ChainNodesMatched.empty()) { 1401 assert(InputChain.getNode() != 0 && 1402 "Matched input chains but didn't produce a chain"); 1403 // Loop over all of the nodes we matched that produced a chain result. 1404 // Replace all the chain results with the final chain we ended up with. 1405 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1406 SDNode *ChainNode = ChainNodesMatched[i]; 1407 1408 // If this node was already deleted, don't look at it. 1409 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1410 continue; 1411 1412 // Don't replace the results of the root node if we're doing a 1413 // MorphNodeTo. 1414 if (ChainNode == NodeToMatch && isMorphNodeTo) 1415 continue; 1416 1417 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1418 if (ChainVal.getValueType() == MVT::Flag) 1419 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1420 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1421 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1422 1423 // If the node became dead and we haven't already seen it, delete it. 1424 if (ChainNode->use_empty() && 1425 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1426 NowDeadNodes.push_back(ChainNode); 1427 } 1428 } 1429 1430 // If the result produces a flag, update any flag results in the matched 1431 // pattern with the flag result. 1432 if (InputFlag.getNode() != 0) { 1433 // Handle any interior nodes explicitly marked. 1434 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1435 SDNode *FRN = FlagResultNodesMatched[i]; 1436 1437 // If this node was already deleted, don't look at it. 1438 if (FRN->getOpcode() == ISD::DELETED_NODE) 1439 continue; 1440 1441 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1442 "Doesn't have a flag result"); 1443 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1444 InputFlag, &ISU); 1445 1446 // If the node became dead and we haven't already seen it, delete it. 1447 if (FRN->use_empty() && 1448 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1449 NowDeadNodes.push_back(FRN); 1450 } 1451 } 1452 1453 if (!NowDeadNodes.empty()) 1454 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1455 1456 DEBUG(errs() << "ISEL: Match complete!\n"); 1457} 1458 1459enum ChainResult { 1460 CR_Simple, 1461 CR_InducesCycle, 1462 CR_LeadsToInteriorNode 1463}; 1464 1465/// WalkChainUsers - Walk down the users of the specified chained node that is 1466/// part of the pattern we're matching, looking at all of the users we find. 1467/// This determines whether something is an interior node, whether we have a 1468/// non-pattern node in between two pattern nodes (which prevent folding because 1469/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1470/// between pattern nodes (in which case the TF becomes part of the pattern). 1471/// 1472/// The walk we do here is guaranteed to be small because we quickly get down to 1473/// already selected nodes "below" us. 1474static ChainResult 1475WalkChainUsers(SDNode *ChainedNode, 1476 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1477 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1478 ChainResult Result = CR_Simple; 1479 1480 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1481 E = ChainedNode->use_end(); UI != E; ++UI) { 1482 // Make sure the use is of the chain, not some other value we produce. 1483 if (UI.getUse().getValueType() != MVT::Other) continue; 1484 1485 SDNode *User = *UI; 1486 1487 // If we see an already-selected machine node, then we've gone beyond the 1488 // pattern that we're selecting down into the already selected chunk of the 1489 // DAG. 1490 if (User->isMachineOpcode() || 1491 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1492 continue; 1493 1494 if (User->getOpcode() == ISD::CopyToReg || 1495 User->getOpcode() == ISD::CopyFromReg || 1496 User->getOpcode() == ISD::INLINEASM || 1497 User->getOpcode() == ISD::EH_LABEL) { 1498 // If their node ID got reset to -1 then they've already been selected. 1499 // Treat them like a MachineOpcode. 1500 if (User->getNodeId() == -1) 1501 continue; 1502 } 1503 1504 // If we have a TokenFactor, we handle it specially. 1505 if (User->getOpcode() != ISD::TokenFactor) { 1506 // If the node isn't a token factor and isn't part of our pattern, then it 1507 // must be a random chained node in between two nodes we're selecting. 1508 // This happens when we have something like: 1509 // x = load ptr 1510 // call 1511 // y = x+4 1512 // store y -> ptr 1513 // Because we structurally match the load/store as a read/modify/write, 1514 // but the call is chained between them. We cannot fold in this case 1515 // because it would induce a cycle in the graph. 1516 if (!std::count(ChainedNodesInPattern.begin(), 1517 ChainedNodesInPattern.end(), User)) 1518 return CR_InducesCycle; 1519 1520 // Otherwise we found a node that is part of our pattern. For example in: 1521 // x = load ptr 1522 // y = x+4 1523 // store y -> ptr 1524 // This would happen when we're scanning down from the load and see the 1525 // store as a user. Record that there is a use of ChainedNode that is 1526 // part of the pattern and keep scanning uses. 1527 Result = CR_LeadsToInteriorNode; 1528 InteriorChainedNodes.push_back(User); 1529 continue; 1530 } 1531 1532 // If we found a TokenFactor, there are two cases to consider: first if the 1533 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1534 // uses of the TF are in our pattern) we just want to ignore it. Second, 1535 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1536 // [Load chain] 1537 // ^ 1538 // | 1539 // [Load] 1540 // ^ ^ 1541 // | \ DAG's like cheese 1542 // / \ do you? 1543 // / | 1544 // [TokenFactor] [Op] 1545 // ^ ^ 1546 // | | 1547 // \ / 1548 // \ / 1549 // [Store] 1550 // 1551 // In this case, the TokenFactor becomes part of our match and we rewrite it 1552 // as a new TokenFactor. 1553 // 1554 // To distinguish these two cases, do a recursive walk down the uses. 1555 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1556 case CR_Simple: 1557 // If the uses of the TokenFactor are just already-selected nodes, ignore 1558 // it, it is "below" our pattern. 1559 continue; 1560 case CR_InducesCycle: 1561 // If the uses of the TokenFactor lead to nodes that are not part of our 1562 // pattern that are not selected, folding would turn this into a cycle, 1563 // bail out now. 1564 return CR_InducesCycle; 1565 case CR_LeadsToInteriorNode: 1566 break; // Otherwise, keep processing. 1567 } 1568 1569 // Okay, we know we're in the interesting interior case. The TokenFactor 1570 // is now going to be considered part of the pattern so that we rewrite its 1571 // uses (it may have uses that are not part of the pattern) with the 1572 // ultimate chain result of the generated code. We will also add its chain 1573 // inputs as inputs to the ultimate TokenFactor we create. 1574 Result = CR_LeadsToInteriorNode; 1575 ChainedNodesInPattern.push_back(User); 1576 InteriorChainedNodes.push_back(User); 1577 continue; 1578 } 1579 1580 return Result; 1581} 1582 1583/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1584/// operation for when the pattern matched at least one node with a chains. The 1585/// input vector contains a list of all of the chained nodes that we match. We 1586/// must determine if this is a valid thing to cover (i.e. matching it won't 1587/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1588/// be used as the input node chain for the generated nodes. 1589static SDValue 1590HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1591 SelectionDAG *CurDAG) { 1592 // Walk all of the chained nodes we've matched, recursively scanning down the 1593 // users of the chain result. This adds any TokenFactor nodes that are caught 1594 // in between chained nodes to the chained and interior nodes list. 1595 SmallVector<SDNode*, 3> InteriorChainedNodes; 1596 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1597 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1598 InteriorChainedNodes) == CR_InducesCycle) 1599 return SDValue(); // Would induce a cycle. 1600 } 1601 1602 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1603 // that we are interested in. Form our input TokenFactor node. 1604 SmallVector<SDValue, 3> InputChains; 1605 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1606 // Add the input chain of this node to the InputChains list (which will be 1607 // the operands of the generated TokenFactor) if it's not an interior node. 1608 SDNode *N = ChainNodesMatched[i]; 1609 if (N->getOpcode() != ISD::TokenFactor) { 1610 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1611 continue; 1612 1613 // Otherwise, add the input chain. 1614 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1615 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1616 InputChains.push_back(InChain); 1617 continue; 1618 } 1619 1620 // If we have a token factor, we want to add all inputs of the token factor 1621 // that are not part of the pattern we're matching. 1622 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1623 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1624 N->getOperand(op).getNode())) 1625 InputChains.push_back(N->getOperand(op)); 1626 } 1627 } 1628 1629 SDValue Res; 1630 if (InputChains.size() == 1) 1631 return InputChains[0]; 1632 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1633 MVT::Other, &InputChains[0], InputChains.size()); 1634} 1635 1636/// MorphNode - Handle morphing a node in place for the selector. 1637SDNode *SelectionDAGISel:: 1638MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1639 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1640 // It is possible we're using MorphNodeTo to replace a node with no 1641 // normal results with one that has a normal result (or we could be 1642 // adding a chain) and the input could have flags and chains as well. 1643 // In this case we need to shift the operands down. 1644 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1645 // than the old isel though. 1646 int OldFlagResultNo = -1, OldChainResultNo = -1; 1647 1648 unsigned NTMNumResults = Node->getNumValues(); 1649 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1650 OldFlagResultNo = NTMNumResults-1; 1651 if (NTMNumResults != 1 && 1652 Node->getValueType(NTMNumResults-2) == MVT::Other) 1653 OldChainResultNo = NTMNumResults-2; 1654 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1655 OldChainResultNo = NTMNumResults-1; 1656 1657 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1658 // that this deletes operands of the old node that become dead. 1659 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1660 1661 // MorphNodeTo can operate in two ways: if an existing node with the 1662 // specified operands exists, it can just return it. Otherwise, it 1663 // updates the node in place to have the requested operands. 1664 if (Res == Node) { 1665 // If we updated the node in place, reset the node ID. To the isel, 1666 // this should be just like a newly allocated machine node. 1667 Res->setNodeId(-1); 1668 } 1669 1670 unsigned ResNumResults = Res->getNumValues(); 1671 // Move the flag if needed. 1672 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1673 (unsigned)OldFlagResultNo != ResNumResults-1) 1674 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1675 SDValue(Res, ResNumResults-1)); 1676 1677 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1678 --ResNumResults; 1679 1680 // Move the chain reference if needed. 1681 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1682 (unsigned)OldChainResultNo != ResNumResults-1) 1683 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1684 SDValue(Res, ResNumResults-1)); 1685 1686 // Otherwise, no replacement happened because the node already exists. Replace 1687 // Uses of the old node with the new one. 1688 if (Res != Node) 1689 CurDAG->ReplaceAllUsesWith(Node, Res); 1690 1691 return Res; 1692} 1693 1694/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1695ALWAYS_INLINE static bool 1696CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1697 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1698 // Accept if it is exactly the same as a previously recorded node. 1699 unsigned RecNo = MatcherTable[MatcherIndex++]; 1700 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1701 return N == RecordedNodes[RecNo]; 1702} 1703 1704/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1705ALWAYS_INLINE static bool 1706CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1707 SelectionDAGISel &SDISel) { 1708 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1709} 1710 1711/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1712ALWAYS_INLINE static bool 1713CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1714 SelectionDAGISel &SDISel, SDNode *N) { 1715 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1716} 1717 1718ALWAYS_INLINE static bool 1719CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1720 SDNode *N) { 1721 uint16_t Opc = MatcherTable[MatcherIndex++]; 1722 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1723 return N->getOpcode() == Opc; 1724} 1725 1726ALWAYS_INLINE static bool 1727CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1728 SDValue N, const TargetLowering &TLI) { 1729 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1730 if (N.getValueType() == VT) return true; 1731 1732 // Handle the case when VT is iPTR. 1733 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1734} 1735 1736ALWAYS_INLINE static bool 1737CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1738 SDValue N, const TargetLowering &TLI, 1739 unsigned ChildNo) { 1740 if (ChildNo >= N.getNumOperands()) 1741 return false; // Match fails if out of range child #. 1742 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1743} 1744 1745 1746ALWAYS_INLINE static bool 1747CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1748 SDValue N) { 1749 return cast<CondCodeSDNode>(N)->get() == 1750 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1751} 1752 1753ALWAYS_INLINE static bool 1754CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1755 SDValue N, const TargetLowering &TLI) { 1756 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1757 if (cast<VTSDNode>(N)->getVT() == VT) 1758 return true; 1759 1760 // Handle the case when VT is iPTR. 1761 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1762} 1763 1764ALWAYS_INLINE static bool 1765CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1766 SDValue N) { 1767 int64_t Val = MatcherTable[MatcherIndex++]; 1768 if (Val & 128) 1769 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1770 1771 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1772 return C != 0 && C->getSExtValue() == Val; 1773} 1774 1775ALWAYS_INLINE static bool 1776CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1777 SDValue N, SelectionDAGISel &SDISel) { 1778 int64_t Val = MatcherTable[MatcherIndex++]; 1779 if (Val & 128) 1780 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1781 1782 if (N->getOpcode() != ISD::AND) return false; 1783 1784 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1785 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1786} 1787 1788ALWAYS_INLINE static bool 1789CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1790 SDValue N, SelectionDAGISel &SDISel) { 1791 int64_t Val = MatcherTable[MatcherIndex++]; 1792 if (Val & 128) 1793 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1794 1795 if (N->getOpcode() != ISD::OR) return false; 1796 1797 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1798 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1799} 1800 1801/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1802/// scope, evaluate the current node. If the current predicate is known to 1803/// fail, set Result=true and return anything. If the current predicate is 1804/// known to pass, set Result=false and return the MatcherIndex to continue 1805/// with. If the current predicate is unknown, set Result=false and return the 1806/// MatcherIndex to continue with. 1807static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1808 unsigned Index, SDValue N, 1809 bool &Result, SelectionDAGISel &SDISel, 1810 SmallVectorImpl<SDValue> &RecordedNodes){ 1811 switch (Table[Index++]) { 1812 default: 1813 Result = false; 1814 return Index-1; // Could not evaluate this predicate. 1815 case SelectionDAGISel::OPC_CheckSame: 1816 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1817 return Index; 1818 case SelectionDAGISel::OPC_CheckPatternPredicate: 1819 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1820 return Index; 1821 case SelectionDAGISel::OPC_CheckPredicate: 1822 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1823 return Index; 1824 case SelectionDAGISel::OPC_CheckOpcode: 1825 Result = !::CheckOpcode(Table, Index, N.getNode()); 1826 return Index; 1827 case SelectionDAGISel::OPC_CheckType: 1828 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1829 return Index; 1830 case SelectionDAGISel::OPC_CheckChild0Type: 1831 case SelectionDAGISel::OPC_CheckChild1Type: 1832 case SelectionDAGISel::OPC_CheckChild2Type: 1833 case SelectionDAGISel::OPC_CheckChild3Type: 1834 case SelectionDAGISel::OPC_CheckChild4Type: 1835 case SelectionDAGISel::OPC_CheckChild5Type: 1836 case SelectionDAGISel::OPC_CheckChild6Type: 1837 case SelectionDAGISel::OPC_CheckChild7Type: 1838 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1839 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1840 return Index; 1841 case SelectionDAGISel::OPC_CheckCondCode: 1842 Result = !::CheckCondCode(Table, Index, N); 1843 return Index; 1844 case SelectionDAGISel::OPC_CheckValueType: 1845 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1846 return Index; 1847 case SelectionDAGISel::OPC_CheckInteger: 1848 Result = !::CheckInteger(Table, Index, N); 1849 return Index; 1850 case SelectionDAGISel::OPC_CheckAndImm: 1851 Result = !::CheckAndImm(Table, Index, N, SDISel); 1852 return Index; 1853 case SelectionDAGISel::OPC_CheckOrImm: 1854 Result = !::CheckOrImm(Table, Index, N, SDISel); 1855 return Index; 1856 } 1857} 1858 1859namespace { 1860 1861struct MatchScope { 1862 /// FailIndex - If this match fails, this is the index to continue with. 1863 unsigned FailIndex; 1864 1865 /// NodeStack - The node stack when the scope was formed. 1866 SmallVector<SDValue, 4> NodeStack; 1867 1868 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1869 unsigned NumRecordedNodes; 1870 1871 /// NumMatchedMemRefs - The number of matched memref entries. 1872 unsigned NumMatchedMemRefs; 1873 1874 /// InputChain/InputFlag - The current chain/flag 1875 SDValue InputChain, InputFlag; 1876 1877 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1878 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1879}; 1880 1881} 1882 1883SDNode *SelectionDAGISel:: 1884SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1885 unsigned TableSize) { 1886 // FIXME: Should these even be selected? Handle these cases in the caller? 1887 switch (NodeToMatch->getOpcode()) { 1888 default: 1889 break; 1890 case ISD::EntryToken: // These nodes remain the same. 1891 case ISD::BasicBlock: 1892 case ISD::Register: 1893 //case ISD::VALUETYPE: 1894 //case ISD::CONDCODE: 1895 case ISD::HANDLENODE: 1896 case ISD::MDNODE_SDNODE: 1897 case ISD::TargetConstant: 1898 case ISD::TargetConstantFP: 1899 case ISD::TargetConstantPool: 1900 case ISD::TargetFrameIndex: 1901 case ISD::TargetExternalSymbol: 1902 case ISD::TargetBlockAddress: 1903 case ISD::TargetJumpTable: 1904 case ISD::TargetGlobalTLSAddress: 1905 case ISD::TargetGlobalAddress: 1906 case ISD::TokenFactor: 1907 case ISD::CopyFromReg: 1908 case ISD::CopyToReg: 1909 case ISD::EH_LABEL: 1910 NodeToMatch->setNodeId(-1); // Mark selected. 1911 return 0; 1912 case ISD::AssertSext: 1913 case ISD::AssertZext: 1914 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1915 NodeToMatch->getOperand(0)); 1916 return 0; 1917 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1918 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1919 } 1920 1921 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1922 1923 // Set up the node stack with NodeToMatch as the only node on the stack. 1924 SmallVector<SDValue, 8> NodeStack; 1925 SDValue N = SDValue(NodeToMatch, 0); 1926 NodeStack.push_back(N); 1927 1928 // MatchScopes - Scopes used when matching, if a match failure happens, this 1929 // indicates where to continue checking. 1930 SmallVector<MatchScope, 8> MatchScopes; 1931 1932 // RecordedNodes - This is the set of nodes that have been recorded by the 1933 // state machine. 1934 SmallVector<SDValue, 8> RecordedNodes; 1935 1936 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1937 // pattern. 1938 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1939 1940 // These are the current input chain and flag for use when generating nodes. 1941 // Various Emit operations change these. For example, emitting a copytoreg 1942 // uses and updates these. 1943 SDValue InputChain, InputFlag; 1944 1945 // ChainNodesMatched - If a pattern matches nodes that have input/output 1946 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1947 // which ones they are. The result is captured into this list so that we can 1948 // update the chain results when the pattern is complete. 1949 SmallVector<SDNode*, 3> ChainNodesMatched; 1950 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1951 1952 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1953 NodeToMatch->dump(CurDAG); 1954 errs() << '\n'); 1955 1956 // Determine where to start the interpreter. Normally we start at opcode #0, 1957 // but if the state machine starts with an OPC_SwitchOpcode, then we 1958 // accelerate the first lookup (which is guaranteed to be hot) with the 1959 // OpcodeOffset table. 1960 unsigned MatcherIndex = 0; 1961 1962 if (!OpcodeOffset.empty()) { 1963 // Already computed the OpcodeOffset table, just index into it. 1964 if (N.getOpcode() < OpcodeOffset.size()) 1965 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1966 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1967 1968 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1969 // Otherwise, the table isn't computed, but the state machine does start 1970 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1971 // is the first time we're selecting an instruction. 1972 unsigned Idx = 1; 1973 while (1) { 1974 // Get the size of this case. 1975 unsigned CaseSize = MatcherTable[Idx++]; 1976 if (CaseSize & 128) 1977 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1978 if (CaseSize == 0) break; 1979 1980 // Get the opcode, add the index to the table. 1981 uint16_t Opc = MatcherTable[Idx++]; 1982 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1983 if (Opc >= OpcodeOffset.size()) 1984 OpcodeOffset.resize((Opc+1)*2); 1985 OpcodeOffset[Opc] = Idx; 1986 Idx += CaseSize; 1987 } 1988 1989 // Okay, do the lookup for the first opcode. 1990 if (N.getOpcode() < OpcodeOffset.size()) 1991 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1992 } 1993 1994 while (1) { 1995 assert(MatcherIndex < TableSize && "Invalid index"); 1996#ifndef NDEBUG 1997 unsigned CurrentOpcodeIndex = MatcherIndex; 1998#endif 1999 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2000 switch (Opcode) { 2001 case OPC_Scope: { 2002 // Okay, the semantics of this operation are that we should push a scope 2003 // then evaluate the first child. However, pushing a scope only to have 2004 // the first check fail (which then pops it) is inefficient. If we can 2005 // determine immediately that the first check (or first several) will 2006 // immediately fail, don't even bother pushing a scope for them. 2007 unsigned FailIndex; 2008 2009 while (1) { 2010 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2011 if (NumToSkip & 128) 2012 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2013 // Found the end of the scope with no match. 2014 if (NumToSkip == 0) { 2015 FailIndex = 0; 2016 break; 2017 } 2018 2019 FailIndex = MatcherIndex+NumToSkip; 2020 2021 unsigned MatcherIndexOfPredicate = MatcherIndex; 2022 (void)MatcherIndexOfPredicate; // silence warning. 2023 2024 // If we can't evaluate this predicate without pushing a scope (e.g. if 2025 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2026 // push the scope and evaluate the full predicate chain. 2027 bool Result; 2028 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2029 Result, *this, RecordedNodes); 2030 if (!Result) 2031 break; 2032 2033 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2034 << "index " << MatcherIndexOfPredicate 2035 << ", continuing at " << FailIndex << "\n"); 2036 ++NumDAGIselRetries; 2037 2038 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2039 // move to the next case. 2040 MatcherIndex = FailIndex; 2041 } 2042 2043 // If the whole scope failed to match, bail. 2044 if (FailIndex == 0) break; 2045 2046 // Push a MatchScope which indicates where to go if the first child fails 2047 // to match. 2048 MatchScope NewEntry; 2049 NewEntry.FailIndex = FailIndex; 2050 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2051 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2052 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2053 NewEntry.InputChain = InputChain; 2054 NewEntry.InputFlag = InputFlag; 2055 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2056 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2057 MatchScopes.push_back(NewEntry); 2058 continue; 2059 } 2060 case OPC_RecordNode: 2061 // Remember this node, it may end up being an operand in the pattern. 2062 RecordedNodes.push_back(N); 2063 continue; 2064 2065 case OPC_RecordChild0: case OPC_RecordChild1: 2066 case OPC_RecordChild2: case OPC_RecordChild3: 2067 case OPC_RecordChild4: case OPC_RecordChild5: 2068 case OPC_RecordChild6: case OPC_RecordChild7: { 2069 unsigned ChildNo = Opcode-OPC_RecordChild0; 2070 if (ChildNo >= N.getNumOperands()) 2071 break; // Match fails if out of range child #. 2072 2073 RecordedNodes.push_back(N->getOperand(ChildNo)); 2074 continue; 2075 } 2076 case OPC_RecordMemRef: 2077 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2078 continue; 2079 2080 case OPC_CaptureFlagInput: 2081 // If the current node has an input flag, capture it in InputFlag. 2082 if (N->getNumOperands() != 0 && 2083 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2084 InputFlag = N->getOperand(N->getNumOperands()-1); 2085 continue; 2086 2087 case OPC_MoveChild: { 2088 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2089 if (ChildNo >= N.getNumOperands()) 2090 break; // Match fails if out of range child #. 2091 N = N.getOperand(ChildNo); 2092 NodeStack.push_back(N); 2093 continue; 2094 } 2095 2096 case OPC_MoveParent: 2097 // Pop the current node off the NodeStack. 2098 NodeStack.pop_back(); 2099 assert(!NodeStack.empty() && "Node stack imbalance!"); 2100 N = NodeStack.back(); 2101 continue; 2102 2103 case OPC_CheckSame: 2104 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2105 continue; 2106 case OPC_CheckPatternPredicate: 2107 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2108 continue; 2109 case OPC_CheckPredicate: 2110 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2111 N.getNode())) 2112 break; 2113 continue; 2114 case OPC_CheckComplexPat: { 2115 unsigned CPNum = MatcherTable[MatcherIndex++]; 2116 unsigned RecNo = MatcherTable[MatcherIndex++]; 2117 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2118 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2119 RecordedNodes)) 2120 break; 2121 continue; 2122 } 2123 case OPC_CheckOpcode: 2124 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2125 continue; 2126 2127 case OPC_CheckType: 2128 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2129 continue; 2130 2131 case OPC_SwitchOpcode: { 2132 unsigned CurNodeOpcode = N.getOpcode(); 2133 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2134 unsigned CaseSize; 2135 while (1) { 2136 // Get the size of this case. 2137 CaseSize = MatcherTable[MatcherIndex++]; 2138 if (CaseSize & 128) 2139 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2140 if (CaseSize == 0) break; 2141 2142 uint16_t Opc = MatcherTable[MatcherIndex++]; 2143 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2144 2145 // If the opcode matches, then we will execute this case. 2146 if (CurNodeOpcode == Opc) 2147 break; 2148 2149 // Otherwise, skip over this case. 2150 MatcherIndex += CaseSize; 2151 } 2152 2153 // If no cases matched, bail out. 2154 if (CaseSize == 0) break; 2155 2156 // Otherwise, execute the case we found. 2157 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2158 << " to " << MatcherIndex << "\n"); 2159 continue; 2160 } 2161 2162 case OPC_SwitchType: { 2163 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2164 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2165 unsigned CaseSize; 2166 while (1) { 2167 // Get the size of this case. 2168 CaseSize = MatcherTable[MatcherIndex++]; 2169 if (CaseSize & 128) 2170 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2171 if (CaseSize == 0) break; 2172 2173 MVT::SimpleValueType CaseVT = 2174 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2175 if (CaseVT == MVT::iPTR) 2176 CaseVT = TLI.getPointerTy().SimpleTy; 2177 2178 // If the VT matches, then we will execute this case. 2179 if (CurNodeVT == CaseVT) 2180 break; 2181 2182 // Otherwise, skip over this case. 2183 MatcherIndex += CaseSize; 2184 } 2185 2186 // If no cases matched, bail out. 2187 if (CaseSize == 0) break; 2188 2189 // Otherwise, execute the case we found. 2190 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2191 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2192 continue; 2193 } 2194 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2195 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2196 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2197 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2198 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2199 Opcode-OPC_CheckChild0Type)) 2200 break; 2201 continue; 2202 case OPC_CheckCondCode: 2203 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2204 continue; 2205 case OPC_CheckValueType: 2206 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2207 continue; 2208 case OPC_CheckInteger: 2209 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2210 continue; 2211 case OPC_CheckAndImm: 2212 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2213 continue; 2214 case OPC_CheckOrImm: 2215 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2216 continue; 2217 2218 case OPC_CheckFoldableChainNode: { 2219 assert(NodeStack.size() != 1 && "No parent node"); 2220 // Verify that all intermediate nodes between the root and this one have 2221 // a single use. 2222 bool HasMultipleUses = false; 2223 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2224 if (!NodeStack[i].hasOneUse()) { 2225 HasMultipleUses = true; 2226 break; 2227 } 2228 if (HasMultipleUses) break; 2229 2230 // Check to see that the target thinks this is profitable to fold and that 2231 // we can fold it without inducing cycles in the graph. 2232 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2233 NodeToMatch) || 2234 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2235 NodeToMatch, OptLevel, 2236 true/*We validate our own chains*/)) 2237 break; 2238 2239 continue; 2240 } 2241 case OPC_EmitInteger: { 2242 MVT::SimpleValueType VT = 2243 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2244 int64_t Val = MatcherTable[MatcherIndex++]; 2245 if (Val & 128) 2246 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2247 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2248 continue; 2249 } 2250 case OPC_EmitRegister: { 2251 MVT::SimpleValueType VT = 2252 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2253 unsigned RegNo = MatcherTable[MatcherIndex++]; 2254 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2255 continue; 2256 } 2257 2258 case OPC_EmitConvertToTarget: { 2259 // Convert from IMM/FPIMM to target version. 2260 unsigned RecNo = MatcherTable[MatcherIndex++]; 2261 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2262 SDValue Imm = RecordedNodes[RecNo]; 2263 2264 if (Imm->getOpcode() == ISD::Constant) { 2265 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2266 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2267 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2268 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2269 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2270 } 2271 2272 RecordedNodes.push_back(Imm); 2273 continue; 2274 } 2275 2276 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2277 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2278 // These are space-optimized forms of OPC_EmitMergeInputChains. 2279 assert(InputChain.getNode() == 0 && 2280 "EmitMergeInputChains should be the first chain producing node"); 2281 assert(ChainNodesMatched.empty() && 2282 "Should only have one EmitMergeInputChains per match"); 2283 2284 // Read all of the chained nodes. 2285 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2286 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2287 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2288 2289 // FIXME: What if other value results of the node have uses not matched 2290 // by this pattern? 2291 if (ChainNodesMatched.back() != NodeToMatch && 2292 !RecordedNodes[RecNo].hasOneUse()) { 2293 ChainNodesMatched.clear(); 2294 break; 2295 } 2296 2297 // Merge the input chains if they are not intra-pattern references. 2298 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2299 2300 if (InputChain.getNode() == 0) 2301 break; // Failed to merge. 2302 continue; 2303 } 2304 2305 case OPC_EmitMergeInputChains: { 2306 assert(InputChain.getNode() == 0 && 2307 "EmitMergeInputChains should be the first chain producing node"); 2308 // This node gets a list of nodes we matched in the input that have 2309 // chains. We want to token factor all of the input chains to these nodes 2310 // together. However, if any of the input chains is actually one of the 2311 // nodes matched in this pattern, then we have an intra-match reference. 2312 // Ignore these because the newly token factored chain should not refer to 2313 // the old nodes. 2314 unsigned NumChains = MatcherTable[MatcherIndex++]; 2315 assert(NumChains != 0 && "Can't TF zero chains"); 2316 2317 assert(ChainNodesMatched.empty() && 2318 "Should only have one EmitMergeInputChains per match"); 2319 2320 // Read all of the chained nodes. 2321 for (unsigned i = 0; i != NumChains; ++i) { 2322 unsigned RecNo = MatcherTable[MatcherIndex++]; 2323 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2324 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2325 2326 // FIXME: What if other value results of the node have uses not matched 2327 // by this pattern? 2328 if (ChainNodesMatched.back() != NodeToMatch && 2329 !RecordedNodes[RecNo].hasOneUse()) { 2330 ChainNodesMatched.clear(); 2331 break; 2332 } 2333 } 2334 2335 // If the inner loop broke out, the match fails. 2336 if (ChainNodesMatched.empty()) 2337 break; 2338 2339 // Merge the input chains if they are not intra-pattern references. 2340 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2341 2342 if (InputChain.getNode() == 0) 2343 break; // Failed to merge. 2344 2345 continue; 2346 } 2347 2348 case OPC_EmitCopyToReg: { 2349 unsigned RecNo = MatcherTable[MatcherIndex++]; 2350 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2351 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2352 2353 if (InputChain.getNode() == 0) 2354 InputChain = CurDAG->getEntryNode(); 2355 2356 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2357 DestPhysReg, RecordedNodes[RecNo], 2358 InputFlag); 2359 2360 InputFlag = InputChain.getValue(1); 2361 continue; 2362 } 2363 2364 case OPC_EmitNodeXForm: { 2365 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2366 unsigned RecNo = MatcherTable[MatcherIndex++]; 2367 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2368 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2369 continue; 2370 } 2371 2372 case OPC_EmitNode: 2373 case OPC_MorphNodeTo: { 2374 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2375 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2376 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2377 // Get the result VT list. 2378 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2379 SmallVector<EVT, 4> VTs; 2380 for (unsigned i = 0; i != NumVTs; ++i) { 2381 MVT::SimpleValueType VT = 2382 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2383 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2384 VTs.push_back(VT); 2385 } 2386 2387 if (EmitNodeInfo & OPFL_Chain) 2388 VTs.push_back(MVT::Other); 2389 if (EmitNodeInfo & OPFL_FlagOutput) 2390 VTs.push_back(MVT::Flag); 2391 2392 // This is hot code, so optimize the two most common cases of 1 and 2 2393 // results. 2394 SDVTList VTList; 2395 if (VTs.size() == 1) 2396 VTList = CurDAG->getVTList(VTs[0]); 2397 else if (VTs.size() == 2) 2398 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2399 else 2400 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2401 2402 // Get the operand list. 2403 unsigned NumOps = MatcherTable[MatcherIndex++]; 2404 SmallVector<SDValue, 8> Ops; 2405 for (unsigned i = 0; i != NumOps; ++i) { 2406 unsigned RecNo = MatcherTable[MatcherIndex++]; 2407 if (RecNo & 128) 2408 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2409 2410 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2411 Ops.push_back(RecordedNodes[RecNo]); 2412 } 2413 2414 // If there are variadic operands to add, handle them now. 2415 if (EmitNodeInfo & OPFL_VariadicInfo) { 2416 // Determine the start index to copy from. 2417 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2418 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2419 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2420 "Invalid variadic node"); 2421 // Copy all of the variadic operands, not including a potential flag 2422 // input. 2423 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2424 i != e; ++i) { 2425 SDValue V = NodeToMatch->getOperand(i); 2426 if (V.getValueType() == MVT::Flag) break; 2427 Ops.push_back(V); 2428 } 2429 } 2430 2431 // If this has chain/flag inputs, add them. 2432 if (EmitNodeInfo & OPFL_Chain) 2433 Ops.push_back(InputChain); 2434 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2435 Ops.push_back(InputFlag); 2436 2437 // Create the node. 2438 SDNode *Res = 0; 2439 if (Opcode != OPC_MorphNodeTo) { 2440 // If this is a normal EmitNode command, just create the new node and 2441 // add the results to the RecordedNodes list. 2442 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2443 VTList, Ops.data(), Ops.size()); 2444 2445 // Add all the non-flag/non-chain results to the RecordedNodes list. 2446 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2447 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2448 RecordedNodes.push_back(SDValue(Res, i)); 2449 } 2450 2451 } else { 2452 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2453 EmitNodeInfo); 2454 } 2455 2456 // If the node had chain/flag results, update our notion of the current 2457 // chain and flag. 2458 if (EmitNodeInfo & OPFL_FlagOutput) { 2459 InputFlag = SDValue(Res, VTs.size()-1); 2460 if (EmitNodeInfo & OPFL_Chain) 2461 InputChain = SDValue(Res, VTs.size()-2); 2462 } else if (EmitNodeInfo & OPFL_Chain) 2463 InputChain = SDValue(Res, VTs.size()-1); 2464 2465 // If the OPFL_MemRefs flag is set on this node, slap all of the 2466 // accumulated memrefs onto it. 2467 // 2468 // FIXME: This is vastly incorrect for patterns with multiple outputs 2469 // instructions that access memory and for ComplexPatterns that match 2470 // loads. 2471 if (EmitNodeInfo & OPFL_MemRefs) { 2472 MachineSDNode::mmo_iterator MemRefs = 2473 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2474 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2475 cast<MachineSDNode>(Res) 2476 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2477 } 2478 2479 DEBUG(errs() << " " 2480 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2481 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2482 2483 // If this was a MorphNodeTo then we're completely done! 2484 if (Opcode == OPC_MorphNodeTo) { 2485 // Update chain and flag uses. 2486 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2487 InputFlag, FlagResultNodesMatched, true); 2488 return Res; 2489 } 2490 2491 continue; 2492 } 2493 2494 case OPC_MarkFlagResults: { 2495 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2496 2497 // Read and remember all the flag-result nodes. 2498 for (unsigned i = 0; i != NumNodes; ++i) { 2499 unsigned RecNo = MatcherTable[MatcherIndex++]; 2500 if (RecNo & 128) 2501 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2502 2503 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2504 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2505 } 2506 continue; 2507 } 2508 2509 case OPC_CompleteMatch: { 2510 // The match has been completed, and any new nodes (if any) have been 2511 // created. Patch up references to the matched dag to use the newly 2512 // created nodes. 2513 unsigned NumResults = MatcherTable[MatcherIndex++]; 2514 2515 for (unsigned i = 0; i != NumResults; ++i) { 2516 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2517 if (ResSlot & 128) 2518 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2519 2520 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2521 SDValue Res = RecordedNodes[ResSlot]; 2522 2523 assert(i < NodeToMatch->getNumValues() && 2524 NodeToMatch->getValueType(i) != MVT::Other && 2525 NodeToMatch->getValueType(i) != MVT::Flag && 2526 "Invalid number of results to complete!"); 2527 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2528 NodeToMatch->getValueType(i) == MVT::iPTR || 2529 Res.getValueType() == MVT::iPTR || 2530 NodeToMatch->getValueType(i).getSizeInBits() == 2531 Res.getValueType().getSizeInBits()) && 2532 "invalid replacement"); 2533 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2534 } 2535 2536 // If the root node defines a flag, add it to the flag nodes to update 2537 // list. 2538 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2539 FlagResultNodesMatched.push_back(NodeToMatch); 2540 2541 // Update chain and flag uses. 2542 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2543 InputFlag, FlagResultNodesMatched, false); 2544 2545 assert(NodeToMatch->use_empty() && 2546 "Didn't replace all uses of the node?"); 2547 2548 // FIXME: We just return here, which interacts correctly with SelectRoot 2549 // above. We should fix this to not return an SDNode* anymore. 2550 return 0; 2551 } 2552 } 2553 2554 // If the code reached this point, then the match failed. See if there is 2555 // another child to try in the current 'Scope', otherwise pop it until we 2556 // find a case to check. 2557 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2558 ++NumDAGIselRetries; 2559 while (1) { 2560 if (MatchScopes.empty()) { 2561 CannotYetSelect(NodeToMatch); 2562 return 0; 2563 } 2564 2565 // Restore the interpreter state back to the point where the scope was 2566 // formed. 2567 MatchScope &LastScope = MatchScopes.back(); 2568 RecordedNodes.resize(LastScope.NumRecordedNodes); 2569 NodeStack.clear(); 2570 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2571 N = NodeStack.back(); 2572 2573 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2574 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2575 MatcherIndex = LastScope.FailIndex; 2576 2577 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2578 2579 InputChain = LastScope.InputChain; 2580 InputFlag = LastScope.InputFlag; 2581 if (!LastScope.HasChainNodesMatched) 2582 ChainNodesMatched.clear(); 2583 if (!LastScope.HasFlagResultNodesMatched) 2584 FlagResultNodesMatched.clear(); 2585 2586 // Check to see what the offset is at the new MatcherIndex. If it is zero 2587 // we have reached the end of this scope, otherwise we have another child 2588 // in the current scope to try. 2589 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2590 if (NumToSkip & 128) 2591 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2592 2593 // If we have another child in this scope to match, update FailIndex and 2594 // try it. 2595 if (NumToSkip != 0) { 2596 LastScope.FailIndex = MatcherIndex+NumToSkip; 2597 break; 2598 } 2599 2600 // End of this scope, pop it and try the next child in the containing 2601 // scope. 2602 MatchScopes.pop_back(); 2603 } 2604 } 2605} 2606 2607 2608 2609void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2610 std::string msg; 2611 raw_string_ostream Msg(msg); 2612 Msg << "Cannot yet select: "; 2613 2614 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2615 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2616 N->getOpcode() != ISD::INTRINSIC_VOID) { 2617 N->printrFull(Msg, CurDAG); 2618 } else { 2619 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2620 unsigned iid = 2621 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2622 if (iid < Intrinsic::num_intrinsics) 2623 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2624 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2625 Msg << "target intrinsic %" << TII->getName(iid); 2626 else 2627 Msg << "unknown intrinsic #" << iid; 2628 } 2629 report_fatal_error(Msg.str()); 2630} 2631 2632char SelectionDAGISel::ID = 0; 2633