SelectionDAGISel.cpp revision cf01f7a78c18224866595b4b493d03a3de305e1f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/ScheduleDAG.h" 39#include "llvm/CodeGen/SchedulerRegistry.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetData.h" 43#include "llvm/Target/TargetFrameInfo.h" 44#include "llvm/Target/TargetInstrInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/Timer.h" 52#include <algorithm> 53using namespace llvm; 54 55static cl::opt<bool> 56EnableValueProp("enable-value-prop", cl::Hidden); 57static cl::opt<bool> 58EnableLegalizeTypes("enable-legalize-types", cl::Hidden); 59static cl::opt<bool> 60EnableFastISel("fast-isel", cl::Hidden, 61 cl::desc("Enable the experimental \"fast\" instruction selector")); 62static cl::opt<bool> 63DisableFastISelAbort("fast-isel-no-abort", cl::Hidden, 64 cl::desc("Use the SelectionDAGISel when \"fast\" instruction " 65 "selection fails")); 66static cl::opt<bool> 67SchedLiveInCopies("schedule-livein-copies", 68 cl::desc("Schedule copies of livein registers"), 69 cl::init(false)); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before the first " 75 "dag combine pass")); 76static cl::opt<bool> 77ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 78 cl::desc("Pop up a window to show dags before legalize types")); 79static cl::opt<bool> 80ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize")); 82static cl::opt<bool> 83ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before the second " 85 "dag combine pass")); 86static cl::opt<bool> 87ViewISelDAGs("view-isel-dags", cl::Hidden, 88 cl::desc("Pop up a window to show isel dags as they are selected")); 89static cl::opt<bool> 90ViewSchedDAGs("view-sched-dags", cl::Hidden, 91 cl::desc("Pop up a window to show sched dags as they are processed")); 92static cl::opt<bool> 93ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 94 cl::desc("Pop up a window to show SUnit dags after they are processed")); 95#else 96static const bool ViewDAGCombine1 = false, 97 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 98 ViewDAGCombine2 = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", " Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 131 SelectionDAG *DAG, 132 MachineBasicBlock *BB, 133 bool Fast) { 134 TargetLowering &TLI = IS->getTargetLowering(); 135 136 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 137 return createTDListDAGScheduler(IS, DAG, BB, Fast); 138 } else { 139 assert(TLI.getSchedulingPreference() == 140 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 141 return createBURRListDAGScheduler(IS, DAG, BB, Fast); 142 } 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and the scheduler passes ownership of it to this method. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB) { 153 cerr << "If a target marks an instruction with " 154 << "'usesCustomDAGSchedInserter', it must implement " 155 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 156 abort(); 157 return 0; 158} 159 160/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 161/// physical register has only a single copy use, then coalesced the copy 162/// if possible. 163static void EmitLiveInCopy(MachineBasicBlock *MBB, 164 MachineBasicBlock::iterator &InsertPos, 165 unsigned VirtReg, unsigned PhysReg, 166 const TargetRegisterClass *RC, 167 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 168 const MachineRegisterInfo &MRI, 169 const TargetRegisterInfo &TRI, 170 const TargetInstrInfo &TII) { 171 unsigned NumUses = 0; 172 MachineInstr *UseMI = NULL; 173 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 174 UE = MRI.use_end(); UI != UE; ++UI) { 175 UseMI = &*UI; 176 if (++NumUses > 1) 177 break; 178 } 179 180 // If the number of uses is not one, or the use is not a move instruction, 181 // don't coalesce. Also, only coalesce away a virtual register to virtual 182 // register copy. 183 bool Coalesced = false; 184 unsigned SrcReg, DstReg; 185 if (NumUses == 1 && 186 TII.isMoveInstr(*UseMI, SrcReg, DstReg) && 187 TargetRegisterInfo::isVirtualRegister(DstReg)) { 188 VirtReg = DstReg; 189 Coalesced = true; 190 } 191 192 // Now find an ideal location to insert the copy. 193 MachineBasicBlock::iterator Pos = InsertPos; 194 while (Pos != MBB->begin()) { 195 MachineInstr *PrevMI = prior(Pos); 196 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 197 // copyRegToReg might emit multiple instructions to do a copy. 198 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 199 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 200 // This is what the BB looks like right now: 201 // r1024 = mov r0 202 // ... 203 // r1 = mov r1024 204 // 205 // We want to insert "r1025 = mov r1". Inserting this copy below the 206 // move to r1024 makes it impossible for that move to be coalesced. 207 // 208 // r1025 = mov r1 209 // r1024 = mov r0 210 // ... 211 // r1 = mov 1024 212 // r2 = mov 1025 213 break; // Woot! Found a good location. 214 --Pos; 215 } 216 217 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 218 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 219 if (Coalesced) { 220 if (&*InsertPos == UseMI) ++InsertPos; 221 MBB->erase(UseMI); 222 } 223} 224 225/// EmitLiveInCopies - If this is the first basic block in the function, 226/// and if it has live ins that need to be copied into vregs, emit the 227/// copies into the block. 228static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 229 const MachineRegisterInfo &MRI, 230 const TargetRegisterInfo &TRI, 231 const TargetInstrInfo &TII) { 232 if (SchedLiveInCopies) { 233 // Emit the copies at a heuristically-determined location in the block. 234 DenseMap<MachineInstr*, unsigned> CopyRegMap; 235 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 236 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 237 E = MRI.livein_end(); LI != E; ++LI) 238 if (LI->second) { 239 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 240 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 241 RC, CopyRegMap, MRI, TRI, TII); 242 } 243 } else { 244 // Emit the copies into the top of the block. 245 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 246 E = MRI.livein_end(); LI != E; ++LI) 247 if (LI->second) { 248 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 249 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 250 LI->second, LI->first, RC, RC); 251 } 252 } 253} 254 255//===----------------------------------------------------------------------===// 256// SelectionDAGISel code 257//===----------------------------------------------------------------------===// 258 259SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) : 260 FunctionPass(&ID), TLI(tli), 261 FuncInfo(new FunctionLoweringInfo(TLI)), 262 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 263 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)), 264 GFI(), 265 Fast(fast), 266 DAGSize(0) 267{} 268 269SelectionDAGISel::~SelectionDAGISel() { 270 delete SDL; 271 delete CurDAG; 272 delete FuncInfo; 273} 274 275unsigned SelectionDAGISel::MakeReg(MVT VT) { 276 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 277} 278 279void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 280 AU.addRequired<AliasAnalysis>(); 281 AU.addRequired<GCModuleInfo>(); 282 AU.setPreservesAll(); 283} 284 285bool SelectionDAGISel::runOnFunction(Function &Fn) { 286 // Get alias analysis for load/store combining. 287 AA = &getAnalysis<AliasAnalysis>(); 288 289 TargetMachine &TM = TLI.getTargetMachine(); 290 MachineFunction &MF = MachineFunction::construct(&Fn, TM); 291 const MachineRegisterInfo &MRI = MF.getRegInfo(); 292 const TargetInstrInfo &TII = *TM.getInstrInfo(); 293 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 294 295 if (MF.getFunction()->hasGC()) 296 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction()); 297 else 298 GFI = 0; 299 RegInfo = &MF.getRegInfo(); 300 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 301 302 FuncInfo->set(Fn, MF, EnableFastISel); 303 CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>()); 304 SDL->init(GFI, *AA); 305 306 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 307 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 308 // Mark landing pad. 309 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 310 311 SelectAllBasicBlocks(Fn, MF); 312 313 // If the first basic block in the function has live ins that need to be 314 // copied into vregs, emit the copies into the top of the block before 315 // emitting the code for the block. 316 EmitLiveInCopies(MF.begin(), MRI, TRI, TII); 317 318 // Add function live-ins to entry block live-in set. 319 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 320 E = RegInfo->livein_end(); I != E; ++I) 321 MF.begin()->addLiveIn(I->first); 322 323#ifndef NDEBUG 324 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 325 "Not all catch info was assigned to a landing pad!"); 326#endif 327 328 FuncInfo->clear(); 329 330 return true; 331} 332 333static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 334 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 335 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 336 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 337 // Apply the catch info to DestBB. 338 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 339#ifndef NDEBUG 340 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 341 FLI.CatchInfoFound.insert(EHSel); 342#endif 343 } 344} 345 346/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 347/// whether object offset >= 0. 348static bool 349IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) { 350 if (!isa<FrameIndexSDNode>(Op)) return false; 351 352 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 353 int FrameIdx = FrameIdxNode->getIndex(); 354 return MFI->isFixedObjectIndex(FrameIdx) && 355 MFI->getObjectOffset(FrameIdx) >= 0; 356} 357 358/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 359/// possibly be overwritten when lowering the outgoing arguments in a tail 360/// call. Currently the implementation of this call is very conservative and 361/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 362/// virtual registers would be overwritten by direct lowering. 363static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 364 MachineFrameInfo * MFI) { 365 RegisterSDNode * OpReg = NULL; 366 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 367 (Op.getOpcode()== ISD::CopyFromReg && 368 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 369 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 370 (Op.getOpcode() == ISD::LOAD && 371 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 372 (Op.getOpcode() == ISD::MERGE_VALUES && 373 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD && 374 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()). 375 getOperand(1)))) 376 return true; 377 return false; 378} 379 380/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 381/// DAG and fixes their tailcall attribute operand. 382static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 383 TargetLowering& TLI) { 384 SDNode * Ret = NULL; 385 SDValue Terminator = DAG.getRoot(); 386 387 // Find RET node. 388 if (Terminator.getOpcode() == ISD::RET) { 389 Ret = Terminator.getNode(); 390 } 391 392 // Fix tail call attribute of CALL nodes. 393 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 394 BI = DAG.allnodes_end(); BI != BE; ) { 395 --BI; 396 if (BI->getOpcode() == ISD::CALL) { 397 SDValue OpRet(Ret, 0); 398 SDValue OpCall(BI, 0); 399 bool isMarkedTailCall = 400 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 401 // If CALL node has tail call attribute set to true and the call is not 402 // eligible (no RET or the target rejects) the attribute is fixed to 403 // false. The TargetLowering::IsEligibleForTailCallOptimization function 404 // must correctly identify tail call optimizable calls. 405 if (!isMarkedTailCall) continue; 406 if (Ret==NULL || 407 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) { 408 // Not eligible. Mark CALL node as non tail call. 409 SmallVector<SDValue, 32> Ops; 410 unsigned idx=0; 411 for(SDNode::op_iterator I =OpCall.getNode()->op_begin(), 412 E = OpCall.getNode()->op_end(); I != E; I++, idx++) { 413 if (idx!=3) 414 Ops.push_back(*I); 415 else 416 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 417 } 418 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 419 } else { 420 // Look for tail call clobbered arguments. Emit a series of 421 // copyto/copyfrom virtual register nodes to protect them. 422 SmallVector<SDValue, 32> Ops; 423 SDValue Chain = OpCall.getOperand(0), InFlag; 424 unsigned idx=0; 425 for(SDNode::op_iterator I = OpCall.getNode()->op_begin(), 426 E = OpCall.getNode()->op_end(); I != E; I++, idx++) { 427 SDValue Arg = *I; 428 if (idx > 4 && (idx % 2)) { 429 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))-> 430 getArgFlags().isByVal(); 431 MachineFunction &MF = DAG.getMachineFunction(); 432 MachineFrameInfo *MFI = MF.getFrameInfo(); 433 if (!isByVal && 434 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 435 MVT VT = Arg.getValueType(); 436 unsigned VReg = MF.getRegInfo(). 437 createVirtualRegister(TLI.getRegClassFor(VT)); 438 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 439 InFlag = Chain.getValue(1); 440 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); 441 Chain = Arg.getValue(1); 442 InFlag = Arg.getValue(2); 443 } 444 } 445 Ops.push_back(Arg); 446 } 447 // Link in chain of CopyTo/CopyFromReg. 448 Ops[0] = Chain; 449 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 450 } 451 } 452 } 453} 454 455void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 456 BasicBlock::iterator Begin, 457 BasicBlock::iterator End) { 458 SDL->setCurrentBasicBlock(BB); 459 460 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo(); 461 462 if (MMI && BB->isLandingPad()) { 463 // Add a label to mark the beginning of the landing pad. Deletion of the 464 // landing pad can thus be detected via the MachineModuleInfo. 465 unsigned LabelID = MMI->addLandingPad(BB); 466 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL, 467 CurDAG->getEntryNode(), LabelID)); 468 469 // Mark exception register as live in. 470 unsigned Reg = TLI.getExceptionAddressRegister(); 471 if (Reg) BB->addLiveIn(Reg); 472 473 // Mark exception selector register as live in. 474 Reg = TLI.getExceptionSelectorRegister(); 475 if (Reg) BB->addLiveIn(Reg); 476 477 // FIXME: Hack around an exception handling flaw (PR1508): the personality 478 // function and list of typeids logically belong to the invoke (or, if you 479 // like, the basic block containing the invoke), and need to be associated 480 // with it in the dwarf exception handling tables. Currently however the 481 // information is provided by an intrinsic (eh.selector) that can be moved 482 // to unexpected places by the optimizers: if the unwind edge is critical, 483 // then breaking it can result in the intrinsics being in the successor of 484 // the landing pad, not the landing pad itself. This results in exceptions 485 // not being caught because no typeids are associated with the invoke. 486 // This may not be the only way things can go wrong, but it is the only way 487 // we try to work around for the moment. 488 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 489 490 if (Br && Br->isUnconditional()) { // Critical edge? 491 BasicBlock::iterator I, E; 492 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 493 if (isa<EHSelectorInst>(I)) 494 break; 495 496 if (I == E) 497 // No catch info found - try to extract some from the successor. 498 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 499 } 500 } 501 502 // Lower all of the non-terminator instructions. 503 for (BasicBlock::iterator I = Begin; I != End; ++I) 504 if (!isa<TerminatorInst>(I)) 505 SDL->visit(*I); 506 507 // Ensure that all instructions which are used outside of their defining 508 // blocks are available as virtual registers. Invoke is handled elsewhere. 509 for (BasicBlock::iterator I = Begin; I != End; ++I) 510 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 511 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I); 512 if (VMI != FuncInfo->ValueMap.end()) 513 SDL->CopyValueToVirtualRegister(I, VMI->second); 514 } 515 516 // Handle PHI nodes in successor blocks. 517 if (End == LLVMBB->end()) { 518 HandlePHINodesInSuccessorBlocks(LLVMBB); 519 520 // Lower the terminator after the copies are emitted. 521 SDL->visit(*LLVMBB->getTerminator()); 522 } 523 524 // Make sure the root of the DAG is up-to-date. 525 CurDAG->setRoot(SDL->getControlRoot()); 526 527 // Check whether calls in this block are real tail calls. Fix up CALL nodes 528 // with correct tailcall attribute so that the target can rely on the tailcall 529 // attribute indicating whether the call is really eligible for tail call 530 // optimization. 531 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI); 532 533 // Final step, emit the lowered DAG as machine code. 534 CodeGenAndEmitDAG(); 535 SDL->clear(); 536} 537 538void SelectionDAGISel::ComputeLiveOutVRegInfo() { 539 SmallPtrSet<SDNode*, 128> VisitedNodes; 540 SmallVector<SDNode*, 128> Worklist; 541 542 Worklist.push_back(CurDAG->getRoot().getNode()); 543 544 APInt Mask; 545 APInt KnownZero; 546 APInt KnownOne; 547 548 while (!Worklist.empty()) { 549 SDNode *N = Worklist.back(); 550 Worklist.pop_back(); 551 552 // If we've already seen this node, ignore it. 553 if (!VisitedNodes.insert(N)) 554 continue; 555 556 // Otherwise, add all chain operands to the worklist. 557 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 558 if (N->getOperand(i).getValueType() == MVT::Other) 559 Worklist.push_back(N->getOperand(i).getNode()); 560 561 // If this is a CopyToReg with a vreg dest, process it. 562 if (N->getOpcode() != ISD::CopyToReg) 563 continue; 564 565 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 566 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 567 continue; 568 569 // Ignore non-scalar or non-integer values. 570 SDValue Src = N->getOperand(2); 571 MVT SrcVT = Src.getValueType(); 572 if (!SrcVT.isInteger() || SrcVT.isVector()) 573 continue; 574 575 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 576 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 577 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 578 579 // Only install this information if it tells us something. 580 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 581 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 582 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo(); 583 if (DestReg >= FLI.LiveOutRegInfo.size()) 584 FLI.LiveOutRegInfo.resize(DestReg+1); 585 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 586 LOI.NumSignBits = NumSignBits; 587 LOI.KnownOne = NumSignBits; 588 LOI.KnownZero = NumSignBits; 589 } 590 } 591} 592 593void SelectionDAGISel::CodeGenAndEmitDAG() { 594 std::string GroupName; 595 if (TimePassesIsEnabled) 596 GroupName = "Instruction Selection and Scheduling"; 597 std::string BlockName; 598 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 599 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) 600 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' + 601 BB->getBasicBlock()->getName(); 602 603 DOUT << "Initial selection DAG:\n"; 604 DEBUG(CurDAG->dump()); 605 606 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 607 608 // Run the DAG combiner in pre-legalize mode. 609 if (TimePassesIsEnabled) { 610 NamedRegionTimer T("DAG Combining 1", GroupName); 611 CurDAG->Combine(false, *AA, Fast); 612 } else { 613 CurDAG->Combine(false, *AA, Fast); 614 } 615 616 DOUT << "Optimized lowered selection DAG:\n"; 617 DEBUG(CurDAG->dump()); 618 619 // Second step, hack on the DAG until it only uses operations and types that 620 // the target supports. 621 if (EnableLegalizeTypes) {// Enable this some day. 622 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 623 BlockName); 624 625 if (TimePassesIsEnabled) { 626 NamedRegionTimer T("Type Legalization", GroupName); 627 CurDAG->LegalizeTypes(); 628 } else { 629 CurDAG->LegalizeTypes(); 630 } 631 632 DOUT << "Type-legalized selection DAG:\n"; 633 DEBUG(CurDAG->dump()); 634 635 // TODO: enable a dag combine pass here. 636 } 637 638 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 639 640 if (TimePassesIsEnabled) { 641 NamedRegionTimer T("DAG Legalization", GroupName); 642 CurDAG->Legalize(); 643 } else { 644 CurDAG->Legalize(); 645 } 646 647 DOUT << "Legalized selection DAG:\n"; 648 DEBUG(CurDAG->dump()); 649 650 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 651 652 // Run the DAG combiner in post-legalize mode. 653 if (TimePassesIsEnabled) { 654 NamedRegionTimer T("DAG Combining 2", GroupName); 655 CurDAG->Combine(true, *AA, Fast); 656 } else { 657 CurDAG->Combine(true, *AA, Fast); 658 } 659 660 DOUT << "Optimized legalized selection DAG:\n"; 661 DEBUG(CurDAG->dump()); 662 663 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 664 665 if (!Fast && EnableValueProp) 666 ComputeLiveOutVRegInfo(); 667 668 // Third, instruction select all of the operations to machine code, adding the 669 // code to the MachineBasicBlock. 670 if (TimePassesIsEnabled) { 671 NamedRegionTimer T("Instruction Selection", GroupName); 672 InstructionSelect(); 673 } else { 674 InstructionSelect(); 675 } 676 677 DOUT << "Selected selection DAG:\n"; 678 DEBUG(CurDAG->dump()); 679 680 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 681 682 // Schedule machine code. 683 ScheduleDAG *Scheduler; 684 if (TimePassesIsEnabled) { 685 NamedRegionTimer T("Instruction Scheduling", GroupName); 686 Scheduler = Schedule(); 687 } else { 688 Scheduler = Schedule(); 689 } 690 691 if (ViewSUnitDAGs) Scheduler->viewGraph(); 692 693 // Emit machine code to BB. This can change 'BB' to the last block being 694 // inserted into. 695 if (TimePassesIsEnabled) { 696 NamedRegionTimer T("Instruction Creation", GroupName); 697 BB = Scheduler->EmitSchedule(); 698 } else { 699 BB = Scheduler->EmitSchedule(); 700 } 701 702 // Free the scheduler state. 703 if (TimePassesIsEnabled) { 704 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 705 delete Scheduler; 706 } else { 707 delete Scheduler; 708 } 709 710 DOUT << "Selected machine code:\n"; 711 DEBUG(BB->dump()); 712} 713 714void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) { 715 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 716 BasicBlock *LLVMBB = &*I; 717 BB = FuncInfo->MBBMap[LLVMBB]; 718 719 BasicBlock::iterator const Begin = LLVMBB->begin(); 720 BasicBlock::iterator const End = LLVMBB->end(); 721 BasicBlock::iterator BI = Begin; 722 723 // Lower any arguments needed in this block if this is the entry block. 724 if (LLVMBB == &Fn.getEntryBlock()) 725 LowerArguments(LLVMBB); 726 727 // Before doing SelectionDAG ISel, see if FastISel has been requested. 728 // FastISel doesn't support EH landing pads, which require special handling. 729 if (EnableFastISel && !BB->isLandingPad()) { 730 if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, FuncInfo->ValueMap, 731 FuncInfo->MBBMap)) { 732 // Emit code for any incoming arguments. This must happen before 733 // beginning FastISel on the entry block. 734 if (LLVMBB == &Fn.getEntryBlock()) { 735 CurDAG->setRoot(SDL->getControlRoot()); 736 CodeGenAndEmitDAG(); 737 SDL->clear(); 738 } 739 F->setCurrentBlock(BB); 740 // Do FastISel on as many instructions as possible. 741 for (; BI != End; ++BI) { 742 // Just before the terminator instruction, insert instructions to 743 // feed PHI nodes in successor blocks. 744 if (isa<TerminatorInst>(BI)) 745 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, F)) { 746 if (DisableFastISelAbort) 747 break; 748#ifndef NDEBUG 749 BI->dump(); 750#endif 751 assert(0 && "FastISel didn't handle a PHI in a successor"); 752 } 753 754 // First try normal tablegen-generated "fast" selection. 755 if (F->SelectInstruction(BI)) 756 continue; 757 758 // Next, try calling the target to attempt to handle the instruction. 759 if (F->TargetSelectInstruction(BI)) 760 continue; 761 762 // Then handle certain instructions as single-LLVM-Instruction blocks. 763 if (isa<CallInst>(BI)) { 764 if (BI->getType() != Type::VoidTy) { 765 unsigned &R = FuncInfo->ValueMap[BI]; 766 if (!R) 767 R = FuncInfo->CreateRegForValue(BI); 768 } 769 770 SelectBasicBlock(LLVMBB, BI, next(BI)); 771 continue; 772 } 773 774 if (!DisableFastISelAbort && 775 // For now, don't abort on non-conditional-branch terminators. 776 (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI))) { 777 // The "fast" selector couldn't handle something and bailed. 778 // For the purpose of debugging, just abort. 779#ifndef NDEBUG 780 BI->dump(); 781#endif 782 assert(0 && "FastISel didn't select the entire block"); 783 } 784 break; 785 } 786 delete F; 787 } 788 } 789 790 // Run SelectionDAG instruction selection on the remainder of the block 791 // not handled by FastISel. If FastISel is not run, this is the entire 792 // block. 793 if (BI != End) 794 SelectBasicBlock(LLVMBB, BI, End); 795 796 FinishBasicBlock(); 797 } 798} 799 800void 801SelectionDAGISel::FinishBasicBlock() { 802 803 // Perform target specific isel post processing. 804 InstructionSelectPostProcessing(); 805 806 DOUT << "Target-post-processed machine code:\n"; 807 DEBUG(BB->dump()); 808 809 DOUT << "Total amount of phi nodes to update: " 810 << SDL->PHINodesToUpdate.size() << "\n"; 811 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 812 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 813 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 814 815 // Next, now that we know what the last MBB the LLVM BB expanded is, update 816 // PHI nodes in successors. 817 if (SDL->SwitchCases.empty() && 818 SDL->JTCases.empty() && 819 SDL->BitTestCases.empty()) { 820 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 821 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 822 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 823 "This is not a machine PHI node that we are updating!"); 824 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 825 false)); 826 PHI->addOperand(MachineOperand::CreateMBB(BB)); 827 } 828 SDL->PHINodesToUpdate.clear(); 829 return; 830 } 831 832 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 833 // Lower header first, if it wasn't already lowered 834 if (!SDL->BitTestCases[i].Emitted) { 835 // Set the current basic block to the mbb we wish to insert the code into 836 BB = SDL->BitTestCases[i].Parent; 837 SDL->setCurrentBasicBlock(BB); 838 // Emit the code 839 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 840 CurDAG->setRoot(SDL->getRoot()); 841 CodeGenAndEmitDAG(); 842 SDL->clear(); 843 } 844 845 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 846 // Set the current basic block to the mbb we wish to insert the code into 847 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 848 SDL->setCurrentBasicBlock(BB); 849 // Emit the code 850 if (j+1 != ej) 851 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 852 SDL->BitTestCases[i].Reg, 853 SDL->BitTestCases[i].Cases[j]); 854 else 855 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 856 SDL->BitTestCases[i].Reg, 857 SDL->BitTestCases[i].Cases[j]); 858 859 860 CurDAG->setRoot(SDL->getRoot()); 861 CodeGenAndEmitDAG(); 862 SDL->clear(); 863 } 864 865 // Update PHI Nodes 866 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 867 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 868 MachineBasicBlock *PHIBB = PHI->getParent(); 869 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 870 "This is not a machine PHI node that we are updating!"); 871 // This is "default" BB. We have two jumps to it. From "header" BB and 872 // from last "case" BB. 873 if (PHIBB == SDL->BitTestCases[i].Default) { 874 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 875 false)); 876 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 877 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 878 false)); 879 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 880 back().ThisBB)); 881 } 882 // One of "cases" BB. 883 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 884 j != ej; ++j) { 885 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 886 if (cBB->succ_end() != 887 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 888 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 889 false)); 890 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 891 } 892 } 893 } 894 } 895 SDL->BitTestCases.clear(); 896 897 // If the JumpTable record is filled in, then we need to emit a jump table. 898 // Updating the PHI nodes is tricky in this case, since we need to determine 899 // whether the PHI is a successor of the range check MBB or the jump table MBB 900 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 901 // Lower header first, if it wasn't already lowered 902 if (!SDL->JTCases[i].first.Emitted) { 903 // Set the current basic block to the mbb we wish to insert the code into 904 BB = SDL->JTCases[i].first.HeaderBB; 905 SDL->setCurrentBasicBlock(BB); 906 // Emit the code 907 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 908 CurDAG->setRoot(SDL->getRoot()); 909 CodeGenAndEmitDAG(); 910 SDL->clear(); 911 } 912 913 // Set the current basic block to the mbb we wish to insert the code into 914 BB = SDL->JTCases[i].second.MBB; 915 SDL->setCurrentBasicBlock(BB); 916 // Emit the code 917 SDL->visitJumpTable(SDL->JTCases[i].second); 918 CurDAG->setRoot(SDL->getRoot()); 919 CodeGenAndEmitDAG(); 920 SDL->clear(); 921 922 // Update PHI Nodes 923 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 924 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 925 MachineBasicBlock *PHIBB = PHI->getParent(); 926 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 927 "This is not a machine PHI node that we are updating!"); 928 // "default" BB. We can go there only from header BB. 929 if (PHIBB == SDL->JTCases[i].second.Default) { 930 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 931 false)); 932 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 933 } 934 // JT BB. Just iterate over successors here 935 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 936 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 937 false)); 938 PHI->addOperand(MachineOperand::CreateMBB(BB)); 939 } 940 } 941 } 942 SDL->JTCases.clear(); 943 944 // If the switch block involved a branch to one of the actual successors, we 945 // need to update PHI nodes in that block. 946 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 947 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 948 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 949 "This is not a machine PHI node that we are updating!"); 950 if (BB->isSuccessor(PHI->getParent())) { 951 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 952 false)); 953 PHI->addOperand(MachineOperand::CreateMBB(BB)); 954 } 955 } 956 957 // If we generated any switch lowering information, build and codegen any 958 // additional DAGs necessary. 959 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 960 // Set the current basic block to the mbb we wish to insert the code into 961 BB = SDL->SwitchCases[i].ThisBB; 962 SDL->setCurrentBasicBlock(BB); 963 964 // Emit the code 965 SDL->visitSwitchCase(SDL->SwitchCases[i]); 966 CurDAG->setRoot(SDL->getRoot()); 967 CodeGenAndEmitDAG(); 968 SDL->clear(); 969 970 // Handle any PHI nodes in successors of this chunk, as if we were coming 971 // from the original BB before switch expansion. Note that PHI nodes can 972 // occur multiple times in PHINodesToUpdate. We have to be very careful to 973 // handle them the right number of times. 974 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 975 for (MachineBasicBlock::iterator Phi = BB->begin(); 976 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 977 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 978 for (unsigned pn = 0; ; ++pn) { 979 assert(pn != SDL->PHINodesToUpdate.size() && 980 "Didn't find PHI entry!"); 981 if (SDL->PHINodesToUpdate[pn].first == Phi) { 982 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 983 second, false)); 984 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 985 break; 986 } 987 } 988 } 989 990 // Don't process RHS if same block as LHS. 991 if (BB == SDL->SwitchCases[i].FalseBB) 992 SDL->SwitchCases[i].FalseBB = 0; 993 994 // If we haven't handled the RHS, do so now. Otherwise, we're done. 995 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 996 SDL->SwitchCases[i].FalseBB = 0; 997 } 998 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 999 } 1000 SDL->SwitchCases.clear(); 1001 1002 SDL->PHINodesToUpdate.clear(); 1003} 1004 1005 1006/// Schedule - Pick a safe ordering for instructions for each 1007/// target node in the graph. 1008/// 1009ScheduleDAG *SelectionDAGISel::Schedule() { 1010 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1011 1012 if (!Ctor) { 1013 Ctor = ISHeuristic; 1014 RegisterScheduler::setDefault(Ctor); 1015 } 1016 1017 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast); 1018 Scheduler->Run(); 1019 1020 return Scheduler; 1021} 1022 1023 1024HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1025 return new HazardRecognizer(); 1026} 1027 1028//===----------------------------------------------------------------------===// 1029// Helper functions used by the generated instruction selector. 1030//===----------------------------------------------------------------------===// 1031// Calls to these methods are generated by tblgen. 1032 1033/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1034/// the dag combiner simplified the 255, we still want to match. RHS is the 1035/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1036/// specified in the .td file (e.g. 255). 1037bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1038 int64_t DesiredMaskS) const { 1039 const APInt &ActualMask = RHS->getAPIntValue(); 1040 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1041 1042 // If the actual mask exactly matches, success! 1043 if (ActualMask == DesiredMask) 1044 return true; 1045 1046 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1047 if (ActualMask.intersects(~DesiredMask)) 1048 return false; 1049 1050 // Otherwise, the DAG Combiner may have proven that the value coming in is 1051 // either already zero or is not demanded. Check for known zero input bits. 1052 APInt NeededMask = DesiredMask & ~ActualMask; 1053 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1054 return true; 1055 1056 // TODO: check to see if missing bits are just not demanded. 1057 1058 // Otherwise, this pattern doesn't match. 1059 return false; 1060} 1061 1062/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1063/// the dag combiner simplified the 255, we still want to match. RHS is the 1064/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1065/// specified in the .td file (e.g. 255). 1066bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1067 int64_t DesiredMaskS) const { 1068 const APInt &ActualMask = RHS->getAPIntValue(); 1069 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1070 1071 // If the actual mask exactly matches, success! 1072 if (ActualMask == DesiredMask) 1073 return true; 1074 1075 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1076 if (ActualMask.intersects(~DesiredMask)) 1077 return false; 1078 1079 // Otherwise, the DAG Combiner may have proven that the value coming in is 1080 // either already zero or is not demanded. Check for known zero input bits. 1081 APInt NeededMask = DesiredMask & ~ActualMask; 1082 1083 APInt KnownZero, KnownOne; 1084 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1085 1086 // If all the missing bits in the or are already known to be set, match! 1087 if ((NeededMask & KnownOne) == NeededMask) 1088 return true; 1089 1090 // TODO: check to see if missing bits are just not demanded. 1091 1092 // Otherwise, this pattern doesn't match. 1093 return false; 1094} 1095 1096 1097/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1098/// by tblgen. Others should not call it. 1099void SelectionDAGISel:: 1100SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1101 std::vector<SDValue> InOps; 1102 std::swap(InOps, Ops); 1103 1104 Ops.push_back(InOps[0]); // input chain. 1105 Ops.push_back(InOps[1]); // input asm string. 1106 1107 unsigned i = 2, e = InOps.size(); 1108 if (InOps[e-1].getValueType() == MVT::Flag) 1109 --e; // Don't process a flag operand if it is here. 1110 1111 while (i != e) { 1112 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 1113 if ((Flags & 7) != 4 /*MEM*/) { 1114 // Just skip over this operand, copying the operands verbatim. 1115 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 1116 i += (Flags >> 3) + 1; 1117 } else { 1118 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 1119 // Otherwise, this is a memory operand. Ask the target to select it. 1120 std::vector<SDValue> SelOps; 1121 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1122 cerr << "Could not match memory address. Inline asm failure!\n"; 1123 exit(1); 1124 } 1125 1126 // Add this to the output node. 1127 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy(); 1128 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 1129 IntPtrTy)); 1130 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1131 i += 2; 1132 } 1133 } 1134 1135 // Add the flag input back if present. 1136 if (e != InOps.size()) 1137 Ops.push_back(InOps.back()); 1138} 1139 1140char SelectionDAGISel::ID = 0; 1141