SelectionDAGISel.cpp revision d0e9b6728ee42919652fd1fe450f2c73ebe0ea79
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 36#include "llvm/CodeGen/SchedulerRegistry.h" 37#include "llvm/CodeGen/SelectionDAG.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetIntrinsicInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/Statistic.h" 50#include <algorithm> 51using namespace llvm; 52 53STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 54STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 55 56static cl::opt<bool> 57EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 58 cl::desc("Enable verbose messages in the \"fast\" " 59 "instruction selector")); 60static cl::opt<bool> 61EnableFastISelAbort("fast-isel-abort", cl::Hidden, 62 cl::desc("Enable abort calls when \"fast\" instruction fails")); 63 64#ifndef NDEBUG 65static cl::opt<bool> 66ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 67 cl::desc("Pop up a window to show dags before the first " 68 "dag combine pass")); 69static cl::opt<bool> 70ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 71 cl::desc("Pop up a window to show dags before legalize types")); 72static cl::opt<bool> 73ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 74 cl::desc("Pop up a window to show dags before legalize")); 75static cl::opt<bool> 76ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the second " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the post legalize types" 82 " dag combine pass")); 83static cl::opt<bool> 84ViewISelDAGs("view-isel-dags", cl::Hidden, 85 cl::desc("Pop up a window to show isel dags as they are selected")); 86static cl::opt<bool> 87ViewSchedDAGs("view-sched-dags", cl::Hidden, 88 cl::desc("Pop up a window to show sched dags as they are processed")); 89static cl::opt<bool> 90ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 91 cl::desc("Pop up a window to show SUnit dags after they are processed")); 92#else 93static const bool ViewDAGCombine1 = false, 94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 95 ViewDAGCombine2 = false, 96 ViewDAGCombineLT = false, 97 ViewISelDAGs = false, ViewSchedDAGs = false, 98 ViewSUnitDAGs = false; 99#endif 100 101//===---------------------------------------------------------------------===// 102/// 103/// RegisterScheduler class - Track the registration of instruction schedulers. 104/// 105//===---------------------------------------------------------------------===// 106MachinePassRegistry RegisterScheduler::Registry; 107 108//===---------------------------------------------------------------------===// 109/// 110/// ISHeuristic command line option for instruction schedulers. 111/// 112//===---------------------------------------------------------------------===// 113static cl::opt<RegisterScheduler::FunctionPassCtor, false, 114 RegisterPassParser<RegisterScheduler> > 115ISHeuristic("pre-RA-sched", 116 cl::init(&createDefaultScheduler), 117 cl::desc("Instruction schedulers available (before register" 118 " allocation):")); 119 120static RegisterScheduler 121defaultListDAGScheduler("default", "Best scheduler for the target", 122 createDefaultScheduler); 123 124namespace llvm { 125 //===--------------------------------------------------------------------===// 126 /// createDefaultScheduler - This creates an instruction scheduler appropriate 127 /// for the target. 128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 129 CodeGenOpt::Level OptLevel) { 130 const TargetLowering &TLI = IS->getTargetLowering(); 131 132 if (OptLevel == CodeGenOpt::None) 133 return createFastDAGScheduler(IS, OptLevel); 134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 135 return createTDListDAGScheduler(IS, OptLevel); 136 assert(TLI.getSchedulingPreference() == 137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 138 return createBURRListDAGScheduler(IS, OptLevel); 139 } 140} 141 142// EmitInstrWithCustomInserter - This method should be implemented by targets 143// that mark instructions with the 'usesCustomInserter' flag. These 144// instructions are special in various ways, which require special support to 145// insert. The specified MachineInstr is created but not inserted into any 146// basic blocks, and this method is called to expand it into a sequence of 147// instructions, potentially also creating new basic blocks and control flow. 148// When new basic blocks are inserted and the edges from MBB to its successors 149// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 150// DenseMap. 151MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 152 MachineBasicBlock *MBB, 153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 154#ifndef NDEBUG 155 dbgs() << "If a target marks an instruction with " 156 "'usesCustomInserter', it must implement " 157 "TargetLowering::EmitInstrWithCustomInserter!"; 158#endif 159 llvm_unreachable(0); 160 return 0; 161} 162 163//===----------------------------------------------------------------------===// 164// SelectionDAGISel code 165//===----------------------------------------------------------------------===// 166 167SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 169 FuncInfo(new FunctionLoweringInfo(TLI)), 170 CurDAG(new SelectionDAG(tm, *FuncInfo)), 171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 172 GFI(), 173 OptLevel(OL), 174 DAGSize(0) 175{} 176 177SelectionDAGISel::~SelectionDAGISel() { 178 delete SDB; 179 delete CurDAG; 180 delete FuncInfo; 181} 182 183void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 184 AU.addRequired<AliasAnalysis>(); 185 AU.addPreserved<AliasAnalysis>(); 186 AU.addRequired<GCModuleInfo>(); 187 AU.addPreserved<GCModuleInfo>(); 188 MachineFunctionPass::getAnalysisUsage(AU); 189} 190 191bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 192 // Do some sanity-checking on the command-line options. 193 assert((!EnableFastISelVerbose || EnableFastISel) && 194 "-fast-isel-verbose requires -fast-isel"); 195 assert((!EnableFastISelAbort || EnableFastISel) && 196 "-fast-isel-abort requires -fast-isel"); 197 198 const Function &Fn = *mf.getFunction(); 199 const TargetInstrInfo &TII = *TM.getInstrInfo(); 200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 201 202 MF = &mf; 203 RegInfo = &MF->getRegInfo(); 204 AA = &getAnalysis<AliasAnalysis>(); 205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 206 207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 208 209 CurDAG->init(*MF); 210 FuncInfo->set(Fn, *MF, EnableFastISel); 211 SDB->init(GFI, *AA); 212 213 SelectAllBasicBlocks(Fn); 214 215 // Release function-specific state. SDB and CurDAG are already cleared 216 // at this point. 217 FuncInfo->clear(); 218 219 // If the first basic block in the function has live ins that need to be 220 // copied into vregs, emit the copies into the top of the block before 221 // emitting the code for the block. 222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII); 223 224 return true; 225} 226 227/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 228/// attached with this instruction. 229static void SetDebugLoc(const Instruction *I, SelectionDAGBuilder *SDB, 230 FastISel *FastIS, MachineFunction *MF) { 231 DebugLoc DL = I->getDebugLoc(); 232 if (DL.isUnknown()) return; 233 234 SDB->setCurDebugLoc(DL); 235 236 if (FastIS) 237 FastIS->setCurDebugLoc(DL); 238} 239 240/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 241static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 242 SDB->setCurDebugLoc(DebugLoc()); 243 if (FastIS) 244 FastIS->setCurDebugLoc(DebugLoc()); 245} 246 247MachineBasicBlock * 248SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 249 const BasicBlock *LLVMBB, 250 BasicBlock::const_iterator Begin, 251 BasicBlock::const_iterator End, 252 bool &HadTailCall) { 253 // Lower all of the non-terminator instructions. If a call is emitted 254 // as a tail call, cease emitting nodes for this block. Terminators 255 // are handled below. 256 for (BasicBlock::const_iterator I = Begin; 257 I != End && !SDB->HasTailCall && !isa<TerminatorInst>(I); 258 ++I) { 259 SetDebugLoc(I, SDB, 0, MF); 260 SDB->visit(*I); 261 ResetDebugLoc(SDB, 0); 262 } 263 264 if (!SDB->HasTailCall) { 265 // Ensure that all instructions which are used outside of their defining 266 // blocks are available as virtual registers. Invoke is handled elsewhere. 267 for (BasicBlock::const_iterator I = Begin; I != End; ++I) 268 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 269 SDB->CopyToExportRegsIfNeeded(I); 270 271 // Handle PHI nodes in successor blocks. 272 if (End == LLVMBB->end()) { 273 HandlePHINodesInSuccessorBlocks(LLVMBB); 274 275 // Lower the terminator after the copies are emitted. 276 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF); 277 SDB->visit(*LLVMBB->getTerminator()); 278 ResetDebugLoc(SDB, 0); 279 } 280 } 281 282 // Make sure the root of the DAG is up-to-date. 283 CurDAG->setRoot(SDB->getControlRoot()); 284 285 // Final step, emit the lowered DAG as machine code. 286 BB = CodeGenAndEmitDAG(BB); 287 HadTailCall = SDB->HasTailCall; 288 SDB->clear(); 289 return BB; 290} 291 292namespace { 293/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 294/// nodes from the worklist. 295class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 296 SmallVector<SDNode*, 128> &Worklist; 297 SmallPtrSet<SDNode*, 128> &InWorklist; 298public: 299 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 300 SmallPtrSet<SDNode*, 128> &inwl) 301 : Worklist(wl), InWorklist(inwl) {} 302 303 void RemoveFromWorklist(SDNode *N) { 304 if (!InWorklist.erase(N)) return; 305 306 SmallVector<SDNode*, 128>::iterator I = 307 std::find(Worklist.begin(), Worklist.end(), N); 308 assert(I != Worklist.end() && "Not in worklist"); 309 310 *I = Worklist.back(); 311 Worklist.pop_back(); 312 } 313 314 virtual void NodeDeleted(SDNode *N, SDNode *E) { 315 RemoveFromWorklist(N); 316 } 317 318 virtual void NodeUpdated(SDNode *N) { 319 // Ignore updates. 320 } 321}; 322} 323 324/// TrivialTruncElim - Eliminate some trivial nops that can result from 325/// ShrinkDemandedOps: (trunc (ext n)) -> n. 326static bool TrivialTruncElim(SDValue Op, 327 TargetLowering::TargetLoweringOpt &TLO) { 328 SDValue N0 = Op.getOperand(0); 329 EVT VT = Op.getValueType(); 330 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 331 N0.getOpcode() == ISD::SIGN_EXTEND || 332 N0.getOpcode() == ISD::ANY_EXTEND) && 333 N0.getOperand(0).getValueType() == VT) { 334 return TLO.CombineTo(Op, N0.getOperand(0)); 335 } 336 return false; 337} 338 339/// ShrinkDemandedOps - A late transformation pass that shrink expressions 340/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 341/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 342void SelectionDAGISel::ShrinkDemandedOps() { 343 SmallVector<SDNode*, 128> Worklist; 344 SmallPtrSet<SDNode*, 128> InWorklist; 345 346 // Add all the dag nodes to the worklist. 347 Worklist.reserve(CurDAG->allnodes_size()); 348 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 349 E = CurDAG->allnodes_end(); I != E; ++I) { 350 Worklist.push_back(I); 351 InWorklist.insert(I); 352 } 353 354 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); 355 while (!Worklist.empty()) { 356 SDNode *N = Worklist.pop_back_val(); 357 InWorklist.erase(N); 358 359 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 360 // Deleting this node may make its operands dead, add them to the worklist 361 // if they aren't already there. 362 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 363 if (InWorklist.insert(N->getOperand(i).getNode())) 364 Worklist.push_back(N->getOperand(i).getNode()); 365 366 CurDAG->DeleteNode(N); 367 continue; 368 } 369 370 // Run ShrinkDemandedOp on scalar binary operations. 371 if (N->getNumValues() != 1 || 372 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) 373 continue; 374 375 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 376 APInt Demanded = APInt::getAllOnesValue(BitWidth); 377 APInt KnownZero, KnownOne; 378 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 379 KnownZero, KnownOne, TLO) && 380 (N->getOpcode() != ISD::TRUNCATE || 381 !TrivialTruncElim(SDValue(N, 0), TLO))) 382 continue; 383 384 // Revisit the node. 385 assert(!InWorklist.count(N) && "Already in worklist"); 386 Worklist.push_back(N); 387 InWorklist.insert(N); 388 389 // Replace the old value with the new one. 390 DEBUG(errs() << "\nShrinkDemandedOps replacing "; 391 TLO.Old.getNode()->dump(CurDAG); 392 errs() << "\nWith: "; 393 TLO.New.getNode()->dump(CurDAG); 394 errs() << '\n'); 395 396 if (InWorklist.insert(TLO.New.getNode())) 397 Worklist.push_back(TLO.New.getNode()); 398 399 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); 400 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 401 402 if (!TLO.Old.getNode()->use_empty()) continue; 403 404 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 405 i != e; ++i) { 406 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 407 if (OpNode->hasOneUse()) { 408 // Add OpNode to the end of the list to revisit. 409 DeadNodes.RemoveFromWorklist(OpNode); 410 Worklist.push_back(OpNode); 411 InWorklist.insert(OpNode); 412 } 413 } 414 415 DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); 416 CurDAG->DeleteNode(TLO.Old.getNode()); 417 } 418} 419 420void SelectionDAGISel::ComputeLiveOutVRegInfo() { 421 SmallPtrSet<SDNode*, 128> VisitedNodes; 422 SmallVector<SDNode*, 128> Worklist; 423 424 Worklist.push_back(CurDAG->getRoot().getNode()); 425 426 APInt Mask; 427 APInt KnownZero; 428 APInt KnownOne; 429 430 do { 431 SDNode *N = Worklist.pop_back_val(); 432 433 // If we've already seen this node, ignore it. 434 if (!VisitedNodes.insert(N)) 435 continue; 436 437 // Otherwise, add all chain operands to the worklist. 438 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 439 if (N->getOperand(i).getValueType() == MVT::Other) 440 Worklist.push_back(N->getOperand(i).getNode()); 441 442 // If this is a CopyToReg with a vreg dest, process it. 443 if (N->getOpcode() != ISD::CopyToReg) 444 continue; 445 446 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 447 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 448 continue; 449 450 // Ignore non-scalar or non-integer values. 451 SDValue Src = N->getOperand(2); 452 EVT SrcVT = Src.getValueType(); 453 if (!SrcVT.isInteger() || SrcVT.isVector()) 454 continue; 455 456 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 457 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 458 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 459 460 // Only install this information if it tells us something. 461 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 462 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 463 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 464 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 465 FunctionLoweringInfo::LiveOutInfo &LOI = 466 FuncInfo->LiveOutRegInfo[DestReg]; 467 LOI.NumSignBits = NumSignBits; 468 LOI.KnownOne = KnownOne; 469 LOI.KnownZero = KnownZero; 470 } 471 } while (!Worklist.empty()); 472} 473 474MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 475 std::string GroupName; 476 if (TimePassesIsEnabled) 477 GroupName = "Instruction Selection and Scheduling"; 478 std::string BlockName; 479 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 480 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 481 ViewSUnitDAGs) 482 BlockName = MF->getFunction()->getNameStr() + ":" + 483 BB->getBasicBlock()->getNameStr(); 484 485 DEBUG(dbgs() << "Initial selection DAG:\n"); 486 DEBUG(CurDAG->dump()); 487 488 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 489 490 // Run the DAG combiner in pre-legalize mode. 491 if (TimePassesIsEnabled) { 492 NamedRegionTimer T("DAG Combining 1", GroupName); 493 CurDAG->Combine(Unrestricted, *AA, OptLevel); 494 } else { 495 CurDAG->Combine(Unrestricted, *AA, OptLevel); 496 } 497 498 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 499 DEBUG(CurDAG->dump()); 500 501 // Second step, hack on the DAG until it only uses operations and types that 502 // the target supports. 503 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 504 BlockName); 505 506 bool Changed; 507 if (TimePassesIsEnabled) { 508 NamedRegionTimer T("Type Legalization", GroupName); 509 Changed = CurDAG->LegalizeTypes(); 510 } else { 511 Changed = CurDAG->LegalizeTypes(); 512 } 513 514 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 515 DEBUG(CurDAG->dump()); 516 517 if (Changed) { 518 if (ViewDAGCombineLT) 519 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 520 521 // Run the DAG combiner in post-type-legalize mode. 522 if (TimePassesIsEnabled) { 523 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 524 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 525 } else { 526 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 527 } 528 529 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 530 DEBUG(CurDAG->dump()); 531 } 532 533 if (TimePassesIsEnabled) { 534 NamedRegionTimer T("Vector Legalization", GroupName); 535 Changed = CurDAG->LegalizeVectors(); 536 } else { 537 Changed = CurDAG->LegalizeVectors(); 538 } 539 540 if (Changed) { 541 if (TimePassesIsEnabled) { 542 NamedRegionTimer T("Type Legalization 2", GroupName); 543 CurDAG->LegalizeTypes(); 544 } else { 545 CurDAG->LegalizeTypes(); 546 } 547 548 if (ViewDAGCombineLT) 549 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 550 551 // Run the DAG combiner in post-type-legalize mode. 552 if (TimePassesIsEnabled) { 553 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 554 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 555 } else { 556 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 557 } 558 559 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 560 DEBUG(CurDAG->dump()); 561 } 562 563 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 564 565 if (TimePassesIsEnabled) { 566 NamedRegionTimer T("DAG Legalization", GroupName); 567 CurDAG->Legalize(OptLevel); 568 } else { 569 CurDAG->Legalize(OptLevel); 570 } 571 572 DEBUG(dbgs() << "Legalized selection DAG:\n"); 573 DEBUG(CurDAG->dump()); 574 575 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 576 577 // Run the DAG combiner in post-legalize mode. 578 if (TimePassesIsEnabled) { 579 NamedRegionTimer T("DAG Combining 2", GroupName); 580 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 581 } else { 582 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 583 } 584 585 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 586 DEBUG(CurDAG->dump()); 587 588 if (OptLevel != CodeGenOpt::None) { 589 ShrinkDemandedOps(); 590 ComputeLiveOutVRegInfo(); 591 } 592 593 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 594 595 // Third, instruction select all of the operations to machine code, adding the 596 // code to the MachineBasicBlock. 597 if (TimePassesIsEnabled) { 598 NamedRegionTimer T("Instruction Selection", GroupName); 599 DoInstructionSelection(); 600 } else { 601 DoInstructionSelection(); 602 } 603 604 DEBUG(dbgs() << "Selected selection DAG:\n"); 605 DEBUG(CurDAG->dump()); 606 607 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 608 609 // Schedule machine code. 610 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 611 if (TimePassesIsEnabled) { 612 NamedRegionTimer T("Instruction Scheduling", GroupName); 613 Scheduler->Run(CurDAG, BB, BB->end()); 614 } else { 615 Scheduler->Run(CurDAG, BB, BB->end()); 616 } 617 618 if (ViewSUnitDAGs) Scheduler->viewGraph(); 619 620 // Emit machine code to BB. This can change 'BB' to the last block being 621 // inserted into. 622 if (TimePassesIsEnabled) { 623 NamedRegionTimer T("Instruction Creation", GroupName); 624 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 625 } else { 626 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 627 } 628 629 // Free the scheduler state. 630 if (TimePassesIsEnabled) { 631 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 632 delete Scheduler; 633 } else { 634 delete Scheduler; 635 } 636 637 DEBUG(dbgs() << "Selected machine code:\n"); 638 DEBUG(BB->dump()); 639 return BB; 640} 641 642void SelectionDAGISel::DoInstructionSelection() { 643 DEBUG(errs() << "===== Instruction selection begins:\n"); 644 645 PreprocessISelDAG(); 646 647 // Select target instructions for the DAG. 648 { 649 // Number all nodes with a topological order and set DAGSize. 650 DAGSize = CurDAG->AssignTopologicalOrder(); 651 652 // Create a dummy node (which is not added to allnodes), that adds 653 // a reference to the root node, preventing it from being deleted, 654 // and tracking any changes of the root. 655 HandleSDNode Dummy(CurDAG->getRoot()); 656 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 657 ++ISelPosition; 658 659 // The AllNodes list is now topological-sorted. Visit the 660 // nodes by starting at the end of the list (the root of the 661 // graph) and preceding back toward the beginning (the entry 662 // node). 663 while (ISelPosition != CurDAG->allnodes_begin()) { 664 SDNode *Node = --ISelPosition; 665 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 666 // but there are currently some corner cases that it misses. Also, this 667 // makes it theoretically possible to disable the DAGCombiner. 668 if (Node->use_empty()) 669 continue; 670 671 SDNode *ResNode = Select(Node); 672 673 // FIXME: This is pretty gross. 'Select' should be changed to not return 674 // anything at all and this code should be nuked with a tactical strike. 675 676 // If node should not be replaced, continue with the next one. 677 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 678 continue; 679 // Replace node. 680 if (ResNode) 681 ReplaceUses(Node, ResNode); 682 683 // If after the replacement this node is not used any more, 684 // remove this dead node. 685 if (Node->use_empty()) { // Don't delete EntryToken, etc. 686 ISelUpdater ISU(ISelPosition); 687 CurDAG->RemoveDeadNode(Node, &ISU); 688 } 689 } 690 691 CurDAG->setRoot(Dummy.getValue()); 692 } 693 DEBUG(errs() << "===== Instruction selection ends:\n"); 694 695 PostprocessISelDAG(); 696} 697 698/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 699/// do other setup for EH landing-pad blocks. 700void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 701 // Add a label to mark the beginning of the landing pad. Deletion of the 702 // landing pad can thus be detected via the MachineModuleInfo. 703 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 704 705 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 706 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 707 708 // Mark exception register as live in. 709 unsigned Reg = TLI.getExceptionAddressRegister(); 710 if (Reg) BB->addLiveIn(Reg); 711 712 // Mark exception selector register as live in. 713 Reg = TLI.getExceptionSelectorRegister(); 714 if (Reg) BB->addLiveIn(Reg); 715 716 // FIXME: Hack around an exception handling flaw (PR1508): the personality 717 // function and list of typeids logically belong to the invoke (or, if you 718 // like, the basic block containing the invoke), and need to be associated 719 // with it in the dwarf exception handling tables. Currently however the 720 // information is provided by an intrinsic (eh.selector) that can be moved 721 // to unexpected places by the optimizers: if the unwind edge is critical, 722 // then breaking it can result in the intrinsics being in the successor of 723 // the landing pad, not the landing pad itself. This results 724 // in exceptions not being caught because no typeids are associated with 725 // the invoke. This may not be the only way things can go wrong, but it 726 // is the only way we try to work around for the moment. 727 const BasicBlock *LLVMBB = BB->getBasicBlock(); 728 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 729 730 if (Br && Br->isUnconditional()) { // Critical edge? 731 BasicBlock::const_iterator I, E; 732 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 733 if (isa<EHSelectorInst>(I)) 734 break; 735 736 if (I == E) 737 // No catch info found - try to extract some from the successor. 738 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 739 } 740} 741 742void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 743 // Initialize the Fast-ISel state, if needed. 744 FastISel *FastIS = 0; 745 if (EnableFastISel) 746 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 747 FuncInfo->StaticAllocaMap 748#ifndef NDEBUG 749 , FuncInfo->CatchInfoLost 750#endif 751 ); 752 753 // Iterate over all basic blocks in the function. 754 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 755 const BasicBlock *LLVMBB = &*I; 756 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 757 758 BasicBlock::const_iterator const Begin = LLVMBB->begin(); 759 BasicBlock::const_iterator const End = LLVMBB->end(); 760 BasicBlock::const_iterator BI = Begin; 761 762 // Lower any arguments needed in this block if this is the entry block. 763 bool SuppressFastISel = false; 764 if (LLVMBB == &Fn.getEntryBlock()) { 765 LowerArguments(LLVMBB); 766 767 // If any of the arguments has the byval attribute, forgo 768 // fast-isel in the entry block. 769 if (FastIS) { 770 unsigned j = 1; 771 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 772 I != E; ++I, ++j) 773 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 774 if (EnableFastISelVerbose || EnableFastISelAbort) 775 dbgs() << "FastISel skips entry block due to byval argument\n"; 776 SuppressFastISel = true; 777 break; 778 } 779 } 780 } 781 782 // Setup an EH landing-pad block. 783 if (BB->isLandingPad()) 784 PrepareEHLandingPad(BB); 785 786 // Before doing SelectionDAG ISel, see if FastISel has been requested. 787 if (FastIS && !SuppressFastISel) { 788 // Emit code for any incoming arguments. This must happen before 789 // beginning FastISel on the entry block. 790 if (LLVMBB == &Fn.getEntryBlock()) { 791 CurDAG->setRoot(SDB->getControlRoot()); 792 BB = CodeGenAndEmitDAG(BB); 793 SDB->clear(); 794 } 795 FastIS->startNewBlock(BB); 796 // Do FastISel on as many instructions as possible. 797 for (; BI != End; ++BI) { 798 // Just before the terminator instruction, insert instructions to 799 // feed PHI nodes in successor blocks. 800 if (isa<TerminatorInst>(BI)) 801 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 802 ++NumFastIselFailures; 803 ResetDebugLoc(SDB, FastIS); 804 if (EnableFastISelVerbose || EnableFastISelAbort) { 805 dbgs() << "FastISel miss: "; 806 BI->dump(); 807 } 808 assert(!EnableFastISelAbort && 809 "FastISel didn't handle a PHI in a successor"); 810 break; 811 } 812 813 SetDebugLoc(BI, SDB, FastIS, MF); 814 815 // Try to select the instruction with FastISel. 816 if (FastIS->SelectInstruction(BI)) { 817 ResetDebugLoc(SDB, FastIS); 818 continue; 819 } 820 821 // Clear out the debug location so that it doesn't carry over to 822 // unrelated instructions. 823 ResetDebugLoc(SDB, FastIS); 824 825 // Then handle certain instructions as single-LLVM-Instruction blocks. 826 if (isa<CallInst>(BI)) { 827 ++NumFastIselFailures; 828 if (EnableFastISelVerbose || EnableFastISelAbort) { 829 dbgs() << "FastISel missed call: "; 830 BI->dump(); 831 } 832 833 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 834 unsigned &R = FuncInfo->ValueMap[BI]; 835 if (!R) 836 R = FuncInfo->CreateRegForValue(BI); 837 } 838 839 bool HadTailCall = false; 840 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 841 842 // If the call was emitted as a tail call, we're done with the block. 843 if (HadTailCall) { 844 BI = End; 845 break; 846 } 847 848 // If the instruction was codegen'd with multiple blocks, 849 // inform the FastISel object where to resume inserting. 850 FastIS->setCurrentBlock(BB); 851 continue; 852 } 853 854 // Otherwise, give up on FastISel for the rest of the block. 855 // For now, be a little lenient about non-branch terminators. 856 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 857 ++NumFastIselFailures; 858 if (EnableFastISelVerbose || EnableFastISelAbort) { 859 dbgs() << "FastISel miss: "; 860 BI->dump(); 861 } 862 if (EnableFastISelAbort) 863 // The "fast" selector couldn't handle something and bailed. 864 // For the purpose of debugging, just abort. 865 llvm_unreachable("FastISel didn't select the entire block"); 866 } 867 break; 868 } 869 } 870 871 // Run SelectionDAG instruction selection on the remainder of the block 872 // not handled by FastISel. If FastISel is not run, this is the entire 873 // block. 874 if (BI != End) { 875 bool HadTailCall; 876 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 877 } 878 879 FinishBasicBlock(BB); 880 } 881 882 delete FastIS; 883} 884 885void 886SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 887 888 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 889 DEBUG(BB->dump()); 890 891 DEBUG(dbgs() << "Total amount of phi nodes to update: " 892 << SDB->PHINodesToUpdate.size() << "\n"); 893 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 894 dbgs() << "Node " << i << " : (" 895 << SDB->PHINodesToUpdate[i].first 896 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 897 898 // Next, now that we know what the last MBB the LLVM BB expanded is, update 899 // PHI nodes in successors. 900 if (SDB->SwitchCases.empty() && 901 SDB->JTCases.empty() && 902 SDB->BitTestCases.empty()) { 903 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 904 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 905 assert(PHI->isPHI() && 906 "This is not a machine PHI node that we are updating!"); 907 if (!BB->isSuccessor(PHI->getParent())) 908 continue; 909 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 910 false)); 911 PHI->addOperand(MachineOperand::CreateMBB(BB)); 912 } 913 SDB->PHINodesToUpdate.clear(); 914 return; 915 } 916 917 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 918 // Lower header first, if it wasn't already lowered 919 if (!SDB->BitTestCases[i].Emitted) { 920 // Set the current basic block to the mbb we wish to insert the code into 921 BB = SDB->BitTestCases[i].Parent; 922 // Emit the code 923 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 924 CurDAG->setRoot(SDB->getRoot()); 925 BB = CodeGenAndEmitDAG(BB); 926 SDB->clear(); 927 } 928 929 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 930 // Set the current basic block to the mbb we wish to insert the code into 931 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 932 // Emit the code 933 if (j+1 != ej) 934 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 935 SDB->BitTestCases[i].Reg, 936 SDB->BitTestCases[i].Cases[j], 937 BB); 938 else 939 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 940 SDB->BitTestCases[i].Reg, 941 SDB->BitTestCases[i].Cases[j], 942 BB); 943 944 945 CurDAG->setRoot(SDB->getRoot()); 946 BB = CodeGenAndEmitDAG(BB); 947 SDB->clear(); 948 } 949 950 // Update PHI Nodes 951 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 952 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 953 MachineBasicBlock *PHIBB = PHI->getParent(); 954 assert(PHI->isPHI() && 955 "This is not a machine PHI node that we are updating!"); 956 // This is "default" BB. We have two jumps to it. From "header" BB and 957 // from last "case" BB. 958 if (PHIBB == SDB->BitTestCases[i].Default) { 959 PHI->addOperand(MachineOperand:: 960 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 961 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 962 PHI->addOperand(MachineOperand:: 963 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 964 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 965 back().ThisBB)); 966 } 967 // One of "cases" BB. 968 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 969 j != ej; ++j) { 970 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 971 if (cBB->isSuccessor(PHIBB)) { 972 PHI->addOperand(MachineOperand:: 973 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 974 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 975 } 976 } 977 } 978 } 979 SDB->BitTestCases.clear(); 980 981 // If the JumpTable record is filled in, then we need to emit a jump table. 982 // Updating the PHI nodes is tricky in this case, since we need to determine 983 // whether the PHI is a successor of the range check MBB or the jump table MBB 984 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 985 // Lower header first, if it wasn't already lowered 986 if (!SDB->JTCases[i].first.Emitted) { 987 // Set the current basic block to the mbb we wish to insert the code into 988 BB = SDB->JTCases[i].first.HeaderBB; 989 // Emit the code 990 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 991 BB); 992 CurDAG->setRoot(SDB->getRoot()); 993 BB = CodeGenAndEmitDAG(BB); 994 SDB->clear(); 995 } 996 997 // Set the current basic block to the mbb we wish to insert the code into 998 BB = SDB->JTCases[i].second.MBB; 999 // Emit the code 1000 SDB->visitJumpTable(SDB->JTCases[i].second); 1001 CurDAG->setRoot(SDB->getRoot()); 1002 BB = CodeGenAndEmitDAG(BB); 1003 SDB->clear(); 1004 1005 // Update PHI Nodes 1006 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1007 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1008 MachineBasicBlock *PHIBB = PHI->getParent(); 1009 assert(PHI->isPHI() && 1010 "This is not a machine PHI node that we are updating!"); 1011 // "default" BB. We can go there only from header BB. 1012 if (PHIBB == SDB->JTCases[i].second.Default) { 1013 PHI->addOperand 1014 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1015 PHI->addOperand 1016 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1017 } 1018 // JT BB. Just iterate over successors here 1019 if (BB->isSuccessor(PHIBB)) { 1020 PHI->addOperand 1021 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1022 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1023 } 1024 } 1025 } 1026 SDB->JTCases.clear(); 1027 1028 // If the switch block involved a branch to one of the actual successors, we 1029 // need to update PHI nodes in that block. 1030 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1031 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1032 assert(PHI->isPHI() && 1033 "This is not a machine PHI node that we are updating!"); 1034 if (BB->isSuccessor(PHI->getParent())) { 1035 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1036 false)); 1037 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1038 } 1039 } 1040 1041 // If we generated any switch lowering information, build and codegen any 1042 // additional DAGs necessary. 1043 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1044 // Set the current basic block to the mbb we wish to insert the code into 1045 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1046 1047 // Emit the code 1048 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 1049 CurDAG->setRoot(SDB->getRoot()); 1050 BB = CodeGenAndEmitDAG(BB); 1051 1052 // Handle any PHI nodes in successors of this chunk, as if we were coming 1053 // from the original BB before switch expansion. Note that PHI nodes can 1054 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1055 // handle them the right number of times. 1056 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1057 // If new BB's are created during scheduling, the edges may have been 1058 // updated. That is, the edge from ThisBB to BB may have been split and 1059 // BB's predecessor is now another block. 1060 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1061 SDB->EdgeMapping.find(BB); 1062 if (EI != SDB->EdgeMapping.end()) 1063 ThisBB = EI->second; 1064 1065 // BB may have been removed from the CFG if a branch was constant folded. 1066 if (ThisBB->isSuccessor(BB)) { 1067 for (MachineBasicBlock::iterator Phi = BB->begin(); 1068 Phi != BB->end() && Phi->isPHI(); 1069 ++Phi) { 1070 // This value for this PHI node is recorded in PHINodesToUpdate. 1071 for (unsigned pn = 0; ; ++pn) { 1072 assert(pn != SDB->PHINodesToUpdate.size() && 1073 "Didn't find PHI entry!"); 1074 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1075 Phi->addOperand(MachineOperand:: 1076 CreateReg(SDB->PHINodesToUpdate[pn].second, 1077 false)); 1078 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1079 break; 1080 } 1081 } 1082 } 1083 } 1084 1085 // Don't process RHS if same block as LHS. 1086 if (BB == SDB->SwitchCases[i].FalseBB) 1087 SDB->SwitchCases[i].FalseBB = 0; 1088 1089 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1090 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1091 SDB->SwitchCases[i].FalseBB = 0; 1092 } 1093 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1094 SDB->clear(); 1095 } 1096 SDB->SwitchCases.clear(); 1097 1098 SDB->PHINodesToUpdate.clear(); 1099} 1100 1101 1102/// Create the scheduler. If a specific scheduler was specified 1103/// via the SchedulerRegistry, use it, otherwise select the 1104/// one preferred by the target. 1105/// 1106ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1107 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1108 1109 if (!Ctor) { 1110 Ctor = ISHeuristic; 1111 RegisterScheduler::setDefault(Ctor); 1112 } 1113 1114 return Ctor(this, OptLevel); 1115} 1116 1117ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1118 return new ScheduleHazardRecognizer(); 1119} 1120 1121//===----------------------------------------------------------------------===// 1122// Helper functions used by the generated instruction selector. 1123//===----------------------------------------------------------------------===// 1124// Calls to these methods are generated by tblgen. 1125 1126/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1127/// the dag combiner simplified the 255, we still want to match. RHS is the 1128/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1129/// specified in the .td file (e.g. 255). 1130bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1131 int64_t DesiredMaskS) const { 1132 const APInt &ActualMask = RHS->getAPIntValue(); 1133 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1134 1135 // If the actual mask exactly matches, success! 1136 if (ActualMask == DesiredMask) 1137 return true; 1138 1139 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1140 if (ActualMask.intersects(~DesiredMask)) 1141 return false; 1142 1143 // Otherwise, the DAG Combiner may have proven that the value coming in is 1144 // either already zero or is not demanded. Check for known zero input bits. 1145 APInt NeededMask = DesiredMask & ~ActualMask; 1146 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1147 return true; 1148 1149 // TODO: check to see if missing bits are just not demanded. 1150 1151 // Otherwise, this pattern doesn't match. 1152 return false; 1153} 1154 1155/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1156/// the dag combiner simplified the 255, we still want to match. RHS is the 1157/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1158/// specified in the .td file (e.g. 255). 1159bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1160 int64_t DesiredMaskS) const { 1161 const APInt &ActualMask = RHS->getAPIntValue(); 1162 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1163 1164 // If the actual mask exactly matches, success! 1165 if (ActualMask == DesiredMask) 1166 return true; 1167 1168 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1169 if (ActualMask.intersects(~DesiredMask)) 1170 return false; 1171 1172 // Otherwise, the DAG Combiner may have proven that the value coming in is 1173 // either already zero or is not demanded. Check for known zero input bits. 1174 APInt NeededMask = DesiredMask & ~ActualMask; 1175 1176 APInt KnownZero, KnownOne; 1177 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1178 1179 // If all the missing bits in the or are already known to be set, match! 1180 if ((NeededMask & KnownOne) == NeededMask) 1181 return true; 1182 1183 // TODO: check to see if missing bits are just not demanded. 1184 1185 // Otherwise, this pattern doesn't match. 1186 return false; 1187} 1188 1189 1190/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1191/// by tblgen. Others should not call it. 1192void SelectionDAGISel:: 1193SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1194 std::vector<SDValue> InOps; 1195 std::swap(InOps, Ops); 1196 1197 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1198 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1199 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1200 1201 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1202 if (InOps[e-1].getValueType() == MVT::Flag) 1203 --e; // Don't process a flag operand if it is here. 1204 1205 while (i != e) { 1206 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1207 if (!InlineAsm::isMemKind(Flags)) { 1208 // Just skip over this operand, copying the operands verbatim. 1209 Ops.insert(Ops.end(), InOps.begin()+i, 1210 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1211 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1212 } else { 1213 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1214 "Memory operand with multiple values?"); 1215 // Otherwise, this is a memory operand. Ask the target to select it. 1216 std::vector<SDValue> SelOps; 1217 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1218 report_fatal_error("Could not match memory address. Inline asm" 1219 " failure!"); 1220 1221 // Add this to the output node. 1222 unsigned NewFlags = 1223 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1224 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1225 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1226 i += 2; 1227 } 1228 } 1229 1230 // Add the flag input back if present. 1231 if (e != InOps.size()) 1232 Ops.push_back(InOps.back()); 1233} 1234 1235/// findFlagUse - Return use of EVT::Flag value produced by the specified 1236/// SDNode. 1237/// 1238static SDNode *findFlagUse(SDNode *N) { 1239 unsigned FlagResNo = N->getNumValues()-1; 1240 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1241 SDUse &Use = I.getUse(); 1242 if (Use.getResNo() == FlagResNo) 1243 return Use.getUser(); 1244 } 1245 return NULL; 1246} 1247 1248/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1249/// This function recursively traverses up the operand chain, ignoring 1250/// certain nodes. 1251static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1252 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1253 bool IgnoreChains) { 1254 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1255 // greater than all of its (recursive) operands. If we scan to a point where 1256 // 'use' is smaller than the node we're scanning for, then we know we will 1257 // never find it. 1258 // 1259 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1260 // happen because we scan down to newly selected nodes in the case of flag 1261 // uses. 1262 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1263 return false; 1264 1265 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1266 // won't fail if we scan it again. 1267 if (!Visited.insert(Use)) 1268 return false; 1269 1270 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1271 // Ignore chain uses, they are validated by HandleMergeInputChains. 1272 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1273 continue; 1274 1275 SDNode *N = Use->getOperand(i).getNode(); 1276 if (N == Def) { 1277 if (Use == ImmedUse || Use == Root) 1278 continue; // We are not looking for immediate use. 1279 assert(N != Root); 1280 return true; 1281 } 1282 1283 // Traverse up the operand chain. 1284 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1285 return true; 1286 } 1287 return false; 1288} 1289 1290/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1291/// operand node N of U during instruction selection that starts at Root. 1292bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1293 SDNode *Root) const { 1294 if (OptLevel == CodeGenOpt::None) return false; 1295 return N.hasOneUse(); 1296} 1297 1298/// IsLegalToFold - Returns true if the specific operand node N of 1299/// U can be folded during instruction selection that starts at Root. 1300bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1301 CodeGenOpt::Level OptLevel, 1302 bool IgnoreChains) { 1303 if (OptLevel == CodeGenOpt::None) return false; 1304 1305 // If Root use can somehow reach N through a path that that doesn't contain 1306 // U then folding N would create a cycle. e.g. In the following 1307 // diagram, Root can reach N through X. If N is folded into into Root, then 1308 // X is both a predecessor and a successor of U. 1309 // 1310 // [N*] // 1311 // ^ ^ // 1312 // / \ // 1313 // [U*] [X]? // 1314 // ^ ^ // 1315 // \ / // 1316 // \ / // 1317 // [Root*] // 1318 // 1319 // * indicates nodes to be folded together. 1320 // 1321 // If Root produces a flag, then it gets (even more) interesting. Since it 1322 // will be "glued" together with its flag use in the scheduler, we need to 1323 // check if it might reach N. 1324 // 1325 // [N*] // 1326 // ^ ^ // 1327 // / \ // 1328 // [U*] [X]? // 1329 // ^ ^ // 1330 // \ \ // 1331 // \ | // 1332 // [Root*] | // 1333 // ^ | // 1334 // f | // 1335 // | / // 1336 // [Y] / // 1337 // ^ / // 1338 // f / // 1339 // | / // 1340 // [FU] // 1341 // 1342 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1343 // (call it Fold), then X is a predecessor of FU and a successor of 1344 // Fold. But since Fold and FU are flagged together, this will create 1345 // a cycle in the scheduling graph. 1346 1347 // If the node has flags, walk down the graph to the "lowest" node in the 1348 // flagged set. 1349 EVT VT = Root->getValueType(Root->getNumValues()-1); 1350 while (VT == MVT::Flag) { 1351 SDNode *FU = findFlagUse(Root); 1352 if (FU == NULL) 1353 break; 1354 Root = FU; 1355 VT = Root->getValueType(Root->getNumValues()-1); 1356 1357 // If our query node has a flag result with a use, we've walked up it. If 1358 // the user (which has already been selected) has a chain or indirectly uses 1359 // the chain, our WalkChainUsers predicate will not consider it. Because of 1360 // this, we cannot ignore chains in this predicate. 1361 IgnoreChains = false; 1362 } 1363 1364 1365 SmallPtrSet<SDNode*, 16> Visited; 1366 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1367} 1368 1369SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1370 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1371 SelectInlineAsmMemoryOperands(Ops); 1372 1373 std::vector<EVT> VTs; 1374 VTs.push_back(MVT::Other); 1375 VTs.push_back(MVT::Flag); 1376 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1377 VTs, &Ops[0], Ops.size()); 1378 New->setNodeId(-1); 1379 return New.getNode(); 1380} 1381 1382SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1383 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1384} 1385 1386/// GetVBR - decode a vbr encoding whose top bit is set. 1387ALWAYS_INLINE static uint64_t 1388GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1389 assert(Val >= 128 && "Not a VBR"); 1390 Val &= 127; // Remove first vbr bit. 1391 1392 unsigned Shift = 7; 1393 uint64_t NextBits; 1394 do { 1395 NextBits = MatcherTable[Idx++]; 1396 Val |= (NextBits&127) << Shift; 1397 Shift += 7; 1398 } while (NextBits & 128); 1399 1400 return Val; 1401} 1402 1403 1404/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1405/// interior flag and chain results to use the new flag and chain results. 1406void SelectionDAGISel:: 1407UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1408 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1409 SDValue InputFlag, 1410 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1411 bool isMorphNodeTo) { 1412 SmallVector<SDNode*, 4> NowDeadNodes; 1413 1414 ISelUpdater ISU(ISelPosition); 1415 1416 // Now that all the normal results are replaced, we replace the chain and 1417 // flag results if present. 1418 if (!ChainNodesMatched.empty()) { 1419 assert(InputChain.getNode() != 0 && 1420 "Matched input chains but didn't produce a chain"); 1421 // Loop over all of the nodes we matched that produced a chain result. 1422 // Replace all the chain results with the final chain we ended up with. 1423 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1424 SDNode *ChainNode = ChainNodesMatched[i]; 1425 1426 // If this node was already deleted, don't look at it. 1427 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1428 continue; 1429 1430 // Don't replace the results of the root node if we're doing a 1431 // MorphNodeTo. 1432 if (ChainNode == NodeToMatch && isMorphNodeTo) 1433 continue; 1434 1435 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1436 if (ChainVal.getValueType() == MVT::Flag) 1437 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1438 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1439 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1440 1441 // If the node became dead and we haven't already seen it, delete it. 1442 if (ChainNode->use_empty() && 1443 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1444 NowDeadNodes.push_back(ChainNode); 1445 } 1446 } 1447 1448 // If the result produces a flag, update any flag results in the matched 1449 // pattern with the flag result. 1450 if (InputFlag.getNode() != 0) { 1451 // Handle any interior nodes explicitly marked. 1452 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1453 SDNode *FRN = FlagResultNodesMatched[i]; 1454 1455 // If this node was already deleted, don't look at it. 1456 if (FRN->getOpcode() == ISD::DELETED_NODE) 1457 continue; 1458 1459 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1460 "Doesn't have a flag result"); 1461 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1462 InputFlag, &ISU); 1463 1464 // If the node became dead and we haven't already seen it, delete it. 1465 if (FRN->use_empty() && 1466 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1467 NowDeadNodes.push_back(FRN); 1468 } 1469 } 1470 1471 if (!NowDeadNodes.empty()) 1472 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1473 1474 DEBUG(errs() << "ISEL: Match complete!\n"); 1475} 1476 1477enum ChainResult { 1478 CR_Simple, 1479 CR_InducesCycle, 1480 CR_LeadsToInteriorNode 1481}; 1482 1483/// WalkChainUsers - Walk down the users of the specified chained node that is 1484/// part of the pattern we're matching, looking at all of the users we find. 1485/// This determines whether something is an interior node, whether we have a 1486/// non-pattern node in between two pattern nodes (which prevent folding because 1487/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1488/// between pattern nodes (in which case the TF becomes part of the pattern). 1489/// 1490/// The walk we do here is guaranteed to be small because we quickly get down to 1491/// already selected nodes "below" us. 1492static ChainResult 1493WalkChainUsers(SDNode *ChainedNode, 1494 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1495 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1496 ChainResult Result = CR_Simple; 1497 1498 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1499 E = ChainedNode->use_end(); UI != E; ++UI) { 1500 // Make sure the use is of the chain, not some other value we produce. 1501 if (UI.getUse().getValueType() != MVT::Other) continue; 1502 1503 SDNode *User = *UI; 1504 1505 // If we see an already-selected machine node, then we've gone beyond the 1506 // pattern that we're selecting down into the already selected chunk of the 1507 // DAG. 1508 if (User->isMachineOpcode() || 1509 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1510 continue; 1511 1512 if (User->getOpcode() == ISD::CopyToReg || 1513 User->getOpcode() == ISD::CopyFromReg || 1514 User->getOpcode() == ISD::INLINEASM || 1515 User->getOpcode() == ISD::EH_LABEL) { 1516 // If their node ID got reset to -1 then they've already been selected. 1517 // Treat them like a MachineOpcode. 1518 if (User->getNodeId() == -1) 1519 continue; 1520 } 1521 1522 // If we have a TokenFactor, we handle it specially. 1523 if (User->getOpcode() != ISD::TokenFactor) { 1524 // If the node isn't a token factor and isn't part of our pattern, then it 1525 // must be a random chained node in between two nodes we're selecting. 1526 // This happens when we have something like: 1527 // x = load ptr 1528 // call 1529 // y = x+4 1530 // store y -> ptr 1531 // Because we structurally match the load/store as a read/modify/write, 1532 // but the call is chained between them. We cannot fold in this case 1533 // because it would induce a cycle in the graph. 1534 if (!std::count(ChainedNodesInPattern.begin(), 1535 ChainedNodesInPattern.end(), User)) 1536 return CR_InducesCycle; 1537 1538 // Otherwise we found a node that is part of our pattern. For example in: 1539 // x = load ptr 1540 // y = x+4 1541 // store y -> ptr 1542 // This would happen when we're scanning down from the load and see the 1543 // store as a user. Record that there is a use of ChainedNode that is 1544 // part of the pattern and keep scanning uses. 1545 Result = CR_LeadsToInteriorNode; 1546 InteriorChainedNodes.push_back(User); 1547 continue; 1548 } 1549 1550 // If we found a TokenFactor, there are two cases to consider: first if the 1551 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1552 // uses of the TF are in our pattern) we just want to ignore it. Second, 1553 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1554 // [Load chain] 1555 // ^ 1556 // | 1557 // [Load] 1558 // ^ ^ 1559 // | \ DAG's like cheese 1560 // / \ do you? 1561 // / | 1562 // [TokenFactor] [Op] 1563 // ^ ^ 1564 // | | 1565 // \ / 1566 // \ / 1567 // [Store] 1568 // 1569 // In this case, the TokenFactor becomes part of our match and we rewrite it 1570 // as a new TokenFactor. 1571 // 1572 // To distinguish these two cases, do a recursive walk down the uses. 1573 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1574 case CR_Simple: 1575 // If the uses of the TokenFactor are just already-selected nodes, ignore 1576 // it, it is "below" our pattern. 1577 continue; 1578 case CR_InducesCycle: 1579 // If the uses of the TokenFactor lead to nodes that are not part of our 1580 // pattern that are not selected, folding would turn this into a cycle, 1581 // bail out now. 1582 return CR_InducesCycle; 1583 case CR_LeadsToInteriorNode: 1584 break; // Otherwise, keep processing. 1585 } 1586 1587 // Okay, we know we're in the interesting interior case. The TokenFactor 1588 // is now going to be considered part of the pattern so that we rewrite its 1589 // uses (it may have uses that are not part of the pattern) with the 1590 // ultimate chain result of the generated code. We will also add its chain 1591 // inputs as inputs to the ultimate TokenFactor we create. 1592 Result = CR_LeadsToInteriorNode; 1593 ChainedNodesInPattern.push_back(User); 1594 InteriorChainedNodes.push_back(User); 1595 continue; 1596 } 1597 1598 return Result; 1599} 1600 1601/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1602/// operation for when the pattern matched at least one node with a chains. The 1603/// input vector contains a list of all of the chained nodes that we match. We 1604/// must determine if this is a valid thing to cover (i.e. matching it won't 1605/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1606/// be used as the input node chain for the generated nodes. 1607static SDValue 1608HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1609 SelectionDAG *CurDAG) { 1610 // Walk all of the chained nodes we've matched, recursively scanning down the 1611 // users of the chain result. This adds any TokenFactor nodes that are caught 1612 // in between chained nodes to the chained and interior nodes list. 1613 SmallVector<SDNode*, 3> InteriorChainedNodes; 1614 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1615 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1616 InteriorChainedNodes) == CR_InducesCycle) 1617 return SDValue(); // Would induce a cycle. 1618 } 1619 1620 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1621 // that we are interested in. Form our input TokenFactor node. 1622 SmallVector<SDValue, 3> InputChains; 1623 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1624 // Add the input chain of this node to the InputChains list (which will be 1625 // the operands of the generated TokenFactor) if it's not an interior node. 1626 SDNode *N = ChainNodesMatched[i]; 1627 if (N->getOpcode() != ISD::TokenFactor) { 1628 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1629 continue; 1630 1631 // Otherwise, add the input chain. 1632 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1633 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1634 InputChains.push_back(InChain); 1635 continue; 1636 } 1637 1638 // If we have a token factor, we want to add all inputs of the token factor 1639 // that are not part of the pattern we're matching. 1640 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1641 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1642 N->getOperand(op).getNode())) 1643 InputChains.push_back(N->getOperand(op)); 1644 } 1645 } 1646 1647 SDValue Res; 1648 if (InputChains.size() == 1) 1649 return InputChains[0]; 1650 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1651 MVT::Other, &InputChains[0], InputChains.size()); 1652} 1653 1654/// MorphNode - Handle morphing a node in place for the selector. 1655SDNode *SelectionDAGISel:: 1656MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1657 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1658 // It is possible we're using MorphNodeTo to replace a node with no 1659 // normal results with one that has a normal result (or we could be 1660 // adding a chain) and the input could have flags and chains as well. 1661 // In this case we need to shift the operands down. 1662 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1663 // than the old isel though. 1664 int OldFlagResultNo = -1, OldChainResultNo = -1; 1665 1666 unsigned NTMNumResults = Node->getNumValues(); 1667 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1668 OldFlagResultNo = NTMNumResults-1; 1669 if (NTMNumResults != 1 && 1670 Node->getValueType(NTMNumResults-2) == MVT::Other) 1671 OldChainResultNo = NTMNumResults-2; 1672 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1673 OldChainResultNo = NTMNumResults-1; 1674 1675 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1676 // that this deletes operands of the old node that become dead. 1677 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1678 1679 // MorphNodeTo can operate in two ways: if an existing node with the 1680 // specified operands exists, it can just return it. Otherwise, it 1681 // updates the node in place to have the requested operands. 1682 if (Res == Node) { 1683 // If we updated the node in place, reset the node ID. To the isel, 1684 // this should be just like a newly allocated machine node. 1685 Res->setNodeId(-1); 1686 } 1687 1688 unsigned ResNumResults = Res->getNumValues(); 1689 // Move the flag if needed. 1690 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1691 (unsigned)OldFlagResultNo != ResNumResults-1) 1692 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1693 SDValue(Res, ResNumResults-1)); 1694 1695 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1696 --ResNumResults; 1697 1698 // Move the chain reference if needed. 1699 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1700 (unsigned)OldChainResultNo != ResNumResults-1) 1701 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1702 SDValue(Res, ResNumResults-1)); 1703 1704 // Otherwise, no replacement happened because the node already exists. Replace 1705 // Uses of the old node with the new one. 1706 if (Res != Node) 1707 CurDAG->ReplaceAllUsesWith(Node, Res); 1708 1709 return Res; 1710} 1711 1712/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1713ALWAYS_INLINE static bool 1714CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1715 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1716 // Accept if it is exactly the same as a previously recorded node. 1717 unsigned RecNo = MatcherTable[MatcherIndex++]; 1718 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1719 return N == RecordedNodes[RecNo]; 1720} 1721 1722/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1723ALWAYS_INLINE static bool 1724CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1725 SelectionDAGISel &SDISel) { 1726 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1727} 1728 1729/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1730ALWAYS_INLINE static bool 1731CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1732 SelectionDAGISel &SDISel, SDNode *N) { 1733 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1734} 1735 1736ALWAYS_INLINE static bool 1737CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1738 SDNode *N) { 1739 uint16_t Opc = MatcherTable[MatcherIndex++]; 1740 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1741 return N->getOpcode() == Opc; 1742} 1743 1744ALWAYS_INLINE static bool 1745CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1746 SDValue N, const TargetLowering &TLI) { 1747 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1748 if (N.getValueType() == VT) return true; 1749 1750 // Handle the case when VT is iPTR. 1751 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1752} 1753 1754ALWAYS_INLINE static bool 1755CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1756 SDValue N, const TargetLowering &TLI, 1757 unsigned ChildNo) { 1758 if (ChildNo >= N.getNumOperands()) 1759 return false; // Match fails if out of range child #. 1760 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1761} 1762 1763 1764ALWAYS_INLINE static bool 1765CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1766 SDValue N) { 1767 return cast<CondCodeSDNode>(N)->get() == 1768 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1769} 1770 1771ALWAYS_INLINE static bool 1772CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1773 SDValue N, const TargetLowering &TLI) { 1774 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1775 if (cast<VTSDNode>(N)->getVT() == VT) 1776 return true; 1777 1778 // Handle the case when VT is iPTR. 1779 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1780} 1781 1782ALWAYS_INLINE static bool 1783CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1784 SDValue N) { 1785 int64_t Val = MatcherTable[MatcherIndex++]; 1786 if (Val & 128) 1787 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1788 1789 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1790 return C != 0 && C->getSExtValue() == Val; 1791} 1792 1793ALWAYS_INLINE static bool 1794CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1795 SDValue N, SelectionDAGISel &SDISel) { 1796 int64_t Val = MatcherTable[MatcherIndex++]; 1797 if (Val & 128) 1798 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1799 1800 if (N->getOpcode() != ISD::AND) return false; 1801 1802 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1803 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1804} 1805 1806ALWAYS_INLINE static bool 1807CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1808 SDValue N, SelectionDAGISel &SDISel) { 1809 int64_t Val = MatcherTable[MatcherIndex++]; 1810 if (Val & 128) 1811 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1812 1813 if (N->getOpcode() != ISD::OR) return false; 1814 1815 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1816 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1817} 1818 1819/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1820/// scope, evaluate the current node. If the current predicate is known to 1821/// fail, set Result=true and return anything. If the current predicate is 1822/// known to pass, set Result=false and return the MatcherIndex to continue 1823/// with. If the current predicate is unknown, set Result=false and return the 1824/// MatcherIndex to continue with. 1825static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1826 unsigned Index, SDValue N, 1827 bool &Result, SelectionDAGISel &SDISel, 1828 SmallVectorImpl<SDValue> &RecordedNodes){ 1829 switch (Table[Index++]) { 1830 default: 1831 Result = false; 1832 return Index-1; // Could not evaluate this predicate. 1833 case SelectionDAGISel::OPC_CheckSame: 1834 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1835 return Index; 1836 case SelectionDAGISel::OPC_CheckPatternPredicate: 1837 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1838 return Index; 1839 case SelectionDAGISel::OPC_CheckPredicate: 1840 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1841 return Index; 1842 case SelectionDAGISel::OPC_CheckOpcode: 1843 Result = !::CheckOpcode(Table, Index, N.getNode()); 1844 return Index; 1845 case SelectionDAGISel::OPC_CheckType: 1846 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1847 return Index; 1848 case SelectionDAGISel::OPC_CheckChild0Type: 1849 case SelectionDAGISel::OPC_CheckChild1Type: 1850 case SelectionDAGISel::OPC_CheckChild2Type: 1851 case SelectionDAGISel::OPC_CheckChild3Type: 1852 case SelectionDAGISel::OPC_CheckChild4Type: 1853 case SelectionDAGISel::OPC_CheckChild5Type: 1854 case SelectionDAGISel::OPC_CheckChild6Type: 1855 case SelectionDAGISel::OPC_CheckChild7Type: 1856 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1857 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1858 return Index; 1859 case SelectionDAGISel::OPC_CheckCondCode: 1860 Result = !::CheckCondCode(Table, Index, N); 1861 return Index; 1862 case SelectionDAGISel::OPC_CheckValueType: 1863 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1864 return Index; 1865 case SelectionDAGISel::OPC_CheckInteger: 1866 Result = !::CheckInteger(Table, Index, N); 1867 return Index; 1868 case SelectionDAGISel::OPC_CheckAndImm: 1869 Result = !::CheckAndImm(Table, Index, N, SDISel); 1870 return Index; 1871 case SelectionDAGISel::OPC_CheckOrImm: 1872 Result = !::CheckOrImm(Table, Index, N, SDISel); 1873 return Index; 1874 } 1875} 1876 1877namespace { 1878 1879struct MatchScope { 1880 /// FailIndex - If this match fails, this is the index to continue with. 1881 unsigned FailIndex; 1882 1883 /// NodeStack - The node stack when the scope was formed. 1884 SmallVector<SDValue, 4> NodeStack; 1885 1886 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1887 unsigned NumRecordedNodes; 1888 1889 /// NumMatchedMemRefs - The number of matched memref entries. 1890 unsigned NumMatchedMemRefs; 1891 1892 /// InputChain/InputFlag - The current chain/flag 1893 SDValue InputChain, InputFlag; 1894 1895 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1896 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1897}; 1898 1899} 1900 1901SDNode *SelectionDAGISel:: 1902SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1903 unsigned TableSize) { 1904 // FIXME: Should these even be selected? Handle these cases in the caller? 1905 switch (NodeToMatch->getOpcode()) { 1906 default: 1907 break; 1908 case ISD::EntryToken: // These nodes remain the same. 1909 case ISD::BasicBlock: 1910 case ISD::Register: 1911 //case ISD::VALUETYPE: 1912 //case ISD::CONDCODE: 1913 case ISD::HANDLENODE: 1914 case ISD::MDNODE_SDNODE: 1915 case ISD::TargetConstant: 1916 case ISD::TargetConstantFP: 1917 case ISD::TargetConstantPool: 1918 case ISD::TargetFrameIndex: 1919 case ISD::TargetExternalSymbol: 1920 case ISD::TargetBlockAddress: 1921 case ISD::TargetJumpTable: 1922 case ISD::TargetGlobalTLSAddress: 1923 case ISD::TargetGlobalAddress: 1924 case ISD::TokenFactor: 1925 case ISD::CopyFromReg: 1926 case ISD::CopyToReg: 1927 case ISD::EH_LABEL: 1928 NodeToMatch->setNodeId(-1); // Mark selected. 1929 return 0; 1930 case ISD::AssertSext: 1931 case ISD::AssertZext: 1932 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1933 NodeToMatch->getOperand(0)); 1934 return 0; 1935 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1936 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1937 } 1938 1939 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1940 1941 // Set up the node stack with NodeToMatch as the only node on the stack. 1942 SmallVector<SDValue, 8> NodeStack; 1943 SDValue N = SDValue(NodeToMatch, 0); 1944 NodeStack.push_back(N); 1945 1946 // MatchScopes - Scopes used when matching, if a match failure happens, this 1947 // indicates where to continue checking. 1948 SmallVector<MatchScope, 8> MatchScopes; 1949 1950 // RecordedNodes - This is the set of nodes that have been recorded by the 1951 // state machine. 1952 SmallVector<SDValue, 8> RecordedNodes; 1953 1954 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1955 // pattern. 1956 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1957 1958 // These are the current input chain and flag for use when generating nodes. 1959 // Various Emit operations change these. For example, emitting a copytoreg 1960 // uses and updates these. 1961 SDValue InputChain, InputFlag; 1962 1963 // ChainNodesMatched - If a pattern matches nodes that have input/output 1964 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1965 // which ones they are. The result is captured into this list so that we can 1966 // update the chain results when the pattern is complete. 1967 SmallVector<SDNode*, 3> ChainNodesMatched; 1968 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1969 1970 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1971 NodeToMatch->dump(CurDAG); 1972 errs() << '\n'); 1973 1974 // Determine where to start the interpreter. Normally we start at opcode #0, 1975 // but if the state machine starts with an OPC_SwitchOpcode, then we 1976 // accelerate the first lookup (which is guaranteed to be hot) with the 1977 // OpcodeOffset table. 1978 unsigned MatcherIndex = 0; 1979 1980 if (!OpcodeOffset.empty()) { 1981 // Already computed the OpcodeOffset table, just index into it. 1982 if (N.getOpcode() < OpcodeOffset.size()) 1983 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1984 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1985 1986 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1987 // Otherwise, the table isn't computed, but the state machine does start 1988 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1989 // is the first time we're selecting an instruction. 1990 unsigned Idx = 1; 1991 while (1) { 1992 // Get the size of this case. 1993 unsigned CaseSize = MatcherTable[Idx++]; 1994 if (CaseSize & 128) 1995 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1996 if (CaseSize == 0) break; 1997 1998 // Get the opcode, add the index to the table. 1999 uint16_t Opc = MatcherTable[Idx++]; 2000 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2001 if (Opc >= OpcodeOffset.size()) 2002 OpcodeOffset.resize((Opc+1)*2); 2003 OpcodeOffset[Opc] = Idx; 2004 Idx += CaseSize; 2005 } 2006 2007 // Okay, do the lookup for the first opcode. 2008 if (N.getOpcode() < OpcodeOffset.size()) 2009 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2010 } 2011 2012 while (1) { 2013 assert(MatcherIndex < TableSize && "Invalid index"); 2014#ifndef NDEBUG 2015 unsigned CurrentOpcodeIndex = MatcherIndex; 2016#endif 2017 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2018 switch (Opcode) { 2019 case OPC_Scope: { 2020 // Okay, the semantics of this operation are that we should push a scope 2021 // then evaluate the first child. However, pushing a scope only to have 2022 // the first check fail (which then pops it) is inefficient. If we can 2023 // determine immediately that the first check (or first several) will 2024 // immediately fail, don't even bother pushing a scope for them. 2025 unsigned FailIndex; 2026 2027 while (1) { 2028 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2029 if (NumToSkip & 128) 2030 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2031 // Found the end of the scope with no match. 2032 if (NumToSkip == 0) { 2033 FailIndex = 0; 2034 break; 2035 } 2036 2037 FailIndex = MatcherIndex+NumToSkip; 2038 2039 unsigned MatcherIndexOfPredicate = MatcherIndex; 2040 (void)MatcherIndexOfPredicate; // silence warning. 2041 2042 // If we can't evaluate this predicate without pushing a scope (e.g. if 2043 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2044 // push the scope and evaluate the full predicate chain. 2045 bool Result; 2046 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2047 Result, *this, RecordedNodes); 2048 if (!Result) 2049 break; 2050 2051 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2052 << "index " << MatcherIndexOfPredicate 2053 << ", continuing at " << FailIndex << "\n"); 2054 ++NumDAGIselRetries; 2055 2056 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2057 // move to the next case. 2058 MatcherIndex = FailIndex; 2059 } 2060 2061 // If the whole scope failed to match, bail. 2062 if (FailIndex == 0) break; 2063 2064 // Push a MatchScope which indicates where to go if the first child fails 2065 // to match. 2066 MatchScope NewEntry; 2067 NewEntry.FailIndex = FailIndex; 2068 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2069 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2070 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2071 NewEntry.InputChain = InputChain; 2072 NewEntry.InputFlag = InputFlag; 2073 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2074 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2075 MatchScopes.push_back(NewEntry); 2076 continue; 2077 } 2078 case OPC_RecordNode: 2079 // Remember this node, it may end up being an operand in the pattern. 2080 RecordedNodes.push_back(N); 2081 continue; 2082 2083 case OPC_RecordChild0: case OPC_RecordChild1: 2084 case OPC_RecordChild2: case OPC_RecordChild3: 2085 case OPC_RecordChild4: case OPC_RecordChild5: 2086 case OPC_RecordChild6: case OPC_RecordChild7: { 2087 unsigned ChildNo = Opcode-OPC_RecordChild0; 2088 if (ChildNo >= N.getNumOperands()) 2089 break; // Match fails if out of range child #. 2090 2091 RecordedNodes.push_back(N->getOperand(ChildNo)); 2092 continue; 2093 } 2094 case OPC_RecordMemRef: 2095 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2096 continue; 2097 2098 case OPC_CaptureFlagInput: 2099 // If the current node has an input flag, capture it in InputFlag. 2100 if (N->getNumOperands() != 0 && 2101 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2102 InputFlag = N->getOperand(N->getNumOperands()-1); 2103 continue; 2104 2105 case OPC_MoveChild: { 2106 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2107 if (ChildNo >= N.getNumOperands()) 2108 break; // Match fails if out of range child #. 2109 N = N.getOperand(ChildNo); 2110 NodeStack.push_back(N); 2111 continue; 2112 } 2113 2114 case OPC_MoveParent: 2115 // Pop the current node off the NodeStack. 2116 NodeStack.pop_back(); 2117 assert(!NodeStack.empty() && "Node stack imbalance!"); 2118 N = NodeStack.back(); 2119 continue; 2120 2121 case OPC_CheckSame: 2122 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2123 continue; 2124 case OPC_CheckPatternPredicate: 2125 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2126 continue; 2127 case OPC_CheckPredicate: 2128 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2129 N.getNode())) 2130 break; 2131 continue; 2132 case OPC_CheckComplexPat: { 2133 unsigned CPNum = MatcherTable[MatcherIndex++]; 2134 unsigned RecNo = MatcherTable[MatcherIndex++]; 2135 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2136 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2137 RecordedNodes)) 2138 break; 2139 continue; 2140 } 2141 case OPC_CheckOpcode: 2142 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2143 continue; 2144 2145 case OPC_CheckType: 2146 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2147 continue; 2148 2149 case OPC_SwitchOpcode: { 2150 unsigned CurNodeOpcode = N.getOpcode(); 2151 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2152 unsigned CaseSize; 2153 while (1) { 2154 // Get the size of this case. 2155 CaseSize = MatcherTable[MatcherIndex++]; 2156 if (CaseSize & 128) 2157 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2158 if (CaseSize == 0) break; 2159 2160 uint16_t Opc = MatcherTable[MatcherIndex++]; 2161 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2162 2163 // If the opcode matches, then we will execute this case. 2164 if (CurNodeOpcode == Opc) 2165 break; 2166 2167 // Otherwise, skip over this case. 2168 MatcherIndex += CaseSize; 2169 } 2170 2171 // If no cases matched, bail out. 2172 if (CaseSize == 0) break; 2173 2174 // Otherwise, execute the case we found. 2175 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2176 << " to " << MatcherIndex << "\n"); 2177 continue; 2178 } 2179 2180 case OPC_SwitchType: { 2181 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2182 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2183 unsigned CaseSize; 2184 while (1) { 2185 // Get the size of this case. 2186 CaseSize = MatcherTable[MatcherIndex++]; 2187 if (CaseSize & 128) 2188 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2189 if (CaseSize == 0) break; 2190 2191 MVT::SimpleValueType CaseVT = 2192 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2193 if (CaseVT == MVT::iPTR) 2194 CaseVT = TLI.getPointerTy().SimpleTy; 2195 2196 // If the VT matches, then we will execute this case. 2197 if (CurNodeVT == CaseVT) 2198 break; 2199 2200 // Otherwise, skip over this case. 2201 MatcherIndex += CaseSize; 2202 } 2203 2204 // If no cases matched, bail out. 2205 if (CaseSize == 0) break; 2206 2207 // Otherwise, execute the case we found. 2208 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2209 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2210 continue; 2211 } 2212 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2213 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2214 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2215 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2216 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2217 Opcode-OPC_CheckChild0Type)) 2218 break; 2219 continue; 2220 case OPC_CheckCondCode: 2221 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2222 continue; 2223 case OPC_CheckValueType: 2224 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2225 continue; 2226 case OPC_CheckInteger: 2227 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2228 continue; 2229 case OPC_CheckAndImm: 2230 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2231 continue; 2232 case OPC_CheckOrImm: 2233 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2234 continue; 2235 2236 case OPC_CheckFoldableChainNode: { 2237 assert(NodeStack.size() != 1 && "No parent node"); 2238 // Verify that all intermediate nodes between the root and this one have 2239 // a single use. 2240 bool HasMultipleUses = false; 2241 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2242 if (!NodeStack[i].hasOneUse()) { 2243 HasMultipleUses = true; 2244 break; 2245 } 2246 if (HasMultipleUses) break; 2247 2248 // Check to see that the target thinks this is profitable to fold and that 2249 // we can fold it without inducing cycles in the graph. 2250 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2251 NodeToMatch) || 2252 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2253 NodeToMatch, OptLevel, 2254 true/*We validate our own chains*/)) 2255 break; 2256 2257 continue; 2258 } 2259 case OPC_EmitInteger: { 2260 MVT::SimpleValueType VT = 2261 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2262 int64_t Val = MatcherTable[MatcherIndex++]; 2263 if (Val & 128) 2264 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2265 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2266 continue; 2267 } 2268 case OPC_EmitRegister: { 2269 MVT::SimpleValueType VT = 2270 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2271 unsigned RegNo = MatcherTable[MatcherIndex++]; 2272 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2273 continue; 2274 } 2275 2276 case OPC_EmitConvertToTarget: { 2277 // Convert from IMM/FPIMM to target version. 2278 unsigned RecNo = MatcherTable[MatcherIndex++]; 2279 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2280 SDValue Imm = RecordedNodes[RecNo]; 2281 2282 if (Imm->getOpcode() == ISD::Constant) { 2283 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2284 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2285 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2286 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2287 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2288 } 2289 2290 RecordedNodes.push_back(Imm); 2291 continue; 2292 } 2293 2294 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2295 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2296 // These are space-optimized forms of OPC_EmitMergeInputChains. 2297 assert(InputChain.getNode() == 0 && 2298 "EmitMergeInputChains should be the first chain producing node"); 2299 assert(ChainNodesMatched.empty() && 2300 "Should only have one EmitMergeInputChains per match"); 2301 2302 // Read all of the chained nodes. 2303 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2304 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2305 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2306 2307 // FIXME: What if other value results of the node have uses not matched 2308 // by this pattern? 2309 if (ChainNodesMatched.back() != NodeToMatch && 2310 !RecordedNodes[RecNo].hasOneUse()) { 2311 ChainNodesMatched.clear(); 2312 break; 2313 } 2314 2315 // Merge the input chains if they are not intra-pattern references. 2316 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2317 2318 if (InputChain.getNode() == 0) 2319 break; // Failed to merge. 2320 continue; 2321 } 2322 2323 case OPC_EmitMergeInputChains: { 2324 assert(InputChain.getNode() == 0 && 2325 "EmitMergeInputChains should be the first chain producing node"); 2326 // This node gets a list of nodes we matched in the input that have 2327 // chains. We want to token factor all of the input chains to these nodes 2328 // together. However, if any of the input chains is actually one of the 2329 // nodes matched in this pattern, then we have an intra-match reference. 2330 // Ignore these because the newly token factored chain should not refer to 2331 // the old nodes. 2332 unsigned NumChains = MatcherTable[MatcherIndex++]; 2333 assert(NumChains != 0 && "Can't TF zero chains"); 2334 2335 assert(ChainNodesMatched.empty() && 2336 "Should only have one EmitMergeInputChains per match"); 2337 2338 // Read all of the chained nodes. 2339 for (unsigned i = 0; i != NumChains; ++i) { 2340 unsigned RecNo = MatcherTable[MatcherIndex++]; 2341 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2342 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2343 2344 // FIXME: What if other value results of the node have uses not matched 2345 // by this pattern? 2346 if (ChainNodesMatched.back() != NodeToMatch && 2347 !RecordedNodes[RecNo].hasOneUse()) { 2348 ChainNodesMatched.clear(); 2349 break; 2350 } 2351 } 2352 2353 // If the inner loop broke out, the match fails. 2354 if (ChainNodesMatched.empty()) 2355 break; 2356 2357 // Merge the input chains if they are not intra-pattern references. 2358 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2359 2360 if (InputChain.getNode() == 0) 2361 break; // Failed to merge. 2362 2363 continue; 2364 } 2365 2366 case OPC_EmitCopyToReg: { 2367 unsigned RecNo = MatcherTable[MatcherIndex++]; 2368 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2369 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2370 2371 if (InputChain.getNode() == 0) 2372 InputChain = CurDAG->getEntryNode(); 2373 2374 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2375 DestPhysReg, RecordedNodes[RecNo], 2376 InputFlag); 2377 2378 InputFlag = InputChain.getValue(1); 2379 continue; 2380 } 2381 2382 case OPC_EmitNodeXForm: { 2383 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2384 unsigned RecNo = MatcherTable[MatcherIndex++]; 2385 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2386 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2387 continue; 2388 } 2389 2390 case OPC_EmitNode: 2391 case OPC_MorphNodeTo: { 2392 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2393 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2394 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2395 // Get the result VT list. 2396 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2397 SmallVector<EVT, 4> VTs; 2398 for (unsigned i = 0; i != NumVTs; ++i) { 2399 MVT::SimpleValueType VT = 2400 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2401 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2402 VTs.push_back(VT); 2403 } 2404 2405 if (EmitNodeInfo & OPFL_Chain) 2406 VTs.push_back(MVT::Other); 2407 if (EmitNodeInfo & OPFL_FlagOutput) 2408 VTs.push_back(MVT::Flag); 2409 2410 // This is hot code, so optimize the two most common cases of 1 and 2 2411 // results. 2412 SDVTList VTList; 2413 if (VTs.size() == 1) 2414 VTList = CurDAG->getVTList(VTs[0]); 2415 else if (VTs.size() == 2) 2416 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2417 else 2418 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2419 2420 // Get the operand list. 2421 unsigned NumOps = MatcherTable[MatcherIndex++]; 2422 SmallVector<SDValue, 8> Ops; 2423 for (unsigned i = 0; i != NumOps; ++i) { 2424 unsigned RecNo = MatcherTable[MatcherIndex++]; 2425 if (RecNo & 128) 2426 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2427 2428 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2429 Ops.push_back(RecordedNodes[RecNo]); 2430 } 2431 2432 // If there are variadic operands to add, handle them now. 2433 if (EmitNodeInfo & OPFL_VariadicInfo) { 2434 // Determine the start index to copy from. 2435 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2436 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2437 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2438 "Invalid variadic node"); 2439 // Copy all of the variadic operands, not including a potential flag 2440 // input. 2441 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2442 i != e; ++i) { 2443 SDValue V = NodeToMatch->getOperand(i); 2444 if (V.getValueType() == MVT::Flag) break; 2445 Ops.push_back(V); 2446 } 2447 } 2448 2449 // If this has chain/flag inputs, add them. 2450 if (EmitNodeInfo & OPFL_Chain) 2451 Ops.push_back(InputChain); 2452 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2453 Ops.push_back(InputFlag); 2454 2455 // Create the node. 2456 SDNode *Res = 0; 2457 if (Opcode != OPC_MorphNodeTo) { 2458 // If this is a normal EmitNode command, just create the new node and 2459 // add the results to the RecordedNodes list. 2460 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2461 VTList, Ops.data(), Ops.size()); 2462 2463 // Add all the non-flag/non-chain results to the RecordedNodes list. 2464 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2465 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2466 RecordedNodes.push_back(SDValue(Res, i)); 2467 } 2468 2469 } else { 2470 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2471 EmitNodeInfo); 2472 } 2473 2474 // If the node had chain/flag results, update our notion of the current 2475 // chain and flag. 2476 if (EmitNodeInfo & OPFL_FlagOutput) { 2477 InputFlag = SDValue(Res, VTs.size()-1); 2478 if (EmitNodeInfo & OPFL_Chain) 2479 InputChain = SDValue(Res, VTs.size()-2); 2480 } else if (EmitNodeInfo & OPFL_Chain) 2481 InputChain = SDValue(Res, VTs.size()-1); 2482 2483 // If the OPFL_MemRefs flag is set on this node, slap all of the 2484 // accumulated memrefs onto it. 2485 // 2486 // FIXME: This is vastly incorrect for patterns with multiple outputs 2487 // instructions that access memory and for ComplexPatterns that match 2488 // loads. 2489 if (EmitNodeInfo & OPFL_MemRefs) { 2490 MachineSDNode::mmo_iterator MemRefs = 2491 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2492 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2493 cast<MachineSDNode>(Res) 2494 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2495 } 2496 2497 DEBUG(errs() << " " 2498 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2499 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2500 2501 // If this was a MorphNodeTo then we're completely done! 2502 if (Opcode == OPC_MorphNodeTo) { 2503 // Update chain and flag uses. 2504 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2505 InputFlag, FlagResultNodesMatched, true); 2506 return Res; 2507 } 2508 2509 continue; 2510 } 2511 2512 case OPC_MarkFlagResults: { 2513 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2514 2515 // Read and remember all the flag-result nodes. 2516 for (unsigned i = 0; i != NumNodes; ++i) { 2517 unsigned RecNo = MatcherTable[MatcherIndex++]; 2518 if (RecNo & 128) 2519 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2520 2521 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2522 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2523 } 2524 continue; 2525 } 2526 2527 case OPC_CompleteMatch: { 2528 // The match has been completed, and any new nodes (if any) have been 2529 // created. Patch up references to the matched dag to use the newly 2530 // created nodes. 2531 unsigned NumResults = MatcherTable[MatcherIndex++]; 2532 2533 for (unsigned i = 0; i != NumResults; ++i) { 2534 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2535 if (ResSlot & 128) 2536 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2537 2538 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2539 SDValue Res = RecordedNodes[ResSlot]; 2540 2541 assert(i < NodeToMatch->getNumValues() && 2542 NodeToMatch->getValueType(i) != MVT::Other && 2543 NodeToMatch->getValueType(i) != MVT::Flag && 2544 "Invalid number of results to complete!"); 2545 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2546 NodeToMatch->getValueType(i) == MVT::iPTR || 2547 Res.getValueType() == MVT::iPTR || 2548 NodeToMatch->getValueType(i).getSizeInBits() == 2549 Res.getValueType().getSizeInBits()) && 2550 "invalid replacement"); 2551 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2552 } 2553 2554 // If the root node defines a flag, add it to the flag nodes to update 2555 // list. 2556 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2557 FlagResultNodesMatched.push_back(NodeToMatch); 2558 2559 // Update chain and flag uses. 2560 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2561 InputFlag, FlagResultNodesMatched, false); 2562 2563 assert(NodeToMatch->use_empty() && 2564 "Didn't replace all uses of the node?"); 2565 2566 // FIXME: We just return here, which interacts correctly with SelectRoot 2567 // above. We should fix this to not return an SDNode* anymore. 2568 return 0; 2569 } 2570 } 2571 2572 // If the code reached this point, then the match failed. See if there is 2573 // another child to try in the current 'Scope', otherwise pop it until we 2574 // find a case to check. 2575 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2576 ++NumDAGIselRetries; 2577 while (1) { 2578 if (MatchScopes.empty()) { 2579 CannotYetSelect(NodeToMatch); 2580 return 0; 2581 } 2582 2583 // Restore the interpreter state back to the point where the scope was 2584 // formed. 2585 MatchScope &LastScope = MatchScopes.back(); 2586 RecordedNodes.resize(LastScope.NumRecordedNodes); 2587 NodeStack.clear(); 2588 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2589 N = NodeStack.back(); 2590 2591 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2592 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2593 MatcherIndex = LastScope.FailIndex; 2594 2595 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2596 2597 InputChain = LastScope.InputChain; 2598 InputFlag = LastScope.InputFlag; 2599 if (!LastScope.HasChainNodesMatched) 2600 ChainNodesMatched.clear(); 2601 if (!LastScope.HasFlagResultNodesMatched) 2602 FlagResultNodesMatched.clear(); 2603 2604 // Check to see what the offset is at the new MatcherIndex. If it is zero 2605 // we have reached the end of this scope, otherwise we have another child 2606 // in the current scope to try. 2607 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2608 if (NumToSkip & 128) 2609 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2610 2611 // If we have another child in this scope to match, update FailIndex and 2612 // try it. 2613 if (NumToSkip != 0) { 2614 LastScope.FailIndex = MatcherIndex+NumToSkip; 2615 break; 2616 } 2617 2618 // End of this scope, pop it and try the next child in the containing 2619 // scope. 2620 MatchScopes.pop_back(); 2621 } 2622 } 2623} 2624 2625 2626 2627void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2628 std::string msg; 2629 raw_string_ostream Msg(msg); 2630 Msg << "Cannot yet select: "; 2631 2632 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2633 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2634 N->getOpcode() != ISD::INTRINSIC_VOID) { 2635 N->printrFull(Msg, CurDAG); 2636 } else { 2637 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2638 unsigned iid = 2639 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2640 if (iid < Intrinsic::num_intrinsics) 2641 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2642 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2643 Msg << "target intrinsic %" << TII->getName(iid); 2644 else 2645 Msg << "unknown intrinsic #" << iid; 2646 } 2647 report_fatal_error(Msg.str()); 2648} 2649 2650char SelectionDAGISel::ID = 0; 2651