SelectionDAGISel.cpp revision d38e97f8f5604a6e487633e94b489647c49ad733
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineJumpTableInfo.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/CodeGen/DwarfWriter.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Target/TargetData.h" 43#include "llvm/Target/TargetFrameInfo.h" 44#include "llvm/Target/TargetInstrInfo.h" 45#include "llvm/Target/TargetLowering.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Target/TargetOptions.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/Timer.h" 52#include <algorithm> 53using namespace llvm; 54 55static cl::opt<bool> 56DisableLegalizeTypes("disable-legalize-types", cl::Hidden); 57#ifndef NDEBUG 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65#else 66static const bool EnableFastISelVerbose = false, 67 EnableFastISelAbort = false; 68#endif 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 bool Fast) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (Fast) 143 return createFastDAGScheduler(IS, Fast); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, Fast); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, Fast); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and the scheduler passes ownership of it to this method. 157MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 158 MachineBasicBlock *MBB) const { 159 cerr << "If a target marks an instruction with " 160 << "'usesCustomDAGSchedInserter', it must implement " 161 << "TargetLowering::EmitInstrWithCustomInserter!\n"; 162 abort(); 163 return 0; 164} 165 166/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 167/// physical register has only a single copy use, then coalesced the copy 168/// if possible. 169static void EmitLiveInCopy(MachineBasicBlock *MBB, 170 MachineBasicBlock::iterator &InsertPos, 171 unsigned VirtReg, unsigned PhysReg, 172 const TargetRegisterClass *RC, 173 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 174 const MachineRegisterInfo &MRI, 175 const TargetRegisterInfo &TRI, 176 const TargetInstrInfo &TII) { 177 unsigned NumUses = 0; 178 MachineInstr *UseMI = NULL; 179 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 180 UE = MRI.use_end(); UI != UE; ++UI) { 181 UseMI = &*UI; 182 if (++NumUses > 1) 183 break; 184 } 185 186 // If the number of uses is not one, or the use is not a move instruction, 187 // don't coalesce. Also, only coalesce away a virtual register to virtual 188 // register copy. 189 bool Coalesced = false; 190 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 191 if (NumUses == 1 && 192 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 193 TargetRegisterInfo::isVirtualRegister(DstReg)) { 194 VirtReg = DstReg; 195 Coalesced = true; 196 } 197 198 // Now find an ideal location to insert the copy. 199 MachineBasicBlock::iterator Pos = InsertPos; 200 while (Pos != MBB->begin()) { 201 MachineInstr *PrevMI = prior(Pos); 202 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 203 // copyRegToReg might emit multiple instructions to do a copy. 204 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 205 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 206 // This is what the BB looks like right now: 207 // r1024 = mov r0 208 // ... 209 // r1 = mov r1024 210 // 211 // We want to insert "r1025 = mov r1". Inserting this copy below the 212 // move to r1024 makes it impossible for that move to be coalesced. 213 // 214 // r1025 = mov r1 215 // r1024 = mov r0 216 // ... 217 // r1 = mov 1024 218 // r2 = mov 1025 219 break; // Woot! Found a good location. 220 --Pos; 221 } 222 223 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 224 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 225 if (Coalesced) { 226 if (&*InsertPos == UseMI) ++InsertPos; 227 MBB->erase(UseMI); 228 } 229} 230 231/// EmitLiveInCopies - If this is the first basic block in the function, 232/// and if it has live ins that need to be copied into vregs, emit the 233/// copies into the block. 234static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 235 const MachineRegisterInfo &MRI, 236 const TargetRegisterInfo &TRI, 237 const TargetInstrInfo &TII) { 238 if (SchedLiveInCopies) { 239 // Emit the copies at a heuristically-determined location in the block. 240 DenseMap<MachineInstr*, unsigned> CopyRegMap; 241 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 242 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 243 E = MRI.livein_end(); LI != E; ++LI) 244 if (LI->second) { 245 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 246 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 247 RC, CopyRegMap, MRI, TRI, TII); 248 } 249 } else { 250 // Emit the copies into the top of the block. 251 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 252 E = MRI.livein_end(); LI != E; ++LI) 253 if (LI->second) { 254 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 255 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 256 LI->second, LI->first, RC, RC); 257 } 258 } 259} 260 261//===----------------------------------------------------------------------===// 262// SelectionDAGISel code 263//===----------------------------------------------------------------------===// 264 265SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) : 266 FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 267 FuncInfo(new FunctionLoweringInfo(TLI)), 268 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 269 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)), 270 GFI(), 271 Fast(fast), 272 DAGSize(0) 273{} 274 275SelectionDAGISel::~SelectionDAGISel() { 276 delete SDL; 277 delete CurDAG; 278 delete FuncInfo; 279} 280 281unsigned SelectionDAGISel::MakeReg(MVT VT) { 282 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 283} 284 285void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 286 AU.addRequired<AliasAnalysis>(); 287 AU.addRequired<GCModuleInfo>(); 288 AU.addRequired<DwarfWriter>(); 289 AU.setPreservesAll(); 290} 291 292bool SelectionDAGISel::runOnFunction(Function &Fn) { 293 // Do some sanity-checking on the command-line options. 294 assert((!EnableFastISelVerbose || EnableFastISel) && 295 "-fast-isel-verbose requires -fast-isel"); 296 assert((!EnableFastISelAbort || EnableFastISel) && 297 "-fast-isel-abort requires -fast-isel"); 298 299 // Get alias analysis for load/store combining. 300 AA = &getAnalysis<AliasAnalysis>(); 301 302 TargetMachine &TM = TLI.getTargetMachine(); 303 MF = &MachineFunction::construct(&Fn, TM); 304 const TargetInstrInfo &TII = *TM.getInstrInfo(); 305 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 306 307 if (MF->getFunction()->hasGC()) 308 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction()); 309 else 310 GFI = 0; 311 RegInfo = &MF->getRegInfo(); 312 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 313 314 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 315 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 316 CurDAG->init(*MF, MMI, DW); 317 FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); 318 SDL->init(GFI, *AA); 319 320 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 321 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 322 // Mark landing pad. 323 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 324 325 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 326 327 // If the first basic block in the function has live ins that need to be 328 // copied into vregs, emit the copies into the top of the block before 329 // emitting the code for the block. 330 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 331 332 // Add function live-ins to entry block live-in set. 333 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 334 E = RegInfo->livein_end(); I != E; ++I) 335 MF->begin()->addLiveIn(I->first); 336 337#ifndef NDEBUG 338 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 339 "Not all catch info was assigned to a landing pad!"); 340#endif 341 342 FuncInfo->clear(); 343 344 return true; 345} 346 347static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 348 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 349 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 350 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 351 // Apply the catch info to DestBB. 352 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 353#ifndef NDEBUG 354 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 355 FLI.CatchInfoFound.insert(EHSel); 356#endif 357 } 358} 359 360/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and 361/// whether object offset >= 0. 362static bool 363IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) { 364 if (!isa<FrameIndexSDNode>(Op)) return false; 365 366 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op); 367 int FrameIdx = FrameIdxNode->getIndex(); 368 return MFI->isFixedObjectIndex(FrameIdx) && 369 MFI->getObjectOffset(FrameIdx) >= 0; 370} 371 372/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 373/// possibly be overwritten when lowering the outgoing arguments in a tail 374/// call. Currently the implementation of this call is very conservative and 375/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 376/// virtual registers would be overwritten by direct lowering. 377static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op, 378 MachineFrameInfo *MFI) { 379 RegisterSDNode * OpReg = NULL; 380 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 381 (Op.getOpcode()== ISD::CopyFromReg && 382 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 383 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 384 (Op.getOpcode() == ISD::LOAD && 385 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) || 386 (Op.getOpcode() == ISD::MERGE_VALUES && 387 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD && 388 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()). 389 getOperand(1)))) 390 return true; 391 return false; 392} 393 394/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 395/// DAG and fixes their tailcall attribute operand. 396static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 397 const TargetLowering& TLI) { 398 SDNode * Ret = NULL; 399 SDValue Terminator = DAG.getRoot(); 400 401 // Find RET node. 402 if (Terminator.getOpcode() == ISD::RET) { 403 Ret = Terminator.getNode(); 404 } 405 406 // Fix tail call attribute of CALL nodes. 407 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 408 BI = DAG.allnodes_end(); BI != BE; ) { 409 --BI; 410 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) { 411 SDValue OpRet(Ret, 0); 412 SDValue OpCall(BI, 0); 413 bool isMarkedTailCall = TheCall->isTailCall(); 414 // If CALL node has tail call attribute set to true and the call is not 415 // eligible (no RET or the target rejects) the attribute is fixed to 416 // false. The TargetLowering::IsEligibleForTailCallOptimization function 417 // must correctly identify tail call optimizable calls. 418 if (!isMarkedTailCall) continue; 419 if (Ret==NULL || 420 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) { 421 // Not eligible. Mark CALL node as non tail call. Note that we 422 // can modify the call node in place since calls are not CSE'd. 423 TheCall->setNotTailCall(); 424 } else { 425 // Look for tail call clobbered arguments. Emit a series of 426 // copyto/copyfrom virtual register nodes to protect them. 427 SmallVector<SDValue, 32> Ops; 428 SDValue Chain = TheCall->getChain(), InFlag; 429 Ops.push_back(Chain); 430 Ops.push_back(TheCall->getCallee()); 431 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 432 SDValue Arg = TheCall->getArg(i); 433 bool isByVal = TheCall->getArgFlags(i).isByVal(); 434 MachineFunction &MF = DAG.getMachineFunction(); 435 MachineFrameInfo *MFI = MF.getFrameInfo(); 436 if (!isByVal && 437 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 438 MVT VT = Arg.getValueType(); 439 unsigned VReg = MF.getRegInfo(). 440 createVirtualRegister(TLI.getRegClassFor(VT)); 441 Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(), 442 VReg, Arg, InFlag); 443 InFlag = Chain.getValue(1); 444 Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(), 445 VReg, VT, InFlag); 446 Chain = Arg.getValue(1); 447 InFlag = Arg.getValue(2); 448 } 449 Ops.push_back(Arg); 450 Ops.push_back(TheCall->getArgFlagsVal(i)); 451 } 452 // Link in chain of CopyTo/CopyFromReg. 453 Ops[0] = Chain; 454 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 455 } 456 } 457 } 458} 459 460void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 461 BasicBlock::iterator Begin, 462 BasicBlock::iterator End) { 463 SDL->setCurrentBasicBlock(BB); 464 465 // Lower all of the non-terminator instructions. 466 for (BasicBlock::iterator I = Begin; I != End; ++I) 467 if (!isa<TerminatorInst>(I)) 468 SDL->visit(*I); 469 470 // Ensure that all instructions which are used outside of their defining 471 // blocks are available as virtual registers. Invoke is handled elsewhere. 472 for (BasicBlock::iterator I = Begin; I != End; ++I) 473 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 474 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I); 475 if (VMI != FuncInfo->ValueMap.end()) 476 SDL->CopyValueToVirtualRegister(I, VMI->second); 477 } 478 479 // Handle PHI nodes in successor blocks. 480 if (End == LLVMBB->end()) { 481 HandlePHINodesInSuccessorBlocks(LLVMBB); 482 483 // Lower the terminator after the copies are emitted. 484 SDL->visit(*LLVMBB->getTerminator()); 485 } 486 487 // Make sure the root of the DAG is up-to-date. 488 CurDAG->setRoot(SDL->getControlRoot()); 489 490 // Check whether calls in this block are real tail calls. Fix up CALL nodes 491 // with correct tailcall attribute so that the target can rely on the tailcall 492 // attribute indicating whether the call is really eligible for tail call 493 // optimization. 494 if (PerformTailCallOpt) 495 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI); 496 497 // Final step, emit the lowered DAG as machine code. 498 CodeGenAndEmitDAG(); 499 SDL->clear(); 500} 501 502void SelectionDAGISel::ComputeLiveOutVRegInfo() { 503 SmallPtrSet<SDNode*, 128> VisitedNodes; 504 SmallVector<SDNode*, 128> Worklist; 505 506 Worklist.push_back(CurDAG->getRoot().getNode()); 507 508 APInt Mask; 509 APInt KnownZero; 510 APInt KnownOne; 511 512 while (!Worklist.empty()) { 513 SDNode *N = Worklist.back(); 514 Worklist.pop_back(); 515 516 // If we've already seen this node, ignore it. 517 if (!VisitedNodes.insert(N)) 518 continue; 519 520 // Otherwise, add all chain operands to the worklist. 521 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 522 if (N->getOperand(i).getValueType() == MVT::Other) 523 Worklist.push_back(N->getOperand(i).getNode()); 524 525 // If this is a CopyToReg with a vreg dest, process it. 526 if (N->getOpcode() != ISD::CopyToReg) 527 continue; 528 529 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 530 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 531 continue; 532 533 // Ignore non-scalar or non-integer values. 534 SDValue Src = N->getOperand(2); 535 MVT SrcVT = Src.getValueType(); 536 if (!SrcVT.isInteger() || SrcVT.isVector()) 537 continue; 538 539 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 540 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 541 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 542 543 // Only install this information if it tells us something. 544 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 545 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 546 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo(); 547 if (DestReg >= FLI.LiveOutRegInfo.size()) 548 FLI.LiveOutRegInfo.resize(DestReg+1); 549 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg]; 550 LOI.NumSignBits = NumSignBits; 551 LOI.KnownOne = KnownOne; 552 LOI.KnownZero = KnownZero; 553 } 554 } 555} 556 557void SelectionDAGISel::CodeGenAndEmitDAG() { 558 std::string GroupName; 559 if (TimePassesIsEnabled) 560 GroupName = "Instruction Selection and Scheduling"; 561 std::string BlockName; 562 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 563 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 564 ViewSUnitDAGs) 565 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' + 566 BB->getBasicBlock()->getName(); 567 568 DOUT << "Initial selection DAG:\n"; 569 DEBUG(CurDAG->dump()); 570 571 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 572 573 // Run the DAG combiner in pre-legalize mode. 574 if (TimePassesIsEnabled) { 575 NamedRegionTimer T("DAG Combining 1", GroupName); 576 CurDAG->Combine(Unrestricted, *AA, Fast); 577 } else { 578 CurDAG->Combine(Unrestricted, *AA, Fast); 579 } 580 581 DOUT << "Optimized lowered selection DAG:\n"; 582 DEBUG(CurDAG->dump()); 583 584 // Second step, hack on the DAG until it only uses operations and types that 585 // the target supports. 586 if (!DisableLegalizeTypes) { 587 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 588 BlockName); 589 590 bool Changed; 591 if (TimePassesIsEnabled) { 592 NamedRegionTimer T("Type Legalization", GroupName); 593 Changed = CurDAG->LegalizeTypes(); 594 } else { 595 Changed = CurDAG->LegalizeTypes(); 596 } 597 598 DOUT << "Type-legalized selection DAG:\n"; 599 DEBUG(CurDAG->dump()); 600 601 if (Changed) { 602 if (ViewDAGCombineLT) 603 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 604 605 // Run the DAG combiner in post-type-legalize mode. 606 if (TimePassesIsEnabled) { 607 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 608 CurDAG->Combine(NoIllegalTypes, *AA, Fast); 609 } else { 610 CurDAG->Combine(NoIllegalTypes, *AA, Fast); 611 } 612 613 DOUT << "Optimized type-legalized selection DAG:\n"; 614 DEBUG(CurDAG->dump()); 615 } 616 } 617 618 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 619 620 if (TimePassesIsEnabled) { 621 NamedRegionTimer T("DAG Legalization", GroupName); 622 CurDAG->Legalize(DisableLegalizeTypes, Fast); 623 } else { 624 CurDAG->Legalize(DisableLegalizeTypes, Fast); 625 } 626 627 DOUT << "Legalized selection DAG:\n"; 628 DEBUG(CurDAG->dump()); 629 630 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 631 632 // Run the DAG combiner in post-legalize mode. 633 if (TimePassesIsEnabled) { 634 NamedRegionTimer T("DAG Combining 2", GroupName); 635 CurDAG->Combine(NoIllegalOperations, *AA, Fast); 636 } else { 637 CurDAG->Combine(NoIllegalOperations, *AA, Fast); 638 } 639 640 DOUT << "Optimized legalized selection DAG:\n"; 641 DEBUG(CurDAG->dump()); 642 643 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 644 645 if (!Fast) 646 ComputeLiveOutVRegInfo(); 647 648 // Third, instruction select all of the operations to machine code, adding the 649 // code to the MachineBasicBlock. 650 if (TimePassesIsEnabled) { 651 NamedRegionTimer T("Instruction Selection", GroupName); 652 InstructionSelect(); 653 } else { 654 InstructionSelect(); 655 } 656 657 DOUT << "Selected selection DAG:\n"; 658 DEBUG(CurDAG->dump()); 659 660 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 661 662 // Schedule machine code. 663 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 664 if (TimePassesIsEnabled) { 665 NamedRegionTimer T("Instruction Scheduling", GroupName); 666 Scheduler->Run(CurDAG, BB, BB->end()); 667 } else { 668 Scheduler->Run(CurDAG, BB, BB->end()); 669 } 670 671 if (ViewSUnitDAGs) Scheduler->viewGraph(); 672 673 // Emit machine code to BB. This can change 'BB' to the last block being 674 // inserted into. 675 if (TimePassesIsEnabled) { 676 NamedRegionTimer T("Instruction Creation", GroupName); 677 BB = Scheduler->EmitSchedule(); 678 } else { 679 BB = Scheduler->EmitSchedule(); 680 } 681 682 // Free the scheduler state. 683 if (TimePassesIsEnabled) { 684 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 685 delete Scheduler; 686 } else { 687 delete Scheduler; 688 } 689 690 DOUT << "Selected machine code:\n"; 691 DEBUG(BB->dump()); 692} 693 694void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 695 MachineFunction &MF, 696 MachineModuleInfo *MMI, 697 DwarfWriter *DW, 698 const TargetInstrInfo &TII) { 699 // Initialize the Fast-ISel state, if needed. 700 FastISel *FastIS = 0; 701 if (EnableFastISel) 702 FastIS = TLI.createFastISel(MF, MMI, DW, 703 FuncInfo->ValueMap, 704 FuncInfo->MBBMap, 705 FuncInfo->StaticAllocaMap 706#ifndef NDEBUG 707 , FuncInfo->CatchInfoLost 708#endif 709 ); 710 711 // Iterate over all basic blocks in the function. 712 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 713 BasicBlock *LLVMBB = &*I; 714 BB = FuncInfo->MBBMap[LLVMBB]; 715 716 BasicBlock::iterator const Begin = LLVMBB->begin(); 717 BasicBlock::iterator const End = LLVMBB->end(); 718 BasicBlock::iterator BI = Begin; 719 720 // Lower any arguments needed in this block if this is the entry block. 721 bool SuppressFastISel = false; 722 if (LLVMBB == &Fn.getEntryBlock()) { 723 LowerArguments(LLVMBB); 724 725 // If any of the arguments has the byval attribute, forgo 726 // fast-isel in the entry block. 727 if (FastIS) { 728 unsigned j = 1; 729 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 730 I != E; ++I, ++j) 731 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 732 if (EnableFastISelVerbose || EnableFastISelAbort) 733 cerr << "FastISel skips entry block due to byval argument\n"; 734 SuppressFastISel = true; 735 break; 736 } 737 } 738 } 739 740 if (MMI && BB->isLandingPad()) { 741 // Add a label to mark the beginning of the landing pad. Deletion of the 742 // landing pad can thus be detected via the MachineModuleInfo. 743 unsigned LabelID = MMI->addLandingPad(BB); 744 745 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 746 BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID); 747 748 // Mark exception register as live in. 749 unsigned Reg = TLI.getExceptionAddressRegister(); 750 if (Reg) BB->addLiveIn(Reg); 751 752 // Mark exception selector register as live in. 753 Reg = TLI.getExceptionSelectorRegister(); 754 if (Reg) BB->addLiveIn(Reg); 755 756 // FIXME: Hack around an exception handling flaw (PR1508): the personality 757 // function and list of typeids logically belong to the invoke (or, if you 758 // like, the basic block containing the invoke), and need to be associated 759 // with it in the dwarf exception handling tables. Currently however the 760 // information is provided by an intrinsic (eh.selector) that can be moved 761 // to unexpected places by the optimizers: if the unwind edge is critical, 762 // then breaking it can result in the intrinsics being in the successor of 763 // the landing pad, not the landing pad itself. This results in exceptions 764 // not being caught because no typeids are associated with the invoke. 765 // This may not be the only way things can go wrong, but it is the only way 766 // we try to work around for the moment. 767 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 768 769 if (Br && Br->isUnconditional()) { // Critical edge? 770 BasicBlock::iterator I, E; 771 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 772 if (isa<EHSelectorInst>(I)) 773 break; 774 775 if (I == E) 776 // No catch info found - try to extract some from the successor. 777 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 778 } 779 } 780 781 // Before doing SelectionDAG ISel, see if FastISel has been requested. 782 if (FastIS && !SuppressFastISel) { 783 // Emit code for any incoming arguments. This must happen before 784 // beginning FastISel on the entry block. 785 if (LLVMBB == &Fn.getEntryBlock()) { 786 CurDAG->setRoot(SDL->getControlRoot()); 787 CodeGenAndEmitDAG(); 788 SDL->clear(); 789 } 790 FastIS->startNewBlock(BB); 791 // Do FastISel on as many instructions as possible. 792 for (; BI != End; ++BI) { 793 // Just before the terminator instruction, insert instructions to 794 // feed PHI nodes in successor blocks. 795 if (isa<TerminatorInst>(BI)) 796 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 797 if (EnableFastISelVerbose || EnableFastISelAbort) { 798 cerr << "FastISel miss: "; 799 BI->dump(); 800 } 801 if (EnableFastISelAbort) 802 assert(0 && "FastISel didn't handle a PHI in a successor"); 803 break; 804 } 805 806 // First try normal tablegen-generated "fast" selection. 807 if (FastIS->SelectInstruction(BI)) 808 continue; 809 810 // Next, try calling the target to attempt to handle the instruction. 811 if (FastIS->TargetSelectInstruction(BI)) 812 continue; 813 814 // Then handle certain instructions as single-LLVM-Instruction blocks. 815 if (isa<CallInst>(BI)) { 816 if (EnableFastISelVerbose || EnableFastISelAbort) { 817 cerr << "FastISel missed call: "; 818 BI->dump(); 819 } 820 821 if (BI->getType() != Type::VoidTy) { 822 unsigned &R = FuncInfo->ValueMap[BI]; 823 if (!R) 824 R = FuncInfo->CreateRegForValue(BI); 825 } 826 827 SelectBasicBlock(LLVMBB, BI, next(BI)); 828 // If the instruction was codegen'd with multiple blocks, 829 // inform the FastISel object where to resume inserting. 830 FastIS->setCurrentBlock(BB); 831 continue; 832 } 833 834 // Otherwise, give up on FastISel for the rest of the block. 835 // For now, be a little lenient about non-branch terminators. 836 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 837 if (EnableFastISelVerbose || EnableFastISelAbort) { 838 cerr << "FastISel miss: "; 839 BI->dump(); 840 } 841 if (EnableFastISelAbort) 842 // The "fast" selector couldn't handle something and bailed. 843 // For the purpose of debugging, just abort. 844 assert(0 && "FastISel didn't select the entire block"); 845 } 846 break; 847 } 848 } 849 850 // Run SelectionDAG instruction selection on the remainder of the block 851 // not handled by FastISel. If FastISel is not run, this is the entire 852 // block. 853 if (BI != End) 854 SelectBasicBlock(LLVMBB, BI, End); 855 856 FinishBasicBlock(); 857 } 858 859 delete FastIS; 860} 861 862void 863SelectionDAGISel::FinishBasicBlock() { 864 865 DOUT << "Target-post-processed machine code:\n"; 866 DEBUG(BB->dump()); 867 868 DOUT << "Total amount of phi nodes to update: " 869 << SDL->PHINodesToUpdate.size() << "\n"; 870 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 871 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 872 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 873 874 // Next, now that we know what the last MBB the LLVM BB expanded is, update 875 // PHI nodes in successors. 876 if (SDL->SwitchCases.empty() && 877 SDL->JTCases.empty() && 878 SDL->BitTestCases.empty()) { 879 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 880 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 881 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 882 "This is not a machine PHI node that we are updating!"); 883 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 884 false)); 885 PHI->addOperand(MachineOperand::CreateMBB(BB)); 886 } 887 SDL->PHINodesToUpdate.clear(); 888 return; 889 } 890 891 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 892 // Lower header first, if it wasn't already lowered 893 if (!SDL->BitTestCases[i].Emitted) { 894 // Set the current basic block to the mbb we wish to insert the code into 895 BB = SDL->BitTestCases[i].Parent; 896 SDL->setCurrentBasicBlock(BB); 897 // Emit the code 898 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 899 CurDAG->setRoot(SDL->getRoot()); 900 CodeGenAndEmitDAG(); 901 SDL->clear(); 902 } 903 904 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 905 // Set the current basic block to the mbb we wish to insert the code into 906 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 907 SDL->setCurrentBasicBlock(BB); 908 // Emit the code 909 if (j+1 != ej) 910 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 911 SDL->BitTestCases[i].Reg, 912 SDL->BitTestCases[i].Cases[j]); 913 else 914 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 915 SDL->BitTestCases[i].Reg, 916 SDL->BitTestCases[i].Cases[j]); 917 918 919 CurDAG->setRoot(SDL->getRoot()); 920 CodeGenAndEmitDAG(); 921 SDL->clear(); 922 } 923 924 // Update PHI Nodes 925 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 926 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 927 MachineBasicBlock *PHIBB = PHI->getParent(); 928 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 929 "This is not a machine PHI node that we are updating!"); 930 // This is "default" BB. We have two jumps to it. From "header" BB and 931 // from last "case" BB. 932 if (PHIBB == SDL->BitTestCases[i].Default) { 933 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 934 false)); 935 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 936 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 937 false)); 938 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 939 back().ThisBB)); 940 } 941 // One of "cases" BB. 942 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 943 j != ej; ++j) { 944 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 945 if (cBB->succ_end() != 946 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 947 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 948 false)); 949 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 950 } 951 } 952 } 953 } 954 SDL->BitTestCases.clear(); 955 956 // If the JumpTable record is filled in, then we need to emit a jump table. 957 // Updating the PHI nodes is tricky in this case, since we need to determine 958 // whether the PHI is a successor of the range check MBB or the jump table MBB 959 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 960 // Lower header first, if it wasn't already lowered 961 if (!SDL->JTCases[i].first.Emitted) { 962 // Set the current basic block to the mbb we wish to insert the code into 963 BB = SDL->JTCases[i].first.HeaderBB; 964 SDL->setCurrentBasicBlock(BB); 965 // Emit the code 966 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 967 CurDAG->setRoot(SDL->getRoot()); 968 CodeGenAndEmitDAG(); 969 SDL->clear(); 970 } 971 972 // Set the current basic block to the mbb we wish to insert the code into 973 BB = SDL->JTCases[i].second.MBB; 974 SDL->setCurrentBasicBlock(BB); 975 // Emit the code 976 SDL->visitJumpTable(SDL->JTCases[i].second); 977 CurDAG->setRoot(SDL->getRoot()); 978 CodeGenAndEmitDAG(); 979 SDL->clear(); 980 981 // Update PHI Nodes 982 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 983 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 984 MachineBasicBlock *PHIBB = PHI->getParent(); 985 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 986 "This is not a machine PHI node that we are updating!"); 987 // "default" BB. We can go there only from header BB. 988 if (PHIBB == SDL->JTCases[i].second.Default) { 989 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 990 false)); 991 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 992 } 993 // JT BB. Just iterate over successors here 994 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 995 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 996 false)); 997 PHI->addOperand(MachineOperand::CreateMBB(BB)); 998 } 999 } 1000 } 1001 SDL->JTCases.clear(); 1002 1003 // If the switch block involved a branch to one of the actual successors, we 1004 // need to update PHI nodes in that block. 1005 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 1006 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 1007 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1008 "This is not a machine PHI node that we are updating!"); 1009 if (BB->isSuccessor(PHI->getParent())) { 1010 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 1011 false)); 1012 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1013 } 1014 } 1015 1016 // If we generated any switch lowering information, build and codegen any 1017 // additional DAGs necessary. 1018 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 1019 // Set the current basic block to the mbb we wish to insert the code into 1020 BB = SDL->SwitchCases[i].ThisBB; 1021 SDL->setCurrentBasicBlock(BB); 1022 1023 // Emit the code 1024 SDL->visitSwitchCase(SDL->SwitchCases[i]); 1025 CurDAG->setRoot(SDL->getRoot()); 1026 CodeGenAndEmitDAG(); 1027 SDL->clear(); 1028 1029 // Handle any PHI nodes in successors of this chunk, as if we were coming 1030 // from the original BB before switch expansion. Note that PHI nodes can 1031 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1032 // handle them the right number of times. 1033 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1034 for (MachineBasicBlock::iterator Phi = BB->begin(); 1035 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 1036 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 1037 for (unsigned pn = 0; ; ++pn) { 1038 assert(pn != SDL->PHINodesToUpdate.size() && 1039 "Didn't find PHI entry!"); 1040 if (SDL->PHINodesToUpdate[pn].first == Phi) { 1041 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 1042 second, false)); 1043 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 1044 break; 1045 } 1046 } 1047 } 1048 1049 // Don't process RHS if same block as LHS. 1050 if (BB == SDL->SwitchCases[i].FalseBB) 1051 SDL->SwitchCases[i].FalseBB = 0; 1052 1053 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1054 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 1055 SDL->SwitchCases[i].FalseBB = 0; 1056 } 1057 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 1058 } 1059 SDL->SwitchCases.clear(); 1060 1061 SDL->PHINodesToUpdate.clear(); 1062} 1063 1064 1065/// Create the scheduler. If a specific scheduler was specified 1066/// via the SchedulerRegistry, use it, otherwise select the 1067/// one preferred by the target. 1068/// 1069ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1070 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1071 1072 if (!Ctor) { 1073 Ctor = ISHeuristic; 1074 RegisterScheduler::setDefault(Ctor); 1075 } 1076 1077 return Ctor(this, Fast); 1078} 1079 1080ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1081 return new ScheduleHazardRecognizer(); 1082} 1083 1084//===----------------------------------------------------------------------===// 1085// Helper functions used by the generated instruction selector. 1086//===----------------------------------------------------------------------===// 1087// Calls to these methods are generated by tblgen. 1088 1089/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1090/// the dag combiner simplified the 255, we still want to match. RHS is the 1091/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1092/// specified in the .td file (e.g. 255). 1093bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1094 int64_t DesiredMaskS) const { 1095 const APInt &ActualMask = RHS->getAPIntValue(); 1096 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1097 1098 // If the actual mask exactly matches, success! 1099 if (ActualMask == DesiredMask) 1100 return true; 1101 1102 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1103 if (ActualMask.intersects(~DesiredMask)) 1104 return false; 1105 1106 // Otherwise, the DAG Combiner may have proven that the value coming in is 1107 // either already zero or is not demanded. Check for known zero input bits. 1108 APInt NeededMask = DesiredMask & ~ActualMask; 1109 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1110 return true; 1111 1112 // TODO: check to see if missing bits are just not demanded. 1113 1114 // Otherwise, this pattern doesn't match. 1115 return false; 1116} 1117 1118/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1119/// the dag combiner simplified the 255, we still want to match. RHS is the 1120/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1121/// specified in the .td file (e.g. 255). 1122bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1123 int64_t DesiredMaskS) const { 1124 const APInt &ActualMask = RHS->getAPIntValue(); 1125 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1126 1127 // If the actual mask exactly matches, success! 1128 if (ActualMask == DesiredMask) 1129 return true; 1130 1131 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1132 if (ActualMask.intersects(~DesiredMask)) 1133 return false; 1134 1135 // Otherwise, the DAG Combiner may have proven that the value coming in is 1136 // either already zero or is not demanded. Check for known zero input bits. 1137 APInt NeededMask = DesiredMask & ~ActualMask; 1138 1139 APInt KnownZero, KnownOne; 1140 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1141 1142 // If all the missing bits in the or are already known to be set, match! 1143 if ((NeededMask & KnownOne) == NeededMask) 1144 return true; 1145 1146 // TODO: check to see if missing bits are just not demanded. 1147 1148 // Otherwise, this pattern doesn't match. 1149 return false; 1150} 1151 1152 1153/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1154/// by tblgen. Others should not call it. 1155void SelectionDAGISel:: 1156SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1157 std::vector<SDValue> InOps; 1158 std::swap(InOps, Ops); 1159 1160 Ops.push_back(InOps[0]); // input chain. 1161 Ops.push_back(InOps[1]); // input asm string. 1162 1163 unsigned i = 2, e = InOps.size(); 1164 if (InOps[e-1].getValueType() == MVT::Flag) 1165 --e; // Don't process a flag operand if it is here. 1166 1167 while (i != e) { 1168 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1169 if ((Flags & 7) != 4 /*MEM*/) { 1170 // Just skip over this operand, copying the operands verbatim. 1171 Ops.insert(Ops.end(), InOps.begin()+i, 1172 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1173 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1174 } else { 1175 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1176 "Memory operand with multiple values?"); 1177 // Otherwise, this is a memory operand. Ask the target to select it. 1178 std::vector<SDValue> SelOps; 1179 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1180 cerr << "Could not match memory address. Inline asm failure!\n"; 1181 exit(1); 1182 } 1183 1184 // Add this to the output node. 1185 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy(); 1186 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1187 IntPtrTy)); 1188 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1189 i += 2; 1190 } 1191 } 1192 1193 // Add the flag input back if present. 1194 if (e != InOps.size()) 1195 Ops.push_back(InOps.back()); 1196} 1197 1198char SelectionDAGISel::ID = 0; 1199