SelectionDAGISel.cpp revision d9cb7ca388c400e3c7a509c00d4cf63031de0dde
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createFastDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 assert(TLI.getSchedulingPreference() == Sched::Hybrid && 141 "Unknown sched type!"); 142 return createHybridListDAGScheduler(IS, OptLevel); 143 } 144} 145 146// EmitInstrWithCustomInserter - This method should be implemented by targets 147// that mark instructions with the 'usesCustomInserter' flag. These 148// instructions are special in various ways, which require special support to 149// insert. The specified MachineInstr is created but not inserted into any 150// basic blocks, and this method is called to expand it into a sequence of 151// instructions, potentially also creating new basic blocks and control flow. 152// When new basic blocks are inserted and the edges from MBB to its successors 153// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 154// DenseMap. 155MachineBasicBlock * 156TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 157 MachineBasicBlock *MBB) const { 158#ifndef NDEBUG 159 dbgs() << "If a target marks an instruction with " 160 "'usesCustomInserter', it must implement " 161 "TargetLowering::EmitInstrWithCustomInserter!"; 162#endif 163 llvm_unreachable(0); 164 return 0; 165} 166 167//===----------------------------------------------------------------------===// 168// SelectionDAGISel code 169//===----------------------------------------------------------------------===// 170 171SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 173 FuncInfo(new FunctionLoweringInfo(TLI)), 174 CurDAG(new SelectionDAG(tm)), 175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 176 GFI(), 177 OptLevel(OL), 178 DAGSize(0) 179{} 180 181SelectionDAGISel::~SelectionDAGISel() { 182 delete SDB; 183 delete CurDAG; 184 delete FuncInfo; 185} 186 187void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 188 AU.addRequired<AliasAnalysis>(); 189 AU.addPreserved<AliasAnalysis>(); 190 AU.addRequired<GCModuleInfo>(); 191 AU.addPreserved<GCModuleInfo>(); 192 MachineFunctionPass::getAnalysisUsage(AU); 193} 194 195/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 196/// other function that gcc recognizes as "returning twice". This is used to 197/// limit code-gen optimizations on the machine function. 198/// 199/// FIXME: Remove after <rdar://problem/8031714> is fixed. 200static bool FunctionCallsSetJmp(const Function *F) { 201 const Module *M = F->getParent(); 202 static const char *ReturnsTwiceFns[] = { 203 "setjmp", 204 "sigsetjmp", 205 "setjmp_syscall", 206 "savectx", 207 "qsetjmp", 208 "vfork", 209 "getcontext" 210 }; 211#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 212 213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 215 if (!Callee->use_empty()) 216 for (Value::const_use_iterator 217 I = Callee->use_begin(), E = Callee->use_end(); 218 I != E; ++I) 219 if (const CallInst *CI = dyn_cast<CallInst>(I)) 220 if (CI->getParent()->getParent() == F) 221 return true; 222 } 223 224 return false; 225#undef NUM_RETURNS_TWICE_FNS 226} 227 228bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 229 // Do some sanity-checking on the command-line options. 230 assert((!EnableFastISelVerbose || EnableFastISel) && 231 "-fast-isel-verbose requires -fast-isel"); 232 assert((!EnableFastISelAbort || EnableFastISel) && 233 "-fast-isel-abort requires -fast-isel"); 234 235 const Function &Fn = *mf.getFunction(); 236 const TargetInstrInfo &TII = *TM.getInstrInfo(); 237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 238 239 MF = &mf; 240 RegInfo = &MF->getRegInfo(); 241 AA = &getAnalysis<AliasAnalysis>(); 242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 243 244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 245 246 CurDAG->init(*MF); 247 FuncInfo->set(Fn, *MF); 248 SDB->init(GFI, *AA); 249 250 SelectAllBasicBlocks(Fn); 251 252 // If the first basic block in the function has live ins that need to be 253 // copied into vregs, emit the copies into the top of the block before 254 // emitting the code for the block. 255 MachineBasicBlock *EntryMBB = MF->begin(); 256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 257 258 DenseMap<unsigned, unsigned> LiveInMap; 259 if (!FuncInfo->ArgDbgValues.empty()) 260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 261 E = RegInfo->livein_end(); LI != E; ++LI) 262 if (LI->second) 263 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 264 265 // Insert DBG_VALUE instructions for function arguments to the entry block. 266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 268 unsigned Reg = MI->getOperand(0).getReg(); 269 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 270 EntryMBB->insert(EntryMBB->begin(), MI); 271 else { 272 MachineInstr *Def = RegInfo->getVRegDef(Reg); 273 MachineBasicBlock::iterator InsertPos = Def; 274 // FIXME: VR def may not be in entry block. 275 Def->getParent()->insert(llvm::next(InsertPos), MI); 276 } 277 278 // If Reg is live-in then update debug info to track its copy in a vreg. 279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 280 if (LDI != LiveInMap.end()) { 281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 282 MachineBasicBlock::iterator InsertPos = Def; 283 const MDNode *Variable = 284 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 285 unsigned Offset = MI->getOperand(1).getImm(); 286 // Def is never a terminator here, so it is ok to increment InsertPos. 287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 288 TII.get(TargetOpcode::DBG_VALUE)) 289 .addReg(LDI->second, RegState::Debug) 290 .addImm(Offset).addMetadata(Variable); 291 } 292 } 293 294 // Determine if there are any calls in this machine function. 295 MachineFrameInfo *MFI = MF->getFrameInfo(); 296 if (!MFI->hasCalls()) { 297 for (MachineFunction::const_iterator 298 I = MF->begin(), E = MF->end(); I != E; ++I) { 299 const MachineBasicBlock *MBB = I; 300 for (MachineBasicBlock::const_iterator 301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { 304 MFI->setHasCalls(true); 305 goto done; 306 } 307 } 308 } 309 done:; 310 } 311 312 // Determine if there is a call to setjmp in the machine function. 313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 314 315 // Release function-specific state. SDB and CurDAG are already cleared 316 // at this point. 317 FuncInfo->clear(); 318 319 return true; 320} 321 322MachineBasicBlock * 323SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, 324 const BasicBlock *LLVMBB, 325 BasicBlock::const_iterator Begin, 326 BasicBlock::const_iterator End, 327 bool &HadTailCall) { 328 // Lower all of the non-terminator instructions. If a call is emitted 329 // as a tail call, cease emitting nodes for this block. Terminators 330 // are handled below. 331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 332 SDB->visit(*I); 333 334 // Make sure the root of the DAG is up-to-date. 335 CurDAG->setRoot(SDB->getControlRoot()); 336 HadTailCall = SDB->HasTailCall; 337 SDB->clear(); 338 339 // Final step, emit the lowered DAG as machine code. 340 return CodeGenAndEmitDAG(BB); 341} 342 343namespace { 344/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 345/// nodes from the worklist. 346class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 347 SmallVector<SDNode*, 128> &Worklist; 348 SmallPtrSet<SDNode*, 128> &InWorklist; 349public: 350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl, 351 SmallPtrSet<SDNode*, 128> &inwl) 352 : Worklist(wl), InWorklist(inwl) {} 353 354 void RemoveFromWorklist(SDNode *N) { 355 if (!InWorklist.erase(N)) return; 356 357 SmallVector<SDNode*, 128>::iterator I = 358 std::find(Worklist.begin(), Worklist.end(), N); 359 assert(I != Worklist.end() && "Not in worklist"); 360 361 *I = Worklist.back(); 362 Worklist.pop_back(); 363 } 364 365 virtual void NodeDeleted(SDNode *N, SDNode *E) { 366 RemoveFromWorklist(N); 367 } 368 369 virtual void NodeUpdated(SDNode *N) { 370 // Ignore updates. 371 } 372}; 373} 374 375void SelectionDAGISel::ComputeLiveOutVRegInfo() { 376 SmallPtrSet<SDNode*, 128> VisitedNodes; 377 SmallVector<SDNode*, 128> Worklist; 378 379 Worklist.push_back(CurDAG->getRoot().getNode()); 380 381 APInt Mask; 382 APInt KnownZero; 383 APInt KnownOne; 384 385 do { 386 SDNode *N = Worklist.pop_back_val(); 387 388 // If we've already seen this node, ignore it. 389 if (!VisitedNodes.insert(N)) 390 continue; 391 392 // Otherwise, add all chain operands to the worklist. 393 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 394 if (N->getOperand(i).getValueType() == MVT::Other) 395 Worklist.push_back(N->getOperand(i).getNode()); 396 397 // If this is a CopyToReg with a vreg dest, process it. 398 if (N->getOpcode() != ISD::CopyToReg) 399 continue; 400 401 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 402 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 403 continue; 404 405 // Ignore non-scalar or non-integer values. 406 SDValue Src = N->getOperand(2); 407 EVT SrcVT = Src.getValueType(); 408 if (!SrcVT.isInteger() || SrcVT.isVector()) 409 continue; 410 411 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 412 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 413 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 414 415 // Only install this information if it tells us something. 416 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 417 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 418 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 419 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 420 FunctionLoweringInfo::LiveOutInfo &LOI = 421 FuncInfo->LiveOutRegInfo[DestReg]; 422 LOI.NumSignBits = NumSignBits; 423 LOI.KnownOne = KnownOne; 424 LOI.KnownZero = KnownZero; 425 } 426 } while (!Worklist.empty()); 427} 428 429MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { 430 std::string GroupName; 431 if (TimePassesIsEnabled) 432 GroupName = "Instruction Selection and Scheduling"; 433 std::string BlockName; 434 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 435 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 436 ViewSUnitDAGs) 437 BlockName = MF->getFunction()->getNameStr() + ":" + 438 BB->getBasicBlock()->getNameStr(); 439 440 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 441 442 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 443 444 // Run the DAG combiner in pre-legalize mode. 445 { 446 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 447 CurDAG->Combine(Unrestricted, *AA, OptLevel); 448 } 449 450 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 451 452 // Second step, hack on the DAG until it only uses operations and types that 453 // the target supports. 454 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 455 BlockName); 456 457 bool Changed; 458 { 459 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 460 Changed = CurDAG->LegalizeTypes(); 461 } 462 463 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 464 465 if (Changed) { 466 if (ViewDAGCombineLT) 467 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 468 469 // Run the DAG combiner in post-type-legalize mode. 470 { 471 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 472 TimePassesIsEnabled); 473 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 474 } 475 476 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 477 CurDAG->dump()); 478 } 479 480 { 481 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 482 Changed = CurDAG->LegalizeVectors(); 483 } 484 485 if (Changed) { 486 { 487 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 488 CurDAG->LegalizeTypes(); 489 } 490 491 if (ViewDAGCombineLT) 492 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 493 494 // Run the DAG combiner in post-type-legalize mode. 495 { 496 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 497 TimePassesIsEnabled); 498 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 499 } 500 501 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 502 CurDAG->dump()); 503 } 504 505 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 506 507 { 508 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 509 CurDAG->Legalize(OptLevel); 510 } 511 512 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 513 514 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 515 516 // Run the DAG combiner in post-legalize mode. 517 { 518 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 519 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 520 } 521 522 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 523 524 if (OptLevel != CodeGenOpt::None) 525 ComputeLiveOutVRegInfo(); 526 527 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 528 529 // Third, instruction select all of the operations to machine code, adding the 530 // code to the MachineBasicBlock. 531 { 532 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 533 DoInstructionSelection(); 534 } 535 536 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 537 538 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 539 540 // Schedule machine code. 541 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 542 { 543 NamedRegionTimer T("Instruction Scheduling", GroupName, 544 TimePassesIsEnabled); 545 Scheduler->Run(CurDAG, BB, BB->end()); 546 } 547 548 if (ViewSUnitDAGs) Scheduler->viewGraph(); 549 550 // Emit machine code to BB. This can change 'BB' to the last block being 551 // inserted into. 552 { 553 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 554 BB = Scheduler->EmitSchedule(); 555 } 556 557 // Free the scheduler state. 558 { 559 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 560 TimePassesIsEnabled); 561 delete Scheduler; 562 } 563 564 // Free the SelectionDAG state, now that we're finished with it. 565 CurDAG->clear(); 566 567 return BB; 568} 569 570void SelectionDAGISel::DoInstructionSelection() { 571 DEBUG(errs() << "===== Instruction selection begins:\n"); 572 573 PreprocessISelDAG(); 574 575 // Select target instructions for the DAG. 576 { 577 // Number all nodes with a topological order and set DAGSize. 578 DAGSize = CurDAG->AssignTopologicalOrder(); 579 580 // Create a dummy node (which is not added to allnodes), that adds 581 // a reference to the root node, preventing it from being deleted, 582 // and tracking any changes of the root. 583 HandleSDNode Dummy(CurDAG->getRoot()); 584 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 585 ++ISelPosition; 586 587 // The AllNodes list is now topological-sorted. Visit the 588 // nodes by starting at the end of the list (the root of the 589 // graph) and preceding back toward the beginning (the entry 590 // node). 591 while (ISelPosition != CurDAG->allnodes_begin()) { 592 SDNode *Node = --ISelPosition; 593 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 594 // but there are currently some corner cases that it misses. Also, this 595 // makes it theoretically possible to disable the DAGCombiner. 596 if (Node->use_empty()) 597 continue; 598 599 SDNode *ResNode = Select(Node); 600 601 // FIXME: This is pretty gross. 'Select' should be changed to not return 602 // anything at all and this code should be nuked with a tactical strike. 603 604 // If node should not be replaced, continue with the next one. 605 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 606 continue; 607 // Replace node. 608 if (ResNode) 609 ReplaceUses(Node, ResNode); 610 611 // If after the replacement this node is not used any more, 612 // remove this dead node. 613 if (Node->use_empty()) { // Don't delete EntryToken, etc. 614 ISelUpdater ISU(ISelPosition); 615 CurDAG->RemoveDeadNode(Node, &ISU); 616 } 617 } 618 619 CurDAG->setRoot(Dummy.getValue()); 620 } 621 622 DEBUG(errs() << "===== Instruction selection ends:\n"); 623 624 PostprocessISelDAG(); 625} 626 627/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 628/// do other setup for EH landing-pad blocks. 629void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { 630 // Add a label to mark the beginning of the landing pad. Deletion of the 631 // landing pad can thus be detected via the MachineModuleInfo. 632 MCSymbol *Label = MF->getMMI().addLandingPad(BB); 633 634 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 635 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); 636 637 // Mark exception register as live in. 638 unsigned Reg = TLI.getExceptionAddressRegister(); 639 if (Reg) BB->addLiveIn(Reg); 640 641 // Mark exception selector register as live in. 642 Reg = TLI.getExceptionSelectorRegister(); 643 if (Reg) BB->addLiveIn(Reg); 644 645 // FIXME: Hack around an exception handling flaw (PR1508): the personality 646 // function and list of typeids logically belong to the invoke (or, if you 647 // like, the basic block containing the invoke), and need to be associated 648 // with it in the dwarf exception handling tables. Currently however the 649 // information is provided by an intrinsic (eh.selector) that can be moved 650 // to unexpected places by the optimizers: if the unwind edge is critical, 651 // then breaking it can result in the intrinsics being in the successor of 652 // the landing pad, not the landing pad itself. This results 653 // in exceptions not being caught because no typeids are associated with 654 // the invoke. This may not be the only way things can go wrong, but it 655 // is the only way we try to work around for the moment. 656 const BasicBlock *LLVMBB = BB->getBasicBlock(); 657 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 658 659 if (Br && Br->isUnconditional()) { // Critical edge? 660 BasicBlock::const_iterator I, E; 661 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 662 if (isa<EHSelectorInst>(I)) 663 break; 664 665 if (I == E) 666 // No catch info found - try to extract some from the successor. 667 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 668 } 669} 670 671void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 672 // Initialize the Fast-ISel state, if needed. 673 FastISel *FastIS = 0; 674 if (EnableFastISel) 675 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap, 676 FuncInfo->StaticAllocaMap, 677 FuncInfo->PHINodesToUpdate 678#ifndef NDEBUG 679 , FuncInfo->CatchInfoLost 680#endif 681 ); 682 683 // Iterate over all basic blocks in the function. 684 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 685 const BasicBlock *LLVMBB = &*I; 686 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; 687 688 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 689 BasicBlock::const_iterator const End = LLVMBB->end(); 690 BasicBlock::const_iterator BI = Begin; 691 692 // Lower any arguments needed in this block if this is the entry block. 693 if (LLVMBB == &Fn.getEntryBlock()) 694 LowerArguments(LLVMBB); 695 696 // Setup an EH landing-pad block. 697 if (BB->isLandingPad()) 698 PrepareEHLandingPad(BB); 699 700 // Before doing SelectionDAG ISel, see if FastISel has been requested. 701 if (FastIS) { 702 // Emit code for any incoming arguments. This must happen before 703 // beginning FastISel on the entry block. 704 if (LLVMBB == &Fn.getEntryBlock()) { 705 CurDAG->setRoot(SDB->getControlRoot()); 706 SDB->clear(); 707 BB = CodeGenAndEmitDAG(BB); 708 } 709 FastIS->startNewBlock(BB); 710 // Do FastISel on as many instructions as possible. 711 for (; BI != End; ++BI) { 712#if 0 713 // Defer instructions with no side effects; they'll be emitted 714 // on-demand later. 715 if (BI->isSafeToSpeculativelyExecute() && 716 !FuncInfo->isExportedInst(BI)) 717 continue; 718#endif 719 720 // Try to select the instruction with FastISel. 721 if (FastIS->SelectInstruction(BI)) 722 continue; 723 724 // Then handle certain instructions as single-LLVM-Instruction blocks. 725 if (isa<CallInst>(BI)) { 726 ++NumFastIselFailures; 727 if (EnableFastISelVerbose || EnableFastISelAbort) { 728 dbgs() << "FastISel missed call: "; 729 BI->dump(); 730 } 731 732 if (!BI->getType()->isVoidTy() && !BI->use_empty()) { 733 unsigned &R = FuncInfo->ValueMap[BI]; 734 if (!R) 735 R = FuncInfo->CreateRegs(BI->getType()); 736 } 737 738 bool HadTailCall = false; 739 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall); 740 741 // If the call was emitted as a tail call, we're done with the block. 742 if (HadTailCall) { 743 BI = End; 744 break; 745 } 746 747 // If the instruction was codegen'd with multiple blocks, 748 // inform the FastISel object where to resume inserting. 749 FastIS->setCurrentBlock(BB); 750 continue; 751 } 752 753 // Otherwise, give up on FastISel for the rest of the block. 754 // For now, be a little lenient about non-branch terminators. 755 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 756 ++NumFastIselFailures; 757 if (EnableFastISelVerbose || EnableFastISelAbort) { 758 dbgs() << "FastISel miss: "; 759 BI->dump(); 760 } 761 if (EnableFastISelAbort) 762 // The "fast" selector couldn't handle something and bailed. 763 // For the purpose of debugging, just abort. 764 llvm_unreachable("FastISel didn't select the entire block"); 765 } 766 break; 767 } 768 } 769 770 // Run SelectionDAG instruction selection on the remainder of the block 771 // not handled by FastISel. If FastISel is not run, this is the entire 772 // block. 773 if (BI != End) { 774 bool HadTailCall; 775 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall); 776 } 777 778 FinishBasicBlock(BB); 779 FuncInfo->PHINodesToUpdate.clear(); 780 } 781 782 delete FastIS; 783} 784 785void 786SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { 787 788 DEBUG(dbgs() << "Total amount of phi nodes to update: " 789 << FuncInfo->PHINodesToUpdate.size() << "\n"; 790 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 791 dbgs() << "Node " << i << " : (" 792 << FuncInfo->PHINodesToUpdate[i].first 793 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 794 795 // Next, now that we know what the last MBB the LLVM BB expanded is, update 796 // PHI nodes in successors. 797 if (SDB->SwitchCases.empty() && 798 SDB->JTCases.empty() && 799 SDB->BitTestCases.empty()) { 800 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 801 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 802 assert(PHI->isPHI() && 803 "This is not a machine PHI node that we are updating!"); 804 if (!BB->isSuccessor(PHI->getParent())) 805 continue; 806 PHI->addOperand( 807 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 808 PHI->addOperand(MachineOperand::CreateMBB(BB)); 809 } 810 return; 811 } 812 813 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 814 // Lower header first, if it wasn't already lowered 815 if (!SDB->BitTestCases[i].Emitted) { 816 // Set the current basic block to the mbb we wish to insert the code into 817 BB = SDB->BitTestCases[i].Parent; 818 // Emit the code 819 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); 820 CurDAG->setRoot(SDB->getRoot()); 821 SDB->clear(); 822 BB = CodeGenAndEmitDAG(BB); 823 } 824 825 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 826 // Set the current basic block to the mbb we wish to insert the code into 827 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 828 // Emit the code 829 if (j+1 != ej) 830 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 831 SDB->BitTestCases[i].Reg, 832 SDB->BitTestCases[i].Cases[j], 833 BB); 834 else 835 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 836 SDB->BitTestCases[i].Reg, 837 SDB->BitTestCases[i].Cases[j], 838 BB); 839 840 841 CurDAG->setRoot(SDB->getRoot()); 842 SDB->clear(); 843 BB = CodeGenAndEmitDAG(BB); 844 } 845 846 // Update PHI Nodes 847 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 848 pi != pe; ++pi) { 849 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 850 MachineBasicBlock *PHIBB = PHI->getParent(); 851 assert(PHI->isPHI() && 852 "This is not a machine PHI node that we are updating!"); 853 // This is "default" BB. We have two jumps to it. From "header" BB and 854 // from last "case" BB. 855 if (PHIBB == SDB->BitTestCases[i].Default) { 856 PHI->addOperand(MachineOperand:: 857 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 858 false)); 859 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 860 PHI->addOperand(MachineOperand:: 861 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 862 false)); 863 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 864 back().ThisBB)); 865 } 866 // One of "cases" BB. 867 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 868 j != ej; ++j) { 869 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 870 if (cBB->isSuccessor(PHIBB)) { 871 PHI->addOperand(MachineOperand:: 872 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 873 false)); 874 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 875 } 876 } 877 } 878 } 879 SDB->BitTestCases.clear(); 880 881 // If the JumpTable record is filled in, then we need to emit a jump table. 882 // Updating the PHI nodes is tricky in this case, since we need to determine 883 // whether the PHI is a successor of the range check MBB or the jump table MBB 884 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 885 // Lower header first, if it wasn't already lowered 886 if (!SDB->JTCases[i].first.Emitted) { 887 // Set the current basic block to the mbb we wish to insert the code into 888 BB = SDB->JTCases[i].first.HeaderBB; 889 // Emit the code 890 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 891 BB); 892 CurDAG->setRoot(SDB->getRoot()); 893 SDB->clear(); 894 BB = CodeGenAndEmitDAG(BB); 895 } 896 897 // Set the current basic block to the mbb we wish to insert the code into 898 BB = SDB->JTCases[i].second.MBB; 899 // Emit the code 900 SDB->visitJumpTable(SDB->JTCases[i].second); 901 CurDAG->setRoot(SDB->getRoot()); 902 SDB->clear(); 903 BB = CodeGenAndEmitDAG(BB); 904 905 // Update PHI Nodes 906 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 907 pi != pe; ++pi) { 908 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 909 MachineBasicBlock *PHIBB = PHI->getParent(); 910 assert(PHI->isPHI() && 911 "This is not a machine PHI node that we are updating!"); 912 // "default" BB. We can go there only from header BB. 913 if (PHIBB == SDB->JTCases[i].second.Default) { 914 PHI->addOperand 915 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 916 false)); 917 PHI->addOperand 918 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 919 } 920 // JT BB. Just iterate over successors here 921 if (BB->isSuccessor(PHIBB)) { 922 PHI->addOperand 923 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 924 false)); 925 PHI->addOperand(MachineOperand::CreateMBB(BB)); 926 } 927 } 928 } 929 SDB->JTCases.clear(); 930 931 // If the switch block involved a branch to one of the actual successors, we 932 // need to update PHI nodes in that block. 933 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 934 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 935 assert(PHI->isPHI() && 936 "This is not a machine PHI node that we are updating!"); 937 if (BB->isSuccessor(PHI->getParent())) { 938 PHI->addOperand( 939 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 940 PHI->addOperand(MachineOperand::CreateMBB(BB)); 941 } 942 } 943 944 // If we generated any switch lowering information, build and codegen any 945 // additional DAGs necessary. 946 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 947 // Set the current basic block to the mbb we wish to insert the code into 948 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 949 950 // Determine the unique successors. 951 SmallVector<MachineBasicBlock *, 2> Succs; 952 Succs.push_back(SDB->SwitchCases[i].TrueBB); 953 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 954 Succs.push_back(SDB->SwitchCases[i].FalseBB); 955 956 // Emit the code. Note that this could result in ThisBB being split, so 957 // we need to check for updates. 958 SDB->visitSwitchCase(SDB->SwitchCases[i], BB); 959 CurDAG->setRoot(SDB->getRoot()); 960 SDB->clear(); 961 ThisBB = CodeGenAndEmitDAG(BB); 962 963 // Handle any PHI nodes in successors of this chunk, as if we were coming 964 // from the original BB before switch expansion. Note that PHI nodes can 965 // occur multiple times in PHINodesToUpdate. We have to be very careful to 966 // handle them the right number of times. 967 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 968 BB = Succs[i]; 969 // BB may have been removed from the CFG if a branch was constant folded. 970 if (ThisBB->isSuccessor(BB)) { 971 for (MachineBasicBlock::iterator Phi = BB->begin(); 972 Phi != BB->end() && Phi->isPHI(); 973 ++Phi) { 974 // This value for this PHI node is recorded in PHINodesToUpdate. 975 for (unsigned pn = 0; ; ++pn) { 976 assert(pn != FuncInfo->PHINodesToUpdate.size() && 977 "Didn't find PHI entry!"); 978 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 979 Phi->addOperand(MachineOperand:: 980 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 981 false)); 982 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 983 break; 984 } 985 } 986 } 987 } 988 } 989 } 990 SDB->SwitchCases.clear(); 991} 992 993 994/// Create the scheduler. If a specific scheduler was specified 995/// via the SchedulerRegistry, use it, otherwise select the 996/// one preferred by the target. 997/// 998ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 999 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1000 1001 if (!Ctor) { 1002 Ctor = ISHeuristic; 1003 RegisterScheduler::setDefault(Ctor); 1004 } 1005 1006 return Ctor(this, OptLevel); 1007} 1008 1009ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1010 return new ScheduleHazardRecognizer(); 1011} 1012 1013//===----------------------------------------------------------------------===// 1014// Helper functions used by the generated instruction selector. 1015//===----------------------------------------------------------------------===// 1016// Calls to these methods are generated by tblgen. 1017 1018/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1019/// the dag combiner simplified the 255, we still want to match. RHS is the 1020/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1021/// specified in the .td file (e.g. 255). 1022bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1023 int64_t DesiredMaskS) const { 1024 const APInt &ActualMask = RHS->getAPIntValue(); 1025 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1026 1027 // If the actual mask exactly matches, success! 1028 if (ActualMask == DesiredMask) 1029 return true; 1030 1031 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1032 if (ActualMask.intersects(~DesiredMask)) 1033 return false; 1034 1035 // Otherwise, the DAG Combiner may have proven that the value coming in is 1036 // either already zero or is not demanded. Check for known zero input bits. 1037 APInt NeededMask = DesiredMask & ~ActualMask; 1038 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1039 return true; 1040 1041 // TODO: check to see if missing bits are just not demanded. 1042 1043 // Otherwise, this pattern doesn't match. 1044 return false; 1045} 1046 1047/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1048/// the dag combiner simplified the 255, we still want to match. RHS is the 1049/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1050/// specified in the .td file (e.g. 255). 1051bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1052 int64_t DesiredMaskS) const { 1053 const APInt &ActualMask = RHS->getAPIntValue(); 1054 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1055 1056 // If the actual mask exactly matches, success! 1057 if (ActualMask == DesiredMask) 1058 return true; 1059 1060 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1061 if (ActualMask.intersects(~DesiredMask)) 1062 return false; 1063 1064 // Otherwise, the DAG Combiner may have proven that the value coming in is 1065 // either already zero or is not demanded. Check for known zero input bits. 1066 APInt NeededMask = DesiredMask & ~ActualMask; 1067 1068 APInt KnownZero, KnownOne; 1069 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1070 1071 // If all the missing bits in the or are already known to be set, match! 1072 if ((NeededMask & KnownOne) == NeededMask) 1073 return true; 1074 1075 // TODO: check to see if missing bits are just not demanded. 1076 1077 // Otherwise, this pattern doesn't match. 1078 return false; 1079} 1080 1081 1082/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1083/// by tblgen. Others should not call it. 1084void SelectionDAGISel:: 1085SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1086 std::vector<SDValue> InOps; 1087 std::swap(InOps, Ops); 1088 1089 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1090 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1091 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1092 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3 1093 1094 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1095 if (InOps[e-1].getValueType() == MVT::Flag) 1096 --e; // Don't process a flag operand if it is here. 1097 1098 while (i != e) { 1099 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1100 if (!InlineAsm::isMemKind(Flags)) { 1101 // Just skip over this operand, copying the operands verbatim. 1102 Ops.insert(Ops.end(), InOps.begin()+i, 1103 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1104 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1105 } else { 1106 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1107 "Memory operand with multiple values?"); 1108 // Otherwise, this is a memory operand. Ask the target to select it. 1109 std::vector<SDValue> SelOps; 1110 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1111 report_fatal_error("Could not match memory address. Inline asm" 1112 " failure!"); 1113 1114 // Add this to the output node. 1115 unsigned NewFlags = 1116 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1117 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1118 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1119 i += 2; 1120 } 1121 } 1122 1123 // Add the flag input back if present. 1124 if (e != InOps.size()) 1125 Ops.push_back(InOps.back()); 1126} 1127 1128/// findFlagUse - Return use of EVT::Flag value produced by the specified 1129/// SDNode. 1130/// 1131static SDNode *findFlagUse(SDNode *N) { 1132 unsigned FlagResNo = N->getNumValues()-1; 1133 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1134 SDUse &Use = I.getUse(); 1135 if (Use.getResNo() == FlagResNo) 1136 return Use.getUser(); 1137 } 1138 return NULL; 1139} 1140 1141/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1142/// This function recursively traverses up the operand chain, ignoring 1143/// certain nodes. 1144static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1145 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1146 bool IgnoreChains) { 1147 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1148 // greater than all of its (recursive) operands. If we scan to a point where 1149 // 'use' is smaller than the node we're scanning for, then we know we will 1150 // never find it. 1151 // 1152 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1153 // happen because we scan down to newly selected nodes in the case of flag 1154 // uses. 1155 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1156 return false; 1157 1158 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1159 // won't fail if we scan it again. 1160 if (!Visited.insert(Use)) 1161 return false; 1162 1163 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1164 // Ignore chain uses, they are validated by HandleMergeInputChains. 1165 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1166 continue; 1167 1168 SDNode *N = Use->getOperand(i).getNode(); 1169 if (N == Def) { 1170 if (Use == ImmedUse || Use == Root) 1171 continue; // We are not looking for immediate use. 1172 assert(N != Root); 1173 return true; 1174 } 1175 1176 // Traverse up the operand chain. 1177 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1178 return true; 1179 } 1180 return false; 1181} 1182 1183/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1184/// operand node N of U during instruction selection that starts at Root. 1185bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1186 SDNode *Root) const { 1187 if (OptLevel == CodeGenOpt::None) return false; 1188 return N.hasOneUse(); 1189} 1190 1191/// IsLegalToFold - Returns true if the specific operand node N of 1192/// U can be folded during instruction selection that starts at Root. 1193bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1194 CodeGenOpt::Level OptLevel, 1195 bool IgnoreChains) { 1196 if (OptLevel == CodeGenOpt::None) return false; 1197 1198 // If Root use can somehow reach N through a path that that doesn't contain 1199 // U then folding N would create a cycle. e.g. In the following 1200 // diagram, Root can reach N through X. If N is folded into into Root, then 1201 // X is both a predecessor and a successor of U. 1202 // 1203 // [N*] // 1204 // ^ ^ // 1205 // / \ // 1206 // [U*] [X]? // 1207 // ^ ^ // 1208 // \ / // 1209 // \ / // 1210 // [Root*] // 1211 // 1212 // * indicates nodes to be folded together. 1213 // 1214 // If Root produces a flag, then it gets (even more) interesting. Since it 1215 // will be "glued" together with its flag use in the scheduler, we need to 1216 // check if it might reach N. 1217 // 1218 // [N*] // 1219 // ^ ^ // 1220 // / \ // 1221 // [U*] [X]? // 1222 // ^ ^ // 1223 // \ \ // 1224 // \ | // 1225 // [Root*] | // 1226 // ^ | // 1227 // f | // 1228 // | / // 1229 // [Y] / // 1230 // ^ / // 1231 // f / // 1232 // | / // 1233 // [FU] // 1234 // 1235 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1236 // (call it Fold), then X is a predecessor of FU and a successor of 1237 // Fold. But since Fold and FU are flagged together, this will create 1238 // a cycle in the scheduling graph. 1239 1240 // If the node has flags, walk down the graph to the "lowest" node in the 1241 // flagged set. 1242 EVT VT = Root->getValueType(Root->getNumValues()-1); 1243 while (VT == MVT::Flag) { 1244 SDNode *FU = findFlagUse(Root); 1245 if (FU == NULL) 1246 break; 1247 Root = FU; 1248 VT = Root->getValueType(Root->getNumValues()-1); 1249 1250 // If our query node has a flag result with a use, we've walked up it. If 1251 // the user (which has already been selected) has a chain or indirectly uses 1252 // the chain, our WalkChainUsers predicate will not consider it. Because of 1253 // this, we cannot ignore chains in this predicate. 1254 IgnoreChains = false; 1255 } 1256 1257 1258 SmallPtrSet<SDNode*, 16> Visited; 1259 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1260} 1261 1262SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1263 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1264 SelectInlineAsmMemoryOperands(Ops); 1265 1266 std::vector<EVT> VTs; 1267 VTs.push_back(MVT::Other); 1268 VTs.push_back(MVT::Flag); 1269 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1270 VTs, &Ops[0], Ops.size()); 1271 New->setNodeId(-1); 1272 return New.getNode(); 1273} 1274 1275SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1276 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1277} 1278 1279/// GetVBR - decode a vbr encoding whose top bit is set. 1280ALWAYS_INLINE static uint64_t 1281GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1282 assert(Val >= 128 && "Not a VBR"); 1283 Val &= 127; // Remove first vbr bit. 1284 1285 unsigned Shift = 7; 1286 uint64_t NextBits; 1287 do { 1288 NextBits = MatcherTable[Idx++]; 1289 Val |= (NextBits&127) << Shift; 1290 Shift += 7; 1291 } while (NextBits & 128); 1292 1293 return Val; 1294} 1295 1296 1297/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1298/// interior flag and chain results to use the new flag and chain results. 1299void SelectionDAGISel:: 1300UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1301 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1302 SDValue InputFlag, 1303 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1304 bool isMorphNodeTo) { 1305 SmallVector<SDNode*, 4> NowDeadNodes; 1306 1307 ISelUpdater ISU(ISelPosition); 1308 1309 // Now that all the normal results are replaced, we replace the chain and 1310 // flag results if present. 1311 if (!ChainNodesMatched.empty()) { 1312 assert(InputChain.getNode() != 0 && 1313 "Matched input chains but didn't produce a chain"); 1314 // Loop over all of the nodes we matched that produced a chain result. 1315 // Replace all the chain results with the final chain we ended up with. 1316 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1317 SDNode *ChainNode = ChainNodesMatched[i]; 1318 1319 // If this node was already deleted, don't look at it. 1320 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1321 continue; 1322 1323 // Don't replace the results of the root node if we're doing a 1324 // MorphNodeTo. 1325 if (ChainNode == NodeToMatch && isMorphNodeTo) 1326 continue; 1327 1328 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1329 if (ChainVal.getValueType() == MVT::Flag) 1330 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1331 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1332 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1333 1334 // If the node became dead and we haven't already seen it, delete it. 1335 if (ChainNode->use_empty() && 1336 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1337 NowDeadNodes.push_back(ChainNode); 1338 } 1339 } 1340 1341 // If the result produces a flag, update any flag results in the matched 1342 // pattern with the flag result. 1343 if (InputFlag.getNode() != 0) { 1344 // Handle any interior nodes explicitly marked. 1345 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1346 SDNode *FRN = FlagResultNodesMatched[i]; 1347 1348 // If this node was already deleted, don't look at it. 1349 if (FRN->getOpcode() == ISD::DELETED_NODE) 1350 continue; 1351 1352 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1353 "Doesn't have a flag result"); 1354 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1355 InputFlag, &ISU); 1356 1357 // If the node became dead and we haven't already seen it, delete it. 1358 if (FRN->use_empty() && 1359 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1360 NowDeadNodes.push_back(FRN); 1361 } 1362 } 1363 1364 if (!NowDeadNodes.empty()) 1365 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1366 1367 DEBUG(errs() << "ISEL: Match complete!\n"); 1368} 1369 1370enum ChainResult { 1371 CR_Simple, 1372 CR_InducesCycle, 1373 CR_LeadsToInteriorNode 1374}; 1375 1376/// WalkChainUsers - Walk down the users of the specified chained node that is 1377/// part of the pattern we're matching, looking at all of the users we find. 1378/// This determines whether something is an interior node, whether we have a 1379/// non-pattern node in between two pattern nodes (which prevent folding because 1380/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1381/// between pattern nodes (in which case the TF becomes part of the pattern). 1382/// 1383/// The walk we do here is guaranteed to be small because we quickly get down to 1384/// already selected nodes "below" us. 1385static ChainResult 1386WalkChainUsers(SDNode *ChainedNode, 1387 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1388 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1389 ChainResult Result = CR_Simple; 1390 1391 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1392 E = ChainedNode->use_end(); UI != E; ++UI) { 1393 // Make sure the use is of the chain, not some other value we produce. 1394 if (UI.getUse().getValueType() != MVT::Other) continue; 1395 1396 SDNode *User = *UI; 1397 1398 // If we see an already-selected machine node, then we've gone beyond the 1399 // pattern that we're selecting down into the already selected chunk of the 1400 // DAG. 1401 if (User->isMachineOpcode() || 1402 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1403 continue; 1404 1405 if (User->getOpcode() == ISD::CopyToReg || 1406 User->getOpcode() == ISD::CopyFromReg || 1407 User->getOpcode() == ISD::INLINEASM || 1408 User->getOpcode() == ISD::EH_LABEL) { 1409 // If their node ID got reset to -1 then they've already been selected. 1410 // Treat them like a MachineOpcode. 1411 if (User->getNodeId() == -1) 1412 continue; 1413 } 1414 1415 // If we have a TokenFactor, we handle it specially. 1416 if (User->getOpcode() != ISD::TokenFactor) { 1417 // If the node isn't a token factor and isn't part of our pattern, then it 1418 // must be a random chained node in between two nodes we're selecting. 1419 // This happens when we have something like: 1420 // x = load ptr 1421 // call 1422 // y = x+4 1423 // store y -> ptr 1424 // Because we structurally match the load/store as a read/modify/write, 1425 // but the call is chained between them. We cannot fold in this case 1426 // because it would induce a cycle in the graph. 1427 if (!std::count(ChainedNodesInPattern.begin(), 1428 ChainedNodesInPattern.end(), User)) 1429 return CR_InducesCycle; 1430 1431 // Otherwise we found a node that is part of our pattern. For example in: 1432 // x = load ptr 1433 // y = x+4 1434 // store y -> ptr 1435 // This would happen when we're scanning down from the load and see the 1436 // store as a user. Record that there is a use of ChainedNode that is 1437 // part of the pattern and keep scanning uses. 1438 Result = CR_LeadsToInteriorNode; 1439 InteriorChainedNodes.push_back(User); 1440 continue; 1441 } 1442 1443 // If we found a TokenFactor, there are two cases to consider: first if the 1444 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1445 // uses of the TF are in our pattern) we just want to ignore it. Second, 1446 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1447 // [Load chain] 1448 // ^ 1449 // | 1450 // [Load] 1451 // ^ ^ 1452 // | \ DAG's like cheese 1453 // / \ do you? 1454 // / | 1455 // [TokenFactor] [Op] 1456 // ^ ^ 1457 // | | 1458 // \ / 1459 // \ / 1460 // [Store] 1461 // 1462 // In this case, the TokenFactor becomes part of our match and we rewrite it 1463 // as a new TokenFactor. 1464 // 1465 // To distinguish these two cases, do a recursive walk down the uses. 1466 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1467 case CR_Simple: 1468 // If the uses of the TokenFactor are just already-selected nodes, ignore 1469 // it, it is "below" our pattern. 1470 continue; 1471 case CR_InducesCycle: 1472 // If the uses of the TokenFactor lead to nodes that are not part of our 1473 // pattern that are not selected, folding would turn this into a cycle, 1474 // bail out now. 1475 return CR_InducesCycle; 1476 case CR_LeadsToInteriorNode: 1477 break; // Otherwise, keep processing. 1478 } 1479 1480 // Okay, we know we're in the interesting interior case. The TokenFactor 1481 // is now going to be considered part of the pattern so that we rewrite its 1482 // uses (it may have uses that are not part of the pattern) with the 1483 // ultimate chain result of the generated code. We will also add its chain 1484 // inputs as inputs to the ultimate TokenFactor we create. 1485 Result = CR_LeadsToInteriorNode; 1486 ChainedNodesInPattern.push_back(User); 1487 InteriorChainedNodes.push_back(User); 1488 continue; 1489 } 1490 1491 return Result; 1492} 1493 1494/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1495/// operation for when the pattern matched at least one node with a chains. The 1496/// input vector contains a list of all of the chained nodes that we match. We 1497/// must determine if this is a valid thing to cover (i.e. matching it won't 1498/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1499/// be used as the input node chain for the generated nodes. 1500static SDValue 1501HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1502 SelectionDAG *CurDAG) { 1503 // Walk all of the chained nodes we've matched, recursively scanning down the 1504 // users of the chain result. This adds any TokenFactor nodes that are caught 1505 // in between chained nodes to the chained and interior nodes list. 1506 SmallVector<SDNode*, 3> InteriorChainedNodes; 1507 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1508 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1509 InteriorChainedNodes) == CR_InducesCycle) 1510 return SDValue(); // Would induce a cycle. 1511 } 1512 1513 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1514 // that we are interested in. Form our input TokenFactor node. 1515 SmallVector<SDValue, 3> InputChains; 1516 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1517 // Add the input chain of this node to the InputChains list (which will be 1518 // the operands of the generated TokenFactor) if it's not an interior node. 1519 SDNode *N = ChainNodesMatched[i]; 1520 if (N->getOpcode() != ISD::TokenFactor) { 1521 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1522 continue; 1523 1524 // Otherwise, add the input chain. 1525 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1526 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1527 InputChains.push_back(InChain); 1528 continue; 1529 } 1530 1531 // If we have a token factor, we want to add all inputs of the token factor 1532 // that are not part of the pattern we're matching. 1533 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1534 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1535 N->getOperand(op).getNode())) 1536 InputChains.push_back(N->getOperand(op)); 1537 } 1538 } 1539 1540 SDValue Res; 1541 if (InputChains.size() == 1) 1542 return InputChains[0]; 1543 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1544 MVT::Other, &InputChains[0], InputChains.size()); 1545} 1546 1547/// MorphNode - Handle morphing a node in place for the selector. 1548SDNode *SelectionDAGISel:: 1549MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1550 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1551 // It is possible we're using MorphNodeTo to replace a node with no 1552 // normal results with one that has a normal result (or we could be 1553 // adding a chain) and the input could have flags and chains as well. 1554 // In this case we need to shift the operands down. 1555 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1556 // than the old isel though. 1557 int OldFlagResultNo = -1, OldChainResultNo = -1; 1558 1559 unsigned NTMNumResults = Node->getNumValues(); 1560 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1561 OldFlagResultNo = NTMNumResults-1; 1562 if (NTMNumResults != 1 && 1563 Node->getValueType(NTMNumResults-2) == MVT::Other) 1564 OldChainResultNo = NTMNumResults-2; 1565 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1566 OldChainResultNo = NTMNumResults-1; 1567 1568 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1569 // that this deletes operands of the old node that become dead. 1570 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1571 1572 // MorphNodeTo can operate in two ways: if an existing node with the 1573 // specified operands exists, it can just return it. Otherwise, it 1574 // updates the node in place to have the requested operands. 1575 if (Res == Node) { 1576 // If we updated the node in place, reset the node ID. To the isel, 1577 // this should be just like a newly allocated machine node. 1578 Res->setNodeId(-1); 1579 } 1580 1581 unsigned ResNumResults = Res->getNumValues(); 1582 // Move the flag if needed. 1583 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1584 (unsigned)OldFlagResultNo != ResNumResults-1) 1585 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1586 SDValue(Res, ResNumResults-1)); 1587 1588 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1589 --ResNumResults; 1590 1591 // Move the chain reference if needed. 1592 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1593 (unsigned)OldChainResultNo != ResNumResults-1) 1594 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1595 SDValue(Res, ResNumResults-1)); 1596 1597 // Otherwise, no replacement happened because the node already exists. Replace 1598 // Uses of the old node with the new one. 1599 if (Res != Node) 1600 CurDAG->ReplaceAllUsesWith(Node, Res); 1601 1602 return Res; 1603} 1604 1605/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1606ALWAYS_INLINE static bool 1607CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1608 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1609 // Accept if it is exactly the same as a previously recorded node. 1610 unsigned RecNo = MatcherTable[MatcherIndex++]; 1611 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1612 return N == RecordedNodes[RecNo]; 1613} 1614 1615/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1616ALWAYS_INLINE static bool 1617CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1618 SelectionDAGISel &SDISel) { 1619 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1620} 1621 1622/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1623ALWAYS_INLINE static bool 1624CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1625 SelectionDAGISel &SDISel, SDNode *N) { 1626 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1627} 1628 1629ALWAYS_INLINE static bool 1630CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1631 SDNode *N) { 1632 uint16_t Opc = MatcherTable[MatcherIndex++]; 1633 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1634 return N->getOpcode() == Opc; 1635} 1636 1637ALWAYS_INLINE static bool 1638CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1639 SDValue N, const TargetLowering &TLI) { 1640 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1641 if (N.getValueType() == VT) return true; 1642 1643 // Handle the case when VT is iPTR. 1644 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1645} 1646 1647ALWAYS_INLINE static bool 1648CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1649 SDValue N, const TargetLowering &TLI, 1650 unsigned ChildNo) { 1651 if (ChildNo >= N.getNumOperands()) 1652 return false; // Match fails if out of range child #. 1653 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1654} 1655 1656 1657ALWAYS_INLINE static bool 1658CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1659 SDValue N) { 1660 return cast<CondCodeSDNode>(N)->get() == 1661 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1662} 1663 1664ALWAYS_INLINE static bool 1665CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1666 SDValue N, const TargetLowering &TLI) { 1667 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1668 if (cast<VTSDNode>(N)->getVT() == VT) 1669 return true; 1670 1671 // Handle the case when VT is iPTR. 1672 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1673} 1674 1675ALWAYS_INLINE static bool 1676CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1677 SDValue N) { 1678 int64_t Val = MatcherTable[MatcherIndex++]; 1679 if (Val & 128) 1680 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1681 1682 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1683 return C != 0 && C->getSExtValue() == Val; 1684} 1685 1686ALWAYS_INLINE static bool 1687CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1688 SDValue N, SelectionDAGISel &SDISel) { 1689 int64_t Val = MatcherTable[MatcherIndex++]; 1690 if (Val & 128) 1691 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1692 1693 if (N->getOpcode() != ISD::AND) return false; 1694 1695 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1696 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1697} 1698 1699ALWAYS_INLINE static bool 1700CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1701 SDValue N, SelectionDAGISel &SDISel) { 1702 int64_t Val = MatcherTable[MatcherIndex++]; 1703 if (Val & 128) 1704 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1705 1706 if (N->getOpcode() != ISD::OR) return false; 1707 1708 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1709 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1710} 1711 1712/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1713/// scope, evaluate the current node. If the current predicate is known to 1714/// fail, set Result=true and return anything. If the current predicate is 1715/// known to pass, set Result=false and return the MatcherIndex to continue 1716/// with. If the current predicate is unknown, set Result=false and return the 1717/// MatcherIndex to continue with. 1718static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1719 unsigned Index, SDValue N, 1720 bool &Result, SelectionDAGISel &SDISel, 1721 SmallVectorImpl<SDValue> &RecordedNodes){ 1722 switch (Table[Index++]) { 1723 default: 1724 Result = false; 1725 return Index-1; // Could not evaluate this predicate. 1726 case SelectionDAGISel::OPC_CheckSame: 1727 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1728 return Index; 1729 case SelectionDAGISel::OPC_CheckPatternPredicate: 1730 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1731 return Index; 1732 case SelectionDAGISel::OPC_CheckPredicate: 1733 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1734 return Index; 1735 case SelectionDAGISel::OPC_CheckOpcode: 1736 Result = !::CheckOpcode(Table, Index, N.getNode()); 1737 return Index; 1738 case SelectionDAGISel::OPC_CheckType: 1739 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1740 return Index; 1741 case SelectionDAGISel::OPC_CheckChild0Type: 1742 case SelectionDAGISel::OPC_CheckChild1Type: 1743 case SelectionDAGISel::OPC_CheckChild2Type: 1744 case SelectionDAGISel::OPC_CheckChild3Type: 1745 case SelectionDAGISel::OPC_CheckChild4Type: 1746 case SelectionDAGISel::OPC_CheckChild5Type: 1747 case SelectionDAGISel::OPC_CheckChild6Type: 1748 case SelectionDAGISel::OPC_CheckChild7Type: 1749 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1750 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1751 return Index; 1752 case SelectionDAGISel::OPC_CheckCondCode: 1753 Result = !::CheckCondCode(Table, Index, N); 1754 return Index; 1755 case SelectionDAGISel::OPC_CheckValueType: 1756 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1757 return Index; 1758 case SelectionDAGISel::OPC_CheckInteger: 1759 Result = !::CheckInteger(Table, Index, N); 1760 return Index; 1761 case SelectionDAGISel::OPC_CheckAndImm: 1762 Result = !::CheckAndImm(Table, Index, N, SDISel); 1763 return Index; 1764 case SelectionDAGISel::OPC_CheckOrImm: 1765 Result = !::CheckOrImm(Table, Index, N, SDISel); 1766 return Index; 1767 } 1768} 1769 1770namespace { 1771 1772struct MatchScope { 1773 /// FailIndex - If this match fails, this is the index to continue with. 1774 unsigned FailIndex; 1775 1776 /// NodeStack - The node stack when the scope was formed. 1777 SmallVector<SDValue, 4> NodeStack; 1778 1779 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1780 unsigned NumRecordedNodes; 1781 1782 /// NumMatchedMemRefs - The number of matched memref entries. 1783 unsigned NumMatchedMemRefs; 1784 1785 /// InputChain/InputFlag - The current chain/flag 1786 SDValue InputChain, InputFlag; 1787 1788 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1789 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1790}; 1791 1792} 1793 1794SDNode *SelectionDAGISel:: 1795SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1796 unsigned TableSize) { 1797 // FIXME: Should these even be selected? Handle these cases in the caller? 1798 switch (NodeToMatch->getOpcode()) { 1799 default: 1800 break; 1801 case ISD::EntryToken: // These nodes remain the same. 1802 case ISD::BasicBlock: 1803 case ISD::Register: 1804 //case ISD::VALUETYPE: 1805 //case ISD::CONDCODE: 1806 case ISD::HANDLENODE: 1807 case ISD::MDNODE_SDNODE: 1808 case ISD::TargetConstant: 1809 case ISD::TargetConstantFP: 1810 case ISD::TargetConstantPool: 1811 case ISD::TargetFrameIndex: 1812 case ISD::TargetExternalSymbol: 1813 case ISD::TargetBlockAddress: 1814 case ISD::TargetJumpTable: 1815 case ISD::TargetGlobalTLSAddress: 1816 case ISD::TargetGlobalAddress: 1817 case ISD::TokenFactor: 1818 case ISD::CopyFromReg: 1819 case ISD::CopyToReg: 1820 case ISD::EH_LABEL: 1821 NodeToMatch->setNodeId(-1); // Mark selected. 1822 return 0; 1823 case ISD::AssertSext: 1824 case ISD::AssertZext: 1825 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1826 NodeToMatch->getOperand(0)); 1827 return 0; 1828 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1829 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1830 } 1831 1832 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1833 1834 // Set up the node stack with NodeToMatch as the only node on the stack. 1835 SmallVector<SDValue, 8> NodeStack; 1836 SDValue N = SDValue(NodeToMatch, 0); 1837 NodeStack.push_back(N); 1838 1839 // MatchScopes - Scopes used when matching, if a match failure happens, this 1840 // indicates where to continue checking. 1841 SmallVector<MatchScope, 8> MatchScopes; 1842 1843 // RecordedNodes - This is the set of nodes that have been recorded by the 1844 // state machine. 1845 SmallVector<SDValue, 8> RecordedNodes; 1846 1847 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1848 // pattern. 1849 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1850 1851 // These are the current input chain and flag for use when generating nodes. 1852 // Various Emit operations change these. For example, emitting a copytoreg 1853 // uses and updates these. 1854 SDValue InputChain, InputFlag; 1855 1856 // ChainNodesMatched - If a pattern matches nodes that have input/output 1857 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1858 // which ones they are. The result is captured into this list so that we can 1859 // update the chain results when the pattern is complete. 1860 SmallVector<SDNode*, 3> ChainNodesMatched; 1861 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1862 1863 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1864 NodeToMatch->dump(CurDAG); 1865 errs() << '\n'); 1866 1867 // Determine where to start the interpreter. Normally we start at opcode #0, 1868 // but if the state machine starts with an OPC_SwitchOpcode, then we 1869 // accelerate the first lookup (which is guaranteed to be hot) with the 1870 // OpcodeOffset table. 1871 unsigned MatcherIndex = 0; 1872 1873 if (!OpcodeOffset.empty()) { 1874 // Already computed the OpcodeOffset table, just index into it. 1875 if (N.getOpcode() < OpcodeOffset.size()) 1876 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1877 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1878 1879 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1880 // Otherwise, the table isn't computed, but the state machine does start 1881 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1882 // is the first time we're selecting an instruction. 1883 unsigned Idx = 1; 1884 while (1) { 1885 // Get the size of this case. 1886 unsigned CaseSize = MatcherTable[Idx++]; 1887 if (CaseSize & 128) 1888 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1889 if (CaseSize == 0) break; 1890 1891 // Get the opcode, add the index to the table. 1892 uint16_t Opc = MatcherTable[Idx++]; 1893 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1894 if (Opc >= OpcodeOffset.size()) 1895 OpcodeOffset.resize((Opc+1)*2); 1896 OpcodeOffset[Opc] = Idx; 1897 Idx += CaseSize; 1898 } 1899 1900 // Okay, do the lookup for the first opcode. 1901 if (N.getOpcode() < OpcodeOffset.size()) 1902 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1903 } 1904 1905 while (1) { 1906 assert(MatcherIndex < TableSize && "Invalid index"); 1907#ifndef NDEBUG 1908 unsigned CurrentOpcodeIndex = MatcherIndex; 1909#endif 1910 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1911 switch (Opcode) { 1912 case OPC_Scope: { 1913 // Okay, the semantics of this operation are that we should push a scope 1914 // then evaluate the first child. However, pushing a scope only to have 1915 // the first check fail (which then pops it) is inefficient. If we can 1916 // determine immediately that the first check (or first several) will 1917 // immediately fail, don't even bother pushing a scope for them. 1918 unsigned FailIndex; 1919 1920 while (1) { 1921 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1922 if (NumToSkip & 128) 1923 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1924 // Found the end of the scope with no match. 1925 if (NumToSkip == 0) { 1926 FailIndex = 0; 1927 break; 1928 } 1929 1930 FailIndex = MatcherIndex+NumToSkip; 1931 1932 unsigned MatcherIndexOfPredicate = MatcherIndex; 1933 (void)MatcherIndexOfPredicate; // silence warning. 1934 1935 // If we can't evaluate this predicate without pushing a scope (e.g. if 1936 // it is a 'MoveParent') or if the predicate succeeds on this node, we 1937 // push the scope and evaluate the full predicate chain. 1938 bool Result; 1939 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 1940 Result, *this, RecordedNodes); 1941 if (!Result) 1942 break; 1943 1944 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 1945 << "index " << MatcherIndexOfPredicate 1946 << ", continuing at " << FailIndex << "\n"); 1947 ++NumDAGIselRetries; 1948 1949 // Otherwise, we know that this case of the Scope is guaranteed to fail, 1950 // move to the next case. 1951 MatcherIndex = FailIndex; 1952 } 1953 1954 // If the whole scope failed to match, bail. 1955 if (FailIndex == 0) break; 1956 1957 // Push a MatchScope which indicates where to go if the first child fails 1958 // to match. 1959 MatchScope NewEntry; 1960 NewEntry.FailIndex = FailIndex; 1961 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1962 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1963 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1964 NewEntry.InputChain = InputChain; 1965 NewEntry.InputFlag = InputFlag; 1966 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1967 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1968 MatchScopes.push_back(NewEntry); 1969 continue; 1970 } 1971 case OPC_RecordNode: 1972 // Remember this node, it may end up being an operand in the pattern. 1973 RecordedNodes.push_back(N); 1974 continue; 1975 1976 case OPC_RecordChild0: case OPC_RecordChild1: 1977 case OPC_RecordChild2: case OPC_RecordChild3: 1978 case OPC_RecordChild4: case OPC_RecordChild5: 1979 case OPC_RecordChild6: case OPC_RecordChild7: { 1980 unsigned ChildNo = Opcode-OPC_RecordChild0; 1981 if (ChildNo >= N.getNumOperands()) 1982 break; // Match fails if out of range child #. 1983 1984 RecordedNodes.push_back(N->getOperand(ChildNo)); 1985 continue; 1986 } 1987 case OPC_RecordMemRef: 1988 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 1989 continue; 1990 1991 case OPC_CaptureFlagInput: 1992 // If the current node has an input flag, capture it in InputFlag. 1993 if (N->getNumOperands() != 0 && 1994 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 1995 InputFlag = N->getOperand(N->getNumOperands()-1); 1996 continue; 1997 1998 case OPC_MoveChild: { 1999 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2000 if (ChildNo >= N.getNumOperands()) 2001 break; // Match fails if out of range child #. 2002 N = N.getOperand(ChildNo); 2003 NodeStack.push_back(N); 2004 continue; 2005 } 2006 2007 case OPC_MoveParent: 2008 // Pop the current node off the NodeStack. 2009 NodeStack.pop_back(); 2010 assert(!NodeStack.empty() && "Node stack imbalance!"); 2011 N = NodeStack.back(); 2012 continue; 2013 2014 case OPC_CheckSame: 2015 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2016 continue; 2017 case OPC_CheckPatternPredicate: 2018 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2019 continue; 2020 case OPC_CheckPredicate: 2021 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2022 N.getNode())) 2023 break; 2024 continue; 2025 case OPC_CheckComplexPat: { 2026 unsigned CPNum = MatcherTable[MatcherIndex++]; 2027 unsigned RecNo = MatcherTable[MatcherIndex++]; 2028 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2029 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2030 RecordedNodes)) 2031 break; 2032 continue; 2033 } 2034 case OPC_CheckOpcode: 2035 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2036 continue; 2037 2038 case OPC_CheckType: 2039 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2040 continue; 2041 2042 case OPC_SwitchOpcode: { 2043 unsigned CurNodeOpcode = N.getOpcode(); 2044 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2045 unsigned CaseSize; 2046 while (1) { 2047 // Get the size of this case. 2048 CaseSize = MatcherTable[MatcherIndex++]; 2049 if (CaseSize & 128) 2050 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2051 if (CaseSize == 0) break; 2052 2053 uint16_t Opc = MatcherTable[MatcherIndex++]; 2054 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2055 2056 // If the opcode matches, then we will execute this case. 2057 if (CurNodeOpcode == Opc) 2058 break; 2059 2060 // Otherwise, skip over this case. 2061 MatcherIndex += CaseSize; 2062 } 2063 2064 // If no cases matched, bail out. 2065 if (CaseSize == 0) break; 2066 2067 // Otherwise, execute the case we found. 2068 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2069 << " to " << MatcherIndex << "\n"); 2070 continue; 2071 } 2072 2073 case OPC_SwitchType: { 2074 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2075 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2076 unsigned CaseSize; 2077 while (1) { 2078 // Get the size of this case. 2079 CaseSize = MatcherTable[MatcherIndex++]; 2080 if (CaseSize & 128) 2081 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2082 if (CaseSize == 0) break; 2083 2084 MVT::SimpleValueType CaseVT = 2085 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2086 if (CaseVT == MVT::iPTR) 2087 CaseVT = TLI.getPointerTy().SimpleTy; 2088 2089 // If the VT matches, then we will execute this case. 2090 if (CurNodeVT == CaseVT) 2091 break; 2092 2093 // Otherwise, skip over this case. 2094 MatcherIndex += CaseSize; 2095 } 2096 2097 // If no cases matched, bail out. 2098 if (CaseSize == 0) break; 2099 2100 // Otherwise, execute the case we found. 2101 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2102 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2103 continue; 2104 } 2105 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2106 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2107 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2108 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2109 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2110 Opcode-OPC_CheckChild0Type)) 2111 break; 2112 continue; 2113 case OPC_CheckCondCode: 2114 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2115 continue; 2116 case OPC_CheckValueType: 2117 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2118 continue; 2119 case OPC_CheckInteger: 2120 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2121 continue; 2122 case OPC_CheckAndImm: 2123 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2124 continue; 2125 case OPC_CheckOrImm: 2126 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2127 continue; 2128 2129 case OPC_CheckFoldableChainNode: { 2130 assert(NodeStack.size() != 1 && "No parent node"); 2131 // Verify that all intermediate nodes between the root and this one have 2132 // a single use. 2133 bool HasMultipleUses = false; 2134 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2135 if (!NodeStack[i].hasOneUse()) { 2136 HasMultipleUses = true; 2137 break; 2138 } 2139 if (HasMultipleUses) break; 2140 2141 // Check to see that the target thinks this is profitable to fold and that 2142 // we can fold it without inducing cycles in the graph. 2143 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2144 NodeToMatch) || 2145 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2146 NodeToMatch, OptLevel, 2147 true/*We validate our own chains*/)) 2148 break; 2149 2150 continue; 2151 } 2152 case OPC_EmitInteger: { 2153 MVT::SimpleValueType VT = 2154 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2155 int64_t Val = MatcherTable[MatcherIndex++]; 2156 if (Val & 128) 2157 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2158 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2159 continue; 2160 } 2161 case OPC_EmitRegister: { 2162 MVT::SimpleValueType VT = 2163 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2164 unsigned RegNo = MatcherTable[MatcherIndex++]; 2165 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2166 continue; 2167 } 2168 2169 case OPC_EmitConvertToTarget: { 2170 // Convert from IMM/FPIMM to target version. 2171 unsigned RecNo = MatcherTable[MatcherIndex++]; 2172 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2173 SDValue Imm = RecordedNodes[RecNo]; 2174 2175 if (Imm->getOpcode() == ISD::Constant) { 2176 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2177 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2178 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2179 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2180 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2181 } 2182 2183 RecordedNodes.push_back(Imm); 2184 continue; 2185 } 2186 2187 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2188 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2189 // These are space-optimized forms of OPC_EmitMergeInputChains. 2190 assert(InputChain.getNode() == 0 && 2191 "EmitMergeInputChains should be the first chain producing node"); 2192 assert(ChainNodesMatched.empty() && 2193 "Should only have one EmitMergeInputChains per match"); 2194 2195 // Read all of the chained nodes. 2196 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2197 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2198 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2199 2200 // FIXME: What if other value results of the node have uses not matched 2201 // by this pattern? 2202 if (ChainNodesMatched.back() != NodeToMatch && 2203 !RecordedNodes[RecNo].hasOneUse()) { 2204 ChainNodesMatched.clear(); 2205 break; 2206 } 2207 2208 // Merge the input chains if they are not intra-pattern references. 2209 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2210 2211 if (InputChain.getNode() == 0) 2212 break; // Failed to merge. 2213 continue; 2214 } 2215 2216 case OPC_EmitMergeInputChains: { 2217 assert(InputChain.getNode() == 0 && 2218 "EmitMergeInputChains should be the first chain producing node"); 2219 // This node gets a list of nodes we matched in the input that have 2220 // chains. We want to token factor all of the input chains to these nodes 2221 // together. However, if any of the input chains is actually one of the 2222 // nodes matched in this pattern, then we have an intra-match reference. 2223 // Ignore these because the newly token factored chain should not refer to 2224 // the old nodes. 2225 unsigned NumChains = MatcherTable[MatcherIndex++]; 2226 assert(NumChains != 0 && "Can't TF zero chains"); 2227 2228 assert(ChainNodesMatched.empty() && 2229 "Should only have one EmitMergeInputChains per match"); 2230 2231 // Read all of the chained nodes. 2232 for (unsigned i = 0; i != NumChains; ++i) { 2233 unsigned RecNo = MatcherTable[MatcherIndex++]; 2234 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2235 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2236 2237 // FIXME: What if other value results of the node have uses not matched 2238 // by this pattern? 2239 if (ChainNodesMatched.back() != NodeToMatch && 2240 !RecordedNodes[RecNo].hasOneUse()) { 2241 ChainNodesMatched.clear(); 2242 break; 2243 } 2244 } 2245 2246 // If the inner loop broke out, the match fails. 2247 if (ChainNodesMatched.empty()) 2248 break; 2249 2250 // Merge the input chains if they are not intra-pattern references. 2251 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2252 2253 if (InputChain.getNode() == 0) 2254 break; // Failed to merge. 2255 2256 continue; 2257 } 2258 2259 case OPC_EmitCopyToReg: { 2260 unsigned RecNo = MatcherTable[MatcherIndex++]; 2261 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2262 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2263 2264 if (InputChain.getNode() == 0) 2265 InputChain = CurDAG->getEntryNode(); 2266 2267 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2268 DestPhysReg, RecordedNodes[RecNo], 2269 InputFlag); 2270 2271 InputFlag = InputChain.getValue(1); 2272 continue; 2273 } 2274 2275 case OPC_EmitNodeXForm: { 2276 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2277 unsigned RecNo = MatcherTable[MatcherIndex++]; 2278 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2279 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2280 continue; 2281 } 2282 2283 case OPC_EmitNode: 2284 case OPC_MorphNodeTo: { 2285 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2286 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2287 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2288 // Get the result VT list. 2289 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2290 SmallVector<EVT, 4> VTs; 2291 for (unsigned i = 0; i != NumVTs; ++i) { 2292 MVT::SimpleValueType VT = 2293 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2294 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2295 VTs.push_back(VT); 2296 } 2297 2298 if (EmitNodeInfo & OPFL_Chain) 2299 VTs.push_back(MVT::Other); 2300 if (EmitNodeInfo & OPFL_FlagOutput) 2301 VTs.push_back(MVT::Flag); 2302 2303 // This is hot code, so optimize the two most common cases of 1 and 2 2304 // results. 2305 SDVTList VTList; 2306 if (VTs.size() == 1) 2307 VTList = CurDAG->getVTList(VTs[0]); 2308 else if (VTs.size() == 2) 2309 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2310 else 2311 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2312 2313 // Get the operand list. 2314 unsigned NumOps = MatcherTable[MatcherIndex++]; 2315 SmallVector<SDValue, 8> Ops; 2316 for (unsigned i = 0; i != NumOps; ++i) { 2317 unsigned RecNo = MatcherTable[MatcherIndex++]; 2318 if (RecNo & 128) 2319 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2320 2321 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2322 Ops.push_back(RecordedNodes[RecNo]); 2323 } 2324 2325 // If there are variadic operands to add, handle them now. 2326 if (EmitNodeInfo & OPFL_VariadicInfo) { 2327 // Determine the start index to copy from. 2328 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2329 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2330 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2331 "Invalid variadic node"); 2332 // Copy all of the variadic operands, not including a potential flag 2333 // input. 2334 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2335 i != e; ++i) { 2336 SDValue V = NodeToMatch->getOperand(i); 2337 if (V.getValueType() == MVT::Flag) break; 2338 Ops.push_back(V); 2339 } 2340 } 2341 2342 // If this has chain/flag inputs, add them. 2343 if (EmitNodeInfo & OPFL_Chain) 2344 Ops.push_back(InputChain); 2345 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2346 Ops.push_back(InputFlag); 2347 2348 // Create the node. 2349 SDNode *Res = 0; 2350 if (Opcode != OPC_MorphNodeTo) { 2351 // If this is a normal EmitNode command, just create the new node and 2352 // add the results to the RecordedNodes list. 2353 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2354 VTList, Ops.data(), Ops.size()); 2355 2356 // Add all the non-flag/non-chain results to the RecordedNodes list. 2357 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2358 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2359 RecordedNodes.push_back(SDValue(Res, i)); 2360 } 2361 2362 } else { 2363 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2364 EmitNodeInfo); 2365 } 2366 2367 // If the node had chain/flag results, update our notion of the current 2368 // chain and flag. 2369 if (EmitNodeInfo & OPFL_FlagOutput) { 2370 InputFlag = SDValue(Res, VTs.size()-1); 2371 if (EmitNodeInfo & OPFL_Chain) 2372 InputChain = SDValue(Res, VTs.size()-2); 2373 } else if (EmitNodeInfo & OPFL_Chain) 2374 InputChain = SDValue(Res, VTs.size()-1); 2375 2376 // If the OPFL_MemRefs flag is set on this node, slap all of the 2377 // accumulated memrefs onto it. 2378 // 2379 // FIXME: This is vastly incorrect for patterns with multiple outputs 2380 // instructions that access memory and for ComplexPatterns that match 2381 // loads. 2382 if (EmitNodeInfo & OPFL_MemRefs) { 2383 MachineSDNode::mmo_iterator MemRefs = 2384 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2385 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2386 cast<MachineSDNode>(Res) 2387 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2388 } 2389 2390 DEBUG(errs() << " " 2391 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2392 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2393 2394 // If this was a MorphNodeTo then we're completely done! 2395 if (Opcode == OPC_MorphNodeTo) { 2396 // Update chain and flag uses. 2397 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2398 InputFlag, FlagResultNodesMatched, true); 2399 return Res; 2400 } 2401 2402 continue; 2403 } 2404 2405 case OPC_MarkFlagResults: { 2406 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2407 2408 // Read and remember all the flag-result nodes. 2409 for (unsigned i = 0; i != NumNodes; ++i) { 2410 unsigned RecNo = MatcherTable[MatcherIndex++]; 2411 if (RecNo & 128) 2412 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2413 2414 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2415 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2416 } 2417 continue; 2418 } 2419 2420 case OPC_CompleteMatch: { 2421 // The match has been completed, and any new nodes (if any) have been 2422 // created. Patch up references to the matched dag to use the newly 2423 // created nodes. 2424 unsigned NumResults = MatcherTable[MatcherIndex++]; 2425 2426 for (unsigned i = 0; i != NumResults; ++i) { 2427 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2428 if (ResSlot & 128) 2429 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2430 2431 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2432 SDValue Res = RecordedNodes[ResSlot]; 2433 2434 assert(i < NodeToMatch->getNumValues() && 2435 NodeToMatch->getValueType(i) != MVT::Other && 2436 NodeToMatch->getValueType(i) != MVT::Flag && 2437 "Invalid number of results to complete!"); 2438 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2439 NodeToMatch->getValueType(i) == MVT::iPTR || 2440 Res.getValueType() == MVT::iPTR || 2441 NodeToMatch->getValueType(i).getSizeInBits() == 2442 Res.getValueType().getSizeInBits()) && 2443 "invalid replacement"); 2444 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2445 } 2446 2447 // If the root node defines a flag, add it to the flag nodes to update 2448 // list. 2449 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2450 FlagResultNodesMatched.push_back(NodeToMatch); 2451 2452 // Update chain and flag uses. 2453 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2454 InputFlag, FlagResultNodesMatched, false); 2455 2456 assert(NodeToMatch->use_empty() && 2457 "Didn't replace all uses of the node?"); 2458 2459 // FIXME: We just return here, which interacts correctly with SelectRoot 2460 // above. We should fix this to not return an SDNode* anymore. 2461 return 0; 2462 } 2463 } 2464 2465 // If the code reached this point, then the match failed. See if there is 2466 // another child to try in the current 'Scope', otherwise pop it until we 2467 // find a case to check. 2468 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2469 ++NumDAGIselRetries; 2470 while (1) { 2471 if (MatchScopes.empty()) { 2472 CannotYetSelect(NodeToMatch); 2473 return 0; 2474 } 2475 2476 // Restore the interpreter state back to the point where the scope was 2477 // formed. 2478 MatchScope &LastScope = MatchScopes.back(); 2479 RecordedNodes.resize(LastScope.NumRecordedNodes); 2480 NodeStack.clear(); 2481 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2482 N = NodeStack.back(); 2483 2484 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2485 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2486 MatcherIndex = LastScope.FailIndex; 2487 2488 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2489 2490 InputChain = LastScope.InputChain; 2491 InputFlag = LastScope.InputFlag; 2492 if (!LastScope.HasChainNodesMatched) 2493 ChainNodesMatched.clear(); 2494 if (!LastScope.HasFlagResultNodesMatched) 2495 FlagResultNodesMatched.clear(); 2496 2497 // Check to see what the offset is at the new MatcherIndex. If it is zero 2498 // we have reached the end of this scope, otherwise we have another child 2499 // in the current scope to try. 2500 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2501 if (NumToSkip & 128) 2502 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2503 2504 // If we have another child in this scope to match, update FailIndex and 2505 // try it. 2506 if (NumToSkip != 0) { 2507 LastScope.FailIndex = MatcherIndex+NumToSkip; 2508 break; 2509 } 2510 2511 // End of this scope, pop it and try the next child in the containing 2512 // scope. 2513 MatchScopes.pop_back(); 2514 } 2515 } 2516} 2517 2518 2519 2520void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2521 std::string msg; 2522 raw_string_ostream Msg(msg); 2523 Msg << "Cannot yet select: "; 2524 2525 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2526 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2527 N->getOpcode() != ISD::INTRINSIC_VOID) { 2528 N->printrFull(Msg, CurDAG); 2529 } else { 2530 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2531 unsigned iid = 2532 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2533 if (iid < Intrinsic::num_intrinsics) 2534 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2535 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2536 Msg << "target intrinsic %" << TII->getName(iid); 2537 else 2538 Msg << "unknown intrinsic #" << iid; 2539 } 2540 report_fatal_error(Msg.str()); 2541} 2542 2543char SelectionDAGISel::ID = 0; 2544