SelectionDAGISel.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAGISel.h" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/PostOrderIterator.h" 18#include "llvm/ADT/Statistic.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/BranchProbabilityInfo.h" 21#include "llvm/Analysis/CFG.h" 22#include "llvm/CodeGen/FastISel.h" 23#include "llvm/CodeGen/FunctionLoweringInfo.h" 24#include "llvm/CodeGen/GCMetadata.h" 25#include "llvm/CodeGen/GCStrategy.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 32#include "llvm/CodeGen/SchedulerRegistry.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/IR/Constants.h" 35#include "llvm/IR/DebugInfo.h" 36#include "llvm/IR/Function.h" 37#include "llvm/IR/InlineAsm.h" 38#include "llvm/IR/Instructions.h" 39#include "llvm/IR/IntrinsicInst.h" 40#include "llvm/IR/Intrinsics.h" 41#include "llvm/IR/LLVMContext.h" 42#include "llvm/IR/Module.h" 43#include "llvm/Support/Compiler.h" 44#include "llvm/Support/Debug.h" 45#include "llvm/Support/ErrorHandling.h" 46#include "llvm/Support/Timer.h" 47#include "llvm/Support/raw_ostream.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetMachine.h" 53#include "llvm/Target/TargetOptions.h" 54#include "llvm/Target/TargetRegisterInfo.h" 55#include "llvm/Target/TargetSubtargetInfo.h" 56#include "llvm/Transforms/Utils/BasicBlockUtils.h" 57#include <algorithm> 58using namespace llvm; 59 60#define DEBUG_TYPE "isel" 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 64STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 65STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 66STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 67STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 68STATISTIC(NumFastIselFailLowerArguments, 69 "Number of entry blocks where fast isel failed to lower arguments"); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 74 cl::desc("Enable extra verbose messages in the \"fast\" " 75 "instruction selector")); 76 77 // Terminators 78STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 79STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 80STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 81STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 82STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 83STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 84STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 85 86 // Standard binary operators... 87STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 88STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 89STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 90STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 91STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 92STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 93STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 94STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 95STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 96STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 97STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 98STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 99 100 // Logical operators... 101STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 102STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 103STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 104 105 // Memory instructions... 106STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 107STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 108STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 109STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 110STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 111STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 112STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 113 114 // Convert instructions... 115STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 116STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 117STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 118STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 119STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 120STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 121STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 122STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 123STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 124STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 125STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 126STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 127 128 // Other instructions... 129STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 130STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 131STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 132STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 133STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 134STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 135STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 136STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 137STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 138STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 139STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 140STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 141STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 142STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 143STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 144#endif 145 146static cl::opt<bool> 147EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 148 cl::desc("Enable verbose messages in the \"fast\" " 149 "instruction selector")); 150static cl::opt<bool> 151EnableFastISelAbort("fast-isel-abort", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower an instruction")); 154static cl::opt<bool> 155EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 156 cl::desc("Enable abort calls when \"fast\" instruction selection " 157 "fails to lower a formal argument")); 158 159static cl::opt<bool> 160UseMBPI("use-mbpi", 161 cl::desc("use Machine Branch Probability Info"), 162 cl::init(true), cl::Hidden); 163 164#ifndef NDEBUG 165static cl::opt<bool> 166ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the first " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before legalize types")); 172static cl::opt<bool> 173ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 174 cl::desc("Pop up a window to show dags before legalize")); 175static cl::opt<bool> 176ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the second " 178 "dag combine pass")); 179static cl::opt<bool> 180ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 181 cl::desc("Pop up a window to show dags before the post legalize types" 182 " dag combine pass")); 183static cl::opt<bool> 184ViewISelDAGs("view-isel-dags", cl::Hidden, 185 cl::desc("Pop up a window to show isel dags as they are selected")); 186static cl::opt<bool> 187ViewSchedDAGs("view-sched-dags", cl::Hidden, 188 cl::desc("Pop up a window to show sched dags as they are processed")); 189static cl::opt<bool> 190ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 191 cl::desc("Pop up a window to show SUnit dags after they are processed")); 192#else 193static const bool ViewDAGCombine1 = false, 194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 195 ViewDAGCombine2 = false, 196 ViewDAGCombineLT = false, 197 ViewISelDAGs = false, ViewSchedDAGs = false, 198 ViewSUnitDAGs = false; 199#endif 200 201//===---------------------------------------------------------------------===// 202/// 203/// RegisterScheduler class - Track the registration of instruction schedulers. 204/// 205//===---------------------------------------------------------------------===// 206MachinePassRegistry RegisterScheduler::Registry; 207 208//===---------------------------------------------------------------------===// 209/// 210/// ISHeuristic command line option for instruction schedulers. 211/// 212//===---------------------------------------------------------------------===// 213static cl::opt<RegisterScheduler::FunctionPassCtor, false, 214 RegisterPassParser<RegisterScheduler> > 215ISHeuristic("pre-RA-sched", 216 cl::init(&createDefaultScheduler), cl::Hidden, 217 cl::desc("Instruction schedulers available (before register" 218 " allocation):")); 219 220static RegisterScheduler 221defaultListDAGScheduler("default", "Best scheduler for the target", 222 createDefaultScheduler); 223 224namespace llvm { 225 //===--------------------------------------------------------------------===// 226 /// \brief This class is used by SelectionDAGISel to temporarily override 227 /// the optimization level on a per-function basis. 228 class OptLevelChanger { 229 SelectionDAGISel &IS; 230 CodeGenOpt::Level SavedOptLevel; 231 bool SavedFastISel; 232 233 public: 234 OptLevelChanger(SelectionDAGISel &ISel, 235 CodeGenOpt::Level NewOptLevel) : IS(ISel) { 236 SavedOptLevel = IS.OptLevel; 237 if (NewOptLevel == SavedOptLevel) 238 return; 239 IS.OptLevel = NewOptLevel; 240 IS.TM.setOptLevel(NewOptLevel); 241 SavedFastISel = IS.TM.Options.EnableFastISel; 242 if (NewOptLevel == CodeGenOpt::None) 243 IS.TM.setFastISel(true); 244 DEBUG(dbgs() << "\nChanging optimization level for Function " 245 << IS.MF->getFunction()->getName() << "\n"); 246 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel 247 << " ; After: -O" << NewOptLevel << "\n"); 248 } 249 250 ~OptLevelChanger() { 251 if (IS.OptLevel == SavedOptLevel) 252 return; 253 DEBUG(dbgs() << "\nRestoring optimization level for Function " 254 << IS.MF->getFunction()->getName() << "\n"); 255 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel 256 << " ; After: -O" << SavedOptLevel << "\n"); 257 IS.OptLevel = SavedOptLevel; 258 IS.TM.setOptLevel(SavedOptLevel); 259 IS.TM.setFastISel(SavedFastISel); 260 } 261 }; 262 263 //===--------------------------------------------------------------------===// 264 /// createDefaultScheduler - This creates an instruction scheduler appropriate 265 /// for the target. 266 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 267 CodeGenOpt::Level OptLevel) { 268 const TargetLowering *TLI = IS->getTargetLowering(); 269 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 270 271 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() || 272 TLI->getSchedulingPreference() == Sched::Source) 273 return createSourceListDAGScheduler(IS, OptLevel); 274 if (TLI->getSchedulingPreference() == Sched::RegPressure) 275 return createBURRListDAGScheduler(IS, OptLevel); 276 if (TLI->getSchedulingPreference() == Sched::Hybrid) 277 return createHybridListDAGScheduler(IS, OptLevel); 278 if (TLI->getSchedulingPreference() == Sched::VLIW) 279 return createVLIWDAGScheduler(IS, OptLevel); 280 assert(TLI->getSchedulingPreference() == Sched::ILP && 281 "Unknown sched type!"); 282 return createILPListDAGScheduler(IS, OptLevel); 283 } 284} 285 286// EmitInstrWithCustomInserter - This method should be implemented by targets 287// that mark instructions with the 'usesCustomInserter' flag. These 288// instructions are special in various ways, which require special support to 289// insert. The specified MachineInstr is created but not inserted into any 290// basic blocks, and this method is called to expand it into a sequence of 291// instructions, potentially also creating new basic blocks and control flow. 292// When new basic blocks are inserted and the edges from MBB to its successors 293// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 294// DenseMap. 295MachineBasicBlock * 296TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 297 MachineBasicBlock *MBB) const { 298#ifndef NDEBUG 299 dbgs() << "If a target marks an instruction with " 300 "'usesCustomInserter', it must implement " 301 "TargetLowering::EmitInstrWithCustomInserter!"; 302#endif 303 llvm_unreachable(nullptr); 304} 305 306void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 307 SDNode *Node) const { 308 assert(!MI->hasPostISelHook() && 309 "If a target marks an instruction with 'hasPostISelHook', " 310 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 311} 312 313//===----------------------------------------------------------------------===// 314// SelectionDAGISel code 315//===----------------------------------------------------------------------===// 316 317SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 318 CodeGenOpt::Level OL) : 319 MachineFunctionPass(ID), TM(tm), 320 FuncInfo(new FunctionLoweringInfo(TM)), 321 CurDAG(new SelectionDAG(tm, OL)), 322 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 323 GFI(), 324 OptLevel(OL), 325 DAGSize(0) { 326 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 327 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 328 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 329 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 330 } 331 332SelectionDAGISel::~SelectionDAGISel() { 333 delete SDB; 334 delete CurDAG; 335 delete FuncInfo; 336} 337 338void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 339 AU.addRequired<AliasAnalysis>(); 340 AU.addPreserved<AliasAnalysis>(); 341 AU.addRequired<GCModuleInfo>(); 342 AU.addPreserved<GCModuleInfo>(); 343 AU.addRequired<TargetLibraryInfo>(); 344 if (UseMBPI && OptLevel != CodeGenOpt::None) 345 AU.addRequired<BranchProbabilityInfo>(); 346 MachineFunctionPass::getAnalysisUsage(AU); 347} 348 349/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 350/// may trap on it. In this case we have to split the edge so that the path 351/// through the predecessor block that doesn't go to the phi block doesn't 352/// execute the possibly trapping instruction. 353/// 354/// This is required for correctness, so it must be done at -O0. 355/// 356static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 357 // Loop for blocks with phi nodes. 358 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 359 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 360 if (!PN) continue; 361 362 ReprocessBlock: 363 // For each block with a PHI node, check to see if any of the input values 364 // are potentially trapping constant expressions. Constant expressions are 365 // the only potentially trapping value that can occur as the argument to a 366 // PHI. 367 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 368 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 369 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 370 if (!CE || !CE->canTrap()) continue; 371 372 // The only case we have to worry about is when the edge is critical. 373 // Since this block has a PHI Node, we assume it has multiple input 374 // edges: check to see if the pred has multiple successors. 375 BasicBlock *Pred = PN->getIncomingBlock(i); 376 if (Pred->getTerminator()->getNumSuccessors() == 1) 377 continue; 378 379 // Okay, we have to split this edge. 380 SplitCriticalEdge(Pred->getTerminator(), 381 GetSuccessorNumber(Pred, BB), SDISel, true); 382 goto ReprocessBlock; 383 } 384 } 385} 386 387bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 388 // Do some sanity-checking on the command-line options. 389 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 390 "-fast-isel-verbose requires -fast-isel"); 391 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 392 "-fast-isel-abort requires -fast-isel"); 393 394 const Function &Fn = *mf.getFunction(); 395 const TargetInstrInfo &TII = *TM.getInstrInfo(); 396 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 397 const TargetLowering *TLI = TM.getTargetLowering(); 398 399 MF = &mf; 400 RegInfo = &MF->getRegInfo(); 401 AA = &getAnalysis<AliasAnalysis>(); 402 LibInfo = &getAnalysis<TargetLibraryInfo>(); 403 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr; 404 405 TargetSubtargetInfo &ST = 406 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 407 ST.resetSubtargetFeatures(MF); 408 TM.resetTargetOptions(MF); 409 410 // Reset OptLevel to None for optnone functions. 411 CodeGenOpt::Level NewOptLevel = OptLevel; 412 if (Fn.hasFnAttribute(Attribute::OptimizeNone)) 413 NewOptLevel = CodeGenOpt::None; 414 OptLevelChanger OLC(*this, NewOptLevel); 415 416 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 417 418 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 419 420 CurDAG->init(*MF, TLI); 421 FuncInfo->set(Fn, *MF, CurDAG); 422 423 if (UseMBPI && OptLevel != CodeGenOpt::None) 424 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 425 else 426 FuncInfo->BPI = nullptr; 427 428 SDB->init(GFI, *AA, LibInfo); 429 430 MF->setHasInlineAsm(false); 431 432 SelectAllBasicBlocks(Fn); 433 434 // If the first basic block in the function has live ins that need to be 435 // copied into vregs, emit the copies into the top of the block before 436 // emitting the code for the block. 437 MachineBasicBlock *EntryMBB = MF->begin(); 438 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 439 440 DenseMap<unsigned, unsigned> LiveInMap; 441 if (!FuncInfo->ArgDbgValues.empty()) 442 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 443 E = RegInfo->livein_end(); LI != E; ++LI) 444 if (LI->second) 445 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 446 447 // Insert DBG_VALUE instructions for function arguments to the entry block. 448 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 449 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 450 bool hasFI = MI->getOperand(0).isFI(); 451 unsigned Reg = 452 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 453 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 454 EntryMBB->insert(EntryMBB->begin(), MI); 455 else { 456 MachineInstr *Def = RegInfo->getVRegDef(Reg); 457 if (Def) { 458 MachineBasicBlock::iterator InsertPos = Def; 459 // FIXME: VR def may not be in entry block. 460 Def->getParent()->insert(std::next(InsertPos), MI); 461 } else 462 DEBUG(dbgs() << "Dropping debug info for dead vreg" 463 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 464 } 465 466 // If Reg is live-in then update debug info to track its copy in a vreg. 467 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 468 if (LDI != LiveInMap.end()) { 469 assert(!hasFI && "There's no handling of frame pointer updating here yet " 470 "- add if needed"); 471 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 472 MachineBasicBlock::iterator InsertPos = Def; 473 const MDNode *Variable = 474 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 475 bool IsIndirect = MI->isIndirectDebugValue(); 476 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 477 // Def is never a terminator here, so it is ok to increment InsertPos. 478 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 479 TII.get(TargetOpcode::DBG_VALUE), 480 IsIndirect, 481 LDI->second, Offset, Variable); 482 483 // If this vreg is directly copied into an exported register then 484 // that COPY instructions also need DBG_VALUE, if it is the only 485 // user of LDI->second. 486 MachineInstr *CopyUseMI = nullptr; 487 for (MachineRegisterInfo::use_instr_iterator 488 UI = RegInfo->use_instr_begin(LDI->second), 489 E = RegInfo->use_instr_end(); UI != E; ) { 490 MachineInstr *UseMI = &*(UI++); 491 if (UseMI->isDebugValue()) continue; 492 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 493 CopyUseMI = UseMI; continue; 494 } 495 // Otherwise this is another use or second copy use. 496 CopyUseMI = nullptr; break; 497 } 498 if (CopyUseMI) { 499 MachineInstr *NewMI = 500 BuildMI(*MF, CopyUseMI->getDebugLoc(), 501 TII.get(TargetOpcode::DBG_VALUE), 502 IsIndirect, 503 CopyUseMI->getOperand(0).getReg(), 504 Offset, Variable); 505 MachineBasicBlock::iterator Pos = CopyUseMI; 506 EntryMBB->insertAfter(Pos, NewMI); 507 } 508 } 509 } 510 511 // Determine if there are any calls in this machine function. 512 MachineFrameInfo *MFI = MF->getFrameInfo(); 513 for (const auto &MBB : *MF) { 514 if (MFI->hasCalls() && MF->hasInlineAsm()) 515 break; 516 517 for (const auto &MI : MBB) { 518 const MCInstrDesc &MCID = TM.getInstrInfo()->get(MI.getOpcode()); 519 if ((MCID.isCall() && !MCID.isReturn()) || 520 MI.isStackAligningInlineAsm()) { 521 MFI->setHasCalls(true); 522 } 523 if (MI.isInlineAsm()) { 524 MF->setHasInlineAsm(true); 525 } 526 } 527 } 528 529 // Determine if there is a call to setjmp in the machine function. 530 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 531 532 // Replace forward-declared registers with the registers containing 533 // the desired value. 534 MachineRegisterInfo &MRI = MF->getRegInfo(); 535 for (DenseMap<unsigned, unsigned>::iterator 536 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 537 I != E; ++I) { 538 unsigned From = I->first; 539 unsigned To = I->second; 540 // If To is also scheduled to be replaced, find what its ultimate 541 // replacement is. 542 for (;;) { 543 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 544 if (J == E) break; 545 To = J->second; 546 } 547 // Make sure the new register has a sufficiently constrained register class. 548 if (TargetRegisterInfo::isVirtualRegister(From) && 549 TargetRegisterInfo::isVirtualRegister(To)) 550 MRI.constrainRegClass(To, MRI.getRegClass(From)); 551 // Replace it. 552 MRI.replaceRegWith(From, To); 553 } 554 555 // Freeze the set of reserved registers now that MachineFrameInfo has been 556 // set up. All the information required by getReservedRegs() should be 557 // available now. 558 MRI.freezeReservedRegs(*MF); 559 560 // Release function-specific state. SDB and CurDAG are already cleared 561 // at this point. 562 FuncInfo->clear(); 563 564 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); 565 DEBUG(MF->print(dbgs())); 566 567 return true; 568} 569 570void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 571 BasicBlock::const_iterator End, 572 bool &HadTailCall) { 573 // Lower all of the non-terminator instructions. If a call is emitted 574 // as a tail call, cease emitting nodes for this block. Terminators 575 // are handled below. 576 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 577 SDB->visit(*I); 578 579 // Make sure the root of the DAG is up-to-date. 580 CurDAG->setRoot(SDB->getControlRoot()); 581 HadTailCall = SDB->HasTailCall; 582 SDB->clear(); 583 584 // Final step, emit the lowered DAG as machine code. 585 CodeGenAndEmitDAG(); 586} 587 588void SelectionDAGISel::ComputeLiveOutVRegInfo() { 589 SmallPtrSet<SDNode*, 128> VisitedNodes; 590 SmallVector<SDNode*, 128> Worklist; 591 592 Worklist.push_back(CurDAG->getRoot().getNode()); 593 594 APInt KnownZero; 595 APInt KnownOne; 596 597 do { 598 SDNode *N = Worklist.pop_back_val(); 599 600 // If we've already seen this node, ignore it. 601 if (!VisitedNodes.insert(N)) 602 continue; 603 604 // Otherwise, add all chain operands to the worklist. 605 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 606 if (N->getOperand(i).getValueType() == MVT::Other) 607 Worklist.push_back(N->getOperand(i).getNode()); 608 609 // If this is a CopyToReg with a vreg dest, process it. 610 if (N->getOpcode() != ISD::CopyToReg) 611 continue; 612 613 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 614 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 615 continue; 616 617 // Ignore non-scalar or non-integer values. 618 SDValue Src = N->getOperand(2); 619 EVT SrcVT = Src.getValueType(); 620 if (!SrcVT.isInteger() || SrcVT.isVector()) 621 continue; 622 623 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 624 CurDAG->computeKnownBits(Src, KnownZero, KnownOne); 625 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 626 } while (!Worklist.empty()); 627} 628 629void SelectionDAGISel::CodeGenAndEmitDAG() { 630 std::string GroupName; 631 if (TimePassesIsEnabled) 632 GroupName = "Instruction Selection and Scheduling"; 633 std::string BlockName; 634 int BlockNumber = -1; 635 (void)BlockNumber; 636#ifdef NDEBUG 637 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 638 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 639 ViewSUnitDAGs) 640#endif 641 { 642 BlockNumber = FuncInfo->MBB->getNumber(); 643 BlockName = MF->getName().str() + ":" + 644 FuncInfo->MBB->getBasicBlock()->getName().str(); 645 } 646 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 647 << " '" << BlockName << "'\n"; CurDAG->dump()); 648 649 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 650 651 // Run the DAG combiner in pre-legalize mode. 652 { 653 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 654 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 655 } 656 657 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 658 << " '" << BlockName << "'\n"; CurDAG->dump()); 659 660 // Second step, hack on the DAG until it only uses operations and types that 661 // the target supports. 662 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 663 BlockName); 664 665 bool Changed; 666 { 667 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 668 Changed = CurDAG->LegalizeTypes(); 669 } 670 671 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 672 << " '" << BlockName << "'\n"; CurDAG->dump()); 673 674 CurDAG->NewNodesMustHaveLegalTypes = true; 675 676 if (Changed) { 677 if (ViewDAGCombineLT) 678 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 679 680 // Run the DAG combiner in post-type-legalize mode. 681 { 682 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 683 TimePassesIsEnabled); 684 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 685 } 686 687 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 688 << " '" << BlockName << "'\n"; CurDAG->dump()); 689 690 } 691 692 { 693 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 694 Changed = CurDAG->LegalizeVectors(); 695 } 696 697 if (Changed) { 698 { 699 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 700 CurDAG->LegalizeTypes(); 701 } 702 703 if (ViewDAGCombineLT) 704 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 705 706 // Run the DAG combiner in post-type-legalize mode. 707 { 708 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 709 TimePassesIsEnabled); 710 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 711 } 712 713 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 714 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 715 } 716 717 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 718 719 { 720 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 721 CurDAG->Legalize(); 722 } 723 724 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 725 << " '" << BlockName << "'\n"; CurDAG->dump()); 726 727 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 728 729 // Run the DAG combiner in post-legalize mode. 730 { 731 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 732 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 733 } 734 735 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 736 << " '" << BlockName << "'\n"; CurDAG->dump()); 737 738 if (OptLevel != CodeGenOpt::None) 739 ComputeLiveOutVRegInfo(); 740 741 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 742 743 // Third, instruction select all of the operations to machine code, adding the 744 // code to the MachineBasicBlock. 745 { 746 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 747 DoInstructionSelection(); 748 } 749 750 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 751 << " '" << BlockName << "'\n"; CurDAG->dump()); 752 753 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 754 755 // Schedule machine code. 756 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 757 { 758 NamedRegionTimer T("Instruction Scheduling", GroupName, 759 TimePassesIsEnabled); 760 Scheduler->Run(CurDAG, FuncInfo->MBB); 761 } 762 763 if (ViewSUnitDAGs) Scheduler->viewGraph(); 764 765 // Emit machine code to BB. This can change 'BB' to the last block being 766 // inserted into. 767 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 768 { 769 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 770 771 // FuncInfo->InsertPt is passed by reference and set to the end of the 772 // scheduled instructions. 773 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 774 } 775 776 // If the block was split, make sure we update any references that are used to 777 // update PHI nodes later on. 778 if (FirstMBB != LastMBB) 779 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 780 781 // Free the scheduler state. 782 { 783 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 784 TimePassesIsEnabled); 785 delete Scheduler; 786 } 787 788 // Free the SelectionDAG state, now that we're finished with it. 789 CurDAG->clear(); 790} 791 792namespace { 793/// ISelUpdater - helper class to handle updates of the instruction selection 794/// graph. 795class ISelUpdater : public SelectionDAG::DAGUpdateListener { 796 SelectionDAG::allnodes_iterator &ISelPosition; 797public: 798 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 799 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 800 801 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 802 /// deleted is the current ISelPosition node, update ISelPosition. 803 /// 804 void NodeDeleted(SDNode *N, SDNode *E) override { 805 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 806 ++ISelPosition; 807 } 808}; 809} // end anonymous namespace 810 811void SelectionDAGISel::DoInstructionSelection() { 812 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 813 << FuncInfo->MBB->getNumber() 814 << " '" << FuncInfo->MBB->getName() << "'\n"); 815 816 PreprocessISelDAG(); 817 818 // Select target instructions for the DAG. 819 { 820 // Number all nodes with a topological order and set DAGSize. 821 DAGSize = CurDAG->AssignTopologicalOrder(); 822 823 // Create a dummy node (which is not added to allnodes), that adds 824 // a reference to the root node, preventing it from being deleted, 825 // and tracking any changes of the root. 826 HandleSDNode Dummy(CurDAG->getRoot()); 827 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 828 ++ISelPosition; 829 830 // Make sure that ISelPosition gets properly updated when nodes are deleted 831 // in calls made from this function. 832 ISelUpdater ISU(*CurDAG, ISelPosition); 833 834 // The AllNodes list is now topological-sorted. Visit the 835 // nodes by starting at the end of the list (the root of the 836 // graph) and preceding back toward the beginning (the entry 837 // node). 838 while (ISelPosition != CurDAG->allnodes_begin()) { 839 SDNode *Node = --ISelPosition; 840 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 841 // but there are currently some corner cases that it misses. Also, this 842 // makes it theoretically possible to disable the DAGCombiner. 843 if (Node->use_empty()) 844 continue; 845 846 SDNode *ResNode = Select(Node); 847 848 // FIXME: This is pretty gross. 'Select' should be changed to not return 849 // anything at all and this code should be nuked with a tactical strike. 850 851 // If node should not be replaced, continue with the next one. 852 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 853 continue; 854 // Replace node. 855 if (ResNode) { 856 ReplaceUses(Node, ResNode); 857 } 858 859 // If after the replacement this node is not used any more, 860 // remove this dead node. 861 if (Node->use_empty()) // Don't delete EntryToken, etc. 862 CurDAG->RemoveDeadNode(Node); 863 } 864 865 CurDAG->setRoot(Dummy.getValue()); 866 } 867 868 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 869 870 PostprocessISelDAG(); 871} 872 873/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 874/// do other setup for EH landing-pad blocks. 875void SelectionDAGISel::PrepareEHLandingPad() { 876 MachineBasicBlock *MBB = FuncInfo->MBB; 877 878 // Add a label to mark the beginning of the landing pad. Deletion of the 879 // landing pad can thus be detected via the MachineModuleInfo. 880 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 881 882 // Assign the call site to the landing pad's begin label. 883 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 884 885 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 886 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 887 .addSym(Label); 888 889 // Mark exception register as live in. 890 const TargetLowering *TLI = getTargetLowering(); 891 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 892 if (unsigned Reg = TLI->getExceptionPointerRegister()) 893 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 894 895 // Mark exception selector register as live in. 896 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 897 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 898} 899 900/// isFoldedOrDeadInstruction - Return true if the specified instruction is 901/// side-effect free and is either dead or folded into a generated instruction. 902/// Return false if it needs to be emitted. 903static bool isFoldedOrDeadInstruction(const Instruction *I, 904 FunctionLoweringInfo *FuncInfo) { 905 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 906 !isa<TerminatorInst>(I) && // Terminators aren't folded. 907 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 908 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 909 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 910} 911 912#ifndef NDEBUG 913// Collect per Instruction statistics for fast-isel misses. Only those 914// instructions that cause the bail are accounted for. It does not account for 915// instructions higher in the block. Thus, summing the per instructions stats 916// will not add up to what is reported by NumFastIselFailures. 917static void collectFailStats(const Instruction *I) { 918 switch (I->getOpcode()) { 919 default: assert (0 && "<Invalid operator> "); 920 921 // Terminators 922 case Instruction::Ret: NumFastIselFailRet++; return; 923 case Instruction::Br: NumFastIselFailBr++; return; 924 case Instruction::Switch: NumFastIselFailSwitch++; return; 925 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 926 case Instruction::Invoke: NumFastIselFailInvoke++; return; 927 case Instruction::Resume: NumFastIselFailResume++; return; 928 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 929 930 // Standard binary operators... 931 case Instruction::Add: NumFastIselFailAdd++; return; 932 case Instruction::FAdd: NumFastIselFailFAdd++; return; 933 case Instruction::Sub: NumFastIselFailSub++; return; 934 case Instruction::FSub: NumFastIselFailFSub++; return; 935 case Instruction::Mul: NumFastIselFailMul++; return; 936 case Instruction::FMul: NumFastIselFailFMul++; return; 937 case Instruction::UDiv: NumFastIselFailUDiv++; return; 938 case Instruction::SDiv: NumFastIselFailSDiv++; return; 939 case Instruction::FDiv: NumFastIselFailFDiv++; return; 940 case Instruction::URem: NumFastIselFailURem++; return; 941 case Instruction::SRem: NumFastIselFailSRem++; return; 942 case Instruction::FRem: NumFastIselFailFRem++; return; 943 944 // Logical operators... 945 case Instruction::And: NumFastIselFailAnd++; return; 946 case Instruction::Or: NumFastIselFailOr++; return; 947 case Instruction::Xor: NumFastIselFailXor++; return; 948 949 // Memory instructions... 950 case Instruction::Alloca: NumFastIselFailAlloca++; return; 951 case Instruction::Load: NumFastIselFailLoad++; return; 952 case Instruction::Store: NumFastIselFailStore++; return; 953 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 954 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 955 case Instruction::Fence: NumFastIselFailFence++; return; 956 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 957 958 // Convert instructions... 959 case Instruction::Trunc: NumFastIselFailTrunc++; return; 960 case Instruction::ZExt: NumFastIselFailZExt++; return; 961 case Instruction::SExt: NumFastIselFailSExt++; return; 962 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 963 case Instruction::FPExt: NumFastIselFailFPExt++; return; 964 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 965 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 966 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 967 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 968 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 969 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 970 case Instruction::BitCast: NumFastIselFailBitCast++; return; 971 972 // Other instructions... 973 case Instruction::ICmp: NumFastIselFailICmp++; return; 974 case Instruction::FCmp: NumFastIselFailFCmp++; return; 975 case Instruction::PHI: NumFastIselFailPHI++; return; 976 case Instruction::Select: NumFastIselFailSelect++; return; 977 case Instruction::Call: NumFastIselFailCall++; return; 978 case Instruction::Shl: NumFastIselFailShl++; return; 979 case Instruction::LShr: NumFastIselFailLShr++; return; 980 case Instruction::AShr: NumFastIselFailAShr++; return; 981 case Instruction::VAArg: NumFastIselFailVAArg++; return; 982 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 983 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 984 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 985 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 986 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 987 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 988 } 989} 990#endif 991 992void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 993 // Initialize the Fast-ISel state, if needed. 994 FastISel *FastIS = nullptr; 995 if (TM.Options.EnableFastISel) 996 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 997 998 // Iterate over all basic blocks in the function. 999 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 1000 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1001 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1002 const BasicBlock *LLVMBB = *I; 1003 1004 if (OptLevel != CodeGenOpt::None) { 1005 bool AllPredsVisited = true; 1006 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1007 PI != PE; ++PI) { 1008 if (!FuncInfo->VisitedBBs.count(*PI)) { 1009 AllPredsVisited = false; 1010 break; 1011 } 1012 } 1013 1014 if (AllPredsVisited) { 1015 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1016 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1017 FuncInfo->ComputePHILiveOutRegInfo(PN); 1018 } else { 1019 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1020 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1021 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1022 } 1023 1024 FuncInfo->VisitedBBs.insert(LLVMBB); 1025 } 1026 1027 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1028 BasicBlock::const_iterator const End = LLVMBB->end(); 1029 BasicBlock::const_iterator BI = End; 1030 1031 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1032 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1033 1034 // Setup an EH landing-pad block. 1035 FuncInfo->ExceptionPointerVirtReg = 0; 1036 FuncInfo->ExceptionSelectorVirtReg = 0; 1037 if (FuncInfo->MBB->isLandingPad()) 1038 PrepareEHLandingPad(); 1039 1040 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1041 if (FastIS) { 1042 FastIS->startNewBlock(); 1043 1044 // Emit code for any incoming arguments. This must happen before 1045 // beginning FastISel on the entry block. 1046 if (LLVMBB == &Fn.getEntryBlock()) { 1047 ++NumEntryBlocks; 1048 1049 // Lower any arguments needed in this block if this is the entry block. 1050 if (!FastIS->LowerArguments()) { 1051 // Fast isel failed to lower these arguments 1052 ++NumFastIselFailLowerArguments; 1053 if (EnableFastISelAbortArgs) 1054 llvm_unreachable("FastISel didn't lower all arguments"); 1055 1056 // Use SelectionDAG argument lowering 1057 LowerArguments(Fn); 1058 CurDAG->setRoot(SDB->getControlRoot()); 1059 SDB->clear(); 1060 CodeGenAndEmitDAG(); 1061 } 1062 1063 // If we inserted any instructions at the beginning, make a note of 1064 // where they are, so we can be sure to emit subsequent instructions 1065 // after them. 1066 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1067 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt)); 1068 else 1069 FastIS->setLastLocalValue(nullptr); 1070 } 1071 1072 unsigned NumFastIselRemaining = std::distance(Begin, End); 1073 // Do FastISel on as many instructions as possible. 1074 for (; BI != Begin; --BI) { 1075 const Instruction *Inst = std::prev(BI); 1076 1077 // If we no longer require this instruction, skip it. 1078 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1079 --NumFastIselRemaining; 1080 continue; 1081 } 1082 1083 // Bottom-up: reset the insert pos at the top, after any local-value 1084 // instructions. 1085 FastIS->recomputeInsertPt(); 1086 1087 // Try to select the instruction with FastISel. 1088 if (FastIS->SelectInstruction(Inst)) { 1089 --NumFastIselRemaining; 1090 ++NumFastIselSuccess; 1091 // If fast isel succeeded, skip over all the folded instructions, and 1092 // then see if there is a load right before the selected instructions. 1093 // Try to fold the load if so. 1094 const Instruction *BeforeInst = Inst; 1095 while (BeforeInst != Begin) { 1096 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst)); 1097 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1098 break; 1099 } 1100 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1101 BeforeInst->hasOneUse() && 1102 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1103 // If we succeeded, don't re-select the load. 1104 BI = std::next(BasicBlock::const_iterator(BeforeInst)); 1105 --NumFastIselRemaining; 1106 ++NumFastIselSuccess; 1107 } 1108 continue; 1109 } 1110 1111#ifndef NDEBUG 1112 if (EnableFastISelVerbose2) 1113 collectFailStats(Inst); 1114#endif 1115 1116 // Then handle certain instructions as single-LLVM-Instruction blocks. 1117 if (isa<CallInst>(Inst)) { 1118 1119 if (EnableFastISelVerbose || EnableFastISelAbort) { 1120 dbgs() << "FastISel missed call: "; 1121 Inst->dump(); 1122 } 1123 1124 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1125 unsigned &R = FuncInfo->ValueMap[Inst]; 1126 if (!R) 1127 R = FuncInfo->CreateRegs(Inst->getType()); 1128 } 1129 1130 bool HadTailCall = false; 1131 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1132 SelectBasicBlock(Inst, BI, HadTailCall); 1133 1134 // If the call was emitted as a tail call, we're done with the block. 1135 // We also need to delete any previously emitted instructions. 1136 if (HadTailCall) { 1137 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1138 --BI; 1139 break; 1140 } 1141 1142 // Recompute NumFastIselRemaining as Selection DAG instruction 1143 // selection may have handled the call, input args, etc. 1144 unsigned RemainingNow = std::distance(Begin, BI); 1145 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1146 NumFastIselRemaining = RemainingNow; 1147 continue; 1148 } 1149 1150 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1151 // Don't abort, and use a different message for terminator misses. 1152 NumFastIselFailures += NumFastIselRemaining; 1153 if (EnableFastISelVerbose || EnableFastISelAbort) { 1154 dbgs() << "FastISel missed terminator: "; 1155 Inst->dump(); 1156 } 1157 } else { 1158 NumFastIselFailures += NumFastIselRemaining; 1159 if (EnableFastISelVerbose || EnableFastISelAbort) { 1160 dbgs() << "FastISel miss: "; 1161 Inst->dump(); 1162 } 1163 if (EnableFastISelAbort) 1164 // The "fast" selector couldn't handle something and bailed. 1165 // For the purpose of debugging, just abort. 1166 llvm_unreachable("FastISel didn't select the entire block"); 1167 } 1168 break; 1169 } 1170 1171 FastIS->recomputeInsertPt(); 1172 } else { 1173 // Lower any arguments needed in this block if this is the entry block. 1174 if (LLVMBB == &Fn.getEntryBlock()) { 1175 ++NumEntryBlocks; 1176 LowerArguments(Fn); 1177 } 1178 } 1179 1180 if (Begin != BI) 1181 ++NumDAGBlocks; 1182 else 1183 ++NumFastIselBlocks; 1184 1185 if (Begin != BI) { 1186 // Run SelectionDAG instruction selection on the remainder of the block 1187 // not handled by FastISel. If FastISel is not run, this is the entire 1188 // block. 1189 bool HadTailCall; 1190 SelectBasicBlock(Begin, BI, HadTailCall); 1191 } 1192 1193 FinishBasicBlock(); 1194 FuncInfo->PHINodesToUpdate.clear(); 1195 } 1196 1197 delete FastIS; 1198 SDB->clearDanglingDebugInfo(); 1199 SDB->SPDescriptor.resetPerFunctionState(); 1200} 1201 1202/// Given that the input MI is before a partial terminator sequence TSeq, return 1203/// true if M + TSeq also a partial terminator sequence. 1204/// 1205/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1206/// lowering copy vregs into physical registers, which are then passed into 1207/// terminator instructors so we can satisfy ABI constraints. A partial 1208/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1209/// may be the whole terminator sequence). 1210static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1211 // If we do not have a copy or an implicit def, we return true if and only if 1212 // MI is a debug value. 1213 if (!MI->isCopy() && !MI->isImplicitDef()) 1214 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1215 // physical registers if there is debug info associated with the terminator 1216 // of our mbb. We want to include said debug info in our terminator 1217 // sequence, so we return true in that case. 1218 return MI->isDebugValue(); 1219 1220 // We have left the terminator sequence if we are not doing one of the 1221 // following: 1222 // 1223 // 1. Copying a vreg into a physical register. 1224 // 2. Copying a vreg into a vreg. 1225 // 3. Defining a register via an implicit def. 1226 1227 // OPI should always be a register definition... 1228 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1229 if (!OPI->isReg() || !OPI->isDef()) 1230 return false; 1231 1232 // Defining any register via an implicit def is always ok. 1233 if (MI->isImplicitDef()) 1234 return true; 1235 1236 // Grab the copy source... 1237 MachineInstr::const_mop_iterator OPI2 = OPI; 1238 ++OPI2; 1239 assert(OPI2 != MI->operands_end() 1240 && "Should have a copy implying we should have 2 arguments."); 1241 1242 // Make sure that the copy dest is not a vreg when the copy source is a 1243 // physical register. 1244 if (!OPI2->isReg() || 1245 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1246 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1247 return false; 1248 1249 return true; 1250} 1251 1252/// Find the split point at which to splice the end of BB into its success stack 1253/// protector check machine basic block. 1254/// 1255/// On many platforms, due to ABI constraints, terminators, even before register 1256/// allocation, use physical registers. This creates an issue for us since 1257/// physical registers at this point can not travel across basic 1258/// blocks. Luckily, selectiondag always moves physical registers into vregs 1259/// when they enter functions and moves them through a sequence of copies back 1260/// into the physical registers right before the terminator creating a 1261/// ``Terminator Sequence''. This function is searching for the beginning of the 1262/// terminator sequence so that we can ensure that we splice off not just the 1263/// terminator, but additionally the copies that move the vregs into the 1264/// physical registers. 1265static MachineBasicBlock::iterator 1266FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1267 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1268 // 1269 if (SplitPoint == BB->begin()) 1270 return SplitPoint; 1271 1272 MachineBasicBlock::iterator Start = BB->begin(); 1273 MachineBasicBlock::iterator Previous = SplitPoint; 1274 --Previous; 1275 1276 while (MIIsInTerminatorSequence(Previous)) { 1277 SplitPoint = Previous; 1278 if (Previous == Start) 1279 break; 1280 --Previous; 1281 } 1282 1283 return SplitPoint; 1284} 1285 1286void 1287SelectionDAGISel::FinishBasicBlock() { 1288 1289 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1290 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1291 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1292 dbgs() << "Node " << i << " : (" 1293 << FuncInfo->PHINodesToUpdate[i].first 1294 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1295 1296 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1297 SDB->JTCases.empty() && 1298 SDB->BitTestCases.empty(); 1299 1300 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1301 // PHI nodes in successors. 1302 if (MustUpdatePHINodes) { 1303 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1304 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1305 assert(PHI->isPHI() && 1306 "This is not a machine PHI node that we are updating!"); 1307 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1308 continue; 1309 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1310 } 1311 } 1312 1313 // Handle stack protector. 1314 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1315 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1316 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1317 1318 // Find the split point to split the parent mbb. At the same time copy all 1319 // physical registers used in the tail of parent mbb into virtual registers 1320 // before the split point and back into physical registers after the split 1321 // point. This prevents us needing to deal with Live-ins and many other 1322 // register allocation issues caused by us splitting the parent mbb. The 1323 // register allocator will clean up said virtual copies later on. 1324 MachineBasicBlock::iterator SplitPoint = 1325 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1326 1327 // Splice the terminator of ParentMBB into SuccessMBB. 1328 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1329 SplitPoint, 1330 ParentMBB->end()); 1331 1332 // Add compare/jump on neq/jump to the parent BB. 1333 FuncInfo->MBB = ParentMBB; 1334 FuncInfo->InsertPt = ParentMBB->end(); 1335 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1336 CurDAG->setRoot(SDB->getRoot()); 1337 SDB->clear(); 1338 CodeGenAndEmitDAG(); 1339 1340 // CodeGen Failure MBB if we have not codegened it yet. 1341 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1342 if (!FailureMBB->size()) { 1343 FuncInfo->MBB = FailureMBB; 1344 FuncInfo->InsertPt = FailureMBB->end(); 1345 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1346 CurDAG->setRoot(SDB->getRoot()); 1347 SDB->clear(); 1348 CodeGenAndEmitDAG(); 1349 } 1350 1351 // Clear the Per-BB State. 1352 SDB->SPDescriptor.resetPerBBState(); 1353 } 1354 1355 // If we updated PHI Nodes, return early. 1356 if (MustUpdatePHINodes) 1357 return; 1358 1359 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1360 // Lower header first, if it wasn't already lowered 1361 if (!SDB->BitTestCases[i].Emitted) { 1362 // Set the current basic block to the mbb we wish to insert the code into 1363 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1364 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1365 // Emit the code 1366 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1367 CurDAG->setRoot(SDB->getRoot()); 1368 SDB->clear(); 1369 CodeGenAndEmitDAG(); 1370 } 1371 1372 uint32_t UnhandledWeight = 0; 1373 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1374 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1375 1376 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1377 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1378 // Set the current basic block to the mbb we wish to insert the code into 1379 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1380 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1381 // Emit the code 1382 if (j+1 != ej) 1383 SDB->visitBitTestCase(SDB->BitTestCases[i], 1384 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1385 UnhandledWeight, 1386 SDB->BitTestCases[i].Reg, 1387 SDB->BitTestCases[i].Cases[j], 1388 FuncInfo->MBB); 1389 else 1390 SDB->visitBitTestCase(SDB->BitTestCases[i], 1391 SDB->BitTestCases[i].Default, 1392 UnhandledWeight, 1393 SDB->BitTestCases[i].Reg, 1394 SDB->BitTestCases[i].Cases[j], 1395 FuncInfo->MBB); 1396 1397 1398 CurDAG->setRoot(SDB->getRoot()); 1399 SDB->clear(); 1400 CodeGenAndEmitDAG(); 1401 } 1402 1403 // Update PHI Nodes 1404 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1405 pi != pe; ++pi) { 1406 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1407 MachineBasicBlock *PHIBB = PHI->getParent(); 1408 assert(PHI->isPHI() && 1409 "This is not a machine PHI node that we are updating!"); 1410 // This is "default" BB. We have two jumps to it. From "header" BB and 1411 // from last "case" BB. 1412 if (PHIBB == SDB->BitTestCases[i].Default) 1413 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1414 .addMBB(SDB->BitTestCases[i].Parent) 1415 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1416 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1417 // One of "cases" BB. 1418 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1419 j != ej; ++j) { 1420 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1421 if (cBB->isSuccessor(PHIBB)) 1422 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1423 } 1424 } 1425 } 1426 SDB->BitTestCases.clear(); 1427 1428 // If the JumpTable record is filled in, then we need to emit a jump table. 1429 // Updating the PHI nodes is tricky in this case, since we need to determine 1430 // whether the PHI is a successor of the range check MBB or the jump table MBB 1431 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1432 // Lower header first, if it wasn't already lowered 1433 if (!SDB->JTCases[i].first.Emitted) { 1434 // Set the current basic block to the mbb we wish to insert the code into 1435 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1436 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1437 // Emit the code 1438 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1439 FuncInfo->MBB); 1440 CurDAG->setRoot(SDB->getRoot()); 1441 SDB->clear(); 1442 CodeGenAndEmitDAG(); 1443 } 1444 1445 // Set the current basic block to the mbb we wish to insert the code into 1446 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1447 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1448 // Emit the code 1449 SDB->visitJumpTable(SDB->JTCases[i].second); 1450 CurDAG->setRoot(SDB->getRoot()); 1451 SDB->clear(); 1452 CodeGenAndEmitDAG(); 1453 1454 // Update PHI Nodes 1455 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1456 pi != pe; ++pi) { 1457 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1458 MachineBasicBlock *PHIBB = PHI->getParent(); 1459 assert(PHI->isPHI() && 1460 "This is not a machine PHI node that we are updating!"); 1461 // "default" BB. We can go there only from header BB. 1462 if (PHIBB == SDB->JTCases[i].second.Default) 1463 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1464 .addMBB(SDB->JTCases[i].first.HeaderBB); 1465 // JT BB. Just iterate over successors here 1466 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1467 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1468 } 1469 } 1470 SDB->JTCases.clear(); 1471 1472 // If the switch block involved a branch to one of the actual successors, we 1473 // need to update PHI nodes in that block. 1474 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1475 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1476 assert(PHI->isPHI() && 1477 "This is not a machine PHI node that we are updating!"); 1478 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1479 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1480 } 1481 1482 // If we generated any switch lowering information, build and codegen any 1483 // additional DAGs necessary. 1484 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1485 // Set the current basic block to the mbb we wish to insert the code into 1486 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1487 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1488 1489 // Determine the unique successors. 1490 SmallVector<MachineBasicBlock *, 2> Succs; 1491 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1492 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1493 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1494 1495 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1496 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1497 CurDAG->setRoot(SDB->getRoot()); 1498 SDB->clear(); 1499 CodeGenAndEmitDAG(); 1500 1501 // Remember the last block, now that any splitting is done, for use in 1502 // populating PHI nodes in successors. 1503 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1504 1505 // Handle any PHI nodes in successors of this chunk, as if we were coming 1506 // from the original BB before switch expansion. Note that PHI nodes can 1507 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1508 // handle them the right number of times. 1509 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1510 FuncInfo->MBB = Succs[i]; 1511 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1512 // FuncInfo->MBB may have been removed from the CFG if a branch was 1513 // constant folded. 1514 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1515 for (MachineBasicBlock::iterator 1516 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1517 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1518 MachineInstrBuilder PHI(*MF, MBBI); 1519 // This value for this PHI node is recorded in PHINodesToUpdate. 1520 for (unsigned pn = 0; ; ++pn) { 1521 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1522 "Didn't find PHI entry!"); 1523 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1524 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1525 break; 1526 } 1527 } 1528 } 1529 } 1530 } 1531 } 1532 SDB->SwitchCases.clear(); 1533} 1534 1535 1536/// Create the scheduler. If a specific scheduler was specified 1537/// via the SchedulerRegistry, use it, otherwise select the 1538/// one preferred by the target. 1539/// 1540ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1541 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1542 1543 if (!Ctor) { 1544 Ctor = ISHeuristic; 1545 RegisterScheduler::setDefault(Ctor); 1546 } 1547 1548 return Ctor(this, OptLevel); 1549} 1550 1551//===----------------------------------------------------------------------===// 1552// Helper functions used by the generated instruction selector. 1553//===----------------------------------------------------------------------===// 1554// Calls to these methods are generated by tblgen. 1555 1556/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1557/// the dag combiner simplified the 255, we still want to match. RHS is the 1558/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1559/// specified in the .td file (e.g. 255). 1560bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1561 int64_t DesiredMaskS) const { 1562 const APInt &ActualMask = RHS->getAPIntValue(); 1563 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1564 1565 // If the actual mask exactly matches, success! 1566 if (ActualMask == DesiredMask) 1567 return true; 1568 1569 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1570 if (ActualMask.intersects(~DesiredMask)) 1571 return false; 1572 1573 // Otherwise, the DAG Combiner may have proven that the value coming in is 1574 // either already zero or is not demanded. Check for known zero input bits. 1575 APInt NeededMask = DesiredMask & ~ActualMask; 1576 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1577 return true; 1578 1579 // TODO: check to see if missing bits are just not demanded. 1580 1581 // Otherwise, this pattern doesn't match. 1582 return false; 1583} 1584 1585/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1586/// the dag combiner simplified the 255, we still want to match. RHS is the 1587/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1588/// specified in the .td file (e.g. 255). 1589bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1590 int64_t DesiredMaskS) const { 1591 const APInt &ActualMask = RHS->getAPIntValue(); 1592 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1593 1594 // If the actual mask exactly matches, success! 1595 if (ActualMask == DesiredMask) 1596 return true; 1597 1598 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1599 if (ActualMask.intersects(~DesiredMask)) 1600 return false; 1601 1602 // Otherwise, the DAG Combiner may have proven that the value coming in is 1603 // either already zero or is not demanded. Check for known zero input bits. 1604 APInt NeededMask = DesiredMask & ~ActualMask; 1605 1606 APInt KnownZero, KnownOne; 1607 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne); 1608 1609 // If all the missing bits in the or are already known to be set, match! 1610 if ((NeededMask & KnownOne) == NeededMask) 1611 return true; 1612 1613 // TODO: check to see if missing bits are just not demanded. 1614 1615 // Otherwise, this pattern doesn't match. 1616 return false; 1617} 1618 1619 1620/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1621/// by tblgen. Others should not call it. 1622void SelectionDAGISel:: 1623SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1624 std::vector<SDValue> InOps; 1625 std::swap(InOps, Ops); 1626 1627 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1628 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1629 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1630 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1631 1632 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1633 if (InOps[e-1].getValueType() == MVT::Glue) 1634 --e; // Don't process a glue operand if it is here. 1635 1636 while (i != e) { 1637 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1638 if (!InlineAsm::isMemKind(Flags)) { 1639 // Just skip over this operand, copying the operands verbatim. 1640 Ops.insert(Ops.end(), InOps.begin()+i, 1641 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1642 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1643 } else { 1644 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1645 "Memory operand with multiple values?"); 1646 // Otherwise, this is a memory operand. Ask the target to select it. 1647 std::vector<SDValue> SelOps; 1648 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1649 report_fatal_error("Could not match memory address. Inline asm" 1650 " failure!"); 1651 1652 // Add this to the output node. 1653 unsigned NewFlags = 1654 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1655 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1656 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1657 i += 2; 1658 } 1659 } 1660 1661 // Add the glue input back if present. 1662 if (e != InOps.size()) 1663 Ops.push_back(InOps.back()); 1664} 1665 1666/// findGlueUse - Return use of MVT::Glue value produced by the specified 1667/// SDNode. 1668/// 1669static SDNode *findGlueUse(SDNode *N) { 1670 unsigned FlagResNo = N->getNumValues()-1; 1671 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1672 SDUse &Use = I.getUse(); 1673 if (Use.getResNo() == FlagResNo) 1674 return Use.getUser(); 1675 } 1676 return nullptr; 1677} 1678 1679/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1680/// This function recursively traverses up the operand chain, ignoring 1681/// certain nodes. 1682static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1683 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1684 bool IgnoreChains) { 1685 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1686 // greater than all of its (recursive) operands. If we scan to a point where 1687 // 'use' is smaller than the node we're scanning for, then we know we will 1688 // never find it. 1689 // 1690 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1691 // happen because we scan down to newly selected nodes in the case of glue 1692 // uses. 1693 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1694 return false; 1695 1696 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1697 // won't fail if we scan it again. 1698 if (!Visited.insert(Use)) 1699 return false; 1700 1701 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1702 // Ignore chain uses, they are validated by HandleMergeInputChains. 1703 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1704 continue; 1705 1706 SDNode *N = Use->getOperand(i).getNode(); 1707 if (N == Def) { 1708 if (Use == ImmedUse || Use == Root) 1709 continue; // We are not looking for immediate use. 1710 assert(N != Root); 1711 return true; 1712 } 1713 1714 // Traverse up the operand chain. 1715 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1716 return true; 1717 } 1718 return false; 1719} 1720 1721/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1722/// operand node N of U during instruction selection that starts at Root. 1723bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1724 SDNode *Root) const { 1725 if (OptLevel == CodeGenOpt::None) return false; 1726 return N.hasOneUse(); 1727} 1728 1729/// IsLegalToFold - Returns true if the specific operand node N of 1730/// U can be folded during instruction selection that starts at Root. 1731bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1732 CodeGenOpt::Level OptLevel, 1733 bool IgnoreChains) { 1734 if (OptLevel == CodeGenOpt::None) return false; 1735 1736 // If Root use can somehow reach N through a path that that doesn't contain 1737 // U then folding N would create a cycle. e.g. In the following 1738 // diagram, Root can reach N through X. If N is folded into into Root, then 1739 // X is both a predecessor and a successor of U. 1740 // 1741 // [N*] // 1742 // ^ ^ // 1743 // / \ // 1744 // [U*] [X]? // 1745 // ^ ^ // 1746 // \ / // 1747 // \ / // 1748 // [Root*] // 1749 // 1750 // * indicates nodes to be folded together. 1751 // 1752 // If Root produces glue, then it gets (even more) interesting. Since it 1753 // will be "glued" together with its glue use in the scheduler, we need to 1754 // check if it might reach N. 1755 // 1756 // [N*] // 1757 // ^ ^ // 1758 // / \ // 1759 // [U*] [X]? // 1760 // ^ ^ // 1761 // \ \ // 1762 // \ | // 1763 // [Root*] | // 1764 // ^ | // 1765 // f | // 1766 // | / // 1767 // [Y] / // 1768 // ^ / // 1769 // f / // 1770 // | / // 1771 // [GU] // 1772 // 1773 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1774 // (call it Fold), then X is a predecessor of GU and a successor of 1775 // Fold. But since Fold and GU are glued together, this will create 1776 // a cycle in the scheduling graph. 1777 1778 // If the node has glue, walk down the graph to the "lowest" node in the 1779 // glueged set. 1780 EVT VT = Root->getValueType(Root->getNumValues()-1); 1781 while (VT == MVT::Glue) { 1782 SDNode *GU = findGlueUse(Root); 1783 if (!GU) 1784 break; 1785 Root = GU; 1786 VT = Root->getValueType(Root->getNumValues()-1); 1787 1788 // If our query node has a glue result with a use, we've walked up it. If 1789 // the user (which has already been selected) has a chain or indirectly uses 1790 // the chain, our WalkChainUsers predicate will not consider it. Because of 1791 // this, we cannot ignore chains in this predicate. 1792 IgnoreChains = false; 1793 } 1794 1795 1796 SmallPtrSet<SDNode*, 16> Visited; 1797 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1798} 1799 1800SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1801 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1802 SelectInlineAsmMemoryOperands(Ops); 1803 1804 EVT VTs[] = { MVT::Other, MVT::Glue }; 1805 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops); 1806 New->setNodeId(-1); 1807 return New.getNode(); 1808} 1809 1810SDNode 1811*SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) { 1812 SDLoc dl(Op); 1813 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0)); 1814 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); 1815 unsigned Reg = getTargetLowering()->getRegisterByName( 1816 RegStr->getString().data(), Op->getValueType(0)); 1817 SDValue New = CurDAG->getCopyFromReg( 1818 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0)); 1819 New->setNodeId(-1); 1820 return New.getNode(); 1821} 1822 1823SDNode 1824*SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) { 1825 SDLoc dl(Op); 1826 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); 1827 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); 1828 unsigned Reg = getTargetLowering()->getRegisterByName( 1829 RegStr->getString().data(), Op->getOperand(2).getValueType()); 1830 SDValue New = CurDAG->getCopyToReg( 1831 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2)); 1832 New->setNodeId(-1); 1833 return New.getNode(); 1834} 1835 1836 1837 1838SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1839 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1840} 1841 1842/// GetVBR - decode a vbr encoding whose top bit is set. 1843LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1844GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1845 assert(Val >= 128 && "Not a VBR"); 1846 Val &= 127; // Remove first vbr bit. 1847 1848 unsigned Shift = 7; 1849 uint64_t NextBits; 1850 do { 1851 NextBits = MatcherTable[Idx++]; 1852 Val |= (NextBits&127) << Shift; 1853 Shift += 7; 1854 } while (NextBits & 128); 1855 1856 return Val; 1857} 1858 1859 1860/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1861/// interior glue and chain results to use the new glue and chain results. 1862void SelectionDAGISel:: 1863UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1864 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1865 SDValue InputGlue, 1866 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1867 bool isMorphNodeTo) { 1868 SmallVector<SDNode*, 4> NowDeadNodes; 1869 1870 // Now that all the normal results are replaced, we replace the chain and 1871 // glue results if present. 1872 if (!ChainNodesMatched.empty()) { 1873 assert(InputChain.getNode() && 1874 "Matched input chains but didn't produce a chain"); 1875 // Loop over all of the nodes we matched that produced a chain result. 1876 // Replace all the chain results with the final chain we ended up with. 1877 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1878 SDNode *ChainNode = ChainNodesMatched[i]; 1879 1880 // If this node was already deleted, don't look at it. 1881 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1882 continue; 1883 1884 // Don't replace the results of the root node if we're doing a 1885 // MorphNodeTo. 1886 if (ChainNode == NodeToMatch && isMorphNodeTo) 1887 continue; 1888 1889 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1890 if (ChainVal.getValueType() == MVT::Glue) 1891 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1892 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1893 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1894 1895 // If the node became dead and we haven't already seen it, delete it. 1896 if (ChainNode->use_empty() && 1897 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1898 NowDeadNodes.push_back(ChainNode); 1899 } 1900 } 1901 1902 // If the result produces glue, update any glue results in the matched 1903 // pattern with the glue result. 1904 if (InputGlue.getNode()) { 1905 // Handle any interior nodes explicitly marked. 1906 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1907 SDNode *FRN = GlueResultNodesMatched[i]; 1908 1909 // If this node was already deleted, don't look at it. 1910 if (FRN->getOpcode() == ISD::DELETED_NODE) 1911 continue; 1912 1913 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1914 "Doesn't have a glue result"); 1915 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1916 InputGlue); 1917 1918 // If the node became dead and we haven't already seen it, delete it. 1919 if (FRN->use_empty() && 1920 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1921 NowDeadNodes.push_back(FRN); 1922 } 1923 } 1924 1925 if (!NowDeadNodes.empty()) 1926 CurDAG->RemoveDeadNodes(NowDeadNodes); 1927 1928 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1929} 1930 1931enum ChainResult { 1932 CR_Simple, 1933 CR_InducesCycle, 1934 CR_LeadsToInteriorNode 1935}; 1936 1937/// WalkChainUsers - Walk down the users of the specified chained node that is 1938/// part of the pattern we're matching, looking at all of the users we find. 1939/// This determines whether something is an interior node, whether we have a 1940/// non-pattern node in between two pattern nodes (which prevent folding because 1941/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1942/// between pattern nodes (in which case the TF becomes part of the pattern). 1943/// 1944/// The walk we do here is guaranteed to be small because we quickly get down to 1945/// already selected nodes "below" us. 1946static ChainResult 1947WalkChainUsers(const SDNode *ChainedNode, 1948 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1949 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1950 ChainResult Result = CR_Simple; 1951 1952 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1953 E = ChainedNode->use_end(); UI != E; ++UI) { 1954 // Make sure the use is of the chain, not some other value we produce. 1955 if (UI.getUse().getValueType() != MVT::Other) continue; 1956 1957 SDNode *User = *UI; 1958 1959 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1960 continue; 1961 1962 // If we see an already-selected machine node, then we've gone beyond the 1963 // pattern that we're selecting down into the already selected chunk of the 1964 // DAG. 1965 unsigned UserOpcode = User->getOpcode(); 1966 if (User->isMachineOpcode() || 1967 UserOpcode == ISD::CopyToReg || 1968 UserOpcode == ISD::CopyFromReg || 1969 UserOpcode == ISD::INLINEASM || 1970 UserOpcode == ISD::EH_LABEL || 1971 UserOpcode == ISD::LIFETIME_START || 1972 UserOpcode == ISD::LIFETIME_END) { 1973 // If their node ID got reset to -1 then they've already been selected. 1974 // Treat them like a MachineOpcode. 1975 if (User->getNodeId() == -1) 1976 continue; 1977 } 1978 1979 // If we have a TokenFactor, we handle it specially. 1980 if (User->getOpcode() != ISD::TokenFactor) { 1981 // If the node isn't a token factor and isn't part of our pattern, then it 1982 // must be a random chained node in between two nodes we're selecting. 1983 // This happens when we have something like: 1984 // x = load ptr 1985 // call 1986 // y = x+4 1987 // store y -> ptr 1988 // Because we structurally match the load/store as a read/modify/write, 1989 // but the call is chained between them. We cannot fold in this case 1990 // because it would induce a cycle in the graph. 1991 if (!std::count(ChainedNodesInPattern.begin(), 1992 ChainedNodesInPattern.end(), User)) 1993 return CR_InducesCycle; 1994 1995 // Otherwise we found a node that is part of our pattern. For example in: 1996 // x = load ptr 1997 // y = x+4 1998 // store y -> ptr 1999 // This would happen when we're scanning down from the load and see the 2000 // store as a user. Record that there is a use of ChainedNode that is 2001 // part of the pattern and keep scanning uses. 2002 Result = CR_LeadsToInteriorNode; 2003 InteriorChainedNodes.push_back(User); 2004 continue; 2005 } 2006 2007 // If we found a TokenFactor, there are two cases to consider: first if the 2008 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 2009 // uses of the TF are in our pattern) we just want to ignore it. Second, 2010 // the TokenFactor can be sandwiched in between two chained nodes, like so: 2011 // [Load chain] 2012 // ^ 2013 // | 2014 // [Load] 2015 // ^ ^ 2016 // | \ DAG's like cheese 2017 // / \ do you? 2018 // / | 2019 // [TokenFactor] [Op] 2020 // ^ ^ 2021 // | | 2022 // \ / 2023 // \ / 2024 // [Store] 2025 // 2026 // In this case, the TokenFactor becomes part of our match and we rewrite it 2027 // as a new TokenFactor. 2028 // 2029 // To distinguish these two cases, do a recursive walk down the uses. 2030 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 2031 case CR_Simple: 2032 // If the uses of the TokenFactor are just already-selected nodes, ignore 2033 // it, it is "below" our pattern. 2034 continue; 2035 case CR_InducesCycle: 2036 // If the uses of the TokenFactor lead to nodes that are not part of our 2037 // pattern that are not selected, folding would turn this into a cycle, 2038 // bail out now. 2039 return CR_InducesCycle; 2040 case CR_LeadsToInteriorNode: 2041 break; // Otherwise, keep processing. 2042 } 2043 2044 // Okay, we know we're in the interesting interior case. The TokenFactor 2045 // is now going to be considered part of the pattern so that we rewrite its 2046 // uses (it may have uses that are not part of the pattern) with the 2047 // ultimate chain result of the generated code. We will also add its chain 2048 // inputs as inputs to the ultimate TokenFactor we create. 2049 Result = CR_LeadsToInteriorNode; 2050 ChainedNodesInPattern.push_back(User); 2051 InteriorChainedNodes.push_back(User); 2052 continue; 2053 } 2054 2055 return Result; 2056} 2057 2058/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 2059/// operation for when the pattern matched at least one node with a chains. The 2060/// input vector contains a list of all of the chained nodes that we match. We 2061/// must determine if this is a valid thing to cover (i.e. matching it won't 2062/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 2063/// be used as the input node chain for the generated nodes. 2064static SDValue 2065HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 2066 SelectionDAG *CurDAG) { 2067 // Walk all of the chained nodes we've matched, recursively scanning down the 2068 // users of the chain result. This adds any TokenFactor nodes that are caught 2069 // in between chained nodes to the chained and interior nodes list. 2070 SmallVector<SDNode*, 3> InteriorChainedNodes; 2071 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2072 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 2073 InteriorChainedNodes) == CR_InducesCycle) 2074 return SDValue(); // Would induce a cycle. 2075 } 2076 2077 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2078 // that we are interested in. Form our input TokenFactor node. 2079 SmallVector<SDValue, 3> InputChains; 2080 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2081 // Add the input chain of this node to the InputChains list (which will be 2082 // the operands of the generated TokenFactor) if it's not an interior node. 2083 SDNode *N = ChainNodesMatched[i]; 2084 if (N->getOpcode() != ISD::TokenFactor) { 2085 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2086 continue; 2087 2088 // Otherwise, add the input chain. 2089 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2090 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2091 InputChains.push_back(InChain); 2092 continue; 2093 } 2094 2095 // If we have a token factor, we want to add all inputs of the token factor 2096 // that are not part of the pattern we're matching. 2097 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 2098 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2099 N->getOperand(op).getNode())) 2100 InputChains.push_back(N->getOperand(op)); 2101 } 2102 } 2103 2104 if (InputChains.size() == 1) 2105 return InputChains[0]; 2106 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2107 MVT::Other, InputChains); 2108} 2109 2110/// MorphNode - Handle morphing a node in place for the selector. 2111SDNode *SelectionDAGISel:: 2112MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2113 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) { 2114 // It is possible we're using MorphNodeTo to replace a node with no 2115 // normal results with one that has a normal result (or we could be 2116 // adding a chain) and the input could have glue and chains as well. 2117 // In this case we need to shift the operands down. 2118 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2119 // than the old isel though. 2120 int OldGlueResultNo = -1, OldChainResultNo = -1; 2121 2122 unsigned NTMNumResults = Node->getNumValues(); 2123 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2124 OldGlueResultNo = NTMNumResults-1; 2125 if (NTMNumResults != 1 && 2126 Node->getValueType(NTMNumResults-2) == MVT::Other) 2127 OldChainResultNo = NTMNumResults-2; 2128 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2129 OldChainResultNo = NTMNumResults-1; 2130 2131 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2132 // that this deletes operands of the old node that become dead. 2133 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops); 2134 2135 // MorphNodeTo can operate in two ways: if an existing node with the 2136 // specified operands exists, it can just return it. Otherwise, it 2137 // updates the node in place to have the requested operands. 2138 if (Res == Node) { 2139 // If we updated the node in place, reset the node ID. To the isel, 2140 // this should be just like a newly allocated machine node. 2141 Res->setNodeId(-1); 2142 } 2143 2144 unsigned ResNumResults = Res->getNumValues(); 2145 // Move the glue if needed. 2146 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2147 (unsigned)OldGlueResultNo != ResNumResults-1) 2148 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2149 SDValue(Res, ResNumResults-1)); 2150 2151 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2152 --ResNumResults; 2153 2154 // Move the chain reference if needed. 2155 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2156 (unsigned)OldChainResultNo != ResNumResults-1) 2157 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2158 SDValue(Res, ResNumResults-1)); 2159 2160 // Otherwise, no replacement happened because the node already exists. Replace 2161 // Uses of the old node with the new one. 2162 if (Res != Node) 2163 CurDAG->ReplaceAllUsesWith(Node, Res); 2164 2165 return Res; 2166} 2167 2168/// CheckSame - Implements OP_CheckSame. 2169LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2170CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2171 SDValue N, 2172 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2173 // Accept if it is exactly the same as a previously recorded node. 2174 unsigned RecNo = MatcherTable[MatcherIndex++]; 2175 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2176 return N == RecordedNodes[RecNo].first; 2177} 2178 2179/// CheckChildSame - Implements OP_CheckChildXSame. 2180LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2181CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2182 SDValue N, 2183 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2184 unsigned ChildNo) { 2185 if (ChildNo >= N.getNumOperands()) 2186 return false; // Match fails if out of range child #. 2187 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2188 RecordedNodes); 2189} 2190 2191/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2192LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2193CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2194 const SelectionDAGISel &SDISel) { 2195 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2196} 2197 2198/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2199LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2200CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2201 const SelectionDAGISel &SDISel, SDNode *N) { 2202 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2203} 2204 2205LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2206CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2207 SDNode *N) { 2208 uint16_t Opc = MatcherTable[MatcherIndex++]; 2209 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2210 return N->getOpcode() == Opc; 2211} 2212 2213LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2214CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2215 SDValue N, const TargetLowering *TLI) { 2216 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2217 if (N.getValueType() == VT) return true; 2218 2219 // Handle the case when VT is iPTR. 2220 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2221} 2222 2223LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2224CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2225 SDValue N, const TargetLowering *TLI, unsigned ChildNo) { 2226 if (ChildNo >= N.getNumOperands()) 2227 return false; // Match fails if out of range child #. 2228 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2229} 2230 2231LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2232CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2233 SDValue N) { 2234 return cast<CondCodeSDNode>(N)->get() == 2235 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2236} 2237 2238LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2239CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2240 SDValue N, const TargetLowering *TLI) { 2241 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2242 if (cast<VTSDNode>(N)->getVT() == VT) 2243 return true; 2244 2245 // Handle the case when VT is iPTR. 2246 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2247} 2248 2249LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2250CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2251 SDValue N) { 2252 int64_t Val = MatcherTable[MatcherIndex++]; 2253 if (Val & 128) 2254 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2255 2256 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2257 return C && C->getSExtValue() == Val; 2258} 2259 2260LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2261CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2262 SDValue N, unsigned ChildNo) { 2263 if (ChildNo >= N.getNumOperands()) 2264 return false; // Match fails if out of range child #. 2265 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo)); 2266} 2267 2268LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2269CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2270 SDValue N, const SelectionDAGISel &SDISel) { 2271 int64_t Val = MatcherTable[MatcherIndex++]; 2272 if (Val & 128) 2273 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2274 2275 if (N->getOpcode() != ISD::AND) return false; 2276 2277 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2278 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2279} 2280 2281LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2282CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2283 SDValue N, const SelectionDAGISel &SDISel) { 2284 int64_t Val = MatcherTable[MatcherIndex++]; 2285 if (Val & 128) 2286 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2287 2288 if (N->getOpcode() != ISD::OR) return false; 2289 2290 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2291 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2292} 2293 2294/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2295/// scope, evaluate the current node. If the current predicate is known to 2296/// fail, set Result=true and return anything. If the current predicate is 2297/// known to pass, set Result=false and return the MatcherIndex to continue 2298/// with. If the current predicate is unknown, set Result=false and return the 2299/// MatcherIndex to continue with. 2300static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2301 unsigned Index, SDValue N, 2302 bool &Result, 2303 const SelectionDAGISel &SDISel, 2304 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2305 switch (Table[Index++]) { 2306 default: 2307 Result = false; 2308 return Index-1; // Could not evaluate this predicate. 2309 case SelectionDAGISel::OPC_CheckSame: 2310 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2311 return Index; 2312 case SelectionDAGISel::OPC_CheckChild0Same: 2313 case SelectionDAGISel::OPC_CheckChild1Same: 2314 case SelectionDAGISel::OPC_CheckChild2Same: 2315 case SelectionDAGISel::OPC_CheckChild3Same: 2316 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2317 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2318 return Index; 2319 case SelectionDAGISel::OPC_CheckPatternPredicate: 2320 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2321 return Index; 2322 case SelectionDAGISel::OPC_CheckPredicate: 2323 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2324 return Index; 2325 case SelectionDAGISel::OPC_CheckOpcode: 2326 Result = !::CheckOpcode(Table, Index, N.getNode()); 2327 return Index; 2328 case SelectionDAGISel::OPC_CheckType: 2329 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2330 return Index; 2331 case SelectionDAGISel::OPC_CheckChild0Type: 2332 case SelectionDAGISel::OPC_CheckChild1Type: 2333 case SelectionDAGISel::OPC_CheckChild2Type: 2334 case SelectionDAGISel::OPC_CheckChild3Type: 2335 case SelectionDAGISel::OPC_CheckChild4Type: 2336 case SelectionDAGISel::OPC_CheckChild5Type: 2337 case SelectionDAGISel::OPC_CheckChild6Type: 2338 case SelectionDAGISel::OPC_CheckChild7Type: 2339 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2340 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2341 return Index; 2342 case SelectionDAGISel::OPC_CheckCondCode: 2343 Result = !::CheckCondCode(Table, Index, N); 2344 return Index; 2345 case SelectionDAGISel::OPC_CheckValueType: 2346 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2347 return Index; 2348 case SelectionDAGISel::OPC_CheckInteger: 2349 Result = !::CheckInteger(Table, Index, N); 2350 return Index; 2351 case SelectionDAGISel::OPC_CheckChild0Integer: 2352 case SelectionDAGISel::OPC_CheckChild1Integer: 2353 case SelectionDAGISel::OPC_CheckChild2Integer: 2354 case SelectionDAGISel::OPC_CheckChild3Integer: 2355 case SelectionDAGISel::OPC_CheckChild4Integer: 2356 Result = !::CheckChildInteger(Table, Index, N, 2357 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer); 2358 return Index; 2359 case SelectionDAGISel::OPC_CheckAndImm: 2360 Result = !::CheckAndImm(Table, Index, N, SDISel); 2361 return Index; 2362 case SelectionDAGISel::OPC_CheckOrImm: 2363 Result = !::CheckOrImm(Table, Index, N, SDISel); 2364 return Index; 2365 } 2366} 2367 2368namespace { 2369 2370struct MatchScope { 2371 /// FailIndex - If this match fails, this is the index to continue with. 2372 unsigned FailIndex; 2373 2374 /// NodeStack - The node stack when the scope was formed. 2375 SmallVector<SDValue, 4> NodeStack; 2376 2377 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2378 unsigned NumRecordedNodes; 2379 2380 /// NumMatchedMemRefs - The number of matched memref entries. 2381 unsigned NumMatchedMemRefs; 2382 2383 /// InputChain/InputGlue - The current chain/glue 2384 SDValue InputChain, InputGlue; 2385 2386 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2387 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2388}; 2389 2390} 2391 2392SDNode *SelectionDAGISel:: 2393SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2394 unsigned TableSize) { 2395 // FIXME: Should these even be selected? Handle these cases in the caller? 2396 switch (NodeToMatch->getOpcode()) { 2397 default: 2398 break; 2399 case ISD::EntryToken: // These nodes remain the same. 2400 case ISD::BasicBlock: 2401 case ISD::Register: 2402 case ISD::RegisterMask: 2403 //case ISD::VALUETYPE: 2404 //case ISD::CONDCODE: 2405 case ISD::HANDLENODE: 2406 case ISD::MDNODE_SDNODE: 2407 case ISD::TargetConstant: 2408 case ISD::TargetConstantFP: 2409 case ISD::TargetConstantPool: 2410 case ISD::TargetFrameIndex: 2411 case ISD::TargetExternalSymbol: 2412 case ISD::TargetBlockAddress: 2413 case ISD::TargetJumpTable: 2414 case ISD::TargetGlobalTLSAddress: 2415 case ISD::TargetGlobalAddress: 2416 case ISD::TokenFactor: 2417 case ISD::CopyFromReg: 2418 case ISD::CopyToReg: 2419 case ISD::EH_LABEL: 2420 case ISD::LIFETIME_START: 2421 case ISD::LIFETIME_END: 2422 NodeToMatch->setNodeId(-1); // Mark selected. 2423 return nullptr; 2424 case ISD::AssertSext: 2425 case ISD::AssertZext: 2426 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2427 NodeToMatch->getOperand(0)); 2428 return nullptr; 2429 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2430 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch); 2431 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch); 2432 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2433 } 2434 2435 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2436 2437 // Set up the node stack with NodeToMatch as the only node on the stack. 2438 SmallVector<SDValue, 8> NodeStack; 2439 SDValue N = SDValue(NodeToMatch, 0); 2440 NodeStack.push_back(N); 2441 2442 // MatchScopes - Scopes used when matching, if a match failure happens, this 2443 // indicates where to continue checking. 2444 SmallVector<MatchScope, 8> MatchScopes; 2445 2446 // RecordedNodes - This is the set of nodes that have been recorded by the 2447 // state machine. The second value is the parent of the node, or null if the 2448 // root is recorded. 2449 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2450 2451 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2452 // pattern. 2453 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2454 2455 // These are the current input chain and glue for use when generating nodes. 2456 // Various Emit operations change these. For example, emitting a copytoreg 2457 // uses and updates these. 2458 SDValue InputChain, InputGlue; 2459 2460 // ChainNodesMatched - If a pattern matches nodes that have input/output 2461 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2462 // which ones they are. The result is captured into this list so that we can 2463 // update the chain results when the pattern is complete. 2464 SmallVector<SDNode*, 3> ChainNodesMatched; 2465 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2466 2467 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2468 NodeToMatch->dump(CurDAG); 2469 dbgs() << '\n'); 2470 2471 // Determine where to start the interpreter. Normally we start at opcode #0, 2472 // but if the state machine starts with an OPC_SwitchOpcode, then we 2473 // accelerate the first lookup (which is guaranteed to be hot) with the 2474 // OpcodeOffset table. 2475 unsigned MatcherIndex = 0; 2476 2477 if (!OpcodeOffset.empty()) { 2478 // Already computed the OpcodeOffset table, just index into it. 2479 if (N.getOpcode() < OpcodeOffset.size()) 2480 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2481 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2482 2483 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2484 // Otherwise, the table isn't computed, but the state machine does start 2485 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2486 // is the first time we're selecting an instruction. 2487 unsigned Idx = 1; 2488 while (1) { 2489 // Get the size of this case. 2490 unsigned CaseSize = MatcherTable[Idx++]; 2491 if (CaseSize & 128) 2492 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2493 if (CaseSize == 0) break; 2494 2495 // Get the opcode, add the index to the table. 2496 uint16_t Opc = MatcherTable[Idx++]; 2497 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2498 if (Opc >= OpcodeOffset.size()) 2499 OpcodeOffset.resize((Opc+1)*2); 2500 OpcodeOffset[Opc] = Idx; 2501 Idx += CaseSize; 2502 } 2503 2504 // Okay, do the lookup for the first opcode. 2505 if (N.getOpcode() < OpcodeOffset.size()) 2506 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2507 } 2508 2509 while (1) { 2510 assert(MatcherIndex < TableSize && "Invalid index"); 2511#ifndef NDEBUG 2512 unsigned CurrentOpcodeIndex = MatcherIndex; 2513#endif 2514 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2515 switch (Opcode) { 2516 case OPC_Scope: { 2517 // Okay, the semantics of this operation are that we should push a scope 2518 // then evaluate the first child. However, pushing a scope only to have 2519 // the first check fail (which then pops it) is inefficient. If we can 2520 // determine immediately that the first check (or first several) will 2521 // immediately fail, don't even bother pushing a scope for them. 2522 unsigned FailIndex; 2523 2524 while (1) { 2525 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2526 if (NumToSkip & 128) 2527 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2528 // Found the end of the scope with no match. 2529 if (NumToSkip == 0) { 2530 FailIndex = 0; 2531 break; 2532 } 2533 2534 FailIndex = MatcherIndex+NumToSkip; 2535 2536 unsigned MatcherIndexOfPredicate = MatcherIndex; 2537 (void)MatcherIndexOfPredicate; // silence warning. 2538 2539 // If we can't evaluate this predicate without pushing a scope (e.g. if 2540 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2541 // push the scope and evaluate the full predicate chain. 2542 bool Result; 2543 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2544 Result, *this, RecordedNodes); 2545 if (!Result) 2546 break; 2547 2548 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2549 << "index " << MatcherIndexOfPredicate 2550 << ", continuing at " << FailIndex << "\n"); 2551 ++NumDAGIselRetries; 2552 2553 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2554 // move to the next case. 2555 MatcherIndex = FailIndex; 2556 } 2557 2558 // If the whole scope failed to match, bail. 2559 if (FailIndex == 0) break; 2560 2561 // Push a MatchScope which indicates where to go if the first child fails 2562 // to match. 2563 MatchScope NewEntry; 2564 NewEntry.FailIndex = FailIndex; 2565 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2566 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2567 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2568 NewEntry.InputChain = InputChain; 2569 NewEntry.InputGlue = InputGlue; 2570 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2571 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2572 MatchScopes.push_back(NewEntry); 2573 continue; 2574 } 2575 case OPC_RecordNode: { 2576 // Remember this node, it may end up being an operand in the pattern. 2577 SDNode *Parent = nullptr; 2578 if (NodeStack.size() > 1) 2579 Parent = NodeStack[NodeStack.size()-2].getNode(); 2580 RecordedNodes.push_back(std::make_pair(N, Parent)); 2581 continue; 2582 } 2583 2584 case OPC_RecordChild0: case OPC_RecordChild1: 2585 case OPC_RecordChild2: case OPC_RecordChild3: 2586 case OPC_RecordChild4: case OPC_RecordChild5: 2587 case OPC_RecordChild6: case OPC_RecordChild7: { 2588 unsigned ChildNo = Opcode-OPC_RecordChild0; 2589 if (ChildNo >= N.getNumOperands()) 2590 break; // Match fails if out of range child #. 2591 2592 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2593 N.getNode())); 2594 continue; 2595 } 2596 case OPC_RecordMemRef: 2597 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2598 continue; 2599 2600 case OPC_CaptureGlueInput: 2601 // If the current node has an input glue, capture it in InputGlue. 2602 if (N->getNumOperands() != 0 && 2603 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2604 InputGlue = N->getOperand(N->getNumOperands()-1); 2605 continue; 2606 2607 case OPC_MoveChild: { 2608 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2609 if (ChildNo >= N.getNumOperands()) 2610 break; // Match fails if out of range child #. 2611 N = N.getOperand(ChildNo); 2612 NodeStack.push_back(N); 2613 continue; 2614 } 2615 2616 case OPC_MoveParent: 2617 // Pop the current node off the NodeStack. 2618 NodeStack.pop_back(); 2619 assert(!NodeStack.empty() && "Node stack imbalance!"); 2620 N = NodeStack.back(); 2621 continue; 2622 2623 case OPC_CheckSame: 2624 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2625 continue; 2626 2627 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2628 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2629 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2630 Opcode-OPC_CheckChild0Same)) 2631 break; 2632 continue; 2633 2634 case OPC_CheckPatternPredicate: 2635 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2636 continue; 2637 case OPC_CheckPredicate: 2638 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2639 N.getNode())) 2640 break; 2641 continue; 2642 case OPC_CheckComplexPat: { 2643 unsigned CPNum = MatcherTable[MatcherIndex++]; 2644 unsigned RecNo = MatcherTable[MatcherIndex++]; 2645 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2646 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2647 RecordedNodes[RecNo].first, CPNum, 2648 RecordedNodes)) 2649 break; 2650 continue; 2651 } 2652 case OPC_CheckOpcode: 2653 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2654 continue; 2655 2656 case OPC_CheckType: 2657 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2658 break; 2659 continue; 2660 2661 case OPC_SwitchOpcode: { 2662 unsigned CurNodeOpcode = N.getOpcode(); 2663 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2664 unsigned CaseSize; 2665 while (1) { 2666 // Get the size of this case. 2667 CaseSize = MatcherTable[MatcherIndex++]; 2668 if (CaseSize & 128) 2669 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2670 if (CaseSize == 0) break; 2671 2672 uint16_t Opc = MatcherTable[MatcherIndex++]; 2673 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2674 2675 // If the opcode matches, then we will execute this case. 2676 if (CurNodeOpcode == Opc) 2677 break; 2678 2679 // Otherwise, skip over this case. 2680 MatcherIndex += CaseSize; 2681 } 2682 2683 // If no cases matched, bail out. 2684 if (CaseSize == 0) break; 2685 2686 // Otherwise, execute the case we found. 2687 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2688 << " to " << MatcherIndex << "\n"); 2689 continue; 2690 } 2691 2692 case OPC_SwitchType: { 2693 MVT CurNodeVT = N.getSimpleValueType(); 2694 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2695 unsigned CaseSize; 2696 while (1) { 2697 // Get the size of this case. 2698 CaseSize = MatcherTable[MatcherIndex++]; 2699 if (CaseSize & 128) 2700 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2701 if (CaseSize == 0) break; 2702 2703 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2704 if (CaseVT == MVT::iPTR) 2705 CaseVT = getTargetLowering()->getPointerTy(); 2706 2707 // If the VT matches, then we will execute this case. 2708 if (CurNodeVT == CaseVT) 2709 break; 2710 2711 // Otherwise, skip over this case. 2712 MatcherIndex += CaseSize; 2713 } 2714 2715 // If no cases matched, bail out. 2716 if (CaseSize == 0) break; 2717 2718 // Otherwise, execute the case we found. 2719 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2720 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2721 continue; 2722 } 2723 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2724 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2725 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2726 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2727 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2728 Opcode-OPC_CheckChild0Type)) 2729 break; 2730 continue; 2731 case OPC_CheckCondCode: 2732 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2733 continue; 2734 case OPC_CheckValueType: 2735 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2736 break; 2737 continue; 2738 case OPC_CheckInteger: 2739 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2740 continue; 2741 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer: 2742 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer: 2743 case OPC_CheckChild4Integer: 2744 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N, 2745 Opcode-OPC_CheckChild0Integer)) break; 2746 continue; 2747 case OPC_CheckAndImm: 2748 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2749 continue; 2750 case OPC_CheckOrImm: 2751 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2752 continue; 2753 2754 case OPC_CheckFoldableChainNode: { 2755 assert(NodeStack.size() != 1 && "No parent node"); 2756 // Verify that all intermediate nodes between the root and this one have 2757 // a single use. 2758 bool HasMultipleUses = false; 2759 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2760 if (!NodeStack[i].hasOneUse()) { 2761 HasMultipleUses = true; 2762 break; 2763 } 2764 if (HasMultipleUses) break; 2765 2766 // Check to see that the target thinks this is profitable to fold and that 2767 // we can fold it without inducing cycles in the graph. 2768 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2769 NodeToMatch) || 2770 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2771 NodeToMatch, OptLevel, 2772 true/*We validate our own chains*/)) 2773 break; 2774 2775 continue; 2776 } 2777 case OPC_EmitInteger: { 2778 MVT::SimpleValueType VT = 2779 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2780 int64_t Val = MatcherTable[MatcherIndex++]; 2781 if (Val & 128) 2782 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2783 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2784 CurDAG->getTargetConstant(Val, VT), nullptr)); 2785 continue; 2786 } 2787 case OPC_EmitRegister: { 2788 MVT::SimpleValueType VT = 2789 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2790 unsigned RegNo = MatcherTable[MatcherIndex++]; 2791 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2792 CurDAG->getRegister(RegNo, VT), nullptr)); 2793 continue; 2794 } 2795 case OPC_EmitRegister2: { 2796 // For targets w/ more than 256 register names, the register enum 2797 // values are stored in two bytes in the matcher table (just like 2798 // opcodes). 2799 MVT::SimpleValueType VT = 2800 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2801 unsigned RegNo = MatcherTable[MatcherIndex++]; 2802 RegNo |= MatcherTable[MatcherIndex++] << 8; 2803 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2804 CurDAG->getRegister(RegNo, VT), nullptr)); 2805 continue; 2806 } 2807 2808 case OPC_EmitConvertToTarget: { 2809 // Convert from IMM/FPIMM to target version. 2810 unsigned RecNo = MatcherTable[MatcherIndex++]; 2811 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 2812 SDValue Imm = RecordedNodes[RecNo].first; 2813 2814 if (Imm->getOpcode() == ISD::Constant) { 2815 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2816 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2817 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2818 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2819 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2820 } 2821 2822 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2823 continue; 2824 } 2825 2826 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2827 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2828 // These are space-optimized forms of OPC_EmitMergeInputChains. 2829 assert(!InputChain.getNode() && 2830 "EmitMergeInputChains should be the first chain producing node"); 2831 assert(ChainNodesMatched.empty() && 2832 "Should only have one EmitMergeInputChains per match"); 2833 2834 // Read all of the chained nodes. 2835 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2836 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2837 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2838 2839 // FIXME: What if other value results of the node have uses not matched 2840 // by this pattern? 2841 if (ChainNodesMatched.back() != NodeToMatch && 2842 !RecordedNodes[RecNo].first.hasOneUse()) { 2843 ChainNodesMatched.clear(); 2844 break; 2845 } 2846 2847 // Merge the input chains if they are not intra-pattern references. 2848 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2849 2850 if (!InputChain.getNode()) 2851 break; // Failed to merge. 2852 continue; 2853 } 2854 2855 case OPC_EmitMergeInputChains: { 2856 assert(!InputChain.getNode() && 2857 "EmitMergeInputChains should be the first chain producing node"); 2858 // This node gets a list of nodes we matched in the input that have 2859 // chains. We want to token factor all of the input chains to these nodes 2860 // together. However, if any of the input chains is actually one of the 2861 // nodes matched in this pattern, then we have an intra-match reference. 2862 // Ignore these because the newly token factored chain should not refer to 2863 // the old nodes. 2864 unsigned NumChains = MatcherTable[MatcherIndex++]; 2865 assert(NumChains != 0 && "Can't TF zero chains"); 2866 2867 assert(ChainNodesMatched.empty() && 2868 "Should only have one EmitMergeInputChains per match"); 2869 2870 // Read all of the chained nodes. 2871 for (unsigned i = 0; i != NumChains; ++i) { 2872 unsigned RecNo = MatcherTable[MatcherIndex++]; 2873 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2874 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2875 2876 // FIXME: What if other value results of the node have uses not matched 2877 // by this pattern? 2878 if (ChainNodesMatched.back() != NodeToMatch && 2879 !RecordedNodes[RecNo].first.hasOneUse()) { 2880 ChainNodesMatched.clear(); 2881 break; 2882 } 2883 } 2884 2885 // If the inner loop broke out, the match fails. 2886 if (ChainNodesMatched.empty()) 2887 break; 2888 2889 // Merge the input chains if they are not intra-pattern references. 2890 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2891 2892 if (!InputChain.getNode()) 2893 break; // Failed to merge. 2894 2895 continue; 2896 } 2897 2898 case OPC_EmitCopyToReg: { 2899 unsigned RecNo = MatcherTable[MatcherIndex++]; 2900 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 2901 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2902 2903 if (!InputChain.getNode()) 2904 InputChain = CurDAG->getEntryNode(); 2905 2906 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2907 DestPhysReg, RecordedNodes[RecNo].first, 2908 InputGlue); 2909 2910 InputGlue = InputChain.getValue(1); 2911 continue; 2912 } 2913 2914 case OPC_EmitNodeXForm: { 2915 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2916 unsigned RecNo = MatcherTable[MatcherIndex++]; 2917 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 2918 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2919 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr)); 2920 continue; 2921 } 2922 2923 case OPC_EmitNode: 2924 case OPC_MorphNodeTo: { 2925 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2926 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2927 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2928 // Get the result VT list. 2929 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2930 SmallVector<EVT, 4> VTs; 2931 for (unsigned i = 0; i != NumVTs; ++i) { 2932 MVT::SimpleValueType VT = 2933 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2934 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2935 VTs.push_back(VT); 2936 } 2937 2938 if (EmitNodeInfo & OPFL_Chain) 2939 VTs.push_back(MVT::Other); 2940 if (EmitNodeInfo & OPFL_GlueOutput) 2941 VTs.push_back(MVT::Glue); 2942 2943 // This is hot code, so optimize the two most common cases of 1 and 2 2944 // results. 2945 SDVTList VTList; 2946 if (VTs.size() == 1) 2947 VTList = CurDAG->getVTList(VTs[0]); 2948 else if (VTs.size() == 2) 2949 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2950 else 2951 VTList = CurDAG->getVTList(VTs); 2952 2953 // Get the operand list. 2954 unsigned NumOps = MatcherTable[MatcherIndex++]; 2955 SmallVector<SDValue, 8> Ops; 2956 for (unsigned i = 0; i != NumOps; ++i) { 2957 unsigned RecNo = MatcherTable[MatcherIndex++]; 2958 if (RecNo & 128) 2959 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2960 2961 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2962 Ops.push_back(RecordedNodes[RecNo].first); 2963 } 2964 2965 // If there are variadic operands to add, handle them now. 2966 if (EmitNodeInfo & OPFL_VariadicInfo) { 2967 // Determine the start index to copy from. 2968 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2969 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2970 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2971 "Invalid variadic node"); 2972 // Copy all of the variadic operands, not including a potential glue 2973 // input. 2974 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2975 i != e; ++i) { 2976 SDValue V = NodeToMatch->getOperand(i); 2977 if (V.getValueType() == MVT::Glue) break; 2978 Ops.push_back(V); 2979 } 2980 } 2981 2982 // If this has chain/glue inputs, add them. 2983 if (EmitNodeInfo & OPFL_Chain) 2984 Ops.push_back(InputChain); 2985 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr) 2986 Ops.push_back(InputGlue); 2987 2988 // Create the node. 2989 SDNode *Res = nullptr; 2990 if (Opcode != OPC_MorphNodeTo) { 2991 // If this is a normal EmitNode command, just create the new node and 2992 // add the results to the RecordedNodes list. 2993 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2994 VTList, Ops); 2995 2996 // Add all the non-glue/non-chain results to the RecordedNodes list. 2997 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2998 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2999 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 3000 nullptr)); 3001 } 3002 3003 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 3004 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo); 3005 } else { 3006 // NodeToMatch was eliminated by CSE when the target changed the DAG. 3007 // We will visit the equivalent node later. 3008 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 3009 return nullptr; 3010 } 3011 3012 // If the node had chain/glue results, update our notion of the current 3013 // chain and glue. 3014 if (EmitNodeInfo & OPFL_GlueOutput) { 3015 InputGlue = SDValue(Res, VTs.size()-1); 3016 if (EmitNodeInfo & OPFL_Chain) 3017 InputChain = SDValue(Res, VTs.size()-2); 3018 } else if (EmitNodeInfo & OPFL_Chain) 3019 InputChain = SDValue(Res, VTs.size()-1); 3020 3021 // If the OPFL_MemRefs glue is set on this node, slap all of the 3022 // accumulated memrefs onto it. 3023 // 3024 // FIXME: This is vastly incorrect for patterns with multiple outputs 3025 // instructions that access memory and for ComplexPatterns that match 3026 // loads. 3027 if (EmitNodeInfo & OPFL_MemRefs) { 3028 // Only attach load or store memory operands if the generated 3029 // instruction may load or store. 3030 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 3031 bool mayLoad = MCID.mayLoad(); 3032 bool mayStore = MCID.mayStore(); 3033 3034 unsigned NumMemRefs = 0; 3035 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3036 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3037 if ((*I)->isLoad()) { 3038 if (mayLoad) 3039 ++NumMemRefs; 3040 } else if ((*I)->isStore()) { 3041 if (mayStore) 3042 ++NumMemRefs; 3043 } else { 3044 ++NumMemRefs; 3045 } 3046 } 3047 3048 MachineSDNode::mmo_iterator MemRefs = 3049 MF->allocateMemRefsArray(NumMemRefs); 3050 3051 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 3052 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3053 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3054 if ((*I)->isLoad()) { 3055 if (mayLoad) 3056 *MemRefsPos++ = *I; 3057 } else if ((*I)->isStore()) { 3058 if (mayStore) 3059 *MemRefsPos++ = *I; 3060 } else { 3061 *MemRefsPos++ = *I; 3062 } 3063 } 3064 3065 cast<MachineSDNode>(Res) 3066 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 3067 } 3068 3069 DEBUG(dbgs() << " " 3070 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 3071 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 3072 3073 // If this was a MorphNodeTo then we're completely done! 3074 if (Opcode == OPC_MorphNodeTo) { 3075 // Update chain and glue uses. 3076 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3077 InputGlue, GlueResultNodesMatched, true); 3078 return Res; 3079 } 3080 3081 continue; 3082 } 3083 3084 case OPC_MarkGlueResults: { 3085 unsigned NumNodes = MatcherTable[MatcherIndex++]; 3086 3087 // Read and remember all the glue-result nodes. 3088 for (unsigned i = 0; i != NumNodes; ++i) { 3089 unsigned RecNo = MatcherTable[MatcherIndex++]; 3090 if (RecNo & 128) 3091 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3092 3093 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 3094 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3095 } 3096 continue; 3097 } 3098 3099 case OPC_CompleteMatch: { 3100 // The match has been completed, and any new nodes (if any) have been 3101 // created. Patch up references to the matched dag to use the newly 3102 // created nodes. 3103 unsigned NumResults = MatcherTable[MatcherIndex++]; 3104 3105 for (unsigned i = 0; i != NumResults; ++i) { 3106 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3107 if (ResSlot & 128) 3108 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3109 3110 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3111 SDValue Res = RecordedNodes[ResSlot].first; 3112 3113 assert(i < NodeToMatch->getNumValues() && 3114 NodeToMatch->getValueType(i) != MVT::Other && 3115 NodeToMatch->getValueType(i) != MVT::Glue && 3116 "Invalid number of results to complete!"); 3117 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3118 NodeToMatch->getValueType(i) == MVT::iPTR || 3119 Res.getValueType() == MVT::iPTR || 3120 NodeToMatch->getValueType(i).getSizeInBits() == 3121 Res.getValueType().getSizeInBits()) && 3122 "invalid replacement"); 3123 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3124 } 3125 3126 // If the root node defines glue, add it to the glue nodes to update list. 3127 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3128 GlueResultNodesMatched.push_back(NodeToMatch); 3129 3130 // Update chain and glue uses. 3131 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3132 InputGlue, GlueResultNodesMatched, false); 3133 3134 assert(NodeToMatch->use_empty() && 3135 "Didn't replace all uses of the node?"); 3136 3137 // FIXME: We just return here, which interacts correctly with SelectRoot 3138 // above. We should fix this to not return an SDNode* anymore. 3139 return nullptr; 3140 } 3141 } 3142 3143 // If the code reached this point, then the match failed. See if there is 3144 // another child to try in the current 'Scope', otherwise pop it until we 3145 // find a case to check. 3146 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3147 ++NumDAGIselRetries; 3148 while (1) { 3149 if (MatchScopes.empty()) { 3150 CannotYetSelect(NodeToMatch); 3151 return nullptr; 3152 } 3153 3154 // Restore the interpreter state back to the point where the scope was 3155 // formed. 3156 MatchScope &LastScope = MatchScopes.back(); 3157 RecordedNodes.resize(LastScope.NumRecordedNodes); 3158 NodeStack.clear(); 3159 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3160 N = NodeStack.back(); 3161 3162 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3163 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3164 MatcherIndex = LastScope.FailIndex; 3165 3166 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3167 3168 InputChain = LastScope.InputChain; 3169 InputGlue = LastScope.InputGlue; 3170 if (!LastScope.HasChainNodesMatched) 3171 ChainNodesMatched.clear(); 3172 if (!LastScope.HasGlueResultNodesMatched) 3173 GlueResultNodesMatched.clear(); 3174 3175 // Check to see what the offset is at the new MatcherIndex. If it is zero 3176 // we have reached the end of this scope, otherwise we have another child 3177 // in the current scope to try. 3178 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3179 if (NumToSkip & 128) 3180 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3181 3182 // If we have another child in this scope to match, update FailIndex and 3183 // try it. 3184 if (NumToSkip != 0) { 3185 LastScope.FailIndex = MatcherIndex+NumToSkip; 3186 break; 3187 } 3188 3189 // End of this scope, pop it and try the next child in the containing 3190 // scope. 3191 MatchScopes.pop_back(); 3192 } 3193 } 3194} 3195 3196 3197 3198void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3199 std::string msg; 3200 raw_string_ostream Msg(msg); 3201 Msg << "Cannot select: "; 3202 3203 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3204 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3205 N->getOpcode() != ISD::INTRINSIC_VOID) { 3206 N->printrFull(Msg, CurDAG); 3207 Msg << "\nIn function: " << MF->getName(); 3208 } else { 3209 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3210 unsigned iid = 3211 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3212 if (iid < Intrinsic::num_intrinsics) 3213 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3214 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3215 Msg << "target intrinsic %" << TII->getName(iid); 3216 else 3217 Msg << "unknown intrinsic #" << iid; 3218 } 3219 report_fatal_error(Msg.str()); 3220} 3221 3222char SelectionDAGISel::ID = 0; 3223