SelectionDAGISel.cpp revision dd437ba15e00d1a137e0c6e3ca1ff213ed6a2aa0
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 CodeGenOpt::Level OptLevel) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (OptLevel == CodeGenOpt::None) 143 return createFastDAGScheduler(IS, OptLevel); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, OptLevel); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, OptLevel); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and this method is called to expand it into a sequence of 157// instructions, potentially also creating new basic blocks and control flow. 158// When new basic blocks are inserted and the edges from MBB to its successors 159// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 160// DenseMap. 161MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 162 MachineBasicBlock *MBB, 163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 164#ifndef NDEBUG 165 dbgs() << "If a target marks an instruction with " 166 "'usesCustomInserter', it must implement " 167 "TargetLowering::EmitInstrWithCustomInserter!"; 168#endif 169 llvm_unreachable(0); 170 return 0; 171} 172 173/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 174/// physical register has only a single copy use, then coalesced the copy 175/// if possible. 176static void EmitLiveInCopy(MachineBasicBlock *MBB, 177 MachineBasicBlock::iterator &InsertPos, 178 unsigned VirtReg, unsigned PhysReg, 179 const TargetRegisterClass *RC, 180 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 181 const MachineRegisterInfo &MRI, 182 const TargetRegisterInfo &TRI, 183 const TargetInstrInfo &TII) { 184 unsigned NumUses = 0; 185 MachineInstr *UseMI = NULL; 186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 187 UE = MRI.use_end(); UI != UE; ++UI) { 188 UseMI = &*UI; 189 if (++NumUses > 1) 190 break; 191 } 192 193 // If the number of uses is not one, or the use is not a move instruction, 194 // don't coalesce. Also, only coalesce away a virtual register to virtual 195 // register copy. 196 bool Coalesced = false; 197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 198 if (NumUses == 1 && 199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 200 TargetRegisterInfo::isVirtualRegister(DstReg)) { 201 VirtReg = DstReg; 202 Coalesced = true; 203 } 204 205 // Now find an ideal location to insert the copy. 206 MachineBasicBlock::iterator Pos = InsertPos; 207 while (Pos != MBB->begin()) { 208 MachineInstr *PrevMI = prior(Pos); 209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 210 // copyRegToReg might emit multiple instructions to do a copy. 211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 213 // This is what the BB looks like right now: 214 // r1024 = mov r0 215 // ... 216 // r1 = mov r1024 217 // 218 // We want to insert "r1025 = mov r1". Inserting this copy below the 219 // move to r1024 makes it impossible for that move to be coalesced. 220 // 221 // r1025 = mov r1 222 // r1024 = mov r0 223 // ... 224 // r1 = mov 1024 225 // r2 = mov 1025 226 break; // Woot! Found a good location. 227 --Pos; 228 } 229 230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 231 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 232 (void) Emitted; 233 234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 235 if (Coalesced) { 236 if (&*InsertPos == UseMI) ++InsertPos; 237 MBB->erase(UseMI); 238 } 239} 240 241/// EmitLiveInCopies - If this is the first basic block in the function, 242/// and if it has live ins that need to be copied into vregs, emit the 243/// copies into the block. 244static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 245 const MachineRegisterInfo &MRI, 246 const TargetRegisterInfo &TRI, 247 const TargetInstrInfo &TII) { 248 if (SchedLiveInCopies) { 249 // Emit the copies at a heuristically-determined location in the block. 250 DenseMap<MachineInstr*, unsigned> CopyRegMap; 251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 253 E = MRI.livein_end(); LI != E; ++LI) 254 if (LI->second) { 255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 257 RC, CopyRegMap, MRI, TRI, TII); 258 } 259 } else { 260 // Emit the copies into the top of the block. 261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 262 E = MRI.livein_end(); LI != E; ++LI) 263 if (LI->second) { 264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 266 LI->second, LI->first, RC, RC); 267 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 268 (void) Emitted; 269 } 270 } 271} 272 273//===----------------------------------------------------------------------===// 274// SelectionDAGISel code 275//===----------------------------------------------------------------------===// 276 277SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 279 FuncInfo(new FunctionLoweringInfo(TLI)), 280 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 282 GFI(), 283 OptLevel(OL), 284 DAGSize(0) 285{} 286 287SelectionDAGISel::~SelectionDAGISel() { 288 delete SDB; 289 delete CurDAG; 290 delete FuncInfo; 291} 292 293unsigned SelectionDAGISel::MakeReg(EVT VT) { 294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 295} 296 297void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 298 AU.addRequired<AliasAnalysis>(); 299 AU.addPreserved<AliasAnalysis>(); 300 AU.addRequired<GCModuleInfo>(); 301 AU.addPreserved<GCModuleInfo>(); 302 AU.addRequired<DwarfWriter>(); 303 AU.addPreserved<DwarfWriter>(); 304 MachineFunctionPass::getAnalysisUsage(AU); 305} 306 307bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 308 Function &Fn = *mf.getFunction(); 309 310 // Do some sanity-checking on the command-line options. 311 assert((!EnableFastISelVerbose || EnableFastISel) && 312 "-fast-isel-verbose requires -fast-isel"); 313 assert((!EnableFastISelAbort || EnableFastISel) && 314 "-fast-isel-abort requires -fast-isel"); 315 316 // Get alias analysis for load/store combining. 317 AA = &getAnalysis<AliasAnalysis>(); 318 319 MF = &mf; 320 const TargetInstrInfo &TII = *TM.getInstrInfo(); 321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 322 323 if (Fn.hasGC()) 324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 325 else 326 GFI = 0; 327 RegInfo = &MF->getRegInfo(); 328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 329 330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 332 CurDAG->init(*MF, MMI, DW); 333 FuncInfo->set(Fn, *MF, EnableFastISel); 334 SDB->init(GFI, *AA); 335 336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 338 // Mark landing pad. 339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 340 341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 342 343 // If the first basic block in the function has live ins that need to be 344 // copied into vregs, emit the copies into the top of the block before 345 // emitting the code for the block. 346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 347 348 // Add function live-ins to entry block live-in set. 349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 350 E = RegInfo->livein_end(); I != E; ++I) 351 MF->begin()->addLiveIn(I->first); 352 353#ifndef NDEBUG 354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 355 "Not all catch info was assigned to a landing pad!"); 356#endif 357 358 FuncInfo->clear(); 359 360 return true; 361} 362 363/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 364/// attached with this instruction. 365static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 366 SelectionDAGBuilder *SDB, 367 FastISel *FastIS, MachineFunction *MF) { 368 if (isa<DbgInfoIntrinsic>(I)) return; 369 370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 371 DILocation DILoc(Dbg); 372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 373 374 SDB->setCurDebugLoc(Loc); 375 376 if (FastIS) 377 FastIS->setCurDebugLoc(Loc); 378 379 // If the function doesn't have a default debug location yet, set 380 // it. This is kind of a hack. 381 if (MF->getDefaultDebugLoc().isUnknown()) 382 MF->setDefaultDebugLoc(Loc); 383 } 384} 385 386/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 387static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 389 if (FastIS) 390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 391} 392 393void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 394 BasicBlock::iterator Begin, 395 BasicBlock::iterator End, 396 bool &HadTailCall) { 397 SDB->setCurrentBasicBlock(BB); 398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 399 400 // Lower all of the non-terminator instructions. If a call is emitted 401 // as a tail call, cease emitting nodes for this block. 402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 404 405 if (!isa<TerminatorInst>(I)) { 406 SDB->visit(*I); 407 408 // Set the current debug location back to "unknown" so that it doesn't 409 // spuriously apply to subsequent instructions. 410 ResetDebugLoc(SDB, 0); 411 } 412 } 413 414 if (!SDB->HasTailCall) { 415 // Ensure that all instructions which are used outside of their defining 416 // blocks are available as virtual registers. Invoke is handled elsewhere. 417 for (BasicBlock::iterator I = Begin; I != End; ++I) 418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 419 SDB->CopyToExportRegsIfNeeded(I); 420 421 // Handle PHI nodes in successor blocks. 422 if (End == LLVMBB->end()) { 423 HandlePHINodesInSuccessorBlocks(LLVMBB); 424 425 // Lower the terminator after the copies are emitted. 426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 427 SDB->visit(*LLVMBB->getTerminator()); 428 ResetDebugLoc(SDB, 0); 429 } 430 } 431 432 // Make sure the root of the DAG is up-to-date. 433 CurDAG->setRoot(SDB->getControlRoot()); 434 435 // Final step, emit the lowered DAG as machine code. 436 CodeGenAndEmitDAG(); 437 HadTailCall = SDB->HasTailCall; 438 SDB->clear(); 439} 440 441namespace { 442/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 443/// nodes from the worklist. 444class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 445 SmallVector<SDNode*, 128> &Worklist; 446public: 447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {} 448 449 virtual void NodeDeleted(SDNode *N, SDNode *E) { 450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 451 Worklist.end()); 452 } 453 454 virtual void NodeUpdated(SDNode *N) { 455 // Ignore updates. 456 } 457}; 458} 459 460/// ShrinkDemandedOps - A late transformation pass that shrink expressions 461/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 462/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 463void SelectionDAGISel::ShrinkDemandedOps() { 464 SmallVector<SDNode*, 128> Worklist; 465 466 // Add all the dag nodes to the worklist. 467 Worklist.reserve(CurDAG->allnodes_size()); 468 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 469 E = CurDAG->allnodes_end(); I != E; ++I) 470 Worklist.push_back(I); 471 472 APInt Mask; 473 APInt KnownZero; 474 APInt KnownOne; 475 476 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 477 while (!Worklist.empty()) { 478 SDNode *N = Worklist.pop_back_val(); 479 480 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 481 CurDAG->DeleteNode(N); 482 continue; 483 } 484 485 // Run ShrinkDemandedOp on scalar binary operations. 486 if (N->getNumValues() == 1 && 487 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) { 488 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 489 APInt Demanded = APInt::getAllOnesValue(BitWidth); 490 APInt KnownZero, KnownOne; 491 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 492 KnownZero, KnownOne, TLO)) { 493 // Revisit the node. 494 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 495 Worklist.end()); 496 Worklist.push_back(N); 497 498 // Replace the old value with the new one. 499 DEBUG(errs() << "\nReplacing "; 500 TLO.Old.getNode()->dump(CurDAG); 501 errs() << "\nWith: "; 502 TLO.New.getNode()->dump(CurDAG); 503 errs() << '\n'); 504 505 Worklist.push_back(TLO.New.getNode()); 506 507 SDOPsWorkListRemover DeadNodes(Worklist); 508 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 509 510 if (TLO.Old.getNode()->use_empty()) { 511 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 512 i != e; ++i) { 513 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 514 if (OpNode->hasOneUse()) { 515 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 516 OpNode), Worklist.end()); 517 Worklist.push_back(OpNode); 518 } 519 } 520 521 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 522 TLO.Old.getNode()), Worklist.end()); 523 CurDAG->DeleteNode(TLO.Old.getNode()); 524 } 525 } 526 } 527 } 528} 529 530void SelectionDAGISel::ComputeLiveOutVRegInfo() { 531 SmallPtrSet<SDNode*, 128> VisitedNodes; 532 SmallVector<SDNode*, 128> Worklist; 533 534 Worklist.push_back(CurDAG->getRoot().getNode()); 535 536 APInt Mask; 537 APInt KnownZero; 538 APInt KnownOne; 539 540 do { 541 SDNode *N = Worklist.pop_back_val(); 542 543 // If we've already seen this node, ignore it. 544 if (!VisitedNodes.insert(N)) 545 continue; 546 547 // Otherwise, add all chain operands to the worklist. 548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 549 if (N->getOperand(i).getValueType() == MVT::Other) 550 Worklist.push_back(N->getOperand(i).getNode()); 551 552 // If this is a CopyToReg with a vreg dest, process it. 553 if (N->getOpcode() != ISD::CopyToReg) 554 continue; 555 556 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 557 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 558 continue; 559 560 // Ignore non-scalar or non-integer values. 561 SDValue Src = N->getOperand(2); 562 EVT SrcVT = Src.getValueType(); 563 if (!SrcVT.isInteger() || SrcVT.isVector()) 564 continue; 565 566 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 567 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 568 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 569 570 // Only install this information if it tells us something. 571 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 572 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 573 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 574 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 575 FunctionLoweringInfo::LiveOutInfo &LOI = 576 FuncInfo->LiveOutRegInfo[DestReg]; 577 LOI.NumSignBits = NumSignBits; 578 LOI.KnownOne = KnownOne; 579 LOI.KnownZero = KnownZero; 580 } 581 } while (!Worklist.empty()); 582} 583 584void SelectionDAGISel::CodeGenAndEmitDAG() { 585 std::string GroupName; 586 if (TimePassesIsEnabled) 587 GroupName = "Instruction Selection and Scheduling"; 588 std::string BlockName; 589 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 590 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 591 ViewSUnitDAGs) 592 BlockName = MF->getFunction()->getNameStr() + ":" + 593 BB->getBasicBlock()->getNameStr(); 594 595 DEBUG(dbgs() << "Initial selection DAG:\n"); 596 DEBUG(CurDAG->dump()); 597 598 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 599 600 // Run the DAG combiner in pre-legalize mode. 601 if (TimePassesIsEnabled) { 602 NamedRegionTimer T("DAG Combining 1", GroupName); 603 CurDAG->Combine(Unrestricted, *AA, OptLevel); 604 } else { 605 CurDAG->Combine(Unrestricted, *AA, OptLevel); 606 } 607 608 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 609 DEBUG(CurDAG->dump()); 610 611 // Second step, hack on the DAG until it only uses operations and types that 612 // the target supports. 613 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 614 BlockName); 615 616 bool Changed; 617 if (TimePassesIsEnabled) { 618 NamedRegionTimer T("Type Legalization", GroupName); 619 Changed = CurDAG->LegalizeTypes(); 620 } else { 621 Changed = CurDAG->LegalizeTypes(); 622 } 623 624 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 625 DEBUG(CurDAG->dump()); 626 627 if (Changed) { 628 if (ViewDAGCombineLT) 629 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 630 631 // Run the DAG combiner in post-type-legalize mode. 632 if (TimePassesIsEnabled) { 633 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 634 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 635 } else { 636 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 637 } 638 639 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 640 DEBUG(CurDAG->dump()); 641 } 642 643 if (TimePassesIsEnabled) { 644 NamedRegionTimer T("Vector Legalization", GroupName); 645 Changed = CurDAG->LegalizeVectors(); 646 } else { 647 Changed = CurDAG->LegalizeVectors(); 648 } 649 650 if (Changed) { 651 if (TimePassesIsEnabled) { 652 NamedRegionTimer T("Type Legalization 2", GroupName); 653 CurDAG->LegalizeTypes(); 654 } else { 655 CurDAG->LegalizeTypes(); 656 } 657 658 if (ViewDAGCombineLT) 659 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 660 661 // Run the DAG combiner in post-type-legalize mode. 662 if (TimePassesIsEnabled) { 663 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 664 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 665 } else { 666 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 667 } 668 669 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 670 DEBUG(CurDAG->dump()); 671 } 672 673 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 674 675 if (TimePassesIsEnabled) { 676 NamedRegionTimer T("DAG Legalization", GroupName); 677 CurDAG->Legalize(OptLevel); 678 } else { 679 CurDAG->Legalize(OptLevel); 680 } 681 682 DEBUG(dbgs() << "Legalized selection DAG:\n"); 683 DEBUG(CurDAG->dump()); 684 685 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 686 687 // Run the DAG combiner in post-legalize mode. 688 if (TimePassesIsEnabled) { 689 NamedRegionTimer T("DAG Combining 2", GroupName); 690 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 691 } else { 692 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 693 } 694 695 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 696 DEBUG(CurDAG->dump()); 697 698 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 699 700 if (OptLevel != CodeGenOpt::None) { 701 ShrinkDemandedOps(); 702 ComputeLiveOutVRegInfo(); 703 } 704 705 // Third, instruction select all of the operations to machine code, adding the 706 // code to the MachineBasicBlock. 707 if (TimePassesIsEnabled) { 708 NamedRegionTimer T("Instruction Selection", GroupName); 709 InstructionSelect(); 710 } else { 711 InstructionSelect(); 712 } 713 714 DEBUG(dbgs() << "Selected selection DAG:\n"); 715 DEBUG(CurDAG->dump()); 716 717 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 718 719 // Schedule machine code. 720 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 721 if (TimePassesIsEnabled) { 722 NamedRegionTimer T("Instruction Scheduling", GroupName); 723 Scheduler->Run(CurDAG, BB, BB->end()); 724 } else { 725 Scheduler->Run(CurDAG, BB, BB->end()); 726 } 727 728 if (ViewSUnitDAGs) Scheduler->viewGraph(); 729 730 // Emit machine code to BB. This can change 'BB' to the last block being 731 // inserted into. 732 if (TimePassesIsEnabled) { 733 NamedRegionTimer T("Instruction Creation", GroupName); 734 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 735 } else { 736 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 737 } 738 739 // Free the scheduler state. 740 if (TimePassesIsEnabled) { 741 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 742 delete Scheduler; 743 } else { 744 delete Scheduler; 745 } 746 747 DEBUG(dbgs() << "Selected machine code:\n"); 748 DEBUG(BB->dump()); 749} 750 751void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 752 MachineFunction &MF, 753 MachineModuleInfo *MMI, 754 DwarfWriter *DW, 755 const TargetInstrInfo &TII) { 756 // Initialize the Fast-ISel state, if needed. 757 FastISel *FastIS = 0; 758 if (EnableFastISel) 759 FastIS = TLI.createFastISel(MF, MMI, DW, 760 FuncInfo->ValueMap, 761 FuncInfo->MBBMap, 762 FuncInfo->StaticAllocaMap 763#ifndef NDEBUG 764 , FuncInfo->CatchInfoLost 765#endif 766 ); 767 768 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 769 770 // Iterate over all basic blocks in the function. 771 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 772 BasicBlock *LLVMBB = &*I; 773 BB = FuncInfo->MBBMap[LLVMBB]; 774 775 BasicBlock::iterator const Begin = LLVMBB->begin(); 776 BasicBlock::iterator const End = LLVMBB->end(); 777 BasicBlock::iterator BI = Begin; 778 779 // Lower any arguments needed in this block if this is the entry block. 780 bool SuppressFastISel = false; 781 if (LLVMBB == &Fn.getEntryBlock()) { 782 LowerArguments(LLVMBB); 783 784 // If any of the arguments has the byval attribute, forgo 785 // fast-isel in the entry block. 786 if (FastIS) { 787 unsigned j = 1; 788 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 789 I != E; ++I, ++j) 790 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 791 if (EnableFastISelVerbose || EnableFastISelAbort) 792 dbgs() << "FastISel skips entry block due to byval argument\n"; 793 SuppressFastISel = true; 794 break; 795 } 796 } 797 } 798 799 if (MMI && BB->isLandingPad()) { 800 // Add a label to mark the beginning of the landing pad. Deletion of the 801 // landing pad can thus be detected via the MachineModuleInfo. 802 unsigned LabelID = MMI->addLandingPad(BB); 803 804 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 805 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 806 807 // Mark exception register as live in. 808 unsigned Reg = TLI.getExceptionAddressRegister(); 809 if (Reg) BB->addLiveIn(Reg); 810 811 // Mark exception selector register as live in. 812 Reg = TLI.getExceptionSelectorRegister(); 813 if (Reg) BB->addLiveIn(Reg); 814 815 // FIXME: Hack around an exception handling flaw (PR1508): the personality 816 // function and list of typeids logically belong to the invoke (or, if you 817 // like, the basic block containing the invoke), and need to be associated 818 // with it in the dwarf exception handling tables. Currently however the 819 // information is provided by an intrinsic (eh.selector) that can be moved 820 // to unexpected places by the optimizers: if the unwind edge is critical, 821 // then breaking it can result in the intrinsics being in the successor of 822 // the landing pad, not the landing pad itself. This results in exceptions 823 // not being caught because no typeids are associated with the invoke. 824 // This may not be the only way things can go wrong, but it is the only way 825 // we try to work around for the moment. 826 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 827 828 if (Br && Br->isUnconditional()) { // Critical edge? 829 BasicBlock::iterator I, E; 830 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 831 if (isa<EHSelectorInst>(I)) 832 break; 833 834 if (I == E) 835 // No catch info found - try to extract some from the successor. 836 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 837 } 838 } 839 840 // Before doing SelectionDAG ISel, see if FastISel has been requested. 841 if (FastIS && !SuppressFastISel) { 842 // Emit code for any incoming arguments. This must happen before 843 // beginning FastISel on the entry block. 844 if (LLVMBB == &Fn.getEntryBlock()) { 845 CurDAG->setRoot(SDB->getControlRoot()); 846 CodeGenAndEmitDAG(); 847 SDB->clear(); 848 } 849 FastIS->startNewBlock(BB); 850 // Do FastISel on as many instructions as possible. 851 for (; BI != End; ++BI) { 852 // Just before the terminator instruction, insert instructions to 853 // feed PHI nodes in successor blocks. 854 if (isa<TerminatorInst>(BI)) 855 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 856 ResetDebugLoc(SDB, FastIS); 857 if (EnableFastISelVerbose || EnableFastISelAbort) { 858 dbgs() << "FastISel miss: "; 859 BI->dump(); 860 } 861 assert(!EnableFastISelAbort && 862 "FastISel didn't handle a PHI in a successor"); 863 break; 864 } 865 866 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 867 868 // First try normal tablegen-generated "fast" selection. 869 if (FastIS->SelectInstruction(BI)) { 870 ResetDebugLoc(SDB, FastIS); 871 continue; 872 } 873 874 // Clear out the debug location so that it doesn't carry over to 875 // unrelated instructions. 876 ResetDebugLoc(SDB, FastIS); 877 878 // Then handle certain instructions as single-LLVM-Instruction blocks. 879 if (isa<CallInst>(BI)) { 880 if (EnableFastISelVerbose || EnableFastISelAbort) { 881 dbgs() << "FastISel missed call: "; 882 BI->dump(); 883 } 884 885 if (!BI->getType()->isVoidTy()) { 886 unsigned &R = FuncInfo->ValueMap[BI]; 887 if (!R) 888 R = FuncInfo->CreateRegForValue(BI); 889 } 890 891 bool HadTailCall = false; 892 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 893 894 // If the call was emitted as a tail call, we're done with the block. 895 if (HadTailCall) { 896 BI = End; 897 break; 898 } 899 900 // If the instruction was codegen'd with multiple blocks, 901 // inform the FastISel object where to resume inserting. 902 FastIS->setCurrentBlock(BB); 903 continue; 904 } 905 906 // Otherwise, give up on FastISel for the rest of the block. 907 // For now, be a little lenient about non-branch terminators. 908 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 909 if (EnableFastISelVerbose || EnableFastISelAbort) { 910 dbgs() << "FastISel miss: "; 911 BI->dump(); 912 } 913 if (EnableFastISelAbort) 914 // The "fast" selector couldn't handle something and bailed. 915 // For the purpose of debugging, just abort. 916 llvm_unreachable("FastISel didn't select the entire block"); 917 } 918 break; 919 } 920 } 921 922 // Run SelectionDAG instruction selection on the remainder of the block 923 // not handled by FastISel. If FastISel is not run, this is the entire 924 // block. 925 if (BI != End) { 926 bool HadTailCall; 927 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 928 } 929 930 FinishBasicBlock(); 931 } 932 933 delete FastIS; 934} 935 936void 937SelectionDAGISel::FinishBasicBlock() { 938 939 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 940 DEBUG(BB->dump()); 941 942 DEBUG(dbgs() << "Total amount of phi nodes to update: " 943 << SDB->PHINodesToUpdate.size() << "\n"); 944 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 945 dbgs() << "Node " << i << " : (" 946 << SDB->PHINodesToUpdate[i].first 947 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 948 949 // Next, now that we know what the last MBB the LLVM BB expanded is, update 950 // PHI nodes in successors. 951 if (SDB->SwitchCases.empty() && 952 SDB->JTCases.empty() && 953 SDB->BitTestCases.empty()) { 954 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 955 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 956 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 957 "This is not a machine PHI node that we are updating!"); 958 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 959 false)); 960 PHI->addOperand(MachineOperand::CreateMBB(BB)); 961 } 962 SDB->PHINodesToUpdate.clear(); 963 return; 964 } 965 966 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 967 // Lower header first, if it wasn't already lowered 968 if (!SDB->BitTestCases[i].Emitted) { 969 // Set the current basic block to the mbb we wish to insert the code into 970 BB = SDB->BitTestCases[i].Parent; 971 SDB->setCurrentBasicBlock(BB); 972 // Emit the code 973 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 974 CurDAG->setRoot(SDB->getRoot()); 975 CodeGenAndEmitDAG(); 976 SDB->clear(); 977 } 978 979 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 980 // Set the current basic block to the mbb we wish to insert the code into 981 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 982 SDB->setCurrentBasicBlock(BB); 983 // Emit the code 984 if (j+1 != ej) 985 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 986 SDB->BitTestCases[i].Reg, 987 SDB->BitTestCases[i].Cases[j]); 988 else 989 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 990 SDB->BitTestCases[i].Reg, 991 SDB->BitTestCases[i].Cases[j]); 992 993 994 CurDAG->setRoot(SDB->getRoot()); 995 CodeGenAndEmitDAG(); 996 SDB->clear(); 997 } 998 999 // Update PHI Nodes 1000 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1001 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1002 MachineBasicBlock *PHIBB = PHI->getParent(); 1003 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1004 "This is not a machine PHI node that we are updating!"); 1005 // This is "default" BB. We have two jumps to it. From "header" BB and 1006 // from last "case" BB. 1007 if (PHIBB == SDB->BitTestCases[i].Default) { 1008 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 1009 false)); 1010 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1011 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 1012 false)); 1013 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1014 back().ThisBB)); 1015 } 1016 // One of "cases" BB. 1017 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1018 j != ej; ++j) { 1019 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1020 if (cBB->isSuccessor(PHIBB)) { 1021 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, 1022 false)); 1023 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1024 } 1025 } 1026 } 1027 } 1028 SDB->BitTestCases.clear(); 1029 1030 // If the JumpTable record is filled in, then we need to emit a jump table. 1031 // Updating the PHI nodes is tricky in this case, since we need to determine 1032 // whether the PHI is a successor of the range check MBB or the jump table MBB 1033 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1034 // Lower header first, if it wasn't already lowered 1035 if (!SDB->JTCases[i].first.Emitted) { 1036 // Set the current basic block to the mbb we wish to insert the code into 1037 BB = SDB->JTCases[i].first.HeaderBB; 1038 SDB->setCurrentBasicBlock(BB); 1039 // Emit the code 1040 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1041 CurDAG->setRoot(SDB->getRoot()); 1042 CodeGenAndEmitDAG(); 1043 SDB->clear(); 1044 } 1045 1046 // Set the current basic block to the mbb we wish to insert the code into 1047 BB = SDB->JTCases[i].second.MBB; 1048 SDB->setCurrentBasicBlock(BB); 1049 // Emit the code 1050 SDB->visitJumpTable(SDB->JTCases[i].second); 1051 CurDAG->setRoot(SDB->getRoot()); 1052 CodeGenAndEmitDAG(); 1053 SDB->clear(); 1054 1055 // Update PHI Nodes 1056 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1057 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1058 MachineBasicBlock *PHIBB = PHI->getParent(); 1059 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1060 "This is not a machine PHI node that we are updating!"); 1061 // "default" BB. We can go there only from header BB. 1062 if (PHIBB == SDB->JTCases[i].second.Default) { 1063 PHI->addOperand 1064 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1065 PHI->addOperand 1066 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1067 } 1068 // JT BB. Just iterate over successors here 1069 if (BB->isSuccessor(PHIBB)) { 1070 PHI->addOperand 1071 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1072 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1073 } 1074 } 1075 } 1076 SDB->JTCases.clear(); 1077 1078 // If the switch block involved a branch to one of the actual successors, we 1079 // need to update PHI nodes in that block. 1080 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1081 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1082 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1083 "This is not a machine PHI node that we are updating!"); 1084 if (BB->isSuccessor(PHI->getParent())) { 1085 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1086 false)); 1087 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1088 } 1089 } 1090 1091 // If we generated any switch lowering information, build and codegen any 1092 // additional DAGs necessary. 1093 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1094 // Set the current basic block to the mbb we wish to insert the code into 1095 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1096 SDB->setCurrentBasicBlock(BB); 1097 1098 // Emit the code 1099 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1100 CurDAG->setRoot(SDB->getRoot()); 1101 CodeGenAndEmitDAG(); 1102 1103 // Handle any PHI nodes in successors of this chunk, as if we were coming 1104 // from the original BB before switch expansion. Note that PHI nodes can 1105 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1106 // handle them the right number of times. 1107 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1108 // If new BB's are created during scheduling, the edges may have been 1109 // updated. That is, the edge from ThisBB to BB may have been split and 1110 // BB's predecessor is now another block. 1111 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1112 SDB->EdgeMapping.find(BB); 1113 if (EI != SDB->EdgeMapping.end()) 1114 ThisBB = EI->second; 1115 1116 // BB may have been removed from the CFG if a branch was constant folded. 1117 if (ThisBB->isSuccessor(BB)) { 1118 for (MachineBasicBlock::iterator Phi = BB->begin(); 1119 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; 1120 ++Phi) { 1121 // This value for this PHI node is recorded in PHINodesToUpdate. 1122 for (unsigned pn = 0; ; ++pn) { 1123 assert(pn != SDB->PHINodesToUpdate.size() && 1124 "Didn't find PHI entry!"); 1125 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1126 Phi->addOperand(MachineOperand:: 1127 CreateReg(SDB->PHINodesToUpdate[pn].second, 1128 false)); 1129 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1130 break; 1131 } 1132 } 1133 } 1134 } 1135 1136 // Don't process RHS if same block as LHS. 1137 if (BB == SDB->SwitchCases[i].FalseBB) 1138 SDB->SwitchCases[i].FalseBB = 0; 1139 1140 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1141 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1142 SDB->SwitchCases[i].FalseBB = 0; 1143 } 1144 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1145 SDB->clear(); 1146 } 1147 SDB->SwitchCases.clear(); 1148 1149 SDB->PHINodesToUpdate.clear(); 1150} 1151 1152 1153/// Create the scheduler. If a specific scheduler was specified 1154/// via the SchedulerRegistry, use it, otherwise select the 1155/// one preferred by the target. 1156/// 1157ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1158 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1159 1160 if (!Ctor) { 1161 Ctor = ISHeuristic; 1162 RegisterScheduler::setDefault(Ctor); 1163 } 1164 1165 return Ctor(this, OptLevel); 1166} 1167 1168ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1169 return new ScheduleHazardRecognizer(); 1170} 1171 1172//===----------------------------------------------------------------------===// 1173// Helper functions used by the generated instruction selector. 1174//===----------------------------------------------------------------------===// 1175// Calls to these methods are generated by tblgen. 1176 1177/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1178/// the dag combiner simplified the 255, we still want to match. RHS is the 1179/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1180/// specified in the .td file (e.g. 255). 1181bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1182 int64_t DesiredMaskS) const { 1183 const APInt &ActualMask = RHS->getAPIntValue(); 1184 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1185 1186 // If the actual mask exactly matches, success! 1187 if (ActualMask == DesiredMask) 1188 return true; 1189 1190 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1191 if (ActualMask.intersects(~DesiredMask)) 1192 return false; 1193 1194 // Otherwise, the DAG Combiner may have proven that the value coming in is 1195 // either already zero or is not demanded. Check for known zero input bits. 1196 APInt NeededMask = DesiredMask & ~ActualMask; 1197 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1198 return true; 1199 1200 // TODO: check to see if missing bits are just not demanded. 1201 1202 // Otherwise, this pattern doesn't match. 1203 return false; 1204} 1205 1206/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1207/// the dag combiner simplified the 255, we still want to match. RHS is the 1208/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1209/// specified in the .td file (e.g. 255). 1210bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1211 int64_t DesiredMaskS) const { 1212 const APInt &ActualMask = RHS->getAPIntValue(); 1213 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1214 1215 // If the actual mask exactly matches, success! 1216 if (ActualMask == DesiredMask) 1217 return true; 1218 1219 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1220 if (ActualMask.intersects(~DesiredMask)) 1221 return false; 1222 1223 // Otherwise, the DAG Combiner may have proven that the value coming in is 1224 // either already zero or is not demanded. Check for known zero input bits. 1225 APInt NeededMask = DesiredMask & ~ActualMask; 1226 1227 APInt KnownZero, KnownOne; 1228 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1229 1230 // If all the missing bits in the or are already known to be set, match! 1231 if ((NeededMask & KnownOne) == NeededMask) 1232 return true; 1233 1234 // TODO: check to see if missing bits are just not demanded. 1235 1236 // Otherwise, this pattern doesn't match. 1237 return false; 1238} 1239 1240 1241/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1242/// by tblgen. Others should not call it. 1243void SelectionDAGISel:: 1244SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1245 std::vector<SDValue> InOps; 1246 std::swap(InOps, Ops); 1247 1248 Ops.push_back(InOps[0]); // input chain. 1249 Ops.push_back(InOps[1]); // input asm string. 1250 1251 unsigned i = 2, e = InOps.size(); 1252 if (InOps[e-1].getValueType() == MVT::Flag) 1253 --e; // Don't process a flag operand if it is here. 1254 1255 while (i != e) { 1256 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1257 if ((Flags & 7) != 4 /*MEM*/) { 1258 // Just skip over this operand, copying the operands verbatim. 1259 Ops.insert(Ops.end(), InOps.begin()+i, 1260 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1261 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1262 } else { 1263 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1264 "Memory operand with multiple values?"); 1265 // Otherwise, this is a memory operand. Ask the target to select it. 1266 std::vector<SDValue> SelOps; 1267 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1268 llvm_report_error("Could not match memory address. Inline asm" 1269 " failure!"); 1270 } 1271 1272 // Add this to the output node. 1273 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1274 MVT::i32)); 1275 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1276 i += 2; 1277 } 1278 } 1279 1280 // Add the flag input back if present. 1281 if (e != InOps.size()) 1282 Ops.push_back(InOps.back()); 1283} 1284 1285/// findFlagUse - Return use of EVT::Flag value produced by the specified 1286/// SDNode. 1287/// 1288static SDNode *findFlagUse(SDNode *N) { 1289 unsigned FlagResNo = N->getNumValues()-1; 1290 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1291 SDUse &Use = I.getUse(); 1292 if (Use.getResNo() == FlagResNo) 1293 return Use.getUser(); 1294 } 1295 return NULL; 1296} 1297 1298/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1299/// This function recursively traverses up the operand chain, ignoring 1300/// certain nodes. 1301static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1302 SDNode *Root, 1303 SmallPtrSet<SDNode*, 16> &Visited) { 1304 if (Use->getNodeId() < Def->getNodeId() || 1305 !Visited.insert(Use)) 1306 return false; 1307 1308 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1309 SDNode *N = Use->getOperand(i).getNode(); 1310 if (N == Def) { 1311 if (Use == ImmedUse || Use == Root) 1312 continue; // We are not looking for immediate use. 1313 assert(N != Root); 1314 return true; 1315 } 1316 1317 // Traverse up the operand chain. 1318 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1319 return true; 1320 } 1321 return false; 1322} 1323 1324/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1325/// be reached. Return true if that's the case. However, ignore direct uses 1326/// by ImmedUse (which would be U in the example illustrated in 1327/// IsLegalAndProfitableToFold) and by Root (which can happen in the store 1328/// case). 1329/// FIXME: to be really generic, we should allow direct use by any node 1330/// that is being folded. But realisticly since we only fold loads which 1331/// have one non-chain use, we only need to watch out for load/op/store 1332/// and load/op/cmp case where the root (store / cmp) may reach the load via 1333/// its chain operand. 1334static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1335 SmallPtrSet<SDNode*, 16> Visited; 1336 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1337} 1338 1339/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 1340/// U can be folded during instruction selection that starts at Root and 1341/// folding N is profitable. 1342bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 1343 SDNode *Root) const { 1344 if (OptLevel == CodeGenOpt::None) return false; 1345 1346 // If Root use can somehow reach N through a path that that doesn't contain 1347 // U then folding N would create a cycle. e.g. In the following 1348 // diagram, Root can reach N through X. If N is folded into into Root, then 1349 // X is both a predecessor and a successor of U. 1350 // 1351 // [N*] // 1352 // ^ ^ // 1353 // / \ // 1354 // [U*] [X]? // 1355 // ^ ^ // 1356 // \ / // 1357 // \ / // 1358 // [Root*] // 1359 // 1360 // * indicates nodes to be folded together. 1361 // 1362 // If Root produces a flag, then it gets (even more) interesting. Since it 1363 // will be "glued" together with its flag use in the scheduler, we need to 1364 // check if it might reach N. 1365 // 1366 // [N*] // 1367 // ^ ^ // 1368 // / \ // 1369 // [U*] [X]? // 1370 // ^ ^ // 1371 // \ \ // 1372 // \ | // 1373 // [Root*] | // 1374 // ^ | // 1375 // f | // 1376 // | / // 1377 // [Y] / // 1378 // ^ / // 1379 // f / // 1380 // | / // 1381 // [FU] // 1382 // 1383 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1384 // (call it Fold), then X is a predecessor of FU and a successor of 1385 // Fold. But since Fold and FU are flagged together, this will create 1386 // a cycle in the scheduling graph. 1387 1388 EVT VT = Root->getValueType(Root->getNumValues()-1); 1389 while (VT == MVT::Flag) { 1390 SDNode *FU = findFlagUse(Root); 1391 if (FU == NULL) 1392 break; 1393 Root = FU; 1394 VT = Root->getValueType(Root->getNumValues()-1); 1395 } 1396 1397 return !isNonImmUse(Root, N, U); 1398} 1399 1400SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1401 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1402 SelectInlineAsmMemoryOperands(Ops); 1403 1404 std::vector<EVT> VTs; 1405 VTs.push_back(MVT::Other); 1406 VTs.push_back(MVT::Flag); 1407 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1408 VTs, &Ops[0], Ops.size()); 1409 return New.getNode(); 1410} 1411 1412SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1413 return CurDAG->SelectNodeTo(N, TargetInstrInfo::IMPLICIT_DEF, 1414 N->getValueType(0)); 1415} 1416 1417SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1418 SDValue Chain = N->getOperand(0); 1419 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1420 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1421 return CurDAG->SelectNodeTo(N, TargetInstrInfo::EH_LABEL, 1422 MVT::Other, Tmp, Chain); 1423} 1424 1425void SelectionDAGISel::CannotYetSelect(SDNode *N) { 1426 std::string msg; 1427 raw_string_ostream Msg(msg); 1428 Msg << "Cannot yet select: "; 1429 N->print(Msg, CurDAG); 1430 llvm_report_error(Msg.str()); 1431} 1432 1433void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) { 1434 dbgs() << "Cannot yet select: "; 1435 unsigned iid = 1436 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == MVT::Other))->getZExtValue(); 1437 if (iid < Intrinsic::num_intrinsics) 1438 llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid)); 1439 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 1440 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 1441 tii->getName(iid)); 1442} 1443 1444char SelectionDAGISel::ID = 0; 1445