SelectionDAGISel.cpp revision e4454320b3cfffe926a487c33fbeb454366de2f8
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include "llvm/ADT/Statistic.h" 60#include <algorithm> 61using namespace llvm; 62 63STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 64 65static cl::opt<bool> 66EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 67 cl::desc("Enable verbose messages in the \"fast\" " 68 "instruction selector")); 69static cl::opt<bool> 70EnableFastISelAbort("fast-isel-abort", cl::Hidden, 71 cl::desc("Enable abort calls when \"fast\" instruction fails")); 72static cl::opt<bool> 73SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 74 cl::desc("Schedule copies of livein registers"), 75 cl::init(false)); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createFastDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 assert(TLI.getSchedulingPreference() == 150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 151 return createBURRListDAGScheduler(IS, OptLevel); 152 } 153} 154 155// EmitInstrWithCustomInserter - This method should be implemented by targets 156// that mark instructions with the 'usesCustomInserter' flag. These 157// instructions are special in various ways, which require special support to 158// insert. The specified MachineInstr is created but not inserted into any 159// basic blocks, and this method is called to expand it into a sequence of 160// instructions, potentially also creating new basic blocks and control flow. 161// When new basic blocks are inserted and the edges from MBB to its successors 162// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 163// DenseMap. 164MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 165 MachineBasicBlock *MBB, 166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 167#ifndef NDEBUG 168 dbgs() << "If a target marks an instruction with " 169 "'usesCustomInserter', it must implement " 170 "TargetLowering::EmitInstrWithCustomInserter!"; 171#endif 172 llvm_unreachable(0); 173 return 0; 174} 175 176/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 177/// physical register has only a single copy use, then coalesced the copy 178/// if possible. 179static void EmitLiveInCopy(MachineBasicBlock *MBB, 180 MachineBasicBlock::iterator &InsertPos, 181 unsigned VirtReg, unsigned PhysReg, 182 const TargetRegisterClass *RC, 183 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 184 const MachineRegisterInfo &MRI, 185 const TargetRegisterInfo &TRI, 186 const TargetInstrInfo &TII) { 187 unsigned NumUses = 0; 188 MachineInstr *UseMI = NULL; 189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 190 UE = MRI.use_end(); UI != UE; ++UI) { 191 UseMI = &*UI; 192 if (++NumUses > 1) 193 break; 194 } 195 196 // If the number of uses is not one, or the use is not a move instruction, 197 // don't coalesce. Also, only coalesce away a virtual register to virtual 198 // register copy. 199 bool Coalesced = false; 200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 201 if (NumUses == 1 && 202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 203 TargetRegisterInfo::isVirtualRegister(DstReg)) { 204 VirtReg = DstReg; 205 Coalesced = true; 206 } 207 208 // Now find an ideal location to insert the copy. 209 MachineBasicBlock::iterator Pos = InsertPos; 210 while (Pos != MBB->begin()) { 211 MachineInstr *PrevMI = prior(Pos); 212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 213 // copyRegToReg might emit multiple instructions to do a copy. 214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 216 // This is what the BB looks like right now: 217 // r1024 = mov r0 218 // ... 219 // r1 = mov r1024 220 // 221 // We want to insert "r1025 = mov r1". Inserting this copy below the 222 // move to r1024 makes it impossible for that move to be coalesced. 223 // 224 // r1025 = mov r1 225 // r1024 = mov r0 226 // ... 227 // r1 = mov 1024 228 // r2 = mov 1025 229 break; // Woot! Found a good location. 230 --Pos; 231 } 232 233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 234 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 235 (void) Emitted; 236 237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 238 if (Coalesced) { 239 if (&*InsertPos == UseMI) ++InsertPos; 240 MBB->erase(UseMI); 241 } 242} 243 244/// EmitLiveInCopies - If this is the first basic block in the function, 245/// and if it has live ins that need to be copied into vregs, emit the 246/// copies into the block. 247static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 248 const MachineRegisterInfo &MRI, 249 const TargetRegisterInfo &TRI, 250 const TargetInstrInfo &TII) { 251 if (SchedLiveInCopies) { 252 // Emit the copies at a heuristically-determined location in the block. 253 DenseMap<MachineInstr*, unsigned> CopyRegMap; 254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 256 E = MRI.livein_end(); LI != E; ++LI) 257 if (LI->second) { 258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 260 RC, CopyRegMap, MRI, TRI, TII); 261 } 262 } else { 263 // Emit the copies into the top of the block. 264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 265 E = MRI.livein_end(); LI != E; ++LI) 266 if (LI->second) { 267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 269 LI->second, LI->first, RC, RC); 270 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 271 (void) Emitted; 272 } 273 } 274} 275 276//===----------------------------------------------------------------------===// 277// SelectionDAGISel code 278//===----------------------------------------------------------------------===// 279 280SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 282 FuncInfo(new FunctionLoweringInfo(TLI)), 283 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) 288{} 289 290SelectionDAGISel::~SelectionDAGISel() { 291 delete SDB; 292 delete CurDAG; 293 delete FuncInfo; 294} 295 296unsigned SelectionDAGISel::MakeReg(EVT VT) { 297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<DwarfWriter>(); 306 AU.addPreserved<DwarfWriter>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 311 Function &Fn = *mf.getFunction(); 312 313 // Do some sanity-checking on the command-line options. 314 assert((!EnableFastISelVerbose || EnableFastISel) && 315 "-fast-isel-verbose requires -fast-isel"); 316 assert((!EnableFastISelAbort || EnableFastISel) && 317 "-fast-isel-abort requires -fast-isel"); 318 319 // Get alias analysis for load/store combining. 320 AA = &getAnalysis<AliasAnalysis>(); 321 322 MF = &mf; 323 const TargetInstrInfo &TII = *TM.getInstrInfo(); 324 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 325 326 if (Fn.hasGC()) 327 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 328 else 329 GFI = 0; 330 RegInfo = &MF->getRegInfo(); 331 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 332 333 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 334 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 335 CurDAG->init(*MF, MMI, DW); 336 FuncInfo->set(Fn, *MF, EnableFastISel); 337 SDB->init(GFI, *AA); 338 339 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 340 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 341 // Mark landing pad. 342 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 343 344 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 345 346 // If the first basic block in the function has live ins that need to be 347 // copied into vregs, emit the copies into the top of the block before 348 // emitting the code for the block. 349 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 350 351 // Add function live-ins to entry block live-in set. 352 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 353 E = RegInfo->livein_end(); I != E; ++I) 354 MF->begin()->addLiveIn(I->first); 355 356#ifndef NDEBUG 357 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 358 "Not all catch info was assigned to a landing pad!"); 359#endif 360 361 FuncInfo->clear(); 362 363 return true; 364} 365 366/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 367/// attached with this instruction. 368static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 369 SelectionDAGBuilder *SDB, 370 FastISel *FastIS, MachineFunction *MF) { 371 if (isa<DbgInfoIntrinsic>(I)) return; 372 373 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 374 DILocation DILoc(Dbg); 375 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 376 377 SDB->setCurDebugLoc(Loc); 378 379 if (FastIS) 380 FastIS->setCurDebugLoc(Loc); 381 382 // If the function doesn't have a default debug location yet, set 383 // it. This is kind of a hack. 384 if (MF->getDefaultDebugLoc().isUnknown()) 385 MF->setDefaultDebugLoc(Loc); 386 } 387} 388 389/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 390static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 391 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 392 if (FastIS) 393 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 394} 395 396void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 397 BasicBlock::iterator Begin, 398 BasicBlock::iterator End, 399 bool &HadTailCall) { 400 SDB->setCurrentBasicBlock(BB); 401 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 402 403 // Lower all of the non-terminator instructions. If a call is emitted 404 // as a tail call, cease emitting nodes for this block. 405 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 406 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 407 408 if (!isa<TerminatorInst>(I)) { 409 SDB->visit(*I); 410 411 // Set the current debug location back to "unknown" so that it doesn't 412 // spuriously apply to subsequent instructions. 413 ResetDebugLoc(SDB, 0); 414 } 415 } 416 417 if (!SDB->HasTailCall) { 418 // Ensure that all instructions which are used outside of their defining 419 // blocks are available as virtual registers. Invoke is handled elsewhere. 420 for (BasicBlock::iterator I = Begin; I != End; ++I) 421 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 422 SDB->CopyToExportRegsIfNeeded(I); 423 424 // Handle PHI nodes in successor blocks. 425 if (End == LLVMBB->end()) { 426 HandlePHINodesInSuccessorBlocks(LLVMBB); 427 428 // Lower the terminator after the copies are emitted. 429 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 430 SDB->visit(*LLVMBB->getTerminator()); 431 ResetDebugLoc(SDB, 0); 432 } 433 } 434 435 // Make sure the root of the DAG is up-to-date. 436 CurDAG->setRoot(SDB->getControlRoot()); 437 438 // Final step, emit the lowered DAG as machine code. 439 CodeGenAndEmitDAG(); 440 HadTailCall = SDB->HasTailCall; 441 SDB->clear(); 442} 443 444namespace { 445/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 446/// nodes from the worklist. 447class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 448 SmallVector<SDNode*, 128> &Worklist; 449public: 450 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {} 451 452 virtual void NodeDeleted(SDNode *N, SDNode *E) { 453 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 454 Worklist.end()); 455 } 456 457 virtual void NodeUpdated(SDNode *N) { 458 // Ignore updates. 459 } 460}; 461} 462 463/// TrivialTruncElim - Eliminate some trivial nops that can result from 464/// ShrinkDemandedOps: (trunc (ext n)) -> n. 465static bool TrivialTruncElim(SDValue Op, 466 TargetLowering::TargetLoweringOpt &TLO) { 467 SDValue N0 = Op.getOperand(0); 468 EVT VT = Op.getValueType(); 469 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 470 N0.getOpcode() == ISD::SIGN_EXTEND || 471 N0.getOpcode() == ISD::ANY_EXTEND) && 472 N0.getOperand(0).getValueType() == VT) { 473 return TLO.CombineTo(Op, N0.getOperand(0)); 474 } 475 return false; 476} 477 478/// ShrinkDemandedOps - A late transformation pass that shrink expressions 479/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 480/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 481void SelectionDAGISel::ShrinkDemandedOps() { 482 SmallVector<SDNode*, 128> Worklist; 483 484 // Add all the dag nodes to the worklist. 485 Worklist.reserve(CurDAG->allnodes_size()); 486 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 487 E = CurDAG->allnodes_end(); I != E; ++I) 488 Worklist.push_back(I); 489 490 APInt Mask; 491 APInt KnownZero; 492 APInt KnownOne; 493 494 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 495 while (!Worklist.empty()) { 496 SDNode *N = Worklist.pop_back_val(); 497 498 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 499 CurDAG->DeleteNode(N); 500 continue; 501 } 502 503 // Run ShrinkDemandedOp on scalar binary operations. 504 if (N->getNumValues() == 1 && 505 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) { 506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 507 APInt Demanded = APInt::getAllOnesValue(BitWidth); 508 APInt KnownZero, KnownOne; 509 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 510 KnownZero, KnownOne, TLO) || 511 (N->getOpcode() == ISD::TRUNCATE && 512 TrivialTruncElim(SDValue(N, 0), TLO))) { 513 // Revisit the node. 514 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 515 Worklist.end()); 516 Worklist.push_back(N); 517 518 // Replace the old value with the new one. 519 DEBUG(errs() << "\nReplacing "; 520 TLO.Old.getNode()->dump(CurDAG); 521 errs() << "\nWith: "; 522 TLO.New.getNode()->dump(CurDAG); 523 errs() << '\n'); 524 525 Worklist.push_back(TLO.New.getNode()); 526 527 SDOPsWorkListRemover DeadNodes(Worklist); 528 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 529 530 if (TLO.Old.getNode()->use_empty()) { 531 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 532 i != e; ++i) { 533 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 534 if (OpNode->hasOneUse()) { 535 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 536 OpNode), Worklist.end()); 537 Worklist.push_back(OpNode); 538 } 539 } 540 541 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 542 TLO.Old.getNode()), Worklist.end()); 543 CurDAG->DeleteNode(TLO.Old.getNode()); 544 } 545 } 546 } 547 } 548} 549 550void SelectionDAGISel::ComputeLiveOutVRegInfo() { 551 SmallPtrSet<SDNode*, 128> VisitedNodes; 552 SmallVector<SDNode*, 128> Worklist; 553 554 Worklist.push_back(CurDAG->getRoot().getNode()); 555 556 APInt Mask; 557 APInt KnownZero; 558 APInt KnownOne; 559 560 do { 561 SDNode *N = Worklist.pop_back_val(); 562 563 // If we've already seen this node, ignore it. 564 if (!VisitedNodes.insert(N)) 565 continue; 566 567 // Otherwise, add all chain operands to the worklist. 568 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 569 if (N->getOperand(i).getValueType() == MVT::Other) 570 Worklist.push_back(N->getOperand(i).getNode()); 571 572 // If this is a CopyToReg with a vreg dest, process it. 573 if (N->getOpcode() != ISD::CopyToReg) 574 continue; 575 576 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 577 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 578 continue; 579 580 // Ignore non-scalar or non-integer values. 581 SDValue Src = N->getOperand(2); 582 EVT SrcVT = Src.getValueType(); 583 if (!SrcVT.isInteger() || SrcVT.isVector()) 584 continue; 585 586 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 587 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 588 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 589 590 // Only install this information if it tells us something. 591 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 592 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 593 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 594 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 595 FunctionLoweringInfo::LiveOutInfo &LOI = 596 FuncInfo->LiveOutRegInfo[DestReg]; 597 LOI.NumSignBits = NumSignBits; 598 LOI.KnownOne = KnownOne; 599 LOI.KnownZero = KnownZero; 600 } 601 } while (!Worklist.empty()); 602} 603 604void SelectionDAGISel::CodeGenAndEmitDAG() { 605 std::string GroupName; 606 if (TimePassesIsEnabled) 607 GroupName = "Instruction Selection and Scheduling"; 608 std::string BlockName; 609 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 610 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 611 ViewSUnitDAGs) 612 BlockName = MF->getFunction()->getNameStr() + ":" + 613 BB->getBasicBlock()->getNameStr(); 614 615 DEBUG(dbgs() << "Initial selection DAG:\n"); 616 DEBUG(CurDAG->dump()); 617 618 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 619 620 // Run the DAG combiner in pre-legalize mode. 621 if (TimePassesIsEnabled) { 622 NamedRegionTimer T("DAG Combining 1", GroupName); 623 CurDAG->Combine(Unrestricted, *AA, OptLevel); 624 } else { 625 CurDAG->Combine(Unrestricted, *AA, OptLevel); 626 } 627 628 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 629 DEBUG(CurDAG->dump()); 630 631 // Second step, hack on the DAG until it only uses operations and types that 632 // the target supports. 633 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 634 BlockName); 635 636 bool Changed; 637 if (TimePassesIsEnabled) { 638 NamedRegionTimer T("Type Legalization", GroupName); 639 Changed = CurDAG->LegalizeTypes(); 640 } else { 641 Changed = CurDAG->LegalizeTypes(); 642 } 643 644 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 645 DEBUG(CurDAG->dump()); 646 647 if (Changed) { 648 if (ViewDAGCombineLT) 649 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 650 651 // Run the DAG combiner in post-type-legalize mode. 652 if (TimePassesIsEnabled) { 653 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 654 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 655 } else { 656 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 657 } 658 659 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 660 DEBUG(CurDAG->dump()); 661 } 662 663 if (TimePassesIsEnabled) { 664 NamedRegionTimer T("Vector Legalization", GroupName); 665 Changed = CurDAG->LegalizeVectors(); 666 } else { 667 Changed = CurDAG->LegalizeVectors(); 668 } 669 670 if (Changed) { 671 if (TimePassesIsEnabled) { 672 NamedRegionTimer T("Type Legalization 2", GroupName); 673 CurDAG->LegalizeTypes(); 674 } else { 675 CurDAG->LegalizeTypes(); 676 } 677 678 if (ViewDAGCombineLT) 679 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 680 681 // Run the DAG combiner in post-type-legalize mode. 682 if (TimePassesIsEnabled) { 683 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 684 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 685 } else { 686 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 687 } 688 689 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 690 DEBUG(CurDAG->dump()); 691 } 692 693 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 694 695 if (TimePassesIsEnabled) { 696 NamedRegionTimer T("DAG Legalization", GroupName); 697 CurDAG->Legalize(OptLevel); 698 } else { 699 CurDAG->Legalize(OptLevel); 700 } 701 702 DEBUG(dbgs() << "Legalized selection DAG:\n"); 703 DEBUG(CurDAG->dump()); 704 705 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 706 707 // Run the DAG combiner in post-legalize mode. 708 if (TimePassesIsEnabled) { 709 NamedRegionTimer T("DAG Combining 2", GroupName); 710 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 711 } else { 712 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 713 } 714 715 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 716 DEBUG(CurDAG->dump()); 717 718 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 719 720 if (OptLevel != CodeGenOpt::None) { 721 ShrinkDemandedOps(); 722 ComputeLiveOutVRegInfo(); 723 } 724 725 // Third, instruction select all of the operations to machine code, adding the 726 // code to the MachineBasicBlock. 727 if (TimePassesIsEnabled) { 728 NamedRegionTimer T("Instruction Selection", GroupName); 729 DoInstructionSelection(); 730 } else { 731 DoInstructionSelection(); 732 } 733 734 DEBUG(dbgs() << "Selected selection DAG:\n"); 735 DEBUG(CurDAG->dump()); 736 737 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 738 739 // Schedule machine code. 740 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 741 if (TimePassesIsEnabled) { 742 NamedRegionTimer T("Instruction Scheduling", GroupName); 743 Scheduler->Run(CurDAG, BB, BB->end()); 744 } else { 745 Scheduler->Run(CurDAG, BB, BB->end()); 746 } 747 748 if (ViewSUnitDAGs) Scheduler->viewGraph(); 749 750 // Emit machine code to BB. This can change 'BB' to the last block being 751 // inserted into. 752 if (TimePassesIsEnabled) { 753 NamedRegionTimer T("Instruction Creation", GroupName); 754 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 755 } else { 756 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 757 } 758 759 // Free the scheduler state. 760 if (TimePassesIsEnabled) { 761 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 762 delete Scheduler; 763 } else { 764 delete Scheduler; 765 } 766 767 DEBUG(dbgs() << "Selected machine code:\n"); 768 DEBUG(BB->dump()); 769} 770 771void SelectionDAGISel::DoInstructionSelection() { 772 DEBUG(errs() << "===== Instruction selection begins:\n"); 773 774 PreprocessISelDAG(); 775 776 // Select target instructions for the DAG. 777 { 778 // Number all nodes with a topological order and set DAGSize. 779 DAGSize = CurDAG->AssignTopologicalOrder(); 780 781 // Create a dummy node (which is not added to allnodes), that adds 782 // a reference to the root node, preventing it from being deleted, 783 // and tracking any changes of the root. 784 HandleSDNode Dummy(CurDAG->getRoot()); 785 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 786 ++ISelPosition; 787 788 // The AllNodes list is now topological-sorted. Visit the 789 // nodes by starting at the end of the list (the root of the 790 // graph) and preceding back toward the beginning (the entry 791 // node). 792 while (ISelPosition != CurDAG->allnodes_begin()) { 793 SDNode *Node = --ISelPosition; 794 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 795 // but there are currently some corner cases that it misses. Also, this 796 // makes it theoretically possible to disable the DAGCombiner. 797 if (Node->use_empty()) 798 continue; 799 800 SDNode *ResNode = Select(Node); 801 802 // FIXME: This is pretty gross. 'Select' should be changed to not return 803 // anything at all and this code should be nuked with a tactical strike. 804 805 // If node should not be replaced, continue with the next one. 806 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 807 continue; 808 // Replace node. 809 if (ResNode) 810 ReplaceUses(Node, ResNode); 811 812 // If after the replacement this node is not used any more, 813 // remove this dead node. 814 if (Node->use_empty()) { // Don't delete EntryToken, etc. 815 ISelUpdater ISU(ISelPosition); 816 CurDAG->RemoveDeadNode(Node, &ISU); 817 } 818 } 819 820 CurDAG->setRoot(Dummy.getValue()); 821 } 822 DEBUG(errs() << "===== Instruction selection ends:\n"); 823 824 PostprocessISelDAG(); 825 826 // FIXME: This shouldn't be needed, remove it. 827 CurDAG->RemoveDeadNodes(); 828} 829 830 831void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 832 MachineFunction &MF, 833 MachineModuleInfo *MMI, 834 DwarfWriter *DW, 835 const TargetInstrInfo &TII) { 836 // Initialize the Fast-ISel state, if needed. 837 FastISel *FastIS = 0; 838 if (EnableFastISel) 839 FastIS = TLI.createFastISel(MF, MMI, DW, 840 FuncInfo->ValueMap, 841 FuncInfo->MBBMap, 842 FuncInfo->StaticAllocaMap 843#ifndef NDEBUG 844 , FuncInfo->CatchInfoLost 845#endif 846 ); 847 848 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 849 850 // Iterate over all basic blocks in the function. 851 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 852 BasicBlock *LLVMBB = &*I; 853 BB = FuncInfo->MBBMap[LLVMBB]; 854 855 BasicBlock::iterator const Begin = LLVMBB->begin(); 856 BasicBlock::iterator const End = LLVMBB->end(); 857 BasicBlock::iterator BI = Begin; 858 859 // Lower any arguments needed in this block if this is the entry block. 860 bool SuppressFastISel = false; 861 if (LLVMBB == &Fn.getEntryBlock()) { 862 LowerArguments(LLVMBB); 863 864 // If any of the arguments has the byval attribute, forgo 865 // fast-isel in the entry block. 866 if (FastIS) { 867 unsigned j = 1; 868 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 869 I != E; ++I, ++j) 870 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 871 if (EnableFastISelVerbose || EnableFastISelAbort) 872 dbgs() << "FastISel skips entry block due to byval argument\n"; 873 SuppressFastISel = true; 874 break; 875 } 876 } 877 } 878 879 if (MMI && BB->isLandingPad()) { 880 // Add a label to mark the beginning of the landing pad. Deletion of the 881 // landing pad can thus be detected via the MachineModuleInfo. 882 unsigned LabelID = MMI->addLandingPad(BB); 883 884 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 885 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 886 887 // Mark exception register as live in. 888 unsigned Reg = TLI.getExceptionAddressRegister(); 889 if (Reg) BB->addLiveIn(Reg); 890 891 // Mark exception selector register as live in. 892 Reg = TLI.getExceptionSelectorRegister(); 893 if (Reg) BB->addLiveIn(Reg); 894 895 // FIXME: Hack around an exception handling flaw (PR1508): the personality 896 // function and list of typeids logically belong to the invoke (or, if you 897 // like, the basic block containing the invoke), and need to be associated 898 // with it in the dwarf exception handling tables. Currently however the 899 // information is provided by an intrinsic (eh.selector) that can be moved 900 // to unexpected places by the optimizers: if the unwind edge is critical, 901 // then breaking it can result in the intrinsics being in the successor of 902 // the landing pad, not the landing pad itself. This results 903 // in exceptions not being caught because no typeids are associated with 904 // the invoke. This may not be the only way things can go wrong, but it 905 // is the only way we try to work around for the moment. 906 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 907 908 if (Br && Br->isUnconditional()) { // Critical edge? 909 BasicBlock::iterator I, E; 910 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 911 if (isa<EHSelectorInst>(I)) 912 break; 913 914 if (I == E) 915 // No catch info found - try to extract some from the successor. 916 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 917 } 918 } 919 920 // Before doing SelectionDAG ISel, see if FastISel has been requested. 921 if (FastIS && !SuppressFastISel) { 922 // Emit code for any incoming arguments. This must happen before 923 // beginning FastISel on the entry block. 924 if (LLVMBB == &Fn.getEntryBlock()) { 925 CurDAG->setRoot(SDB->getControlRoot()); 926 CodeGenAndEmitDAG(); 927 SDB->clear(); 928 } 929 FastIS->startNewBlock(BB); 930 // Do FastISel on as many instructions as possible. 931 for (; BI != End; ++BI) { 932 // Just before the terminator instruction, insert instructions to 933 // feed PHI nodes in successor blocks. 934 if (isa<TerminatorInst>(BI)) 935 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 936 ++NumFastIselFailures; 937 ResetDebugLoc(SDB, FastIS); 938 if (EnableFastISelVerbose || EnableFastISelAbort) { 939 dbgs() << "FastISel miss: "; 940 BI->dump(); 941 } 942 assert(!EnableFastISelAbort && 943 "FastISel didn't handle a PHI in a successor"); 944 break; 945 } 946 947 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 948 949 // Try to select the instruction with FastISel. 950 if (FastIS->SelectInstruction(BI)) { 951 ResetDebugLoc(SDB, FastIS); 952 continue; 953 } 954 955 // Clear out the debug location so that it doesn't carry over to 956 // unrelated instructions. 957 ResetDebugLoc(SDB, FastIS); 958 959 // Then handle certain instructions as single-LLVM-Instruction blocks. 960 if (isa<CallInst>(BI)) { 961 ++NumFastIselFailures; 962 if (EnableFastISelVerbose || EnableFastISelAbort) { 963 dbgs() << "FastISel missed call: "; 964 BI->dump(); 965 } 966 967 if (!BI->getType()->isVoidTy()) { 968 unsigned &R = FuncInfo->ValueMap[BI]; 969 if (!R) 970 R = FuncInfo->CreateRegForValue(BI); 971 } 972 973 bool HadTailCall = false; 974 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 975 976 // If the call was emitted as a tail call, we're done with the block. 977 if (HadTailCall) { 978 BI = End; 979 break; 980 } 981 982 // If the instruction was codegen'd with multiple blocks, 983 // inform the FastISel object where to resume inserting. 984 FastIS->setCurrentBlock(BB); 985 continue; 986 } 987 988 // Otherwise, give up on FastISel for the rest of the block. 989 // For now, be a little lenient about non-branch terminators. 990 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 991 ++NumFastIselFailures; 992 if (EnableFastISelVerbose || EnableFastISelAbort) { 993 dbgs() << "FastISel miss: "; 994 BI->dump(); 995 } 996 if (EnableFastISelAbort) 997 // The "fast" selector couldn't handle something and bailed. 998 // For the purpose of debugging, just abort. 999 llvm_unreachable("FastISel didn't select the entire block"); 1000 } 1001 break; 1002 } 1003 } 1004 1005 // Run SelectionDAG instruction selection on the remainder of the block 1006 // not handled by FastISel. If FastISel is not run, this is the entire 1007 // block. 1008 if (BI != End) { 1009 bool HadTailCall; 1010 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1011 } 1012 1013 FinishBasicBlock(); 1014 } 1015 1016 delete FastIS; 1017} 1018 1019void 1020SelectionDAGISel::FinishBasicBlock() { 1021 1022 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1023 DEBUG(BB->dump()); 1024 1025 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1026 << SDB->PHINodesToUpdate.size() << "\n"); 1027 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1028 dbgs() << "Node " << i << " : (" 1029 << SDB->PHINodesToUpdate[i].first 1030 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1031 1032 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1033 // PHI nodes in successors. 1034 if (SDB->SwitchCases.empty() && 1035 SDB->JTCases.empty() && 1036 SDB->BitTestCases.empty()) { 1037 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1038 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1039 assert(PHI->isPHI() && 1040 "This is not a machine PHI node that we are updating!"); 1041 if (!BB->isSuccessor(PHI->getParent())) 1042 continue; 1043 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1044 false)); 1045 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1046 } 1047 SDB->PHINodesToUpdate.clear(); 1048 return; 1049 } 1050 1051 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1052 // Lower header first, if it wasn't already lowered 1053 if (!SDB->BitTestCases[i].Emitted) { 1054 // Set the current basic block to the mbb we wish to insert the code into 1055 BB = SDB->BitTestCases[i].Parent; 1056 SDB->setCurrentBasicBlock(BB); 1057 // Emit the code 1058 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1059 CurDAG->setRoot(SDB->getRoot()); 1060 CodeGenAndEmitDAG(); 1061 SDB->clear(); 1062 } 1063 1064 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1065 // Set the current basic block to the mbb we wish to insert the code into 1066 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1067 SDB->setCurrentBasicBlock(BB); 1068 // Emit the code 1069 if (j+1 != ej) 1070 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1071 SDB->BitTestCases[i].Reg, 1072 SDB->BitTestCases[i].Cases[j]); 1073 else 1074 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1075 SDB->BitTestCases[i].Reg, 1076 SDB->BitTestCases[i].Cases[j]); 1077 1078 1079 CurDAG->setRoot(SDB->getRoot()); 1080 CodeGenAndEmitDAG(); 1081 SDB->clear(); 1082 } 1083 1084 // Update PHI Nodes 1085 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1086 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1087 MachineBasicBlock *PHIBB = PHI->getParent(); 1088 assert(PHI->isPHI() && 1089 "This is not a machine PHI node that we are updating!"); 1090 // This is "default" BB. We have two jumps to it. From "header" BB and 1091 // from last "case" BB. 1092 if (PHIBB == SDB->BitTestCases[i].Default) { 1093 PHI->addOperand(MachineOperand:: 1094 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1095 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1096 PHI->addOperand(MachineOperand:: 1097 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1098 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1099 back().ThisBB)); 1100 } 1101 // One of "cases" BB. 1102 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1103 j != ej; ++j) { 1104 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1105 if (cBB->isSuccessor(PHIBB)) { 1106 PHI->addOperand(MachineOperand:: 1107 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1108 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1109 } 1110 } 1111 } 1112 } 1113 SDB->BitTestCases.clear(); 1114 1115 // If the JumpTable record is filled in, then we need to emit a jump table. 1116 // Updating the PHI nodes is tricky in this case, since we need to determine 1117 // whether the PHI is a successor of the range check MBB or the jump table MBB 1118 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1119 // Lower header first, if it wasn't already lowered 1120 if (!SDB->JTCases[i].first.Emitted) { 1121 // Set the current basic block to the mbb we wish to insert the code into 1122 BB = SDB->JTCases[i].first.HeaderBB; 1123 SDB->setCurrentBasicBlock(BB); 1124 // Emit the code 1125 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1126 CurDAG->setRoot(SDB->getRoot()); 1127 CodeGenAndEmitDAG(); 1128 SDB->clear(); 1129 } 1130 1131 // Set the current basic block to the mbb we wish to insert the code into 1132 BB = SDB->JTCases[i].second.MBB; 1133 SDB->setCurrentBasicBlock(BB); 1134 // Emit the code 1135 SDB->visitJumpTable(SDB->JTCases[i].second); 1136 CurDAG->setRoot(SDB->getRoot()); 1137 CodeGenAndEmitDAG(); 1138 SDB->clear(); 1139 1140 // Update PHI Nodes 1141 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1142 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1143 MachineBasicBlock *PHIBB = PHI->getParent(); 1144 assert(PHI->isPHI() && 1145 "This is not a machine PHI node that we are updating!"); 1146 // "default" BB. We can go there only from header BB. 1147 if (PHIBB == SDB->JTCases[i].second.Default) { 1148 PHI->addOperand 1149 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1150 PHI->addOperand 1151 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1152 } 1153 // JT BB. Just iterate over successors here 1154 if (BB->isSuccessor(PHIBB)) { 1155 PHI->addOperand 1156 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1157 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1158 } 1159 } 1160 } 1161 SDB->JTCases.clear(); 1162 1163 // If the switch block involved a branch to one of the actual successors, we 1164 // need to update PHI nodes in that block. 1165 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1166 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1167 assert(PHI->isPHI() && 1168 "This is not a machine PHI node that we are updating!"); 1169 if (BB->isSuccessor(PHI->getParent())) { 1170 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1171 false)); 1172 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1173 } 1174 } 1175 1176 // If we generated any switch lowering information, build and codegen any 1177 // additional DAGs necessary. 1178 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1179 // Set the current basic block to the mbb we wish to insert the code into 1180 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1181 SDB->setCurrentBasicBlock(BB); 1182 1183 // Emit the code 1184 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1185 CurDAG->setRoot(SDB->getRoot()); 1186 CodeGenAndEmitDAG(); 1187 1188 // Handle any PHI nodes in successors of this chunk, as if we were coming 1189 // from the original BB before switch expansion. Note that PHI nodes can 1190 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1191 // handle them the right number of times. 1192 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1193 // If new BB's are created during scheduling, the edges may have been 1194 // updated. That is, the edge from ThisBB to BB may have been split and 1195 // BB's predecessor is now another block. 1196 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1197 SDB->EdgeMapping.find(BB); 1198 if (EI != SDB->EdgeMapping.end()) 1199 ThisBB = EI->second; 1200 1201 // BB may have been removed from the CFG if a branch was constant folded. 1202 if (ThisBB->isSuccessor(BB)) { 1203 for (MachineBasicBlock::iterator Phi = BB->begin(); 1204 Phi != BB->end() && Phi->isPHI(); 1205 ++Phi) { 1206 // This value for this PHI node is recorded in PHINodesToUpdate. 1207 for (unsigned pn = 0; ; ++pn) { 1208 assert(pn != SDB->PHINodesToUpdate.size() && 1209 "Didn't find PHI entry!"); 1210 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1211 Phi->addOperand(MachineOperand:: 1212 CreateReg(SDB->PHINodesToUpdate[pn].second, 1213 false)); 1214 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1215 break; 1216 } 1217 } 1218 } 1219 } 1220 1221 // Don't process RHS if same block as LHS. 1222 if (BB == SDB->SwitchCases[i].FalseBB) 1223 SDB->SwitchCases[i].FalseBB = 0; 1224 1225 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1226 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1227 SDB->SwitchCases[i].FalseBB = 0; 1228 } 1229 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1230 SDB->clear(); 1231 } 1232 SDB->SwitchCases.clear(); 1233 1234 SDB->PHINodesToUpdate.clear(); 1235} 1236 1237 1238/// Create the scheduler. If a specific scheduler was specified 1239/// via the SchedulerRegistry, use it, otherwise select the 1240/// one preferred by the target. 1241/// 1242ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1243 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1244 1245 if (!Ctor) { 1246 Ctor = ISHeuristic; 1247 RegisterScheduler::setDefault(Ctor); 1248 } 1249 1250 return Ctor(this, OptLevel); 1251} 1252 1253ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1254 return new ScheduleHazardRecognizer(); 1255} 1256 1257//===----------------------------------------------------------------------===// 1258// Helper functions used by the generated instruction selector. 1259//===----------------------------------------------------------------------===// 1260// Calls to these methods are generated by tblgen. 1261 1262/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1263/// the dag combiner simplified the 255, we still want to match. RHS is the 1264/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1265/// specified in the .td file (e.g. 255). 1266bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1267 int64_t DesiredMaskS) const { 1268 const APInt &ActualMask = RHS->getAPIntValue(); 1269 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1270 1271 // If the actual mask exactly matches, success! 1272 if (ActualMask == DesiredMask) 1273 return true; 1274 1275 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1276 if (ActualMask.intersects(~DesiredMask)) 1277 return false; 1278 1279 // Otherwise, the DAG Combiner may have proven that the value coming in is 1280 // either already zero or is not demanded. Check for known zero input bits. 1281 APInt NeededMask = DesiredMask & ~ActualMask; 1282 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1283 return true; 1284 1285 // TODO: check to see if missing bits are just not demanded. 1286 1287 // Otherwise, this pattern doesn't match. 1288 return false; 1289} 1290 1291/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1292/// the dag combiner simplified the 255, we still want to match. RHS is the 1293/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1294/// specified in the .td file (e.g. 255). 1295bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1296 int64_t DesiredMaskS) const { 1297 const APInt &ActualMask = RHS->getAPIntValue(); 1298 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1299 1300 // If the actual mask exactly matches, success! 1301 if (ActualMask == DesiredMask) 1302 return true; 1303 1304 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1305 if (ActualMask.intersects(~DesiredMask)) 1306 return false; 1307 1308 // Otherwise, the DAG Combiner may have proven that the value coming in is 1309 // either already zero or is not demanded. Check for known zero input bits. 1310 APInt NeededMask = DesiredMask & ~ActualMask; 1311 1312 APInt KnownZero, KnownOne; 1313 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1314 1315 // If all the missing bits in the or are already known to be set, match! 1316 if ((NeededMask & KnownOne) == NeededMask) 1317 return true; 1318 1319 // TODO: check to see if missing bits are just not demanded. 1320 1321 // Otherwise, this pattern doesn't match. 1322 return false; 1323} 1324 1325 1326/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1327/// by tblgen. Others should not call it. 1328void SelectionDAGISel:: 1329SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1330 std::vector<SDValue> InOps; 1331 std::swap(InOps, Ops); 1332 1333 Ops.push_back(InOps[0]); // input chain. 1334 Ops.push_back(InOps[1]); // input asm string. 1335 1336 unsigned i = 2, e = InOps.size(); 1337 if (InOps[e-1].getValueType() == MVT::Flag) 1338 --e; // Don't process a flag operand if it is here. 1339 1340 while (i != e) { 1341 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1342 if ((Flags & 7) != 4 /*MEM*/) { 1343 // Just skip over this operand, copying the operands verbatim. 1344 Ops.insert(Ops.end(), InOps.begin()+i, 1345 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1346 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1347 } else { 1348 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1349 "Memory operand with multiple values?"); 1350 // Otherwise, this is a memory operand. Ask the target to select it. 1351 std::vector<SDValue> SelOps; 1352 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1353 llvm_report_error("Could not match memory address. Inline asm" 1354 " failure!"); 1355 } 1356 1357 // Add this to the output node. 1358 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1359 MVT::i32)); 1360 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1361 i += 2; 1362 } 1363 } 1364 1365 // Add the flag input back if present. 1366 if (e != InOps.size()) 1367 Ops.push_back(InOps.back()); 1368} 1369 1370/// findFlagUse - Return use of EVT::Flag value produced by the specified 1371/// SDNode. 1372/// 1373static SDNode *findFlagUse(SDNode *N) { 1374 unsigned FlagResNo = N->getNumValues()-1; 1375 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1376 SDUse &Use = I.getUse(); 1377 if (Use.getResNo() == FlagResNo) 1378 return Use.getUser(); 1379 } 1380 return NULL; 1381} 1382 1383/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1384/// This function recursively traverses up the operand chain, ignoring 1385/// certain nodes. 1386static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1387 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1388 bool IgnoreChains) { 1389 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1390 // greater than all of its (recursive) operands. If we scan to a point where 1391 // 'use' is smaller than the node we're scanning for, then we know we will 1392 // never find it. 1393 // 1394 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1395 // happen because we scan down to newly selected nodes in the case of flag 1396 // uses. 1397 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1398 return false; 1399 1400 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1401 // won't fail if we scan it again. 1402 if (!Visited.insert(Use)) 1403 return false; 1404 1405 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1406 // Ignore chain uses, they are validated by HandleMergeInputChains. 1407 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1408 continue; 1409 1410 SDNode *N = Use->getOperand(i).getNode(); 1411 if (N == Def) { 1412 if (Use == ImmedUse || Use == Root) 1413 continue; // We are not looking for immediate use. 1414 assert(N != Root); 1415 return true; 1416 } 1417 1418 // Traverse up the operand chain. 1419 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1420 return true; 1421 } 1422 return false; 1423} 1424 1425/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1426/// operand node N of U during instruction selection that starts at Root. 1427bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1428 SDNode *Root) const { 1429 if (OptLevel == CodeGenOpt::None) return false; 1430 return N.hasOneUse(); 1431} 1432 1433/// IsLegalToFold - Returns true if the specific operand node N of 1434/// U can be folded during instruction selection that starts at Root. 1435bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1436 bool IgnoreChains) const { 1437 if (OptLevel == CodeGenOpt::None) return false; 1438 1439 // If Root use can somehow reach N through a path that that doesn't contain 1440 // U then folding N would create a cycle. e.g. In the following 1441 // diagram, Root can reach N through X. If N is folded into into Root, then 1442 // X is both a predecessor and a successor of U. 1443 // 1444 // [N*] // 1445 // ^ ^ // 1446 // / \ // 1447 // [U*] [X]? // 1448 // ^ ^ // 1449 // \ / // 1450 // \ / // 1451 // [Root*] // 1452 // 1453 // * indicates nodes to be folded together. 1454 // 1455 // If Root produces a flag, then it gets (even more) interesting. Since it 1456 // will be "glued" together with its flag use in the scheduler, we need to 1457 // check if it might reach N. 1458 // 1459 // [N*] // 1460 // ^ ^ // 1461 // / \ // 1462 // [U*] [X]? // 1463 // ^ ^ // 1464 // \ \ // 1465 // \ | // 1466 // [Root*] | // 1467 // ^ | // 1468 // f | // 1469 // | / // 1470 // [Y] / // 1471 // ^ / // 1472 // f / // 1473 // | / // 1474 // [FU] // 1475 // 1476 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1477 // (call it Fold), then X is a predecessor of FU and a successor of 1478 // Fold. But since Fold and FU are flagged together, this will create 1479 // a cycle in the scheduling graph. 1480 1481 // If the node has flags, walk down the graph to the "lowest" node in the 1482 // flagged set. 1483 EVT VT = Root->getValueType(Root->getNumValues()-1); 1484 while (VT == MVT::Flag) { 1485 SDNode *FU = findFlagUse(Root); 1486 if (FU == NULL) 1487 break; 1488 Root = FU; 1489 VT = Root->getValueType(Root->getNumValues()-1); 1490 1491 // If our query node has a flag result with a use, we've walked up it. If 1492 // the user (which has already been selected) has a chain or indirectly uses 1493 // the chain, our WalkChainUsers predicate will not consider it. Because of 1494 // this, we cannot ignore chains in this predicate. 1495 IgnoreChains = false; 1496 } 1497 1498 1499 SmallPtrSet<SDNode*, 16> Visited; 1500 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1501} 1502 1503SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1504 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1505 SelectInlineAsmMemoryOperands(Ops); 1506 1507 std::vector<EVT> VTs; 1508 VTs.push_back(MVT::Other); 1509 VTs.push_back(MVT::Flag); 1510 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1511 VTs, &Ops[0], Ops.size()); 1512 New->setNodeId(-1); 1513 return New.getNode(); 1514} 1515 1516SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1517 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1518} 1519 1520SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1521 SDValue Chain = N->getOperand(0); 1522 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1523 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1524 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL, 1525 MVT::Other, Tmp, Chain); 1526} 1527 1528/// GetVBR - decode a vbr encoding whose top bit is set. 1529ALWAYS_INLINE static uint64_t 1530GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1531 assert(Val >= 128 && "Not a VBR"); 1532 Val &= 127; // Remove first vbr bit. 1533 1534 unsigned Shift = 7; 1535 uint64_t NextBits; 1536 do { 1537 NextBits = MatcherTable[Idx++]; 1538 Val |= (NextBits&127) << Shift; 1539 Shift += 7; 1540 } while (NextBits & 128); 1541 1542 return Val; 1543} 1544 1545 1546/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1547/// interior flag and chain results to use the new flag and chain results. 1548void SelectionDAGISel:: 1549UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1550 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1551 SDValue InputFlag, 1552 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1553 bool isMorphNodeTo) { 1554 SmallVector<SDNode*, 4> NowDeadNodes; 1555 1556 ISelUpdater ISU(ISelPosition); 1557 1558 // Now that all the normal results are replaced, we replace the chain and 1559 // flag results if present. 1560 if (!ChainNodesMatched.empty()) { 1561 assert(InputChain.getNode() != 0 && 1562 "Matched input chains but didn't produce a chain"); 1563 // Loop over all of the nodes we matched that produced a chain result. 1564 // Replace all the chain results with the final chain we ended up with. 1565 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1566 SDNode *ChainNode = ChainNodesMatched[i]; 1567 1568 // If this node was already deleted, don't look at it. 1569 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1570 continue; 1571 1572 // Don't replace the results of the root node if we're doing a 1573 // MorphNodeTo. 1574 if (ChainNode == NodeToMatch && isMorphNodeTo) 1575 continue; 1576 1577 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1578 if (ChainVal.getValueType() == MVT::Flag) 1579 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1580 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1581 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1582 1583 // If the node became dead, delete it. 1584 if (ChainNode->use_empty()) 1585 NowDeadNodes.push_back(ChainNode); 1586 } 1587 } 1588 1589 // If the result produces a flag, update any flag results in the matched 1590 // pattern with the flag result. 1591 if (InputFlag.getNode() != 0) { 1592 // Handle any interior nodes explicitly marked. 1593 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1594 SDNode *FRN = FlagResultNodesMatched[i]; 1595 1596 // If this node was already deleted, don't look at it. 1597 if (FRN->getOpcode() == ISD::DELETED_NODE) 1598 continue; 1599 1600 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1601 "Doesn't have a flag result"); 1602 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1603 InputFlag, &ISU); 1604 1605 // If the node became dead, delete it. 1606 if (FRN->use_empty()) 1607 NowDeadNodes.push_back(FRN); 1608 } 1609 } 1610 1611 if (!NowDeadNodes.empty()) 1612 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1613 1614 DEBUG(errs() << "ISEL: Match complete!\n"); 1615} 1616 1617enum ChainResult { 1618 CR_Simple, 1619 CR_InducesCycle, 1620 CR_LeadsToInteriorNode 1621}; 1622 1623/// WalkChainUsers - Walk down the users of the specified chained node that is 1624/// part of the pattern we're matching, looking at all of the users we find. 1625/// This determines whether something is an interior node, whether we have a 1626/// non-pattern node in between two pattern nodes (which prevent folding because 1627/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1628/// between pattern nodes (in which case the TF becomes part of the pattern). 1629/// 1630/// The walk we do here is guaranteed to be small because we quickly get down to 1631/// already selected nodes "below" us. 1632static ChainResult 1633WalkChainUsers(SDNode *ChainedNode, 1634 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1635 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1636 ChainResult Result = CR_Simple; 1637 1638 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1639 E = ChainedNode->use_end(); UI != E; ++UI) { 1640 // Make sure the use is of the chain, not some other value we produce. 1641 if (UI.getUse().getValueType() != MVT::Other) continue; 1642 1643 SDNode *User = *UI; 1644 1645 // If we see an already-selected machine node, then we've gone beyond the 1646 // pattern that we're selecting down into the already selected chunk of the 1647 // DAG. 1648 if (User->isMachineOpcode() || 1649 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1650 continue; 1651 1652 if (User->getOpcode() == ISD::CopyToReg || 1653 User->getOpcode() == ISD::CopyFromReg || 1654 User->getOpcode() == ISD::INLINEASM) { 1655 // If their node ID got reset to -1 then they've already been selected. 1656 // Treat them like a MachineOpcode. 1657 if (User->getNodeId() == -1) 1658 continue; 1659 } 1660 1661 // If we have a TokenFactor, we handle it specially. 1662 if (User->getOpcode() != ISD::TokenFactor) { 1663 // If the node isn't a token factor and isn't part of our pattern, then it 1664 // must be a random chained node in between two nodes we're selecting. 1665 // This happens when we have something like: 1666 // x = load ptr 1667 // call 1668 // y = x+4 1669 // store y -> ptr 1670 // Because we structurally match the load/store as a read/modify/write, 1671 // but the call is chained between them. We cannot fold in this case 1672 // because it would induce a cycle in the graph. 1673 if (!std::count(ChainedNodesInPattern.begin(), 1674 ChainedNodesInPattern.end(), User)) 1675 return CR_InducesCycle; 1676 1677 // Otherwise we found a node that is part of our pattern. For example in: 1678 // x = load ptr 1679 // y = x+4 1680 // store y -> ptr 1681 // This would happen when we're scanning down from the load and see the 1682 // store as a user. Record that there is a use of ChainedNode that is 1683 // part of the pattern and keep scanning uses. 1684 Result = CR_LeadsToInteriorNode; 1685 InteriorChainedNodes.push_back(User); 1686 continue; 1687 } 1688 1689 // If we found a TokenFactor, there are two cases to consider: first if the 1690 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1691 // uses of the TF are in our pattern) we just want to ignore it. Second, 1692 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1693 // [Load chain] 1694 // ^ 1695 // | 1696 // [Load] 1697 // ^ ^ 1698 // | \ DAG's like cheese 1699 // / \ do you? 1700 // / | 1701 // [TokenFactor] [Op] 1702 // ^ ^ 1703 // | | 1704 // \ / 1705 // \ / 1706 // [Store] 1707 // 1708 // In this case, the TokenFactor becomes part of our match and we rewrite it 1709 // as a new TokenFactor. 1710 // 1711 // To distinguish these two cases, do a recursive walk down the uses. 1712 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1713 case CR_Simple: 1714 // If the uses of the TokenFactor are just already-selected nodes, ignore 1715 // it, it is "below" our pattern. 1716 continue; 1717 case CR_InducesCycle: 1718 // If the uses of the TokenFactor lead to nodes that are not part of our 1719 // pattern that are not selected, folding would turn this into a cycle, 1720 // bail out now. 1721 return CR_InducesCycle; 1722 case CR_LeadsToInteriorNode: 1723 break; // Otherwise, keep processing. 1724 } 1725 1726 // Okay, we know we're in the interesting interior case. The TokenFactor 1727 // is now going to be considered part of the pattern so that we rewrite its 1728 // uses (it may have uses that are not part of the pattern) with the 1729 // ultimate chain result of the generated code. We will also add its chain 1730 // inputs as inputs to the ultimate TokenFactor we create. 1731 Result = CR_LeadsToInteriorNode; 1732 ChainedNodesInPattern.push_back(User); 1733 InteriorChainedNodes.push_back(User); 1734 continue; 1735 } 1736 1737 return Result; 1738} 1739 1740/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1741/// operation for when the pattern matched at least one node with a chains. The 1742/// input vector contains a list of all of the chained nodes that we match. We 1743/// must determine if this is a valid thing to cover (i.e. matching it won't 1744/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1745/// be used as the input node chain for the generated nodes. 1746static SDValue 1747HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1748 SelectionDAG *CurDAG) { 1749 // Walk all of the chained nodes we've matched, recursively scanning down the 1750 // users of the chain result. This adds any TokenFactor nodes that are caught 1751 // in between chained nodes to the chained and interior nodes list. 1752 SmallVector<SDNode*, 3> InteriorChainedNodes; 1753 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1754 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1755 InteriorChainedNodes) == CR_InducesCycle) 1756 return SDValue(); // Would induce a cycle. 1757 } 1758 1759 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1760 // that we are interested in. Form our input TokenFactor node. 1761 SmallVector<SDValue, 3> InputChains; 1762 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1763 // Add the input chain of this node to the InputChains list (which will be 1764 // the operands of the generated TokenFactor) if it's not an interior node. 1765 SDNode *N = ChainNodesMatched[i]; 1766 if (N->getOpcode() != ISD::TokenFactor) { 1767 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1768 continue; 1769 1770 // Otherwise, add the input chain. 1771 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1772 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1773 InputChains.push_back(InChain); 1774 continue; 1775 } 1776 1777 // If we have a token factor, we want to add all inputs of the token factor 1778 // that are not part of the pattern we're matching. 1779 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1780 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1781 N->getOperand(op).getNode())) 1782 InputChains.push_back(N->getOperand(op)); 1783 } 1784 } 1785 1786 SDValue Res; 1787 if (InputChains.size() == 1) 1788 return InputChains[0]; 1789 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1790 MVT::Other, &InputChains[0], InputChains.size()); 1791} 1792 1793/// MorphNode - Handle morphing a node in place for the selector. 1794SDNode *SelectionDAGISel:: 1795MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1796 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1797 // It is possible we're using MorphNodeTo to replace a node with no 1798 // normal results with one that has a normal result (or we could be 1799 // adding a chain) and the input could have flags and chains as well. 1800 // In this case we need to shifting the operands down. 1801 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1802 // than the old isel though. We should sink this into MorphNodeTo. 1803 int OldFlagResultNo = -1, OldChainResultNo = -1; 1804 1805 unsigned NTMNumResults = Node->getNumValues(); 1806 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1807 OldFlagResultNo = NTMNumResults-1; 1808 if (NTMNumResults != 1 && 1809 Node->getValueType(NTMNumResults-2) == MVT::Other) 1810 OldChainResultNo = NTMNumResults-2; 1811 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1812 OldChainResultNo = NTMNumResults-1; 1813 1814 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1815 // that this deletes operands of the old node that become dead. 1816 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1817 1818 // MorphNodeTo can operate in two ways: if an existing node with the 1819 // specified operands exists, it can just return it. Otherwise, it 1820 // updates the node in place to have the requested operands. 1821 if (Res == Node) { 1822 // If we updated the node in place, reset the node ID. To the isel, 1823 // this should be just like a newly allocated machine node. 1824 Res->setNodeId(-1); 1825 } 1826 1827 unsigned ResNumResults = Res->getNumValues(); 1828 // Move the flag if needed. 1829 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1830 (unsigned)OldFlagResultNo != ResNumResults-1) 1831 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1832 SDValue(Res, ResNumResults-1)); 1833 1834 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1835 --ResNumResults; 1836 1837 // Move the chain reference if needed. 1838 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1839 (unsigned)OldChainResultNo != ResNumResults-1) 1840 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1841 SDValue(Res, ResNumResults-1)); 1842 1843 // Otherwise, no replacement happened because the node already exists. Replace 1844 // Uses of the old node with the new one. 1845 if (Res != Node) 1846 CurDAG->ReplaceAllUsesWith(Node, Res); 1847 1848 return Res; 1849} 1850 1851/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1852ALWAYS_INLINE static bool 1853CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1854 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1855 // Accept if it is exactly the same as a previously recorded node. 1856 unsigned RecNo = MatcherTable[MatcherIndex++]; 1857 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1858 return N == RecordedNodes[RecNo]; 1859} 1860 1861/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1862ALWAYS_INLINE static bool 1863CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1864 SelectionDAGISel &SDISel) { 1865 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1866} 1867 1868/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1869ALWAYS_INLINE static bool 1870CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1871 SelectionDAGISel &SDISel, SDNode *N) { 1872 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1873} 1874 1875ALWAYS_INLINE static bool 1876CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1877 SDNode *N) { 1878 return N->getOpcode() == MatcherTable[MatcherIndex++]; 1879} 1880 1881ALWAYS_INLINE static bool 1882CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1883 SDValue N, const TargetLowering &TLI) { 1884 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1885 if (N.getValueType() == VT) return true; 1886 1887 // Handle the case when VT is iPTR. 1888 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1889} 1890 1891ALWAYS_INLINE static bool 1892CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1893 SDValue N, const TargetLowering &TLI, 1894 unsigned ChildNo) { 1895 if (ChildNo >= N.getNumOperands()) 1896 return false; // Match fails if out of range child #. 1897 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1898} 1899 1900 1901ALWAYS_INLINE static bool 1902CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1903 SDValue N) { 1904 return cast<CondCodeSDNode>(N)->get() == 1905 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1906} 1907 1908ALWAYS_INLINE static bool 1909CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1910 SDValue N, const TargetLowering &TLI) { 1911 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1912 if (cast<VTSDNode>(N)->getVT() == VT) 1913 return true; 1914 1915 // Handle the case when VT is iPTR. 1916 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1917} 1918 1919ALWAYS_INLINE static bool 1920CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1921 SDValue N) { 1922 int64_t Val = MatcherTable[MatcherIndex++]; 1923 if (Val & 128) 1924 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1925 1926 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1927 return C != 0 && C->getSExtValue() == Val; 1928} 1929 1930ALWAYS_INLINE static bool 1931CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1932 SDValue N, SelectionDAGISel &SDISel) { 1933 int64_t Val = MatcherTable[MatcherIndex++]; 1934 if (Val & 128) 1935 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1936 1937 if (N->getOpcode() != ISD::AND) return false; 1938 1939 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1940 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1941} 1942 1943ALWAYS_INLINE static bool 1944CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1945 SDValue N, SelectionDAGISel &SDISel) { 1946 int64_t Val = MatcherTable[MatcherIndex++]; 1947 if (Val & 128) 1948 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1949 1950 if (N->getOpcode() != ISD::OR) return false; 1951 1952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1953 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1954} 1955 1956/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1957/// scope, evaluate the current node. If the current predicate is known to 1958/// fail, set Result=true and return anything. If the current predicate is 1959/// known to pass, set Result=false and return the MatcherIndex to continue 1960/// with. If the current predicate is unknown, set Result=false and return the 1961/// MatcherIndex to continue with. 1962static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1963 unsigned Index, SDValue N, 1964 bool &Result, SelectionDAGISel &SDISel, 1965 SmallVectorImpl<SDValue> &RecordedNodes){ 1966 switch (Table[Index++]) { 1967 default: 1968 Result = false; 1969 return Index-1; // Could not evaluate this predicate. 1970 case SelectionDAGISel::OPC_CheckSame: 1971 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1972 return Index; 1973 case SelectionDAGISel::OPC_CheckPatternPredicate: 1974 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1975 return Index; 1976 case SelectionDAGISel::OPC_CheckPredicate: 1977 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1978 return Index; 1979 case SelectionDAGISel::OPC_CheckOpcode: 1980 Result = !::CheckOpcode(Table, Index, N.getNode()); 1981 return Index; 1982 case SelectionDAGISel::OPC_CheckType: 1983 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1984 return Index; 1985 case SelectionDAGISel::OPC_CheckChild0Type: 1986 case SelectionDAGISel::OPC_CheckChild1Type: 1987 case SelectionDAGISel::OPC_CheckChild2Type: 1988 case SelectionDAGISel::OPC_CheckChild3Type: 1989 case SelectionDAGISel::OPC_CheckChild4Type: 1990 case SelectionDAGISel::OPC_CheckChild5Type: 1991 case SelectionDAGISel::OPC_CheckChild6Type: 1992 case SelectionDAGISel::OPC_CheckChild7Type: 1993 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1994 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckCondCode: 1997 Result = !::CheckCondCode(Table, Index, N); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckValueType: 2000 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2001 return Index; 2002 case SelectionDAGISel::OPC_CheckInteger: 2003 Result = !::CheckInteger(Table, Index, N); 2004 return Index; 2005 case SelectionDAGISel::OPC_CheckAndImm: 2006 Result = !::CheckAndImm(Table, Index, N, SDISel); 2007 return Index; 2008 case SelectionDAGISel::OPC_CheckOrImm: 2009 Result = !::CheckOrImm(Table, Index, N, SDISel); 2010 return Index; 2011 } 2012} 2013 2014 2015struct MatchScope { 2016 /// FailIndex - If this match fails, this is the index to continue with. 2017 unsigned FailIndex; 2018 2019 /// NodeStack - The node stack when the scope was formed. 2020 SmallVector<SDValue, 4> NodeStack; 2021 2022 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2023 unsigned NumRecordedNodes; 2024 2025 /// NumMatchedMemRefs - The number of matched memref entries. 2026 unsigned NumMatchedMemRefs; 2027 2028 /// InputChain/InputFlag - The current chain/flag 2029 SDValue InputChain, InputFlag; 2030 2031 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2032 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2033}; 2034 2035SDNode *SelectionDAGISel:: 2036SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2037 unsigned TableSize) { 2038 // FIXME: Should these even be selected? Handle these cases in the caller? 2039 switch (NodeToMatch->getOpcode()) { 2040 default: 2041 break; 2042 case ISD::EntryToken: // These nodes remain the same. 2043 case ISD::BasicBlock: 2044 case ISD::Register: 2045 case ISD::HANDLENODE: 2046 case ISD::TargetConstant: 2047 case ISD::TargetConstantFP: 2048 case ISD::TargetConstantPool: 2049 case ISD::TargetFrameIndex: 2050 case ISD::TargetExternalSymbol: 2051 case ISD::TargetBlockAddress: 2052 case ISD::TargetJumpTable: 2053 case ISD::TargetGlobalTLSAddress: 2054 case ISD::TargetGlobalAddress: 2055 case ISD::TokenFactor: 2056 case ISD::CopyFromReg: 2057 case ISD::CopyToReg: 2058 NodeToMatch->setNodeId(-1); // Mark selected. 2059 return 0; 2060 case ISD::AssertSext: 2061 case ISD::AssertZext: 2062 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2063 NodeToMatch->getOperand(0)); 2064 return 0; 2065 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2066 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch); 2067 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2068 } 2069 2070 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2071 2072 // Set up the node stack with NodeToMatch as the only node on the stack. 2073 SmallVector<SDValue, 8> NodeStack; 2074 SDValue N = SDValue(NodeToMatch, 0); 2075 NodeStack.push_back(N); 2076 2077 // MatchScopes - Scopes used when matching, if a match failure happens, this 2078 // indicates where to continue checking. 2079 SmallVector<MatchScope, 8> MatchScopes; 2080 2081 // RecordedNodes - This is the set of nodes that have been recorded by the 2082 // state machine. 2083 SmallVector<SDValue, 8> RecordedNodes; 2084 2085 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2086 // pattern. 2087 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2088 2089 // These are the current input chain and flag for use when generating nodes. 2090 // Various Emit operations change these. For example, emitting a copytoreg 2091 // uses and updates these. 2092 SDValue InputChain, InputFlag; 2093 2094 // ChainNodesMatched - If a pattern matches nodes that have input/output 2095 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2096 // which ones they are. The result is captured into this list so that we can 2097 // update the chain results when the pattern is complete. 2098 SmallVector<SDNode*, 3> ChainNodesMatched; 2099 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2100 2101 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2102 NodeToMatch->dump(CurDAG); 2103 errs() << '\n'); 2104 2105 // Determine where to start the interpreter. Normally we start at opcode #0, 2106 // but if the state machine starts with an OPC_SwitchOpcode, then we 2107 // accelerate the first lookup (which is guaranteed to be hot) with the 2108 // OpcodeOffset table. 2109 unsigned MatcherIndex = 0; 2110 2111 if (!OpcodeOffset.empty()) { 2112 // Already computed the OpcodeOffset table, just index into it. 2113 if (N.getOpcode() < OpcodeOffset.size()) 2114 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2115 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2116 2117 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2118 // Otherwise, the table isn't computed, but the state machine does start 2119 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2120 // is the first time we're selecting an instruction. 2121 unsigned Idx = 1; 2122 while (1) { 2123 // Get the size of this case. 2124 unsigned CaseSize = MatcherTable[Idx++]; 2125 if (CaseSize & 128) 2126 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2127 if (CaseSize == 0) break; 2128 2129 // Get the opcode, add the index to the table. 2130 unsigned Opc = MatcherTable[Idx++]; 2131 if (Opc >= OpcodeOffset.size()) 2132 OpcodeOffset.resize((Opc+1)*2); 2133 OpcodeOffset[Opc] = Idx; 2134 Idx += CaseSize; 2135 } 2136 2137 // Okay, do the lookup for the first opcode. 2138 if (N.getOpcode() < OpcodeOffset.size()) 2139 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2140 } 2141 2142 while (1) { 2143 assert(MatcherIndex < TableSize && "Invalid index"); 2144 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2145 switch (Opcode) { 2146 case OPC_Scope: { 2147 // Okay, the semantics of this operation are that we should push a scope 2148 // then evaluate the first child. However, pushing a scope only to have 2149 // the first check fail (which then pops it) is inefficient. If we can 2150 // determine immediately that the first check (or first several) will 2151 // immediately fail, don't even bother pushing a scope for them. 2152 unsigned FailIndex; 2153 2154 while (1) { 2155 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2156 if (NumToSkip & 128) 2157 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2158 // Found the end of the scope with no match. 2159 if (NumToSkip == 0) { 2160 FailIndex = 0; 2161 break; 2162 } 2163 2164 FailIndex = MatcherIndex+NumToSkip; 2165 2166 // If we can't evaluate this predicate without pushing a scope (e.g. if 2167 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2168 // push the scope and evaluate the full predicate chain. 2169 bool Result; 2170 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2171 Result, *this, RecordedNodes); 2172 if (!Result) 2173 break; 2174 2175 DEBUG(errs() << " Skipped scope entry at index " << MatcherIndex 2176 << " continuing at " << FailIndex << "\n"); 2177 2178 2179 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2180 // move to the next case. 2181 MatcherIndex = FailIndex; 2182 } 2183 2184 // If the whole scope failed to match, bail. 2185 if (FailIndex == 0) break; 2186 2187 // Push a MatchScope which indicates where to go if the first child fails 2188 // to match. 2189 MatchScope NewEntry; 2190 NewEntry.FailIndex = FailIndex; 2191 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2192 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2193 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2194 NewEntry.InputChain = InputChain; 2195 NewEntry.InputFlag = InputFlag; 2196 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2197 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2198 MatchScopes.push_back(NewEntry); 2199 continue; 2200 } 2201 case OPC_RecordNode: 2202 // Remember this node, it may end up being an operand in the pattern. 2203 RecordedNodes.push_back(N); 2204 continue; 2205 2206 case OPC_RecordChild0: case OPC_RecordChild1: 2207 case OPC_RecordChild2: case OPC_RecordChild3: 2208 case OPC_RecordChild4: case OPC_RecordChild5: 2209 case OPC_RecordChild6: case OPC_RecordChild7: { 2210 unsigned ChildNo = Opcode-OPC_RecordChild0; 2211 if (ChildNo >= N.getNumOperands()) 2212 break; // Match fails if out of range child #. 2213 2214 RecordedNodes.push_back(N->getOperand(ChildNo)); 2215 continue; 2216 } 2217 case OPC_RecordMemRef: 2218 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2219 continue; 2220 2221 case OPC_CaptureFlagInput: 2222 // If the current node has an input flag, capture it in InputFlag. 2223 if (N->getNumOperands() != 0 && 2224 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2225 InputFlag = N->getOperand(N->getNumOperands()-1); 2226 continue; 2227 2228 case OPC_MoveChild: { 2229 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2230 if (ChildNo >= N.getNumOperands()) 2231 break; // Match fails if out of range child #. 2232 N = N.getOperand(ChildNo); 2233 NodeStack.push_back(N); 2234 continue; 2235 } 2236 2237 case OPC_MoveParent: 2238 // Pop the current node off the NodeStack. 2239 NodeStack.pop_back(); 2240 assert(!NodeStack.empty() && "Node stack imbalance!"); 2241 N = NodeStack.back(); 2242 continue; 2243 2244 case OPC_CheckSame: 2245 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2246 continue; 2247 case OPC_CheckPatternPredicate: 2248 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2249 continue; 2250 case OPC_CheckPredicate: 2251 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2252 N.getNode())) 2253 break; 2254 continue; 2255 case OPC_CheckComplexPat: { 2256 unsigned CPNum = MatcherTable[MatcherIndex++]; 2257 unsigned RecNo = MatcherTable[MatcherIndex++]; 2258 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2259 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2260 RecordedNodes)) 2261 break; 2262 continue; 2263 } 2264 case OPC_CheckOpcode: 2265 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2266 continue; 2267 2268 case OPC_CheckType: 2269 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2270 continue; 2271 2272 case OPC_SwitchOpcode: { 2273 unsigned CurNodeOpcode = N.getOpcode(); 2274 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2275 unsigned CaseSize; 2276 while (1) { 2277 // Get the size of this case. 2278 CaseSize = MatcherTable[MatcherIndex++]; 2279 if (CaseSize & 128) 2280 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2281 if (CaseSize == 0) break; 2282 2283 // If the opcode matches, then we will execute this case. 2284 if (CurNodeOpcode == MatcherTable[MatcherIndex++]) 2285 break; 2286 2287 // Otherwise, skip over this case. 2288 MatcherIndex += CaseSize; 2289 } 2290 2291 // If no cases matched, bail out. 2292 if (CaseSize == 0) break; 2293 2294 // Otherwise, execute the case we found. 2295 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2296 << " to " << MatcherIndex << "\n"); 2297 continue; 2298 } 2299 2300 case OPC_SwitchType: { 2301 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2302 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2303 unsigned CaseSize; 2304 while (1) { 2305 // Get the size of this case. 2306 CaseSize = MatcherTable[MatcherIndex++]; 2307 if (CaseSize & 128) 2308 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2309 if (CaseSize == 0) break; 2310 2311 MVT::SimpleValueType CaseVT = 2312 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2313 if (CaseVT == MVT::iPTR) 2314 CaseVT = TLI.getPointerTy().SimpleTy; 2315 2316 // If the VT matches, then we will execute this case. 2317 if (CurNodeVT == CaseVT) 2318 break; 2319 2320 // Otherwise, skip over this case. 2321 MatcherIndex += CaseSize; 2322 } 2323 2324 // If no cases matched, bail out. 2325 if (CaseSize == 0) break; 2326 2327 // Otherwise, execute the case we found. 2328 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2329 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2330 continue; 2331 } 2332 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2333 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2334 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2335 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2336 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2337 Opcode-OPC_CheckChild0Type)) 2338 break; 2339 continue; 2340 case OPC_CheckCondCode: 2341 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2342 continue; 2343 case OPC_CheckValueType: 2344 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2345 continue; 2346 case OPC_CheckInteger: 2347 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2348 continue; 2349 case OPC_CheckAndImm: 2350 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2351 continue; 2352 case OPC_CheckOrImm: 2353 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2354 continue; 2355 2356 case OPC_CheckFoldableChainNode: { 2357 assert(NodeStack.size() != 1 && "No parent node"); 2358 // Verify that all intermediate nodes between the root and this one have 2359 // a single use. 2360 bool HasMultipleUses = false; 2361 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2362 if (!NodeStack[i].hasOneUse()) { 2363 HasMultipleUses = true; 2364 break; 2365 } 2366 if (HasMultipleUses) break; 2367 2368 // Check to see that the target thinks this is profitable to fold and that 2369 // we can fold it without inducing cycles in the graph. 2370 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2371 NodeToMatch) || 2372 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2373 NodeToMatch, true/*We validate our own chains*/)) 2374 break; 2375 2376 continue; 2377 } 2378 case OPC_EmitInteger: { 2379 MVT::SimpleValueType VT = 2380 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2381 int64_t Val = MatcherTable[MatcherIndex++]; 2382 if (Val & 128) 2383 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2384 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2385 continue; 2386 } 2387 case OPC_EmitRegister: { 2388 MVT::SimpleValueType VT = 2389 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2390 unsigned RegNo = MatcherTable[MatcherIndex++]; 2391 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2392 continue; 2393 } 2394 2395 case OPC_EmitConvertToTarget: { 2396 // Convert from IMM/FPIMM to target version. 2397 unsigned RecNo = MatcherTable[MatcherIndex++]; 2398 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2399 SDValue Imm = RecordedNodes[RecNo]; 2400 2401 if (Imm->getOpcode() == ISD::Constant) { 2402 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2403 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2404 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2405 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2406 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2407 } 2408 2409 RecordedNodes.push_back(Imm); 2410 continue; 2411 } 2412 2413 case OPC_EmitMergeInputChains: { 2414 assert(InputChain.getNode() == 0 && 2415 "EmitMergeInputChains should be the first chain producing node"); 2416 // This node gets a list of nodes we matched in the input that have 2417 // chains. We want to token factor all of the input chains to these nodes 2418 // together. However, if any of the input chains is actually one of the 2419 // nodes matched in this pattern, then we have an intra-match reference. 2420 // Ignore these because the newly token factored chain should not refer to 2421 // the old nodes. 2422 unsigned NumChains = MatcherTable[MatcherIndex++]; 2423 assert(NumChains != 0 && "Can't TF zero chains"); 2424 2425 assert(ChainNodesMatched.empty() && 2426 "Should only have one EmitMergeInputChains per match"); 2427 2428 // Read all of the chained nodes. 2429 for (unsigned i = 0; i != NumChains; ++i) { 2430 unsigned RecNo = MatcherTable[MatcherIndex++]; 2431 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2432 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2433 2434 // FIXME: What if other value results of the node have uses not matched 2435 // by this pattern? 2436 if (ChainNodesMatched.back() != NodeToMatch && 2437 !RecordedNodes[RecNo].hasOneUse()) { 2438 ChainNodesMatched.clear(); 2439 break; 2440 } 2441 } 2442 2443 // If the inner loop broke out, the match fails. 2444 if (ChainNodesMatched.empty()) 2445 break; 2446 2447 // Merge the input chains if they are not intra-pattern references. 2448 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2449 2450 if (InputChain.getNode() == 0) 2451 break; // Failed to merge. 2452 2453 continue; 2454 } 2455 2456 case OPC_EmitCopyToReg: { 2457 unsigned RecNo = MatcherTable[MatcherIndex++]; 2458 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2459 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2460 2461 if (InputChain.getNode() == 0) 2462 InputChain = CurDAG->getEntryNode(); 2463 2464 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2465 DestPhysReg, RecordedNodes[RecNo], 2466 InputFlag); 2467 2468 InputFlag = InputChain.getValue(1); 2469 continue; 2470 } 2471 2472 case OPC_EmitNodeXForm: { 2473 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2474 unsigned RecNo = MatcherTable[MatcherIndex++]; 2475 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2476 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2477 continue; 2478 } 2479 2480 case OPC_EmitNode: 2481 case OPC_MorphNodeTo: { 2482 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2483 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2484 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2485 // Get the result VT list. 2486 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2487 SmallVector<EVT, 4> VTs; 2488 for (unsigned i = 0; i != NumVTs; ++i) { 2489 MVT::SimpleValueType VT = 2490 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2491 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2492 VTs.push_back(VT); 2493 } 2494 2495 if (EmitNodeInfo & OPFL_Chain) 2496 VTs.push_back(MVT::Other); 2497 if (EmitNodeInfo & OPFL_FlagOutput) 2498 VTs.push_back(MVT::Flag); 2499 2500 // This is hot code, so optimize the two most common cases of 1 and 2 2501 // results. 2502 SDVTList VTList; 2503 if (VTs.size() == 1) 2504 VTList = CurDAG->getVTList(VTs[0]); 2505 else if (VTs.size() == 2) 2506 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2507 else 2508 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2509 2510 // Get the operand list. 2511 unsigned NumOps = MatcherTable[MatcherIndex++]; 2512 SmallVector<SDValue, 8> Ops; 2513 for (unsigned i = 0; i != NumOps; ++i) { 2514 unsigned RecNo = MatcherTable[MatcherIndex++]; 2515 if (RecNo & 128) 2516 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2517 2518 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2519 Ops.push_back(RecordedNodes[RecNo]); 2520 } 2521 2522 // If there are variadic operands to add, handle them now. 2523 if (EmitNodeInfo & OPFL_VariadicInfo) { 2524 // Determine the start index to copy from. 2525 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2526 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2527 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2528 "Invalid variadic node"); 2529 // Copy all of the variadic operands, not including a potential flag 2530 // input. 2531 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2532 i != e; ++i) { 2533 SDValue V = NodeToMatch->getOperand(i); 2534 if (V.getValueType() == MVT::Flag) break; 2535 Ops.push_back(V); 2536 } 2537 } 2538 2539 // If this has chain/flag inputs, add them. 2540 if (EmitNodeInfo & OPFL_Chain) 2541 Ops.push_back(InputChain); 2542 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2543 Ops.push_back(InputFlag); 2544 2545 // Create the node. 2546 SDNode *Res = 0; 2547 if (Opcode != OPC_MorphNodeTo) { 2548 // If this is a normal EmitNode command, just create the new node and 2549 // add the results to the RecordedNodes list. 2550 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2551 VTList, Ops.data(), Ops.size()); 2552 2553 // Add all the non-flag/non-chain results to the RecordedNodes list. 2554 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2555 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2556 RecordedNodes.push_back(SDValue(Res, i)); 2557 } 2558 2559 } else { 2560 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2561 EmitNodeInfo); 2562 } 2563 2564 // If the node had chain/flag results, update our notion of the current 2565 // chain and flag. 2566 if (EmitNodeInfo & OPFL_FlagOutput) { 2567 InputFlag = SDValue(Res, VTs.size()-1); 2568 if (EmitNodeInfo & OPFL_Chain) 2569 InputChain = SDValue(Res, VTs.size()-2); 2570 } else if (EmitNodeInfo & OPFL_Chain) 2571 InputChain = SDValue(Res, VTs.size()-1); 2572 2573 // If the OPFL_MemRefs flag is set on this node, slap all of the 2574 // accumulated memrefs onto it. 2575 // 2576 // FIXME: This is vastly incorrect for patterns with multiple outputs 2577 // instructions that access memory and for ComplexPatterns that match 2578 // loads. 2579 if (EmitNodeInfo & OPFL_MemRefs) { 2580 MachineSDNode::mmo_iterator MemRefs = 2581 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2582 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2583 cast<MachineSDNode>(Res) 2584 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2585 } 2586 2587 DEBUG(errs() << " " 2588 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2589 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2590 2591 // If this was a MorphNodeTo then we're completely done! 2592 if (Opcode == OPC_MorphNodeTo) { 2593 // Update chain and flag uses. 2594 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2595 InputFlag, FlagResultNodesMatched, true); 2596 return Res; 2597 } 2598 2599 continue; 2600 } 2601 2602 case OPC_MarkFlagResults: { 2603 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2604 2605 // Read and remember all the flag-result nodes. 2606 for (unsigned i = 0; i != NumNodes; ++i) { 2607 unsigned RecNo = MatcherTable[MatcherIndex++]; 2608 if (RecNo & 128) 2609 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2610 2611 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2612 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2613 } 2614 continue; 2615 } 2616 2617 case OPC_CompleteMatch: { 2618 // The match has been completed, and any new nodes (if any) have been 2619 // created. Patch up references to the matched dag to use the newly 2620 // created nodes. 2621 unsigned NumResults = MatcherTable[MatcherIndex++]; 2622 2623 for (unsigned i = 0; i != NumResults; ++i) { 2624 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2625 if (ResSlot & 128) 2626 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2627 2628 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2629 SDValue Res = RecordedNodes[ResSlot]; 2630 2631 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program 2632 // after (parallel) on input patterns are removed. This would also 2633 // allow us to stop encoding #results in OPC_CompleteMatch's table 2634 // entry. 2635 if (NodeToMatch->getNumValues() <= i || 2636 NodeToMatch->getValueType(i) == MVT::Other || 2637 NodeToMatch->getValueType(i) == MVT::Flag) 2638 break; 2639 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2640 NodeToMatch->getValueType(i) == MVT::iPTR || 2641 Res.getValueType() == MVT::iPTR || 2642 NodeToMatch->getValueType(i).getSizeInBits() == 2643 Res.getValueType().getSizeInBits()) && 2644 "invalid replacement"); 2645 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2646 } 2647 2648 // If the root node defines a flag, add it to the flag nodes to update 2649 // list. 2650 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2651 FlagResultNodesMatched.push_back(NodeToMatch); 2652 2653 // Update chain and flag uses. 2654 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2655 InputFlag, FlagResultNodesMatched, false); 2656 2657 assert(NodeToMatch->use_empty() && 2658 "Didn't replace all uses of the node?"); 2659 2660 // FIXME: We just return here, which interacts correctly with SelectRoot 2661 // above. We should fix this to not return an SDNode* anymore. 2662 return 0; 2663 } 2664 } 2665 2666 // If the code reached this point, then the match failed. See if there is 2667 // another child to try in the current 'Scope', otherwise pop it until we 2668 // find a case to check. 2669 while (1) { 2670 if (MatchScopes.empty()) { 2671 CannotYetSelect(NodeToMatch); 2672 return 0; 2673 } 2674 2675 // Restore the interpreter state back to the point where the scope was 2676 // formed. 2677 MatchScope &LastScope = MatchScopes.back(); 2678 RecordedNodes.resize(LastScope.NumRecordedNodes); 2679 NodeStack.clear(); 2680 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2681 N = NodeStack.back(); 2682 2683 DEBUG(errs() << " Match failed at index " << MatcherIndex 2684 << " continuing at " << LastScope.FailIndex << "\n"); 2685 2686 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2687 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2688 MatcherIndex = LastScope.FailIndex; 2689 2690 InputChain = LastScope.InputChain; 2691 InputFlag = LastScope.InputFlag; 2692 if (!LastScope.HasChainNodesMatched) 2693 ChainNodesMatched.clear(); 2694 if (!LastScope.HasFlagResultNodesMatched) 2695 FlagResultNodesMatched.clear(); 2696 2697 // Check to see what the offset is at the new MatcherIndex. If it is zero 2698 // we have reached the end of this scope, otherwise we have another child 2699 // in the current scope to try. 2700 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2701 if (NumToSkip & 128) 2702 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2703 2704 // If we have another child in this scope to match, update FailIndex and 2705 // try it. 2706 if (NumToSkip != 0) { 2707 LastScope.FailIndex = MatcherIndex+NumToSkip; 2708 break; 2709 } 2710 2711 // End of this scope, pop it and try the next child in the containing 2712 // scope. 2713 MatchScopes.pop_back(); 2714 } 2715 } 2716} 2717 2718 2719 2720void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2721 std::string msg; 2722 raw_string_ostream Msg(msg); 2723 Msg << "Cannot yet select: "; 2724 2725 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2726 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2727 N->getOpcode() != ISD::INTRINSIC_VOID) { 2728 N->printrFull(Msg, CurDAG); 2729 } else { 2730 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2731 unsigned iid = 2732 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2733 if (iid < Intrinsic::num_intrinsics) 2734 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2735 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2736 Msg << "target intrinsic %" << TII->getName(iid); 2737 else 2738 Msg << "unknown intrinsic #" << iid; 2739 } 2740 llvm_report_error(Msg.str()); 2741} 2742 2743char SelectionDAGISel::ID = 0; 2744