SelectionDAGISel.cpp revision e50ed30282bb5b4a9ed952580523f2dda16215ac
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuild.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/Analysis/AliasAnalysis.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/CodeGen/FastISel.h" 29#include "llvm/CodeGen/GCStrategy.h" 30#include "llvm/CodeGen/GCMetadata.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineFunctionAnalysis.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 39#include "llvm/CodeGen/SchedulerRegistry.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/CodeGen/DwarfWriter.h" 42#include "llvm/Target/TargetRegisterInfo.h" 43#include "llvm/Target/TargetData.h" 44#include "llvm/Target/TargetFrameInfo.h" 45#include "llvm/Target/TargetInstrInfo.h" 46#include "llvm/Target/TargetLowering.h" 47#include "llvm/Target/TargetMachine.h" 48#include "llvm/Target/TargetOptions.h" 49#include "llvm/Support/Compiler.h" 50#include "llvm/Support/Debug.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/Timer.h" 54#include "llvm/Support/raw_ostream.h" 55#include <algorithm> 56using namespace llvm; 57 58static cl::opt<bool> 59DisableLegalizeTypes("disable-legalize-types", cl::Hidden); 60static cl::opt<bool> 61EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 62 cl::desc("Enable verbose messages in the \"fast\" " 63 "instruction selector")); 64static cl::opt<bool> 65EnableFastISelAbort("fast-isel-abort", cl::Hidden, 66 cl::desc("Enable abort calls when \"fast\" instruction fails")); 67static cl::opt<bool> 68SchedLiveInCopies("schedule-livein-copies", 69 cl::desc("Schedule copies of livein registers"), 70 cl::init(false)); 71 72#ifndef NDEBUG 73static cl::opt<bool> 74ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 75 cl::desc("Pop up a window to show dags before the first " 76 "dag combine pass")); 77static cl::opt<bool> 78ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before legalize types")); 80static cl::opt<bool> 81ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 82 cl::desc("Pop up a window to show dags before legalize")); 83static cl::opt<bool> 84ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 85 cl::desc("Pop up a window to show dags before the second " 86 "dag combine pass")); 87static cl::opt<bool> 88ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 89 cl::desc("Pop up a window to show dags before the post legalize types" 90 " dag combine pass")); 91static cl::opt<bool> 92ViewISelDAGs("view-isel-dags", cl::Hidden, 93 cl::desc("Pop up a window to show isel dags as they are selected")); 94static cl::opt<bool> 95ViewSchedDAGs("view-sched-dags", cl::Hidden, 96 cl::desc("Pop up a window to show sched dags as they are processed")); 97static cl::opt<bool> 98ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 99 cl::desc("Pop up a window to show SUnit dags after they are processed")); 100#else 101static const bool ViewDAGCombine1 = false, 102 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 103 ViewDAGCombine2 = false, 104 ViewDAGCombineLT = false, 105 ViewISelDAGs = false, ViewSchedDAGs = false, 106 ViewSUnitDAGs = false; 107#endif 108 109//===---------------------------------------------------------------------===// 110/// 111/// RegisterScheduler class - Track the registration of instruction schedulers. 112/// 113//===---------------------------------------------------------------------===// 114MachinePassRegistry RegisterScheduler::Registry; 115 116//===---------------------------------------------------------------------===// 117/// 118/// ISHeuristic command line option for instruction schedulers. 119/// 120//===---------------------------------------------------------------------===// 121static cl::opt<RegisterScheduler::FunctionPassCtor, false, 122 RegisterPassParser<RegisterScheduler> > 123ISHeuristic("pre-RA-sched", 124 cl::init(&createDefaultScheduler), 125 cl::desc("Instruction schedulers available (before register" 126 " allocation):")); 127 128static RegisterScheduler 129defaultListDAGScheduler("default", "Best scheduler for the target", 130 createDefaultScheduler); 131 132namespace llvm { 133 //===--------------------------------------------------------------------===// 134 /// createDefaultScheduler - This creates an instruction scheduler appropriate 135 /// for the target. 136 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 137 CodeGenOpt::Level OptLevel) { 138 const TargetLowering &TLI = IS->getTargetLowering(); 139 140 if (OptLevel == CodeGenOpt::None) 141 return createFastDAGScheduler(IS, OptLevel); 142 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 143 return createTDListDAGScheduler(IS, OptLevel); 144 assert(TLI.getSchedulingPreference() == 145 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 146 return createBURRListDAGScheduler(IS, OptLevel); 147 } 148} 149 150// EmitInstrWithCustomInserter - This method should be implemented by targets 151// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 152// instructions are special in various ways, which require special support to 153// insert. The specified MachineInstr is created but not inserted into any 154// basic blocks, and the scheduler passes ownership of it to this method. 155MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 156 MachineBasicBlock *MBB) const { 157#ifndef NDEBUG 158 cerr << "If a target marks an instruction with " 159 "'usesCustomDAGSchedInserter', it must implement " 160 "TargetLowering::EmitInstrWithCustomInserter!"; 161#endif 162 llvm_unreachable(0); 163 return 0; 164} 165 166/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 167/// physical register has only a single copy use, then coalesced the copy 168/// if possible. 169static void EmitLiveInCopy(MachineBasicBlock *MBB, 170 MachineBasicBlock::iterator &InsertPos, 171 unsigned VirtReg, unsigned PhysReg, 172 const TargetRegisterClass *RC, 173 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 174 const MachineRegisterInfo &MRI, 175 const TargetRegisterInfo &TRI, 176 const TargetInstrInfo &TII) { 177 unsigned NumUses = 0; 178 MachineInstr *UseMI = NULL; 179 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 180 UE = MRI.use_end(); UI != UE; ++UI) { 181 UseMI = &*UI; 182 if (++NumUses > 1) 183 break; 184 } 185 186 // If the number of uses is not one, or the use is not a move instruction, 187 // don't coalesce. Also, only coalesce away a virtual register to virtual 188 // register copy. 189 bool Coalesced = false; 190 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 191 if (NumUses == 1 && 192 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 193 TargetRegisterInfo::isVirtualRegister(DstReg)) { 194 VirtReg = DstReg; 195 Coalesced = true; 196 } 197 198 // Now find an ideal location to insert the copy. 199 MachineBasicBlock::iterator Pos = InsertPos; 200 while (Pos != MBB->begin()) { 201 MachineInstr *PrevMI = prior(Pos); 202 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 203 // copyRegToReg might emit multiple instructions to do a copy. 204 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 205 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 206 // This is what the BB looks like right now: 207 // r1024 = mov r0 208 // ... 209 // r1 = mov r1024 210 // 211 // We want to insert "r1025 = mov r1". Inserting this copy below the 212 // move to r1024 makes it impossible for that move to be coalesced. 213 // 214 // r1025 = mov r1 215 // r1024 = mov r0 216 // ... 217 // r1 = mov 1024 218 // r2 = mov 1025 219 break; // Woot! Found a good location. 220 --Pos; 221 } 222 223 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 224 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 225 (void) Emitted; 226 227CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 228 if (Coalesced) { 229 if (&*InsertPos == UseMI) ++InsertPos; 230 MBB->erase(UseMI); 231 } 232} 233 234/// EmitLiveInCopies - If this is the first basic block in the function, 235/// and if it has live ins that need to be copied into vregs, emit the 236/// copies into the block. 237static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 238 const MachineRegisterInfo &MRI, 239 const TargetRegisterInfo &TRI, 240 const TargetInstrInfo &TII) { 241 if (SchedLiveInCopies) { 242 // Emit the copies at a heuristically-determined location in the block. 243 DenseMap<MachineInstr*, unsigned> CopyRegMap; 244 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 245 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 246 E = MRI.livein_end(); LI != E; ++LI) 247 if (LI->second) { 248 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 249 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 250 RC, CopyRegMap, MRI, TRI, TII); 251 } 252 } else { 253 // Emit the copies into the top of the block. 254 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 255 E = MRI.livein_end(); LI != E; ++LI) 256 if (LI->second) { 257 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 258 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 259 LI->second, LI->first, RC, RC); 260 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 261 (void) Emitted; 262 } 263 } 264} 265 266//===----------------------------------------------------------------------===// 267// SelectionDAGISel code 268//===----------------------------------------------------------------------===// 269 270SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 271 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 272 FuncInfo(new FunctionLoweringInfo(TLI)), 273 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 274 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)), 275 GFI(), 276 OptLevel(OL), 277 DAGSize(0) 278{} 279 280SelectionDAGISel::~SelectionDAGISel() { 281 delete SDL; 282 delete CurDAG; 283 delete FuncInfo; 284} 285 286unsigned SelectionDAGISel::MakeReg(EVT VT) { 287 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 288} 289 290void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 291 AU.addRequired<AliasAnalysis>(); 292 AU.addPreserved<AliasAnalysis>(); 293 AU.addRequired<GCModuleInfo>(); 294 AU.addPreserved<GCModuleInfo>(); 295 AU.addRequired<DwarfWriter>(); 296 AU.addPreserved<DwarfWriter>(); 297 MachineFunctionPass::getAnalysisUsage(AU); 298} 299 300bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 301 Function &Fn = *mf.getFunction(); 302 303 // Do some sanity-checking on the command-line options. 304 assert((!EnableFastISelVerbose || EnableFastISel) && 305 "-fast-isel-verbose requires -fast-isel"); 306 assert((!EnableFastISelAbort || EnableFastISel) && 307 "-fast-isel-abort requires -fast-isel"); 308 309 // Get alias analysis for load/store combining. 310 AA = &getAnalysis<AliasAnalysis>(); 311 312 MF = &mf; 313 const TargetInstrInfo &TII = *TM.getInstrInfo(); 314 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 315 316 if (Fn.hasGC()) 317 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 318 else 319 GFI = 0; 320 RegInfo = &MF->getRegInfo(); 321 DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n"); 322 323 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 324 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 325 CurDAG->init(*MF, MMI, DW); 326 FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); 327 SDL->init(GFI, *AA); 328 329 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 330 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 331 // Mark landing pad. 332 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 333 334 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 335 336 // If the first basic block in the function has live ins that need to be 337 // copied into vregs, emit the copies into the top of the block before 338 // emitting the code for the block. 339 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 340 341 // Add function live-ins to entry block live-in set. 342 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 343 E = RegInfo->livein_end(); I != E; ++I) 344 MF->begin()->addLiveIn(I->first); 345 346#ifndef NDEBUG 347 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 348 "Not all catch info was assigned to a landing pad!"); 349#endif 350 351 FuncInfo->clear(); 352 353 return true; 354} 355 356static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 357 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 358 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 359 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 360 // Apply the catch info to DestBB. 361 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 362#ifndef NDEBUG 363 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 364 FLI.CatchInfoFound.insert(EHSel); 365#endif 366 } 367} 368 369void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 370 BasicBlock::iterator Begin, 371 BasicBlock::iterator End) { 372 SDL->setCurrentBasicBlock(BB); 373 374 // Lower all of the non-terminator instructions. If a call is emitted 375 // as a tail call, cease emitting nodes for this block. 376 for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) 377 if (!isa<TerminatorInst>(I)) 378 SDL->visit(*I); 379 380 if (!SDL->HasTailCall) { 381 // Ensure that all instructions which are used outside of their defining 382 // blocks are available as virtual registers. Invoke is handled elsewhere. 383 for (BasicBlock::iterator I = Begin; I != End; ++I) 384 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 385 SDL->CopyToExportRegsIfNeeded(I); 386 387 // Handle PHI nodes in successor blocks. 388 if (End == LLVMBB->end()) { 389 HandlePHINodesInSuccessorBlocks(LLVMBB); 390 391 // Lower the terminator after the copies are emitted. 392 SDL->visit(*LLVMBB->getTerminator()); 393 } 394 } 395 396 // Make sure the root of the DAG is up-to-date. 397 CurDAG->setRoot(SDL->getControlRoot()); 398 399 // Final step, emit the lowered DAG as machine code. 400 CodeGenAndEmitDAG(); 401 SDL->clear(); 402} 403 404void SelectionDAGISel::ComputeLiveOutVRegInfo() { 405 SmallPtrSet<SDNode*, 128> VisitedNodes; 406 SmallVector<SDNode*, 128> Worklist; 407 408 Worklist.push_back(CurDAG->getRoot().getNode()); 409 410 APInt Mask; 411 APInt KnownZero; 412 APInt KnownOne; 413 414 while (!Worklist.empty()) { 415 SDNode *N = Worklist.back(); 416 Worklist.pop_back(); 417 418 // If we've already seen this node, ignore it. 419 if (!VisitedNodes.insert(N)) 420 continue; 421 422 // Otherwise, add all chain operands to the worklist. 423 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 424 if (N->getOperand(i).getValueType() == EVT::Other) 425 Worklist.push_back(N->getOperand(i).getNode()); 426 427 // If this is a CopyToReg with a vreg dest, process it. 428 if (N->getOpcode() != ISD::CopyToReg) 429 continue; 430 431 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 432 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 433 continue; 434 435 // Ignore non-scalar or non-integer values. 436 SDValue Src = N->getOperand(2); 437 EVT SrcVT = Src.getValueType(); 438 if (!SrcVT.isInteger() || SrcVT.isVector()) 439 continue; 440 441 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 442 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 443 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 444 445 // Only install this information if it tells us something. 446 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 447 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 448 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 449 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 450 FunctionLoweringInfo::LiveOutInfo &LOI = 451 FuncInfo->LiveOutRegInfo[DestReg]; 452 LOI.NumSignBits = NumSignBits; 453 LOI.KnownOne = KnownOne; 454 LOI.KnownZero = KnownZero; 455 } 456 } 457} 458 459void SelectionDAGISel::CodeGenAndEmitDAG() { 460 std::string GroupName; 461 if (TimePassesIsEnabled) 462 GroupName = "Instruction Selection and Scheduling"; 463 std::string BlockName; 464 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 465 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 466 ViewSUnitDAGs) 467 BlockName = MF->getFunction()->getNameStr() + ":" + 468 BB->getBasicBlock()->getNameStr(); 469 470 DOUT << "Initial selection DAG:\n"; 471 DEBUG(CurDAG->dump()); 472 473 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 474 475 // Run the DAG combiner in pre-legalize mode. 476 if (TimePassesIsEnabled) { 477 NamedRegionTimer T("DAG Combining 1", GroupName); 478 CurDAG->Combine(Unrestricted, *AA, OptLevel); 479 } else { 480 CurDAG->Combine(Unrestricted, *AA, OptLevel); 481 } 482 483 DOUT << "Optimized lowered selection DAG:\n"; 484 DEBUG(CurDAG->dump()); 485 486 // Second step, hack on the DAG until it only uses operations and types that 487 // the target supports. 488 if (!DisableLegalizeTypes) { 489 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 490 BlockName); 491 492 bool Changed; 493 if (TimePassesIsEnabled) { 494 NamedRegionTimer T("Type Legalization", GroupName); 495 Changed = CurDAG->LegalizeTypes(); 496 } else { 497 Changed = CurDAG->LegalizeTypes(); 498 } 499 500 DOUT << "Type-legalized selection DAG:\n"; 501 DEBUG(CurDAG->dump()); 502 503 if (Changed) { 504 if (ViewDAGCombineLT) 505 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 506 507 // Run the DAG combiner in post-type-legalize mode. 508 if (TimePassesIsEnabled) { 509 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 510 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 511 } else { 512 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 513 } 514 515 DOUT << "Optimized type-legalized selection DAG:\n"; 516 DEBUG(CurDAG->dump()); 517 } 518 519 if (TimePassesIsEnabled) { 520 NamedRegionTimer T("Vector Legalization", GroupName); 521 Changed = CurDAG->LegalizeVectors(); 522 } else { 523 Changed = CurDAG->LegalizeVectors(); 524 } 525 526 if (Changed) { 527 if (TimePassesIsEnabled) { 528 NamedRegionTimer T("Type Legalization 2", GroupName); 529 Changed = CurDAG->LegalizeTypes(); 530 } else { 531 Changed = CurDAG->LegalizeTypes(); 532 } 533 534 if (ViewDAGCombineLT) 535 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 536 537 // Run the DAG combiner in post-type-legalize mode. 538 if (TimePassesIsEnabled) { 539 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 540 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 541 } else { 542 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 543 } 544 545 DOUT << "Optimized vector-legalized selection DAG:\n"; 546 DEBUG(CurDAG->dump()); 547 } 548 } 549 550 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 551 552 if (TimePassesIsEnabled) { 553 NamedRegionTimer T("DAG Legalization", GroupName); 554 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 555 } else { 556 CurDAG->Legalize(DisableLegalizeTypes, OptLevel); 557 } 558 559 DOUT << "Legalized selection DAG:\n"; 560 DEBUG(CurDAG->dump()); 561 562 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 563 564 // Run the DAG combiner in post-legalize mode. 565 if (TimePassesIsEnabled) { 566 NamedRegionTimer T("DAG Combining 2", GroupName); 567 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 568 } else { 569 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 570 } 571 572 DOUT << "Optimized legalized selection DAG:\n"; 573 DEBUG(CurDAG->dump()); 574 575 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 576 577 if (OptLevel != CodeGenOpt::None) 578 ComputeLiveOutVRegInfo(); 579 580 // Third, instruction select all of the operations to machine code, adding the 581 // code to the MachineBasicBlock. 582 if (TimePassesIsEnabled) { 583 NamedRegionTimer T("Instruction Selection", GroupName); 584 InstructionSelect(); 585 } else { 586 InstructionSelect(); 587 } 588 589 DOUT << "Selected selection DAG:\n"; 590 DEBUG(CurDAG->dump()); 591 592 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 593 594 // Schedule machine code. 595 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 596 if (TimePassesIsEnabled) { 597 NamedRegionTimer T("Instruction Scheduling", GroupName); 598 Scheduler->Run(CurDAG, BB, BB->end()); 599 } else { 600 Scheduler->Run(CurDAG, BB, BB->end()); 601 } 602 603 if (ViewSUnitDAGs) Scheduler->viewGraph(); 604 605 // Emit machine code to BB. This can change 'BB' to the last block being 606 // inserted into. 607 if (TimePassesIsEnabled) { 608 NamedRegionTimer T("Instruction Creation", GroupName); 609 BB = Scheduler->EmitSchedule(); 610 } else { 611 BB = Scheduler->EmitSchedule(); 612 } 613 614 // Free the scheduler state. 615 if (TimePassesIsEnabled) { 616 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 617 delete Scheduler; 618 } else { 619 delete Scheduler; 620 } 621 622 DOUT << "Selected machine code:\n"; 623 DEBUG(BB->dump()); 624} 625 626void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 627 MachineFunction &MF, 628 MachineModuleInfo *MMI, 629 DwarfWriter *DW, 630 const TargetInstrInfo &TII) { 631 // Initialize the Fast-ISel state, if needed. 632 FastISel *FastIS = 0; 633 if (EnableFastISel) 634 FastIS = TLI.createFastISel(MF, MMI, DW, 635 FuncInfo->ValueMap, 636 FuncInfo->MBBMap, 637 FuncInfo->StaticAllocaMap 638#ifndef NDEBUG 639 , FuncInfo->CatchInfoLost 640#endif 641 ); 642 643 // Iterate over all basic blocks in the function. 644 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 645 BasicBlock *LLVMBB = &*I; 646 BB = FuncInfo->MBBMap[LLVMBB]; 647 648 BasicBlock::iterator const Begin = LLVMBB->begin(); 649 BasicBlock::iterator const End = LLVMBB->end(); 650 BasicBlock::iterator BI = Begin; 651 652 // Lower any arguments needed in this block if this is the entry block. 653 bool SuppressFastISel = false; 654 if (LLVMBB == &Fn.getEntryBlock()) { 655 LowerArguments(LLVMBB); 656 657 // If any of the arguments has the byval attribute, forgo 658 // fast-isel in the entry block. 659 if (FastIS) { 660 unsigned j = 1; 661 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 662 I != E; ++I, ++j) 663 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 664 if (EnableFastISelVerbose || EnableFastISelAbort) 665 cerr << "FastISel skips entry block due to byval argument\n"; 666 SuppressFastISel = true; 667 break; 668 } 669 } 670 } 671 672 if (MMI && BB->isLandingPad()) { 673 // Add a label to mark the beginning of the landing pad. Deletion of the 674 // landing pad can thus be detected via the MachineModuleInfo. 675 unsigned LabelID = MMI->addLandingPad(BB); 676 677 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); 678 BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID); 679 680 // Mark exception register as live in. 681 unsigned Reg = TLI.getExceptionAddressRegister(); 682 if (Reg) BB->addLiveIn(Reg); 683 684 // Mark exception selector register as live in. 685 Reg = TLI.getExceptionSelectorRegister(); 686 if (Reg) BB->addLiveIn(Reg); 687 688 // FIXME: Hack around an exception handling flaw (PR1508): the personality 689 // function and list of typeids logically belong to the invoke (or, if you 690 // like, the basic block containing the invoke), and need to be associated 691 // with it in the dwarf exception handling tables. Currently however the 692 // information is provided by an intrinsic (eh.selector) that can be moved 693 // to unexpected places by the optimizers: if the unwind edge is critical, 694 // then breaking it can result in the intrinsics being in the successor of 695 // the landing pad, not the landing pad itself. This results in exceptions 696 // not being caught because no typeids are associated with the invoke. 697 // This may not be the only way things can go wrong, but it is the only way 698 // we try to work around for the moment. 699 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 700 701 if (Br && Br->isUnconditional()) { // Critical edge? 702 BasicBlock::iterator I, E; 703 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 704 if (isa<EHSelectorInst>(I)) 705 break; 706 707 if (I == E) 708 // No catch info found - try to extract some from the successor. 709 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 710 } 711 } 712 713 // Before doing SelectionDAG ISel, see if FastISel has been requested. 714 if (FastIS && !SuppressFastISel) { 715 // Emit code for any incoming arguments. This must happen before 716 // beginning FastISel on the entry block. 717 if (LLVMBB == &Fn.getEntryBlock()) { 718 CurDAG->setRoot(SDL->getControlRoot()); 719 CodeGenAndEmitDAG(); 720 SDL->clear(); 721 } 722 FastIS->startNewBlock(BB); 723 // Do FastISel on as many instructions as possible. 724 for (; BI != End; ++BI) { 725 // Just before the terminator instruction, insert instructions to 726 // feed PHI nodes in successor blocks. 727 if (isa<TerminatorInst>(BI)) 728 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 729 if (EnableFastISelVerbose || EnableFastISelAbort) { 730 cerr << "FastISel miss: "; 731 BI->dump(); 732 } 733 assert(!EnableFastISelAbort && 734 "FastISel didn't handle a PHI in a successor"); 735 break; 736 } 737 738 // First try normal tablegen-generated "fast" selection. 739 if (FastIS->SelectInstruction(BI)) 740 continue; 741 742 // Next, try calling the target to attempt to handle the instruction. 743 if (FastIS->TargetSelectInstruction(BI)) 744 continue; 745 746 // Then handle certain instructions as single-LLVM-Instruction blocks. 747 if (isa<CallInst>(BI)) { 748 if (EnableFastISelVerbose || EnableFastISelAbort) { 749 cerr << "FastISel missed call: "; 750 BI->dump(); 751 } 752 753 if (BI->getType() != Type::VoidTy) { 754 unsigned &R = FuncInfo->ValueMap[BI]; 755 if (!R) 756 R = FuncInfo->CreateRegForValue(BI); 757 } 758 759 SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); 760 SelectBasicBlock(LLVMBB, BI, next(BI)); 761 // If the instruction was codegen'd with multiple blocks, 762 // inform the FastISel object where to resume inserting. 763 FastIS->setCurrentBlock(BB); 764 continue; 765 } 766 767 // Otherwise, give up on FastISel for the rest of the block. 768 // For now, be a little lenient about non-branch terminators. 769 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 770 if (EnableFastISelVerbose || EnableFastISelAbort) { 771 cerr << "FastISel miss: "; 772 BI->dump(); 773 } 774 if (EnableFastISelAbort) 775 // The "fast" selector couldn't handle something and bailed. 776 // For the purpose of debugging, just abort. 777 llvm_unreachable("FastISel didn't select the entire block"); 778 } 779 break; 780 } 781 } 782 783 // Run SelectionDAG instruction selection on the remainder of the block 784 // not handled by FastISel. If FastISel is not run, this is the entire 785 // block. 786 if (BI != End) { 787 // If FastISel is run and it has known DebugLoc then use it. 788 if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) 789 SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); 790 SelectBasicBlock(LLVMBB, BI, End); 791 } 792 793 FinishBasicBlock(); 794 } 795 796 delete FastIS; 797} 798 799void 800SelectionDAGISel::FinishBasicBlock() { 801 802 DOUT << "Target-post-processed machine code:\n"; 803 DEBUG(BB->dump()); 804 805 DOUT << "Total amount of phi nodes to update: " 806 << SDL->PHINodesToUpdate.size() << "\n"; 807 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) 808 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first 809 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";); 810 811 // Next, now that we know what the last MBB the LLVM BB expanded is, update 812 // PHI nodes in successors. 813 if (SDL->SwitchCases.empty() && 814 SDL->JTCases.empty() && 815 SDL->BitTestCases.empty()) { 816 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 817 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 818 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 819 "This is not a machine PHI node that we are updating!"); 820 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 821 false)); 822 PHI->addOperand(MachineOperand::CreateMBB(BB)); 823 } 824 SDL->PHINodesToUpdate.clear(); 825 return; 826 } 827 828 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) { 829 // Lower header first, if it wasn't already lowered 830 if (!SDL->BitTestCases[i].Emitted) { 831 // Set the current basic block to the mbb we wish to insert the code into 832 BB = SDL->BitTestCases[i].Parent; 833 SDL->setCurrentBasicBlock(BB); 834 // Emit the code 835 SDL->visitBitTestHeader(SDL->BitTestCases[i]); 836 CurDAG->setRoot(SDL->getRoot()); 837 CodeGenAndEmitDAG(); 838 SDL->clear(); 839 } 840 841 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) { 842 // Set the current basic block to the mbb we wish to insert the code into 843 BB = SDL->BitTestCases[i].Cases[j].ThisBB; 844 SDL->setCurrentBasicBlock(BB); 845 // Emit the code 846 if (j+1 != ej) 847 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB, 848 SDL->BitTestCases[i].Reg, 849 SDL->BitTestCases[i].Cases[j]); 850 else 851 SDL->visitBitTestCase(SDL->BitTestCases[i].Default, 852 SDL->BitTestCases[i].Reg, 853 SDL->BitTestCases[i].Cases[j]); 854 855 856 CurDAG->setRoot(SDL->getRoot()); 857 CodeGenAndEmitDAG(); 858 SDL->clear(); 859 } 860 861 // Update PHI Nodes 862 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 863 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 864 MachineBasicBlock *PHIBB = PHI->getParent(); 865 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 866 "This is not a machine PHI node that we are updating!"); 867 // This is "default" BB. We have two jumps to it. From "header" BB and 868 // from last "case" BB. 869 if (PHIBB == SDL->BitTestCases[i].Default) { 870 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 871 false)); 872 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent)); 873 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 874 false)); 875 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases. 876 back().ThisBB)); 877 } 878 // One of "cases" BB. 879 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); 880 j != ej; ++j) { 881 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB; 882 if (cBB->succ_end() != 883 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 884 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 885 false)); 886 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 887 } 888 } 889 } 890 } 891 SDL->BitTestCases.clear(); 892 893 // If the JumpTable record is filled in, then we need to emit a jump table. 894 // Updating the PHI nodes is tricky in this case, since we need to determine 895 // whether the PHI is a successor of the range check MBB or the jump table MBB 896 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) { 897 // Lower header first, if it wasn't already lowered 898 if (!SDL->JTCases[i].first.Emitted) { 899 // Set the current basic block to the mbb we wish to insert the code into 900 BB = SDL->JTCases[i].first.HeaderBB; 901 SDL->setCurrentBasicBlock(BB); 902 // Emit the code 903 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first); 904 CurDAG->setRoot(SDL->getRoot()); 905 CodeGenAndEmitDAG(); 906 SDL->clear(); 907 } 908 909 // Set the current basic block to the mbb we wish to insert the code into 910 BB = SDL->JTCases[i].second.MBB; 911 SDL->setCurrentBasicBlock(BB); 912 // Emit the code 913 SDL->visitJumpTable(SDL->JTCases[i].second); 914 CurDAG->setRoot(SDL->getRoot()); 915 CodeGenAndEmitDAG(); 916 SDL->clear(); 917 918 // Update PHI Nodes 919 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) { 920 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first; 921 MachineBasicBlock *PHIBB = PHI->getParent(); 922 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 923 "This is not a machine PHI node that we are updating!"); 924 // "default" BB. We can go there only from header BB. 925 if (PHIBB == SDL->JTCases[i].second.Default) { 926 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 927 false)); 928 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB)); 929 } 930 // JT BB. Just iterate over successors here 931 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 932 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, 933 false)); 934 PHI->addOperand(MachineOperand::CreateMBB(BB)); 935 } 936 } 937 } 938 SDL->JTCases.clear(); 939 940 // If the switch block involved a branch to one of the actual successors, we 941 // need to update PHI nodes in that block. 942 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) { 943 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first; 944 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 945 "This is not a machine PHI node that we are updating!"); 946 if (BB->isSuccessor(PHI->getParent())) { 947 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second, 948 false)); 949 PHI->addOperand(MachineOperand::CreateMBB(BB)); 950 } 951 } 952 953 // If we generated any switch lowering information, build and codegen any 954 // additional DAGs necessary. 955 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) { 956 // Set the current basic block to the mbb we wish to insert the code into 957 BB = SDL->SwitchCases[i].ThisBB; 958 SDL->setCurrentBasicBlock(BB); 959 960 // Emit the code 961 SDL->visitSwitchCase(SDL->SwitchCases[i]); 962 CurDAG->setRoot(SDL->getRoot()); 963 CodeGenAndEmitDAG(); 964 SDL->clear(); 965 966 // Handle any PHI nodes in successors of this chunk, as if we were coming 967 // from the original BB before switch expansion. Note that PHI nodes can 968 // occur multiple times in PHINodesToUpdate. We have to be very careful to 969 // handle them the right number of times. 970 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 971 for (MachineBasicBlock::iterator Phi = BB->begin(); 972 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 973 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 974 for (unsigned pn = 0; ; ++pn) { 975 assert(pn != SDL->PHINodesToUpdate.size() && 976 "Didn't find PHI entry!"); 977 if (SDL->PHINodesToUpdate[pn].first == Phi) { 978 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn]. 979 second, false)); 980 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB)); 981 break; 982 } 983 } 984 } 985 986 // Don't process RHS if same block as LHS. 987 if (BB == SDL->SwitchCases[i].FalseBB) 988 SDL->SwitchCases[i].FalseBB = 0; 989 990 // If we haven't handled the RHS, do so now. Otherwise, we're done. 991 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB; 992 SDL->SwitchCases[i].FalseBB = 0; 993 } 994 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0); 995 } 996 SDL->SwitchCases.clear(); 997 998 SDL->PHINodesToUpdate.clear(); 999} 1000 1001 1002/// Create the scheduler. If a specific scheduler was specified 1003/// via the SchedulerRegistry, use it, otherwise select the 1004/// one preferred by the target. 1005/// 1006ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1007 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1008 1009 if (!Ctor) { 1010 Ctor = ISHeuristic; 1011 RegisterScheduler::setDefault(Ctor); 1012 } 1013 1014 return Ctor(this, OptLevel); 1015} 1016 1017ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1018 return new ScheduleHazardRecognizer(); 1019} 1020 1021//===----------------------------------------------------------------------===// 1022// Helper functions used by the generated instruction selector. 1023//===----------------------------------------------------------------------===// 1024// Calls to these methods are generated by tblgen. 1025 1026/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1027/// the dag combiner simplified the 255, we still want to match. RHS is the 1028/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1029/// specified in the .td file (e.g. 255). 1030bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1031 int64_t DesiredMaskS) const { 1032 const APInt &ActualMask = RHS->getAPIntValue(); 1033 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1034 1035 // If the actual mask exactly matches, success! 1036 if (ActualMask == DesiredMask) 1037 return true; 1038 1039 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1040 if (ActualMask.intersects(~DesiredMask)) 1041 return false; 1042 1043 // Otherwise, the DAG Combiner may have proven that the value coming in is 1044 // either already zero or is not demanded. Check for known zero input bits. 1045 APInt NeededMask = DesiredMask & ~ActualMask; 1046 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1047 return true; 1048 1049 // TODO: check to see if missing bits are just not demanded. 1050 1051 // Otherwise, this pattern doesn't match. 1052 return false; 1053} 1054 1055/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1056/// the dag combiner simplified the 255, we still want to match. RHS is the 1057/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1058/// specified in the .td file (e.g. 255). 1059bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1060 int64_t DesiredMaskS) const { 1061 const APInt &ActualMask = RHS->getAPIntValue(); 1062 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1063 1064 // If the actual mask exactly matches, success! 1065 if (ActualMask == DesiredMask) 1066 return true; 1067 1068 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1069 if (ActualMask.intersects(~DesiredMask)) 1070 return false; 1071 1072 // Otherwise, the DAG Combiner may have proven that the value coming in is 1073 // either already zero or is not demanded. Check for known zero input bits. 1074 APInt NeededMask = DesiredMask & ~ActualMask; 1075 1076 APInt KnownZero, KnownOne; 1077 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1078 1079 // If all the missing bits in the or are already known to be set, match! 1080 if ((NeededMask & KnownOne) == NeededMask) 1081 return true; 1082 1083 // TODO: check to see if missing bits are just not demanded. 1084 1085 // Otherwise, this pattern doesn't match. 1086 return false; 1087} 1088 1089 1090/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1091/// by tblgen. Others should not call it. 1092void SelectionDAGISel:: 1093SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1094 std::vector<SDValue> InOps; 1095 std::swap(InOps, Ops); 1096 1097 Ops.push_back(InOps[0]); // input chain. 1098 Ops.push_back(InOps[1]); // input asm string. 1099 1100 unsigned i = 2, e = InOps.size(); 1101 if (InOps[e-1].getValueType() == EVT::Flag) 1102 --e; // Don't process a flag operand if it is here. 1103 1104 while (i != e) { 1105 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1106 if ((Flags & 7) != 4 /*MEM*/) { 1107 // Just skip over this operand, copying the operands verbatim. 1108 Ops.insert(Ops.end(), InOps.begin()+i, 1109 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1110 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1111 } else { 1112 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1113 "Memory operand with multiple values?"); 1114 // Otherwise, this is a memory operand. Ask the target to select it. 1115 std::vector<SDValue> SelOps; 1116 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1117 llvm_report_error("Could not match memory address. Inline asm" 1118 " failure!"); 1119 } 1120 1121 // Add this to the output node. 1122 EVT IntPtrTy = TLI.getPointerTy(); 1123 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1124 IntPtrTy)); 1125 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1126 i += 2; 1127 } 1128 } 1129 1130 // Add the flag input back if present. 1131 if (e != InOps.size()) 1132 Ops.push_back(InOps.back()); 1133} 1134 1135/// findFlagUse - Return use of EVT::Flag value produced by the specified 1136/// SDNode. 1137/// 1138static SDNode *findFlagUse(SDNode *N) { 1139 unsigned FlagResNo = N->getNumValues()-1; 1140 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1141 SDUse &Use = I.getUse(); 1142 if (Use.getResNo() == FlagResNo) 1143 return Use.getUser(); 1144 } 1145 return NULL; 1146} 1147 1148/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1149/// This function recursively traverses up the operand chain, ignoring 1150/// certain nodes. 1151static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1152 SDNode *Root, 1153 SmallPtrSet<SDNode*, 16> &Visited) { 1154 if (Use->getNodeId() < Def->getNodeId() || 1155 !Visited.insert(Use)) 1156 return false; 1157 1158 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1159 SDNode *N = Use->getOperand(i).getNode(); 1160 if (N == Def) { 1161 if (Use == ImmedUse || Use == Root) 1162 continue; // We are not looking for immediate use. 1163 assert(N != Root); 1164 return true; 1165 } 1166 1167 // Traverse up the operand chain. 1168 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1169 return true; 1170 } 1171 return false; 1172} 1173 1174/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1175/// be reached. Return true if that's the case. However, ignore direct uses 1176/// by ImmedUse (which would be U in the example illustrated in 1177/// IsLegalAndProfitableToFold) and by Root (which can happen in the store 1178/// case). 1179/// FIXME: to be really generic, we should allow direct use by any node 1180/// that is being folded. But realisticly since we only fold loads which 1181/// have one non-chain use, we only need to watch out for load/op/store 1182/// and load/op/cmp case where the root (store / cmp) may reach the load via 1183/// its chain operand. 1184static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1185 SmallPtrSet<SDNode*, 16> Visited; 1186 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1187} 1188 1189/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 1190/// U can be folded during instruction selection that starts at Root and 1191/// folding N is profitable. 1192bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 1193 SDNode *Root) const { 1194 if (OptLevel == CodeGenOpt::None) return false; 1195 1196 // If Root use can somehow reach N through a path that that doesn't contain 1197 // U then folding N would create a cycle. e.g. In the following 1198 // diagram, Root can reach N through X. If N is folded into into Root, then 1199 // X is both a predecessor and a successor of U. 1200 // 1201 // [N*] // 1202 // ^ ^ // 1203 // / \ // 1204 // [U*] [X]? // 1205 // ^ ^ // 1206 // \ / // 1207 // \ / // 1208 // [Root*] // 1209 // 1210 // * indicates nodes to be folded together. 1211 // 1212 // If Root produces a flag, then it gets (even more) interesting. Since it 1213 // will be "glued" together with its flag use in the scheduler, we need to 1214 // check if it might reach N. 1215 // 1216 // [N*] // 1217 // ^ ^ // 1218 // / \ // 1219 // [U*] [X]? // 1220 // ^ ^ // 1221 // \ \ // 1222 // \ | // 1223 // [Root*] | // 1224 // ^ | // 1225 // f | // 1226 // | / // 1227 // [Y] / // 1228 // ^ / // 1229 // f / // 1230 // | / // 1231 // [FU] // 1232 // 1233 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1234 // (call it Fold), then X is a predecessor of FU and a successor of 1235 // Fold. But since Fold and FU are flagged together, this will create 1236 // a cycle in the scheduling graph. 1237 1238 EVT VT = Root->getValueType(Root->getNumValues()-1); 1239 while (VT == EVT::Flag) { 1240 SDNode *FU = findFlagUse(Root); 1241 if (FU == NULL) 1242 break; 1243 Root = FU; 1244 VT = Root->getValueType(Root->getNumValues()-1); 1245 } 1246 1247 return !isNonImmUse(Root, N, U); 1248} 1249 1250 1251char SelectionDAGISel::ID = 0; 1252