SelectionDAGISel.cpp revision eac59b0c6ce69beed03154b5d3f51a311b6dd9c1
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62static cl::opt<bool> 63EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 64 cl::desc("Enable verbose messages in the \"fast\" " 65 "instruction selector")); 66static cl::opt<bool> 67EnableFastISelAbort("fast-isel-abort", cl::Hidden, 68 cl::desc("Enable abort calls when \"fast\" instruction fails")); 69static cl::opt<bool> 70SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 71 cl::desc("Schedule copies of livein registers"), 72 cl::init(false)); 73 74#ifndef NDEBUG 75static cl::opt<bool> 76ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 77 cl::desc("Pop up a window to show dags before the first " 78 "dag combine pass")); 79static cl::opt<bool> 80ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before legalize types")); 82static cl::opt<bool> 83ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize")); 85static cl::opt<bool> 86ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before the second " 88 "dag combine pass")); 89static cl::opt<bool> 90ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the post legalize types" 92 " dag combine pass")); 93static cl::opt<bool> 94ViewISelDAGs("view-isel-dags", cl::Hidden, 95 cl::desc("Pop up a window to show isel dags as they are selected")); 96static cl::opt<bool> 97ViewSchedDAGs("view-sched-dags", cl::Hidden, 98 cl::desc("Pop up a window to show sched dags as they are processed")); 99static cl::opt<bool> 100ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 101 cl::desc("Pop up a window to show SUnit dags after they are processed")); 102#else 103static const bool ViewDAGCombine1 = false, 104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 105 ViewDAGCombine2 = false, 106 ViewDAGCombineLT = false, 107 ViewISelDAGs = false, ViewSchedDAGs = false, 108 ViewSUnitDAGs = false; 109#endif 110 111//===---------------------------------------------------------------------===// 112/// 113/// RegisterScheduler class - Track the registration of instruction schedulers. 114/// 115//===---------------------------------------------------------------------===// 116MachinePassRegistry RegisterScheduler::Registry; 117 118//===---------------------------------------------------------------------===// 119/// 120/// ISHeuristic command line option for instruction schedulers. 121/// 122//===---------------------------------------------------------------------===// 123static cl::opt<RegisterScheduler::FunctionPassCtor, false, 124 RegisterPassParser<RegisterScheduler> > 125ISHeuristic("pre-RA-sched", 126 cl::init(&createDefaultScheduler), 127 cl::desc("Instruction schedulers available (before register" 128 " allocation):")); 129 130static RegisterScheduler 131defaultListDAGScheduler("default", "Best scheduler for the target", 132 createDefaultScheduler); 133 134namespace llvm { 135 //===--------------------------------------------------------------------===// 136 /// createDefaultScheduler - This creates an instruction scheduler appropriate 137 /// for the target. 138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 139 CodeGenOpt::Level OptLevel) { 140 const TargetLowering &TLI = IS->getTargetLowering(); 141 142 if (OptLevel == CodeGenOpt::None) 143 return createFastDAGScheduler(IS, OptLevel); 144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 145 return createTDListDAGScheduler(IS, OptLevel); 146 assert(TLI.getSchedulingPreference() == 147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 148 return createBURRListDAGScheduler(IS, OptLevel); 149 } 150} 151 152// EmitInstrWithCustomInserter - This method should be implemented by targets 153// that mark instructions with the 'usesCustomInserter' flag. These 154// instructions are special in various ways, which require special support to 155// insert. The specified MachineInstr is created but not inserted into any 156// basic blocks, and this method is called to expand it into a sequence of 157// instructions, potentially also creating new basic blocks and control flow. 158// When new basic blocks are inserted and the edges from MBB to its successors 159// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 160// DenseMap. 161MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 162 MachineBasicBlock *MBB, 163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 164#ifndef NDEBUG 165 dbgs() << "If a target marks an instruction with " 166 "'usesCustomInserter', it must implement " 167 "TargetLowering::EmitInstrWithCustomInserter!"; 168#endif 169 llvm_unreachable(0); 170 return 0; 171} 172 173/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 174/// physical register has only a single copy use, then coalesced the copy 175/// if possible. 176static void EmitLiveInCopy(MachineBasicBlock *MBB, 177 MachineBasicBlock::iterator &InsertPos, 178 unsigned VirtReg, unsigned PhysReg, 179 const TargetRegisterClass *RC, 180 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 181 const MachineRegisterInfo &MRI, 182 const TargetRegisterInfo &TRI, 183 const TargetInstrInfo &TII) { 184 unsigned NumUses = 0; 185 MachineInstr *UseMI = NULL; 186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 187 UE = MRI.use_end(); UI != UE; ++UI) { 188 UseMI = &*UI; 189 if (++NumUses > 1) 190 break; 191 } 192 193 // If the number of uses is not one, or the use is not a move instruction, 194 // don't coalesce. Also, only coalesce away a virtual register to virtual 195 // register copy. 196 bool Coalesced = false; 197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 198 if (NumUses == 1 && 199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 200 TargetRegisterInfo::isVirtualRegister(DstReg)) { 201 VirtReg = DstReg; 202 Coalesced = true; 203 } 204 205 // Now find an ideal location to insert the copy. 206 MachineBasicBlock::iterator Pos = InsertPos; 207 while (Pos != MBB->begin()) { 208 MachineInstr *PrevMI = prior(Pos); 209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 210 // copyRegToReg might emit multiple instructions to do a copy. 211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 213 // This is what the BB looks like right now: 214 // r1024 = mov r0 215 // ... 216 // r1 = mov r1024 217 // 218 // We want to insert "r1025 = mov r1". Inserting this copy below the 219 // move to r1024 makes it impossible for that move to be coalesced. 220 // 221 // r1025 = mov r1 222 // r1024 = mov r0 223 // ... 224 // r1 = mov 1024 225 // r2 = mov 1025 226 break; // Woot! Found a good location. 227 --Pos; 228 } 229 230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 231 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 232 (void) Emitted; 233 234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 235 if (Coalesced) { 236 if (&*InsertPos == UseMI) ++InsertPos; 237 MBB->erase(UseMI); 238 } 239} 240 241/// EmitLiveInCopies - If this is the first basic block in the function, 242/// and if it has live ins that need to be copied into vregs, emit the 243/// copies into the block. 244static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 245 const MachineRegisterInfo &MRI, 246 const TargetRegisterInfo &TRI, 247 const TargetInstrInfo &TII) { 248 if (SchedLiveInCopies) { 249 // Emit the copies at a heuristically-determined location in the block. 250 DenseMap<MachineInstr*, unsigned> CopyRegMap; 251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 253 E = MRI.livein_end(); LI != E; ++LI) 254 if (LI->second) { 255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 257 RC, CopyRegMap, MRI, TRI, TII); 258 } 259 } else { 260 // Emit the copies into the top of the block. 261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 262 E = MRI.livein_end(); LI != E; ++LI) 263 if (LI->second) { 264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 266 LI->second, LI->first, RC, RC); 267 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 268 (void) Emitted; 269 } 270 } 271} 272 273//===----------------------------------------------------------------------===// 274// SelectionDAGISel code 275//===----------------------------------------------------------------------===// 276 277SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 279 FuncInfo(new FunctionLoweringInfo(TLI)), 280 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 282 GFI(), 283 OptLevel(OL), 284 DAGSize(0) 285{} 286 287SelectionDAGISel::~SelectionDAGISel() { 288 delete SDB; 289 delete CurDAG; 290 delete FuncInfo; 291} 292 293unsigned SelectionDAGISel::MakeReg(EVT VT) { 294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 295} 296 297void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 298 AU.addRequired<AliasAnalysis>(); 299 AU.addPreserved<AliasAnalysis>(); 300 AU.addRequired<GCModuleInfo>(); 301 AU.addPreserved<GCModuleInfo>(); 302 AU.addRequired<DwarfWriter>(); 303 AU.addPreserved<DwarfWriter>(); 304 MachineFunctionPass::getAnalysisUsage(AU); 305} 306 307bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 308 Function &Fn = *mf.getFunction(); 309 310 // Do some sanity-checking on the command-line options. 311 assert((!EnableFastISelVerbose || EnableFastISel) && 312 "-fast-isel-verbose requires -fast-isel"); 313 assert((!EnableFastISelAbort || EnableFastISel) && 314 "-fast-isel-abort requires -fast-isel"); 315 316 // Get alias analysis for load/store combining. 317 AA = &getAnalysis<AliasAnalysis>(); 318 319 MF = &mf; 320 const TargetInstrInfo &TII = *TM.getInstrInfo(); 321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 322 323 if (Fn.hasGC()) 324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 325 else 326 GFI = 0; 327 RegInfo = &MF->getRegInfo(); 328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 329 330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 332 CurDAG->init(*MF, MMI, DW); 333 FuncInfo->set(Fn, *MF, EnableFastISel); 334 SDB->init(GFI, *AA); 335 336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 338 // Mark landing pad. 339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 340 341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 342 343 // If the first basic block in the function has live ins that need to be 344 // copied into vregs, emit the copies into the top of the block before 345 // emitting the code for the block. 346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 347 348 // Add function live-ins to entry block live-in set. 349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 350 E = RegInfo->livein_end(); I != E; ++I) 351 MF->begin()->addLiveIn(I->first); 352 353#ifndef NDEBUG 354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 355 "Not all catch info was assigned to a landing pad!"); 356#endif 357 358 FuncInfo->clear(); 359 360 return true; 361} 362 363/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 364/// attached with this instruction. 365static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 366 SelectionDAGBuilder *SDB, 367 FastISel *FastIS, MachineFunction *MF) { 368 if (isa<DbgInfoIntrinsic>(I)) return; 369 370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 371 DILocation DILoc(Dbg); 372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 373 374 SDB->setCurDebugLoc(Loc); 375 376 if (FastIS) 377 FastIS->setCurDebugLoc(Loc); 378 379 // If the function doesn't have a default debug location yet, set 380 // it. This is kind of a hack. 381 if (MF->getDefaultDebugLoc().isUnknown()) 382 MF->setDefaultDebugLoc(Loc); 383 } 384} 385 386/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 387static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 389 if (FastIS) 390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 391} 392 393void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 394 BasicBlock::iterator Begin, 395 BasicBlock::iterator End, 396 bool &HadTailCall) { 397 SDB->setCurrentBasicBlock(BB); 398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 399 400 // Lower all of the non-terminator instructions. If a call is emitted 401 // as a tail call, cease emitting nodes for this block. 402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 404 405 if (!isa<TerminatorInst>(I)) { 406 SDB->visit(*I); 407 408 // Set the current debug location back to "unknown" so that it doesn't 409 // spuriously apply to subsequent instructions. 410 ResetDebugLoc(SDB, 0); 411 } 412 } 413 414 if (!SDB->HasTailCall) { 415 // Ensure that all instructions which are used outside of their defining 416 // blocks are available as virtual registers. Invoke is handled elsewhere. 417 for (BasicBlock::iterator I = Begin; I != End; ++I) 418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 419 SDB->CopyToExportRegsIfNeeded(I); 420 421 // Handle PHI nodes in successor blocks. 422 if (End == LLVMBB->end()) { 423 HandlePHINodesInSuccessorBlocks(LLVMBB); 424 425 // Lower the terminator after the copies are emitted. 426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 427 SDB->visit(*LLVMBB->getTerminator()); 428 ResetDebugLoc(SDB, 0); 429 } 430 } 431 432 // Make sure the root of the DAG is up-to-date. 433 CurDAG->setRoot(SDB->getControlRoot()); 434 435 // Final step, emit the lowered DAG as machine code. 436 CodeGenAndEmitDAG(); 437 HadTailCall = SDB->HasTailCall; 438 SDB->clear(); 439} 440 441namespace { 442/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 443/// nodes from the worklist. 444class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 445 SmallVector<SDNode*, 128> &Worklist; 446public: 447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {} 448 449 virtual void NodeDeleted(SDNode *N, SDNode *E) { 450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 451 Worklist.end()); 452 } 453 454 virtual void NodeUpdated(SDNode *N) { 455 // Ignore updates. 456 } 457}; 458} 459 460/// TrivialTruncElim - Eliminate some trivial nops that can result from 461/// ShrinkDemandedOps: (trunc (ext n)) -> n. 462static bool TrivialTruncElim(SDValue Op, 463 TargetLowering::TargetLoweringOpt &TLO) { 464 SDValue N0 = Op.getOperand(0); 465 EVT VT = Op.getValueType(); 466 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 467 N0.getOpcode() == ISD::SIGN_EXTEND || 468 N0.getOpcode() == ISD::ANY_EXTEND) && 469 N0.getOperand(0).getValueType() == VT) { 470 return TLO.CombineTo(Op, N0.getOperand(0)); 471 } 472 return false; 473} 474 475/// ShrinkDemandedOps - A late transformation pass that shrink expressions 476/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 477/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 478void SelectionDAGISel::ShrinkDemandedOps() { 479 SmallVector<SDNode*, 128> Worklist; 480 481 // Add all the dag nodes to the worklist. 482 Worklist.reserve(CurDAG->allnodes_size()); 483 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 484 E = CurDAG->allnodes_end(); I != E; ++I) 485 Worklist.push_back(I); 486 487 APInt Mask; 488 APInt KnownZero; 489 APInt KnownOne; 490 491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 492 while (!Worklist.empty()) { 493 SDNode *N = Worklist.pop_back_val(); 494 495 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 496 CurDAG->DeleteNode(N); 497 continue; 498 } 499 500 // Run ShrinkDemandedOp on scalar binary operations. 501 if (N->getNumValues() == 1 && 502 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) { 503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 504 APInt Demanded = APInt::getAllOnesValue(BitWidth); 505 APInt KnownZero, KnownOne; 506 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 507 KnownZero, KnownOne, TLO) || 508 (N->getOpcode() == ISD::TRUNCATE && 509 TrivialTruncElim(SDValue(N, 0), TLO))) { 510 // Revisit the node. 511 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 512 Worklist.end()); 513 Worklist.push_back(N); 514 515 // Replace the old value with the new one. 516 DEBUG(errs() << "\nReplacing "; 517 TLO.Old.getNode()->dump(CurDAG); 518 errs() << "\nWith: "; 519 TLO.New.getNode()->dump(CurDAG); 520 errs() << '\n'); 521 522 Worklist.push_back(TLO.New.getNode()); 523 524 SDOPsWorkListRemover DeadNodes(Worklist); 525 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 526 527 if (TLO.Old.getNode()->use_empty()) { 528 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 529 i != e; ++i) { 530 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 531 if (OpNode->hasOneUse()) { 532 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 533 OpNode), Worklist.end()); 534 Worklist.push_back(OpNode); 535 } 536 } 537 538 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 539 TLO.Old.getNode()), Worklist.end()); 540 CurDAG->DeleteNode(TLO.Old.getNode()); 541 } 542 } 543 } 544 } 545} 546 547void SelectionDAGISel::ComputeLiveOutVRegInfo() { 548 SmallPtrSet<SDNode*, 128> VisitedNodes; 549 SmallVector<SDNode*, 128> Worklist; 550 551 Worklist.push_back(CurDAG->getRoot().getNode()); 552 553 APInt Mask; 554 APInt KnownZero; 555 APInt KnownOne; 556 557 do { 558 SDNode *N = Worklist.pop_back_val(); 559 560 // If we've already seen this node, ignore it. 561 if (!VisitedNodes.insert(N)) 562 continue; 563 564 // Otherwise, add all chain operands to the worklist. 565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 566 if (N->getOperand(i).getValueType() == MVT::Other) 567 Worklist.push_back(N->getOperand(i).getNode()); 568 569 // If this is a CopyToReg with a vreg dest, process it. 570 if (N->getOpcode() != ISD::CopyToReg) 571 continue; 572 573 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 574 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 575 continue; 576 577 // Ignore non-scalar or non-integer values. 578 SDValue Src = N->getOperand(2); 579 EVT SrcVT = Src.getValueType(); 580 if (!SrcVT.isInteger() || SrcVT.isVector()) 581 continue; 582 583 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 584 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 585 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 586 587 // Only install this information if it tells us something. 588 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 589 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 590 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 591 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 592 FunctionLoweringInfo::LiveOutInfo &LOI = 593 FuncInfo->LiveOutRegInfo[DestReg]; 594 LOI.NumSignBits = NumSignBits; 595 LOI.KnownOne = KnownOne; 596 LOI.KnownZero = KnownZero; 597 } 598 } while (!Worklist.empty()); 599} 600 601void SelectionDAGISel::CodeGenAndEmitDAG() { 602 std::string GroupName; 603 if (TimePassesIsEnabled) 604 GroupName = "Instruction Selection and Scheduling"; 605 std::string BlockName; 606 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 607 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 608 ViewSUnitDAGs) 609 BlockName = MF->getFunction()->getNameStr() + ":" + 610 BB->getBasicBlock()->getNameStr(); 611 612 DEBUG(dbgs() << "Initial selection DAG:\n"); 613 DEBUG(CurDAG->dump()); 614 615 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 616 617 // Run the DAG combiner in pre-legalize mode. 618 if (TimePassesIsEnabled) { 619 NamedRegionTimer T("DAG Combining 1", GroupName); 620 CurDAG->Combine(Unrestricted, *AA, OptLevel); 621 } else { 622 CurDAG->Combine(Unrestricted, *AA, OptLevel); 623 } 624 625 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 626 DEBUG(CurDAG->dump()); 627 628 // Second step, hack on the DAG until it only uses operations and types that 629 // the target supports. 630 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 631 BlockName); 632 633 bool Changed; 634 if (TimePassesIsEnabled) { 635 NamedRegionTimer T("Type Legalization", GroupName); 636 Changed = CurDAG->LegalizeTypes(); 637 } else { 638 Changed = CurDAG->LegalizeTypes(); 639 } 640 641 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 642 DEBUG(CurDAG->dump()); 643 644 if (Changed) { 645 if (ViewDAGCombineLT) 646 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 647 648 // Run the DAG combiner in post-type-legalize mode. 649 if (TimePassesIsEnabled) { 650 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 651 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 652 } else { 653 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 654 } 655 656 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 657 DEBUG(CurDAG->dump()); 658 } 659 660 if (TimePassesIsEnabled) { 661 NamedRegionTimer T("Vector Legalization", GroupName); 662 Changed = CurDAG->LegalizeVectors(); 663 } else { 664 Changed = CurDAG->LegalizeVectors(); 665 } 666 667 if (Changed) { 668 if (TimePassesIsEnabled) { 669 NamedRegionTimer T("Type Legalization 2", GroupName); 670 CurDAG->LegalizeTypes(); 671 } else { 672 CurDAG->LegalizeTypes(); 673 } 674 675 if (ViewDAGCombineLT) 676 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 677 678 // Run the DAG combiner in post-type-legalize mode. 679 if (TimePassesIsEnabled) { 680 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 681 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 682 } else { 683 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 684 } 685 686 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 687 DEBUG(CurDAG->dump()); 688 } 689 690 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 691 692 if (TimePassesIsEnabled) { 693 NamedRegionTimer T("DAG Legalization", GroupName); 694 CurDAG->Legalize(OptLevel); 695 } else { 696 CurDAG->Legalize(OptLevel); 697 } 698 699 DEBUG(dbgs() << "Legalized selection DAG:\n"); 700 DEBUG(CurDAG->dump()); 701 702 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 703 704 // Run the DAG combiner in post-legalize mode. 705 if (TimePassesIsEnabled) { 706 NamedRegionTimer T("DAG Combining 2", GroupName); 707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 708 } else { 709 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 710 } 711 712 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 713 DEBUG(CurDAG->dump()); 714 715 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 716 717 if (OptLevel != CodeGenOpt::None) { 718 ShrinkDemandedOps(); 719 ComputeLiveOutVRegInfo(); 720 } 721 722 // Third, instruction select all of the operations to machine code, adding the 723 // code to the MachineBasicBlock. 724 if (TimePassesIsEnabled) { 725 NamedRegionTimer T("Instruction Selection", GroupName); 726 InstructionSelect(); 727 } else { 728 InstructionSelect(); 729 } 730 731 DEBUG(dbgs() << "Selected selection DAG:\n"); 732 DEBUG(CurDAG->dump()); 733 734 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 735 736 // Schedule machine code. 737 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 738 if (TimePassesIsEnabled) { 739 NamedRegionTimer T("Instruction Scheduling", GroupName); 740 Scheduler->Run(CurDAG, BB, BB->end()); 741 } else { 742 Scheduler->Run(CurDAG, BB, BB->end()); 743 } 744 745 if (ViewSUnitDAGs) Scheduler->viewGraph(); 746 747 // Emit machine code to BB. This can change 'BB' to the last block being 748 // inserted into. 749 if (TimePassesIsEnabled) { 750 NamedRegionTimer T("Instruction Creation", GroupName); 751 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 752 } else { 753 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 754 } 755 756 // Free the scheduler state. 757 if (TimePassesIsEnabled) { 758 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 759 delete Scheduler; 760 } else { 761 delete Scheduler; 762 } 763 764 DEBUG(dbgs() << "Selected machine code:\n"); 765 DEBUG(BB->dump()); 766} 767 768void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 769 MachineFunction &MF, 770 MachineModuleInfo *MMI, 771 DwarfWriter *DW, 772 const TargetInstrInfo &TII) { 773 // Initialize the Fast-ISel state, if needed. 774 FastISel *FastIS = 0; 775 if (EnableFastISel) 776 FastIS = TLI.createFastISel(MF, MMI, DW, 777 FuncInfo->ValueMap, 778 FuncInfo->MBBMap, 779 FuncInfo->StaticAllocaMap 780#ifndef NDEBUG 781 , FuncInfo->CatchInfoLost 782#endif 783 ); 784 785 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 786 787 // Iterate over all basic blocks in the function. 788 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 789 BasicBlock *LLVMBB = &*I; 790 BB = FuncInfo->MBBMap[LLVMBB]; 791 792 BasicBlock::iterator const Begin = LLVMBB->begin(); 793 BasicBlock::iterator const End = LLVMBB->end(); 794 BasicBlock::iterator BI = Begin; 795 796 // Lower any arguments needed in this block if this is the entry block. 797 bool SuppressFastISel = false; 798 if (LLVMBB == &Fn.getEntryBlock()) { 799 LowerArguments(LLVMBB); 800 801 // If any of the arguments has the byval attribute, forgo 802 // fast-isel in the entry block. 803 if (FastIS) { 804 unsigned j = 1; 805 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 806 I != E; ++I, ++j) 807 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 808 if (EnableFastISelVerbose || EnableFastISelAbort) 809 dbgs() << "FastISel skips entry block due to byval argument\n"; 810 SuppressFastISel = true; 811 break; 812 } 813 } 814 } 815 816 if (MMI && BB->isLandingPad()) { 817 // Add a label to mark the beginning of the landing pad. Deletion of the 818 // landing pad can thus be detected via the MachineModuleInfo. 819 unsigned LabelID = MMI->addLandingPad(BB); 820 821 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 822 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 823 824 // Mark exception register as live in. 825 unsigned Reg = TLI.getExceptionAddressRegister(); 826 if (Reg) BB->addLiveIn(Reg); 827 828 // Mark exception selector register as live in. 829 Reg = TLI.getExceptionSelectorRegister(); 830 if (Reg) BB->addLiveIn(Reg); 831 832 // FIXME: Hack around an exception handling flaw (PR1508): the personality 833 // function and list of typeids logically belong to the invoke (or, if you 834 // like, the basic block containing the invoke), and need to be associated 835 // with it in the dwarf exception handling tables. Currently however the 836 // information is provided by an intrinsic (eh.selector) that can be moved 837 // to unexpected places by the optimizers: if the unwind edge is critical, 838 // then breaking it can result in the intrinsics being in the successor of 839 // the landing pad, not the landing pad itself. This results 840 // in exceptions not being caught because no typeids are associated with 841 // the invoke. This may not be the only way things can go wrong, but it 842 // is the only way we try to work around for the moment. 843 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 844 845 if (Br && Br->isUnconditional()) { // Critical edge? 846 BasicBlock::iterator I, E; 847 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 848 if (isa<EHSelectorInst>(I)) 849 break; 850 851 if (I == E) 852 // No catch info found - try to extract some from the successor. 853 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 854 } 855 } 856 857 // Before doing SelectionDAG ISel, see if FastISel has been requested. 858 if (FastIS && !SuppressFastISel) { 859 // Emit code for any incoming arguments. This must happen before 860 // beginning FastISel on the entry block. 861 if (LLVMBB == &Fn.getEntryBlock()) { 862 CurDAG->setRoot(SDB->getControlRoot()); 863 CodeGenAndEmitDAG(); 864 SDB->clear(); 865 } 866 FastIS->startNewBlock(BB); 867 // Do FastISel on as many instructions as possible. 868 for (; BI != End; ++BI) { 869 // Just before the terminator instruction, insert instructions to 870 // feed PHI nodes in successor blocks. 871 if (isa<TerminatorInst>(BI)) 872 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 873 ResetDebugLoc(SDB, FastIS); 874 if (EnableFastISelVerbose || EnableFastISelAbort) { 875 dbgs() << "FastISel miss: "; 876 BI->dump(); 877 } 878 assert(!EnableFastISelAbort && 879 "FastISel didn't handle a PHI in a successor"); 880 break; 881 } 882 883 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 884 885 // Try to select the instruction with FastISel. 886 if (FastIS->SelectInstruction(BI)) { 887 ResetDebugLoc(SDB, FastIS); 888 continue; 889 } 890 891 // Clear out the debug location so that it doesn't carry over to 892 // unrelated instructions. 893 ResetDebugLoc(SDB, FastIS); 894 895 // Then handle certain instructions as single-LLVM-Instruction blocks. 896 if (isa<CallInst>(BI)) { 897 if (EnableFastISelVerbose || EnableFastISelAbort) { 898 dbgs() << "FastISel missed call: "; 899 BI->dump(); 900 } 901 902 if (!BI->getType()->isVoidTy()) { 903 unsigned &R = FuncInfo->ValueMap[BI]; 904 if (!R) 905 R = FuncInfo->CreateRegForValue(BI); 906 } 907 908 bool HadTailCall = false; 909 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 910 911 // If the call was emitted as a tail call, we're done with the block. 912 if (HadTailCall) { 913 BI = End; 914 break; 915 } 916 917 // If the instruction was codegen'd with multiple blocks, 918 // inform the FastISel object where to resume inserting. 919 FastIS->setCurrentBlock(BB); 920 continue; 921 } 922 923 // Otherwise, give up on FastISel for the rest of the block. 924 // For now, be a little lenient about non-branch terminators. 925 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 926 if (EnableFastISelVerbose || EnableFastISelAbort) { 927 dbgs() << "FastISel miss: "; 928 BI->dump(); 929 } 930 if (EnableFastISelAbort) 931 // The "fast" selector couldn't handle something and bailed. 932 // For the purpose of debugging, just abort. 933 llvm_unreachable("FastISel didn't select the entire block"); 934 } 935 break; 936 } 937 } 938 939 // Run SelectionDAG instruction selection on the remainder of the block 940 // not handled by FastISel. If FastISel is not run, this is the entire 941 // block. 942 if (BI != End) { 943 bool HadTailCall; 944 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 945 } 946 947 FinishBasicBlock(); 948 } 949 950 delete FastIS; 951} 952 953void 954SelectionDAGISel::FinishBasicBlock() { 955 956 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 957 DEBUG(BB->dump()); 958 959 DEBUG(dbgs() << "Total amount of phi nodes to update: " 960 << SDB->PHINodesToUpdate.size() << "\n"); 961 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 962 dbgs() << "Node " << i << " : (" 963 << SDB->PHINodesToUpdate[i].first 964 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 965 966 // Next, now that we know what the last MBB the LLVM BB expanded is, update 967 // PHI nodes in successors. 968 if (SDB->SwitchCases.empty() && 969 SDB->JTCases.empty() && 970 SDB->BitTestCases.empty()) { 971 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 972 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 973 assert(PHI->isPHI() && 974 "This is not a machine PHI node that we are updating!"); 975 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 976 false)); 977 PHI->addOperand(MachineOperand::CreateMBB(BB)); 978 } 979 SDB->PHINodesToUpdate.clear(); 980 return; 981 } 982 983 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 984 // Lower header first, if it wasn't already lowered 985 if (!SDB->BitTestCases[i].Emitted) { 986 // Set the current basic block to the mbb we wish to insert the code into 987 BB = SDB->BitTestCases[i].Parent; 988 SDB->setCurrentBasicBlock(BB); 989 // Emit the code 990 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 991 CurDAG->setRoot(SDB->getRoot()); 992 CodeGenAndEmitDAG(); 993 SDB->clear(); 994 } 995 996 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 997 // Set the current basic block to the mbb we wish to insert the code into 998 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 999 SDB->setCurrentBasicBlock(BB); 1000 // Emit the code 1001 if (j+1 != ej) 1002 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1003 SDB->BitTestCases[i].Reg, 1004 SDB->BitTestCases[i].Cases[j]); 1005 else 1006 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1007 SDB->BitTestCases[i].Reg, 1008 SDB->BitTestCases[i].Cases[j]); 1009 1010 1011 CurDAG->setRoot(SDB->getRoot()); 1012 CodeGenAndEmitDAG(); 1013 SDB->clear(); 1014 } 1015 1016 // Update PHI Nodes 1017 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1018 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1019 MachineBasicBlock *PHIBB = PHI->getParent(); 1020 assert(PHI->isPHI() && 1021 "This is not a machine PHI node that we are updating!"); 1022 // This is "default" BB. We have two jumps to it. From "header" BB and 1023 // from last "case" BB. 1024 if (PHIBB == SDB->BitTestCases[i].Default) { 1025 PHI->addOperand(MachineOperand:: 1026 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1027 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1028 PHI->addOperand(MachineOperand:: 1029 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1030 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1031 back().ThisBB)); 1032 } 1033 // One of "cases" BB. 1034 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1035 j != ej; ++j) { 1036 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1037 if (cBB->isSuccessor(PHIBB)) { 1038 PHI->addOperand(MachineOperand:: 1039 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1040 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1041 } 1042 } 1043 } 1044 } 1045 SDB->BitTestCases.clear(); 1046 1047 // If the JumpTable record is filled in, then we need to emit a jump table. 1048 // Updating the PHI nodes is tricky in this case, since we need to determine 1049 // whether the PHI is a successor of the range check MBB or the jump table MBB 1050 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1051 // Lower header first, if it wasn't already lowered 1052 if (!SDB->JTCases[i].first.Emitted) { 1053 // Set the current basic block to the mbb we wish to insert the code into 1054 BB = SDB->JTCases[i].first.HeaderBB; 1055 SDB->setCurrentBasicBlock(BB); 1056 // Emit the code 1057 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1058 CurDAG->setRoot(SDB->getRoot()); 1059 CodeGenAndEmitDAG(); 1060 SDB->clear(); 1061 } 1062 1063 // Set the current basic block to the mbb we wish to insert the code into 1064 BB = SDB->JTCases[i].second.MBB; 1065 SDB->setCurrentBasicBlock(BB); 1066 // Emit the code 1067 SDB->visitJumpTable(SDB->JTCases[i].second); 1068 CurDAG->setRoot(SDB->getRoot()); 1069 CodeGenAndEmitDAG(); 1070 SDB->clear(); 1071 1072 // Update PHI Nodes 1073 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1074 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1075 MachineBasicBlock *PHIBB = PHI->getParent(); 1076 assert(PHI->isPHI() && 1077 "This is not a machine PHI node that we are updating!"); 1078 // "default" BB. We can go there only from header BB. 1079 if (PHIBB == SDB->JTCases[i].second.Default) { 1080 PHI->addOperand 1081 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1082 PHI->addOperand 1083 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1084 } 1085 // JT BB. Just iterate over successors here 1086 if (BB->isSuccessor(PHIBB)) { 1087 PHI->addOperand 1088 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1089 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1090 } 1091 } 1092 } 1093 SDB->JTCases.clear(); 1094 1095 // If the switch block involved a branch to one of the actual successors, we 1096 // need to update PHI nodes in that block. 1097 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1098 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1099 assert(PHI->isPHI() && 1100 "This is not a machine PHI node that we are updating!"); 1101 if (BB->isSuccessor(PHI->getParent())) { 1102 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1103 false)); 1104 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1105 } 1106 } 1107 1108 // If we generated any switch lowering information, build and codegen any 1109 // additional DAGs necessary. 1110 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1111 // Set the current basic block to the mbb we wish to insert the code into 1112 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1113 SDB->setCurrentBasicBlock(BB); 1114 1115 // Emit the code 1116 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1117 CurDAG->setRoot(SDB->getRoot()); 1118 CodeGenAndEmitDAG(); 1119 1120 // Handle any PHI nodes in successors of this chunk, as if we were coming 1121 // from the original BB before switch expansion. Note that PHI nodes can 1122 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1123 // handle them the right number of times. 1124 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1125 // If new BB's are created during scheduling, the edges may have been 1126 // updated. That is, the edge from ThisBB to BB may have been split and 1127 // BB's predecessor is now another block. 1128 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1129 SDB->EdgeMapping.find(BB); 1130 if (EI != SDB->EdgeMapping.end()) 1131 ThisBB = EI->second; 1132 1133 // BB may have been removed from the CFG if a branch was constant folded. 1134 if (ThisBB->isSuccessor(BB)) { 1135 for (MachineBasicBlock::iterator Phi = BB->begin(); 1136 Phi != BB->end() && Phi->isPHI(); 1137 ++Phi) { 1138 // This value for this PHI node is recorded in PHINodesToUpdate. 1139 for (unsigned pn = 0; ; ++pn) { 1140 assert(pn != SDB->PHINodesToUpdate.size() && 1141 "Didn't find PHI entry!"); 1142 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1143 Phi->addOperand(MachineOperand:: 1144 CreateReg(SDB->PHINodesToUpdate[pn].second, 1145 false)); 1146 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1147 break; 1148 } 1149 } 1150 } 1151 } 1152 1153 // Don't process RHS if same block as LHS. 1154 if (BB == SDB->SwitchCases[i].FalseBB) 1155 SDB->SwitchCases[i].FalseBB = 0; 1156 1157 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1158 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1159 SDB->SwitchCases[i].FalseBB = 0; 1160 } 1161 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1162 SDB->clear(); 1163 } 1164 SDB->SwitchCases.clear(); 1165 1166 SDB->PHINodesToUpdate.clear(); 1167} 1168 1169 1170/// Create the scheduler. If a specific scheduler was specified 1171/// via the SchedulerRegistry, use it, otherwise select the 1172/// one preferred by the target. 1173/// 1174ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1175 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1176 1177 if (!Ctor) { 1178 Ctor = ISHeuristic; 1179 RegisterScheduler::setDefault(Ctor); 1180 } 1181 1182 return Ctor(this, OptLevel); 1183} 1184 1185ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1186 return new ScheduleHazardRecognizer(); 1187} 1188 1189//===----------------------------------------------------------------------===// 1190// Helper functions used by the generated instruction selector. 1191//===----------------------------------------------------------------------===// 1192// Calls to these methods are generated by tblgen. 1193 1194/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1195/// the dag combiner simplified the 255, we still want to match. RHS is the 1196/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1197/// specified in the .td file (e.g. 255). 1198bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1199 int64_t DesiredMaskS) const { 1200 const APInt &ActualMask = RHS->getAPIntValue(); 1201 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1202 1203 // If the actual mask exactly matches, success! 1204 if (ActualMask == DesiredMask) 1205 return true; 1206 1207 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1208 if (ActualMask.intersects(~DesiredMask)) 1209 return false; 1210 1211 // Otherwise, the DAG Combiner may have proven that the value coming in is 1212 // either already zero or is not demanded. Check for known zero input bits. 1213 APInt NeededMask = DesiredMask & ~ActualMask; 1214 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1215 return true; 1216 1217 // TODO: check to see if missing bits are just not demanded. 1218 1219 // Otherwise, this pattern doesn't match. 1220 return false; 1221} 1222 1223/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1224/// the dag combiner simplified the 255, we still want to match. RHS is the 1225/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1226/// specified in the .td file (e.g. 255). 1227bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1228 int64_t DesiredMaskS) const { 1229 const APInt &ActualMask = RHS->getAPIntValue(); 1230 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1231 1232 // If the actual mask exactly matches, success! 1233 if (ActualMask == DesiredMask) 1234 return true; 1235 1236 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1237 if (ActualMask.intersects(~DesiredMask)) 1238 return false; 1239 1240 // Otherwise, the DAG Combiner may have proven that the value coming in is 1241 // either already zero or is not demanded. Check for known zero input bits. 1242 APInt NeededMask = DesiredMask & ~ActualMask; 1243 1244 APInt KnownZero, KnownOne; 1245 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1246 1247 // If all the missing bits in the or are already known to be set, match! 1248 if ((NeededMask & KnownOne) == NeededMask) 1249 return true; 1250 1251 // TODO: check to see if missing bits are just not demanded. 1252 1253 // Otherwise, this pattern doesn't match. 1254 return false; 1255} 1256 1257 1258/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1259/// by tblgen. Others should not call it. 1260void SelectionDAGISel:: 1261SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1262 std::vector<SDValue> InOps; 1263 std::swap(InOps, Ops); 1264 1265 Ops.push_back(InOps[0]); // input chain. 1266 Ops.push_back(InOps[1]); // input asm string. 1267 1268 unsigned i = 2, e = InOps.size(); 1269 if (InOps[e-1].getValueType() == MVT::Flag) 1270 --e; // Don't process a flag operand if it is here. 1271 1272 while (i != e) { 1273 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1274 if ((Flags & 7) != 4 /*MEM*/) { 1275 // Just skip over this operand, copying the operands verbatim. 1276 Ops.insert(Ops.end(), InOps.begin()+i, 1277 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1278 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1279 } else { 1280 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1281 "Memory operand with multiple values?"); 1282 // Otherwise, this is a memory operand. Ask the target to select it. 1283 std::vector<SDValue> SelOps; 1284 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1285 llvm_report_error("Could not match memory address. Inline asm" 1286 " failure!"); 1287 } 1288 1289 // Add this to the output node. 1290 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1291 MVT::i32)); 1292 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1293 i += 2; 1294 } 1295 } 1296 1297 // Add the flag input back if present. 1298 if (e != InOps.size()) 1299 Ops.push_back(InOps.back()); 1300} 1301 1302/// findFlagUse - Return use of EVT::Flag value produced by the specified 1303/// SDNode. 1304/// 1305static SDNode *findFlagUse(SDNode *N) { 1306 unsigned FlagResNo = N->getNumValues()-1; 1307 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1308 SDUse &Use = I.getUse(); 1309 if (Use.getResNo() == FlagResNo) 1310 return Use.getUser(); 1311 } 1312 return NULL; 1313} 1314 1315/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1316/// This function recursively traverses up the operand chain, ignoring 1317/// certain nodes. 1318static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1319 SDNode *Root, 1320 SmallPtrSet<SDNode*, 16> &Visited) { 1321 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1322 // greater than all of its (recursive) operands. If we scan to a point where 1323 // 'use' is smaller than the node we're scanning for, then we know we will 1324 // never find it. 1325 // 1326 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1327 // happen because we scan down to newly selected nodes in the case of flag 1328 // uses. 1329 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1330 return false; 1331 1332 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1333 // won't fail if we scan it again. 1334 if (!Visited.insert(Use)) 1335 return false; 1336 1337 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1338 SDNode *N = Use->getOperand(i).getNode(); 1339 if (N == Def) { 1340 if (Use == ImmedUse || Use == Root) 1341 continue; // We are not looking for immediate use. 1342 assert(N != Root); 1343 return true; 1344 } 1345 1346 // Traverse up the operand chain. 1347 if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) 1348 return true; 1349 } 1350 return false; 1351} 1352 1353/// isNonImmUse - Start searching from Root up the DAG to check is Def can 1354/// be reached. Return true if that's the case. However, ignore direct uses 1355/// by ImmedUse (which would be U in the example illustrated in 1356/// IsLegalToFold) and by Root (which can happen in the store case). 1357/// FIXME: to be really generic, we should allow direct use by any node 1358/// that is being folded. But realisticly since we only fold loads which 1359/// have one non-chain use, we only need to watch out for load/op/store 1360/// and load/op/cmp case where the root (store / cmp) may reach the load via 1361/// its chain operand. 1362static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { 1363 SmallPtrSet<SDNode*, 16> Visited; 1364 return findNonImmUse(Root, Def, ImmedUse, Root, Visited); 1365} 1366 1367/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1368/// operand node N of U during instruction selection that starts at Root. 1369bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1370 SDNode *Root) const { 1371 if (OptLevel == CodeGenOpt::None) return false; 1372 return N.hasOneUse(); 1373} 1374 1375/// IsLegalToFold - Returns true if the specific operand node N of 1376/// U can be folded during instruction selection that starts at Root. 1377bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const { 1378 if (OptLevel == CodeGenOpt::None) return false; 1379 1380 // If Root use can somehow reach N through a path that that doesn't contain 1381 // U then folding N would create a cycle. e.g. In the following 1382 // diagram, Root can reach N through X. If N is folded into into Root, then 1383 // X is both a predecessor and a successor of U. 1384 // 1385 // [N*] // 1386 // ^ ^ // 1387 // / \ // 1388 // [U*] [X]? // 1389 // ^ ^ // 1390 // \ / // 1391 // \ / // 1392 // [Root*] // 1393 // 1394 // * indicates nodes to be folded together. 1395 // 1396 // If Root produces a flag, then it gets (even more) interesting. Since it 1397 // will be "glued" together with its flag use in the scheduler, we need to 1398 // check if it might reach N. 1399 // 1400 // [N*] // 1401 // ^ ^ // 1402 // / \ // 1403 // [U*] [X]? // 1404 // ^ ^ // 1405 // \ \ // 1406 // \ | // 1407 // [Root*] | // 1408 // ^ | // 1409 // f | // 1410 // | / // 1411 // [Y] / // 1412 // ^ / // 1413 // f / // 1414 // | / // 1415 // [FU] // 1416 // 1417 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1418 // (call it Fold), then X is a predecessor of FU and a successor of 1419 // Fold. But since Fold and FU are flagged together, this will create 1420 // a cycle in the scheduling graph. 1421 1422 EVT VT = Root->getValueType(Root->getNumValues()-1); 1423 while (VT == MVT::Flag) { 1424 SDNode *FU = findFlagUse(Root); 1425 if (FU == NULL) 1426 break; 1427 Root = FU; 1428 VT = Root->getValueType(Root->getNumValues()-1); 1429 } 1430 1431 return !isNonImmUse(Root, N.getNode(), U); 1432} 1433 1434SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1435 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1436 SelectInlineAsmMemoryOperands(Ops); 1437 1438 std::vector<EVT> VTs; 1439 VTs.push_back(MVT::Other); 1440 VTs.push_back(MVT::Flag); 1441 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1442 VTs, &Ops[0], Ops.size()); 1443 return New.getNode(); 1444} 1445 1446SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1447 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1448} 1449 1450SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1451 SDValue Chain = N->getOperand(0); 1452 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1453 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1454 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL, 1455 MVT::Other, Tmp, Chain); 1456} 1457 1458 1459/// ChainNotReachable - Returns true if Chain does not reach Op. 1460static bool ChainNotReachable(SDNode *Chain, SDNode *Op) { 1461 if (Chain->getOpcode() == ISD::EntryToken) 1462 return true; 1463 if (Chain->getOpcode() == ISD::TokenFactor) 1464 return false; 1465 if (Chain->getNumOperands() > 0) { 1466 SDValue C0 = Chain->getOperand(0); 1467 if (C0.getValueType() == MVT::Other) 1468 return C0.getNode() != Op && ChainNotReachable(C0.getNode(), Op); 1469 } 1470 return true; 1471} 1472 1473/// IsChainCompatible - Returns true if Chain is Op or Chain does not reach Op. 1474/// This is used to ensure that there are no nodes trapped between Chain, which 1475/// is the first chain node discovered in a pattern and Op, a later node, that 1476/// will not be selected into the pattern. 1477static bool IsChainCompatible(SDNode *Chain, SDNode *Op) { 1478 return Chain == Op || ChainNotReachable(Chain, Op); 1479} 1480 1481 1482/// GetVBR - decode a vbr encoding whose top bit is set. 1483ALWAYS_INLINE static uint64_t 1484GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1485 assert(Val >= 128 && "Not a VBR"); 1486 Val &= 127; // Remove first vbr bit. 1487 1488 unsigned Shift = 7; 1489 uint64_t NextBits; 1490 do { 1491 NextBits = MatcherTable[Idx++]; 1492 Val |= (NextBits&127) << Shift; 1493 Shift += 7; 1494 } while (NextBits & 128); 1495 1496 return Val; 1497} 1498 1499 1500/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1501/// interior flag and chain results to use the new flag and chain results. 1502static void UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1503 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1504 SDValue InputFlag, 1505 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1506 bool isMorphNodeTo, SelectionDAG *CurDAG) { 1507 // Now that all the normal results are replaced, we replace the chain and 1508 // flag results if present. 1509 if (!ChainNodesMatched.empty()) { 1510 assert(InputChain.getNode() != 0 && 1511 "Matched input chains but didn't produce a chain"); 1512 // Loop over all of the nodes we matched that produced a chain result. 1513 // Replace all the chain results with the final chain we ended up with. 1514 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1515 SDNode *ChainNode = ChainNodesMatched[i]; 1516 1517 // Don't replace the results of the root node if we're doing a 1518 // MorphNodeTo. 1519 if (ChainNode == NodeToMatch && isMorphNodeTo) 1520 continue; 1521 1522 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1523 if (ChainVal.getValueType() == MVT::Flag) 1524 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1525 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1526 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1527 } 1528 } 1529 1530 // If the result produces a flag, update any flag results in the matched 1531 // pattern with the flag result. 1532 if (InputFlag.getNode() != 0) { 1533 // Handle any interior nodes explicitly marked. 1534 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1535 SDNode *FRN = FlagResultNodesMatched[i]; 1536 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1537 "Doesn't have a flag result"); 1538 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1539 InputFlag); 1540 } 1541 } 1542 1543 DEBUG(errs() << "ISEL: Match complete!\n"); 1544} 1545 1546/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1547/// operation for when the pattern matched multiple nodes with chains. 1548static SDValue 1549HandleMergeInputChains(const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1550 SelectionDAG *CurDAG) { 1551 assert(ChainNodesMatched.size() > 1 && 1552 "Should only happen for multi chain node case"); 1553 1554 // Walk all the chained nodes, adding the input chains if they are not in 1555 // ChainedNodes (and this, not in the matched pattern). This is an N^2 1556 // algorithm, but # chains is usually 2 here, at most 3 for MSP430. 1557 SmallVector<SDValue, 3> InputChains; 1558 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1559 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1560 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1561 bool Invalid = false; 1562 for (unsigned j = 0; j != e; ++j) 1563 Invalid |= ChainNodesMatched[j] == InChain.getNode(); 1564 if (!Invalid) 1565 InputChains.push_back(InChain); 1566 } 1567 1568 SDValue Res; 1569 if (InputChains.size() == 1) 1570 return InputChains[0]; 1571 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1572 MVT::Other, &InputChains[0], InputChains.size()); 1573} 1574 1575struct MatchScope { 1576 /// FailIndex - If this match fails, this is the index to continue with. 1577 unsigned FailIndex; 1578 1579 /// NodeStack - The node stack when the scope was formed. 1580 SmallVector<SDValue, 4> NodeStack; 1581 1582 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1583 unsigned NumRecordedNodes; 1584 1585 /// NumMatchedMemRefs - The number of matched memref entries. 1586 unsigned NumMatchedMemRefs; 1587 1588 /// InputChain/InputFlag - The current chain/flag 1589 SDValue InputChain, InputFlag; 1590 1591 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1592 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1593}; 1594 1595SDNode *SelectionDAGISel:: 1596SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1597 unsigned TableSize) { 1598 // FIXME: Should these even be selected? Handle these cases in the caller? 1599 switch (NodeToMatch->getOpcode()) { 1600 default: 1601 break; 1602 case ISD::EntryToken: // These nodes remain the same. 1603 case ISD::BasicBlock: 1604 case ISD::Register: 1605 case ISD::HANDLENODE: 1606 case ISD::TargetConstant: 1607 case ISD::TargetConstantFP: 1608 case ISD::TargetConstantPool: 1609 case ISD::TargetFrameIndex: 1610 case ISD::TargetExternalSymbol: 1611 case ISD::TargetBlockAddress: 1612 case ISD::TargetJumpTable: 1613 case ISD::TargetGlobalTLSAddress: 1614 case ISD::TargetGlobalAddress: 1615 case ISD::TokenFactor: 1616 case ISD::CopyFromReg: 1617 case ISD::CopyToReg: 1618 return 0; 1619 case ISD::AssertSext: 1620 case ISD::AssertZext: 1621 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1622 NodeToMatch->getOperand(0)); 1623 return 0; 1624 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1625 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch); 1626 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1627 } 1628 1629 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1630 1631 // Set up the node stack with NodeToMatch as the only node on the stack. 1632 SmallVector<SDValue, 8> NodeStack; 1633 SDValue N = SDValue(NodeToMatch, 0); 1634 NodeStack.push_back(N); 1635 1636 // MatchScopes - Scopes used when matching, if a match failure happens, this 1637 // indicates where to continue checking. 1638 SmallVector<MatchScope, 8> MatchScopes; 1639 1640 // RecordedNodes - This is the set of nodes that have been recorded by the 1641 // state machine. 1642 SmallVector<SDValue, 8> RecordedNodes; 1643 1644 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1645 // pattern. 1646 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1647 1648 // These are the current input chain and flag for use when generating nodes. 1649 // Various Emit operations change these. For example, emitting a copytoreg 1650 // uses and updates these. 1651 SDValue InputChain, InputFlag; 1652 1653 // ChainNodesMatched - If a pattern matches nodes that have input/output 1654 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1655 // which ones they are. The result is captured into this list so that we can 1656 // update the chain results when the pattern is complete. 1657 SmallVector<SDNode*, 3> ChainNodesMatched; 1658 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1659 1660 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1661 NodeToMatch->dump(CurDAG); 1662 errs() << '\n'); 1663 1664 // Determine where to start the interpreter. Normally we start at opcode #0, 1665 // but if the state machine starts with an OPC_SwitchOpcode, then we 1666 // accelerate the first lookup (which is guaranteed to be hot) with the 1667 // OpcodeOffset table. 1668 unsigned MatcherIndex = 0; 1669 1670 if (!OpcodeOffset.empty()) { 1671 // Already computed the OpcodeOffset table, just index into it. 1672 if (N.getOpcode() < OpcodeOffset.size()) 1673 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1674 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1675 1676 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1677 // Otherwise, the table isn't computed, but the state machine does start 1678 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1679 // is the first time we're selecting an instruction. 1680 unsigned Idx = 1; 1681 while (1) { 1682 // Get the size of this case. 1683 unsigned CaseSize = MatcherTable[Idx++]; 1684 if (CaseSize & 128) 1685 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1686 if (CaseSize == 0) break; 1687 1688 // Get the opcode, add the index to the table. 1689 unsigned Opc = MatcherTable[Idx++]; 1690 if (Opc >= OpcodeOffset.size()) 1691 OpcodeOffset.resize((Opc+1)*2); 1692 OpcodeOffset[Opc] = Idx; 1693 Idx += CaseSize; 1694 } 1695 1696 // Okay, do the lookup for the first opcode. 1697 if (N.getOpcode() < OpcodeOffset.size()) 1698 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1699 } 1700 1701 while (1) { 1702 assert(MatcherIndex < TableSize && "Invalid index"); 1703 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 1704 switch (Opcode) { 1705 case OPC_Scope: { 1706 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 1707 if (NumToSkip & 128) 1708 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 1709 assert(NumToSkip != 0 && 1710 "First entry of OPC_Scope shouldn't be 0, scope has no children?"); 1711 1712 // Push a MatchScope which indicates where to go if the first child fails 1713 // to match. 1714 MatchScope NewEntry; 1715 NewEntry.FailIndex = MatcherIndex+NumToSkip; 1716 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 1717 NewEntry.NumRecordedNodes = RecordedNodes.size(); 1718 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 1719 NewEntry.InputChain = InputChain; 1720 NewEntry.InputFlag = InputFlag; 1721 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 1722 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 1723 MatchScopes.push_back(NewEntry); 1724 continue; 1725 } 1726 case OPC_RecordNode: 1727 // Remember this node, it may end up being an operand in the pattern. 1728 RecordedNodes.push_back(N); 1729 continue; 1730 1731 case OPC_RecordChild0: case OPC_RecordChild1: 1732 case OPC_RecordChild2: case OPC_RecordChild3: 1733 case OPC_RecordChild4: case OPC_RecordChild5: 1734 case OPC_RecordChild6: case OPC_RecordChild7: { 1735 unsigned ChildNo = Opcode-OPC_RecordChild0; 1736 if (ChildNo >= N.getNumOperands()) 1737 break; // Match fails if out of range child #. 1738 1739 RecordedNodes.push_back(N->getOperand(ChildNo)); 1740 continue; 1741 } 1742 case OPC_RecordMemRef: 1743 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 1744 continue; 1745 1746 case OPC_CaptureFlagInput: 1747 // If the current node has an input flag, capture it in InputFlag. 1748 if (N->getNumOperands() != 0 && 1749 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 1750 InputFlag = N->getOperand(N->getNumOperands()-1); 1751 continue; 1752 1753 case OPC_MoveChild: { 1754 unsigned ChildNo = MatcherTable[MatcherIndex++]; 1755 if (ChildNo >= N.getNumOperands()) 1756 break; // Match fails if out of range child #. 1757 N = N.getOperand(ChildNo); 1758 NodeStack.push_back(N); 1759 continue; 1760 } 1761 1762 case OPC_MoveParent: 1763 // Pop the current node off the NodeStack. 1764 NodeStack.pop_back(); 1765 assert(!NodeStack.empty() && "Node stack imbalance!"); 1766 N = NodeStack.back(); 1767 continue; 1768 1769 case OPC_CheckSame: { 1770 // Accept if it is exactly the same as a previously recorded node. 1771 unsigned RecNo = MatcherTable[MatcherIndex++]; 1772 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1773 if (N != RecordedNodes[RecNo]) break; 1774 continue; 1775 } 1776 case OPC_CheckPatternPredicate: 1777 if (!CheckPatternPredicate(MatcherTable[MatcherIndex++])) break; 1778 continue; 1779 case OPC_CheckPredicate: 1780 if (!CheckNodePredicate(N.getNode(), MatcherTable[MatcherIndex++])) break; 1781 continue; 1782 case OPC_CheckComplexPat: 1783 if (!CheckComplexPattern(NodeToMatch, N, 1784 MatcherTable[MatcherIndex++], RecordedNodes)) 1785 break; 1786 continue; 1787 case OPC_CheckOpcode: 1788 if (N->getOpcode() != MatcherTable[MatcherIndex++]) break; 1789 continue; 1790 1791 case OPC_SwitchOpcode: { 1792 unsigned CurNodeOpcode = N.getOpcode(); 1793 1794 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 1795 1796 unsigned CaseSize; 1797 while (1) { 1798 // Get the size of this case. 1799 CaseSize = MatcherTable[MatcherIndex++]; 1800 if (CaseSize & 128) 1801 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 1802 if (CaseSize == 0) break; 1803 1804 // If the opcode matches, then we will execute this case. 1805 if (CurNodeOpcode == MatcherTable[MatcherIndex++]) 1806 break; 1807 1808 // Otherwise, skip over this case. 1809 MatcherIndex += CaseSize; 1810 } 1811 1812 // If we failed to match, bail out. 1813 if (CaseSize == 0) break; 1814 1815 // Otherwise, execute the case we found. 1816 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 1817 << " to " << MatcherIndex << "\n"); 1818 continue; 1819 } 1820 1821 case OPC_CheckType: { 1822 MVT::SimpleValueType VT = 1823 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1824 if (N.getValueType() != VT) { 1825 // Handle the case when VT is iPTR. 1826 if (VT != MVT::iPTR || N.getValueType() != TLI.getPointerTy()) 1827 break; 1828 } 1829 continue; 1830 } 1831 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 1832 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 1833 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 1834 case OPC_CheckChild6Type: case OPC_CheckChild7Type: { 1835 unsigned ChildNo = Opcode-OPC_CheckChild0Type; 1836 if (ChildNo >= N.getNumOperands()) 1837 break; // Match fails if out of range child #. 1838 1839 MVT::SimpleValueType VT = 1840 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1841 EVT ChildVT = N.getOperand(ChildNo).getValueType(); 1842 if (ChildVT != VT) { 1843 // Handle the case when VT is iPTR. 1844 if (VT != MVT::iPTR || ChildVT != TLI.getPointerTy()) 1845 break; 1846 } 1847 continue; 1848 } 1849 case OPC_CheckCondCode: 1850 if (cast<CondCodeSDNode>(N)->get() != 1851 (ISD::CondCode)MatcherTable[MatcherIndex++]) break; 1852 continue; 1853 case OPC_CheckValueType: { 1854 MVT::SimpleValueType VT = 1855 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1856 if (cast<VTSDNode>(N)->getVT() != VT) { 1857 // Handle the case when VT is iPTR. 1858 if (VT != MVT::iPTR || cast<VTSDNode>(N)->getVT() != TLI.getPointerTy()) 1859 break; 1860 } 1861 continue; 1862 } 1863 case OPC_CheckInteger: { 1864 int64_t Val = MatcherTable[MatcherIndex++]; 1865 if (Val & 128) 1866 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1867 1868 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1869 if (C == 0 || C->getSExtValue() != Val) 1870 break; 1871 continue; 1872 } 1873 case OPC_CheckAndImm: { 1874 int64_t Val = MatcherTable[MatcherIndex++]; 1875 if (Val & 128) 1876 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1877 1878 if (N->getOpcode() != ISD::AND) break; 1879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1880 if (C == 0 || !CheckAndMask(N.getOperand(0), C, Val)) 1881 break; 1882 continue; 1883 } 1884 case OPC_CheckOrImm: { 1885 int64_t Val = MatcherTable[MatcherIndex++]; 1886 if (Val & 128) 1887 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1888 1889 if (N->getOpcode() != ISD::OR) break; 1890 1891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1892 if (C == 0 || !CheckOrMask(N.getOperand(0), C, Val)) 1893 break; 1894 continue; 1895 } 1896 1897 case OPC_CheckFoldableChainNode: { 1898 assert(NodeStack.size() != 1 && "No parent node"); 1899 // Verify that all intermediate nodes between the root and this one have 1900 // a single use. 1901 bool HasMultipleUses = false; 1902 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 1903 if (!NodeStack[i].hasOneUse()) { 1904 HasMultipleUses = true; 1905 break; 1906 } 1907 if (HasMultipleUses) break; 1908 1909 // Check to see that the target thinks this is profitable to fold and that 1910 // we can fold it without inducing cycles in the graph. 1911 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 1912 NodeToMatch) || 1913 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 1914 NodeToMatch)) 1915 break; 1916 1917 continue; 1918 } 1919 case OPC_CheckChainCompatible: { 1920 unsigned PrevNode = MatcherTable[MatcherIndex++]; 1921 assert(PrevNode < RecordedNodes.size() && "Invalid CheckChainCompatible"); 1922 SDValue PrevChainedNode = RecordedNodes[PrevNode]; 1923 SDValue ThisChainedNode = RecordedNodes.back(); 1924 1925 // We have two nodes with chains, verify that their input chains are good. 1926 assert(PrevChainedNode.getOperand(0).getValueType() == MVT::Other && 1927 ThisChainedNode.getOperand(0).getValueType() == MVT::Other && 1928 "Invalid chained nodes"); 1929 1930 if (!IsChainCompatible(// Input chain of the previous node. 1931 PrevChainedNode.getOperand(0).getNode(), 1932 // Node with chain. 1933 ThisChainedNode.getNode())) 1934 break; 1935 continue; 1936 } 1937 1938 case OPC_EmitInteger: { 1939 MVT::SimpleValueType VT = 1940 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1941 int64_t Val = MatcherTable[MatcherIndex++]; 1942 if (Val & 128) 1943 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1944 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 1945 continue; 1946 } 1947 case OPC_EmitRegister: { 1948 MVT::SimpleValueType VT = 1949 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1950 unsigned RegNo = MatcherTable[MatcherIndex++]; 1951 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 1952 continue; 1953 } 1954 1955 case OPC_EmitConvertToTarget: { 1956 // Convert from IMM/FPIMM to target version. 1957 unsigned RecNo = MatcherTable[MatcherIndex++]; 1958 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1959 SDValue Imm = RecordedNodes[RecNo]; 1960 1961 if (Imm->getOpcode() == ISD::Constant) { 1962 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 1963 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 1964 } else if (Imm->getOpcode() == ISD::ConstantFP) { 1965 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 1966 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 1967 } 1968 1969 RecordedNodes.push_back(Imm); 1970 continue; 1971 } 1972 1973 case OPC_EmitMergeInputChains: { 1974 assert(InputChain.getNode() == 0 && 1975 "EmitMergeInputChains should be the first chain producing node"); 1976 // This node gets a list of nodes we matched in the input that have 1977 // chains. We want to token factor all of the input chains to these nodes 1978 // together. However, if any of the input chains is actually one of the 1979 // nodes matched in this pattern, then we have an intra-match reference. 1980 // Ignore these because the newly token factored chain should not refer to 1981 // the old nodes. 1982 unsigned NumChains = MatcherTable[MatcherIndex++]; 1983 assert(NumChains != 0 && "Can't TF zero chains"); 1984 1985 assert(ChainNodesMatched.empty() && 1986 "Should only have one EmitMergeInputChains per match"); 1987 1988 // Handle the first chain. 1989 unsigned RecNo = MatcherTable[MatcherIndex++]; 1990 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1991 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 1992 1993 // If the chained node is not the root, we can't fold it if it has 1994 // multiple uses. 1995 // FIXME: What if other value results of the node have uses not matched by 1996 // this pattern? 1997 if (ChainNodesMatched.back() != NodeToMatch && 1998 !RecordedNodes[RecNo].hasOneUse()) { 1999 ChainNodesMatched.clear(); 2000 break; 2001 } 2002 2003 // The common case here is that we have exactly one chain, which is really 2004 // cheap to handle, just do it. 2005 if (NumChains == 1) { 2006 InputChain = RecordedNodes[RecNo].getOperand(0); 2007 assert(InputChain.getValueType() == MVT::Other && "Not a chain"); 2008 continue; 2009 } 2010 2011 // Read all of the chained nodes. 2012 for (unsigned i = 1; i != NumChains; ++i) { 2013 RecNo = MatcherTable[MatcherIndex++]; 2014 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2015 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2016 2017 // FIXME: What if other value results of the node have uses not matched 2018 // by this pattern? 2019 if (ChainNodesMatched.back() != NodeToMatch && 2020 !RecordedNodes[RecNo].hasOneUse()) { 2021 ChainNodesMatched.clear(); 2022 break; 2023 } 2024 } 2025 2026 // If the inner loop broke out, the match fails. 2027 if (ChainNodesMatched.empty()) 2028 break; 2029 2030 // Merge the input chains if they are not intra-pattern references. 2031 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2032 2033 if (InputChain.getNode() == 0) 2034 break; // Failed to merge. 2035 2036 continue; 2037 } 2038 2039 case OPC_EmitCopyToReg: { 2040 unsigned RecNo = MatcherTable[MatcherIndex++]; 2041 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2042 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2043 2044 if (InputChain.getNode() == 0) 2045 InputChain = CurDAG->getEntryNode(); 2046 2047 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2048 DestPhysReg, RecordedNodes[RecNo], 2049 InputFlag); 2050 2051 InputFlag = InputChain.getValue(1); 2052 continue; 2053 } 2054 2055 case OPC_EmitNodeXForm: { 2056 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2057 unsigned RecNo = MatcherTable[MatcherIndex++]; 2058 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2059 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2060 continue; 2061 } 2062 2063 case OPC_EmitNode: 2064 case OPC_MorphNodeTo: { 2065 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2066 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2067 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2068 // Get the result VT list. 2069 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2070 SmallVector<EVT, 4> VTs; 2071 for (unsigned i = 0; i != NumVTs; ++i) { 2072 MVT::SimpleValueType VT = 2073 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2074 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2075 VTs.push_back(VT); 2076 } 2077 2078 if (EmitNodeInfo & OPFL_Chain) 2079 VTs.push_back(MVT::Other); 2080 if (EmitNodeInfo & OPFL_FlagOutput) 2081 VTs.push_back(MVT::Flag); 2082 2083 // This is hot code, so optimize the two most common cases of 1 and 2 2084 // results. 2085 SDVTList VTList; 2086 if (VTs.size() == 1) 2087 VTList = CurDAG->getVTList(VTs[0]); 2088 else if (VTs.size() == 2) 2089 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2090 else 2091 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2092 2093 // Get the operand list. 2094 unsigned NumOps = MatcherTable[MatcherIndex++]; 2095 SmallVector<SDValue, 8> Ops; 2096 for (unsigned i = 0; i != NumOps; ++i) { 2097 unsigned RecNo = MatcherTable[MatcherIndex++]; 2098 if (RecNo & 128) 2099 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2100 2101 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2102 Ops.push_back(RecordedNodes[RecNo]); 2103 } 2104 2105 // If there are variadic operands to add, handle them now. 2106 if (EmitNodeInfo & OPFL_VariadicInfo) { 2107 // Determine the start index to copy from. 2108 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2109 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2110 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2111 "Invalid variadic node"); 2112 // Copy all of the variadic operands, not including a potential flag 2113 // input. 2114 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2115 i != e; ++i) { 2116 SDValue V = NodeToMatch->getOperand(i); 2117 if (V.getValueType() == MVT::Flag) break; 2118 Ops.push_back(V); 2119 } 2120 } 2121 2122 // If this has chain/flag inputs, add them. 2123 if (EmitNodeInfo & OPFL_Chain) 2124 Ops.push_back(InputChain); 2125 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2126 Ops.push_back(InputFlag); 2127 2128 // Create the node. 2129 SDNode *Res = 0; 2130 if (Opcode != OPC_MorphNodeTo) { 2131 // If this is a normal EmitNode command, just create the new node and 2132 // add the results to the RecordedNodes list. 2133 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2134 VTList, Ops.data(), Ops.size()); 2135 2136 // Add all the non-flag/non-chain results to the RecordedNodes list. 2137 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2138 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2139 RecordedNodes.push_back(SDValue(Res, i)); 2140 } 2141 2142 } else { 2143 // It is possible we're using MorphNodeTo to replace a node with no 2144 // normal results with one that has a normal result (or we could be 2145 // adding a chain) and the input could have flags and chains as well. 2146 // In this case we need to shifting the operands down. 2147 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2148 // than the old isel though. We should sink this into MorphNodeTo. 2149 int OldFlagResultNo = -1, OldChainResultNo = -1; 2150 2151 unsigned NTMNumResults = NodeToMatch->getNumValues(); 2152 if (NodeToMatch->getValueType(NTMNumResults-1) == MVT::Flag) { 2153 OldFlagResultNo = NTMNumResults-1; 2154 if (NTMNumResults != 1 && 2155 NodeToMatch->getValueType(NTMNumResults-2) == MVT::Other) 2156 OldChainResultNo = NTMNumResults-2; 2157 } else if (NodeToMatch->getValueType(NTMNumResults-1) == MVT::Other) 2158 OldChainResultNo = NTMNumResults-1; 2159 2160 Res = CurDAG->MorphNodeTo(NodeToMatch, ~TargetOpc, VTList, 2161 Ops.data(), Ops.size()); 2162 2163 // MorphNodeTo can operate in two ways: if an existing node with the 2164 // specified operands exists, it can just return it. Otherwise, it 2165 // updates the node in place to have the requested operands. 2166 if (Res == NodeToMatch) { 2167 // If we updated the node in place, reset the node ID. To the isel, 2168 // this should be just like a newly allocated machine node. 2169 Res->setNodeId(-1); 2170 } 2171 2172 unsigned ResNumResults = Res->getNumValues(); 2173 // Move the flag if needed. 2174 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 2175 (unsigned)OldFlagResultNo != ResNumResults-1) 2176 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 2177 OldFlagResultNo), 2178 SDValue(Res, ResNumResults-1)); 2179 2180 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 2181 --ResNumResults; 2182 2183 // Move the chain reference if needed. 2184 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2185 (unsigned)OldChainResultNo != ResNumResults-1) 2186 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 2187 OldChainResultNo), 2188 SDValue(Res, ResNumResults-1)); 2189 2190 if (Res != NodeToMatch) { 2191 // Otherwise, no replacement happened because the node already exists. 2192 CurDAG->ReplaceAllUsesWith(NodeToMatch, Res); 2193 } 2194 } 2195 2196 // If the node had chain/flag results, update our notion of the current 2197 // chain and flag. 2198 if (VTs.back() == MVT::Flag) { 2199 InputFlag = SDValue(Res, VTs.size()-1); 2200 if (EmitNodeInfo & OPFL_Chain) 2201 InputChain = SDValue(Res, VTs.size()-2); 2202 } else if (EmitNodeInfo & OPFL_Chain) 2203 InputChain = SDValue(Res, VTs.size()-1); 2204 2205 // If the OPFL_MemRefs flag is set on this node, slap all of the 2206 // accumulated memrefs onto it. 2207 // 2208 // FIXME: This is vastly incorrect for patterns with multiple outputs 2209 // instructions that access memory and for ComplexPatterns that match 2210 // loads. 2211 if (EmitNodeInfo & OPFL_MemRefs) { 2212 MachineSDNode::mmo_iterator MemRefs = 2213 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2214 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2215 cast<MachineSDNode>(Res) 2216 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2217 } 2218 2219 DEBUG(errs() << " " 2220 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2221 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2222 2223 // If this was a MorphNodeTo then we're completely done! 2224 if (Opcode == OPC_MorphNodeTo) { 2225 // Update chain and flag uses. 2226 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2227 InputFlag, FlagResultNodesMatched, true, CurDAG); 2228 return 0; 2229 } 2230 2231 continue; 2232 } 2233 2234 case OPC_MarkFlagResults: { 2235 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2236 2237 // Read and remember all the flag-result nodes. 2238 for (unsigned i = 0; i != NumNodes; ++i) { 2239 unsigned RecNo = MatcherTable[MatcherIndex++]; 2240 if (RecNo & 128) 2241 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2242 2243 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2244 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2245 } 2246 continue; 2247 } 2248 2249 case OPC_CompleteMatch: { 2250 // The match has been completed, and any new nodes (if any) have been 2251 // created. Patch up references to the matched dag to use the newly 2252 // created nodes. 2253 unsigned NumResults = MatcherTable[MatcherIndex++]; 2254 2255 for (unsigned i = 0; i != NumResults; ++i) { 2256 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2257 if (ResSlot & 128) 2258 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2259 2260 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2261 SDValue Res = RecordedNodes[ResSlot]; 2262 2263 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program 2264 // after (parallel) on input patterns are removed. This would also 2265 // allow us to stop encoding #results in OPC_CompleteMatch's table 2266 // entry. 2267 if (NodeToMatch->getNumValues() <= i || 2268 NodeToMatch->getValueType(i) == MVT::Other || 2269 NodeToMatch->getValueType(i) == MVT::Flag) 2270 break; 2271 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2272 NodeToMatch->getValueType(i) == MVT::iPTR || 2273 Res.getValueType() == MVT::iPTR || 2274 NodeToMatch->getValueType(i).getSizeInBits() == 2275 Res.getValueType().getSizeInBits()) && 2276 "invalid replacement"); 2277 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2278 } 2279 2280 // If the root node defines a flag, add it to the flag nodes to update 2281 // list. 2282 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2283 FlagResultNodesMatched.push_back(NodeToMatch); 2284 2285 // Update chain and flag uses. 2286 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2287 InputFlag, FlagResultNodesMatched, false, CurDAG); 2288 2289 assert(NodeToMatch->use_empty() && 2290 "Didn't replace all uses of the node?"); 2291 2292 // FIXME: We just return here, which interacts correctly with SelectRoot 2293 // above. We should fix this to not return an SDNode* anymore. 2294 return 0; 2295 } 2296 } 2297 2298 // If the code reached this point, then the match failed. See if there is 2299 // another child to try in the current 'Scope', otherwise pop it until we 2300 // find a case to check. 2301 while (1) { 2302 if (MatchScopes.empty()) { 2303 CannotYetSelect(NodeToMatch); 2304 return 0; 2305 } 2306 2307 // Restore the interpreter state back to the point where the scope was 2308 // formed. 2309 MatchScope &LastScope = MatchScopes.back(); 2310 RecordedNodes.resize(LastScope.NumRecordedNodes); 2311 NodeStack.clear(); 2312 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2313 N = NodeStack.back(); 2314 2315 DEBUG(errs() << " Match failed at index " << MatcherIndex 2316 << " continuing at " << LastScope.FailIndex << "\n"); 2317 2318 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2319 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2320 MatcherIndex = LastScope.FailIndex; 2321 2322 InputChain = LastScope.InputChain; 2323 InputFlag = LastScope.InputFlag; 2324 if (!LastScope.HasChainNodesMatched) 2325 ChainNodesMatched.clear(); 2326 if (!LastScope.HasFlagResultNodesMatched) 2327 FlagResultNodesMatched.clear(); 2328 2329 // Check to see what the offset is at the new MatcherIndex. If it is zero 2330 // we have reached the end of this scope, otherwise we have another child 2331 // in the current scope to try. 2332 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2333 if (NumToSkip & 128) 2334 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2335 2336 // If we have another child in this scope to match, update FailIndex and 2337 // try it. 2338 if (NumToSkip != 0) { 2339 LastScope.FailIndex = MatcherIndex+NumToSkip; 2340 break; 2341 } 2342 2343 // End of this scope, pop it and try the next child in the containing 2344 // scope. 2345 MatchScopes.pop_back(); 2346 } 2347 } 2348} 2349 2350 2351 2352void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2353 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN || 2354 N->getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2355 N->getOpcode() == ISD::INTRINSIC_VOID) 2356 return CannotYetSelectIntrinsic(N); 2357 2358 std::string msg; 2359 raw_string_ostream Msg(msg); 2360 Msg << "Cannot yet select: "; 2361 N->printrFull(Msg, CurDAG); 2362 llvm_report_error(Msg.str()); 2363} 2364 2365void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) { 2366 dbgs() << "Cannot yet select: "; 2367 unsigned iid = 2368 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == 2369 MVT::Other))->getZExtValue(); 2370 if (iid < Intrinsic::num_intrinsics) 2371 llvm_report_error("Cannot yet select: intrinsic %" + 2372 Intrinsic::getName((Intrinsic::ID)iid)); 2373 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo()) 2374 llvm_report_error(Twine("Cannot yet select: target intrinsic %") + 2375 tii->getName(iid)); 2376} 2377 2378char SelectionDAGISel::ID = 0; 2379