SelectionDAGISel.cpp revision f147a8d56e0811525916f4d8cd5dd1777f834a85
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61//===---------------------------------------------------------------------===// 62/// 63/// RegisterScheduler class - Track the registration of instruction schedulers. 64/// 65//===---------------------------------------------------------------------===// 66MachinePassRegistry RegisterScheduler::Registry; 67 68//===---------------------------------------------------------------------===// 69/// 70/// ISHeuristic command line option for instruction schedulers. 71/// 72//===---------------------------------------------------------------------===// 73namespace { 74 cl::opt<RegisterScheduler::FunctionPassCtor, false, 75 RegisterPassParser<RegisterScheduler> > 76 ISHeuristic("sched", 77 cl::init(&createDefaultScheduler), 78 cl::desc("Instruction schedulers available:")); 79 80 static RegisterScheduler 81 defaultListDAGScheduler("default", " Best scheduler for the target", 82 createDefaultScheduler); 83} // namespace 84 85namespace { 86 /// RegsForValue - This struct represents the physical registers that a 87 /// particular value is assigned and the type information about the value. 88 /// This is needed because values can be promoted into larger registers and 89 /// expanded into multiple smaller registers than the value. 90 struct VISIBILITY_HIDDEN RegsForValue { 91 /// Regs - This list hold the register (for legal and promoted values) 92 /// or register set (for expanded values) that the value should be assigned 93 /// to. 94 std::vector<unsigned> Regs; 95 96 /// RegVT - The value type of each register. 97 /// 98 MVT::ValueType RegVT; 99 100 /// ValueVT - The value type of the LLVM value, which may be promoted from 101 /// RegVT or made from merging the two expanded parts. 102 MVT::ValueType ValueVT; 103 104 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 105 106 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 107 : RegVT(regvt), ValueVT(valuevt) { 108 Regs.push_back(Reg); 109 } 110 RegsForValue(const std::vector<unsigned> ®s, 111 MVT::ValueType regvt, MVT::ValueType valuevt) 112 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 113 } 114 115 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 116 /// this value and returns the result as a ValueVT value. This uses 117 /// Chain/Flag as the input and updates them for the output Chain/Flag. 118 SDOperand getCopyFromRegs(SelectionDAG &DAG, 119 SDOperand &Chain, SDOperand &Flag) const; 120 121 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 122 /// specified value into the registers specified by this object. This uses 123 /// Chain/Flag as the input and updates them for the output Chain/Flag. 124 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 125 SDOperand &Chain, SDOperand &Flag, 126 MVT::ValueType PtrVT) const; 127 128 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 129 /// operand list. This adds the code marker and includes the number of 130 /// values added into it. 131 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 132 std::vector<SDOperand> &Ops) const; 133 }; 134} 135 136namespace llvm { 137 //===--------------------------------------------------------------------===// 138 /// createDefaultScheduler - This creates an instruction scheduler appropriate 139 /// for the target. 140 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 141 SelectionDAG *DAG, 142 MachineBasicBlock *BB) { 143 TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 146 return createTDListDAGScheduler(IS, DAG, BB); 147 } else { 148 assert(TLI.getSchedulingPreference() == 149 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 150 return createBURRListDAGScheduler(IS, DAG, BB); 151 } 152 } 153 154 155 //===--------------------------------------------------------------------===// 156 /// FunctionLoweringInfo - This contains information that is global to a 157 /// function that is used when lowering a region of the function. 158 class FunctionLoweringInfo { 159 public: 160 TargetLowering &TLI; 161 Function &Fn; 162 MachineFunction &MF; 163 SSARegMap *RegMap; 164 165 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 166 167 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 168 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 169 170 /// ValueMap - Since we emit code for the function a basic block at a time, 171 /// we must remember which virtual registers hold the values for 172 /// cross-basic-block values. 173 DenseMap<const Value*, unsigned> ValueMap; 174 175 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 176 /// the entry block. This allows the allocas to be efficiently referenced 177 /// anywhere in the function. 178 std::map<const AllocaInst*, int> StaticAllocaMap; 179 180 unsigned MakeReg(MVT::ValueType VT) { 181 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 182 } 183 184 /// isExportedInst - Return true if the specified value is an instruction 185 /// exported from its block. 186 bool isExportedInst(const Value *V) { 187 return ValueMap.count(V); 188 } 189 190 unsigned CreateRegForValue(const Value *V); 191 192 unsigned InitializeRegForValue(const Value *V) { 193 unsigned &R = ValueMap[V]; 194 assert(R == 0 && "Already initialized this value register!"); 195 return R = CreateRegForValue(V); 196 } 197 }; 198} 199 200/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 201/// PHI nodes or outside of the basic block that defines it, or used by a 202/// switch instruction, which may expand to multiple basic blocks. 203static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 204 if (isa<PHINode>(I)) return true; 205 BasicBlock *BB = I->getParent(); 206 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 207 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 208 // FIXME: Remove switchinst special case. 209 isa<SwitchInst>(*UI)) 210 return true; 211 return false; 212} 213 214/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 215/// entry block, return true. This includes arguments used by switches, since 216/// the switch may expand into multiple basic blocks. 217static bool isOnlyUsedInEntryBlock(Argument *A) { 218 BasicBlock *Entry = A->getParent()->begin(); 219 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 220 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 221 return false; // Use not in entry block. 222 return true; 223} 224 225FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 226 Function &fn, MachineFunction &mf) 227 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 228 229 // Create a vreg for each argument register that is not dead and is used 230 // outside of the entry block for the function. 231 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 232 AI != E; ++AI) 233 if (!isOnlyUsedInEntryBlock(AI)) 234 InitializeRegForValue(AI); 235 236 // Initialize the mapping of values to registers. This is only set up for 237 // instruction values that are used outside of the block that defines 238 // them. 239 Function::iterator BB = Fn.begin(), EB = Fn.end(); 240 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 241 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 242 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 243 const Type *Ty = AI->getAllocatedType(); 244 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 245 unsigned Align = 246 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 247 AI->getAlignment()); 248 249 TySize *= CUI->getZExtValue(); // Get total allocated size. 250 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 251 StaticAllocaMap[AI] = 252 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 253 } 254 255 for (; BB != EB; ++BB) 256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 257 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 258 if (!isa<AllocaInst>(I) || 259 !StaticAllocaMap.count(cast<AllocaInst>(I))) 260 InitializeRegForValue(I); 261 262 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 263 // also creates the initial PHI MachineInstrs, though none of the input 264 // operands are populated. 265 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 266 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 267 MBBMap[BB] = MBB; 268 MF.getBasicBlockList().push_back(MBB); 269 270 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 271 // appropriate. 272 PHINode *PN; 273 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 274 if (PN->use_empty()) continue; 275 276 MVT::ValueType VT = TLI.getValueType(PN->getType()); 277 unsigned NumElements; 278 if (VT != MVT::Vector) 279 NumElements = TLI.getNumElements(VT); 280 else { 281 MVT::ValueType VT1,VT2; 282 NumElements = 283 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()), 284 VT1, VT2); 285 } 286 unsigned PHIReg = ValueMap[PN]; 287 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 288 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 289 for (unsigned i = 0; i != NumElements; ++i) 290 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 291 } 292 } 293} 294 295/// CreateRegForValue - Allocate the appropriate number of virtual registers of 296/// the correctly promoted or expanded types. Assign these registers 297/// consecutive vreg numbers and return the first assigned number. 298unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 299 MVT::ValueType VT = TLI.getValueType(V->getType()); 300 301 // The number of multiples of registers that we need, to, e.g., split up 302 // a <2 x int64> -> 4 x i32 registers. 303 unsigned NumVectorRegs = 1; 304 305 // If this is a vector type, figure out what type it will decompose into 306 // and how many of the elements it will use. 307 if (VT == MVT::Vector) { 308 const VectorType *PTy = cast<VectorType>(V->getType()); 309 unsigned NumElts = PTy->getNumElements(); 310 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 311 312 // Divide the input until we get to a supported size. This will always 313 // end with a scalar if the target doesn't support vectors. 314 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { 315 NumElts >>= 1; 316 NumVectorRegs <<= 1; 317 } 318 if (NumElts == 1) 319 VT = EltTy; 320 else 321 VT = getVectorType(EltTy, NumElts); 322 } 323 324 // The common case is that we will only create one register for this 325 // value. If we have that case, create and return the virtual register. 326 unsigned NV = TLI.getNumElements(VT); 327 if (NV == 1) { 328 // If we are promoting this value, pick the next largest supported type. 329 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 330 unsigned Reg = MakeReg(PromotedType); 331 // If this is a vector of supported or promoted types (e.g. 4 x i16), 332 // create all of the registers. 333 for (unsigned i = 1; i != NumVectorRegs; ++i) 334 MakeReg(PromotedType); 335 return Reg; 336 } 337 338 // If this value is represented with multiple target registers, make sure 339 // to create enough consecutive registers of the right (smaller) type. 340 VT = TLI.getTypeToExpandTo(VT); 341 unsigned R = MakeReg(VT); 342 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 343 MakeReg(VT); 344 return R; 345} 346 347//===----------------------------------------------------------------------===// 348/// SelectionDAGLowering - This is the common target-independent lowering 349/// implementation that is parameterized by a TargetLowering object. 350/// Also, targets can overload any lowering method. 351/// 352namespace llvm { 353class SelectionDAGLowering { 354 MachineBasicBlock *CurMBB; 355 356 DenseMap<const Value*, SDOperand> NodeMap; 357 358 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 359 /// them up and then emit token factor nodes when possible. This allows us to 360 /// get simple disambiguation between loads without worrying about alias 361 /// analysis. 362 std::vector<SDOperand> PendingLoads; 363 364 /// Case - A struct to record the Value for a switch case, and the 365 /// case's target basic block. 366 struct Case { 367 Constant* Low; 368 Constant* High; 369 MachineBasicBlock* BB; 370 371 Case() : Low(0), High(0), BB(0) { } 372 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 373 Low(low), High(high), BB(bb) { } 374 uint64_t size() const { 375 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 376 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 377 return (rHigh - rLow + 1ULL); 378 } 379 }; 380 381 struct CaseBits { 382 uint64_t Mask; 383 MachineBasicBlock* BB; 384 unsigned Bits; 385 386 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 387 Mask(mask), BB(bb), Bits(bits) { } 388 }; 389 390 typedef std::vector<Case> CaseVector; 391 typedef std::vector<CaseBits> CaseBitsVector; 392 typedef CaseVector::iterator CaseItr; 393 typedef std::pair<CaseItr, CaseItr> CaseRange; 394 395 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 396 /// of conditional branches. 397 struct CaseRec { 398 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 399 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 400 401 /// CaseBB - The MBB in which to emit the compare and branch 402 MachineBasicBlock *CaseBB; 403 /// LT, GE - If nonzero, we know the current case value must be less-than or 404 /// greater-than-or-equal-to these Constants. 405 Constant *LT; 406 Constant *GE; 407 /// Range - A pair of iterators representing the range of case values to be 408 /// processed at this point in the binary search tree. 409 CaseRange Range; 410 }; 411 412 typedef std::vector<CaseRec> CaseRecVector; 413 414 /// The comparison function for sorting the switch case values in the vector. 415 /// WARNING: Case ranges should be disjoint! 416 struct CaseCmp { 417 bool operator () (const Case& C1, const Case& C2) { 418 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 419 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 420 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 421 return CI1->getValue().slt(CI2->getValue()); 422 } 423 }; 424 425 struct CaseBitsCmp { 426 bool operator () (const CaseBits& C1, const CaseBits& C2) { 427 return C1.Bits > C2.Bits; 428 } 429 }; 430 431 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 432 433public: 434 // TLI - This is information that describes the available target features we 435 // need for lowering. This indicates when operations are unavailable, 436 // implemented with a libcall, etc. 437 TargetLowering &TLI; 438 SelectionDAG &DAG; 439 const TargetData *TD; 440 441 /// SwitchCases - Vector of CaseBlock structures used to communicate 442 /// SwitchInst code generation information. 443 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 444 /// JTCases - Vector of JumpTable structures used to communicate 445 /// SwitchInst code generation information. 446 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 447 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 448 449 /// FuncInfo - Information about the function as a whole. 450 /// 451 FunctionLoweringInfo &FuncInfo; 452 453 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 454 FunctionLoweringInfo &funcinfo) 455 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 456 FuncInfo(funcinfo) { 457 } 458 459 /// getRoot - Return the current virtual root of the Selection DAG. 460 /// 461 SDOperand getRoot() { 462 if (PendingLoads.empty()) 463 return DAG.getRoot(); 464 465 if (PendingLoads.size() == 1) { 466 SDOperand Root = PendingLoads[0]; 467 DAG.setRoot(Root); 468 PendingLoads.clear(); 469 return Root; 470 } 471 472 // Otherwise, we have to make a token factor node. 473 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 474 &PendingLoads[0], PendingLoads.size()); 475 PendingLoads.clear(); 476 DAG.setRoot(Root); 477 return Root; 478 } 479 480 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 481 482 void visit(Instruction &I) { visit(I.getOpcode(), I); } 483 484 void visit(unsigned Opcode, User &I) { 485 // Note: this doesn't use InstVisitor, because it has to work with 486 // ConstantExpr's in addition to instructions. 487 switch (Opcode) { 488 default: assert(0 && "Unknown instruction type encountered!"); 489 abort(); 490 // Build the switch statement using the Instruction.def file. 491#define HANDLE_INST(NUM, OPCODE, CLASS) \ 492 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 493#include "llvm/Instruction.def" 494 } 495 } 496 497 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 498 499 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 500 const Value *SV, SDOperand Root, 501 bool isVolatile, unsigned Alignment); 502 503 SDOperand getIntPtrConstant(uint64_t Val) { 504 return DAG.getConstant(Val, TLI.getPointerTy()); 505 } 506 507 SDOperand getValue(const Value *V); 508 509 void setValue(const Value *V, SDOperand NewN) { 510 SDOperand &N = NodeMap[V]; 511 assert(N.Val == 0 && "Already set a value for this node!"); 512 N = NewN; 513 } 514 515 RegsForValue GetRegistersForValue(const std::string &ConstrCode, 516 MVT::ValueType VT, 517 bool OutReg, bool InReg, 518 std::set<unsigned> &OutputRegs, 519 std::set<unsigned> &InputRegs); 520 521 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 522 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 523 unsigned Opc); 524 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 525 void ExportFromCurrentBlock(Value *V); 526 void LowerCallTo(Instruction &I, 527 const Type *CalledValueTy, unsigned CallingConv, 528 bool IsTailCall, SDOperand Callee, unsigned OpIdx); 529 530 // Terminator instructions. 531 void visitRet(ReturnInst &I); 532 void visitBr(BranchInst &I); 533 void visitSwitch(SwitchInst &I); 534 void visitUnreachable(UnreachableInst &I) { /* noop */ } 535 536 // Helpers for visitSwitch 537 bool handleSmallSwitchRange(CaseRec& CR, 538 CaseRecVector& WorkList, 539 Value* SV, 540 MachineBasicBlock* Default); 541 bool handleJTSwitchCase(CaseRec& CR, 542 CaseRecVector& WorkList, 543 Value* SV, 544 MachineBasicBlock* Default); 545 bool handleBTSplitSwitchCase(CaseRec& CR, 546 CaseRecVector& WorkList, 547 Value* SV, 548 MachineBasicBlock* Default); 549 bool handleBitTestsSwitchCase(CaseRec& CR, 550 CaseRecVector& WorkList, 551 Value* SV, 552 MachineBasicBlock* Default); 553 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 554 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 555 void visitBitTestCase(MachineBasicBlock* NextMBB, 556 unsigned Reg, 557 SelectionDAGISel::BitTestCase &B); 558 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 559 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 560 SelectionDAGISel::JumpTableHeader &JTH); 561 562 // These all get lowered before this pass. 563 void visitInvoke(InvokeInst &I); 564 void visitInvoke(InvokeInst &I, bool AsTerminator); 565 void visitUnwind(UnwindInst &I); 566 567 void visitScalarBinary(User &I, unsigned OpCode); 568 void visitVectorBinary(User &I, unsigned OpCode); 569 void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp); 570 void visitShift(User &I, unsigned Opcode); 571 void visitAdd(User &I) { 572 if (isa<VectorType>(I.getType())) 573 visitVectorBinary(I, ISD::VADD); 574 else if (I.getType()->isFloatingPoint()) 575 visitScalarBinary(I, ISD::FADD); 576 else 577 visitScalarBinary(I, ISD::ADD); 578 } 579 void visitSub(User &I); 580 void visitMul(User &I) { 581 if (isa<VectorType>(I.getType())) 582 visitVectorBinary(I, ISD::VMUL); 583 else if (I.getType()->isFloatingPoint()) 584 visitScalarBinary(I, ISD::FMUL); 585 else 586 visitScalarBinary(I, ISD::MUL); 587 } 588 void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); } 589 void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); } 590 void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); } 591 void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); } 592 void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); } 593 void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); } 594 void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); } 595 void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); } 596 void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); } 597 void visitShl (User &I) { visitShift(I, ISD::SHL); } 598 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 599 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 600 void visitICmp(User &I); 601 void visitFCmp(User &I); 602 // Visit the conversion instructions 603 void visitTrunc(User &I); 604 void visitZExt(User &I); 605 void visitSExt(User &I); 606 void visitFPTrunc(User &I); 607 void visitFPExt(User &I); 608 void visitFPToUI(User &I); 609 void visitFPToSI(User &I); 610 void visitUIToFP(User &I); 611 void visitSIToFP(User &I); 612 void visitPtrToInt(User &I); 613 void visitIntToPtr(User &I); 614 void visitBitCast(User &I); 615 616 void visitExtractElement(User &I); 617 void visitInsertElement(User &I); 618 void visitShuffleVector(User &I); 619 620 void visitGetElementPtr(User &I); 621 void visitSelect(User &I); 622 623 void visitMalloc(MallocInst &I); 624 void visitFree(FreeInst &I); 625 void visitAlloca(AllocaInst &I); 626 void visitLoad(LoadInst &I); 627 void visitStore(StoreInst &I); 628 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 629 void visitCall(CallInst &I); 630 void visitInlineAsm(CallInst &I); 631 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 632 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 633 634 void visitVAStart(CallInst &I); 635 void visitVAArg(VAArgInst &I); 636 void visitVAEnd(CallInst &I); 637 void visitVACopy(CallInst &I); 638 639 void visitMemIntrinsic(CallInst &I, unsigned Op); 640 641 void visitUserOp1(Instruction &I) { 642 assert(0 && "UserOp1 should not exist at instruction selection time!"); 643 abort(); 644 } 645 void visitUserOp2(Instruction &I) { 646 assert(0 && "UserOp2 should not exist at instruction selection time!"); 647 abort(); 648 } 649}; 650} // end namespace llvm 651 652SDOperand SelectionDAGLowering::getValue(const Value *V) { 653 SDOperand &N = NodeMap[V]; 654 if (N.Val) return N; 655 656 const Type *VTy = V->getType(); 657 MVT::ValueType VT = TLI.getValueType(VTy); 658 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 659 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 660 visit(CE->getOpcode(), *CE); 661 SDOperand N1 = NodeMap[V]; 662 assert(N1.Val && "visit didn't populate the ValueMap!"); 663 return N1; 664 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 665 return N = DAG.getGlobalAddress(GV, VT); 666 } else if (isa<ConstantPointerNull>(C)) { 667 return N = DAG.getConstant(0, TLI.getPointerTy()); 668 } else if (isa<UndefValue>(C)) { 669 if (!isa<VectorType>(VTy)) 670 return N = DAG.getNode(ISD::UNDEF, VT); 671 672 // Create a VBUILD_VECTOR of undef nodes. 673 const VectorType *PTy = cast<VectorType>(VTy); 674 unsigned NumElements = PTy->getNumElements(); 675 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 676 677 SmallVector<SDOperand, 8> Ops; 678 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 679 680 // Create a VConstant node with generic Vector type. 681 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 682 Ops.push_back(DAG.getValueType(PVT)); 683 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 684 &Ops[0], Ops.size()); 685 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 686 return N = DAG.getConstantFP(CFP->getValue(), VT); 687 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 688 unsigned NumElements = PTy->getNumElements(); 689 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 690 691 // Now that we know the number and type of the elements, push a 692 // Constant or ConstantFP node onto the ops list for each element of 693 // the packed constant. 694 SmallVector<SDOperand, 8> Ops; 695 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 696 for (unsigned i = 0; i != NumElements; ++i) 697 Ops.push_back(getValue(CP->getOperand(i))); 698 } else { 699 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 700 SDOperand Op; 701 if (MVT::isFloatingPoint(PVT)) 702 Op = DAG.getConstantFP(0, PVT); 703 else 704 Op = DAG.getConstant(0, PVT); 705 Ops.assign(NumElements, Op); 706 } 707 708 // Create a VBUILD_VECTOR node with generic Vector type. 709 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 710 Ops.push_back(DAG.getValueType(PVT)); 711 return NodeMap[V] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], 712 Ops.size()); 713 } else { 714 // Canonicalize all constant ints to be unsigned. 715 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 716 } 717 } 718 719 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 720 std::map<const AllocaInst*, int>::iterator SI = 721 FuncInfo.StaticAllocaMap.find(AI); 722 if (SI != FuncInfo.StaticAllocaMap.end()) 723 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 724 } 725 726 unsigned InReg = FuncInfo.ValueMap[V]; 727 assert(InReg && "Value not in map!"); 728 729 // If this type is not legal, make it so now. 730 if (VT != MVT::Vector) { 731 if (TLI.getTypeAction(VT) == TargetLowering::Expand) { 732 // Source must be expanded. This input value is actually coming from the 733 // register pair InReg and InReg+1. 734 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT); 735 unsigned NumVals = TLI.getNumElements(VT); 736 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 737 if (NumVals == 1) 738 N = DAG.getNode(ISD::BIT_CONVERT, VT, N); 739 else { 740 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 741 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 742 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 743 } 744 } else { 745 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 746 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 747 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case 748 N = MVT::isFloatingPoint(VT) 749 ? DAG.getNode(ISD::FP_ROUND, VT, N) 750 : DAG.getNode(ISD::TRUNCATE, VT, N); 751 } 752 } else { 753 // Otherwise, if this is a vector, make it available as a generic vector 754 // here. 755 MVT::ValueType PTyElementVT, PTyLegalElementVT; 756 const VectorType *PTy = cast<VectorType>(VTy); 757 unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT, 758 PTyLegalElementVT); 759 760 // Build a VBUILD_VECTOR with the input registers. 761 SmallVector<SDOperand, 8> Ops; 762 if (PTyElementVT == PTyLegalElementVT) { 763 // If the value types are legal, just VBUILD the CopyFromReg nodes. 764 for (unsigned i = 0; i != NE; ++i) 765 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 766 PTyElementVT)); 767 } else if (PTyElementVT < PTyLegalElementVT) { 768 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate. 769 for (unsigned i = 0; i != NE; ++i) { 770 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 771 PTyElementVT); 772 if (MVT::isFloatingPoint(PTyElementVT)) 773 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 774 else 775 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 776 Ops.push_back(Op); 777 } 778 } else { 779 // If the register was expanded, use BUILD_PAIR. 780 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 781 for (unsigned i = 0; i != NE/2; ++i) { 782 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 783 PTyElementVT); 784 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 785 PTyElementVT); 786 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); 787 } 788 } 789 790 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 791 Ops.push_back(DAG.getValueType(PTyLegalElementVT)); 792 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 793 794 // Finally, use a VBIT_CONVERT to make this available as the appropriate 795 // vector type. 796 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 797 DAG.getConstant(PTy->getNumElements(), 798 MVT::i32), 799 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 800 } 801 802 return N; 803} 804 805 806void SelectionDAGLowering::visitRet(ReturnInst &I) { 807 if (I.getNumOperands() == 0) { 808 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 809 return; 810 } 811 SmallVector<SDOperand, 8> NewValues; 812 NewValues.push_back(getRoot()); 813 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 814 SDOperand RetOp = getValue(I.getOperand(i)); 815 816 // If this is an integer return value, we need to promote it ourselves to 817 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 818 // than sign/zero. 819 // FIXME: C calling convention requires the return type to be promoted to 820 // at least 32-bit. But this is not necessary for non-C calling conventions. 821 if (MVT::isInteger(RetOp.getValueType()) && 822 RetOp.getValueType() < MVT::i64) { 823 MVT::ValueType TmpVT; 824 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 825 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 826 else 827 TmpVT = MVT::i32; 828 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType(); 829 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 830 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 831 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt)) 832 ExtendKind = ISD::SIGN_EXTEND; 833 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt)) 834 ExtendKind = ISD::ZERO_EXTEND; 835 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 836 } 837 NewValues.push_back(RetOp); 838 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 839 } 840 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 841 &NewValues[0], NewValues.size())); 842} 843 844/// ExportFromCurrentBlock - If this condition isn't known to be exported from 845/// the current basic block, add it to ValueMap now so that we'll get a 846/// CopyTo/FromReg. 847void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 848 // No need to export constants. 849 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 850 851 // Already exported? 852 if (FuncInfo.isExportedInst(V)) return; 853 854 unsigned Reg = FuncInfo.InitializeRegForValue(V); 855 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 856} 857 858bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 859 const BasicBlock *FromBB) { 860 // The operands of the setcc have to be in this block. We don't know 861 // how to export them from some other block. 862 if (Instruction *VI = dyn_cast<Instruction>(V)) { 863 // Can export from current BB. 864 if (VI->getParent() == FromBB) 865 return true; 866 867 // Is already exported, noop. 868 return FuncInfo.isExportedInst(V); 869 } 870 871 // If this is an argument, we can export it if the BB is the entry block or 872 // if it is already exported. 873 if (isa<Argument>(V)) { 874 if (FromBB == &FromBB->getParent()->getEntryBlock()) 875 return true; 876 877 // Otherwise, can only export this if it is already exported. 878 return FuncInfo.isExportedInst(V); 879 } 880 881 // Otherwise, constants can always be exported. 882 return true; 883} 884 885static bool InBlock(const Value *V, const BasicBlock *BB) { 886 if (const Instruction *I = dyn_cast<Instruction>(V)) 887 return I->getParent() == BB; 888 return true; 889} 890 891/// FindMergedConditions - If Cond is an expression like 892void SelectionDAGLowering::FindMergedConditions(Value *Cond, 893 MachineBasicBlock *TBB, 894 MachineBasicBlock *FBB, 895 MachineBasicBlock *CurBB, 896 unsigned Opc) { 897 // If this node is not part of the or/and tree, emit it as a branch. 898 Instruction *BOp = dyn_cast<Instruction>(Cond); 899 900 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 901 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 902 BOp->getParent() != CurBB->getBasicBlock() || 903 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 904 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 905 const BasicBlock *BB = CurBB->getBasicBlock(); 906 907 // If the leaf of the tree is a comparison, merge the condition into 908 // the caseblock. 909 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 910 // The operands of the cmp have to be in this block. We don't know 911 // how to export them from some other block. If this is the first block 912 // of the sequence, no exporting is needed. 913 (CurBB == CurMBB || 914 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 915 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 916 BOp = cast<Instruction>(Cond); 917 ISD::CondCode Condition; 918 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 919 switch (IC->getPredicate()) { 920 default: assert(0 && "Unknown icmp predicate opcode!"); 921 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 922 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 923 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 924 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 925 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 926 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 927 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 928 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 929 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 930 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 931 } 932 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 933 ISD::CondCode FPC, FOC; 934 switch (FC->getPredicate()) { 935 default: assert(0 && "Unknown fcmp predicate opcode!"); 936 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 937 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 938 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 939 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 940 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 941 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 942 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 943 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 944 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 945 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 946 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 947 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 948 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 949 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 950 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 951 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 952 } 953 if (FiniteOnlyFPMath()) 954 Condition = FOC; 955 else 956 Condition = FPC; 957 } else { 958 Condition = ISD::SETEQ; // silence warning. 959 assert(0 && "Unknown compare instruction"); 960 } 961 962 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 963 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 964 SwitchCases.push_back(CB); 965 return; 966 } 967 968 // Create a CaseBlock record representing this branch. 969 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 970 NULL, TBB, FBB, CurBB); 971 SwitchCases.push_back(CB); 972 return; 973 } 974 975 976 // Create TmpBB after CurBB. 977 MachineFunction::iterator BBI = CurBB; 978 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 979 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 980 981 if (Opc == Instruction::Or) { 982 // Codegen X | Y as: 983 // jmp_if_X TBB 984 // jmp TmpBB 985 // TmpBB: 986 // jmp_if_Y TBB 987 // jmp FBB 988 // 989 990 // Emit the LHS condition. 991 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 992 993 // Emit the RHS condition into TmpBB. 994 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 995 } else { 996 assert(Opc == Instruction::And && "Unknown merge op!"); 997 // Codegen X & Y as: 998 // jmp_if_X TmpBB 999 // jmp FBB 1000 // TmpBB: 1001 // jmp_if_Y TBB 1002 // jmp FBB 1003 // 1004 // This requires creation of TmpBB after CurBB. 1005 1006 // Emit the LHS condition. 1007 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1008 1009 // Emit the RHS condition into TmpBB. 1010 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1011 } 1012} 1013 1014/// If the set of cases should be emitted as a series of branches, return true. 1015/// If we should emit this as a bunch of and/or'd together conditions, return 1016/// false. 1017static bool 1018ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1019 if (Cases.size() != 2) return true; 1020 1021 // If this is two comparisons of the same values or'd or and'd together, they 1022 // will get folded into a single comparison, so don't emit two blocks. 1023 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1024 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1025 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1026 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1027 return false; 1028 } 1029 1030 return true; 1031} 1032 1033void SelectionDAGLowering::visitBr(BranchInst &I) { 1034 // Update machine-CFG edges. 1035 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1036 1037 // Figure out which block is immediately after the current one. 1038 MachineBasicBlock *NextBlock = 0; 1039 MachineFunction::iterator BBI = CurMBB; 1040 if (++BBI != CurMBB->getParent()->end()) 1041 NextBlock = BBI; 1042 1043 if (I.isUnconditional()) { 1044 // If this is not a fall-through branch, emit the branch. 1045 if (Succ0MBB != NextBlock) 1046 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1047 DAG.getBasicBlock(Succ0MBB))); 1048 1049 // Update machine-CFG edges. 1050 CurMBB->addSuccessor(Succ0MBB); 1051 1052 return; 1053 } 1054 1055 // If this condition is one of the special cases we handle, do special stuff 1056 // now. 1057 Value *CondVal = I.getCondition(); 1058 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1059 1060 // If this is a series of conditions that are or'd or and'd together, emit 1061 // this as a sequence of branches instead of setcc's with and/or operations. 1062 // For example, instead of something like: 1063 // cmp A, B 1064 // C = seteq 1065 // cmp D, E 1066 // F = setle 1067 // or C, F 1068 // jnz foo 1069 // Emit: 1070 // cmp A, B 1071 // je foo 1072 // cmp D, E 1073 // jle foo 1074 // 1075 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1076 if (BOp->hasOneUse() && 1077 (BOp->getOpcode() == Instruction::And || 1078 BOp->getOpcode() == Instruction::Or)) { 1079 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1080 // If the compares in later blocks need to use values not currently 1081 // exported from this block, export them now. This block should always 1082 // be the first entry. 1083 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1084 1085 // Allow some cases to be rejected. 1086 if (ShouldEmitAsBranches(SwitchCases)) { 1087 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1088 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1089 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1090 } 1091 1092 // Emit the branch for this block. 1093 visitSwitchCase(SwitchCases[0]); 1094 SwitchCases.erase(SwitchCases.begin()); 1095 return; 1096 } 1097 1098 // Okay, we decided not to do this, remove any inserted MBB's and clear 1099 // SwitchCases. 1100 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1101 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1102 1103 SwitchCases.clear(); 1104 } 1105 } 1106 1107 // Create a CaseBlock record representing this branch. 1108 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1109 NULL, Succ0MBB, Succ1MBB, CurMBB); 1110 // Use visitSwitchCase to actually insert the fast branch sequence for this 1111 // cond branch. 1112 visitSwitchCase(CB); 1113} 1114 1115/// visitSwitchCase - Emits the necessary code to represent a single node in 1116/// the binary search tree resulting from lowering a switch instruction. 1117void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1118 SDOperand Cond; 1119 SDOperand CondLHS = getValue(CB.CmpLHS); 1120 1121 // Build the setcc now. 1122 if (CB.CmpMHS == NULL) { 1123 // Fold "(X == true)" to X and "(X == false)" to !X to 1124 // handle common cases produced by branch lowering. 1125 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1126 Cond = CondLHS; 1127 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1128 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1129 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1130 } else 1131 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1132 } else { 1133 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1134 1135 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1136 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1137 1138 SDOperand CmpOp = getValue(CB.CmpMHS); 1139 MVT::ValueType VT = CmpOp.getValueType(); 1140 1141 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1142 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1143 } else { 1144 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1145 Cond = DAG.getSetCC(MVT::i1, SUB, 1146 DAG.getConstant(High-Low, VT), ISD::SETULE); 1147 } 1148 1149 } 1150 1151 // Set NextBlock to be the MBB immediately after the current one, if any. 1152 // This is used to avoid emitting unnecessary branches to the next block. 1153 MachineBasicBlock *NextBlock = 0; 1154 MachineFunction::iterator BBI = CurMBB; 1155 if (++BBI != CurMBB->getParent()->end()) 1156 NextBlock = BBI; 1157 1158 // If the lhs block is the next block, invert the condition so that we can 1159 // fall through to the lhs instead of the rhs block. 1160 if (CB.TrueBB == NextBlock) { 1161 std::swap(CB.TrueBB, CB.FalseBB); 1162 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1163 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1164 } 1165 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1166 DAG.getBasicBlock(CB.TrueBB)); 1167 if (CB.FalseBB == NextBlock) 1168 DAG.setRoot(BrCond); 1169 else 1170 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1171 DAG.getBasicBlock(CB.FalseBB))); 1172 // Update successor info 1173 CurMBB->addSuccessor(CB.TrueBB); 1174 CurMBB->addSuccessor(CB.FalseBB); 1175} 1176 1177/// visitJumpTable - Emit JumpTable node in the current MBB 1178void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1179 // Emit the code for the jump table 1180 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1181 MVT::ValueType PTy = TLI.getPointerTy(); 1182 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1183 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1184 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1185 Table, Index)); 1186 return; 1187} 1188 1189/// visitJumpTableHeader - This function emits necessary code to produce index 1190/// in the JumpTable from switch case. 1191void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1192 SelectionDAGISel::JumpTableHeader &JTH) { 1193 // Subtract the lowest switch case value from the value being switched on 1194 // and conditional branch to default mbb if the result is greater than the 1195 // difference between smallest and largest cases. 1196 SDOperand SwitchOp = getValue(JTH.SValue); 1197 MVT::ValueType VT = SwitchOp.getValueType(); 1198 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1199 DAG.getConstant(JTH.First, VT)); 1200 1201 // The SDNode we just created, which holds the value being switched on 1202 // minus the the smallest case value, needs to be copied to a virtual 1203 // register so it can be used as an index into the jump table in a 1204 // subsequent basic block. This value may be smaller or larger than the 1205 // target's pointer type, and therefore require extension or truncating. 1206 if (VT > TLI.getPointerTy()) 1207 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1208 else 1209 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1210 1211 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1212 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1213 JT.Reg = JumpTableReg; 1214 1215 // Emit the range check for the jump table, and branch to the default 1216 // block for the switch statement if the value being switched on exceeds 1217 // the largest case in the switch. 1218 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1219 DAG.getConstant(JTH.Last-JTH.First,VT), 1220 ISD::SETUGT); 1221 1222 // Set NextBlock to be the MBB immediately after the current one, if any. 1223 // This is used to avoid emitting unnecessary branches to the next block. 1224 MachineBasicBlock *NextBlock = 0; 1225 MachineFunction::iterator BBI = CurMBB; 1226 if (++BBI != CurMBB->getParent()->end()) 1227 NextBlock = BBI; 1228 1229 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1230 DAG.getBasicBlock(JT.Default)); 1231 1232 if (JT.MBB == NextBlock) 1233 DAG.setRoot(BrCond); 1234 else 1235 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1236 DAG.getBasicBlock(JT.MBB))); 1237 1238 return; 1239} 1240 1241/// visitBitTestHeader - This function emits necessary code to produce value 1242/// suitable for "bit tests" 1243void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1244 // Subtract the minimum value 1245 SDOperand SwitchOp = getValue(B.SValue); 1246 MVT::ValueType VT = SwitchOp.getValueType(); 1247 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1248 DAG.getConstant(B.First, VT)); 1249 1250 // Check range 1251 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1252 DAG.getConstant(B.Range, VT), 1253 ISD::SETUGT); 1254 1255 SDOperand ShiftOp; 1256 if (VT > TLI.getShiftAmountTy()) 1257 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1258 else 1259 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1260 1261 // Make desired shift 1262 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1263 DAG.getConstant(1, TLI.getPointerTy()), 1264 ShiftOp); 1265 1266 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1267 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1268 B.Reg = SwitchReg; 1269 1270 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1271 DAG.getBasicBlock(B.Default)); 1272 1273 // Set NextBlock to be the MBB immediately after the current one, if any. 1274 // This is used to avoid emitting unnecessary branches to the next block. 1275 MachineBasicBlock *NextBlock = 0; 1276 MachineFunction::iterator BBI = CurMBB; 1277 if (++BBI != CurMBB->getParent()->end()) 1278 NextBlock = BBI; 1279 1280 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1281 if (MBB == NextBlock) 1282 DAG.setRoot(BrRange); 1283 else 1284 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1285 DAG.getBasicBlock(MBB))); 1286 1287 CurMBB->addSuccessor(B.Default); 1288 CurMBB->addSuccessor(MBB); 1289 1290 return; 1291} 1292 1293/// visitBitTestCase - this function produces one "bit test" 1294void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1295 unsigned Reg, 1296 SelectionDAGISel::BitTestCase &B) { 1297 // Emit bit tests and jumps 1298 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1299 1300 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1301 SwitchVal, 1302 DAG.getConstant(B.Mask, 1303 TLI.getPointerTy())); 1304 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1305 DAG.getConstant(0, TLI.getPointerTy()), 1306 ISD::SETNE); 1307 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1308 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1309 1310 // Set NextBlock to be the MBB immediately after the current one, if any. 1311 // This is used to avoid emitting unnecessary branches to the next block. 1312 MachineBasicBlock *NextBlock = 0; 1313 MachineFunction::iterator BBI = CurMBB; 1314 if (++BBI != CurMBB->getParent()->end()) 1315 NextBlock = BBI; 1316 1317 if (NextMBB == NextBlock) 1318 DAG.setRoot(BrAnd); 1319 else 1320 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1321 DAG.getBasicBlock(NextMBB))); 1322 1323 CurMBB->addSuccessor(B.TargetBB); 1324 CurMBB->addSuccessor(NextMBB); 1325 1326 return; 1327} 1328 1329void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1330 assert(0 && "Should never be visited directly"); 1331} 1332void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) { 1333 // Retrieve successors. 1334 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1335 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1336 1337 if (!AsTerminator) { 1338 // Mark landing pad so that it doesn't get deleted in branch folding. 1339 LandingPad->setIsLandingPad(); 1340 1341 // Insert a label before the invoke call to mark the try range. 1342 // This can be used to detect deletion of the invoke via the 1343 // MachineModuleInfo. 1344 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1345 unsigned BeginLabel = MMI->NextLabelID(); 1346 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 1347 DAG.getConstant(BeginLabel, MVT::i32))); 1348 1349 LowerCallTo(I, I.getCalledValue()->getType(), 1350 I.getCallingConv(), 1351 false, 1352 getValue(I.getOperand(0)), 1353 3); 1354 1355 // Insert a label before the invoke call to mark the try range. 1356 // This can be used to detect deletion of the invoke via the 1357 // MachineModuleInfo. 1358 unsigned EndLabel = MMI->NextLabelID(); 1359 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 1360 DAG.getConstant(EndLabel, MVT::i32))); 1361 1362 // Inform MachineModuleInfo of range. 1363 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 1364 1365 // Update successor info 1366 CurMBB->addSuccessor(Return); 1367 CurMBB->addSuccessor(LandingPad); 1368 } else { 1369 // Drop into normal successor. 1370 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1371 DAG.getBasicBlock(Return))); 1372 } 1373} 1374 1375void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1376} 1377 1378/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1379/// small case ranges). 1380bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1381 CaseRecVector& WorkList, 1382 Value* SV, 1383 MachineBasicBlock* Default) { 1384 Case& BackCase = *(CR.Range.second-1); 1385 1386 // Size is the number of Cases represented by this range. 1387 unsigned Size = CR.Range.second - CR.Range.first; 1388 if (Size > 3) 1389 return false; 1390 1391 // Get the MachineFunction which holds the current MBB. This is used when 1392 // inserting any additional MBBs necessary to represent the switch. 1393 MachineFunction *CurMF = CurMBB->getParent(); 1394 1395 // Figure out which block is immediately after the current one. 1396 MachineBasicBlock *NextBlock = 0; 1397 MachineFunction::iterator BBI = CR.CaseBB; 1398 1399 if (++BBI != CurMBB->getParent()->end()) 1400 NextBlock = BBI; 1401 1402 // TODO: If any two of the cases has the same destination, and if one value 1403 // is the same as the other, but has one bit unset that the other has set, 1404 // use bit manipulation to do two compares at once. For example: 1405 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1406 1407 // Rearrange the case blocks so that the last one falls through if possible. 1408 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1409 // The last case block won't fall through into 'NextBlock' if we emit the 1410 // branches in this order. See if rearranging a case value would help. 1411 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1412 if (I->BB == NextBlock) { 1413 std::swap(*I, BackCase); 1414 break; 1415 } 1416 } 1417 } 1418 1419 // Create a CaseBlock record representing a conditional branch to 1420 // the Case's target mbb if the value being switched on SV is equal 1421 // to C. 1422 MachineBasicBlock *CurBlock = CR.CaseBB; 1423 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1424 MachineBasicBlock *FallThrough; 1425 if (I != E-1) { 1426 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1427 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1428 } else { 1429 // If the last case doesn't match, go to the default block. 1430 FallThrough = Default; 1431 } 1432 1433 Value *RHS, *LHS, *MHS; 1434 ISD::CondCode CC; 1435 if (I->High == I->Low) { 1436 // This is just small small case range :) containing exactly 1 case 1437 CC = ISD::SETEQ; 1438 LHS = SV; RHS = I->High; MHS = NULL; 1439 } else { 1440 CC = ISD::SETLE; 1441 LHS = I->Low; MHS = SV; RHS = I->High; 1442 } 1443 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1444 I->BB, FallThrough, CurBlock); 1445 1446 // If emitting the first comparison, just call visitSwitchCase to emit the 1447 // code into the current block. Otherwise, push the CaseBlock onto the 1448 // vector to be later processed by SDISel, and insert the node's MBB 1449 // before the next MBB. 1450 if (CurBlock == CurMBB) 1451 visitSwitchCase(CB); 1452 else 1453 SwitchCases.push_back(CB); 1454 1455 CurBlock = FallThrough; 1456 } 1457 1458 return true; 1459} 1460 1461/// handleJTSwitchCase - Emit jumptable for current switch case range 1462bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1463 CaseRecVector& WorkList, 1464 Value* SV, 1465 MachineBasicBlock* Default) { 1466 Case& FrontCase = *CR.Range.first; 1467 Case& BackCase = *(CR.Range.second-1); 1468 1469 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1470 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1471 1472 uint64_t TSize = 0; 1473 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1474 I!=E; ++I) 1475 TSize += I->size(); 1476 1477 if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) && 1478 !TLI.isOperationLegal(ISD::BRIND, MVT::Other)) || 1479 TSize <= 3) 1480 return false; 1481 1482 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1483 if (Density < 0.4) 1484 return false; 1485 1486 DOUT << "Lowering jump table\n" 1487 << "First entry: " << First << ". Last entry: " << Last << "\n" 1488 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1489 1490 // Get the MachineFunction which holds the current MBB. This is used when 1491 // inserting any additional MBBs necessary to represent the switch. 1492 MachineFunction *CurMF = CurMBB->getParent(); 1493 1494 // Figure out which block is immediately after the current one. 1495 MachineBasicBlock *NextBlock = 0; 1496 MachineFunction::iterator BBI = CR.CaseBB; 1497 1498 if (++BBI != CurMBB->getParent()->end()) 1499 NextBlock = BBI; 1500 1501 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1502 1503 // Create a new basic block to hold the code for loading the address 1504 // of the jump table, and jumping to it. Update successor information; 1505 // we will either branch to the default case for the switch, or the jump 1506 // table. 1507 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1508 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1509 CR.CaseBB->addSuccessor(Default); 1510 CR.CaseBB->addSuccessor(JumpTableBB); 1511 1512 // Build a vector of destination BBs, corresponding to each target 1513 // of the jump table. If the value of the jump table slot corresponds to 1514 // a case statement, push the case's BB onto the vector, otherwise, push 1515 // the default BB. 1516 std::vector<MachineBasicBlock*> DestBBs; 1517 int64_t TEI = First; 1518 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1519 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1520 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1521 1522 if ((Low <= TEI) && (TEI <= High)) { 1523 DestBBs.push_back(I->BB); 1524 if (TEI==High) 1525 ++I; 1526 } else { 1527 DestBBs.push_back(Default); 1528 } 1529 } 1530 1531 // Update successor info. Add one edge to each unique successor. 1532 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1533 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1534 E = DestBBs.end(); I != E; ++I) { 1535 if (!SuccsHandled[(*I)->getNumber()]) { 1536 SuccsHandled[(*I)->getNumber()] = true; 1537 JumpTableBB->addSuccessor(*I); 1538 } 1539 } 1540 1541 // Create a jump table index for this jump table, or return an existing 1542 // one. 1543 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1544 1545 // Set the jump table information so that we can codegen it as a second 1546 // MachineBasicBlock 1547 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1548 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1549 (CR.CaseBB == CurMBB)); 1550 if (CR.CaseBB == CurMBB) 1551 visitJumpTableHeader(JT, JTH); 1552 1553 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1554 1555 return true; 1556} 1557 1558/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1559/// 2 subtrees. 1560bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1561 CaseRecVector& WorkList, 1562 Value* SV, 1563 MachineBasicBlock* Default) { 1564 // Get the MachineFunction which holds the current MBB. This is used when 1565 // inserting any additional MBBs necessary to represent the switch. 1566 MachineFunction *CurMF = CurMBB->getParent(); 1567 1568 // Figure out which block is immediately after the current one. 1569 MachineBasicBlock *NextBlock = 0; 1570 MachineFunction::iterator BBI = CR.CaseBB; 1571 1572 if (++BBI != CurMBB->getParent()->end()) 1573 NextBlock = BBI; 1574 1575 Case& FrontCase = *CR.Range.first; 1576 Case& BackCase = *(CR.Range.second-1); 1577 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1578 1579 // Size is the number of Cases represented by this range. 1580 unsigned Size = CR.Range.second - CR.Range.first; 1581 1582 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1583 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1584 double FMetric = 0; 1585 CaseItr Pivot = CR.Range.first + Size/2; 1586 1587 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1588 // (heuristically) allow us to emit JumpTable's later. 1589 uint64_t TSize = 0; 1590 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1591 I!=E; ++I) 1592 TSize += I->size(); 1593 1594 uint64_t LSize = FrontCase.size(); 1595 uint64_t RSize = TSize-LSize; 1596 DOUT << "Selecting best pivot: \n" 1597 << "First: " << First << ", Last: " << Last <<"\n" 1598 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1599 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1600 J!=E; ++I, ++J) { 1601 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1602 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1603 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1604 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1605 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1606 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1607 // Should always split in some non-trivial place 1608 DOUT <<"=>Step\n" 1609 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1610 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1611 << "Metric: " << Metric << "\n"; 1612 if (FMetric < Metric) { 1613 Pivot = J; 1614 FMetric = Metric; 1615 DOUT << "Current metric set to: " << FMetric << "\n"; 1616 } 1617 1618 LSize += J->size(); 1619 RSize -= J->size(); 1620 } 1621 // If our case is dense we *really* should handle it earlier! 1622 assert((FMetric > 0) && "Should handle dense range earlier!"); 1623 1624 CaseRange LHSR(CR.Range.first, Pivot); 1625 CaseRange RHSR(Pivot, CR.Range.second); 1626 Constant *C = Pivot->Low; 1627 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1628 1629 // We know that we branch to the LHS if the Value being switched on is 1630 // less than the Pivot value, C. We use this to optimize our binary 1631 // tree a bit, by recognizing that if SV is greater than or equal to the 1632 // LHS's Case Value, and that Case Value is exactly one less than the 1633 // Pivot's Value, then we can branch directly to the LHS's Target, 1634 // rather than creating a leaf node for it. 1635 if ((LHSR.second - LHSR.first) == 1 && 1636 LHSR.first->High == CR.GE && 1637 cast<ConstantInt>(C)->getSExtValue() == 1638 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1639 TrueBB = LHSR.first->BB; 1640 } else { 1641 TrueBB = new MachineBasicBlock(LLVMBB); 1642 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1643 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1644 } 1645 1646 // Similar to the optimization above, if the Value being switched on is 1647 // known to be less than the Constant CR.LT, and the current Case Value 1648 // is CR.LT - 1, then we can branch directly to the target block for 1649 // the current Case Value, rather than emitting a RHS leaf node for it. 1650 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1651 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1652 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1653 FalseBB = RHSR.first->BB; 1654 } else { 1655 FalseBB = new MachineBasicBlock(LLVMBB); 1656 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1657 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1658 } 1659 1660 // Create a CaseBlock record representing a conditional branch to 1661 // the LHS node if the value being switched on SV is less than C. 1662 // Otherwise, branch to LHS. 1663 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1664 TrueBB, FalseBB, CR.CaseBB); 1665 1666 if (CR.CaseBB == CurMBB) 1667 visitSwitchCase(CB); 1668 else 1669 SwitchCases.push_back(CB); 1670 1671 return true; 1672} 1673 1674/// handleBitTestsSwitchCase - if current case range has few destination and 1675/// range span less, than machine word bitwidth, encode case range into series 1676/// of masks and emit bit tests with these masks. 1677bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1678 CaseRecVector& WorkList, 1679 Value* SV, 1680 MachineBasicBlock* Default){ 1681 return false; 1682 unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy()); 1683 1684 Case& FrontCase = *CR.Range.first; 1685 Case& BackCase = *(CR.Range.second-1); 1686 1687 // Get the MachineFunction which holds the current MBB. This is used when 1688 // inserting any additional MBBs necessary to represent the switch. 1689 MachineFunction *CurMF = CurMBB->getParent(); 1690 1691 unsigned numCmps = 0; 1692 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1693 I!=E; ++I) { 1694 // Single case counts one, case range - two. 1695 if (I->Low == I->High) 1696 numCmps +=1; 1697 else 1698 numCmps +=2; 1699 } 1700 1701 // Count unique destinations 1702 SmallSet<MachineBasicBlock*, 4> Dests; 1703 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1704 Dests.insert(I->BB); 1705 if (Dests.size() > 3) 1706 // Don't bother the code below, if there are too much unique destinations 1707 return false; 1708 } 1709 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1710 << "Total number of comparisons: " << numCmps << "\n"; 1711 1712 // Compute span of values. 1713 Constant* minValue = FrontCase.Low; 1714 Constant* maxValue = BackCase.High; 1715 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1716 cast<ConstantInt>(minValue)->getSExtValue(); 1717 DOUT << "Compare range: " << range << "\n" 1718 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1719 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1720 1721 if (range>IntPtrBits || 1722 (!(Dests.size() == 1 && numCmps >= 3) && 1723 !(Dests.size() == 2 && numCmps >= 5) && 1724 !(Dests.size() >= 3 && numCmps >= 6))) 1725 return false; 1726 1727 DOUT << "Emitting bit tests\n"; 1728 int64_t lowBound = 0; 1729 1730 // Optimize the case where all the case values fit in a 1731 // word without having to subtract minValue. In this case, 1732 // we can optimize away the subtraction. 1733 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1734 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1735 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1736 } else { 1737 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1738 } 1739 1740 CaseBitsVector CasesBits; 1741 unsigned i, count = 0; 1742 1743 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1744 MachineBasicBlock* Dest = I->BB; 1745 for (i = 0; i < count; ++i) 1746 if (Dest == CasesBits[i].BB) 1747 break; 1748 1749 if (i == count) { 1750 assert((count < 3) && "Too much destinations to test!"); 1751 CasesBits.push_back(CaseBits(0, Dest, 0)); 1752 count++; 1753 } 1754 1755 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1756 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1757 1758 for (uint64_t j = lo; j <= hi; j++) { 1759 CasesBits[i].Mask |= 1ULL << j; 1760 CasesBits[i].Bits++; 1761 } 1762 1763 } 1764 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1765 1766 SelectionDAGISel::BitTestInfo BTC; 1767 1768 // Figure out which block is immediately after the current one. 1769 MachineFunction::iterator BBI = CR.CaseBB; 1770 ++BBI; 1771 1772 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1773 1774 DOUT << "Cases:\n"; 1775 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1776 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1777 << ", BB: " << CasesBits[i].BB << "\n"; 1778 1779 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1780 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1781 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1782 CaseBB, 1783 CasesBits[i].BB)); 1784 } 1785 1786 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1787 -1U, (CR.CaseBB == CurMBB), 1788 CR.CaseBB, Default, BTC); 1789 1790 if (CR.CaseBB == CurMBB) 1791 visitBitTestHeader(BTB); 1792 1793 BitTestCases.push_back(BTB); 1794 1795 return true; 1796} 1797 1798 1799// Clusterify - Transform simple list of Cases into list of CaseRange's 1800unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1801 const SwitchInst& SI) { 1802 unsigned numCmps = 0; 1803 1804 // Start with "simple" cases 1805 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1806 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1807 Cases.push_back(Case(SI.getSuccessorValue(i), 1808 SI.getSuccessorValue(i), 1809 SMBB)); 1810 } 1811 sort(Cases.begin(), Cases.end(), CaseCmp()); 1812 1813 // Merge case into clusters 1814 if (Cases.size()>=2) 1815 for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) { 1816 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1817 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1818 MachineBasicBlock* nextBB = J->BB; 1819 MachineBasicBlock* currentBB = I->BB; 1820 1821 // If the two neighboring cases go to the same destination, merge them 1822 // into a single case. 1823 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1824 I->High = J->High; 1825 J = Cases.erase(J); 1826 } else { 1827 I = J++; 1828 } 1829 } 1830 1831 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1832 if (I->Low != I->High) 1833 // A range counts double, since it requires two compares. 1834 ++numCmps; 1835 } 1836 1837 return numCmps; 1838} 1839 1840void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1841 // Figure out which block is immediately after the current one. 1842 MachineBasicBlock *NextBlock = 0; 1843 MachineFunction::iterator BBI = CurMBB; 1844 1845 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1846 1847 // If there is only the default destination, branch to it if it is not the 1848 // next basic block. Otherwise, just fall through. 1849 if (SI.getNumOperands() == 2) { 1850 // Update machine-CFG edges. 1851 1852 // If this is not a fall-through branch, emit the branch. 1853 if (Default != NextBlock) 1854 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1855 DAG.getBasicBlock(Default))); 1856 1857 CurMBB->addSuccessor(Default); 1858 return; 1859 } 1860 1861 // If there are any non-default case statements, create a vector of Cases 1862 // representing each one, and sort the vector so that we can efficiently 1863 // create a binary search tree from them. 1864 CaseVector Cases; 1865 unsigned numCmps = Clusterify(Cases, SI); 1866 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1867 << ". Total compares: " << numCmps << "\n"; 1868 1869 // Get the Value to be switched on and default basic blocks, which will be 1870 // inserted into CaseBlock records, representing basic blocks in the binary 1871 // search tree. 1872 Value *SV = SI.getOperand(0); 1873 1874 // Push the initial CaseRec onto the worklist 1875 CaseRecVector WorkList; 1876 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1877 1878 while (!WorkList.empty()) { 1879 // Grab a record representing a case range to process off the worklist 1880 CaseRec CR = WorkList.back(); 1881 WorkList.pop_back(); 1882 1883 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1884 continue; 1885 1886 // If the range has few cases (two or less) emit a series of specific 1887 // tests. 1888 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 1889 continue; 1890 1891 // If the switch has more than 5 blocks, and at least 40% dense, and the 1892 // target supports indirect branches, then emit a jump table rather than 1893 // lowering the switch to a binary tree of conditional branches. 1894 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 1895 continue; 1896 1897 // Emit binary tree. We need to pick a pivot, and push left and right ranges 1898 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 1899 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 1900 } 1901} 1902 1903 1904void SelectionDAGLowering::visitSub(User &I) { 1905 // -0.0 - X --> fneg 1906 const Type *Ty = I.getType(); 1907 if (isa<VectorType>(Ty)) { 1908 visitVectorBinary(I, ISD::VSUB); 1909 } else if (Ty->isFloatingPoint()) { 1910 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1911 if (CFP->isExactlyValue(-0.0)) { 1912 SDOperand Op2 = getValue(I.getOperand(1)); 1913 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1914 return; 1915 } 1916 visitScalarBinary(I, ISD::FSUB); 1917 } else 1918 visitScalarBinary(I, ISD::SUB); 1919} 1920 1921void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) { 1922 SDOperand Op1 = getValue(I.getOperand(0)); 1923 SDOperand Op2 = getValue(I.getOperand(1)); 1924 1925 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 1926} 1927 1928void 1929SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) { 1930 assert(isa<VectorType>(I.getType())); 1931 const VectorType *Ty = cast<VectorType>(I.getType()); 1932 SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType())); 1933 1934 setValue(&I, DAG.getNode(OpCode, MVT::Vector, 1935 getValue(I.getOperand(0)), 1936 getValue(I.getOperand(1)), 1937 DAG.getConstant(Ty->getNumElements(), MVT::i32), 1938 Typ)); 1939} 1940 1941void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp, 1942 unsigned VectorOp) { 1943 if (isa<VectorType>(I.getType())) 1944 visitVectorBinary(I, VectorOp); 1945 else 1946 visitScalarBinary(I, ScalarOp); 1947} 1948 1949void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1950 SDOperand Op1 = getValue(I.getOperand(0)); 1951 SDOperand Op2 = getValue(I.getOperand(1)); 1952 1953 if (TLI.getShiftAmountTy() < Op2.getValueType()) 1954 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 1955 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 1956 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1957 1958 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1959} 1960 1961void SelectionDAGLowering::visitICmp(User &I) { 1962 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 1963 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 1964 predicate = IC->getPredicate(); 1965 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 1966 predicate = ICmpInst::Predicate(IC->getPredicate()); 1967 SDOperand Op1 = getValue(I.getOperand(0)); 1968 SDOperand Op2 = getValue(I.getOperand(1)); 1969 ISD::CondCode Opcode; 1970 switch (predicate) { 1971 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 1972 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 1973 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 1974 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 1975 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 1976 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 1977 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 1978 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 1979 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 1980 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 1981 default: 1982 assert(!"Invalid ICmp predicate value"); 1983 Opcode = ISD::SETEQ; 1984 break; 1985 } 1986 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1987} 1988 1989void SelectionDAGLowering::visitFCmp(User &I) { 1990 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 1991 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 1992 predicate = FC->getPredicate(); 1993 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 1994 predicate = FCmpInst::Predicate(FC->getPredicate()); 1995 SDOperand Op1 = getValue(I.getOperand(0)); 1996 SDOperand Op2 = getValue(I.getOperand(1)); 1997 ISD::CondCode Condition, FOC, FPC; 1998 switch (predicate) { 1999 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2000 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2001 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2002 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2003 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2004 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2005 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2006 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2007 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2008 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2009 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2010 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2011 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2012 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2013 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2014 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2015 default: 2016 assert(!"Invalid FCmp predicate value"); 2017 FOC = FPC = ISD::SETFALSE; 2018 break; 2019 } 2020 if (FiniteOnlyFPMath()) 2021 Condition = FOC; 2022 else 2023 Condition = FPC; 2024 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2025} 2026 2027void SelectionDAGLowering::visitSelect(User &I) { 2028 SDOperand Cond = getValue(I.getOperand(0)); 2029 SDOperand TrueVal = getValue(I.getOperand(1)); 2030 SDOperand FalseVal = getValue(I.getOperand(2)); 2031 if (!isa<VectorType>(I.getType())) { 2032 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2033 TrueVal, FalseVal)); 2034 } else { 2035 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 2036 *(TrueVal.Val->op_end()-2), 2037 *(TrueVal.Val->op_end()-1))); 2038 } 2039} 2040 2041 2042void SelectionDAGLowering::visitTrunc(User &I) { 2043 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2044 SDOperand N = getValue(I.getOperand(0)); 2045 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2046 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2047} 2048 2049void SelectionDAGLowering::visitZExt(User &I) { 2050 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2051 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2052 SDOperand N = getValue(I.getOperand(0)); 2053 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2054 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2055} 2056 2057void SelectionDAGLowering::visitSExt(User &I) { 2058 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2059 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2060 SDOperand N = getValue(I.getOperand(0)); 2061 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2062 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2063} 2064 2065void SelectionDAGLowering::visitFPTrunc(User &I) { 2066 // FPTrunc is never a no-op cast, no need to check 2067 SDOperand N = getValue(I.getOperand(0)); 2068 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2069 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2070} 2071 2072void SelectionDAGLowering::visitFPExt(User &I){ 2073 // FPTrunc is never a no-op cast, no need to check 2074 SDOperand N = getValue(I.getOperand(0)); 2075 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2076 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2077} 2078 2079void SelectionDAGLowering::visitFPToUI(User &I) { 2080 // FPToUI is never a no-op cast, no need to check 2081 SDOperand N = getValue(I.getOperand(0)); 2082 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2083 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2084} 2085 2086void SelectionDAGLowering::visitFPToSI(User &I) { 2087 // FPToSI is never a no-op cast, no need to check 2088 SDOperand N = getValue(I.getOperand(0)); 2089 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2090 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2091} 2092 2093void SelectionDAGLowering::visitUIToFP(User &I) { 2094 // UIToFP is never a no-op cast, no need to check 2095 SDOperand N = getValue(I.getOperand(0)); 2096 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2097 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2098} 2099 2100void SelectionDAGLowering::visitSIToFP(User &I){ 2101 // UIToFP is never a no-op cast, no need to check 2102 SDOperand N = getValue(I.getOperand(0)); 2103 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2104 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2105} 2106 2107void SelectionDAGLowering::visitPtrToInt(User &I) { 2108 // What to do depends on the size of the integer and the size of the pointer. 2109 // We can either truncate, zero extend, or no-op, accordingly. 2110 SDOperand N = getValue(I.getOperand(0)); 2111 MVT::ValueType SrcVT = N.getValueType(); 2112 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2113 SDOperand Result; 2114 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2115 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2116 else 2117 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2118 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2119 setValue(&I, Result); 2120} 2121 2122void SelectionDAGLowering::visitIntToPtr(User &I) { 2123 // What to do depends on the size of the integer and the size of the pointer. 2124 // We can either truncate, zero extend, or no-op, accordingly. 2125 SDOperand N = getValue(I.getOperand(0)); 2126 MVT::ValueType SrcVT = N.getValueType(); 2127 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2128 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2129 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2130 else 2131 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2132 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2133} 2134 2135void SelectionDAGLowering::visitBitCast(User &I) { 2136 SDOperand N = getValue(I.getOperand(0)); 2137 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2138 if (DestVT == MVT::Vector) { 2139 // This is a cast to a vector from something else. 2140 // Get information about the output vector. 2141 const VectorType *DestTy = cast<VectorType>(I.getType()); 2142 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2143 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 2144 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 2145 DAG.getValueType(EltVT))); 2146 return; 2147 } 2148 MVT::ValueType SrcVT = N.getValueType(); 2149 if (SrcVT == MVT::Vector) { 2150 // This is a cast from a vctor to something else. 2151 // Get information about the input vector. 2152 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 2153 return; 2154 } 2155 2156 // BitCast assures us that source and destination are the same size so this 2157 // is either a BIT_CONVERT or a no-op. 2158 if (DestVT != N.getValueType()) 2159 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2160 else 2161 setValue(&I, N); // noop cast. 2162} 2163 2164void SelectionDAGLowering::visitInsertElement(User &I) { 2165 SDOperand InVec = getValue(I.getOperand(0)); 2166 SDOperand InVal = getValue(I.getOperand(1)); 2167 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2168 getValue(I.getOperand(2))); 2169 2170 SDOperand Num = *(InVec.Val->op_end()-2); 2171 SDOperand Typ = *(InVec.Val->op_end()-1); 2172 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 2173 InVec, InVal, InIdx, Num, Typ)); 2174} 2175 2176void SelectionDAGLowering::visitExtractElement(User &I) { 2177 SDOperand InVec = getValue(I.getOperand(0)); 2178 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2179 getValue(I.getOperand(1))); 2180 SDOperand Typ = *(InVec.Val->op_end()-1); 2181 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 2182 TLI.getValueType(I.getType()), InVec, InIdx)); 2183} 2184 2185void SelectionDAGLowering::visitShuffleVector(User &I) { 2186 SDOperand V1 = getValue(I.getOperand(0)); 2187 SDOperand V2 = getValue(I.getOperand(1)); 2188 SDOperand Mask = getValue(I.getOperand(2)); 2189 2190 SDOperand Num = *(V1.Val->op_end()-2); 2191 SDOperand Typ = *(V2.Val->op_end()-1); 2192 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2193 V1, V2, Mask, Num, Typ)); 2194} 2195 2196 2197void SelectionDAGLowering::visitGetElementPtr(User &I) { 2198 SDOperand N = getValue(I.getOperand(0)); 2199 const Type *Ty = I.getOperand(0)->getType(); 2200 2201 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2202 OI != E; ++OI) { 2203 Value *Idx = *OI; 2204 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2205 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2206 if (Field) { 2207 // N = N + Offset 2208 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2209 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2210 getIntPtrConstant(Offset)); 2211 } 2212 Ty = StTy->getElementType(Field); 2213 } else { 2214 Ty = cast<SequentialType>(Ty)->getElementType(); 2215 2216 // If this is a constant subscript, handle it quickly. 2217 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2218 if (CI->getZExtValue() == 0) continue; 2219 uint64_t Offs = 2220 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2221 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2222 continue; 2223 } 2224 2225 // N = N + Idx * ElementSize; 2226 uint64_t ElementSize = TD->getTypeSize(Ty); 2227 SDOperand IdxN = getValue(Idx); 2228 2229 // If the index is smaller or larger than intptr_t, truncate or extend 2230 // it. 2231 if (IdxN.getValueType() < N.getValueType()) { 2232 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2233 } else if (IdxN.getValueType() > N.getValueType()) 2234 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2235 2236 // If this is a multiply by a power of two, turn it into a shl 2237 // immediately. This is a very common case. 2238 if (isPowerOf2_64(ElementSize)) { 2239 unsigned Amt = Log2_64(ElementSize); 2240 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2241 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2242 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2243 continue; 2244 } 2245 2246 SDOperand Scale = getIntPtrConstant(ElementSize); 2247 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2248 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2249 } 2250 } 2251 setValue(&I, N); 2252} 2253 2254void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2255 // If this is a fixed sized alloca in the entry block of the function, 2256 // allocate it statically on the stack. 2257 if (FuncInfo.StaticAllocaMap.count(&I)) 2258 return; // getValue will auto-populate this. 2259 2260 const Type *Ty = I.getAllocatedType(); 2261 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 2262 unsigned Align = 2263 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2264 I.getAlignment()); 2265 2266 SDOperand AllocSize = getValue(I.getArraySize()); 2267 MVT::ValueType IntPtr = TLI.getPointerTy(); 2268 if (IntPtr < AllocSize.getValueType()) 2269 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2270 else if (IntPtr > AllocSize.getValueType()) 2271 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2272 2273 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2274 getIntPtrConstant(TySize)); 2275 2276 // Handle alignment. If the requested alignment is less than or equal to the 2277 // stack alignment, ignore it and round the size of the allocation up to the 2278 // stack alignment size. If the size is greater than the stack alignment, we 2279 // note this in the DYNAMIC_STACKALLOC node. 2280 unsigned StackAlign = 2281 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2282 if (Align <= StackAlign) { 2283 Align = 0; 2284 // Add SA-1 to the size. 2285 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2286 getIntPtrConstant(StackAlign-1)); 2287 // Mask out the low bits for alignment purposes. 2288 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2289 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2290 } 2291 2292 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2293 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2294 MVT::Other); 2295 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2296 setValue(&I, DSA); 2297 DAG.setRoot(DSA.getValue(1)); 2298 2299 // Inform the Frame Information that we have just allocated a variable-sized 2300 // object. 2301 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2302} 2303 2304void SelectionDAGLowering::visitLoad(LoadInst &I) { 2305 SDOperand Ptr = getValue(I.getOperand(0)); 2306 2307 SDOperand Root; 2308 if (I.isVolatile()) 2309 Root = getRoot(); 2310 else { 2311 // Do not serialize non-volatile loads against each other. 2312 Root = DAG.getRoot(); 2313 } 2314 2315 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2316 Root, I.isVolatile(), I.getAlignment())); 2317} 2318 2319SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2320 const Value *SV, SDOperand Root, 2321 bool isVolatile, 2322 unsigned Alignment) { 2323 SDOperand L; 2324 if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) { 2325 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 2326 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, 2327 DAG.getSrcValue(SV)); 2328 } else { 2329 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2330 isVolatile, Alignment); 2331 } 2332 2333 if (isVolatile) 2334 DAG.setRoot(L.getValue(1)); 2335 else 2336 PendingLoads.push_back(L.getValue(1)); 2337 2338 return L; 2339} 2340 2341 2342void SelectionDAGLowering::visitStore(StoreInst &I) { 2343 Value *SrcV = I.getOperand(0); 2344 SDOperand Src = getValue(SrcV); 2345 SDOperand Ptr = getValue(I.getOperand(1)); 2346 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2347 I.isVolatile(), I.getAlignment())); 2348} 2349 2350/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 2351/// access memory and has no other side effects at all. 2352static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 2353#define GET_NO_MEMORY_INTRINSICS 2354#include "llvm/Intrinsics.gen" 2355#undef GET_NO_MEMORY_INTRINSICS 2356 return false; 2357} 2358 2359// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 2360// have any side-effects or if it only reads memory. 2361static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 2362#define GET_SIDE_EFFECT_INFO 2363#include "llvm/Intrinsics.gen" 2364#undef GET_SIDE_EFFECT_INFO 2365 return false; 2366} 2367 2368/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2369/// node. 2370void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2371 unsigned Intrinsic) { 2372 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 2373 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 2374 2375 // Build the operand list. 2376 SmallVector<SDOperand, 8> Ops; 2377 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2378 if (OnlyLoad) { 2379 // We don't need to serialize loads against other loads. 2380 Ops.push_back(DAG.getRoot()); 2381 } else { 2382 Ops.push_back(getRoot()); 2383 } 2384 } 2385 2386 // Add the intrinsic ID as an integer operand. 2387 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2388 2389 // Add all operands of the call to the operand list. 2390 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2391 SDOperand Op = getValue(I.getOperand(i)); 2392 2393 // If this is a vector type, force it to the right vector type. 2394 if (Op.getValueType() == MVT::Vector) { 2395 const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType()); 2396 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 2397 2398 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 2399 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 2400 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 2401 } 2402 2403 assert(TLI.isTypeLegal(Op.getValueType()) && 2404 "Intrinsic uses a non-legal type?"); 2405 Ops.push_back(Op); 2406 } 2407 2408 std::vector<MVT::ValueType> VTs; 2409 if (I.getType() != Type::VoidTy) { 2410 MVT::ValueType VT = TLI.getValueType(I.getType()); 2411 if (VT == MVT::Vector) { 2412 const VectorType *DestTy = cast<VectorType>(I.getType()); 2413 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2414 2415 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2416 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2417 } 2418 2419 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2420 VTs.push_back(VT); 2421 } 2422 if (HasChain) 2423 VTs.push_back(MVT::Other); 2424 2425 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2426 2427 // Create the node. 2428 SDOperand Result; 2429 if (!HasChain) 2430 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2431 &Ops[0], Ops.size()); 2432 else if (I.getType() != Type::VoidTy) 2433 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2434 &Ops[0], Ops.size()); 2435 else 2436 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2437 &Ops[0], Ops.size()); 2438 2439 if (HasChain) { 2440 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2441 if (OnlyLoad) 2442 PendingLoads.push_back(Chain); 2443 else 2444 DAG.setRoot(Chain); 2445 } 2446 if (I.getType() != Type::VoidTy) { 2447 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2448 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 2449 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 2450 DAG.getConstant(PTy->getNumElements(), MVT::i32), 2451 DAG.getValueType(EVT)); 2452 } 2453 setValue(&I, Result); 2454 } 2455} 2456 2457/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2458/// we want to emit this as a call to a named external function, return the name 2459/// otherwise lower it and return null. 2460const char * 2461SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2462 switch (Intrinsic) { 2463 default: 2464 // By default, turn this into a target intrinsic node. 2465 visitTargetIntrinsic(I, Intrinsic); 2466 return 0; 2467 case Intrinsic::vastart: visitVAStart(I); return 0; 2468 case Intrinsic::vaend: visitVAEnd(I); return 0; 2469 case Intrinsic::vacopy: visitVACopy(I); return 0; 2470 case Intrinsic::returnaddress: 2471 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2472 getValue(I.getOperand(1)))); 2473 return 0; 2474 case Intrinsic::frameaddress: 2475 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2476 getValue(I.getOperand(1)))); 2477 return 0; 2478 case Intrinsic::setjmp: 2479 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2480 break; 2481 case Intrinsic::longjmp: 2482 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2483 break; 2484 case Intrinsic::memcpy_i32: 2485 case Intrinsic::memcpy_i64: 2486 visitMemIntrinsic(I, ISD::MEMCPY); 2487 return 0; 2488 case Intrinsic::memset_i32: 2489 case Intrinsic::memset_i64: 2490 visitMemIntrinsic(I, ISD::MEMSET); 2491 return 0; 2492 case Intrinsic::memmove_i32: 2493 case Intrinsic::memmove_i64: 2494 visitMemIntrinsic(I, ISD::MEMMOVE); 2495 return 0; 2496 2497 case Intrinsic::dbg_stoppoint: { 2498 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2499 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2500 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2501 SDOperand Ops[5]; 2502 2503 Ops[0] = getRoot(); 2504 Ops[1] = getValue(SPI.getLineValue()); 2505 Ops[2] = getValue(SPI.getColumnValue()); 2506 2507 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2508 assert(DD && "Not a debug information descriptor"); 2509 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2510 2511 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2512 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2513 2514 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2515 } 2516 2517 return 0; 2518 } 2519 case Intrinsic::dbg_region_start: { 2520 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2521 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2522 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2523 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2524 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2525 DAG.getConstant(LabelID, MVT::i32))); 2526 } 2527 2528 return 0; 2529 } 2530 case Intrinsic::dbg_region_end: { 2531 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2532 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2533 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2534 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2535 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2536 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2537 } 2538 2539 return 0; 2540 } 2541 case Intrinsic::dbg_func_start: { 2542 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2543 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2544 if (MMI && FSI.getSubprogram() && 2545 MMI->Verify(FSI.getSubprogram())) { 2546 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2547 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2548 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2549 } 2550 2551 return 0; 2552 } 2553 case Intrinsic::dbg_declare: { 2554 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2555 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2556 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2557 SDOperand AddressOp = getValue(DI.getAddress()); 2558 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2559 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2560 } 2561 2562 return 0; 2563 } 2564 2565 case Intrinsic::eh_exception: { 2566 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2567 2568 if (MMI) { 2569 // Add a label to mark the beginning of the landing pad. Deletion of the 2570 // landing pad can thus be detected via the MachineModuleInfo. 2571 unsigned LabelID = MMI->addLandingPad(CurMBB); 2572 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 2573 DAG.getConstant(LabelID, MVT::i32))); 2574 2575 // Mark exception register as live in. 2576 unsigned Reg = TLI.getExceptionAddressRegister(); 2577 if (Reg) CurMBB->addLiveIn(Reg); 2578 2579 // Insert the EXCEPTIONADDR instruction. 2580 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2581 SDOperand Ops[1]; 2582 Ops[0] = DAG.getRoot(); 2583 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2584 setValue(&I, Op); 2585 DAG.setRoot(Op.getValue(1)); 2586 } else { 2587 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2588 } 2589 return 0; 2590 } 2591 2592 case Intrinsic::eh_selector: 2593 case Intrinsic::eh_filter:{ 2594 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2595 2596 if (MMI) { 2597 // Inform the MachineModuleInfo of the personality for this landing pad. 2598 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(2)); 2599 assert(CE && CE->getOpcode() == Instruction::BitCast && 2600 isa<Function>(CE->getOperand(0)) && 2601 "Personality should be a function"); 2602 MMI->addPersonality(CurMBB, cast<Function>(CE->getOperand(0))); 2603 if (Intrinsic == Intrinsic::eh_filter) 2604 MMI->setIsFilterLandingPad(CurMBB); 2605 2606 // Gather all the type infos for this landing pad and pass them along to 2607 // MachineModuleInfo. 2608 std::vector<GlobalVariable *> TyInfo; 2609 for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) { 2610 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(i)); 2611 if (CE && CE->getOpcode() == Instruction::BitCast && 2612 isa<GlobalVariable>(CE->getOperand(0))) { 2613 TyInfo.push_back(cast<GlobalVariable>(CE->getOperand(0))); 2614 } else { 2615 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i)); 2616 assert(CI && CI->getZExtValue() == 0 && 2617 "TypeInfo must be a global variable typeinfo or NULL"); 2618 TyInfo.push_back(NULL); 2619 } 2620 } 2621 MMI->addCatchTypeInfo(CurMBB, TyInfo); 2622 2623 // Mark exception selector register as live in. 2624 unsigned Reg = TLI.getExceptionSelectorRegister(); 2625 if (Reg) CurMBB->addLiveIn(Reg); 2626 2627 // Insert the EHSELECTION instruction. 2628 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); 2629 SDOperand Ops[2]; 2630 Ops[0] = getValue(I.getOperand(1)); 2631 Ops[1] = getRoot(); 2632 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2633 setValue(&I, Op); 2634 DAG.setRoot(Op.getValue(1)); 2635 } else { 2636 setValue(&I, DAG.getConstant(0, MVT::i32)); 2637 } 2638 2639 return 0; 2640 } 2641 2642 case Intrinsic::eh_typeid_for: { 2643 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2644 2645 if (MMI) { 2646 // Find the type id for the given typeinfo. 2647 GlobalVariable *GV = NULL; 2648 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(1)); 2649 if (CE && CE->getOpcode() == Instruction::BitCast && 2650 isa<GlobalVariable>(CE->getOperand(0))) { 2651 GV = cast<GlobalVariable>(CE->getOperand(0)); 2652 } else { 2653 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); 2654 assert(CI && CI->getZExtValue() == 0 && 2655 "TypeInfo must be a global variable typeinfo or NULL"); 2656 GV = NULL; 2657 } 2658 2659 unsigned TypeID = MMI->getTypeIDFor(GV); 2660 setValue(&I, DAG.getConstant(TypeID, MVT::i32)); 2661 } else { 2662 setValue(&I, DAG.getConstant(0, MVT::i32)); 2663 } 2664 2665 return 0; 2666 } 2667 2668 case Intrinsic::sqrt_f32: 2669 case Intrinsic::sqrt_f64: 2670 setValue(&I, DAG.getNode(ISD::FSQRT, 2671 getValue(I.getOperand(1)).getValueType(), 2672 getValue(I.getOperand(1)))); 2673 return 0; 2674 case Intrinsic::powi_f32: 2675 case Intrinsic::powi_f64: 2676 setValue(&I, DAG.getNode(ISD::FPOWI, 2677 getValue(I.getOperand(1)).getValueType(), 2678 getValue(I.getOperand(1)), 2679 getValue(I.getOperand(2)))); 2680 return 0; 2681 case Intrinsic::pcmarker: { 2682 SDOperand Tmp = getValue(I.getOperand(1)); 2683 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2684 return 0; 2685 } 2686 case Intrinsic::readcyclecounter: { 2687 SDOperand Op = getRoot(); 2688 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2689 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2690 &Op, 1); 2691 setValue(&I, Tmp); 2692 DAG.setRoot(Tmp.getValue(1)); 2693 return 0; 2694 } 2695 case Intrinsic::part_select: { 2696 // Currently not implemented: just abort 2697 assert(0 && "part_select intrinsic not implemented"); 2698 abort(); 2699 } 2700 case Intrinsic::part_set: { 2701 // Currently not implemented: just abort 2702 assert(0 && "part_set intrinsic not implemented"); 2703 abort(); 2704 } 2705 case Intrinsic::bswap: 2706 setValue(&I, DAG.getNode(ISD::BSWAP, 2707 getValue(I.getOperand(1)).getValueType(), 2708 getValue(I.getOperand(1)))); 2709 return 0; 2710 case Intrinsic::cttz: { 2711 SDOperand Arg = getValue(I.getOperand(1)); 2712 MVT::ValueType Ty = Arg.getValueType(); 2713 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2714 if (Ty < MVT::i32) 2715 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2716 else if (Ty > MVT::i32) 2717 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2718 setValue(&I, result); 2719 return 0; 2720 } 2721 case Intrinsic::ctlz: { 2722 SDOperand Arg = getValue(I.getOperand(1)); 2723 MVT::ValueType Ty = Arg.getValueType(); 2724 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2725 if (Ty < MVT::i32) 2726 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2727 else if (Ty > MVT::i32) 2728 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2729 setValue(&I, result); 2730 return 0; 2731 } 2732 case Intrinsic::ctpop: { 2733 SDOperand Arg = getValue(I.getOperand(1)); 2734 MVT::ValueType Ty = Arg.getValueType(); 2735 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2736 if (Ty < MVT::i32) 2737 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result); 2738 else if (Ty > MVT::i32) 2739 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result); 2740 setValue(&I, result); 2741 return 0; 2742 } 2743 case Intrinsic::stacksave: { 2744 SDOperand Op = getRoot(); 2745 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2746 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2747 setValue(&I, Tmp); 2748 DAG.setRoot(Tmp.getValue(1)); 2749 return 0; 2750 } 2751 case Intrinsic::stackrestore: { 2752 SDOperand Tmp = getValue(I.getOperand(1)); 2753 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2754 return 0; 2755 } 2756 case Intrinsic::prefetch: 2757 // FIXME: Currently discarding prefetches. 2758 return 0; 2759 } 2760} 2761 2762 2763void SelectionDAGLowering::LowerCallTo(Instruction &I, 2764 const Type *CalledValueTy, 2765 unsigned CallingConv, 2766 bool IsTailCall, 2767 SDOperand Callee, unsigned OpIdx) { 2768 const PointerType *PT = cast<PointerType>(CalledValueTy); 2769 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2770 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 2771 2772 TargetLowering::ArgListTy Args; 2773 TargetLowering::ArgListEntry Entry; 2774 Args.reserve(I.getNumOperands()); 2775 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2776 Value *Arg = I.getOperand(i); 2777 SDOperand ArgNode = getValue(Arg); 2778 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2779 Entry.isSExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::SExt); 2780 Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::ZExt); 2781 Entry.isInReg = Attrs && Attrs->paramHasAttr(i, ParamAttr::InReg); 2782 Entry.isSRet = Attrs && Attrs->paramHasAttr(i, ParamAttr::StructRet); 2783 Args.push_back(Entry); 2784 } 2785 2786 std::pair<SDOperand,SDOperand> Result = 2787 TLI.LowerCallTo(getRoot(), I.getType(), 2788 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2789 FTy->isVarArg(), CallingConv, IsTailCall, 2790 Callee, Args, DAG); 2791 if (I.getType() != Type::VoidTy) 2792 setValue(&I, Result.first); 2793 DAG.setRoot(Result.second); 2794} 2795 2796 2797void SelectionDAGLowering::visitCall(CallInst &I) { 2798 const char *RenameFn = 0; 2799 if (Function *F = I.getCalledFunction()) { 2800 if (F->isDeclaration()) 2801 if (unsigned IID = F->getIntrinsicID()) { 2802 RenameFn = visitIntrinsicCall(I, IID); 2803 if (!RenameFn) 2804 return; 2805 } else { // Not an LLVM intrinsic. 2806 const std::string &Name = F->getName(); 2807 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2808 if (I.getNumOperands() == 3 && // Basic sanity checks. 2809 I.getOperand(1)->getType()->isFloatingPoint() && 2810 I.getType() == I.getOperand(1)->getType() && 2811 I.getType() == I.getOperand(2)->getType()) { 2812 SDOperand LHS = getValue(I.getOperand(1)); 2813 SDOperand RHS = getValue(I.getOperand(2)); 2814 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2815 LHS, RHS)); 2816 return; 2817 } 2818 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2819 if (I.getNumOperands() == 2 && // Basic sanity checks. 2820 I.getOperand(1)->getType()->isFloatingPoint() && 2821 I.getType() == I.getOperand(1)->getType()) { 2822 SDOperand Tmp = getValue(I.getOperand(1)); 2823 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2824 return; 2825 } 2826 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2827 if (I.getNumOperands() == 2 && // Basic sanity checks. 2828 I.getOperand(1)->getType()->isFloatingPoint() && 2829 I.getType() == I.getOperand(1)->getType()) { 2830 SDOperand Tmp = getValue(I.getOperand(1)); 2831 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2832 return; 2833 } 2834 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2835 if (I.getNumOperands() == 2 && // Basic sanity checks. 2836 I.getOperand(1)->getType()->isFloatingPoint() && 2837 I.getType() == I.getOperand(1)->getType()) { 2838 SDOperand Tmp = getValue(I.getOperand(1)); 2839 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2840 return; 2841 } 2842 } 2843 } 2844 } else if (isa<InlineAsm>(I.getOperand(0))) { 2845 visitInlineAsm(I); 2846 return; 2847 } 2848 2849 SDOperand Callee; 2850 if (!RenameFn) 2851 Callee = getValue(I.getOperand(0)); 2852 else 2853 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2854 2855 LowerCallTo(I, I.getCalledValue()->getType(), 2856 I.getCallingConv(), 2857 I.isTailCall(), 2858 Callee, 2859 1); 2860} 2861 2862 2863SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2864 SDOperand &Chain, SDOperand &Flag)const{ 2865 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 2866 Chain = Val.getValue(1); 2867 Flag = Val.getValue(2); 2868 2869 // If the result was expanded, copy from the top part. 2870 if (Regs.size() > 1) { 2871 assert(Regs.size() == 2 && 2872 "Cannot expand to more than 2 elts yet!"); 2873 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 2874 Chain = Hi.getValue(1); 2875 Flag = Hi.getValue(2); 2876 if (DAG.getTargetLoweringInfo().isLittleEndian()) 2877 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 2878 else 2879 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 2880 } 2881 2882 // Otherwise, if the return value was promoted or extended, truncate it to the 2883 // appropriate type. 2884 if (RegVT == ValueVT) 2885 return Val; 2886 2887 if (MVT::isVector(RegVT)) { 2888 assert(ValueVT == MVT::Vector && "Unknown vector conversion!"); 2889 return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 2890 DAG.getConstant(MVT::getVectorNumElements(RegVT), 2891 MVT::i32), 2892 DAG.getValueType(MVT::getVectorBaseType(RegVT))); 2893 } 2894 2895 if (MVT::isInteger(RegVT)) { 2896 if (ValueVT < RegVT) 2897 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 2898 else 2899 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 2900 } 2901 2902 assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT)); 2903 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 2904} 2905 2906/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 2907/// specified value into the registers specified by this object. This uses 2908/// Chain/Flag as the input and updates them for the output Chain/Flag. 2909void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 2910 SDOperand &Chain, SDOperand &Flag, 2911 MVT::ValueType PtrVT) const { 2912 if (Regs.size() == 1) { 2913 // If there is a single register and the types differ, this must be 2914 // a promotion. 2915 if (RegVT != ValueVT) { 2916 if (MVT::isVector(RegVT)) { 2917 assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?"); 2918 Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val); 2919 } else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) { 2920 if (RegVT < ValueVT) 2921 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 2922 else 2923 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 2924 } else if (MVT::isFloatingPoint(RegVT) && 2925 MVT::isFloatingPoint(Val.getValueType())) { 2926 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 2927 } else if (MVT::getSizeInBits(RegVT) == 2928 MVT::getSizeInBits(Val.getValueType())) { 2929 Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val); 2930 } else { 2931 assert(0 && "Unknown mismatch!"); 2932 } 2933 } 2934 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 2935 Flag = Chain.getValue(1); 2936 } else { 2937 std::vector<unsigned> R(Regs); 2938 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2939 std::reverse(R.begin(), R.end()); 2940 2941 for (unsigned i = 0, e = R.size(); i != e; ++i) { 2942 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 2943 DAG.getConstant(i, PtrVT)); 2944 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 2945 Flag = Chain.getValue(1); 2946 } 2947 } 2948} 2949 2950/// AddInlineAsmOperands - Add this value to the specified inlineasm node 2951/// operand list. This adds the code marker and includes the number of 2952/// values added into it. 2953void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 2954 std::vector<SDOperand> &Ops) const { 2955 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 2956 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 2957 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 2958 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 2959} 2960 2961/// isAllocatableRegister - If the specified register is safe to allocate, 2962/// i.e. it isn't a stack pointer or some other special register, return the 2963/// register class for the register. Otherwise, return null. 2964static const TargetRegisterClass * 2965isAllocatableRegister(unsigned Reg, MachineFunction &MF, 2966 const TargetLowering &TLI, const MRegisterInfo *MRI) { 2967 MVT::ValueType FoundVT = MVT::Other; 2968 const TargetRegisterClass *FoundRC = 0; 2969 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 2970 E = MRI->regclass_end(); RCI != E; ++RCI) { 2971 MVT::ValueType ThisVT = MVT::Other; 2972 2973 const TargetRegisterClass *RC = *RCI; 2974 // If none of the the value types for this register class are valid, we 2975 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2976 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2977 I != E; ++I) { 2978 if (TLI.isTypeLegal(*I)) { 2979 // If we have already found this register in a different register class, 2980 // choose the one with the largest VT specified. For example, on 2981 // PowerPC, we favor f64 register classes over f32. 2982 if (FoundVT == MVT::Other || 2983 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 2984 ThisVT = *I; 2985 break; 2986 } 2987 } 2988 } 2989 2990 if (ThisVT == MVT::Other) continue; 2991 2992 // NOTE: This isn't ideal. In particular, this might allocate the 2993 // frame pointer in functions that need it (due to them not being taken 2994 // out of allocation, because a variable sized allocation hasn't been seen 2995 // yet). This is a slight code pessimization, but should still work. 2996 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 2997 E = RC->allocation_order_end(MF); I != E; ++I) 2998 if (*I == Reg) { 2999 // We found a matching register class. Keep looking at others in case 3000 // we find one with larger registers that this physreg is also in. 3001 FoundRC = RC; 3002 FoundVT = ThisVT; 3003 break; 3004 } 3005 } 3006 return FoundRC; 3007} 3008 3009RegsForValue SelectionDAGLowering:: 3010GetRegistersForValue(const std::string &ConstrCode, 3011 MVT::ValueType VT, bool isOutReg, bool isInReg, 3012 std::set<unsigned> &OutputRegs, 3013 std::set<unsigned> &InputRegs) { 3014 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3015 TLI.getRegForInlineAsmConstraint(ConstrCode, VT); 3016 std::vector<unsigned> Regs; 3017 3018 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1; 3019 MVT::ValueType RegVT; 3020 MVT::ValueType ValueVT = VT; 3021 3022 // If this is a constraint for a specific physical register, like {r17}, 3023 // assign it now. 3024 if (PhysReg.first) { 3025 if (VT == MVT::Other) 3026 ValueVT = *PhysReg.second->vt_begin(); 3027 3028 // Get the actual register value type. This is important, because the user 3029 // may have asked for (e.g.) the AX register in i32 type. We need to 3030 // remember that AX is actually i16 to get the right extension. 3031 RegVT = *PhysReg.second->vt_begin(); 3032 3033 // This is a explicit reference to a physical register. 3034 Regs.push_back(PhysReg.first); 3035 3036 // If this is an expanded reference, add the rest of the regs to Regs. 3037 if (NumRegs != 1) { 3038 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3039 TargetRegisterClass::iterator E = PhysReg.second->end(); 3040 for (; *I != PhysReg.first; ++I) 3041 assert(I != E && "Didn't find reg!"); 3042 3043 // Already added the first reg. 3044 --NumRegs; ++I; 3045 for (; NumRegs; --NumRegs, ++I) { 3046 assert(I != E && "Ran out of registers to allocate!"); 3047 Regs.push_back(*I); 3048 } 3049 } 3050 return RegsForValue(Regs, RegVT, ValueVT); 3051 } 3052 3053 // Otherwise, if this was a reference to an LLVM register class, create vregs 3054 // for this reference. 3055 std::vector<unsigned> RegClassRegs; 3056 if (PhysReg.second) { 3057 // If this is an early clobber or tied register, our regalloc doesn't know 3058 // how to maintain the constraint. If it isn't, go ahead and create vreg 3059 // and let the regalloc do the right thing. 3060 if (!isOutReg || !isInReg) { 3061 RegVT = *PhysReg.second->vt_begin(); 3062 3063 if (VT == MVT::Other) 3064 ValueVT = RegVT; 3065 3066 // Create the appropriate number of virtual registers. 3067 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap(); 3068 for (; NumRegs; --NumRegs) 3069 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3070 3071 return RegsForValue(Regs, RegVT, ValueVT); 3072 } 3073 3074 // Otherwise, we can't allocate it. Let the code below figure out how to 3075 // maintain these constraints. 3076 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3077 3078 } else { 3079 // This is a reference to a register class that doesn't directly correspond 3080 // to an LLVM register class. Allocate NumRegs consecutive, available, 3081 // registers from the class. 3082 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT); 3083 } 3084 3085 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3086 MachineFunction &MF = *CurMBB->getParent(); 3087 unsigned NumAllocated = 0; 3088 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3089 unsigned Reg = RegClassRegs[i]; 3090 // See if this register is available. 3091 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3092 (isInReg && InputRegs.count(Reg))) { // Already used. 3093 // Make sure we find consecutive registers. 3094 NumAllocated = 0; 3095 continue; 3096 } 3097 3098 // Check to see if this register is allocatable (i.e. don't give out the 3099 // stack pointer). 3100 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3101 if (!RC) { 3102 // Make sure we find consecutive registers. 3103 NumAllocated = 0; 3104 continue; 3105 } 3106 3107 // Okay, this register is good, we can use it. 3108 ++NumAllocated; 3109 3110 // If we allocated enough consecutive registers, succeed. 3111 if (NumAllocated == NumRegs) { 3112 unsigned RegStart = (i-NumAllocated)+1; 3113 unsigned RegEnd = i+1; 3114 // Mark all of the allocated registers used. 3115 for (unsigned i = RegStart; i != RegEnd; ++i) { 3116 unsigned Reg = RegClassRegs[i]; 3117 Regs.push_back(Reg); 3118 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used. 3119 if (isInReg) InputRegs.insert(Reg); // Mark reg used. 3120 } 3121 3122 return RegsForValue(Regs, *RC->vt_begin(), VT); 3123 } 3124 } 3125 3126 // Otherwise, we couldn't allocate enough registers for this. 3127 return RegsForValue(); 3128} 3129 3130/// getConstraintGenerality - Return an integer indicating how general CT is. 3131static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3132 switch (CT) { 3133 default: assert(0 && "Unknown constraint type!"); 3134 case TargetLowering::C_Other: 3135 case TargetLowering::C_Unknown: 3136 return 0; 3137 case TargetLowering::C_Register: 3138 return 1; 3139 case TargetLowering::C_RegisterClass: 3140 return 2; 3141 case TargetLowering::C_Memory: 3142 return 3; 3143 } 3144} 3145 3146static std::string GetMostGeneralConstraint(std::vector<std::string> &C, 3147 const TargetLowering &TLI) { 3148 assert(!C.empty() && "Must have at least one constraint"); 3149 if (C.size() == 1) return C[0]; 3150 3151 std::string *Current = &C[0]; 3152 // If we have multiple constraints, try to pick the most general one ahead 3153 // of time. This isn't a wonderful solution, but handles common cases. 3154 TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]); 3155 for (unsigned j = 1, e = C.size(); j != e; ++j) { 3156 TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]); 3157 if (getConstraintGenerality(ThisFlavor) > 3158 getConstraintGenerality(Flavor)) { 3159 // This constraint letter is more general than the previous one, 3160 // use it. 3161 Flavor = ThisFlavor; 3162 Current = &C[j]; 3163 } 3164 } 3165 return *Current; 3166} 3167 3168 3169/// visitInlineAsm - Handle a call to an InlineAsm object. 3170/// 3171void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 3172 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 3173 3174 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 3175 MVT::Other); 3176 3177 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 3178 std::vector<MVT::ValueType> ConstraintVTs; 3179 3180 /// AsmNodeOperands - A list of pairs. The first element is a register, the 3181 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set 3182 /// if it is a def of that register. 3183 std::vector<SDOperand> AsmNodeOperands; 3184 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3185 AsmNodeOperands.push_back(AsmStr); 3186 3187 SDOperand Chain = getRoot(); 3188 SDOperand Flag; 3189 3190 // We fully assign registers here at isel time. This is not optimal, but 3191 // should work. For register classes that correspond to LLVM classes, we 3192 // could let the LLVM RA do its thing, but we currently don't. Do a prepass 3193 // over the constraints, collecting fixed registers that we know we can't use. 3194 std::set<unsigned> OutputRegs, InputRegs; 3195 unsigned OpNum = 1; 3196 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 3197 std::string ConstraintCode = 3198 GetMostGeneralConstraint(Constraints[i].Codes, TLI); 3199 3200 MVT::ValueType OpVT; 3201 3202 // Compute the value type for each operand and add it to ConstraintVTs. 3203 switch (Constraints[i].Type) { 3204 case InlineAsm::isOutput: 3205 if (!Constraints[i].isIndirectOutput) { 3206 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3207 OpVT = TLI.getValueType(I.getType()); 3208 } else { 3209 const Type *OpTy = I.getOperand(OpNum)->getType(); 3210 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType()); 3211 OpNum++; // Consumes a call operand. 3212 } 3213 break; 3214 case InlineAsm::isInput: 3215 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType()); 3216 OpNum++; // Consumes a call operand. 3217 break; 3218 case InlineAsm::isClobber: 3219 OpVT = MVT::Other; 3220 break; 3221 } 3222 3223 ConstraintVTs.push_back(OpVT); 3224 3225 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0) 3226 continue; // Not assigned a fixed reg. 3227 3228 // Build a list of regs that this operand uses. This always has a single 3229 // element for promoted/expanded operands. 3230 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT, 3231 false, false, 3232 OutputRegs, InputRegs); 3233 3234 switch (Constraints[i].Type) { 3235 case InlineAsm::isOutput: 3236 // We can't assign any other output to this register. 3237 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 3238 // If this is an early-clobber output, it cannot be assigned to the same 3239 // value as the input reg. 3240 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 3241 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 3242 break; 3243 case InlineAsm::isInput: 3244 // We can't assign any other input to this register. 3245 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 3246 break; 3247 case InlineAsm::isClobber: 3248 // Clobbered regs cannot be used as inputs or outputs. 3249 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 3250 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 3251 break; 3252 } 3253 } 3254 3255 // Loop over all of the inputs, copying the operand values into the 3256 // appropriate registers and processing the output regs. 3257 RegsForValue RetValRegs; 3258 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3259 OpNum = 1; 3260 3261 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 3262 std::string ConstraintCode = 3263 GetMostGeneralConstraint(Constraints[i].Codes, TLI); 3264 3265 switch (Constraints[i].Type) { 3266 case InlineAsm::isOutput: { 3267 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 3268 if (ConstraintCode.size() == 1) // not a physreg name. 3269 CTy = TLI.getConstraintType(ConstraintCode); 3270 3271 if (CTy == TargetLowering::C_Memory) { 3272 // Memory output. 3273 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 3274 3275 // Check that the operand (the address to store to) isn't a float. 3276 if (!MVT::isInteger(InOperandVal.getValueType())) 3277 assert(0 && "MATCH FAIL!"); 3278 3279 if (!Constraints[i].isIndirectOutput) 3280 assert(0 && "MATCH FAIL!"); 3281 3282 OpNum++; // Consumes a call operand. 3283 3284 // Extend/truncate to the right pointer type if needed. 3285 MVT::ValueType PtrType = TLI.getPointerTy(); 3286 if (InOperandVal.getValueType() < PtrType) 3287 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 3288 else if (InOperandVal.getValueType() > PtrType) 3289 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 3290 3291 // Add information to the INLINEASM node to know about this output. 3292 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3293 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 3294 AsmNodeOperands.push_back(InOperandVal); 3295 break; 3296 } 3297 3298 // Otherwise, this is a register output. 3299 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 3300 3301 // If this is an early-clobber output, or if there is an input 3302 // constraint that matches this, we need to reserve the input register 3303 // so no other inputs allocate to it. 3304 bool UsesInputRegister = false; 3305 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 3306 UsesInputRegister = true; 3307 3308 // Copy the output from the appropriate register. Find a register that 3309 // we can use. 3310 RegsForValue Regs = 3311 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 3312 true, UsesInputRegister, 3313 OutputRegs, InputRegs); 3314 if (Regs.Regs.empty()) { 3315 cerr << "Couldn't allocate output reg for contraint '" 3316 << ConstraintCode << "'!\n"; 3317 exit(1); 3318 } 3319 3320 if (!Constraints[i].isIndirectOutput) { 3321 assert(RetValRegs.Regs.empty() && 3322 "Cannot have multiple output constraints yet!"); 3323 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 3324 RetValRegs = Regs; 3325 } else { 3326 IndirectStoresToEmit.push_back(std::make_pair(Regs, 3327 I.getOperand(OpNum))); 3328 OpNum++; // Consumes a call operand. 3329 } 3330 3331 // Add information to the INLINEASM node to know that this register is 3332 // set. 3333 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands); 3334 break; 3335 } 3336 case InlineAsm::isInput: { 3337 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 3338 OpNum++; // Consumes a call operand. 3339 3340 if (isdigit(ConstraintCode[0])) { // Matching constraint? 3341 // If this is required to match an output register we have already set, 3342 // just use its register. 3343 unsigned OperandNo = atoi(ConstraintCode.c_str()); 3344 3345 // Scan until we find the definition we already emitted of this operand. 3346 // When we find it, create a RegsForValue operand. 3347 unsigned CurOp = 2; // The first operand. 3348 for (; OperandNo; --OperandNo) { 3349 // Advance to the next operand. 3350 unsigned NumOps = 3351 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3352 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3353 (NumOps & 7) == 4 /*MEM*/) && 3354 "Skipped past definitions?"); 3355 CurOp += (NumOps>>3)+1; 3356 } 3357 3358 unsigned NumOps = 3359 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3360 if ((NumOps & 7) == 2 /*REGDEF*/) { 3361 // Add NumOps>>3 registers to MatchedRegs. 3362 RegsForValue MatchedRegs; 3363 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3364 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3365 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3366 unsigned Reg = 3367 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3368 MatchedRegs.Regs.push_back(Reg); 3369 } 3370 3371 // Use the produced MatchedRegs object to 3372 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 3373 TLI.getPointerTy()); 3374 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3375 break; 3376 } else { 3377 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3378 assert(0 && "matching constraints for memory operands unimp"); 3379 } 3380 } 3381 3382 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 3383 if (ConstraintCode.size() == 1) // not a physreg name. 3384 CTy = TLI.getConstraintType(ConstraintCode); 3385 3386 if (CTy == TargetLowering::C_Other) { 3387 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 3388 ConstraintCode[0], DAG); 3389 if (!InOperandVal.Val) { 3390 cerr << "Invalid operand for inline asm constraint '" 3391 << ConstraintCode << "'!\n"; 3392 exit(1); 3393 } 3394 3395 // Add information to the INLINEASM node to know about this input. 3396 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 3397 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 3398 AsmNodeOperands.push_back(InOperandVal); 3399 break; 3400 } else if (CTy == TargetLowering::C_Memory) { 3401 // Memory input. 3402 3403 // If the operand is a float, spill to a constant pool entry to get its 3404 // address. 3405 if (ConstantFP *Val = dyn_cast<ConstantFP>(I.getOperand(OpNum-1))) 3406 InOperandVal = DAG.getConstantPool(Val, TLI.getPointerTy()); 3407 3408 if (!MVT::isInteger(InOperandVal.getValueType())) { 3409 cerr << "Match failed, cannot handle this yet!\n"; 3410 InOperandVal.Val->dump(); 3411 exit(1); 3412 } 3413 3414 // Extend/truncate to the right pointer type if needed. 3415 MVT::ValueType PtrType = TLI.getPointerTy(); 3416 if (InOperandVal.getValueType() < PtrType) 3417 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 3418 else if (InOperandVal.getValueType() > PtrType) 3419 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 3420 3421 // Add information to the INLINEASM node to know about this input. 3422 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3423 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 3424 AsmNodeOperands.push_back(InOperandVal); 3425 break; 3426 } 3427 3428 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 3429 3430 // Copy the input into the appropriate registers. 3431 RegsForValue InRegs = 3432 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 3433 false, true, OutputRegs, InputRegs); 3434 // FIXME: should be match fail. 3435 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!"); 3436 3437 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy()); 3438 3439 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); 3440 break; 3441 } 3442 case InlineAsm::isClobber: { 3443 RegsForValue ClobberedRegs = 3444 GetRegistersForValue(ConstraintCode, MVT::Other, false, false, 3445 OutputRegs, InputRegs); 3446 // Add the clobbered value to the operand list, so that the register 3447 // allocator is aware that the physreg got clobbered. 3448 if (!ClobberedRegs.Regs.empty()) 3449 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands); 3450 break; 3451 } 3452 } 3453 } 3454 3455 // Finish up input operands. 3456 AsmNodeOperands[0] = Chain; 3457 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3458 3459 Chain = DAG.getNode(ISD::INLINEASM, 3460 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3461 &AsmNodeOperands[0], AsmNodeOperands.size()); 3462 Flag = Chain.getValue(1); 3463 3464 // If this asm returns a register value, copy the result from that register 3465 // and set it as the value of the call. 3466 if (!RetValRegs.Regs.empty()) { 3467 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag); 3468 3469 // If the result of the inline asm is a vector, it may have the wrong 3470 // width/num elts. Make sure to convert it to the right type with 3471 // vbit_convert. 3472 if (Val.getValueType() == MVT::Vector) { 3473 const VectorType *VTy = cast<VectorType>(I.getType()); 3474 unsigned DesiredNumElts = VTy->getNumElements(); 3475 MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType()); 3476 3477 Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 3478 DAG.getConstant(DesiredNumElts, MVT::i32), 3479 DAG.getValueType(DesiredEltVT)); 3480 } 3481 3482 setValue(&I, Val); 3483 } 3484 3485 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3486 3487 // Process indirect outputs, first output all of the flagged copies out of 3488 // physregs. 3489 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3490 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3491 Value *Ptr = IndirectStoresToEmit[i].second; 3492 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 3493 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3494 } 3495 3496 // Emit the non-flagged stores from the physregs. 3497 SmallVector<SDOperand, 8> OutChains; 3498 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3499 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3500 getValue(StoresToEmit[i].second), 3501 StoresToEmit[i].second, 0)); 3502 if (!OutChains.empty()) 3503 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3504 &OutChains[0], OutChains.size()); 3505 DAG.setRoot(Chain); 3506} 3507 3508 3509void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3510 SDOperand Src = getValue(I.getOperand(0)); 3511 3512 MVT::ValueType IntPtr = TLI.getPointerTy(); 3513 3514 if (IntPtr < Src.getValueType()) 3515 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3516 else if (IntPtr > Src.getValueType()) 3517 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3518 3519 // Scale the source by the type size. 3520 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 3521 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3522 Src, getIntPtrConstant(ElementSize)); 3523 3524 TargetLowering::ArgListTy Args; 3525 TargetLowering::ArgListEntry Entry; 3526 Entry.Node = Src; 3527 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3528 Args.push_back(Entry); 3529 3530 std::pair<SDOperand,SDOperand> Result = 3531 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3532 DAG.getExternalSymbol("malloc", IntPtr), 3533 Args, DAG); 3534 setValue(&I, Result.first); // Pointers always fit in registers 3535 DAG.setRoot(Result.second); 3536} 3537 3538void SelectionDAGLowering::visitFree(FreeInst &I) { 3539 TargetLowering::ArgListTy Args; 3540 TargetLowering::ArgListEntry Entry; 3541 Entry.Node = getValue(I.getOperand(0)); 3542 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3543 Args.push_back(Entry); 3544 MVT::ValueType IntPtr = TLI.getPointerTy(); 3545 std::pair<SDOperand,SDOperand> Result = 3546 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3547 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3548 DAG.setRoot(Result.second); 3549} 3550 3551// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3552// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3553// instructions are special in various ways, which require special support to 3554// insert. The specified MachineInstr is created but not inserted into any 3555// basic blocks, and the scheduler passes ownership of it to this method. 3556MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3557 MachineBasicBlock *MBB) { 3558 cerr << "If a target marks an instruction with " 3559 << "'usesCustomDAGSchedInserter', it must implement " 3560 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3561 abort(); 3562 return 0; 3563} 3564 3565void SelectionDAGLowering::visitVAStart(CallInst &I) { 3566 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3567 getValue(I.getOperand(1)), 3568 DAG.getSrcValue(I.getOperand(1)))); 3569} 3570 3571void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3572 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3573 getValue(I.getOperand(0)), 3574 DAG.getSrcValue(I.getOperand(0))); 3575 setValue(&I, V); 3576 DAG.setRoot(V.getValue(1)); 3577} 3578 3579void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3580 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3581 getValue(I.getOperand(1)), 3582 DAG.getSrcValue(I.getOperand(1)))); 3583} 3584 3585void SelectionDAGLowering::visitVACopy(CallInst &I) { 3586 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3587 getValue(I.getOperand(1)), 3588 getValue(I.getOperand(2)), 3589 DAG.getSrcValue(I.getOperand(1)), 3590 DAG.getSrcValue(I.getOperand(2)))); 3591} 3592 3593/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either 3594/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate. 3595static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg, 3596 unsigned &i, SelectionDAG &DAG, 3597 TargetLowering &TLI) { 3598 if (TLI.getTypeAction(VT) != TargetLowering::Expand) 3599 return SDOperand(Arg, i++); 3600 3601 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3602 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3603 if (NumVals == 1) { 3604 return DAG.getNode(ISD::BIT_CONVERT, VT, 3605 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI)); 3606 } else if (NumVals == 2) { 3607 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 3608 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 3609 if (!TLI.isLittleEndian()) 3610 std::swap(Lo, Hi); 3611 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 3612 } else { 3613 // Value scalarized into many values. Unimp for now. 3614 assert(0 && "Cannot expand i64 -> i16 yet!"); 3615 } 3616 return SDOperand(); 3617} 3618 3619/// TargetLowering::LowerArguments - This is the default LowerArguments 3620/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3621/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3622/// integrated into SDISel. 3623std::vector<SDOperand> 3624TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3625 const FunctionType *FTy = F.getFunctionType(); 3626 const ParamAttrsList *Attrs = FTy->getParamAttrs(); 3627 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3628 std::vector<SDOperand> Ops; 3629 Ops.push_back(DAG.getRoot()); 3630 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3631 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3632 3633 // Add one result value for each formal argument. 3634 std::vector<MVT::ValueType> RetVals; 3635 unsigned j = 1; 3636 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3637 I != E; ++I, ++j) { 3638 MVT::ValueType VT = getValueType(I->getType()); 3639 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3640 unsigned OriginalAlignment = 3641 getTargetData()->getABITypeAlignment(I->getType()); 3642 3643 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3644 // that is zero extended! 3645 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt)) 3646 Flags &= ~(ISD::ParamFlags::SExt); 3647 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt)) 3648 Flags |= ISD::ParamFlags::SExt; 3649 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg)) 3650 Flags |= ISD::ParamFlags::InReg; 3651 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet)) 3652 Flags |= ISD::ParamFlags::StructReturn; 3653 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3654 3655 switch (getTypeAction(VT)) { 3656 default: assert(0 && "Unknown type action!"); 3657 case Legal: 3658 RetVals.push_back(VT); 3659 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3660 break; 3661 case Promote: 3662 RetVals.push_back(getTypeToTransformTo(VT)); 3663 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3664 break; 3665 case Expand: 3666 if (VT != MVT::Vector) { 3667 // If this is a large integer, it needs to be broken up into small 3668 // integers. Figure out what the destination type is and how many small 3669 // integers it turns into. 3670 MVT::ValueType NVT = getTypeToExpandTo(VT); 3671 unsigned NumVals = getNumElements(VT); 3672 for (unsigned i = 0; i != NumVals; ++i) { 3673 RetVals.push_back(NVT); 3674 // if it isn't first piece, alignment must be 1 3675 if (i > 0) 3676 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3677 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3678 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3679 } 3680 } else { 3681 // Otherwise, this is a vector type. We only support legal vectors 3682 // right now. 3683 unsigned NumElems = cast<VectorType>(I->getType())->getNumElements(); 3684 const Type *EltTy = cast<VectorType>(I->getType())->getElementType(); 3685 3686 // Figure out if there is a Packed type corresponding to this Vector 3687 // type. If so, convert to the vector type. 3688 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3689 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3690 RetVals.push_back(TVT); 3691 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3692 } else { 3693 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3694 } 3695 } 3696 break; 3697 } 3698 } 3699 3700 RetVals.push_back(MVT::Other); 3701 3702 // Create the node. 3703 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3704 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3705 &Ops[0], Ops.size()).Val; 3706 3707 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 3708 3709 // Set up the return result vector. 3710 Ops.clear(); 3711 unsigned i = 0; 3712 unsigned Idx = 1; 3713 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3714 ++I, ++Idx) { 3715 MVT::ValueType VT = getValueType(I->getType()); 3716 3717 switch (getTypeAction(VT)) { 3718 default: assert(0 && "Unknown type action!"); 3719 case Legal: 3720 Ops.push_back(SDOperand(Result, i++)); 3721 break; 3722 case Promote: { 3723 SDOperand Op(Result, i++); 3724 if (MVT::isInteger(VT)) { 3725 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt)) 3726 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3727 DAG.getValueType(VT)); 3728 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt)) 3729 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3730 DAG.getValueType(VT)); 3731 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3732 } else { 3733 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3734 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3735 } 3736 Ops.push_back(Op); 3737 break; 3738 } 3739 case Expand: 3740 if (VT != MVT::Vector) { 3741 // If this is a large integer or a floating point node that needs to be 3742 // expanded, it needs to be reassembled from small integers. Figure out 3743 // what the source elt type is and how many small integers it is. 3744 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this)); 3745 } else { 3746 // Otherwise, this is a vector type. We only support legal vectors 3747 // right now. 3748 const VectorType *PTy = cast<VectorType>(I->getType()); 3749 unsigned NumElems = PTy->getNumElements(); 3750 const Type *EltTy = PTy->getElementType(); 3751 3752 // Figure out if there is a Packed type corresponding to this Vector 3753 // type. If so, convert to the vector type. 3754 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3755 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3756 SDOperand N = SDOperand(Result, i++); 3757 // Handle copies from generic vectors to registers. 3758 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 3759 DAG.getConstant(NumElems, MVT::i32), 3760 DAG.getValueType(getValueType(EltTy))); 3761 Ops.push_back(N); 3762 } else { 3763 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3764 abort(); 3765 } 3766 } 3767 break; 3768 } 3769 } 3770 return Ops; 3771} 3772 3773 3774/// ExpandScalarCallArgs - Recursively expand call argument node by 3775/// bit_converting it or extract a pair of elements from the larger node. 3776static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg, 3777 unsigned Flags, 3778 SmallVector<SDOperand, 32> &Ops, 3779 SelectionDAG &DAG, 3780 TargetLowering &TLI, 3781 bool isFirst = true) { 3782 3783 if (TLI.getTypeAction(VT) != TargetLowering::Expand) { 3784 // if it isn't first piece, alignment must be 1 3785 if (!isFirst) 3786 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3787 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3788 Ops.push_back(Arg); 3789 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3790 return; 3791 } 3792 3793 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3794 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3795 if (NumVals == 1) { 3796 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg); 3797 ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst); 3798 } else if (NumVals == 2) { 3799 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3800 DAG.getConstant(0, TLI.getPointerTy())); 3801 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3802 DAG.getConstant(1, TLI.getPointerTy())); 3803 if (!TLI.isLittleEndian()) 3804 std::swap(Lo, Hi); 3805 ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst); 3806 ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false); 3807 } else { 3808 // Value scalarized into many values. Unimp for now. 3809 assert(0 && "Cannot expand i64 -> i16 yet!"); 3810 } 3811} 3812 3813/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3814/// implementation, which just inserts an ISD::CALL node, which is later custom 3815/// lowered by the target to something concrete. FIXME: When all targets are 3816/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3817std::pair<SDOperand, SDOperand> 3818TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 3819 bool RetTyIsSigned, bool isVarArg, 3820 unsigned CallingConv, bool isTailCall, 3821 SDOperand Callee, 3822 ArgListTy &Args, SelectionDAG &DAG) { 3823 SmallVector<SDOperand, 32> Ops; 3824 Ops.push_back(Chain); // Op#0 - Chain 3825 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3826 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3827 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3828 Ops.push_back(Callee); 3829 3830 // Handle all of the outgoing arguments. 3831 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3832 MVT::ValueType VT = getValueType(Args[i].Ty); 3833 SDOperand Op = Args[i].Node; 3834 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3835 unsigned OriginalAlignment = 3836 getTargetData()->getABITypeAlignment(Args[i].Ty); 3837 3838 if (Args[i].isSExt) 3839 Flags |= ISD::ParamFlags::SExt; 3840 if (Args[i].isZExt) 3841 Flags |= ISD::ParamFlags::ZExt; 3842 if (Args[i].isInReg) 3843 Flags |= ISD::ParamFlags::InReg; 3844 if (Args[i].isSRet) 3845 Flags |= ISD::ParamFlags::StructReturn; 3846 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 3847 3848 switch (getTypeAction(VT)) { 3849 default: assert(0 && "Unknown type action!"); 3850 case Legal: 3851 Ops.push_back(Op); 3852 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3853 break; 3854 case Promote: 3855 if (MVT::isInteger(VT)) { 3856 unsigned ExtOp; 3857 if (Args[i].isSExt) 3858 ExtOp = ISD::SIGN_EXTEND; 3859 else if (Args[i].isZExt) 3860 ExtOp = ISD::ZERO_EXTEND; 3861 else 3862 ExtOp = ISD::ANY_EXTEND; 3863 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3864 } else { 3865 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3866 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 3867 } 3868 Ops.push_back(Op); 3869 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3870 break; 3871 case Expand: 3872 if (VT != MVT::Vector) { 3873 // If this is a large integer, it needs to be broken down into small 3874 // integers. Figure out what the source elt type is and how many small 3875 // integers it is. 3876 ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this); 3877 } else { 3878 // Otherwise, this is a vector type. We only support legal vectors 3879 // right now. 3880 const VectorType *PTy = cast<VectorType>(Args[i].Ty); 3881 unsigned NumElems = PTy->getNumElements(); 3882 const Type *EltTy = PTy->getElementType(); 3883 3884 // Figure out if there is a Packed type corresponding to this Vector 3885 // type. If so, convert to the vector type. 3886 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3887 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3888 // Insert a VBIT_CONVERT of the MVT::Vector type to the vector type. 3889 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 3890 Ops.push_back(Op); 3891 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3892 } else { 3893 assert(0 && "Don't support illegal by-val vector call args yet!"); 3894 abort(); 3895 } 3896 } 3897 break; 3898 } 3899 } 3900 3901 // Figure out the result value types. 3902 SmallVector<MVT::ValueType, 4> RetTys; 3903 3904 if (RetTy != Type::VoidTy) { 3905 MVT::ValueType VT = getValueType(RetTy); 3906 switch (getTypeAction(VT)) { 3907 default: assert(0 && "Unknown type action!"); 3908 case Legal: 3909 RetTys.push_back(VT); 3910 break; 3911 case Promote: 3912 RetTys.push_back(getTypeToTransformTo(VT)); 3913 break; 3914 case Expand: 3915 if (VT != MVT::Vector) { 3916 // If this is a large integer, it needs to be reassembled from small 3917 // integers. Figure out what the source elt type is and how many small 3918 // integers it is. 3919 MVT::ValueType NVT = getTypeToExpandTo(VT); 3920 unsigned NumVals = getNumElements(VT); 3921 for (unsigned i = 0; i != NumVals; ++i) 3922 RetTys.push_back(NVT); 3923 } else { 3924 // Otherwise, this is a vector type. We only support legal vectors 3925 // right now. 3926 const VectorType *PTy = cast<VectorType>(RetTy); 3927 unsigned NumElems = PTy->getNumElements(); 3928 const Type *EltTy = PTy->getElementType(); 3929 3930 // Figure out if there is a Packed type corresponding to this Vector 3931 // type. If so, convert to the vector type. 3932 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3933 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3934 RetTys.push_back(TVT); 3935 } else { 3936 assert(0 && "Don't support illegal by-val vector call results yet!"); 3937 abort(); 3938 } 3939 } 3940 } 3941 } 3942 3943 RetTys.push_back(MVT::Other); // Always has a chain. 3944 3945 // Finally, create the CALL node. 3946 SDOperand Res = DAG.getNode(ISD::CALL, 3947 DAG.getVTList(&RetTys[0], RetTys.size()), 3948 &Ops[0], Ops.size()); 3949 3950 // This returns a pair of operands. The first element is the 3951 // return value for the function (if RetTy is not VoidTy). The second 3952 // element is the outgoing token chain. 3953 SDOperand ResVal; 3954 if (RetTys.size() != 1) { 3955 MVT::ValueType VT = getValueType(RetTy); 3956 if (RetTys.size() == 2) { 3957 ResVal = Res; 3958 3959 // If this value was promoted, truncate it down. 3960 if (ResVal.getValueType() != VT) { 3961 if (VT == MVT::Vector) { 3962 // Insert a VBIT_CONVERT to convert from the packed result type to the 3963 // MVT::Vector type. 3964 unsigned NumElems = cast<VectorType>(RetTy)->getNumElements(); 3965 const Type *EltTy = cast<VectorType>(RetTy)->getElementType(); 3966 3967 // Figure out if there is a Packed type corresponding to this Vector 3968 // type. If so, convert to the vector type. 3969 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems); 3970 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3971 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 3972 // "N x PTyElementVT" MVT::Vector type. 3973 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 3974 DAG.getConstant(NumElems, MVT::i32), 3975 DAG.getValueType(getValueType(EltTy))); 3976 } else { 3977 abort(); 3978 } 3979 } else if (MVT::isInteger(VT)) { 3980 unsigned AssertOp = ISD::AssertSext; 3981 if (!RetTyIsSigned) 3982 AssertOp = ISD::AssertZext; 3983 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 3984 DAG.getValueType(VT)); 3985 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 3986 } else { 3987 assert(MVT::isFloatingPoint(VT)); 3988 if (getTypeAction(VT) == Expand) 3989 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal); 3990 else 3991 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 3992 } 3993 } 3994 } else if (RetTys.size() == 3) { 3995 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 3996 Res.getValue(0), Res.getValue(1)); 3997 3998 } else { 3999 assert(0 && "Case not handled yet!"); 4000 } 4001 } 4002 4003 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 4004} 4005 4006SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4007 assert(0 && "LowerOperation not implemented for this target!"); 4008 abort(); 4009 return SDOperand(); 4010} 4011 4012SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4013 SelectionDAG &DAG) { 4014 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4015 abort(); 4016 return SDOperand(); 4017} 4018 4019/// getMemsetValue - Vectorized representation of the memset value 4020/// operand. 4021static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4022 SelectionDAG &DAG) { 4023 MVT::ValueType CurVT = VT; 4024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4025 uint64_t Val = C->getValue() & 255; 4026 unsigned Shift = 8; 4027 while (CurVT != MVT::i8) { 4028 Val = (Val << Shift) | Val; 4029 Shift <<= 1; 4030 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4031 } 4032 return DAG.getConstant(Val, VT); 4033 } else { 4034 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4035 unsigned Shift = 8; 4036 while (CurVT != MVT::i8) { 4037 Value = 4038 DAG.getNode(ISD::OR, VT, 4039 DAG.getNode(ISD::SHL, VT, Value, 4040 DAG.getConstant(Shift, MVT::i8)), Value); 4041 Shift <<= 1; 4042 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4043 } 4044 4045 return Value; 4046 } 4047} 4048 4049/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4050/// used when a memcpy is turned into a memset when the source is a constant 4051/// string ptr. 4052static SDOperand getMemsetStringVal(MVT::ValueType VT, 4053 SelectionDAG &DAG, TargetLowering &TLI, 4054 std::string &Str, unsigned Offset) { 4055 uint64_t Val = 0; 4056 unsigned MSB = getSizeInBits(VT) / 8; 4057 if (TLI.isLittleEndian()) 4058 Offset = Offset + MSB - 1; 4059 for (unsigned i = 0; i != MSB; ++i) { 4060 Val = (Val << 8) | (unsigned char)Str[Offset]; 4061 Offset += TLI.isLittleEndian() ? -1 : 1; 4062 } 4063 return DAG.getConstant(Val, VT); 4064} 4065 4066/// getMemBasePlusOffset - Returns base and offset node for the 4067static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4068 SelectionDAG &DAG, TargetLowering &TLI) { 4069 MVT::ValueType VT = Base.getValueType(); 4070 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4071} 4072 4073/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4074/// to replace the memset / memcpy is below the threshold. It also returns the 4075/// types of the sequence of memory ops to perform memset / memcpy. 4076static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4077 unsigned Limit, uint64_t Size, 4078 unsigned Align, TargetLowering &TLI) { 4079 MVT::ValueType VT; 4080 4081 if (TLI.allowsUnalignedMemoryAccesses()) { 4082 VT = MVT::i64; 4083 } else { 4084 switch (Align & 7) { 4085 case 0: 4086 VT = MVT::i64; 4087 break; 4088 case 4: 4089 VT = MVT::i32; 4090 break; 4091 case 2: 4092 VT = MVT::i16; 4093 break; 4094 default: 4095 VT = MVT::i8; 4096 break; 4097 } 4098 } 4099 4100 MVT::ValueType LVT = MVT::i64; 4101 while (!TLI.isTypeLegal(LVT)) 4102 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4103 assert(MVT::isInteger(LVT)); 4104 4105 if (VT > LVT) 4106 VT = LVT; 4107 4108 unsigned NumMemOps = 0; 4109 while (Size != 0) { 4110 unsigned VTSize = getSizeInBits(VT) / 8; 4111 while (VTSize > Size) { 4112 VT = (MVT::ValueType)((unsigned)VT - 1); 4113 VTSize >>= 1; 4114 } 4115 assert(MVT::isInteger(VT)); 4116 4117 if (++NumMemOps > Limit) 4118 return false; 4119 MemOps.push_back(VT); 4120 Size -= VTSize; 4121 } 4122 4123 return true; 4124} 4125 4126void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4127 SDOperand Op1 = getValue(I.getOperand(1)); 4128 SDOperand Op2 = getValue(I.getOperand(2)); 4129 SDOperand Op3 = getValue(I.getOperand(3)); 4130 SDOperand Op4 = getValue(I.getOperand(4)); 4131 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4132 if (Align == 0) Align = 1; 4133 4134 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4135 std::vector<MVT::ValueType> MemOps; 4136 4137 // Expand memset / memcpy to a series of load / store ops 4138 // if the size operand falls below a certain threshold. 4139 SmallVector<SDOperand, 8> OutChains; 4140 switch (Op) { 4141 default: break; // Do nothing for now. 4142 case ISD::MEMSET: { 4143 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4144 Size->getValue(), Align, TLI)) { 4145 unsigned NumMemOps = MemOps.size(); 4146 unsigned Offset = 0; 4147 for (unsigned i = 0; i < NumMemOps; i++) { 4148 MVT::ValueType VT = MemOps[i]; 4149 unsigned VTSize = getSizeInBits(VT) / 8; 4150 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4151 SDOperand Store = DAG.getStore(getRoot(), Value, 4152 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4153 I.getOperand(1), Offset); 4154 OutChains.push_back(Store); 4155 Offset += VTSize; 4156 } 4157 } 4158 break; 4159 } 4160 case ISD::MEMCPY: { 4161 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4162 Size->getValue(), Align, TLI)) { 4163 unsigned NumMemOps = MemOps.size(); 4164 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4165 GlobalAddressSDNode *G = NULL; 4166 std::string Str; 4167 bool CopyFromStr = false; 4168 4169 if (Op2.getOpcode() == ISD::GlobalAddress) 4170 G = cast<GlobalAddressSDNode>(Op2); 4171 else if (Op2.getOpcode() == ISD::ADD && 4172 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4173 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4174 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4175 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4176 } 4177 if (G) { 4178 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4179 if (GV && GV->isConstant()) { 4180 Str = GV->getStringValue(false); 4181 if (!Str.empty()) { 4182 CopyFromStr = true; 4183 SrcOff += SrcDelta; 4184 } 4185 } 4186 } 4187 4188 for (unsigned i = 0; i < NumMemOps; i++) { 4189 MVT::ValueType VT = MemOps[i]; 4190 unsigned VTSize = getSizeInBits(VT) / 8; 4191 SDOperand Value, Chain, Store; 4192 4193 if (CopyFromStr) { 4194 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4195 Chain = getRoot(); 4196 Store = 4197 DAG.getStore(Chain, Value, 4198 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4199 I.getOperand(1), DstOff); 4200 } else { 4201 Value = DAG.getLoad(VT, getRoot(), 4202 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4203 I.getOperand(2), SrcOff); 4204 Chain = Value.getValue(1); 4205 Store = 4206 DAG.getStore(Chain, Value, 4207 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4208 I.getOperand(1), DstOff); 4209 } 4210 OutChains.push_back(Store); 4211 SrcOff += VTSize; 4212 DstOff += VTSize; 4213 } 4214 } 4215 break; 4216 } 4217 } 4218 4219 if (!OutChains.empty()) { 4220 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4221 &OutChains[0], OutChains.size())); 4222 return; 4223 } 4224 } 4225 4226 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 4227} 4228 4229//===----------------------------------------------------------------------===// 4230// SelectionDAGISel code 4231//===----------------------------------------------------------------------===// 4232 4233unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4234 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4235} 4236 4237void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4238 AU.addRequired<AliasAnalysis>(); 4239 AU.setPreservesAll(); 4240} 4241 4242 4243 4244bool SelectionDAGISel::runOnFunction(Function &Fn) { 4245 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4246 RegMap = MF.getSSARegMap(); 4247 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4248 4249 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4250 4251 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4252 SelectBasicBlock(I, MF, FuncInfo); 4253 4254 // Add function live-ins to entry block live-in set. 4255 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4256 BB = FuncInfo.MBBMap[EntryBB]; 4257 if (!MF.livein_empty()) 4258 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4259 E = MF.livein_end(); I != E; ++I) 4260 BB->addLiveIn(I->first); 4261 4262 return true; 4263} 4264 4265SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4266 unsigned Reg) { 4267 SDOperand Op = getValue(V); 4268 assert((Op.getOpcode() != ISD::CopyFromReg || 4269 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4270 "Copy from a reg to the same reg!"); 4271 4272 // If this type is not legal, we must make sure to not create an invalid 4273 // register use. 4274 MVT::ValueType SrcVT = Op.getValueType(); 4275 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 4276 if (SrcVT == DestVT) { 4277 return DAG.getCopyToReg(getRoot(), Reg, Op); 4278 } else if (SrcVT == MVT::Vector) { 4279 // Handle copies from generic vectors to registers. 4280 MVT::ValueType PTyElementVT, PTyLegalElementVT; 4281 unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()), 4282 PTyElementVT, PTyLegalElementVT); 4283 4284 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 4285 // MVT::Vector type. 4286 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 4287 DAG.getConstant(NE, MVT::i32), 4288 DAG.getValueType(PTyElementVT)); 4289 4290 // Loop over all of the elements of the resultant vector, 4291 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 4292 // copying them into output registers. 4293 SmallVector<SDOperand, 8> OutChains; 4294 SDOperand Root = getRoot(); 4295 for (unsigned i = 0; i != NE; ++i) { 4296 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 4297 Op, DAG.getConstant(i, TLI.getPointerTy())); 4298 if (PTyElementVT == PTyLegalElementVT) { 4299 // Elements are legal. 4300 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 4301 } else if (PTyLegalElementVT > PTyElementVT) { 4302 // Elements are promoted. 4303 if (MVT::isFloatingPoint(PTyLegalElementVT)) 4304 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 4305 else 4306 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 4307 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 4308 } else { 4309 // Elements are expanded. 4310 // The src value is expanded into multiple registers. 4311 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 4312 Elt, DAG.getConstant(0, TLI.getPointerTy())); 4313 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 4314 Elt, DAG.getConstant(1, TLI.getPointerTy())); 4315 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 4316 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 4317 } 4318 } 4319 return DAG.getNode(ISD::TokenFactor, MVT::Other, 4320 &OutChains[0], OutChains.size()); 4321 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) { 4322 // The src value is promoted to the register. 4323 if (MVT::isFloatingPoint(SrcVT)) 4324 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 4325 else 4326 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 4327 return DAG.getCopyToReg(getRoot(), Reg, Op); 4328 } else { 4329 DestVT = TLI.getTypeToExpandTo(SrcVT); 4330 unsigned NumVals = TLI.getNumElements(SrcVT); 4331 if (NumVals == 1) 4332 return DAG.getCopyToReg(getRoot(), Reg, 4333 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); 4334 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 4335 // The src value is expanded into multiple registers. 4336 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 4337 Op, DAG.getConstant(0, TLI.getPointerTy())); 4338 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 4339 Op, DAG.getConstant(1, TLI.getPointerTy())); 4340 Op = DAG.getCopyToReg(getRoot(), Reg, Lo); 4341 return DAG.getCopyToReg(Op, Reg+1, Hi); 4342 } 4343} 4344 4345void SelectionDAGISel:: 4346LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4347 std::vector<SDOperand> &UnorderedChains) { 4348 // If this is the entry block, emit arguments. 4349 Function &F = *LLVMBB->getParent(); 4350 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4351 SDOperand OldRoot = SDL.DAG.getRoot(); 4352 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4353 4354 unsigned a = 0; 4355 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4356 AI != E; ++AI, ++a) 4357 if (!AI->use_empty()) { 4358 SDL.setValue(AI, Args[a]); 4359 4360 // If this argument is live outside of the entry block, insert a copy from 4361 // whereever we got it to the vreg that other BB's will reference it as. 4362 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4363 if (VMI != FuncInfo.ValueMap.end()) { 4364 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4365 UnorderedChains.push_back(Copy); 4366 } 4367 } 4368 4369 // Finally, if the target has anything special to do, allow it to do so. 4370 // FIXME: this should insert code into the DAG! 4371 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4372} 4373 4374void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4375 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4376 FunctionLoweringInfo &FuncInfo) { 4377 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 4378 4379 std::vector<SDOperand> UnorderedChains; 4380 4381 // Lower any arguments needed in this block if this is the entry block. 4382 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4383 LowerArguments(LLVMBB, SDL, UnorderedChains); 4384 4385 BB = FuncInfo.MBBMap[LLVMBB]; 4386 SDL.setCurrentBasicBlock(BB); 4387 4388 // Lower all of the non-terminator instructions. 4389 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4390 I != E; ++I) 4391 SDL.visit(*I); 4392 4393 // Lower call part of invoke. 4394 InvokeInst *Invoke = dyn_cast<InvokeInst>(LLVMBB->getTerminator()); 4395 if (Invoke) SDL.visitInvoke(*Invoke, false); 4396 4397 // Ensure that all instructions which are used outside of their defining 4398 // blocks are available as virtual registers. 4399 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4400 if (!I->use_empty() && !isa<PHINode>(I)) { 4401 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4402 if (VMI != FuncInfo.ValueMap.end()) 4403 UnorderedChains.push_back( 4404 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4405 } 4406 4407 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4408 // ensure constants are generated when needed. Remember the virtual registers 4409 // that need to be added to the Machine PHI nodes as input. We cannot just 4410 // directly add them, because expansion might result in multiple MBB's for one 4411 // BB. As such, the start of the BB might correspond to a different MBB than 4412 // the end. 4413 // 4414 TerminatorInst *TI = LLVMBB->getTerminator(); 4415 4416 // Emit constants only once even if used by multiple PHI nodes. 4417 std::map<Constant*, unsigned> ConstantsOut; 4418 4419 // Vector bool would be better, but vector<bool> is really slow. 4420 std::vector<unsigned char> SuccsHandled; 4421 if (TI->getNumSuccessors()) 4422 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4423 4424 // Check successor nodes PHI nodes that expect a constant to be available from 4425 // this block. 4426 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4427 BasicBlock *SuccBB = TI->getSuccessor(succ); 4428 if (!isa<PHINode>(SuccBB->begin())) continue; 4429 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4430 4431 // If this terminator has multiple identical successors (common for 4432 // switches), only handle each succ once. 4433 unsigned SuccMBBNo = SuccMBB->getNumber(); 4434 if (SuccsHandled[SuccMBBNo]) continue; 4435 SuccsHandled[SuccMBBNo] = true; 4436 4437 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4438 PHINode *PN; 4439 4440 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4441 // nodes and Machine PHI nodes, but the incoming operands have not been 4442 // emitted yet. 4443 for (BasicBlock::iterator I = SuccBB->begin(); 4444 (PN = dyn_cast<PHINode>(I)); ++I) { 4445 // Ignore dead phi's. 4446 if (PN->use_empty()) continue; 4447 4448 unsigned Reg; 4449 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4450 4451 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4452 unsigned &RegOut = ConstantsOut[C]; 4453 if (RegOut == 0) { 4454 RegOut = FuncInfo.CreateRegForValue(C); 4455 UnorderedChains.push_back( 4456 SDL.CopyValueToVirtualRegister(C, RegOut)); 4457 } 4458 Reg = RegOut; 4459 } else { 4460 Reg = FuncInfo.ValueMap[PHIOp]; 4461 if (Reg == 0) { 4462 assert(isa<AllocaInst>(PHIOp) && 4463 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4464 "Didn't codegen value into a register!??"); 4465 Reg = FuncInfo.CreateRegForValue(PHIOp); 4466 UnorderedChains.push_back( 4467 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4468 } 4469 } 4470 4471 // Remember that this register needs to added to the machine PHI node as 4472 // the input for this MBB. 4473 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4474 unsigned NumElements; 4475 if (VT != MVT::Vector) 4476 NumElements = TLI.getNumElements(VT); 4477 else { 4478 MVT::ValueType VT1,VT2; 4479 NumElements = 4480 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()), 4481 VT1, VT2); 4482 } 4483 for (unsigned i = 0, e = NumElements; i != e; ++i) 4484 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4485 } 4486 } 4487 ConstantsOut.clear(); 4488 4489 // Turn all of the unordered chains into one factored node. 4490 if (!UnorderedChains.empty()) { 4491 SDOperand Root = SDL.getRoot(); 4492 if (Root.getOpcode() != ISD::EntryToken) { 4493 unsigned i = 0, e = UnorderedChains.size(); 4494 for (; i != e; ++i) { 4495 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4496 if (UnorderedChains[i].Val->getOperand(0) == Root) 4497 break; // Don't add the root if we already indirectly depend on it. 4498 } 4499 4500 if (i == e) 4501 UnorderedChains.push_back(Root); 4502 } 4503 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4504 &UnorderedChains[0], UnorderedChains.size())); 4505 } 4506 4507 // Lower the terminator after the copies are emitted. 4508 if (Invoke) { 4509 // Just the branch part of invoke. 4510 SDL.visitInvoke(*Invoke, true); 4511 } else { 4512 SDL.visit(*LLVMBB->getTerminator()); 4513 } 4514 4515 // Copy over any CaseBlock records that may now exist due to SwitchInst 4516 // lowering, as well as any jump table information. 4517 SwitchCases.clear(); 4518 SwitchCases = SDL.SwitchCases; 4519 JTCases.clear(); 4520 JTCases = SDL.JTCases; 4521 BitTestCases.clear(); 4522 BitTestCases = SDL.BitTestCases; 4523 4524 // Make sure the root of the DAG is up-to-date. 4525 DAG.setRoot(SDL.getRoot()); 4526} 4527 4528void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4529 // Get alias analysis for load/store combining. 4530 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4531 4532 // Run the DAG combiner in pre-legalize mode. 4533 DAG.Combine(false, AA); 4534 4535 DOUT << "Lowered selection DAG:\n"; 4536 DEBUG(DAG.dump()); 4537 4538 // Second step, hack on the DAG until it only uses operations and types that 4539 // the target supports. 4540 DAG.Legalize(); 4541 4542 DOUT << "Legalized selection DAG:\n"; 4543 DEBUG(DAG.dump()); 4544 4545 // Run the DAG combiner in post-legalize mode. 4546 DAG.Combine(true, AA); 4547 4548 if (ViewISelDAGs) DAG.viewGraph(); 4549 4550 // Third, instruction select all of the operations to machine code, adding the 4551 // code to the MachineBasicBlock. 4552 InstructionSelectBasicBlock(DAG); 4553 4554 DOUT << "Selected machine code:\n"; 4555 DEBUG(BB->dump()); 4556} 4557 4558void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4559 FunctionLoweringInfo &FuncInfo) { 4560 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4561 { 4562 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4563 CurDAG = &DAG; 4564 4565 // First step, lower LLVM code to some DAG. This DAG may use operations and 4566 // types that are not supported by the target. 4567 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4568 4569 // Second step, emit the lowered DAG as machine code. 4570 CodeGenAndEmitDAG(DAG); 4571 } 4572 4573 DOUT << "Total amount of phi nodes to update: " 4574 << PHINodesToUpdate.size() << "\n"; 4575 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4576 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4577 << ", " << PHINodesToUpdate[i].second << ")\n";); 4578 4579 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4580 // PHI nodes in successors. 4581 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4582 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4583 MachineInstr *PHI = PHINodesToUpdate[i].first; 4584 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4585 "This is not a machine PHI node that we are updating!"); 4586 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4587 PHI->addMachineBasicBlockOperand(BB); 4588 } 4589 return; 4590 } 4591 4592 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4593 // Lower header first, if it wasn't already lowered 4594 if (!BitTestCases[i].Emitted) { 4595 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4596 CurDAG = &HSDAG; 4597 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4598 // Set the current basic block to the mbb we wish to insert the code into 4599 BB = BitTestCases[i].Parent; 4600 HSDL.setCurrentBasicBlock(BB); 4601 // Emit the code 4602 HSDL.visitBitTestHeader(BitTestCases[i]); 4603 HSDAG.setRoot(HSDL.getRoot()); 4604 CodeGenAndEmitDAG(HSDAG); 4605 } 4606 4607 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4608 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4609 CurDAG = &BSDAG; 4610 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo); 4611 // Set the current basic block to the mbb we wish to insert the code into 4612 BB = BitTestCases[i].Cases[j].ThisBB; 4613 BSDL.setCurrentBasicBlock(BB); 4614 // Emit the code 4615 if (j+1 != ej) 4616 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4617 BitTestCases[i].Reg, 4618 BitTestCases[i].Cases[j]); 4619 else 4620 BSDL.visitBitTestCase(BitTestCases[i].Default, 4621 BitTestCases[i].Reg, 4622 BitTestCases[i].Cases[j]); 4623 4624 4625 BSDAG.setRoot(BSDL.getRoot()); 4626 CodeGenAndEmitDAG(BSDAG); 4627 } 4628 4629 // Update PHI Nodes 4630 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4631 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4632 MachineBasicBlock *PHIBB = PHI->getParent(); 4633 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4634 "This is not a machine PHI node that we are updating!"); 4635 // This is "default" BB. We have two jumps to it. From "header" BB and 4636 // from last "case" BB. 4637 if (PHIBB == BitTestCases[i].Default) { 4638 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4639 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4640 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4641 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4642 } 4643 // One of "cases" BB. 4644 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4645 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4646 if (cBB->succ_end() != 4647 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4648 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4649 PHI->addMachineBasicBlockOperand(cBB); 4650 } 4651 } 4652 } 4653 } 4654 4655 // If the JumpTable record is filled in, then we need to emit a jump table. 4656 // Updating the PHI nodes is tricky in this case, since we need to determine 4657 // whether the PHI is a successor of the range check MBB or the jump table MBB 4658 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4659 // Lower header first, if it wasn't already lowered 4660 if (!JTCases[i].first.Emitted) { 4661 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4662 CurDAG = &HSDAG; 4663 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo); 4664 // Set the current basic block to the mbb we wish to insert the code into 4665 BB = JTCases[i].first.HeaderBB; 4666 HSDL.setCurrentBasicBlock(BB); 4667 // Emit the code 4668 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4669 HSDAG.setRoot(HSDL.getRoot()); 4670 CodeGenAndEmitDAG(HSDAG); 4671 } 4672 4673 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4674 CurDAG = &JSDAG; 4675 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo); 4676 // Set the current basic block to the mbb we wish to insert the code into 4677 BB = JTCases[i].second.MBB; 4678 JSDL.setCurrentBasicBlock(BB); 4679 // Emit the code 4680 JSDL.visitJumpTable(JTCases[i].second); 4681 JSDAG.setRoot(JSDL.getRoot()); 4682 CodeGenAndEmitDAG(JSDAG); 4683 4684 // Update PHI Nodes 4685 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4686 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4687 MachineBasicBlock *PHIBB = PHI->getParent(); 4688 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4689 "This is not a machine PHI node that we are updating!"); 4690 // "default" BB. We can go there only from header BB. 4691 if (PHIBB == JTCases[i].second.Default) { 4692 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4693 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4694 } 4695 // JT BB. Just iterate over successors here 4696 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4697 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4698 PHI->addMachineBasicBlockOperand(BB); 4699 } 4700 } 4701 } 4702 4703 // If the switch block involved a branch to one of the actual successors, we 4704 // need to update PHI nodes in that block. 4705 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4706 MachineInstr *PHI = PHINodesToUpdate[i].first; 4707 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4708 "This is not a machine PHI node that we are updating!"); 4709 if (BB->isSuccessor(PHI->getParent())) { 4710 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4711 PHI->addMachineBasicBlockOperand(BB); 4712 } 4713 } 4714 4715 // If we generated any switch lowering information, build and codegen any 4716 // additional DAGs necessary. 4717 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4718 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4719 CurDAG = &SDAG; 4720 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4721 4722 // Set the current basic block to the mbb we wish to insert the code into 4723 BB = SwitchCases[i].ThisBB; 4724 SDL.setCurrentBasicBlock(BB); 4725 4726 // Emit the code 4727 SDL.visitSwitchCase(SwitchCases[i]); 4728 SDAG.setRoot(SDL.getRoot()); 4729 CodeGenAndEmitDAG(SDAG); 4730 4731 // Handle any PHI nodes in successors of this chunk, as if we were coming 4732 // from the original BB before switch expansion. Note that PHI nodes can 4733 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4734 // handle them the right number of times. 4735 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4736 for (MachineBasicBlock::iterator Phi = BB->begin(); 4737 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4738 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4739 for (unsigned pn = 0; ; ++pn) { 4740 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4741 if (PHINodesToUpdate[pn].first == Phi) { 4742 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4743 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4744 break; 4745 } 4746 } 4747 } 4748 4749 // Don't process RHS if same block as LHS. 4750 if (BB == SwitchCases[i].FalseBB) 4751 SwitchCases[i].FalseBB = 0; 4752 4753 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4754 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4755 SwitchCases[i].FalseBB = 0; 4756 } 4757 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4758 } 4759} 4760 4761 4762//===----------------------------------------------------------------------===// 4763/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4764/// target node in the graph. 4765void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4766 if (ViewSchedDAGs) DAG.viewGraph(); 4767 4768 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4769 4770 if (!Ctor) { 4771 Ctor = ISHeuristic; 4772 RegisterScheduler::setDefault(Ctor); 4773 } 4774 4775 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4776 BB = SL->Run(); 4777 delete SL; 4778} 4779 4780 4781HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4782 return new HazardRecognizer(); 4783} 4784 4785//===----------------------------------------------------------------------===// 4786// Helper functions used by the generated instruction selector. 4787//===----------------------------------------------------------------------===// 4788// Calls to these methods are generated by tblgen. 4789 4790/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4791/// the dag combiner simplified the 255, we still want to match. RHS is the 4792/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4793/// specified in the .td file (e.g. 255). 4794bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4795 int64_t DesiredMaskS) { 4796 uint64_t ActualMask = RHS->getValue(); 4797 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4798 4799 // If the actual mask exactly matches, success! 4800 if (ActualMask == DesiredMask) 4801 return true; 4802 4803 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4804 if (ActualMask & ~DesiredMask) 4805 return false; 4806 4807 // Otherwise, the DAG Combiner may have proven that the value coming in is 4808 // either already zero or is not demanded. Check for known zero input bits. 4809 uint64_t NeededMask = DesiredMask & ~ActualMask; 4810 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask)) 4811 return true; 4812 4813 // TODO: check to see if missing bits are just not demanded. 4814 4815 // Otherwise, this pattern doesn't match. 4816 return false; 4817} 4818 4819/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4820/// the dag combiner simplified the 255, we still want to match. RHS is the 4821/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4822/// specified in the .td file (e.g. 255). 4823bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4824 int64_t DesiredMaskS) { 4825 uint64_t ActualMask = RHS->getValue(); 4826 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4827 4828 // If the actual mask exactly matches, success! 4829 if (ActualMask == DesiredMask) 4830 return true; 4831 4832 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4833 if (ActualMask & ~DesiredMask) 4834 return false; 4835 4836 // Otherwise, the DAG Combiner may have proven that the value coming in is 4837 // either already zero or is not demanded. Check for known zero input bits. 4838 uint64_t NeededMask = DesiredMask & ~ActualMask; 4839 4840 uint64_t KnownZero, KnownOne; 4841 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4842 4843 // If all the missing bits in the or are already known to be set, match! 4844 if ((NeededMask & KnownOne) == NeededMask) 4845 return true; 4846 4847 // TODO: check to see if missing bits are just not demanded. 4848 4849 // Otherwise, this pattern doesn't match. 4850 return false; 4851} 4852 4853 4854/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4855/// by tblgen. Others should not call it. 4856void SelectionDAGISel:: 4857SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4858 std::vector<SDOperand> InOps; 4859 std::swap(InOps, Ops); 4860 4861 Ops.push_back(InOps[0]); // input chain. 4862 Ops.push_back(InOps[1]); // input asm string. 4863 4864 unsigned i = 2, e = InOps.size(); 4865 if (InOps[e-1].getValueType() == MVT::Flag) 4866 --e; // Don't process a flag operand if it is here. 4867 4868 while (i != e) { 4869 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4870 if ((Flags & 7) != 4 /*MEM*/) { 4871 // Just skip over this operand, copying the operands verbatim. 4872 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4873 i += (Flags >> 3) + 1; 4874 } else { 4875 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4876 // Otherwise, this is a memory operand. Ask the target to select it. 4877 std::vector<SDOperand> SelOps; 4878 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4879 cerr << "Could not match memory address. Inline asm failure!\n"; 4880 exit(1); 4881 } 4882 4883 // Add this to the output node. 4884 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 4885 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 4886 IntPtrTy)); 4887 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4888 i += 2; 4889 } 4890 } 4891 4892 // Add the flag input back if present. 4893 if (e != InOps.size()) 4894 Ops.push_back(InOps.back()); 4895} 4896