SelectionDAGISel.cpp revision fd3f6351035f6bf1a6bfc851da00c0fb24d6db09
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Transforms/Utils/BasicBlockUtils.h" 47#include "llvm/Support/Compiler.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/Timer.h" 51#include "llvm/Support/raw_ostream.h" 52#include "llvm/ADT/PostOrderIterator.h" 53#include "llvm/ADT/Statistic.h" 54#include <algorithm> 55using namespace llvm; 56 57STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 58STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 59STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 60STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 61 62#ifndef NDEBUG 63STATISTIC(NumBBWithOutOfOrderLineInfo, 64 "Number of blocks with out of order line number info"); 65STATISTIC(NumMBBWithOutOfOrderLineInfo, 66 "Number of machine blocks with out of order line number info"); 67#endif 68 69static cl::opt<bool> 70EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 71 cl::desc("Enable verbose messages in the \"fast\" " 72 "instruction selector")); 73static cl::opt<bool> 74EnableFastISelAbort("fast-isel-abort", cl::Hidden, 75 cl::desc("Enable abort calls when \"fast\" instruction fails")); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createSourceListDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == Sched::Latency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 if (TLI.getSchedulingPreference() == Sched::RegPressure) 150 return createBURRListDAGScheduler(IS, OptLevel); 151 if (TLI.getSchedulingPreference() == Sched::Hybrid) 152 return createHybridListDAGScheduler(IS, OptLevel); 153 assert(TLI.getSchedulingPreference() == Sched::ILP && 154 "Unknown sched type!"); 155 return createILPListDAGScheduler(IS, OptLevel); 156 } 157} 158 159// EmitInstrWithCustomInserter - This method should be implemented by targets 160// that mark instructions with the 'usesCustomInserter' flag. These 161// instructions are special in various ways, which require special support to 162// insert. The specified MachineInstr is created but not inserted into any 163// basic blocks, and this method is called to expand it into a sequence of 164// instructions, potentially also creating new basic blocks and control flow. 165// When new basic blocks are inserted and the edges from MBB to its successors 166// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 167// DenseMap. 168MachineBasicBlock * 169TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 170 MachineBasicBlock *MBB) const { 171#ifndef NDEBUG 172 dbgs() << "If a target marks an instruction with " 173 "'usesCustomInserter', it must implement " 174 "TargetLowering::EmitInstrWithCustomInserter!"; 175#endif 176 llvm_unreachable(0); 177 return 0; 178} 179 180//===----------------------------------------------------------------------===// 181// SelectionDAGISel code 182//===----------------------------------------------------------------------===// 183 184SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 185 CodeGenOpt::Level OL) : 186 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 187 FuncInfo(new FunctionLoweringInfo(TLI)), 188 CurDAG(new SelectionDAG(tm)), 189 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 190 GFI(), 191 OptLevel(OL), 192 DAGSize(0) { 193 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 194 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 195 } 196 197SelectionDAGISel::~SelectionDAGISel() { 198 delete SDB; 199 delete CurDAG; 200 delete FuncInfo; 201} 202 203void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 204 AU.addRequired<AliasAnalysis>(); 205 AU.addPreserved<AliasAnalysis>(); 206 AU.addRequired<GCModuleInfo>(); 207 AU.addPreserved<GCModuleInfo>(); 208 MachineFunctionPass::getAnalysisUsage(AU); 209} 210 211/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 212/// other function that gcc recognizes as "returning twice". This is used to 213/// limit code-gen optimizations on the machine function. 214/// 215/// FIXME: Remove after <rdar://problem/8031714> is fixed. 216static bool FunctionCallsSetJmp(const Function *F) { 217 const Module *M = F->getParent(); 218 static const char *ReturnsTwiceFns[] = { 219 "_setjmp", 220 "setjmp", 221 "sigsetjmp", 222 "setjmp_syscall", 223 "savectx", 224 "qsetjmp", 225 "vfork", 226 "getcontext" 227 }; 228#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 229 230 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 231 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 232 if (!Callee->use_empty()) 233 for (Value::const_use_iterator 234 I = Callee->use_begin(), E = Callee->use_end(); 235 I != E; ++I) 236 if (const CallInst *CI = dyn_cast<CallInst>(*I)) 237 if (CI->getParent()->getParent() == F) 238 return true; 239 } 240 241 return false; 242#undef NUM_RETURNS_TWICE_FNS 243} 244 245/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 246/// may trap on it. In this case we have to split the edge so that the path 247/// through the predecessor block that doesn't go to the phi block doesn't 248/// execute the possibly trapping instruction. 249/// 250/// This is required for correctness, so it must be done at -O0. 251/// 252static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 253 // Loop for blocks with phi nodes. 254 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 255 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 256 if (PN == 0) continue; 257 258 ReprocessBlock: 259 // For each block with a PHI node, check to see if any of the input values 260 // are potentially trapping constant expressions. Constant expressions are 261 // the only potentially trapping value that can occur as the argument to a 262 // PHI. 263 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 264 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 265 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 266 if (CE == 0 || !CE->canTrap()) continue; 267 268 // The only case we have to worry about is when the edge is critical. 269 // Since this block has a PHI Node, we assume it has multiple input 270 // edges: check to see if the pred has multiple successors. 271 BasicBlock *Pred = PN->getIncomingBlock(i); 272 if (Pred->getTerminator()->getNumSuccessors() == 1) 273 continue; 274 275 // Okay, we have to split this edge. 276 SplitCriticalEdge(Pred->getTerminator(), 277 GetSuccessorNumber(Pred, BB), SDISel, true); 278 goto ReprocessBlock; 279 } 280 } 281} 282 283bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 284 // Do some sanity-checking on the command-line options. 285 assert((!EnableFastISelVerbose || EnableFastISel) && 286 "-fast-isel-verbose requires -fast-isel"); 287 assert((!EnableFastISelAbort || EnableFastISel) && 288 "-fast-isel-abort requires -fast-isel"); 289 290 const Function &Fn = *mf.getFunction(); 291 const TargetInstrInfo &TII = *TM.getInstrInfo(); 292 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 293 294 MF = &mf; 295 RegInfo = &MF->getRegInfo(); 296 AA = &getAnalysis<AliasAnalysis>(); 297 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 298 299 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 300 301 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 302 303 CurDAG->init(*MF); 304 FuncInfo->set(Fn, *MF); 305 SDB->init(GFI, *AA); 306 307 SelectAllBasicBlocks(Fn); 308 309 // If the first basic block in the function has live ins that need to be 310 // copied into vregs, emit the copies into the top of the block before 311 // emitting the code for the block. 312 MachineBasicBlock *EntryMBB = MF->begin(); 313 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 314 315 DenseMap<unsigned, unsigned> LiveInMap; 316 if (!FuncInfo->ArgDbgValues.empty()) 317 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 318 E = RegInfo->livein_end(); LI != E; ++LI) 319 if (LI->second) 320 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 321 322 // Insert DBG_VALUE instructions for function arguments to the entry block. 323 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 324 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 325 unsigned Reg = MI->getOperand(0).getReg(); 326 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 327 EntryMBB->insert(EntryMBB->begin(), MI); 328 else { 329 MachineInstr *Def = RegInfo->getVRegDef(Reg); 330 MachineBasicBlock::iterator InsertPos = Def; 331 // FIXME: VR def may not be in entry block. 332 Def->getParent()->insert(llvm::next(InsertPos), MI); 333 } 334 335 // If Reg is live-in then update debug info to track its copy in a vreg. 336 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 337 if (LDI != LiveInMap.end()) { 338 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 339 MachineBasicBlock::iterator InsertPos = Def; 340 const MDNode *Variable = 341 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 342 unsigned Offset = MI->getOperand(1).getImm(); 343 // Def is never a terminator here, so it is ok to increment InsertPos. 344 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 345 TII.get(TargetOpcode::DBG_VALUE)) 346 .addReg(LDI->second, RegState::Debug) 347 .addImm(Offset).addMetadata(Variable); 348 349 // If this vreg is directly copied into an exported register then 350 // that COPY instructions also need DBG_VALUE, if it is the only 351 // user of LDI->second. 352 MachineInstr *CopyUseMI = NULL; 353 for (MachineRegisterInfo::use_iterator 354 UI = RegInfo->use_begin(LDI->second); 355 MachineInstr *UseMI = UI.skipInstruction();) { 356 if (UseMI->isDebugValue()) continue; 357 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 358 CopyUseMI = UseMI; continue; 359 } 360 // Otherwise this is another use or second copy use. 361 CopyUseMI = NULL; break; 362 } 363 if (CopyUseMI) { 364 MachineInstr *NewMI = 365 BuildMI(*MF, CopyUseMI->getDebugLoc(), 366 TII.get(TargetOpcode::DBG_VALUE)) 367 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 368 .addImm(Offset).addMetadata(Variable); 369 EntryMBB->insertAfter(CopyUseMI, NewMI); 370 } 371 } 372 } 373 374 // Determine if there are any calls in this machine function. 375 MachineFrameInfo *MFI = MF->getFrameInfo(); 376 if (!MFI->hasCalls()) { 377 for (MachineFunction::const_iterator 378 I = MF->begin(), E = MF->end(); I != E; ++I) { 379 const MachineBasicBlock *MBB = I; 380 for (MachineBasicBlock::const_iterator 381 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 382 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 383 384 if ((TID.isCall() && !TID.isReturn()) || 385 II->isStackAligningInlineAsm()) { 386 MFI->setHasCalls(true); 387 goto done; 388 } 389 } 390 } 391 done:; 392 } 393 394 // Determine if there is a call to setjmp in the machine function. 395 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 396 397 // Replace forward-declared registers with the registers containing 398 // the desired value. 399 MachineRegisterInfo &MRI = MF->getRegInfo(); 400 for (DenseMap<unsigned, unsigned>::iterator 401 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 402 I != E; ++I) { 403 unsigned From = I->first; 404 unsigned To = I->second; 405 // If To is also scheduled to be replaced, find what its ultimate 406 // replacement is. 407 for (;;) { 408 DenseMap<unsigned, unsigned>::iterator J = 409 FuncInfo->RegFixups.find(To); 410 if (J == E) break; 411 To = J->second; 412 } 413 // Replace it. 414 MRI.replaceRegWith(From, To); 415 } 416 417 // Release function-specific state. SDB and CurDAG are already cleared 418 // at this point. 419 FuncInfo->clear(); 420 421 return true; 422} 423 424void 425SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 426 BasicBlock::const_iterator End, 427 bool &HadTailCall) { 428 // Lower all of the non-terminator instructions. If a call is emitted 429 // as a tail call, cease emitting nodes for this block. Terminators 430 // are handled below. 431 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 432 SDB->visit(*I); 433 434 // Make sure the root of the DAG is up-to-date. 435 CurDAG->setRoot(SDB->getControlRoot()); 436 HadTailCall = SDB->HasTailCall; 437 SDB->clear(); 438 439 // Final step, emit the lowered DAG as machine code. 440 CodeGenAndEmitDAG(); 441 return; 442} 443 444void SelectionDAGISel::ComputeLiveOutVRegInfo() { 445 SmallPtrSet<SDNode*, 128> VisitedNodes; 446 SmallVector<SDNode*, 128> Worklist; 447 448 Worklist.push_back(CurDAG->getRoot().getNode()); 449 450 APInt Mask; 451 APInt KnownZero; 452 APInt KnownOne; 453 454 do { 455 SDNode *N = Worklist.pop_back_val(); 456 457 // If we've already seen this node, ignore it. 458 if (!VisitedNodes.insert(N)) 459 continue; 460 461 // Otherwise, add all chain operands to the worklist. 462 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 463 if (N->getOperand(i).getValueType() == MVT::Other) 464 Worklist.push_back(N->getOperand(i).getNode()); 465 466 // If this is a CopyToReg with a vreg dest, process it. 467 if (N->getOpcode() != ISD::CopyToReg) 468 continue; 469 470 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 471 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 472 continue; 473 474 // Ignore non-scalar or non-integer values. 475 SDValue Src = N->getOperand(2); 476 EVT SrcVT = Src.getValueType(); 477 if (!SrcVT.isInteger() || SrcVT.isVector()) 478 continue; 479 480 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 481 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 482 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 483 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 484 } while (!Worklist.empty()); 485} 486 487void SelectionDAGISel::CodeGenAndEmitDAG() { 488 std::string GroupName; 489 if (TimePassesIsEnabled) 490 GroupName = "Instruction Selection and Scheduling"; 491 std::string BlockName; 492 int BlockNumber = -1; 493#ifdef NDEBUG 494 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 495 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 496 ViewSUnitDAGs) 497#endif 498 { 499 BlockNumber = FuncInfo->MBB->getNumber(); 500 BlockName = MF->getFunction()->getNameStr() + ":" + 501 FuncInfo->MBB->getBasicBlock()->getNameStr(); 502 } 503 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 504 << " '" << BlockName << "'\n"; CurDAG->dump()); 505 506 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 507 508 // Run the DAG combiner in pre-legalize mode. 509 { 510 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 511 CurDAG->Combine(Unrestricted, *AA, OptLevel); 512 } 513 514 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 515 << " '" << BlockName << "'\n"; CurDAG->dump()); 516 517 // Second step, hack on the DAG until it only uses operations and types that 518 // the target supports. 519 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 520 BlockName); 521 522 bool Changed; 523 { 524 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 525 Changed = CurDAG->LegalizeTypes(); 526 } 527 528 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 529 << " '" << BlockName << "'\n"; CurDAG->dump()); 530 531 if (Changed) { 532 if (ViewDAGCombineLT) 533 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 534 535 // Run the DAG combiner in post-type-legalize mode. 536 { 537 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 538 TimePassesIsEnabled); 539 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 540 } 541 542 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 543 << " '" << BlockName << "'\n"; CurDAG->dump()); 544 } 545 546 { 547 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 548 Changed = CurDAG->LegalizeVectors(); 549 } 550 551 if (Changed) { 552 { 553 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 554 CurDAG->LegalizeTypes(); 555 } 556 557 if (ViewDAGCombineLT) 558 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 559 560 // Run the DAG combiner in post-type-legalize mode. 561 { 562 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 563 TimePassesIsEnabled); 564 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 565 } 566 567 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 568 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 569 } 570 571 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 572 573 { 574 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 575 CurDAG->Legalize(OptLevel); 576 } 577 578 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 579 << " '" << BlockName << "'\n"; CurDAG->dump()); 580 581 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 582 583 // Run the DAG combiner in post-legalize mode. 584 { 585 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 586 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 587 } 588 589 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 590 << " '" << BlockName << "'\n"; CurDAG->dump()); 591 592 if (OptLevel != CodeGenOpt::None) 593 ComputeLiveOutVRegInfo(); 594 595 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 596 597 // Third, instruction select all of the operations to machine code, adding the 598 // code to the MachineBasicBlock. 599 { 600 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 601 DoInstructionSelection(); 602 } 603 604 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 605 << " '" << BlockName << "'\n"; CurDAG->dump()); 606 607 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 608 609 // Schedule machine code. 610 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 611 { 612 NamedRegionTimer T("Instruction Scheduling", GroupName, 613 TimePassesIsEnabled); 614 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 615 } 616 617 if (ViewSUnitDAGs) Scheduler->viewGraph(); 618 619 // Emit machine code to BB. This can change 'BB' to the last block being 620 // inserted into. 621 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 622 { 623 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 624 625 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(); 626 FuncInfo->InsertPt = Scheduler->InsertPos; 627 } 628 629 // If the block was split, make sure we update any references that are used to 630 // update PHI nodes later on. 631 if (FirstMBB != LastMBB) 632 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 633 634 // Free the scheduler state. 635 { 636 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 637 TimePassesIsEnabled); 638 delete Scheduler; 639 } 640 641 // Free the SelectionDAG state, now that we're finished with it. 642 CurDAG->clear(); 643} 644 645void SelectionDAGISel::DoInstructionSelection() { 646 DEBUG(errs() << "===== Instruction selection begins: BB#" 647 << FuncInfo->MBB->getNumber() 648 << " '" << FuncInfo->MBB->getName() << "'\n"); 649 650 PreprocessISelDAG(); 651 652 // Select target instructions for the DAG. 653 { 654 // Number all nodes with a topological order and set DAGSize. 655 DAGSize = CurDAG->AssignTopologicalOrder(); 656 657 // Create a dummy node (which is not added to allnodes), that adds 658 // a reference to the root node, preventing it from being deleted, 659 // and tracking any changes of the root. 660 HandleSDNode Dummy(CurDAG->getRoot()); 661 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 662 ++ISelPosition; 663 664 // The AllNodes list is now topological-sorted. Visit the 665 // nodes by starting at the end of the list (the root of the 666 // graph) and preceding back toward the beginning (the entry 667 // node). 668 while (ISelPosition != CurDAG->allnodes_begin()) { 669 SDNode *Node = --ISelPosition; 670 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 671 // but there are currently some corner cases that it misses. Also, this 672 // makes it theoretically possible to disable the DAGCombiner. 673 if (Node->use_empty()) 674 continue; 675 676 SDNode *ResNode = Select(Node); 677 678 // FIXME: This is pretty gross. 'Select' should be changed to not return 679 // anything at all and this code should be nuked with a tactical strike. 680 681 // If node should not be replaced, continue with the next one. 682 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 683 continue; 684 // Replace node. 685 if (ResNode) 686 ReplaceUses(Node, ResNode); 687 688 // If after the replacement this node is not used any more, 689 // remove this dead node. 690 if (Node->use_empty()) { // Don't delete EntryToken, etc. 691 ISelUpdater ISU(ISelPosition); 692 CurDAG->RemoveDeadNode(Node, &ISU); 693 } 694 } 695 696 CurDAG->setRoot(Dummy.getValue()); 697 } 698 699 DEBUG(errs() << "===== Instruction selection ends:\n"); 700 701 PostprocessISelDAG(); 702} 703 704/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 705/// do other setup for EH landing-pad blocks. 706void SelectionDAGISel::PrepareEHLandingPad() { 707 // Add a label to mark the beginning of the landing pad. Deletion of the 708 // landing pad can thus be detected via the MachineModuleInfo. 709 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 710 711 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 712 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 713 .addSym(Label); 714 715 // Mark exception register as live in. 716 unsigned Reg = TLI.getExceptionAddressRegister(); 717 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 718 719 // Mark exception selector register as live in. 720 Reg = TLI.getExceptionSelectorRegister(); 721 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 722 723 // FIXME: Hack around an exception handling flaw (PR1508): the personality 724 // function and list of typeids logically belong to the invoke (or, if you 725 // like, the basic block containing the invoke), and need to be associated 726 // with it in the dwarf exception handling tables. Currently however the 727 // information is provided by an intrinsic (eh.selector) that can be moved 728 // to unexpected places by the optimizers: if the unwind edge is critical, 729 // then breaking it can result in the intrinsics being in the successor of 730 // the landing pad, not the landing pad itself. This results 731 // in exceptions not being caught because no typeids are associated with 732 // the invoke. This may not be the only way things can go wrong, but it 733 // is the only way we try to work around for the moment. 734 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 735 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 736 737 if (Br && Br->isUnconditional()) { // Critical edge? 738 BasicBlock::const_iterator I, E; 739 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 740 if (isa<EHSelectorInst>(I)) 741 break; 742 743 if (I == E) 744 // No catch info found - try to extract some from the successor. 745 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 746 } 747} 748 749 750 751/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 752/// load into the specified FoldInst. Note that we could have a sequence where 753/// multiple LLVM IR instructions are folded into the same machineinstr. For 754/// example we could have: 755/// A: x = load i32 *P 756/// B: y = icmp A, 42 757/// C: br y, ... 758/// 759/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 760/// any other folded instructions) because it is between A and C. 761/// 762/// If we succeed in folding the load into the operation, return true. 763/// 764bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 765 const Instruction *FoldInst, 766 FastISel *FastIS) { 767 SmallPtrSet<const Instruction*, 4> FoldedInsts; 768 for (BasicBlock::const_iterator II = FoldInst; &*II != LI; --II) 769 FoldedInsts.insert(II); 770 771 // We know that the load has a single use, but don't know what it is. If it 772 // isn't one of the folded instructions, then we can't succeed here. 773 if (!FoldedInsts.count(LI->use_back())) 774 return false; 775 776 // Don't try to fold volatile loads. Target has to deal with alignment 777 // constraints. 778 if (LI->isVolatile()) return false; 779 780 // Figure out which vreg this is going into. 781 unsigned LoadReg = FastIS->getRegForValue(LI); 782 assert(LoadReg && "Load isn't already assigned a vreg? "); 783 784 // Check to see what the uses of this vreg are. If it has no uses, or more 785 // than one use (at the machine instr level) then we can't fold it. 786 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 787 if (RI == RegInfo->reg_end()) 788 return false; 789 790 // See if there is exactly one use of the vreg. If there are multiple uses, 791 // then the instruction got lowered to multiple machine instructions or the 792 // use of the loaded value ended up being multiple operands of the result, in 793 // either case, we can't fold this. 794 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 795 if (PostRI != RegInfo->reg_end()) 796 return false; 797 798 assert(RI.getOperand().isUse() && 799 "The only use of the vreg must be a use, we haven't emitted the def!"); 800 801 MachineInstr *User = &*RI; 802 803 // Set the insertion point properly. Folding the load can cause generation of 804 // other random instructions (like sign extends) for addressing modes, make 805 // sure they get inserted in a logical place before the new instruction. 806 FuncInfo->InsertPt = User; 807 FuncInfo->MBB = User->getParent(); 808 809 // Ask the target to try folding the load. 810 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 811} 812 813#ifndef NDEBUG 814/// CheckLineNumbers - Check if basic block instructions follow source order 815/// or not. 816static void CheckLineNumbers(const BasicBlock *BB) { 817 unsigned Line = 0; 818 unsigned Col = 0; 819 for (BasicBlock::const_iterator BI = BB->begin(), 820 BE = BB->end(); BI != BE; ++BI) { 821 const DebugLoc DL = BI->getDebugLoc(); 822 if (DL.isUnknown()) continue; 823 unsigned L = DL.getLine(); 824 unsigned C = DL.getCol(); 825 if (L < Line || (L == Line && C < Col)) { 826 ++NumBBWithOutOfOrderLineInfo; 827 return; 828 } 829 Line = L; 830 Col = C; 831 } 832} 833 834/// CheckLineNumbers - Check if machine basic block instructions follow source 835/// order or not. 836static void CheckLineNumbers(const MachineBasicBlock *MBB) { 837 unsigned Line = 0; 838 unsigned Col = 0; 839 for (MachineBasicBlock::const_iterator MBI = MBB->begin(), 840 MBE = MBB->end(); MBI != MBE; ++MBI) { 841 const DebugLoc DL = MBI->getDebugLoc(); 842 if (DL.isUnknown()) continue; 843 unsigned L = DL.getLine(); 844 unsigned C = DL.getCol(); 845 if (L < Line || (L == Line && C < Col)) { 846 ++NumMBBWithOutOfOrderLineInfo; 847 return; 848 } 849 Line = L; 850 Col = C; 851 } 852} 853#endif 854 855/// isFoldedOrDeadInstruction - Return true if the specified instruction is 856/// side-effect free and is either dead or folded into a generated instruction. 857/// Return false if it needs to be emitted. 858static bool isFoldedOrDeadInstruction(const Instruction *I, 859 FunctionLoweringInfo *FuncInfo) { 860 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 861 !isa<TerminatorInst>(I) && // Terminators aren't folded. 862 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 863 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 864} 865 866void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 867 // Initialize the Fast-ISel state, if needed. 868 FastISel *FastIS = 0; 869 if (EnableFastISel) 870 FastIS = TLI.createFastISel(*FuncInfo); 871 872 // Iterate over all basic blocks in the function. 873 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 874 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 875 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 876 const BasicBlock *LLVMBB = *I; 877#ifndef NDEBUG 878 CheckLineNumbers(LLVMBB); 879#endif 880 881 if (OptLevel != CodeGenOpt::None) { 882 bool AllPredsVisited = true; 883 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 884 PI != PE; ++PI) { 885 if (!FuncInfo->VisitedBBs.count(*PI)) { 886 AllPredsVisited = false; 887 break; 888 } 889 } 890 891 if (AllPredsVisited) { 892 for (BasicBlock::const_iterator I = LLVMBB->begin(); 893 isa<PHINode>(I); ++I) 894 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 895 } else { 896 for (BasicBlock::const_iterator I = LLVMBB->begin(); 897 isa<PHINode>(I); ++I) 898 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 899 } 900 901 FuncInfo->VisitedBBs.insert(LLVMBB); 902 } 903 904 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 905 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 906 907 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 908 BasicBlock::const_iterator const End = LLVMBB->end(); 909 BasicBlock::const_iterator BI = End; 910 911 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 912 913 // Setup an EH landing-pad block. 914 if (FuncInfo->MBB->isLandingPad()) 915 PrepareEHLandingPad(); 916 917 // Lower any arguments needed in this block if this is the entry block. 918 if (LLVMBB == &Fn.getEntryBlock()) 919 LowerArguments(LLVMBB); 920 921 // Before doing SelectionDAG ISel, see if FastISel has been requested. 922 if (FastIS) { 923 FastIS->startNewBlock(); 924 925 // Emit code for any incoming arguments. This must happen before 926 // beginning FastISel on the entry block. 927 if (LLVMBB == &Fn.getEntryBlock()) { 928 CurDAG->setRoot(SDB->getControlRoot()); 929 SDB->clear(); 930 CodeGenAndEmitDAG(); 931 932 // If we inserted any instructions at the beginning, make a note of 933 // where they are, so we can be sure to emit subsequent instructions 934 // after them. 935 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 936 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 937 else 938 FastIS->setLastLocalValue(0); 939 } 940 941 // Do FastISel on as many instructions as possible. 942 for (; BI != Begin; --BI) { 943 const Instruction *Inst = llvm::prior(BI); 944 945 // If we no longer require this instruction, skip it. 946 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) 947 continue; 948 949 // Bottom-up: reset the insert pos at the top, after any local-value 950 // instructions. 951 FastIS->recomputeInsertPt(); 952 953 // Try to select the instruction with FastISel. 954 if (FastIS->SelectInstruction(Inst)) { 955 // If fast isel succeeded, skip over all the folded instructions, and 956 // then see if there is a load right before the selected instructions. 957 // Try to fold the load if so. 958 const Instruction *BeforeInst = Inst; 959 while (BeforeInst != Begin) { 960 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 961 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 962 break; 963 } 964 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 965 BeforeInst->hasOneUse() && 966 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) 967 // If we succeeded, don't re-select the load. 968 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 969 continue; 970 } 971 972 // Then handle certain instructions as single-LLVM-Instruction blocks. 973 if (isa<CallInst>(Inst)) { 974 ++NumFastIselFailures; 975 if (EnableFastISelVerbose || EnableFastISelAbort) { 976 dbgs() << "FastISel missed call: "; 977 Inst->dump(); 978 } 979 980 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 981 unsigned &R = FuncInfo->ValueMap[Inst]; 982 if (!R) 983 R = FuncInfo->CreateRegs(Inst->getType()); 984 } 985 986 bool HadTailCall = false; 987 SelectBasicBlock(Inst, BI, HadTailCall); 988 989 // If the call was emitted as a tail call, we're done with the block. 990 if (HadTailCall) { 991 --BI; 992 break; 993 } 994 995 continue; 996 } 997 998 // Otherwise, give up on FastISel for the rest of the block. 999 // For now, be a little lenient about non-branch terminators. 1000 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) { 1001 ++NumFastIselFailures; 1002 if (EnableFastISelVerbose || EnableFastISelAbort) { 1003 dbgs() << "FastISel miss: "; 1004 Inst->dump(); 1005 } 1006 if (EnableFastISelAbort) 1007 // The "fast" selector couldn't handle something and bailed. 1008 // For the purpose of debugging, just abort. 1009 llvm_unreachable("FastISel didn't select the entire block"); 1010 } 1011 break; 1012 } 1013 1014 FastIS->recomputeInsertPt(); 1015 } 1016 1017 if (Begin != BI) 1018 ++NumDAGBlocks; 1019 else 1020 ++NumFastIselBlocks; 1021 1022 // Run SelectionDAG instruction selection on the remainder of the block 1023 // not handled by FastISel. If FastISel is not run, this is the entire 1024 // block. 1025 bool HadTailCall; 1026 SelectBasicBlock(Begin, BI, HadTailCall); 1027 1028 FinishBasicBlock(); 1029 FuncInfo->PHINodesToUpdate.clear(); 1030 } 1031 1032 delete FastIS; 1033#ifndef NDEBUG 1034 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end(); 1035 MBI != MBE; ++MBI) 1036 CheckLineNumbers(MBI); 1037#endif 1038} 1039 1040void 1041SelectionDAGISel::FinishBasicBlock() { 1042 1043 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1044 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1045 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1046 dbgs() << "Node " << i << " : (" 1047 << FuncInfo->PHINodesToUpdate[i].first 1048 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1049 1050 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1051 // PHI nodes in successors. 1052 if (SDB->SwitchCases.empty() && 1053 SDB->JTCases.empty() && 1054 SDB->BitTestCases.empty()) { 1055 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1056 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1057 assert(PHI->isPHI() && 1058 "This is not a machine PHI node that we are updating!"); 1059 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1060 continue; 1061 PHI->addOperand( 1062 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1063 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1064 } 1065 return; 1066 } 1067 1068 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1069 // Lower header first, if it wasn't already lowered 1070 if (!SDB->BitTestCases[i].Emitted) { 1071 // Set the current basic block to the mbb we wish to insert the code into 1072 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1073 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1074 // Emit the code 1075 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1076 CurDAG->setRoot(SDB->getRoot()); 1077 SDB->clear(); 1078 CodeGenAndEmitDAG(); 1079 } 1080 1081 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1082 // Set the current basic block to the mbb we wish to insert the code into 1083 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1084 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1085 // Emit the code 1086 if (j+1 != ej) 1087 SDB->visitBitTestCase(SDB->BitTestCases[i], 1088 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1089 SDB->BitTestCases[i].Reg, 1090 SDB->BitTestCases[i].Cases[j], 1091 FuncInfo->MBB); 1092 else 1093 SDB->visitBitTestCase(SDB->BitTestCases[i], 1094 SDB->BitTestCases[i].Default, 1095 SDB->BitTestCases[i].Reg, 1096 SDB->BitTestCases[i].Cases[j], 1097 FuncInfo->MBB); 1098 1099 1100 CurDAG->setRoot(SDB->getRoot()); 1101 SDB->clear(); 1102 CodeGenAndEmitDAG(); 1103 } 1104 1105 // Update PHI Nodes 1106 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1107 pi != pe; ++pi) { 1108 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1109 MachineBasicBlock *PHIBB = PHI->getParent(); 1110 assert(PHI->isPHI() && 1111 "This is not a machine PHI node that we are updating!"); 1112 // This is "default" BB. We have two jumps to it. From "header" BB and 1113 // from last "case" BB. 1114 if (PHIBB == SDB->BitTestCases[i].Default) { 1115 PHI->addOperand(MachineOperand:: 1116 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1117 false)); 1118 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1119 PHI->addOperand(MachineOperand:: 1120 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1121 false)); 1122 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1123 back().ThisBB)); 1124 } 1125 // One of "cases" BB. 1126 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1127 j != ej; ++j) { 1128 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1129 if (cBB->isSuccessor(PHIBB)) { 1130 PHI->addOperand(MachineOperand:: 1131 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1132 false)); 1133 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1134 } 1135 } 1136 } 1137 } 1138 SDB->BitTestCases.clear(); 1139 1140 // If the JumpTable record is filled in, then we need to emit a jump table. 1141 // Updating the PHI nodes is tricky in this case, since we need to determine 1142 // whether the PHI is a successor of the range check MBB or the jump table MBB 1143 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1144 // Lower header first, if it wasn't already lowered 1145 if (!SDB->JTCases[i].first.Emitted) { 1146 // Set the current basic block to the mbb we wish to insert the code into 1147 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1148 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1149 // Emit the code 1150 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1151 FuncInfo->MBB); 1152 CurDAG->setRoot(SDB->getRoot()); 1153 SDB->clear(); 1154 CodeGenAndEmitDAG(); 1155 } 1156 1157 // Set the current basic block to the mbb we wish to insert the code into 1158 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1159 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1160 // Emit the code 1161 SDB->visitJumpTable(SDB->JTCases[i].second); 1162 CurDAG->setRoot(SDB->getRoot()); 1163 SDB->clear(); 1164 CodeGenAndEmitDAG(); 1165 1166 // Update PHI Nodes 1167 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1168 pi != pe; ++pi) { 1169 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1170 MachineBasicBlock *PHIBB = PHI->getParent(); 1171 assert(PHI->isPHI() && 1172 "This is not a machine PHI node that we are updating!"); 1173 // "default" BB. We can go there only from header BB. 1174 if (PHIBB == SDB->JTCases[i].second.Default) { 1175 PHI->addOperand 1176 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1177 false)); 1178 PHI->addOperand 1179 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1180 } 1181 // JT BB. Just iterate over successors here 1182 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1183 PHI->addOperand 1184 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1185 false)); 1186 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1187 } 1188 } 1189 } 1190 SDB->JTCases.clear(); 1191 1192 // If the switch block involved a branch to one of the actual successors, we 1193 // need to update PHI nodes in that block. 1194 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1195 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1196 assert(PHI->isPHI() && 1197 "This is not a machine PHI node that we are updating!"); 1198 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1199 PHI->addOperand( 1200 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1201 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1202 } 1203 } 1204 1205 // If we generated any switch lowering information, build and codegen any 1206 // additional DAGs necessary. 1207 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1208 // Set the current basic block to the mbb we wish to insert the code into 1209 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1210 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1211 1212 // Determine the unique successors. 1213 SmallVector<MachineBasicBlock *, 2> Succs; 1214 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1215 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1216 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1217 1218 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1219 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1220 CurDAG->setRoot(SDB->getRoot()); 1221 SDB->clear(); 1222 CodeGenAndEmitDAG(); 1223 1224 // Remember the last block, now that any splitting is done, for use in 1225 // populating PHI nodes in successors. 1226 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1227 1228 // Handle any PHI nodes in successors of this chunk, as if we were coming 1229 // from the original BB before switch expansion. Note that PHI nodes can 1230 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1231 // handle them the right number of times. 1232 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1233 FuncInfo->MBB = Succs[i]; 1234 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1235 // FuncInfo->MBB may have been removed from the CFG if a branch was 1236 // constant folded. 1237 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1238 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1239 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1240 ++Phi) { 1241 // This value for this PHI node is recorded in PHINodesToUpdate. 1242 for (unsigned pn = 0; ; ++pn) { 1243 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1244 "Didn't find PHI entry!"); 1245 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1246 Phi->addOperand(MachineOperand:: 1247 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1248 false)); 1249 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1250 break; 1251 } 1252 } 1253 } 1254 } 1255 } 1256 } 1257 SDB->SwitchCases.clear(); 1258} 1259 1260 1261/// Create the scheduler. If a specific scheduler was specified 1262/// via the SchedulerRegistry, use it, otherwise select the 1263/// one preferred by the target. 1264/// 1265ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1266 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1267 1268 if (!Ctor) { 1269 Ctor = ISHeuristic; 1270 RegisterScheduler::setDefault(Ctor); 1271 } 1272 1273 return Ctor(this, OptLevel); 1274} 1275 1276//===----------------------------------------------------------------------===// 1277// Helper functions used by the generated instruction selector. 1278//===----------------------------------------------------------------------===// 1279// Calls to these methods are generated by tblgen. 1280 1281/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1282/// the dag combiner simplified the 255, we still want to match. RHS is the 1283/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1284/// specified in the .td file (e.g. 255). 1285bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1286 int64_t DesiredMaskS) const { 1287 const APInt &ActualMask = RHS->getAPIntValue(); 1288 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1289 1290 // If the actual mask exactly matches, success! 1291 if (ActualMask == DesiredMask) 1292 return true; 1293 1294 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1295 if (ActualMask.intersects(~DesiredMask)) 1296 return false; 1297 1298 // Otherwise, the DAG Combiner may have proven that the value coming in is 1299 // either already zero or is not demanded. Check for known zero input bits. 1300 APInt NeededMask = DesiredMask & ~ActualMask; 1301 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1302 return true; 1303 1304 // TODO: check to see if missing bits are just not demanded. 1305 1306 // Otherwise, this pattern doesn't match. 1307 return false; 1308} 1309 1310/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1311/// the dag combiner simplified the 255, we still want to match. RHS is the 1312/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1313/// specified in the .td file (e.g. 255). 1314bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1315 int64_t DesiredMaskS) const { 1316 const APInt &ActualMask = RHS->getAPIntValue(); 1317 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1318 1319 // If the actual mask exactly matches, success! 1320 if (ActualMask == DesiredMask) 1321 return true; 1322 1323 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1324 if (ActualMask.intersects(~DesiredMask)) 1325 return false; 1326 1327 // Otherwise, the DAG Combiner may have proven that the value coming in is 1328 // either already zero or is not demanded. Check for known zero input bits. 1329 APInt NeededMask = DesiredMask & ~ActualMask; 1330 1331 APInt KnownZero, KnownOne; 1332 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1333 1334 // If all the missing bits in the or are already known to be set, match! 1335 if ((NeededMask & KnownOne) == NeededMask) 1336 return true; 1337 1338 // TODO: check to see if missing bits are just not demanded. 1339 1340 // Otherwise, this pattern doesn't match. 1341 return false; 1342} 1343 1344 1345/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1346/// by tblgen. Others should not call it. 1347void SelectionDAGISel:: 1348SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1349 std::vector<SDValue> InOps; 1350 std::swap(InOps, Ops); 1351 1352 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1353 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1354 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1355 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1356 1357 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1358 if (InOps[e-1].getValueType() == MVT::Glue) 1359 --e; // Don't process a glue operand if it is here. 1360 1361 while (i != e) { 1362 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1363 if (!InlineAsm::isMemKind(Flags)) { 1364 // Just skip over this operand, copying the operands verbatim. 1365 Ops.insert(Ops.end(), InOps.begin()+i, 1366 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1367 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1368 } else { 1369 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1370 "Memory operand with multiple values?"); 1371 // Otherwise, this is a memory operand. Ask the target to select it. 1372 std::vector<SDValue> SelOps; 1373 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1374 report_fatal_error("Could not match memory address. Inline asm" 1375 " failure!"); 1376 1377 // Add this to the output node. 1378 unsigned NewFlags = 1379 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1380 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1381 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1382 i += 2; 1383 } 1384 } 1385 1386 // Add the glue input back if present. 1387 if (e != InOps.size()) 1388 Ops.push_back(InOps.back()); 1389} 1390 1391/// findGlueUse - Return use of MVT::Glue value produced by the specified 1392/// SDNode. 1393/// 1394static SDNode *findGlueUse(SDNode *N) { 1395 unsigned FlagResNo = N->getNumValues()-1; 1396 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1397 SDUse &Use = I.getUse(); 1398 if (Use.getResNo() == FlagResNo) 1399 return Use.getUser(); 1400 } 1401 return NULL; 1402} 1403 1404/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1405/// This function recursively traverses up the operand chain, ignoring 1406/// certain nodes. 1407static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1408 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1409 bool IgnoreChains) { 1410 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1411 // greater than all of its (recursive) operands. If we scan to a point where 1412 // 'use' is smaller than the node we're scanning for, then we know we will 1413 // never find it. 1414 // 1415 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1416 // happen because we scan down to newly selected nodes in the case of glue 1417 // uses. 1418 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1419 return false; 1420 1421 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1422 // won't fail if we scan it again. 1423 if (!Visited.insert(Use)) 1424 return false; 1425 1426 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1427 // Ignore chain uses, they are validated by HandleMergeInputChains. 1428 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1429 continue; 1430 1431 SDNode *N = Use->getOperand(i).getNode(); 1432 if (N == Def) { 1433 if (Use == ImmedUse || Use == Root) 1434 continue; // We are not looking for immediate use. 1435 assert(N != Root); 1436 return true; 1437 } 1438 1439 // Traverse up the operand chain. 1440 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1441 return true; 1442 } 1443 return false; 1444} 1445 1446/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1447/// operand node N of U during instruction selection that starts at Root. 1448bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1449 SDNode *Root) const { 1450 if (OptLevel == CodeGenOpt::None) return false; 1451 return N.hasOneUse(); 1452} 1453 1454/// IsLegalToFold - Returns true if the specific operand node N of 1455/// U can be folded during instruction selection that starts at Root. 1456bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1457 CodeGenOpt::Level OptLevel, 1458 bool IgnoreChains) { 1459 if (OptLevel == CodeGenOpt::None) return false; 1460 1461 // If Root use can somehow reach N through a path that that doesn't contain 1462 // U then folding N would create a cycle. e.g. In the following 1463 // diagram, Root can reach N through X. If N is folded into into Root, then 1464 // X is both a predecessor and a successor of U. 1465 // 1466 // [N*] // 1467 // ^ ^ // 1468 // / \ // 1469 // [U*] [X]? // 1470 // ^ ^ // 1471 // \ / // 1472 // \ / // 1473 // [Root*] // 1474 // 1475 // * indicates nodes to be folded together. 1476 // 1477 // If Root produces glue, then it gets (even more) interesting. Since it 1478 // will be "glued" together with its glue use in the scheduler, we need to 1479 // check if it might reach N. 1480 // 1481 // [N*] // 1482 // ^ ^ // 1483 // / \ // 1484 // [U*] [X]? // 1485 // ^ ^ // 1486 // \ \ // 1487 // \ | // 1488 // [Root*] | // 1489 // ^ | // 1490 // f | // 1491 // | / // 1492 // [Y] / // 1493 // ^ / // 1494 // f / // 1495 // | / // 1496 // [GU] // 1497 // 1498 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1499 // (call it Fold), then X is a predecessor of GU and a successor of 1500 // Fold. But since Fold and GU are glued together, this will create 1501 // a cycle in the scheduling graph. 1502 1503 // If the node has glue, walk down the graph to the "lowest" node in the 1504 // glueged set. 1505 EVT VT = Root->getValueType(Root->getNumValues()-1); 1506 while (VT == MVT::Glue) { 1507 SDNode *GU = findGlueUse(Root); 1508 if (GU == NULL) 1509 break; 1510 Root = GU; 1511 VT = Root->getValueType(Root->getNumValues()-1); 1512 1513 // If our query node has a glue result with a use, we've walked up it. If 1514 // the user (which has already been selected) has a chain or indirectly uses 1515 // the chain, our WalkChainUsers predicate will not consider it. Because of 1516 // this, we cannot ignore chains in this predicate. 1517 IgnoreChains = false; 1518 } 1519 1520 1521 SmallPtrSet<SDNode*, 16> Visited; 1522 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1523} 1524 1525SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1526 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1527 SelectInlineAsmMemoryOperands(Ops); 1528 1529 std::vector<EVT> VTs; 1530 VTs.push_back(MVT::Other); 1531 VTs.push_back(MVT::Glue); 1532 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1533 VTs, &Ops[0], Ops.size()); 1534 New->setNodeId(-1); 1535 return New.getNode(); 1536} 1537 1538SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1539 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1540} 1541 1542/// GetVBR - decode a vbr encoding whose top bit is set. 1543LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1544GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1545 assert(Val >= 128 && "Not a VBR"); 1546 Val &= 127; // Remove first vbr bit. 1547 1548 unsigned Shift = 7; 1549 uint64_t NextBits; 1550 do { 1551 NextBits = MatcherTable[Idx++]; 1552 Val |= (NextBits&127) << Shift; 1553 Shift += 7; 1554 } while (NextBits & 128); 1555 1556 return Val; 1557} 1558 1559 1560/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1561/// interior glue and chain results to use the new glue and chain results. 1562void SelectionDAGISel:: 1563UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1564 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1565 SDValue InputGlue, 1566 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1567 bool isMorphNodeTo) { 1568 SmallVector<SDNode*, 4> NowDeadNodes; 1569 1570 ISelUpdater ISU(ISelPosition); 1571 1572 // Now that all the normal results are replaced, we replace the chain and 1573 // glue results if present. 1574 if (!ChainNodesMatched.empty()) { 1575 assert(InputChain.getNode() != 0 && 1576 "Matched input chains but didn't produce a chain"); 1577 // Loop over all of the nodes we matched that produced a chain result. 1578 // Replace all the chain results with the final chain we ended up with. 1579 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1580 SDNode *ChainNode = ChainNodesMatched[i]; 1581 1582 // If this node was already deleted, don't look at it. 1583 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1584 continue; 1585 1586 // Don't replace the results of the root node if we're doing a 1587 // MorphNodeTo. 1588 if (ChainNode == NodeToMatch && isMorphNodeTo) 1589 continue; 1590 1591 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1592 if (ChainVal.getValueType() == MVT::Glue) 1593 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1594 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1595 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1596 1597 // If the node became dead and we haven't already seen it, delete it. 1598 if (ChainNode->use_empty() && 1599 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1600 NowDeadNodes.push_back(ChainNode); 1601 } 1602 } 1603 1604 // If the result produces glue, update any glue results in the matched 1605 // pattern with the glue result. 1606 if (InputGlue.getNode() != 0) { 1607 // Handle any interior nodes explicitly marked. 1608 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1609 SDNode *FRN = GlueResultNodesMatched[i]; 1610 1611 // If this node was already deleted, don't look at it. 1612 if (FRN->getOpcode() == ISD::DELETED_NODE) 1613 continue; 1614 1615 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1616 "Doesn't have a glue result"); 1617 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1618 InputGlue, &ISU); 1619 1620 // If the node became dead and we haven't already seen it, delete it. 1621 if (FRN->use_empty() && 1622 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1623 NowDeadNodes.push_back(FRN); 1624 } 1625 } 1626 1627 if (!NowDeadNodes.empty()) 1628 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1629 1630 DEBUG(errs() << "ISEL: Match complete!\n"); 1631} 1632 1633enum ChainResult { 1634 CR_Simple, 1635 CR_InducesCycle, 1636 CR_LeadsToInteriorNode 1637}; 1638 1639/// WalkChainUsers - Walk down the users of the specified chained node that is 1640/// part of the pattern we're matching, looking at all of the users we find. 1641/// This determines whether something is an interior node, whether we have a 1642/// non-pattern node in between two pattern nodes (which prevent folding because 1643/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1644/// between pattern nodes (in which case the TF becomes part of the pattern). 1645/// 1646/// The walk we do here is guaranteed to be small because we quickly get down to 1647/// already selected nodes "below" us. 1648static ChainResult 1649WalkChainUsers(SDNode *ChainedNode, 1650 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1651 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1652 ChainResult Result = CR_Simple; 1653 1654 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1655 E = ChainedNode->use_end(); UI != E; ++UI) { 1656 // Make sure the use is of the chain, not some other value we produce. 1657 if (UI.getUse().getValueType() != MVT::Other) continue; 1658 1659 SDNode *User = *UI; 1660 1661 // If we see an already-selected machine node, then we've gone beyond the 1662 // pattern that we're selecting down into the already selected chunk of the 1663 // DAG. 1664 if (User->isMachineOpcode() || 1665 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1666 continue; 1667 1668 if (User->getOpcode() == ISD::CopyToReg || 1669 User->getOpcode() == ISD::CopyFromReg || 1670 User->getOpcode() == ISD::INLINEASM || 1671 User->getOpcode() == ISD::EH_LABEL) { 1672 // If their node ID got reset to -1 then they've already been selected. 1673 // Treat them like a MachineOpcode. 1674 if (User->getNodeId() == -1) 1675 continue; 1676 } 1677 1678 // If we have a TokenFactor, we handle it specially. 1679 if (User->getOpcode() != ISD::TokenFactor) { 1680 // If the node isn't a token factor and isn't part of our pattern, then it 1681 // must be a random chained node in between two nodes we're selecting. 1682 // This happens when we have something like: 1683 // x = load ptr 1684 // call 1685 // y = x+4 1686 // store y -> ptr 1687 // Because we structurally match the load/store as a read/modify/write, 1688 // but the call is chained between them. We cannot fold in this case 1689 // because it would induce a cycle in the graph. 1690 if (!std::count(ChainedNodesInPattern.begin(), 1691 ChainedNodesInPattern.end(), User)) 1692 return CR_InducesCycle; 1693 1694 // Otherwise we found a node that is part of our pattern. For example in: 1695 // x = load ptr 1696 // y = x+4 1697 // store y -> ptr 1698 // This would happen when we're scanning down from the load and see the 1699 // store as a user. Record that there is a use of ChainedNode that is 1700 // part of the pattern and keep scanning uses. 1701 Result = CR_LeadsToInteriorNode; 1702 InteriorChainedNodes.push_back(User); 1703 continue; 1704 } 1705 1706 // If we found a TokenFactor, there are two cases to consider: first if the 1707 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1708 // uses of the TF are in our pattern) we just want to ignore it. Second, 1709 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1710 // [Load chain] 1711 // ^ 1712 // | 1713 // [Load] 1714 // ^ ^ 1715 // | \ DAG's like cheese 1716 // / \ do you? 1717 // / | 1718 // [TokenFactor] [Op] 1719 // ^ ^ 1720 // | | 1721 // \ / 1722 // \ / 1723 // [Store] 1724 // 1725 // In this case, the TokenFactor becomes part of our match and we rewrite it 1726 // as a new TokenFactor. 1727 // 1728 // To distinguish these two cases, do a recursive walk down the uses. 1729 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1730 case CR_Simple: 1731 // If the uses of the TokenFactor are just already-selected nodes, ignore 1732 // it, it is "below" our pattern. 1733 continue; 1734 case CR_InducesCycle: 1735 // If the uses of the TokenFactor lead to nodes that are not part of our 1736 // pattern that are not selected, folding would turn this into a cycle, 1737 // bail out now. 1738 return CR_InducesCycle; 1739 case CR_LeadsToInteriorNode: 1740 break; // Otherwise, keep processing. 1741 } 1742 1743 // Okay, we know we're in the interesting interior case. The TokenFactor 1744 // is now going to be considered part of the pattern so that we rewrite its 1745 // uses (it may have uses that are not part of the pattern) with the 1746 // ultimate chain result of the generated code. We will also add its chain 1747 // inputs as inputs to the ultimate TokenFactor we create. 1748 Result = CR_LeadsToInteriorNode; 1749 ChainedNodesInPattern.push_back(User); 1750 InteriorChainedNodes.push_back(User); 1751 continue; 1752 } 1753 1754 return Result; 1755} 1756 1757/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1758/// operation for when the pattern matched at least one node with a chains. The 1759/// input vector contains a list of all of the chained nodes that we match. We 1760/// must determine if this is a valid thing to cover (i.e. matching it won't 1761/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1762/// be used as the input node chain for the generated nodes. 1763static SDValue 1764HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1765 SelectionDAG *CurDAG) { 1766 // Walk all of the chained nodes we've matched, recursively scanning down the 1767 // users of the chain result. This adds any TokenFactor nodes that are caught 1768 // in between chained nodes to the chained and interior nodes list. 1769 SmallVector<SDNode*, 3> InteriorChainedNodes; 1770 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1771 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1772 InteriorChainedNodes) == CR_InducesCycle) 1773 return SDValue(); // Would induce a cycle. 1774 } 1775 1776 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1777 // that we are interested in. Form our input TokenFactor node. 1778 SmallVector<SDValue, 3> InputChains; 1779 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1780 // Add the input chain of this node to the InputChains list (which will be 1781 // the operands of the generated TokenFactor) if it's not an interior node. 1782 SDNode *N = ChainNodesMatched[i]; 1783 if (N->getOpcode() != ISD::TokenFactor) { 1784 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1785 continue; 1786 1787 // Otherwise, add the input chain. 1788 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1789 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1790 InputChains.push_back(InChain); 1791 continue; 1792 } 1793 1794 // If we have a token factor, we want to add all inputs of the token factor 1795 // that are not part of the pattern we're matching. 1796 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1797 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1798 N->getOperand(op).getNode())) 1799 InputChains.push_back(N->getOperand(op)); 1800 } 1801 } 1802 1803 SDValue Res; 1804 if (InputChains.size() == 1) 1805 return InputChains[0]; 1806 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1807 MVT::Other, &InputChains[0], InputChains.size()); 1808} 1809 1810/// MorphNode - Handle morphing a node in place for the selector. 1811SDNode *SelectionDAGISel:: 1812MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1813 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1814 // It is possible we're using MorphNodeTo to replace a node with no 1815 // normal results with one that has a normal result (or we could be 1816 // adding a chain) and the input could have glue and chains as well. 1817 // In this case we need to shift the operands down. 1818 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1819 // than the old isel though. 1820 int OldGlueResultNo = -1, OldChainResultNo = -1; 1821 1822 unsigned NTMNumResults = Node->getNumValues(); 1823 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1824 OldGlueResultNo = NTMNumResults-1; 1825 if (NTMNumResults != 1 && 1826 Node->getValueType(NTMNumResults-2) == MVT::Other) 1827 OldChainResultNo = NTMNumResults-2; 1828 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1829 OldChainResultNo = NTMNumResults-1; 1830 1831 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1832 // that this deletes operands of the old node that become dead. 1833 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1834 1835 // MorphNodeTo can operate in two ways: if an existing node with the 1836 // specified operands exists, it can just return it. Otherwise, it 1837 // updates the node in place to have the requested operands. 1838 if (Res == Node) { 1839 // If we updated the node in place, reset the node ID. To the isel, 1840 // this should be just like a newly allocated machine node. 1841 Res->setNodeId(-1); 1842 } 1843 1844 unsigned ResNumResults = Res->getNumValues(); 1845 // Move the glue if needed. 1846 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1847 (unsigned)OldGlueResultNo != ResNumResults-1) 1848 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1849 SDValue(Res, ResNumResults-1)); 1850 1851 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1852 --ResNumResults; 1853 1854 // Move the chain reference if needed. 1855 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1856 (unsigned)OldChainResultNo != ResNumResults-1) 1857 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1858 SDValue(Res, ResNumResults-1)); 1859 1860 // Otherwise, no replacement happened because the node already exists. Replace 1861 // Uses of the old node with the new one. 1862 if (Res != Node) 1863 CurDAG->ReplaceAllUsesWith(Node, Res); 1864 1865 return Res; 1866} 1867 1868/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1869LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1870CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1871 SDValue N, 1872 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1873 // Accept if it is exactly the same as a previously recorded node. 1874 unsigned RecNo = MatcherTable[MatcherIndex++]; 1875 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1876 return N == RecordedNodes[RecNo].first; 1877} 1878 1879/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1880LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1881CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1882 SelectionDAGISel &SDISel) { 1883 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1884} 1885 1886/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1887LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1888CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1889 SelectionDAGISel &SDISel, SDNode *N) { 1890 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1891} 1892 1893LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1894CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1895 SDNode *N) { 1896 uint16_t Opc = MatcherTable[MatcherIndex++]; 1897 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1898 return N->getOpcode() == Opc; 1899} 1900 1901LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1902CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1903 SDValue N, const TargetLowering &TLI) { 1904 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1905 if (N.getValueType() == VT) return true; 1906 1907 // Handle the case when VT is iPTR. 1908 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1909} 1910 1911LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1912CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1913 SDValue N, const TargetLowering &TLI, 1914 unsigned ChildNo) { 1915 if (ChildNo >= N.getNumOperands()) 1916 return false; // Match fails if out of range child #. 1917 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1918} 1919 1920 1921LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1922CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1923 SDValue N) { 1924 return cast<CondCodeSDNode>(N)->get() == 1925 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1926} 1927 1928LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1929CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1930 SDValue N, const TargetLowering &TLI) { 1931 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1932 if (cast<VTSDNode>(N)->getVT() == VT) 1933 return true; 1934 1935 // Handle the case when VT is iPTR. 1936 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1937} 1938 1939LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1940CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1941 SDValue N) { 1942 int64_t Val = MatcherTable[MatcherIndex++]; 1943 if (Val & 128) 1944 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1945 1946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1947 return C != 0 && C->getSExtValue() == Val; 1948} 1949 1950LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1951CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1952 SDValue N, SelectionDAGISel &SDISel) { 1953 int64_t Val = MatcherTable[MatcherIndex++]; 1954 if (Val & 128) 1955 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1956 1957 if (N->getOpcode() != ISD::AND) return false; 1958 1959 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1960 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1961} 1962 1963LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1964CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1965 SDValue N, SelectionDAGISel &SDISel) { 1966 int64_t Val = MatcherTable[MatcherIndex++]; 1967 if (Val & 128) 1968 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1969 1970 if (N->getOpcode() != ISD::OR) return false; 1971 1972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1973 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1974} 1975 1976/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1977/// scope, evaluate the current node. If the current predicate is known to 1978/// fail, set Result=true and return anything. If the current predicate is 1979/// known to pass, set Result=false and return the MatcherIndex to continue 1980/// with. If the current predicate is unknown, set Result=false and return the 1981/// MatcherIndex to continue with. 1982static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1983 unsigned Index, SDValue N, 1984 bool &Result, SelectionDAGISel &SDISel, 1985 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1986 switch (Table[Index++]) { 1987 default: 1988 Result = false; 1989 return Index-1; // Could not evaluate this predicate. 1990 case SelectionDAGISel::OPC_CheckSame: 1991 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1992 return Index; 1993 case SelectionDAGISel::OPC_CheckPatternPredicate: 1994 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckPredicate: 1997 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckOpcode: 2000 Result = !::CheckOpcode(Table, Index, N.getNode()); 2001 return Index; 2002 case SelectionDAGISel::OPC_CheckType: 2003 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2004 return Index; 2005 case SelectionDAGISel::OPC_CheckChild0Type: 2006 case SelectionDAGISel::OPC_CheckChild1Type: 2007 case SelectionDAGISel::OPC_CheckChild2Type: 2008 case SelectionDAGISel::OPC_CheckChild3Type: 2009 case SelectionDAGISel::OPC_CheckChild4Type: 2010 case SelectionDAGISel::OPC_CheckChild5Type: 2011 case SelectionDAGISel::OPC_CheckChild6Type: 2012 case SelectionDAGISel::OPC_CheckChild7Type: 2013 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2014 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2015 return Index; 2016 case SelectionDAGISel::OPC_CheckCondCode: 2017 Result = !::CheckCondCode(Table, Index, N); 2018 return Index; 2019 case SelectionDAGISel::OPC_CheckValueType: 2020 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2021 return Index; 2022 case SelectionDAGISel::OPC_CheckInteger: 2023 Result = !::CheckInteger(Table, Index, N); 2024 return Index; 2025 case SelectionDAGISel::OPC_CheckAndImm: 2026 Result = !::CheckAndImm(Table, Index, N, SDISel); 2027 return Index; 2028 case SelectionDAGISel::OPC_CheckOrImm: 2029 Result = !::CheckOrImm(Table, Index, N, SDISel); 2030 return Index; 2031 } 2032} 2033 2034namespace { 2035 2036struct MatchScope { 2037 /// FailIndex - If this match fails, this is the index to continue with. 2038 unsigned FailIndex; 2039 2040 /// NodeStack - The node stack when the scope was formed. 2041 SmallVector<SDValue, 4> NodeStack; 2042 2043 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2044 unsigned NumRecordedNodes; 2045 2046 /// NumMatchedMemRefs - The number of matched memref entries. 2047 unsigned NumMatchedMemRefs; 2048 2049 /// InputChain/InputGlue - The current chain/glue 2050 SDValue InputChain, InputGlue; 2051 2052 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2053 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2054}; 2055 2056} 2057 2058SDNode *SelectionDAGISel:: 2059SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2060 unsigned TableSize) { 2061 // FIXME: Should these even be selected? Handle these cases in the caller? 2062 switch (NodeToMatch->getOpcode()) { 2063 default: 2064 break; 2065 case ISD::EntryToken: // These nodes remain the same. 2066 case ISD::BasicBlock: 2067 case ISD::Register: 2068 //case ISD::VALUETYPE: 2069 //case ISD::CONDCODE: 2070 case ISD::HANDLENODE: 2071 case ISD::MDNODE_SDNODE: 2072 case ISD::TargetConstant: 2073 case ISD::TargetConstantFP: 2074 case ISD::TargetConstantPool: 2075 case ISD::TargetFrameIndex: 2076 case ISD::TargetExternalSymbol: 2077 case ISD::TargetBlockAddress: 2078 case ISD::TargetJumpTable: 2079 case ISD::TargetGlobalTLSAddress: 2080 case ISD::TargetGlobalAddress: 2081 case ISD::TokenFactor: 2082 case ISD::CopyFromReg: 2083 case ISD::CopyToReg: 2084 case ISD::EH_LABEL: 2085 NodeToMatch->setNodeId(-1); // Mark selected. 2086 return 0; 2087 case ISD::AssertSext: 2088 case ISD::AssertZext: 2089 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2090 NodeToMatch->getOperand(0)); 2091 return 0; 2092 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2093 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2094 } 2095 2096 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2097 2098 // Set up the node stack with NodeToMatch as the only node on the stack. 2099 SmallVector<SDValue, 8> NodeStack; 2100 SDValue N = SDValue(NodeToMatch, 0); 2101 NodeStack.push_back(N); 2102 2103 // MatchScopes - Scopes used when matching, if a match failure happens, this 2104 // indicates where to continue checking. 2105 SmallVector<MatchScope, 8> MatchScopes; 2106 2107 // RecordedNodes - This is the set of nodes that have been recorded by the 2108 // state machine. The second value is the parent of the node, or null if the 2109 // root is recorded. 2110 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2111 2112 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2113 // pattern. 2114 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2115 2116 // These are the current input chain and glue for use when generating nodes. 2117 // Various Emit operations change these. For example, emitting a copytoreg 2118 // uses and updates these. 2119 SDValue InputChain, InputGlue; 2120 2121 // ChainNodesMatched - If a pattern matches nodes that have input/output 2122 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2123 // which ones they are. The result is captured into this list so that we can 2124 // update the chain results when the pattern is complete. 2125 SmallVector<SDNode*, 3> ChainNodesMatched; 2126 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2127 2128 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2129 NodeToMatch->dump(CurDAG); 2130 errs() << '\n'); 2131 2132 // Determine where to start the interpreter. Normally we start at opcode #0, 2133 // but if the state machine starts with an OPC_SwitchOpcode, then we 2134 // accelerate the first lookup (which is guaranteed to be hot) with the 2135 // OpcodeOffset table. 2136 unsigned MatcherIndex = 0; 2137 2138 if (!OpcodeOffset.empty()) { 2139 // Already computed the OpcodeOffset table, just index into it. 2140 if (N.getOpcode() < OpcodeOffset.size()) 2141 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2142 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2143 2144 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2145 // Otherwise, the table isn't computed, but the state machine does start 2146 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2147 // is the first time we're selecting an instruction. 2148 unsigned Idx = 1; 2149 while (1) { 2150 // Get the size of this case. 2151 unsigned CaseSize = MatcherTable[Idx++]; 2152 if (CaseSize & 128) 2153 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2154 if (CaseSize == 0) break; 2155 2156 // Get the opcode, add the index to the table. 2157 uint16_t Opc = MatcherTable[Idx++]; 2158 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2159 if (Opc >= OpcodeOffset.size()) 2160 OpcodeOffset.resize((Opc+1)*2); 2161 OpcodeOffset[Opc] = Idx; 2162 Idx += CaseSize; 2163 } 2164 2165 // Okay, do the lookup for the first opcode. 2166 if (N.getOpcode() < OpcodeOffset.size()) 2167 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2168 } 2169 2170 while (1) { 2171 assert(MatcherIndex < TableSize && "Invalid index"); 2172#ifndef NDEBUG 2173 unsigned CurrentOpcodeIndex = MatcherIndex; 2174#endif 2175 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2176 switch (Opcode) { 2177 case OPC_Scope: { 2178 // Okay, the semantics of this operation are that we should push a scope 2179 // then evaluate the first child. However, pushing a scope only to have 2180 // the first check fail (which then pops it) is inefficient. If we can 2181 // determine immediately that the first check (or first several) will 2182 // immediately fail, don't even bother pushing a scope for them. 2183 unsigned FailIndex; 2184 2185 while (1) { 2186 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2187 if (NumToSkip & 128) 2188 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2189 // Found the end of the scope with no match. 2190 if (NumToSkip == 0) { 2191 FailIndex = 0; 2192 break; 2193 } 2194 2195 FailIndex = MatcherIndex+NumToSkip; 2196 2197 unsigned MatcherIndexOfPredicate = MatcherIndex; 2198 (void)MatcherIndexOfPredicate; // silence warning. 2199 2200 // If we can't evaluate this predicate without pushing a scope (e.g. if 2201 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2202 // push the scope and evaluate the full predicate chain. 2203 bool Result; 2204 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2205 Result, *this, RecordedNodes); 2206 if (!Result) 2207 break; 2208 2209 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2210 << "index " << MatcherIndexOfPredicate 2211 << ", continuing at " << FailIndex << "\n"); 2212 ++NumDAGIselRetries; 2213 2214 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2215 // move to the next case. 2216 MatcherIndex = FailIndex; 2217 } 2218 2219 // If the whole scope failed to match, bail. 2220 if (FailIndex == 0) break; 2221 2222 // Push a MatchScope which indicates where to go if the first child fails 2223 // to match. 2224 MatchScope NewEntry; 2225 NewEntry.FailIndex = FailIndex; 2226 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2227 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2228 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2229 NewEntry.InputChain = InputChain; 2230 NewEntry.InputGlue = InputGlue; 2231 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2232 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2233 MatchScopes.push_back(NewEntry); 2234 continue; 2235 } 2236 case OPC_RecordNode: { 2237 // Remember this node, it may end up being an operand in the pattern. 2238 SDNode *Parent = 0; 2239 if (NodeStack.size() > 1) 2240 Parent = NodeStack[NodeStack.size()-2].getNode(); 2241 RecordedNodes.push_back(std::make_pair(N, Parent)); 2242 continue; 2243 } 2244 2245 case OPC_RecordChild0: case OPC_RecordChild1: 2246 case OPC_RecordChild2: case OPC_RecordChild3: 2247 case OPC_RecordChild4: case OPC_RecordChild5: 2248 case OPC_RecordChild6: case OPC_RecordChild7: { 2249 unsigned ChildNo = Opcode-OPC_RecordChild0; 2250 if (ChildNo >= N.getNumOperands()) 2251 break; // Match fails if out of range child #. 2252 2253 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2254 N.getNode())); 2255 continue; 2256 } 2257 case OPC_RecordMemRef: 2258 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2259 continue; 2260 2261 case OPC_CaptureGlueInput: 2262 // If the current node has an input glue, capture it in InputGlue. 2263 if (N->getNumOperands() != 0 && 2264 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2265 InputGlue = N->getOperand(N->getNumOperands()-1); 2266 continue; 2267 2268 case OPC_MoveChild: { 2269 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2270 if (ChildNo >= N.getNumOperands()) 2271 break; // Match fails if out of range child #. 2272 N = N.getOperand(ChildNo); 2273 NodeStack.push_back(N); 2274 continue; 2275 } 2276 2277 case OPC_MoveParent: 2278 // Pop the current node off the NodeStack. 2279 NodeStack.pop_back(); 2280 assert(!NodeStack.empty() && "Node stack imbalance!"); 2281 N = NodeStack.back(); 2282 continue; 2283 2284 case OPC_CheckSame: 2285 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2286 continue; 2287 case OPC_CheckPatternPredicate: 2288 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2289 continue; 2290 case OPC_CheckPredicate: 2291 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2292 N.getNode())) 2293 break; 2294 continue; 2295 case OPC_CheckComplexPat: { 2296 unsigned CPNum = MatcherTable[MatcherIndex++]; 2297 unsigned RecNo = MatcherTable[MatcherIndex++]; 2298 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2299 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2300 RecordedNodes[RecNo].first, CPNum, 2301 RecordedNodes)) 2302 break; 2303 continue; 2304 } 2305 case OPC_CheckOpcode: 2306 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2307 continue; 2308 2309 case OPC_CheckType: 2310 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2311 continue; 2312 2313 case OPC_SwitchOpcode: { 2314 unsigned CurNodeOpcode = N.getOpcode(); 2315 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2316 unsigned CaseSize; 2317 while (1) { 2318 // Get the size of this case. 2319 CaseSize = MatcherTable[MatcherIndex++]; 2320 if (CaseSize & 128) 2321 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2322 if (CaseSize == 0) break; 2323 2324 uint16_t Opc = MatcherTable[MatcherIndex++]; 2325 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2326 2327 // If the opcode matches, then we will execute this case. 2328 if (CurNodeOpcode == Opc) 2329 break; 2330 2331 // Otherwise, skip over this case. 2332 MatcherIndex += CaseSize; 2333 } 2334 2335 // If no cases matched, bail out. 2336 if (CaseSize == 0) break; 2337 2338 // Otherwise, execute the case we found. 2339 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2340 << " to " << MatcherIndex << "\n"); 2341 continue; 2342 } 2343 2344 case OPC_SwitchType: { 2345 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2346 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2347 unsigned CaseSize; 2348 while (1) { 2349 // Get the size of this case. 2350 CaseSize = MatcherTable[MatcherIndex++]; 2351 if (CaseSize & 128) 2352 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2353 if (CaseSize == 0) break; 2354 2355 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2356 if (CaseVT == MVT::iPTR) 2357 CaseVT = TLI.getPointerTy(); 2358 2359 // If the VT matches, then we will execute this case. 2360 if (CurNodeVT == CaseVT) 2361 break; 2362 2363 // Otherwise, skip over this case. 2364 MatcherIndex += CaseSize; 2365 } 2366 2367 // If no cases matched, bail out. 2368 if (CaseSize == 0) break; 2369 2370 // Otherwise, execute the case we found. 2371 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2372 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2373 continue; 2374 } 2375 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2376 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2377 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2378 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2379 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2380 Opcode-OPC_CheckChild0Type)) 2381 break; 2382 continue; 2383 case OPC_CheckCondCode: 2384 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2385 continue; 2386 case OPC_CheckValueType: 2387 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2388 continue; 2389 case OPC_CheckInteger: 2390 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2391 continue; 2392 case OPC_CheckAndImm: 2393 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2394 continue; 2395 case OPC_CheckOrImm: 2396 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2397 continue; 2398 2399 case OPC_CheckFoldableChainNode: { 2400 assert(NodeStack.size() != 1 && "No parent node"); 2401 // Verify that all intermediate nodes between the root and this one have 2402 // a single use. 2403 bool HasMultipleUses = false; 2404 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2405 if (!NodeStack[i].hasOneUse()) { 2406 HasMultipleUses = true; 2407 break; 2408 } 2409 if (HasMultipleUses) break; 2410 2411 // Check to see that the target thinks this is profitable to fold and that 2412 // we can fold it without inducing cycles in the graph. 2413 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2414 NodeToMatch) || 2415 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2416 NodeToMatch, OptLevel, 2417 true/*We validate our own chains*/)) 2418 break; 2419 2420 continue; 2421 } 2422 case OPC_EmitInteger: { 2423 MVT::SimpleValueType VT = 2424 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2425 int64_t Val = MatcherTable[MatcherIndex++]; 2426 if (Val & 128) 2427 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2428 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2429 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2430 continue; 2431 } 2432 case OPC_EmitRegister: { 2433 MVT::SimpleValueType VT = 2434 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2435 unsigned RegNo = MatcherTable[MatcherIndex++]; 2436 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2437 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2438 continue; 2439 } 2440 case OPC_EmitRegister2: { 2441 // For targets w/ more than 256 register names, the register enum 2442 // values are stored in two bytes in the matcher table (just like 2443 // opcodes). 2444 MVT::SimpleValueType VT = 2445 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2446 unsigned RegNo = MatcherTable[MatcherIndex++]; 2447 RegNo |= MatcherTable[MatcherIndex++] << 8; 2448 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2449 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2450 continue; 2451 } 2452 2453 case OPC_EmitConvertToTarget: { 2454 // Convert from IMM/FPIMM to target version. 2455 unsigned RecNo = MatcherTable[MatcherIndex++]; 2456 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2457 SDValue Imm = RecordedNodes[RecNo].first; 2458 2459 if (Imm->getOpcode() == ISD::Constant) { 2460 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2461 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2462 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2463 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2464 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2465 } 2466 2467 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2468 continue; 2469 } 2470 2471 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2472 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2473 // These are space-optimized forms of OPC_EmitMergeInputChains. 2474 assert(InputChain.getNode() == 0 && 2475 "EmitMergeInputChains should be the first chain producing node"); 2476 assert(ChainNodesMatched.empty() && 2477 "Should only have one EmitMergeInputChains per match"); 2478 2479 // Read all of the chained nodes. 2480 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2481 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2482 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2483 2484 // FIXME: What if other value results of the node have uses not matched 2485 // by this pattern? 2486 if (ChainNodesMatched.back() != NodeToMatch && 2487 !RecordedNodes[RecNo].first.hasOneUse()) { 2488 ChainNodesMatched.clear(); 2489 break; 2490 } 2491 2492 // Merge the input chains if they are not intra-pattern references. 2493 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2494 2495 if (InputChain.getNode() == 0) 2496 break; // Failed to merge. 2497 continue; 2498 } 2499 2500 case OPC_EmitMergeInputChains: { 2501 assert(InputChain.getNode() == 0 && 2502 "EmitMergeInputChains should be the first chain producing node"); 2503 // This node gets a list of nodes we matched in the input that have 2504 // chains. We want to token factor all of the input chains to these nodes 2505 // together. However, if any of the input chains is actually one of the 2506 // nodes matched in this pattern, then we have an intra-match reference. 2507 // Ignore these because the newly token factored chain should not refer to 2508 // the old nodes. 2509 unsigned NumChains = MatcherTable[MatcherIndex++]; 2510 assert(NumChains != 0 && "Can't TF zero chains"); 2511 2512 assert(ChainNodesMatched.empty() && 2513 "Should only have one EmitMergeInputChains per match"); 2514 2515 // Read all of the chained nodes. 2516 for (unsigned i = 0; i != NumChains; ++i) { 2517 unsigned RecNo = MatcherTable[MatcherIndex++]; 2518 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2519 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2520 2521 // FIXME: What if other value results of the node have uses not matched 2522 // by this pattern? 2523 if (ChainNodesMatched.back() != NodeToMatch && 2524 !RecordedNodes[RecNo].first.hasOneUse()) { 2525 ChainNodesMatched.clear(); 2526 break; 2527 } 2528 } 2529 2530 // If the inner loop broke out, the match fails. 2531 if (ChainNodesMatched.empty()) 2532 break; 2533 2534 // Merge the input chains if they are not intra-pattern references. 2535 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2536 2537 if (InputChain.getNode() == 0) 2538 break; // Failed to merge. 2539 2540 continue; 2541 } 2542 2543 case OPC_EmitCopyToReg: { 2544 unsigned RecNo = MatcherTable[MatcherIndex++]; 2545 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2546 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2547 2548 if (InputChain.getNode() == 0) 2549 InputChain = CurDAG->getEntryNode(); 2550 2551 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2552 DestPhysReg, RecordedNodes[RecNo].first, 2553 InputGlue); 2554 2555 InputGlue = InputChain.getValue(1); 2556 continue; 2557 } 2558 2559 case OPC_EmitNodeXForm: { 2560 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2561 unsigned RecNo = MatcherTable[MatcherIndex++]; 2562 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2563 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2564 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2565 continue; 2566 } 2567 2568 case OPC_EmitNode: 2569 case OPC_MorphNodeTo: { 2570 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2571 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2572 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2573 // Get the result VT list. 2574 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2575 SmallVector<EVT, 4> VTs; 2576 for (unsigned i = 0; i != NumVTs; ++i) { 2577 MVT::SimpleValueType VT = 2578 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2579 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2580 VTs.push_back(VT); 2581 } 2582 2583 if (EmitNodeInfo & OPFL_Chain) 2584 VTs.push_back(MVT::Other); 2585 if (EmitNodeInfo & OPFL_GlueOutput) 2586 VTs.push_back(MVT::Glue); 2587 2588 // This is hot code, so optimize the two most common cases of 1 and 2 2589 // results. 2590 SDVTList VTList; 2591 if (VTs.size() == 1) 2592 VTList = CurDAG->getVTList(VTs[0]); 2593 else if (VTs.size() == 2) 2594 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2595 else 2596 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2597 2598 // Get the operand list. 2599 unsigned NumOps = MatcherTable[MatcherIndex++]; 2600 SmallVector<SDValue, 8> Ops; 2601 for (unsigned i = 0; i != NumOps; ++i) { 2602 unsigned RecNo = MatcherTable[MatcherIndex++]; 2603 if (RecNo & 128) 2604 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2605 2606 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2607 Ops.push_back(RecordedNodes[RecNo].first); 2608 } 2609 2610 // If there are variadic operands to add, handle them now. 2611 if (EmitNodeInfo & OPFL_VariadicInfo) { 2612 // Determine the start index to copy from. 2613 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2614 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2615 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2616 "Invalid variadic node"); 2617 // Copy all of the variadic operands, not including a potential glue 2618 // input. 2619 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2620 i != e; ++i) { 2621 SDValue V = NodeToMatch->getOperand(i); 2622 if (V.getValueType() == MVT::Glue) break; 2623 Ops.push_back(V); 2624 } 2625 } 2626 2627 // If this has chain/glue inputs, add them. 2628 if (EmitNodeInfo & OPFL_Chain) 2629 Ops.push_back(InputChain); 2630 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2631 Ops.push_back(InputGlue); 2632 2633 // Create the node. 2634 SDNode *Res = 0; 2635 if (Opcode != OPC_MorphNodeTo) { 2636 // If this is a normal EmitNode command, just create the new node and 2637 // add the results to the RecordedNodes list. 2638 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2639 VTList, Ops.data(), Ops.size()); 2640 2641 // Add all the non-glue/non-chain results to the RecordedNodes list. 2642 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2643 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2644 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2645 (SDNode*) 0)); 2646 } 2647 2648 } else { 2649 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2650 EmitNodeInfo); 2651 } 2652 2653 // If the node had chain/glue results, update our notion of the current 2654 // chain and glue. 2655 if (EmitNodeInfo & OPFL_GlueOutput) { 2656 InputGlue = SDValue(Res, VTs.size()-1); 2657 if (EmitNodeInfo & OPFL_Chain) 2658 InputChain = SDValue(Res, VTs.size()-2); 2659 } else if (EmitNodeInfo & OPFL_Chain) 2660 InputChain = SDValue(Res, VTs.size()-1); 2661 2662 // If the OPFL_MemRefs glue is set on this node, slap all of the 2663 // accumulated memrefs onto it. 2664 // 2665 // FIXME: This is vastly incorrect for patterns with multiple outputs 2666 // instructions that access memory and for ComplexPatterns that match 2667 // loads. 2668 if (EmitNodeInfo & OPFL_MemRefs) { 2669 MachineSDNode::mmo_iterator MemRefs = 2670 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2671 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2672 cast<MachineSDNode>(Res) 2673 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2674 } 2675 2676 DEBUG(errs() << " " 2677 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2678 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2679 2680 // If this was a MorphNodeTo then we're completely done! 2681 if (Opcode == OPC_MorphNodeTo) { 2682 // Update chain and glue uses. 2683 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2684 InputGlue, GlueResultNodesMatched, true); 2685 return Res; 2686 } 2687 2688 continue; 2689 } 2690 2691 case OPC_MarkGlueResults: { 2692 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2693 2694 // Read and remember all the glue-result nodes. 2695 for (unsigned i = 0; i != NumNodes; ++i) { 2696 unsigned RecNo = MatcherTable[MatcherIndex++]; 2697 if (RecNo & 128) 2698 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2699 2700 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2701 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2702 } 2703 continue; 2704 } 2705 2706 case OPC_CompleteMatch: { 2707 // The match has been completed, and any new nodes (if any) have been 2708 // created. Patch up references to the matched dag to use the newly 2709 // created nodes. 2710 unsigned NumResults = MatcherTable[MatcherIndex++]; 2711 2712 for (unsigned i = 0; i != NumResults; ++i) { 2713 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2714 if (ResSlot & 128) 2715 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2716 2717 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2718 SDValue Res = RecordedNodes[ResSlot].first; 2719 2720 assert(i < NodeToMatch->getNumValues() && 2721 NodeToMatch->getValueType(i) != MVT::Other && 2722 NodeToMatch->getValueType(i) != MVT::Glue && 2723 "Invalid number of results to complete!"); 2724 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2725 NodeToMatch->getValueType(i) == MVT::iPTR || 2726 Res.getValueType() == MVT::iPTR || 2727 NodeToMatch->getValueType(i).getSizeInBits() == 2728 Res.getValueType().getSizeInBits()) && 2729 "invalid replacement"); 2730 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2731 } 2732 2733 // If the root node defines glue, add it to the glue nodes to update list. 2734 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2735 GlueResultNodesMatched.push_back(NodeToMatch); 2736 2737 // Update chain and glue uses. 2738 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2739 InputGlue, GlueResultNodesMatched, false); 2740 2741 assert(NodeToMatch->use_empty() && 2742 "Didn't replace all uses of the node?"); 2743 2744 // FIXME: We just return here, which interacts correctly with SelectRoot 2745 // above. We should fix this to not return an SDNode* anymore. 2746 return 0; 2747 } 2748 } 2749 2750 // If the code reached this point, then the match failed. See if there is 2751 // another child to try in the current 'Scope', otherwise pop it until we 2752 // find a case to check. 2753 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2754 ++NumDAGIselRetries; 2755 while (1) { 2756 if (MatchScopes.empty()) { 2757 CannotYetSelect(NodeToMatch); 2758 return 0; 2759 } 2760 2761 // Restore the interpreter state back to the point where the scope was 2762 // formed. 2763 MatchScope &LastScope = MatchScopes.back(); 2764 RecordedNodes.resize(LastScope.NumRecordedNodes); 2765 NodeStack.clear(); 2766 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2767 N = NodeStack.back(); 2768 2769 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2770 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2771 MatcherIndex = LastScope.FailIndex; 2772 2773 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2774 2775 InputChain = LastScope.InputChain; 2776 InputGlue = LastScope.InputGlue; 2777 if (!LastScope.HasChainNodesMatched) 2778 ChainNodesMatched.clear(); 2779 if (!LastScope.HasGlueResultNodesMatched) 2780 GlueResultNodesMatched.clear(); 2781 2782 // Check to see what the offset is at the new MatcherIndex. If it is zero 2783 // we have reached the end of this scope, otherwise we have another child 2784 // in the current scope to try. 2785 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2786 if (NumToSkip & 128) 2787 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2788 2789 // If we have another child in this scope to match, update FailIndex and 2790 // try it. 2791 if (NumToSkip != 0) { 2792 LastScope.FailIndex = MatcherIndex+NumToSkip; 2793 break; 2794 } 2795 2796 // End of this scope, pop it and try the next child in the containing 2797 // scope. 2798 MatchScopes.pop_back(); 2799 } 2800 } 2801} 2802 2803 2804 2805void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2806 std::string msg; 2807 raw_string_ostream Msg(msg); 2808 Msg << "Cannot select: "; 2809 2810 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2811 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2812 N->getOpcode() != ISD::INTRINSIC_VOID) { 2813 N->printrFull(Msg, CurDAG); 2814 } else { 2815 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2816 unsigned iid = 2817 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2818 if (iid < Intrinsic::num_intrinsics) 2819 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2820 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2821 Msg << "target intrinsic %" << TII->getName(iid); 2822 else 2823 Msg << "unknown intrinsic #" << iid; 2824 } 2825 report_fatal_error(Msg.str()); 2826} 2827 2828char SelectionDAGISel::ID = 0; 2829