SelectionDAGISel.cpp revision fd7b326bea39c077eea8d378156bcf09051cc4ec
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/Analysis/AliasAnalysis.h" 17#include "llvm/CodeGen/SelectionDAGISel.h" 18#include "llvm/CodeGen/ScheduleDAG.h" 19#include "llvm/Constants.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/InlineAsm.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/ParameterAttributes.h" 29#include "llvm/CodeGen/MachineModuleInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetFrameInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetLowering.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57static cl::opt<bool> 58ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 59 cl::desc("Pop up a window to show SUnit dags after they are processed")); 60#else 61static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0; 62#endif 63 64//===---------------------------------------------------------------------===// 65/// 66/// RegisterScheduler class - Track the registration of instruction schedulers. 67/// 68//===---------------------------------------------------------------------===// 69MachinePassRegistry RegisterScheduler::Registry; 70 71//===---------------------------------------------------------------------===// 72/// 73/// ISHeuristic command line option for instruction schedulers. 74/// 75//===---------------------------------------------------------------------===// 76namespace { 77 cl::opt<RegisterScheduler::FunctionPassCtor, false, 78 RegisterPassParser<RegisterScheduler> > 79 ISHeuristic("pre-RA-sched", 80 cl::init(&createDefaultScheduler), 81 cl::desc("Instruction schedulers available (before register allocation):")); 82 83 static RegisterScheduler 84 defaultListDAGScheduler("default", " Best scheduler for the target", 85 createDefaultScheduler); 86} // namespace 87 88namespace { struct AsmOperandInfo; } 89 90namespace { 91 /// RegsForValue - This struct represents the physical registers that a 92 /// particular value is assigned and the type information about the value. 93 /// This is needed because values can be promoted into larger registers and 94 /// expanded into multiple smaller registers than the value. 95 struct VISIBILITY_HIDDEN RegsForValue { 96 /// Regs - This list holds the register (for legal and promoted values) 97 /// or register set (for expanded values) that the value should be assigned 98 /// to. 99 std::vector<unsigned> Regs; 100 101 /// RegVT - The value type of each register. 102 /// 103 MVT::ValueType RegVT; 104 105 /// ValueVT - The value type of the LLVM value, which may be promoted from 106 /// RegVT or made from merging the two expanded parts. 107 MVT::ValueType ValueVT; 108 109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 110 111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 112 : RegVT(regvt), ValueVT(valuevt) { 113 Regs.push_back(Reg); 114 } 115 RegsForValue(const std::vector<unsigned> ®s, 116 MVT::ValueType regvt, MVT::ValueType valuevt) 117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 118 } 119 120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 121 /// this value and returns the result as a ValueVT value. This uses 122 /// Chain/Flag as the input and updates them for the output Chain/Flag. 123 /// If the Flag pointer is NULL, no flag is used. 124 SDOperand getCopyFromRegs(SelectionDAG &DAG, 125 SDOperand &Chain, SDOperand *Flag) const; 126 127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 128 /// specified value into the registers specified by this object. This uses 129 /// Chain/Flag as the input and updates them for the output Chain/Flag. 130 /// If the Flag pointer is NULL, no flag is used. 131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 132 SDOperand &Chain, SDOperand *Flag) const; 133 134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 135 /// operand list. This adds the code marker and includes the number of 136 /// values added into it. 137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 138 std::vector<SDOperand> &Ops) const; 139 }; 140} 141 142namespace llvm { 143 //===--------------------------------------------------------------------===// 144 /// createDefaultScheduler - This creates an instruction scheduler appropriate 145 /// for the target. 146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 147 SelectionDAG *DAG, 148 MachineBasicBlock *BB) { 149 TargetLowering &TLI = IS->getTargetLowering(); 150 151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 152 return createTDListDAGScheduler(IS, DAG, BB); 153 } else { 154 assert(TLI.getSchedulingPreference() == 155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 156 return createBURRListDAGScheduler(IS, DAG, BB); 157 } 158 } 159 160 161 //===--------------------------------------------------------------------===// 162 /// FunctionLoweringInfo - This contains information that is global to a 163 /// function that is used when lowering a region of the function. 164 class FunctionLoweringInfo { 165 public: 166 TargetLowering &TLI; 167 Function &Fn; 168 MachineFunction &MF; 169 SSARegMap *RegMap; 170 171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 172 173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 175 176 /// ValueMap - Since we emit code for the function a basic block at a time, 177 /// we must remember which virtual registers hold the values for 178 /// cross-basic-block values. 179 DenseMap<const Value*, unsigned> ValueMap; 180 181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 182 /// the entry block. This allows the allocas to be efficiently referenced 183 /// anywhere in the function. 184 std::map<const AllocaInst*, int> StaticAllocaMap; 185 186#ifndef NDEBUG 187 SmallSet<Instruction*, 8> CatchInfoLost; 188 SmallSet<Instruction*, 8> CatchInfoFound; 189#endif 190 191 unsigned MakeReg(MVT::ValueType VT) { 192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 193 } 194 195 /// isExportedInst - Return true if the specified value is an instruction 196 /// exported from its block. 197 bool isExportedInst(const Value *V) { 198 return ValueMap.count(V); 199 } 200 201 unsigned CreateRegForValue(const Value *V); 202 203 unsigned InitializeRegForValue(const Value *V) { 204 unsigned &R = ValueMap[V]; 205 assert(R == 0 && "Already initialized this value register!"); 206 return R = CreateRegForValue(V); 207 } 208 }; 209} 210 211/// isSelector - Return true if this instruction is a call to the 212/// eh.selector intrinsic. 213static bool isSelector(Instruction *I) { 214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 || 216 II->getIntrinsicID() == Intrinsic::eh_selector_i64); 217 return false; 218} 219 220/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 221/// PHI nodes or outside of the basic block that defines it, or used by a 222/// switch instruction, which may expand to multiple basic blocks. 223static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 224 if (isa<PHINode>(I)) return true; 225 BasicBlock *BB = I->getParent(); 226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 228 // FIXME: Remove switchinst special case. 229 isa<SwitchInst>(*UI)) 230 return true; 231 return false; 232} 233 234/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 235/// entry block, return true. This includes arguments used by switches, since 236/// the switch may expand into multiple basic blocks. 237static bool isOnlyUsedInEntryBlock(Argument *A) { 238 BasicBlock *Entry = A->getParent()->begin(); 239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 241 return false; // Use not in entry block. 242 return true; 243} 244 245FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 246 Function &fn, MachineFunction &mf) 247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 248 249 // Create a vreg for each argument register that is not dead and is used 250 // outside of the entry block for the function. 251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 252 AI != E; ++AI) 253 if (!isOnlyUsedInEntryBlock(AI)) 254 InitializeRegForValue(AI); 255 256 // Initialize the mapping of values to registers. This is only set up for 257 // instruction values that are used outside of the block that defines 258 // them. 259 Function::iterator BB = Fn.begin(), EB = Fn.end(); 260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 263 const Type *Ty = AI->getAllocatedType(); 264 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 265 unsigned Align = 266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 267 AI->getAlignment()); 268 269 TySize *= CUI->getZExtValue(); // Get total allocated size. 270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 271 StaticAllocaMap[AI] = 272 MF.getFrameInfo()->CreateStackObject(TySize, Align); 273 } 274 275 for (; BB != EB; ++BB) 276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 278 if (!isa<AllocaInst>(I) || 279 !StaticAllocaMap.count(cast<AllocaInst>(I))) 280 InitializeRegForValue(I); 281 282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 283 // also creates the initial PHI MachineInstrs, though none of the input 284 // operands are populated. 285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 286 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 287 MBBMap[BB] = MBB; 288 MF.getBasicBlockList().push_back(MBB); 289 290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 291 // appropriate. 292 PHINode *PN; 293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 294 if (PN->use_empty()) continue; 295 296 MVT::ValueType VT = TLI.getValueType(PN->getType()); 297 unsigned NumRegisters = TLI.getNumRegisters(VT); 298 unsigned PHIReg = ValueMap[PN]; 299 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 301 for (unsigned i = 0; i != NumRegisters; ++i) 302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 303 } 304 } 305} 306 307/// CreateRegForValue - Allocate the appropriate number of virtual registers of 308/// the correctly promoted or expanded types. Assign these registers 309/// consecutive vreg numbers and return the first assigned number. 310unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 311 MVT::ValueType VT = TLI.getValueType(V->getType()); 312 313 unsigned NumRegisters = TLI.getNumRegisters(VT); 314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 315 316 unsigned R = MakeReg(RegisterVT); 317 for (unsigned i = 1; i != NumRegisters; ++i) 318 MakeReg(RegisterVT); 319 320 return R; 321} 322 323//===----------------------------------------------------------------------===// 324/// SelectionDAGLowering - This is the common target-independent lowering 325/// implementation that is parameterized by a TargetLowering object. 326/// Also, targets can overload any lowering method. 327/// 328namespace llvm { 329class SelectionDAGLowering { 330 MachineBasicBlock *CurMBB; 331 332 DenseMap<const Value*, SDOperand> NodeMap; 333 334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 335 /// them up and then emit token factor nodes when possible. This allows us to 336 /// get simple disambiguation between loads without worrying about alias 337 /// analysis. 338 std::vector<SDOperand> PendingLoads; 339 340 /// Case - A struct to record the Value for a switch case, and the 341 /// case's target basic block. 342 struct Case { 343 Constant* Low; 344 Constant* High; 345 MachineBasicBlock* BB; 346 347 Case() : Low(0), High(0), BB(0) { } 348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) : 349 Low(low), High(high), BB(bb) { } 350 uint64_t size() const { 351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue(); 352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue(); 353 return (rHigh - rLow + 1ULL); 354 } 355 }; 356 357 struct CaseBits { 358 uint64_t Mask; 359 MachineBasicBlock* BB; 360 unsigned Bits; 361 362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits): 363 Mask(mask), BB(bb), Bits(bits) { } 364 }; 365 366 typedef std::vector<Case> CaseVector; 367 typedef std::vector<CaseBits> CaseBitsVector; 368 typedef CaseVector::iterator CaseItr; 369 typedef std::pair<CaseItr, CaseItr> CaseRange; 370 371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 372 /// of conditional branches. 373 struct CaseRec { 374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 375 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 376 377 /// CaseBB - The MBB in which to emit the compare and branch 378 MachineBasicBlock *CaseBB; 379 /// LT, GE - If nonzero, we know the current case value must be less-than or 380 /// greater-than-or-equal-to these Constants. 381 Constant *LT; 382 Constant *GE; 383 /// Range - A pair of iterators representing the range of case values to be 384 /// processed at this point in the binary search tree. 385 CaseRange Range; 386 }; 387 388 typedef std::vector<CaseRec> CaseRecVector; 389 390 /// The comparison function for sorting the switch case values in the vector. 391 /// WARNING: Case ranges should be disjoint! 392 struct CaseCmp { 393 bool operator () (const Case& C1, const Case& C2) { 394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High)); 395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low); 396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High); 397 return CI1->getValue().slt(CI2->getValue()); 398 } 399 }; 400 401 struct CaseBitsCmp { 402 bool operator () (const CaseBits& C1, const CaseBits& C2) { 403 return C1.Bits > C2.Bits; 404 } 405 }; 406 407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI); 408 409public: 410 // TLI - This is information that describes the available target features we 411 // need for lowering. This indicates when operations are unavailable, 412 // implemented with a libcall, etc. 413 TargetLowering &TLI; 414 SelectionDAG &DAG; 415 const TargetData *TD; 416 AliasAnalysis &AA; 417 418 /// SwitchCases - Vector of CaseBlock structures used to communicate 419 /// SwitchInst code generation information. 420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 421 /// JTCases - Vector of JumpTable structures used to communicate 422 /// SwitchInst code generation information. 423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases; 424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases; 425 426 /// FuncInfo - Information about the function as a whole. 427 /// 428 FunctionLoweringInfo &FuncInfo; 429 430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 431 AliasAnalysis &aa, 432 FunctionLoweringInfo &funcinfo) 433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa), 434 FuncInfo(funcinfo) { 435 } 436 437 /// getRoot - Return the current virtual root of the Selection DAG. 438 /// 439 SDOperand getRoot() { 440 if (PendingLoads.empty()) 441 return DAG.getRoot(); 442 443 if (PendingLoads.size() == 1) { 444 SDOperand Root = PendingLoads[0]; 445 DAG.setRoot(Root); 446 PendingLoads.clear(); 447 return Root; 448 } 449 450 // Otherwise, we have to make a token factor node. 451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 452 &PendingLoads[0], PendingLoads.size()); 453 PendingLoads.clear(); 454 DAG.setRoot(Root); 455 return Root; 456 } 457 458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 459 460 void visit(Instruction &I) { visit(I.getOpcode(), I); } 461 462 void visit(unsigned Opcode, User &I) { 463 // Note: this doesn't use InstVisitor, because it has to work with 464 // ConstantExpr's in addition to instructions. 465 switch (Opcode) { 466 default: assert(0 && "Unknown instruction type encountered!"); 467 abort(); 468 // Build the switch statement using the Instruction.def file. 469#define HANDLE_INST(NUM, OPCODE, CLASS) \ 470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 471#include "llvm/Instruction.def" 472 } 473 } 474 475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 476 477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 478 const Value *SV, SDOperand Root, 479 bool isVolatile, unsigned Alignment); 480 481 SDOperand getIntPtrConstant(uint64_t Val) { 482 return DAG.getConstant(Val, TLI.getPointerTy()); 483 } 484 485 SDOperand getValue(const Value *V); 486 487 void setValue(const Value *V, SDOperand NewN) { 488 SDOperand &N = NodeMap[V]; 489 assert(N.Val == 0 && "Already set a value for this node!"); 490 N = NewN; 491 } 492 493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 494 std::set<unsigned> &OutputRegs, 495 std::set<unsigned> &InputRegs); 496 497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 499 unsigned Opc); 500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 501 void ExportFromCurrentBlock(Value *V); 502 void LowerCallTo(Instruction &I, const Type *CalledValueTy, 503 const ParamAttrsList *PAL, unsigned CallingConv, 504 bool IsTailCall, SDOperand Callee, unsigned OpIdx, 505 MachineBasicBlock *LandingPad = NULL); 506 507 // Terminator instructions. 508 void visitRet(ReturnInst &I); 509 void visitBr(BranchInst &I); 510 void visitSwitch(SwitchInst &I); 511 void visitUnreachable(UnreachableInst &I) { /* noop */ } 512 513 // Helpers for visitSwitch 514 bool handleSmallSwitchRange(CaseRec& CR, 515 CaseRecVector& WorkList, 516 Value* SV, 517 MachineBasicBlock* Default); 518 bool handleJTSwitchCase(CaseRec& CR, 519 CaseRecVector& WorkList, 520 Value* SV, 521 MachineBasicBlock* Default); 522 bool handleBTSplitSwitchCase(CaseRec& CR, 523 CaseRecVector& WorkList, 524 Value* SV, 525 MachineBasicBlock* Default); 526 bool handleBitTestsSwitchCase(CaseRec& CR, 527 CaseRecVector& WorkList, 528 Value* SV, 529 MachineBasicBlock* Default); 530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B); 532 void visitBitTestCase(MachineBasicBlock* NextMBB, 533 unsigned Reg, 534 SelectionDAGISel::BitTestCase &B); 535 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 537 SelectionDAGISel::JumpTableHeader &JTH); 538 539 // These all get lowered before this pass. 540 void visitInvoke(InvokeInst &I); 541 void visitUnwind(UnwindInst &I); 542 543 void visitBinary(User &I, unsigned OpCode); 544 void visitShift(User &I, unsigned Opcode); 545 void visitAdd(User &I) { 546 if (I.getType()->isFPOrFPVector()) 547 visitBinary(I, ISD::FADD); 548 else 549 visitBinary(I, ISD::ADD); 550 } 551 void visitSub(User &I); 552 void visitMul(User &I) { 553 if (I.getType()->isFPOrFPVector()) 554 visitBinary(I, ISD::FMUL); 555 else 556 visitBinary(I, ISD::MUL); 557 } 558 void visitURem(User &I) { visitBinary(I, ISD::UREM); } 559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); } 560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); } 561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); } 562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); } 563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); } 564 void visitAnd (User &I) { visitBinary(I, ISD::AND); } 565 void visitOr (User &I) { visitBinary(I, ISD::OR); } 566 void visitXor (User &I) { visitBinary(I, ISD::XOR); } 567 void visitShl (User &I) { visitShift(I, ISD::SHL); } 568 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 569 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 570 void visitICmp(User &I); 571 void visitFCmp(User &I); 572 // Visit the conversion instructions 573 void visitTrunc(User &I); 574 void visitZExt(User &I); 575 void visitSExt(User &I); 576 void visitFPTrunc(User &I); 577 void visitFPExt(User &I); 578 void visitFPToUI(User &I); 579 void visitFPToSI(User &I); 580 void visitUIToFP(User &I); 581 void visitSIToFP(User &I); 582 void visitPtrToInt(User &I); 583 void visitIntToPtr(User &I); 584 void visitBitCast(User &I); 585 586 void visitExtractElement(User &I); 587 void visitInsertElement(User &I); 588 void visitShuffleVector(User &I); 589 590 void visitGetElementPtr(User &I); 591 void visitSelect(User &I); 592 593 void visitMalloc(MallocInst &I); 594 void visitFree(FreeInst &I); 595 void visitAlloca(AllocaInst &I); 596 void visitLoad(LoadInst &I); 597 void visitStore(StoreInst &I); 598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 599 void visitCall(CallInst &I); 600 void visitInlineAsm(CallSite CS); 601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 603 604 void visitVAStart(CallInst &I); 605 void visitVAArg(VAArgInst &I); 606 void visitVAEnd(CallInst &I); 607 void visitVACopy(CallInst &I); 608 609 void visitMemIntrinsic(CallInst &I, unsigned Op); 610 611 void visitUserOp1(Instruction &I) { 612 assert(0 && "UserOp1 should not exist at instruction selection time!"); 613 abort(); 614 } 615 void visitUserOp2(Instruction &I) { 616 assert(0 && "UserOp2 should not exist at instruction selection time!"); 617 abort(); 618 } 619}; 620} // end namespace llvm 621 622 623/// getCopyFromParts - Create a value that contains the 624/// specified legal parts combined into the value they represent. 625static SDOperand getCopyFromParts(SelectionDAG &DAG, 626 const SDOperand *Parts, 627 unsigned NumParts, 628 MVT::ValueType PartVT, 629 MVT::ValueType ValueVT, 630 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 631 if (!MVT::isVector(ValueVT) || NumParts == 1) { 632 SDOperand Val = Parts[0]; 633 634 // If the value was expanded, copy from the top part. 635 if (NumParts > 1) { 636 assert(NumParts == 2 && 637 "Cannot expand to more than 2 elts yet!"); 638 SDOperand Hi = Parts[1]; 639 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 640 std::swap(Val, Hi); 641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 642 } 643 644 // Otherwise, if the value was promoted or extended, truncate it to the 645 // appropriate type. 646 if (PartVT == ValueVT) 647 return Val; 648 649 if (MVT::isVector(PartVT)) { 650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); 651 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 652 } 653 654 if (MVT::isVector(ValueVT)) { 655 assert(NumParts == 1 && 656 MVT::getVectorElementType(ValueVT) == PartVT && 657 MVT::getVectorNumElements(ValueVT) == 1 && 658 "Only trivial scalar-to-vector conversions should get here!"); 659 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); 660 } 661 662 if (MVT::isInteger(PartVT) && 663 MVT::isInteger(ValueVT)) { 664 if (ValueVT < PartVT) { 665 // For a truncate, see if we have any information to 666 // indicate whether the truncated bits will always be 667 // zero or sign-extension. 668 if (AssertOp != ISD::DELETED_NODE) 669 Val = DAG.getNode(AssertOp, PartVT, Val, 670 DAG.getValueType(ValueVT)); 671 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 672 } else { 673 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 674 } 675 } 676 677 if (MVT::isFloatingPoint(PartVT) && 678 MVT::isFloatingPoint(ValueVT)) 679 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 680 681 if (MVT::getSizeInBits(PartVT) == 682 MVT::getSizeInBits(ValueVT)) 683 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); 684 685 assert(0 && "Unknown mismatch!"); 686 } 687 688 // Handle a multi-element vector. 689 MVT::ValueType IntermediateVT, RegisterVT; 690 unsigned NumIntermediates; 691 unsigned NumRegs = 692 DAG.getTargetLoweringInfo() 693 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 694 RegisterVT); 695 696 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 697 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 698 assert(RegisterVT == Parts[0].getValueType() && 699 "Part type doesn't match part!"); 700 701 // Assemble the parts into intermediate operands. 702 SmallVector<SDOperand, 8> Ops(NumIntermediates); 703 if (NumIntermediates == NumParts) { 704 // If the register was not expanded, truncate or copy the value, 705 // as appropriate. 706 for (unsigned i = 0; i != NumParts; ++i) 707 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, 708 PartVT, IntermediateVT); 709 } else if (NumParts > 0) { 710 // If the intermediate type was expanded, build the intermediate operands 711 // from the parts. 712 assert(NumParts % NumIntermediates == 0 && 713 "Must expand into a divisible number of parts!"); 714 unsigned Factor = NumParts / NumIntermediates; 715 for (unsigned i = 0; i != NumIntermediates; ++i) 716 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, 717 PartVT, IntermediateVT); 718 } 719 720 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate 721 // operands. 722 return DAG.getNode(MVT::isVector(IntermediateVT) ? 723 ISD::CONCAT_VECTORS : 724 ISD::BUILD_VECTOR, 725 ValueVT, &Ops[0], NumIntermediates); 726} 727 728/// getCopyToParts - Create a series of nodes that contain the 729/// specified value split into legal parts. 730static void getCopyToParts(SelectionDAG &DAG, 731 SDOperand Val, 732 SDOperand *Parts, 733 unsigned NumParts, 734 MVT::ValueType PartVT) { 735 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 736 MVT::ValueType PtrVT = TLI.getPointerTy(); 737 MVT::ValueType ValueVT = Val.getValueType(); 738 739 if (!MVT::isVector(ValueVT) || NumParts == 1) { 740 // If the value was expanded, copy from the parts. 741 if (NumParts > 1) { 742 for (unsigned i = 0; i != NumParts; ++i) 743 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, 744 DAG.getConstant(i, PtrVT)); 745 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 746 std::reverse(Parts, Parts + NumParts); 747 return; 748 } 749 750 // If there is a single part and the types differ, this must be 751 // a promotion. 752 if (PartVT != ValueVT) { 753 if (MVT::isVector(PartVT)) { 754 assert(MVT::isVector(ValueVT) && 755 "Not a vector-vector cast?"); 756 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 757 } else if (MVT::isVector(ValueVT)) { 758 assert(NumParts == 1 && 759 MVT::getVectorElementType(ValueVT) == PartVT && 760 MVT::getVectorNumElements(ValueVT) == 1 && 761 "Only trivial vector-to-scalar conversions should get here!"); 762 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, 763 DAG.getConstant(0, PtrVT)); 764 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { 765 if (PartVT < ValueVT) 766 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val); 767 else 768 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val); 769 } else if (MVT::isFloatingPoint(PartVT) && 770 MVT::isFloatingPoint(ValueVT)) { 771 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); 772 } else if (MVT::getSizeInBits(PartVT) == 773 MVT::getSizeInBits(ValueVT)) { 774 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); 775 } else { 776 assert(0 && "Unknown mismatch!"); 777 } 778 } 779 Parts[0] = Val; 780 return; 781 } 782 783 // Handle a multi-element vector. 784 MVT::ValueType IntermediateVT, RegisterVT; 785 unsigned NumIntermediates; 786 unsigned NumRegs = 787 DAG.getTargetLoweringInfo() 788 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, 789 RegisterVT); 790 unsigned NumElements = MVT::getVectorNumElements(ValueVT); 791 792 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 793 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 794 795 // Split the vector into intermediate operands. 796 SmallVector<SDOperand, 8> Ops(NumIntermediates); 797 for (unsigned i = 0; i != NumIntermediates; ++i) 798 if (MVT::isVector(IntermediateVT)) 799 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, 800 IntermediateVT, Val, 801 DAG.getConstant(i * (NumElements / NumIntermediates), 802 PtrVT)); 803 else 804 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 805 IntermediateVT, Val, 806 DAG.getConstant(i, PtrVT)); 807 808 // Split the intermediate operands into legal parts. 809 if (NumParts == NumIntermediates) { 810 // If the register was not expanded, promote or copy the value, 811 // as appropriate. 812 for (unsigned i = 0; i != NumParts; ++i) 813 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); 814 } else if (NumParts > 0) { 815 // If the intermediate type was expanded, split each the value into 816 // legal parts. 817 assert(NumParts % NumIntermediates == 0 && 818 "Must expand into a divisible number of parts!"); 819 unsigned Factor = NumParts / NumIntermediates; 820 for (unsigned i = 0; i != NumIntermediates; ++i) 821 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); 822 } 823} 824 825 826SDOperand SelectionDAGLowering::getValue(const Value *V) { 827 SDOperand &N = NodeMap[V]; 828 if (N.Val) return N; 829 830 const Type *VTy = V->getType(); 831 MVT::ValueType VT = TLI.getValueType(VTy); 832 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 833 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 834 visit(CE->getOpcode(), *CE); 835 SDOperand N1 = NodeMap[V]; 836 assert(N1.Val && "visit didn't populate the ValueMap!"); 837 return N1; 838 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 839 return N = DAG.getGlobalAddress(GV, VT); 840 } else if (isa<ConstantPointerNull>(C)) { 841 return N = DAG.getConstant(0, TLI.getPointerTy()); 842 } else if (isa<UndefValue>(C)) { 843 if (!isa<VectorType>(VTy)) 844 return N = DAG.getNode(ISD::UNDEF, VT); 845 846 // Create a BUILD_VECTOR of undef nodes. 847 const VectorType *PTy = cast<VectorType>(VTy); 848 unsigned NumElements = PTy->getNumElements(); 849 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 850 851 SmallVector<SDOperand, 8> Ops; 852 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 853 854 // Create a VConstant node with generic Vector type. 855 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 856 return N = DAG.getNode(ISD::BUILD_VECTOR, VT, 857 &Ops[0], Ops.size()); 858 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 859 return N = DAG.getConstantFP(CFP->getValueAPF(), VT); 860 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) { 861 unsigned NumElements = PTy->getNumElements(); 862 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 863 864 // Now that we know the number and type of the elements, push a 865 // Constant or ConstantFP node onto the ops list for each element of 866 // the vector constant. 867 SmallVector<SDOperand, 8> Ops; 868 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 869 for (unsigned i = 0; i != NumElements; ++i) 870 Ops.push_back(getValue(CP->getOperand(i))); 871 } else { 872 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 873 SDOperand Op; 874 if (MVT::isFloatingPoint(PVT)) 875 Op = DAG.getConstantFP(0, PVT); 876 else 877 Op = DAG.getConstant(0, PVT); 878 Ops.assign(NumElements, Op); 879 } 880 881 // Create a BUILD_VECTOR node. 882 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements); 883 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], 884 Ops.size()); 885 } else { 886 // Canonicalize all constant ints to be unsigned. 887 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT); 888 } 889 } 890 891 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 892 std::map<const AllocaInst*, int>::iterator SI = 893 FuncInfo.StaticAllocaMap.find(AI); 894 if (SI != FuncInfo.StaticAllocaMap.end()) 895 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 896 } 897 898 unsigned InReg = FuncInfo.ValueMap[V]; 899 assert(InReg && "Value not in map!"); 900 901 MVT::ValueType RegisterVT = TLI.getRegisterType(VT); 902 unsigned NumRegs = TLI.getNumRegisters(VT); 903 904 std::vector<unsigned> Regs(NumRegs); 905 for (unsigned i = 0; i != NumRegs; ++i) 906 Regs[i] = InReg + i; 907 908 RegsForValue RFV(Regs, RegisterVT, VT); 909 SDOperand Chain = DAG.getEntryNode(); 910 911 return RFV.getCopyFromRegs(DAG, Chain, NULL); 912} 913 914 915void SelectionDAGLowering::visitRet(ReturnInst &I) { 916 if (I.getNumOperands() == 0) { 917 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 918 return; 919 } 920 SmallVector<SDOperand, 8> NewValues; 921 NewValues.push_back(getRoot()); 922 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 923 SDOperand RetOp = getValue(I.getOperand(i)); 924 925 // If this is an integer return value, we need to promote it ourselves to 926 // the full width of a register, since getCopyToParts and Legalize will use 927 // ANY_EXTEND rather than sign/zero. 928 // FIXME: C calling convention requires the return type to be promoted to 929 // at least 32-bit. But this is not necessary for non-C calling conventions. 930 if (MVT::isInteger(RetOp.getValueType()) && 931 RetOp.getValueType() < MVT::i64) { 932 MVT::ValueType TmpVT; 933 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 934 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 935 else 936 TmpVT = MVT::i32; 937 const Function *F = I.getParent()->getParent(); 938 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 939 if (F->paramHasAttr(0, ParamAttr::SExt)) 940 ExtendKind = ISD::SIGN_EXTEND; 941 if (F->paramHasAttr(0, ParamAttr::ZExt)) 942 ExtendKind = ISD::ZERO_EXTEND; 943 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp); 944 NewValues.push_back(RetOp); 945 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 946 } else { 947 MVT::ValueType VT = RetOp.getValueType(); 948 unsigned NumParts = TLI.getNumRegisters(VT); 949 MVT::ValueType PartVT = TLI.getRegisterType(VT); 950 SmallVector<SDOperand, 4> Parts(NumParts); 951 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); 952 for (unsigned i = 0; i < NumParts; ++i) { 953 NewValues.push_back(Parts[i]); 954 NewValues.push_back(DAG.getConstant(false, MVT::i32)); 955 } 956 } 957 } 958 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 959 &NewValues[0], NewValues.size())); 960} 961 962/// ExportFromCurrentBlock - If this condition isn't known to be exported from 963/// the current basic block, add it to ValueMap now so that we'll get a 964/// CopyTo/FromReg. 965void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 966 // No need to export constants. 967 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 968 969 // Already exported? 970 if (FuncInfo.isExportedInst(V)) return; 971 972 unsigned Reg = FuncInfo.InitializeRegForValue(V); 973 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 974} 975 976bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 977 const BasicBlock *FromBB) { 978 // The operands of the setcc have to be in this block. We don't know 979 // how to export them from some other block. 980 if (Instruction *VI = dyn_cast<Instruction>(V)) { 981 // Can export from current BB. 982 if (VI->getParent() == FromBB) 983 return true; 984 985 // Is already exported, noop. 986 return FuncInfo.isExportedInst(V); 987 } 988 989 // If this is an argument, we can export it if the BB is the entry block or 990 // if it is already exported. 991 if (isa<Argument>(V)) { 992 if (FromBB == &FromBB->getParent()->getEntryBlock()) 993 return true; 994 995 // Otherwise, can only export this if it is already exported. 996 return FuncInfo.isExportedInst(V); 997 } 998 999 // Otherwise, constants can always be exported. 1000 return true; 1001} 1002 1003static bool InBlock(const Value *V, const BasicBlock *BB) { 1004 if (const Instruction *I = dyn_cast<Instruction>(V)) 1005 return I->getParent() == BB; 1006 return true; 1007} 1008 1009/// FindMergedConditions - If Cond is an expression like 1010void SelectionDAGLowering::FindMergedConditions(Value *Cond, 1011 MachineBasicBlock *TBB, 1012 MachineBasicBlock *FBB, 1013 MachineBasicBlock *CurBB, 1014 unsigned Opc) { 1015 // If this node is not part of the or/and tree, emit it as a branch. 1016 Instruction *BOp = dyn_cast<Instruction>(Cond); 1017 1018 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1019 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1020 BOp->getParent() != CurBB->getBasicBlock() || 1021 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1022 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1023 const BasicBlock *BB = CurBB->getBasicBlock(); 1024 1025 // If the leaf of the tree is a comparison, merge the condition into 1026 // the caseblock. 1027 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && 1028 // The operands of the cmp have to be in this block. We don't know 1029 // how to export them from some other block. If this is the first block 1030 // of the sequence, no exporting is needed. 1031 (CurBB == CurMBB || 1032 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1033 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 1034 BOp = cast<Instruction>(Cond); 1035 ISD::CondCode Condition; 1036 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1037 switch (IC->getPredicate()) { 1038 default: assert(0 && "Unknown icmp predicate opcode!"); 1039 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break; 1040 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break; 1041 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break; 1042 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break; 1043 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break; 1044 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break; 1045 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break; 1046 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break; 1047 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break; 1048 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break; 1049 } 1050 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1051 ISD::CondCode FPC, FOC; 1052 switch (FC->getPredicate()) { 1053 default: assert(0 && "Unknown fcmp predicate opcode!"); 1054 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 1055 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 1056 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 1057 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 1058 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 1059 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 1060 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 1061 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 1062 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 1063 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 1064 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 1065 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 1066 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 1067 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 1068 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 1069 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 1070 } 1071 if (FiniteOnlyFPMath()) 1072 Condition = FOC; 1073 else 1074 Condition = FPC; 1075 } else { 1076 Condition = ISD::SETEQ; // silence warning. 1077 assert(0 && "Unknown compare instruction"); 1078 } 1079 1080 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 1081 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1082 SwitchCases.push_back(CB); 1083 return; 1084 } 1085 1086 // Create a CaseBlock record representing this branch. 1087 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(), 1088 NULL, TBB, FBB, CurBB); 1089 SwitchCases.push_back(CB); 1090 return; 1091 } 1092 1093 1094 // Create TmpBB after CurBB. 1095 MachineFunction::iterator BBI = CurBB; 1096 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 1097 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 1098 1099 if (Opc == Instruction::Or) { 1100 // Codegen X | Y as: 1101 // jmp_if_X TBB 1102 // jmp TmpBB 1103 // TmpBB: 1104 // jmp_if_Y TBB 1105 // jmp FBB 1106 // 1107 1108 // Emit the LHS condition. 1109 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 1110 1111 // Emit the RHS condition into TmpBB. 1112 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1113 } else { 1114 assert(Opc == Instruction::And && "Unknown merge op!"); 1115 // Codegen X & Y as: 1116 // jmp_if_X TmpBB 1117 // jmp FBB 1118 // TmpBB: 1119 // jmp_if_Y TBB 1120 // jmp FBB 1121 // 1122 // This requires creation of TmpBB after CurBB. 1123 1124 // Emit the LHS condition. 1125 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 1126 1127 // Emit the RHS condition into TmpBB. 1128 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 1129 } 1130} 1131 1132/// If the set of cases should be emitted as a series of branches, return true. 1133/// If we should emit this as a bunch of and/or'd together conditions, return 1134/// false. 1135static bool 1136ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 1137 if (Cases.size() != 2) return true; 1138 1139 // If this is two comparisons of the same values or'd or and'd together, they 1140 // will get folded into a single comparison, so don't emit two blocks. 1141 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1142 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1143 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1144 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1145 return false; 1146 } 1147 1148 return true; 1149} 1150 1151void SelectionDAGLowering::visitBr(BranchInst &I) { 1152 // Update machine-CFG edges. 1153 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1154 1155 // Figure out which block is immediately after the current one. 1156 MachineBasicBlock *NextBlock = 0; 1157 MachineFunction::iterator BBI = CurMBB; 1158 if (++BBI != CurMBB->getParent()->end()) 1159 NextBlock = BBI; 1160 1161 if (I.isUnconditional()) { 1162 // If this is not a fall-through branch, emit the branch. 1163 if (Succ0MBB != NextBlock) 1164 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1165 DAG.getBasicBlock(Succ0MBB))); 1166 1167 // Update machine-CFG edges. 1168 CurMBB->addSuccessor(Succ0MBB); 1169 1170 return; 1171 } 1172 1173 // If this condition is one of the special cases we handle, do special stuff 1174 // now. 1175 Value *CondVal = I.getCondition(); 1176 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1177 1178 // If this is a series of conditions that are or'd or and'd together, emit 1179 // this as a sequence of branches instead of setcc's with and/or operations. 1180 // For example, instead of something like: 1181 // cmp A, B 1182 // C = seteq 1183 // cmp D, E 1184 // F = setle 1185 // or C, F 1186 // jnz foo 1187 // Emit: 1188 // cmp A, B 1189 // je foo 1190 // cmp D, E 1191 // jle foo 1192 // 1193 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1194 if (BOp->hasOneUse() && 1195 (BOp->getOpcode() == Instruction::And || 1196 BOp->getOpcode() == Instruction::Or)) { 1197 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1198 // If the compares in later blocks need to use values not currently 1199 // exported from this block, export them now. This block should always 1200 // be the first entry. 1201 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1202 1203 // Allow some cases to be rejected. 1204 if (ShouldEmitAsBranches(SwitchCases)) { 1205 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1206 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1207 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1208 } 1209 1210 // Emit the branch for this block. 1211 visitSwitchCase(SwitchCases[0]); 1212 SwitchCases.erase(SwitchCases.begin()); 1213 return; 1214 } 1215 1216 // Okay, we decided not to do this, remove any inserted MBB's and clear 1217 // SwitchCases. 1218 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1219 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1220 1221 SwitchCases.clear(); 1222 } 1223 } 1224 1225 // Create a CaseBlock record representing this branch. 1226 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), 1227 NULL, Succ0MBB, Succ1MBB, CurMBB); 1228 // Use visitSwitchCase to actually insert the fast branch sequence for this 1229 // cond branch. 1230 visitSwitchCase(CB); 1231} 1232 1233/// visitSwitchCase - Emits the necessary code to represent a single node in 1234/// the binary search tree resulting from lowering a switch instruction. 1235void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1236 SDOperand Cond; 1237 SDOperand CondLHS = getValue(CB.CmpLHS); 1238 1239 // Build the setcc now. 1240 if (CB.CmpMHS == NULL) { 1241 // Fold "(X == true)" to X and "(X == false)" to !X to 1242 // handle common cases produced by branch lowering. 1243 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ) 1244 Cond = CondLHS; 1245 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { 1246 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1247 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1248 } else 1249 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1250 } else { 1251 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1252 1253 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue(); 1254 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); 1255 1256 SDOperand CmpOp = getValue(CB.CmpMHS); 1257 MVT::ValueType VT = CmpOp.getValueType(); 1258 1259 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1260 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); 1261 } else { 1262 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); 1263 Cond = DAG.getSetCC(MVT::i1, SUB, 1264 DAG.getConstant(High-Low, VT), ISD::SETULE); 1265 } 1266 1267 } 1268 1269 // Set NextBlock to be the MBB immediately after the current one, if any. 1270 // This is used to avoid emitting unnecessary branches to the next block. 1271 MachineBasicBlock *NextBlock = 0; 1272 MachineFunction::iterator BBI = CurMBB; 1273 if (++BBI != CurMBB->getParent()->end()) 1274 NextBlock = BBI; 1275 1276 // If the lhs block is the next block, invert the condition so that we can 1277 // fall through to the lhs instead of the rhs block. 1278 if (CB.TrueBB == NextBlock) { 1279 std::swap(CB.TrueBB, CB.FalseBB); 1280 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1281 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1282 } 1283 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1284 DAG.getBasicBlock(CB.TrueBB)); 1285 if (CB.FalseBB == NextBlock) 1286 DAG.setRoot(BrCond); 1287 else 1288 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1289 DAG.getBasicBlock(CB.FalseBB))); 1290 // Update successor info 1291 CurMBB->addSuccessor(CB.TrueBB); 1292 CurMBB->addSuccessor(CB.FalseBB); 1293} 1294 1295/// visitJumpTable - Emit JumpTable node in the current MBB 1296void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1297 // Emit the code for the jump table 1298 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1299 MVT::ValueType PTy = TLI.getPointerTy(); 1300 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1301 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1302 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1303 Table, Index)); 1304 return; 1305} 1306 1307/// visitJumpTableHeader - This function emits necessary code to produce index 1308/// in the JumpTable from switch case. 1309void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, 1310 SelectionDAGISel::JumpTableHeader &JTH) { 1311 // Subtract the lowest switch case value from the value being switched on 1312 // and conditional branch to default mbb if the result is greater than the 1313 // difference between smallest and largest cases. 1314 SDOperand SwitchOp = getValue(JTH.SValue); 1315 MVT::ValueType VT = SwitchOp.getValueType(); 1316 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1317 DAG.getConstant(JTH.First, VT)); 1318 1319 // The SDNode we just created, which holds the value being switched on 1320 // minus the the smallest case value, needs to be copied to a virtual 1321 // register so it can be used as an index into the jump table in a 1322 // subsequent basic block. This value may be smaller or larger than the 1323 // target's pointer type, and therefore require extension or truncating. 1324 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 1325 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1326 else 1327 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1328 1329 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1330 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1331 JT.Reg = JumpTableReg; 1332 1333 // Emit the range check for the jump table, and branch to the default 1334 // block for the switch statement if the value being switched on exceeds 1335 // the largest case in the switch. 1336 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1337 DAG.getConstant(JTH.Last-JTH.First,VT), 1338 ISD::SETUGT); 1339 1340 // Set NextBlock to be the MBB immediately after the current one, if any. 1341 // This is used to avoid emitting unnecessary branches to the next block. 1342 MachineBasicBlock *NextBlock = 0; 1343 MachineFunction::iterator BBI = CurMBB; 1344 if (++BBI != CurMBB->getParent()->end()) 1345 NextBlock = BBI; 1346 1347 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1348 DAG.getBasicBlock(JT.Default)); 1349 1350 if (JT.MBB == NextBlock) 1351 DAG.setRoot(BrCond); 1352 else 1353 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1354 DAG.getBasicBlock(JT.MBB))); 1355 1356 return; 1357} 1358 1359/// visitBitTestHeader - This function emits necessary code to produce value 1360/// suitable for "bit tests" 1361void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { 1362 // Subtract the minimum value 1363 SDOperand SwitchOp = getValue(B.SValue); 1364 MVT::ValueType VT = SwitchOp.getValueType(); 1365 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1366 DAG.getConstant(B.First, VT)); 1367 1368 // Check range 1369 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1370 DAG.getConstant(B.Range, VT), 1371 ISD::SETUGT); 1372 1373 SDOperand ShiftOp; 1374 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) 1375 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); 1376 else 1377 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); 1378 1379 // Make desired shift 1380 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), 1381 DAG.getConstant(1, TLI.getPointerTy()), 1382 ShiftOp); 1383 1384 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1385 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal); 1386 B.Reg = SwitchReg; 1387 1388 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, 1389 DAG.getBasicBlock(B.Default)); 1390 1391 // Set NextBlock to be the MBB immediately after the current one, if any. 1392 // This is used to avoid emitting unnecessary branches to the next block. 1393 MachineBasicBlock *NextBlock = 0; 1394 MachineFunction::iterator BBI = CurMBB; 1395 if (++BBI != CurMBB->getParent()->end()) 1396 NextBlock = BBI; 1397 1398 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1399 if (MBB == NextBlock) 1400 DAG.setRoot(BrRange); 1401 else 1402 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, 1403 DAG.getBasicBlock(MBB))); 1404 1405 CurMBB->addSuccessor(B.Default); 1406 CurMBB->addSuccessor(MBB); 1407 1408 return; 1409} 1410 1411/// visitBitTestCase - this function produces one "bit test" 1412void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, 1413 unsigned Reg, 1414 SelectionDAGISel::BitTestCase &B) { 1415 // Emit bit tests and jumps 1416 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy()); 1417 1418 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), 1419 SwitchVal, 1420 DAG.getConstant(B.Mask, 1421 TLI.getPointerTy())); 1422 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp, 1423 DAG.getConstant(0, TLI.getPointerTy()), 1424 ISD::SETNE); 1425 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 1426 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1427 1428 // Set NextBlock to be the MBB immediately after the current one, if any. 1429 // This is used to avoid emitting unnecessary branches to the next block. 1430 MachineBasicBlock *NextBlock = 0; 1431 MachineFunction::iterator BBI = CurMBB; 1432 if (++BBI != CurMBB->getParent()->end()) 1433 NextBlock = BBI; 1434 1435 if (NextMBB == NextBlock) 1436 DAG.setRoot(BrAnd); 1437 else 1438 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, 1439 DAG.getBasicBlock(NextMBB))); 1440 1441 CurMBB->addSuccessor(B.TargetBB); 1442 CurMBB->addSuccessor(NextMBB); 1443 1444 return; 1445} 1446 1447void SelectionDAGLowering::visitInvoke(InvokeInst &I) { 1448 // Retrieve successors. 1449 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1450 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1451 1452 if (isa<InlineAsm>(I.getCalledValue())) 1453 visitInlineAsm(&I); 1454 else 1455 LowerCallTo(I, I.getCalledValue()->getType(), I.getParamAttrs(), 1456 I.getCallingConv(), 1457 false, 1458 getValue(I.getOperand(0)), 1459 3, LandingPad); 1460 1461 // If the value of the invoke is used outside of its defining block, make it 1462 // available as a virtual register. 1463 if (!I.use_empty()) { 1464 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I); 1465 if (VMI != FuncInfo.ValueMap.end()) 1466 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second)); 1467 } 1468 1469 // Drop into normal successor. 1470 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1471 DAG.getBasicBlock(Return))); 1472 1473 // Update successor info 1474 CurMBB->addSuccessor(Return); 1475 CurMBB->addSuccessor(LandingPad); 1476} 1477 1478void SelectionDAGLowering::visitUnwind(UnwindInst &I) { 1479} 1480 1481/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1482/// small case ranges). 1483bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, 1484 CaseRecVector& WorkList, 1485 Value* SV, 1486 MachineBasicBlock* Default) { 1487 Case& BackCase = *(CR.Range.second-1); 1488 1489 // Size is the number of Cases represented by this range. 1490 unsigned Size = CR.Range.second - CR.Range.first; 1491 if (Size > 3) 1492 return false; 1493 1494 // Get the MachineFunction which holds the current MBB. This is used when 1495 // inserting any additional MBBs necessary to represent the switch. 1496 MachineFunction *CurMF = CurMBB->getParent(); 1497 1498 // Figure out which block is immediately after the current one. 1499 MachineBasicBlock *NextBlock = 0; 1500 MachineFunction::iterator BBI = CR.CaseBB; 1501 1502 if (++BBI != CurMBB->getParent()->end()) 1503 NextBlock = BBI; 1504 1505 // TODO: If any two of the cases has the same destination, and if one value 1506 // is the same as the other, but has one bit unset that the other has set, 1507 // use bit manipulation to do two compares at once. For example: 1508 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1509 1510 // Rearrange the case blocks so that the last one falls through if possible. 1511 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1512 // The last case block won't fall through into 'NextBlock' if we emit the 1513 // branches in this order. See if rearranging a case value would help. 1514 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1515 if (I->BB == NextBlock) { 1516 std::swap(*I, BackCase); 1517 break; 1518 } 1519 } 1520 } 1521 1522 // Create a CaseBlock record representing a conditional branch to 1523 // the Case's target mbb if the value being switched on SV is equal 1524 // to C. 1525 MachineBasicBlock *CurBlock = CR.CaseBB; 1526 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1527 MachineBasicBlock *FallThrough; 1528 if (I != E-1) { 1529 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); 1530 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1531 } else { 1532 // If the last case doesn't match, go to the default block. 1533 FallThrough = Default; 1534 } 1535 1536 Value *RHS, *LHS, *MHS; 1537 ISD::CondCode CC; 1538 if (I->High == I->Low) { 1539 // This is just small small case range :) containing exactly 1 case 1540 CC = ISD::SETEQ; 1541 LHS = SV; RHS = I->High; MHS = NULL; 1542 } else { 1543 CC = ISD::SETLE; 1544 LHS = I->Low; MHS = SV; RHS = I->High; 1545 } 1546 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS, 1547 I->BB, FallThrough, CurBlock); 1548 1549 // If emitting the first comparison, just call visitSwitchCase to emit the 1550 // code into the current block. Otherwise, push the CaseBlock onto the 1551 // vector to be later processed by SDISel, and insert the node's MBB 1552 // before the next MBB. 1553 if (CurBlock == CurMBB) 1554 visitSwitchCase(CB); 1555 else 1556 SwitchCases.push_back(CB); 1557 1558 CurBlock = FallThrough; 1559 } 1560 1561 return true; 1562} 1563 1564static inline bool areJTsAllowed(const TargetLowering &TLI) { 1565 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1566 TLI.isOperationLegal(ISD::BRIND, MVT::Other)); 1567} 1568 1569/// handleJTSwitchCase - Emit jumptable for current switch case range 1570bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, 1571 CaseRecVector& WorkList, 1572 Value* SV, 1573 MachineBasicBlock* Default) { 1574 Case& FrontCase = *CR.Range.first; 1575 Case& BackCase = *(CR.Range.second-1); 1576 1577 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1578 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1579 1580 uint64_t TSize = 0; 1581 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1582 I!=E; ++I) 1583 TSize += I->size(); 1584 1585 if (!areJTsAllowed(TLI) || TSize <= 3) 1586 return false; 1587 1588 double Density = (double)TSize / (double)((Last - First) + 1ULL); 1589 if (Density < 0.4) 1590 return false; 1591 1592 DOUT << "Lowering jump table\n" 1593 << "First entry: " << First << ". Last entry: " << Last << "\n" 1594 << "Size: " << TSize << ". Density: " << Density << "\n\n"; 1595 1596 // Get the MachineFunction which holds the current MBB. This is used when 1597 // inserting any additional MBBs necessary to represent the switch. 1598 MachineFunction *CurMF = CurMBB->getParent(); 1599 1600 // Figure out which block is immediately after the current one. 1601 MachineBasicBlock *NextBlock = 0; 1602 MachineFunction::iterator BBI = CR.CaseBB; 1603 1604 if (++BBI != CurMBB->getParent()->end()) 1605 NextBlock = BBI; 1606 1607 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1608 1609 // Create a new basic block to hold the code for loading the address 1610 // of the jump table, and jumping to it. Update successor information; 1611 // we will either branch to the default case for the switch, or the jump 1612 // table. 1613 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1614 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1615 CR.CaseBB->addSuccessor(Default); 1616 CR.CaseBB->addSuccessor(JumpTableBB); 1617 1618 // Build a vector of destination BBs, corresponding to each target 1619 // of the jump table. If the value of the jump table slot corresponds to 1620 // a case statement, push the case's BB onto the vector, otherwise, push 1621 // the default BB. 1622 std::vector<MachineBasicBlock*> DestBBs; 1623 int64_t TEI = First; 1624 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1625 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue(); 1626 int64_t High = cast<ConstantInt>(I->High)->getSExtValue(); 1627 1628 if ((Low <= TEI) && (TEI <= High)) { 1629 DestBBs.push_back(I->BB); 1630 if (TEI==High) 1631 ++I; 1632 } else { 1633 DestBBs.push_back(Default); 1634 } 1635 } 1636 1637 // Update successor info. Add one edge to each unique successor. 1638 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1639 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1640 E = DestBBs.end(); I != E; ++I) { 1641 if (!SuccsHandled[(*I)->getNumber()]) { 1642 SuccsHandled[(*I)->getNumber()] = true; 1643 JumpTableBB->addSuccessor(*I); 1644 } 1645 } 1646 1647 // Create a jump table index for this jump table, or return an existing 1648 // one. 1649 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1650 1651 // Set the jump table information so that we can codegen it as a second 1652 // MachineBasicBlock 1653 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default); 1654 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB, 1655 (CR.CaseBB == CurMBB)); 1656 if (CR.CaseBB == CurMBB) 1657 visitJumpTableHeader(JT, JTH); 1658 1659 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT)); 1660 1661 return true; 1662} 1663 1664/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1665/// 2 subtrees. 1666bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, 1667 CaseRecVector& WorkList, 1668 Value* SV, 1669 MachineBasicBlock* Default) { 1670 // Get the MachineFunction which holds the current MBB. This is used when 1671 // inserting any additional MBBs necessary to represent the switch. 1672 MachineFunction *CurMF = CurMBB->getParent(); 1673 1674 // Figure out which block is immediately after the current one. 1675 MachineBasicBlock *NextBlock = 0; 1676 MachineFunction::iterator BBI = CR.CaseBB; 1677 1678 if (++BBI != CurMBB->getParent()->end()) 1679 NextBlock = BBI; 1680 1681 Case& FrontCase = *CR.Range.first; 1682 Case& BackCase = *(CR.Range.second-1); 1683 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1684 1685 // Size is the number of Cases represented by this range. 1686 unsigned Size = CR.Range.second - CR.Range.first; 1687 1688 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue(); 1689 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue(); 1690 double FMetric = 0; 1691 CaseItr Pivot = CR.Range.first + Size/2; 1692 1693 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1694 // (heuristically) allow us to emit JumpTable's later. 1695 uint64_t TSize = 0; 1696 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1697 I!=E; ++I) 1698 TSize += I->size(); 1699 1700 uint64_t LSize = FrontCase.size(); 1701 uint64_t RSize = TSize-LSize; 1702 DOUT << "Selecting best pivot: \n" 1703 << "First: " << First << ", Last: " << Last <<"\n" 1704 << "LSize: " << LSize << ", RSize: " << RSize << "\n"; 1705 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1706 J!=E; ++I, ++J) { 1707 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue(); 1708 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue(); 1709 assert((RBegin-LEnd>=1) && "Invalid case distance"); 1710 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); 1711 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); 1712 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); 1713 // Should always split in some non-trivial place 1714 DOUT <<"=>Step\n" 1715 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" 1716 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" 1717 << "Metric: " << Metric << "\n"; 1718 if (FMetric < Metric) { 1719 Pivot = J; 1720 FMetric = Metric; 1721 DOUT << "Current metric set to: " << FMetric << "\n"; 1722 } 1723 1724 LSize += J->size(); 1725 RSize -= J->size(); 1726 } 1727 if (areJTsAllowed(TLI)) { 1728 // If our case is dense we *really* should handle it earlier! 1729 assert((FMetric > 0) && "Should handle dense range earlier!"); 1730 } else { 1731 Pivot = CR.Range.first + Size/2; 1732 } 1733 1734 CaseRange LHSR(CR.Range.first, Pivot); 1735 CaseRange RHSR(Pivot, CR.Range.second); 1736 Constant *C = Pivot->Low; 1737 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1738 1739 // We know that we branch to the LHS if the Value being switched on is 1740 // less than the Pivot value, C. We use this to optimize our binary 1741 // tree a bit, by recognizing that if SV is greater than or equal to the 1742 // LHS's Case Value, and that Case Value is exactly one less than the 1743 // Pivot's Value, then we can branch directly to the LHS's Target, 1744 // rather than creating a leaf node for it. 1745 if ((LHSR.second - LHSR.first) == 1 && 1746 LHSR.first->High == CR.GE && 1747 cast<ConstantInt>(C)->getSExtValue() == 1748 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) { 1749 TrueBB = LHSR.first->BB; 1750 } else { 1751 TrueBB = new MachineBasicBlock(LLVMBB); 1752 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1753 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1754 } 1755 1756 // Similar to the optimization above, if the Value being switched on is 1757 // known to be less than the Constant CR.LT, and the current Case Value 1758 // is CR.LT - 1, then we can branch directly to the target block for 1759 // the current Case Value, rather than emitting a RHS leaf node for it. 1760 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1761 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() == 1762 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) { 1763 FalseBB = RHSR.first->BB; 1764 } else { 1765 FalseBB = new MachineBasicBlock(LLVMBB); 1766 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1767 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1768 } 1769 1770 // Create a CaseBlock record representing a conditional branch to 1771 // the LHS node if the value being switched on SV is less than C. 1772 // Otherwise, branch to LHS. 1773 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL, 1774 TrueBB, FalseBB, CR.CaseBB); 1775 1776 if (CR.CaseBB == CurMBB) 1777 visitSwitchCase(CB); 1778 else 1779 SwitchCases.push_back(CB); 1780 1781 return true; 1782} 1783 1784/// handleBitTestsSwitchCase - if current case range has few destination and 1785/// range span less, than machine word bitwidth, encode case range into series 1786/// of masks and emit bit tests with these masks. 1787bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, 1788 CaseRecVector& WorkList, 1789 Value* SV, 1790 MachineBasicBlock* Default){ 1791 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); 1792 1793 Case& FrontCase = *CR.Range.first; 1794 Case& BackCase = *(CR.Range.second-1); 1795 1796 // Get the MachineFunction which holds the current MBB. This is used when 1797 // inserting any additional MBBs necessary to represent the switch. 1798 MachineFunction *CurMF = CurMBB->getParent(); 1799 1800 unsigned numCmps = 0; 1801 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1802 I!=E; ++I) { 1803 // Single case counts one, case range - two. 1804 if (I->Low == I->High) 1805 numCmps +=1; 1806 else 1807 numCmps +=2; 1808 } 1809 1810 // Count unique destinations 1811 SmallSet<MachineBasicBlock*, 4> Dests; 1812 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1813 Dests.insert(I->BB); 1814 if (Dests.size() > 3) 1815 // Don't bother the code below, if there are too much unique destinations 1816 return false; 1817 } 1818 DOUT << "Total number of unique destinations: " << Dests.size() << "\n" 1819 << "Total number of comparisons: " << numCmps << "\n"; 1820 1821 // Compute span of values. 1822 Constant* minValue = FrontCase.Low; 1823 Constant* maxValue = BackCase.High; 1824 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() - 1825 cast<ConstantInt>(minValue)->getSExtValue(); 1826 DOUT << "Compare range: " << range << "\n" 1827 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n" 1828 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n"; 1829 1830 if (range>=IntPtrBits || 1831 (!(Dests.size() == 1 && numCmps >= 3) && 1832 !(Dests.size() == 2 && numCmps >= 5) && 1833 !(Dests.size() >= 3 && numCmps >= 6))) 1834 return false; 1835 1836 DOUT << "Emitting bit tests\n"; 1837 int64_t lowBound = 0; 1838 1839 // Optimize the case where all the case values fit in a 1840 // word without having to subtract minValue. In this case, 1841 // we can optimize away the subtraction. 1842 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 && 1843 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) { 1844 range = cast<ConstantInt>(maxValue)->getSExtValue(); 1845 } else { 1846 lowBound = cast<ConstantInt>(minValue)->getSExtValue(); 1847 } 1848 1849 CaseBitsVector CasesBits; 1850 unsigned i, count = 0; 1851 1852 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1853 MachineBasicBlock* Dest = I->BB; 1854 for (i = 0; i < count; ++i) 1855 if (Dest == CasesBits[i].BB) 1856 break; 1857 1858 if (i == count) { 1859 assert((count < 3) && "Too much destinations to test!"); 1860 CasesBits.push_back(CaseBits(0, Dest, 0)); 1861 count++; 1862 } 1863 1864 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound; 1865 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound; 1866 1867 for (uint64_t j = lo; j <= hi; j++) { 1868 CasesBits[i].Mask |= 1ULL << j; 1869 CasesBits[i].Bits++; 1870 } 1871 1872 } 1873 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1874 1875 SelectionDAGISel::BitTestInfo BTC; 1876 1877 // Figure out which block is immediately after the current one. 1878 MachineFunction::iterator BBI = CR.CaseBB; 1879 ++BBI; 1880 1881 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1882 1883 DOUT << "Cases:\n"; 1884 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1885 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits 1886 << ", BB: " << CasesBits[i].BB << "\n"; 1887 1888 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); 1889 CurMF->getBasicBlockList().insert(BBI, CaseBB); 1890 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, 1891 CaseBB, 1892 CasesBits[i].BB)); 1893 } 1894 1895 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, 1896 -1U, (CR.CaseBB == CurMBB), 1897 CR.CaseBB, Default, BTC); 1898 1899 if (CR.CaseBB == CurMBB) 1900 visitBitTestHeader(BTB); 1901 1902 BitTestCases.push_back(BTB); 1903 1904 return true; 1905} 1906 1907 1908// Clusterify - Transform simple list of Cases into list of CaseRange's 1909unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, 1910 const SwitchInst& SI) { 1911 unsigned numCmps = 0; 1912 1913 // Start with "simple" cases 1914 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { 1915 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1916 Cases.push_back(Case(SI.getSuccessorValue(i), 1917 SI.getSuccessorValue(i), 1918 SMBB)); 1919 } 1920 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1921 1922 // Merge case into clusters 1923 if (Cases.size()>=2) 1924 // Must recompute end() each iteration because it may be 1925 // invalidated by erase if we hold on to it 1926 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { 1927 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue(); 1928 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue(); 1929 MachineBasicBlock* nextBB = J->BB; 1930 MachineBasicBlock* currentBB = I->BB; 1931 1932 // If the two neighboring cases go to the same destination, merge them 1933 // into a single case. 1934 if ((nextValue-currentValue==1) && (currentBB == nextBB)) { 1935 I->High = J->High; 1936 J = Cases.erase(J); 1937 } else { 1938 I = J++; 1939 } 1940 } 1941 1942 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1943 if (I->Low != I->High) 1944 // A range counts double, since it requires two compares. 1945 ++numCmps; 1946 } 1947 1948 return numCmps; 1949} 1950 1951void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { 1952 // Figure out which block is immediately after the current one. 1953 MachineBasicBlock *NextBlock = 0; 1954 MachineFunction::iterator BBI = CurMBB; 1955 1956 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1957 1958 // If there is only the default destination, branch to it if it is not the 1959 // next basic block. Otherwise, just fall through. 1960 if (SI.getNumOperands() == 2) { 1961 // Update machine-CFG edges. 1962 1963 // If this is not a fall-through branch, emit the branch. 1964 if (Default != NextBlock) 1965 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1966 DAG.getBasicBlock(Default))); 1967 1968 CurMBB->addSuccessor(Default); 1969 return; 1970 } 1971 1972 // If there are any non-default case statements, create a vector of Cases 1973 // representing each one, and sort the vector so that we can efficiently 1974 // create a binary search tree from them. 1975 CaseVector Cases; 1976 unsigned numCmps = Clusterify(Cases, SI); 1977 DOUT << "Clusterify finished. Total clusters: " << Cases.size() 1978 << ". Total compares: " << numCmps << "\n"; 1979 1980 // Get the Value to be switched on and default basic blocks, which will be 1981 // inserted into CaseBlock records, representing basic blocks in the binary 1982 // search tree. 1983 Value *SV = SI.getOperand(0); 1984 1985 // Push the initial CaseRec onto the worklist 1986 CaseRecVector WorkList; 1987 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1988 1989 while (!WorkList.empty()) { 1990 // Grab a record representing a case range to process off the worklist 1991 CaseRec CR = WorkList.back(); 1992 WorkList.pop_back(); 1993 1994 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) 1995 continue; 1996 1997 // If the range has few cases (two or less) emit a series of specific 1998 // tests. 1999 if (handleSmallSwitchRange(CR, WorkList, SV, Default)) 2000 continue; 2001 2002 // If the switch has more than 5 blocks, and at least 40% dense, and the 2003 // target supports indirect branches, then emit a jump table rather than 2004 // lowering the switch to a binary tree of conditional branches. 2005 if (handleJTSwitchCase(CR, WorkList, SV, Default)) 2006 continue; 2007 2008 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2009 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2010 handleBTSplitSwitchCase(CR, WorkList, SV, Default); 2011 } 2012} 2013 2014 2015void SelectionDAGLowering::visitSub(User &I) { 2016 // -0.0 - X --> fneg 2017 const Type *Ty = I.getType(); 2018 if (isa<VectorType>(Ty)) { 2019 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2020 const VectorType *DestTy = cast<VectorType>(I.getType()); 2021 const Type *ElTy = DestTy->getElementType(); 2022 if (ElTy->isFloatingPoint()) { 2023 unsigned VL = DestTy->getNumElements(); 2024 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2025 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2026 if (CV == CNZ) { 2027 SDOperand Op2 = getValue(I.getOperand(1)); 2028 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2029 return; 2030 } 2031 } 2032 } 2033 } 2034 if (Ty->isFloatingPoint()) { 2035 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2036 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2037 SDOperand Op2 = getValue(I.getOperand(1)); 2038 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 2039 return; 2040 } 2041 } 2042 2043 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB); 2044} 2045 2046void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { 2047 SDOperand Op1 = getValue(I.getOperand(0)); 2048 SDOperand Op2 = getValue(I.getOperand(1)); 2049 2050 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); 2051} 2052 2053void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 2054 SDOperand Op1 = getValue(I.getOperand(0)); 2055 SDOperand Op2 = getValue(I.getOperand(1)); 2056 2057 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < 2058 MVT::getSizeInBits(Op2.getValueType())) 2059 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); 2060 else if (TLI.getShiftAmountTy() > Op2.getValueType()) 2061 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 2062 2063 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 2064} 2065 2066void SelectionDAGLowering::visitICmp(User &I) { 2067 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2068 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2069 predicate = IC->getPredicate(); 2070 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2071 predicate = ICmpInst::Predicate(IC->getPredicate()); 2072 SDOperand Op1 = getValue(I.getOperand(0)); 2073 SDOperand Op2 = getValue(I.getOperand(1)); 2074 ISD::CondCode Opcode; 2075 switch (predicate) { 2076 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 2077 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 2078 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 2079 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 2080 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 2081 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 2082 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 2083 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 2084 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 2085 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 2086 default: 2087 assert(!"Invalid ICmp predicate value"); 2088 Opcode = ISD::SETEQ; 2089 break; 2090 } 2091 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 2092} 2093 2094void SelectionDAGLowering::visitFCmp(User &I) { 2095 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2096 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2097 predicate = FC->getPredicate(); 2098 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2099 predicate = FCmpInst::Predicate(FC->getPredicate()); 2100 SDOperand Op1 = getValue(I.getOperand(0)); 2101 SDOperand Op2 = getValue(I.getOperand(1)); 2102 ISD::CondCode Condition, FOC, FPC; 2103 switch (predicate) { 2104 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 2105 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 2106 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 2107 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 2108 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 2109 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 2110 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 2111 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break; 2112 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break; 2113 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 2114 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 2115 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 2116 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 2117 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 2118 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 2119 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 2120 default: 2121 assert(!"Invalid FCmp predicate value"); 2122 FOC = FPC = ISD::SETFALSE; 2123 break; 2124 } 2125 if (FiniteOnlyFPMath()) 2126 Condition = FOC; 2127 else 2128 Condition = FPC; 2129 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); 2130} 2131 2132void SelectionDAGLowering::visitSelect(User &I) { 2133 SDOperand Cond = getValue(I.getOperand(0)); 2134 SDOperand TrueVal = getValue(I.getOperand(1)); 2135 SDOperand FalseVal = getValue(I.getOperand(2)); 2136 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 2137 TrueVal, FalseVal)); 2138} 2139 2140 2141void SelectionDAGLowering::visitTrunc(User &I) { 2142 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2143 SDOperand N = getValue(I.getOperand(0)); 2144 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2145 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2146} 2147 2148void SelectionDAGLowering::visitZExt(User &I) { 2149 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2150 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2151 SDOperand N = getValue(I.getOperand(0)); 2152 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2153 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2154} 2155 2156void SelectionDAGLowering::visitSExt(User &I) { 2157 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2158 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2159 SDOperand N = getValue(I.getOperand(0)); 2160 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2161 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 2162} 2163 2164void SelectionDAGLowering::visitFPTrunc(User &I) { 2165 // FPTrunc is never a no-op cast, no need to check 2166 SDOperand N = getValue(I.getOperand(0)); 2167 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2168 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 2169} 2170 2171void SelectionDAGLowering::visitFPExt(User &I){ 2172 // FPTrunc is never a no-op cast, no need to check 2173 SDOperand N = getValue(I.getOperand(0)); 2174 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2175 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 2176} 2177 2178void SelectionDAGLowering::visitFPToUI(User &I) { 2179 // FPToUI is never a no-op cast, no need to check 2180 SDOperand N = getValue(I.getOperand(0)); 2181 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2182 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 2183} 2184 2185void SelectionDAGLowering::visitFPToSI(User &I) { 2186 // FPToSI is never a no-op cast, no need to check 2187 SDOperand N = getValue(I.getOperand(0)); 2188 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2189 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 2190} 2191 2192void SelectionDAGLowering::visitUIToFP(User &I) { 2193 // UIToFP is never a no-op cast, no need to check 2194 SDOperand N = getValue(I.getOperand(0)); 2195 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2196 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 2197} 2198 2199void SelectionDAGLowering::visitSIToFP(User &I){ 2200 // UIToFP is never a no-op cast, no need to check 2201 SDOperand N = getValue(I.getOperand(0)); 2202 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2203 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 2204} 2205 2206void SelectionDAGLowering::visitPtrToInt(User &I) { 2207 // What to do depends on the size of the integer and the size of the pointer. 2208 // We can either truncate, zero extend, or no-op, accordingly. 2209 SDOperand N = getValue(I.getOperand(0)); 2210 MVT::ValueType SrcVT = N.getValueType(); 2211 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2212 SDOperand Result; 2213 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2214 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 2215 else 2216 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2217 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 2218 setValue(&I, Result); 2219} 2220 2221void SelectionDAGLowering::visitIntToPtr(User &I) { 2222 // What to do depends on the size of the integer and the size of the pointer. 2223 // We can either truncate, zero extend, or no-op, accordingly. 2224 SDOperand N = getValue(I.getOperand(0)); 2225 MVT::ValueType SrcVT = N.getValueType(); 2226 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2227 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 2228 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 2229 else 2230 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 2231 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 2232} 2233 2234void SelectionDAGLowering::visitBitCast(User &I) { 2235 SDOperand N = getValue(I.getOperand(0)); 2236 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 2237 2238 // BitCast assures us that source and destination are the same size so this 2239 // is either a BIT_CONVERT or a no-op. 2240 if (DestVT != N.getValueType()) 2241 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 2242 else 2243 setValue(&I, N); // noop cast. 2244} 2245 2246void SelectionDAGLowering::visitInsertElement(User &I) { 2247 SDOperand InVec = getValue(I.getOperand(0)); 2248 SDOperand InVal = getValue(I.getOperand(1)); 2249 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2250 getValue(I.getOperand(2))); 2251 2252 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, 2253 TLI.getValueType(I.getType()), 2254 InVec, InVal, InIdx)); 2255} 2256 2257void SelectionDAGLowering::visitExtractElement(User &I) { 2258 SDOperand InVec = getValue(I.getOperand(0)); 2259 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 2260 getValue(I.getOperand(1))); 2261 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 2262 TLI.getValueType(I.getType()), InVec, InIdx)); 2263} 2264 2265void SelectionDAGLowering::visitShuffleVector(User &I) { 2266 SDOperand V1 = getValue(I.getOperand(0)); 2267 SDOperand V2 = getValue(I.getOperand(1)); 2268 SDOperand Mask = getValue(I.getOperand(2)); 2269 2270 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, 2271 TLI.getValueType(I.getType()), 2272 V1, V2, Mask)); 2273} 2274 2275 2276void SelectionDAGLowering::visitGetElementPtr(User &I) { 2277 SDOperand N = getValue(I.getOperand(0)); 2278 const Type *Ty = I.getOperand(0)->getType(); 2279 2280 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 2281 OI != E; ++OI) { 2282 Value *Idx = *OI; 2283 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2284 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2285 if (Field) { 2286 // N = N + Offset 2287 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2288 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 2289 getIntPtrConstant(Offset)); 2290 } 2291 Ty = StTy->getElementType(Field); 2292 } else { 2293 Ty = cast<SequentialType>(Ty)->getElementType(); 2294 2295 // If this is a constant subscript, handle it quickly. 2296 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2297 if (CI->getZExtValue() == 0) continue; 2298 uint64_t Offs = 2299 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2300 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 2301 continue; 2302 } 2303 2304 // N = N + Idx * ElementSize; 2305 uint64_t ElementSize = TD->getABITypeSize(Ty); 2306 SDOperand IdxN = getValue(Idx); 2307 2308 // If the index is smaller or larger than intptr_t, truncate or extend 2309 // it. 2310 if (IdxN.getValueType() < N.getValueType()) { 2311 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 2312 } else if (IdxN.getValueType() > N.getValueType()) 2313 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 2314 2315 // If this is a multiply by a power of two, turn it into a shl 2316 // immediately. This is a very common case. 2317 if (isPowerOf2_64(ElementSize)) { 2318 unsigned Amt = Log2_64(ElementSize); 2319 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 2320 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 2321 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2322 continue; 2323 } 2324 2325 SDOperand Scale = getIntPtrConstant(ElementSize); 2326 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 2327 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 2328 } 2329 } 2330 setValue(&I, N); 2331} 2332 2333void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 2334 // If this is a fixed sized alloca in the entry block of the function, 2335 // allocate it statically on the stack. 2336 if (FuncInfo.StaticAllocaMap.count(&I)) 2337 return; // getValue will auto-populate this. 2338 2339 const Type *Ty = I.getAllocatedType(); 2340 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 2341 unsigned Align = 2342 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2343 I.getAlignment()); 2344 2345 SDOperand AllocSize = getValue(I.getArraySize()); 2346 MVT::ValueType IntPtr = TLI.getPointerTy(); 2347 if (IntPtr < AllocSize.getValueType()) 2348 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 2349 else if (IntPtr > AllocSize.getValueType()) 2350 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 2351 2352 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 2353 getIntPtrConstant(TySize)); 2354 2355 // Handle alignment. If the requested alignment is less than or equal to 2356 // the stack alignment, ignore it. If the size is greater than or equal to 2357 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2358 unsigned StackAlign = 2359 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 2360 if (Align <= StackAlign) 2361 Align = 0; 2362 2363 // Round the size of the allocation up to the stack alignment size 2364 // by add SA-1 to the size. 2365 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 2366 getIntPtrConstant(StackAlign-1)); 2367 // Mask out the low bits for alignment purposes. 2368 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 2369 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2370 2371 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 2372 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 2373 MVT::Other); 2374 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 2375 setValue(&I, DSA); 2376 DAG.setRoot(DSA.getValue(1)); 2377 2378 // Inform the Frame Information that we have just allocated a variable-sized 2379 // object. 2380 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 2381} 2382 2383void SelectionDAGLowering::visitLoad(LoadInst &I) { 2384 SDOperand Ptr = getValue(I.getOperand(0)); 2385 2386 SDOperand Root; 2387 if (I.isVolatile()) 2388 Root = getRoot(); 2389 else { 2390 // Do not serialize non-volatile loads against each other. 2391 Root = DAG.getRoot(); 2392 } 2393 2394 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 2395 Root, I.isVolatile(), I.getAlignment())); 2396} 2397 2398SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 2399 const Value *SV, SDOperand Root, 2400 bool isVolatile, 2401 unsigned Alignment) { 2402 SDOperand L = 2403 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, 2404 isVolatile, Alignment); 2405 2406 if (isVolatile) 2407 DAG.setRoot(L.getValue(1)); 2408 else 2409 PendingLoads.push_back(L.getValue(1)); 2410 2411 return L; 2412} 2413 2414 2415void SelectionDAGLowering::visitStore(StoreInst &I) { 2416 Value *SrcV = I.getOperand(0); 2417 SDOperand Src = getValue(SrcV); 2418 SDOperand Ptr = getValue(I.getOperand(1)); 2419 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, 2420 I.isVolatile(), I.getAlignment())); 2421} 2422 2423/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2424/// node. 2425void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 2426 unsigned Intrinsic) { 2427 bool HasChain = !I.doesNotAccessMemory(); 2428 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2429 2430 // Build the operand list. 2431 SmallVector<SDOperand, 8> Ops; 2432 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2433 if (OnlyLoad) { 2434 // We don't need to serialize loads against other loads. 2435 Ops.push_back(DAG.getRoot()); 2436 } else { 2437 Ops.push_back(getRoot()); 2438 } 2439 } 2440 2441 // Add the intrinsic ID as an integer operand. 2442 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2443 2444 // Add all operands of the call to the operand list. 2445 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2446 SDOperand Op = getValue(I.getOperand(i)); 2447 assert(TLI.isTypeLegal(Op.getValueType()) && 2448 "Intrinsic uses a non-legal type?"); 2449 Ops.push_back(Op); 2450 } 2451 2452 std::vector<MVT::ValueType> VTs; 2453 if (I.getType() != Type::VoidTy) { 2454 MVT::ValueType VT = TLI.getValueType(I.getType()); 2455 if (MVT::isVector(VT)) { 2456 const VectorType *DestTy = cast<VectorType>(I.getType()); 2457 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 2458 2459 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 2460 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 2461 } 2462 2463 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 2464 VTs.push_back(VT); 2465 } 2466 if (HasChain) 2467 VTs.push_back(MVT::Other); 2468 2469 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 2470 2471 // Create the node. 2472 SDOperand Result; 2473 if (!HasChain) 2474 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 2475 &Ops[0], Ops.size()); 2476 else if (I.getType() != Type::VoidTy) 2477 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 2478 &Ops[0], Ops.size()); 2479 else 2480 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 2481 &Ops[0], Ops.size()); 2482 2483 if (HasChain) { 2484 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 2485 if (OnlyLoad) 2486 PendingLoads.push_back(Chain); 2487 else 2488 DAG.setRoot(Chain); 2489 } 2490 if (I.getType() != Type::VoidTy) { 2491 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2492 MVT::ValueType VT = TLI.getValueType(PTy); 2493 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); 2494 } 2495 setValue(&I, Result); 2496 } 2497} 2498 2499/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 2500static GlobalVariable *ExtractTypeInfo (Value *V) { 2501 V = IntrinsicInst::StripPointerCasts(V); 2502 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 2503 assert (GV || isa<ConstantPointerNull>(V) && 2504 "TypeInfo must be a global variable or NULL"); 2505 return GV; 2506} 2507 2508/// addCatchInfo - Extract the personality and type infos from an eh.selector 2509/// call, and add them to the specified machine basic block. 2510static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, 2511 MachineBasicBlock *MBB) { 2512 // Inform the MachineModuleInfo of the personality for this landing pad. 2513 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 2514 assert(CE->getOpcode() == Instruction::BitCast && 2515 isa<Function>(CE->getOperand(0)) && 2516 "Personality should be a function"); 2517 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 2518 2519 // Gather all the type infos for this landing pad and pass them along to 2520 // MachineModuleInfo. 2521 std::vector<GlobalVariable *> TyInfo; 2522 unsigned N = I.getNumOperands(); 2523 2524 for (unsigned i = N - 1; i > 2; --i) { 2525 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 2526 unsigned FilterLength = CI->getZExtValue(); 2527 unsigned FirstCatch = i + FilterLength + !FilterLength; 2528 assert (FirstCatch <= N && "Invalid filter length"); 2529 2530 if (FirstCatch < N) { 2531 TyInfo.reserve(N - FirstCatch); 2532 for (unsigned j = FirstCatch; j < N; ++j) 2533 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2534 MMI->addCatchTypeInfo(MBB, TyInfo); 2535 TyInfo.clear(); 2536 } 2537 2538 if (!FilterLength) { 2539 // Cleanup. 2540 MMI->addCleanup(MBB); 2541 } else { 2542 // Filter. 2543 TyInfo.reserve(FilterLength - 1); 2544 for (unsigned j = i + 1; j < FirstCatch; ++j) 2545 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2546 MMI->addFilterTypeInfo(MBB, TyInfo); 2547 TyInfo.clear(); 2548 } 2549 2550 N = i; 2551 } 2552 } 2553 2554 if (N > 3) { 2555 TyInfo.reserve(N - 3); 2556 for (unsigned j = 3; j < N; ++j) 2557 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 2558 MMI->addCatchTypeInfo(MBB, TyInfo); 2559 } 2560} 2561 2562/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 2563/// we want to emit this as a call to a named external function, return the name 2564/// otherwise lower it and return null. 2565const char * 2566SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 2567 switch (Intrinsic) { 2568 default: 2569 // By default, turn this into a target intrinsic node. 2570 visitTargetIntrinsic(I, Intrinsic); 2571 return 0; 2572 case Intrinsic::vastart: visitVAStart(I); return 0; 2573 case Intrinsic::vaend: visitVAEnd(I); return 0; 2574 case Intrinsic::vacopy: visitVACopy(I); return 0; 2575 case Intrinsic::returnaddress: 2576 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), 2577 getValue(I.getOperand(1)))); 2578 return 0; 2579 case Intrinsic::frameaddress: 2580 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), 2581 getValue(I.getOperand(1)))); 2582 return 0; 2583 case Intrinsic::setjmp: 2584 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 2585 break; 2586 case Intrinsic::longjmp: 2587 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 2588 break; 2589 case Intrinsic::memcpy_i32: 2590 case Intrinsic::memcpy_i64: 2591 visitMemIntrinsic(I, ISD::MEMCPY); 2592 return 0; 2593 case Intrinsic::memset_i32: 2594 case Intrinsic::memset_i64: 2595 visitMemIntrinsic(I, ISD::MEMSET); 2596 return 0; 2597 case Intrinsic::memmove_i32: 2598 case Intrinsic::memmove_i64: 2599 visitMemIntrinsic(I, ISD::MEMMOVE); 2600 return 0; 2601 2602 case Intrinsic::dbg_stoppoint: { 2603 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2604 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2605 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { 2606 SDOperand Ops[5]; 2607 2608 Ops[0] = getRoot(); 2609 Ops[1] = getValue(SPI.getLineValue()); 2610 Ops[2] = getValue(SPI.getColumnValue()); 2611 2612 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); 2613 assert(DD && "Not a debug information descriptor"); 2614 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2615 2616 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2617 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2618 2619 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2620 } 2621 2622 return 0; 2623 } 2624 case Intrinsic::dbg_region_start: { 2625 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2626 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2627 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { 2628 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); 2629 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2630 DAG.getConstant(LabelID, MVT::i32))); 2631 } 2632 2633 return 0; 2634 } 2635 case Intrinsic::dbg_region_end: { 2636 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2637 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2638 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { 2639 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); 2640 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2641 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2642 } 2643 2644 return 0; 2645 } 2646 case Intrinsic::dbg_func_start: { 2647 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2648 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2649 if (MMI && FSI.getSubprogram() && 2650 MMI->Verify(FSI.getSubprogram())) { 2651 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram()); 2652 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, 2653 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2654 } 2655 2656 return 0; 2657 } 2658 case Intrinsic::dbg_declare: { 2659 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2660 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2661 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) { 2662 SDOperand AddressOp = getValue(DI.getAddress()); 2663 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2664 MMI->RecordVariable(DI.getVariable(), FI->getIndex()); 2665 } 2666 2667 return 0; 2668 } 2669 2670 case Intrinsic::eh_exception: { 2671 if (ExceptionHandling) { 2672 if (!CurMBB->isLandingPad()) { 2673 // FIXME: Mark exception register as live in. Hack for PR1508. 2674 unsigned Reg = TLI.getExceptionAddressRegister(); 2675 if (Reg) CurMBB->addLiveIn(Reg); 2676 } 2677 // Insert the EXCEPTIONADDR instruction. 2678 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 2679 SDOperand Ops[1]; 2680 Ops[0] = DAG.getRoot(); 2681 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); 2682 setValue(&I, Op); 2683 DAG.setRoot(Op.getValue(1)); 2684 } else { 2685 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2686 } 2687 return 0; 2688 } 2689 2690 case Intrinsic::eh_selector_i32: 2691 case Intrinsic::eh_selector_i64: { 2692 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2693 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? 2694 MVT::i32 : MVT::i64); 2695 2696 if (ExceptionHandling && MMI) { 2697 if (CurMBB->isLandingPad()) 2698 addCatchInfo(I, MMI, CurMBB); 2699 else { 2700#ifndef NDEBUG 2701 FuncInfo.CatchInfoLost.insert(&I); 2702#endif 2703 // FIXME: Mark exception selector register as live in. Hack for PR1508. 2704 unsigned Reg = TLI.getExceptionSelectorRegister(); 2705 if (Reg) CurMBB->addLiveIn(Reg); 2706 } 2707 2708 // Insert the EHSELECTION instruction. 2709 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2710 SDOperand Ops[2]; 2711 Ops[0] = getValue(I.getOperand(1)); 2712 Ops[1] = getRoot(); 2713 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); 2714 setValue(&I, Op); 2715 DAG.setRoot(Op.getValue(1)); 2716 } else { 2717 setValue(&I, DAG.getConstant(0, VT)); 2718 } 2719 2720 return 0; 2721 } 2722 2723 case Intrinsic::eh_typeid_for_i32: 2724 case Intrinsic::eh_typeid_for_i64: { 2725 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2726 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? 2727 MVT::i32 : MVT::i64); 2728 2729 if (MMI) { 2730 // Find the type id for the given typeinfo. 2731 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 2732 2733 unsigned TypeID = MMI->getTypeIDFor(GV); 2734 setValue(&I, DAG.getConstant(TypeID, VT)); 2735 } else { 2736 // Return something different to eh_selector. 2737 setValue(&I, DAG.getConstant(1, VT)); 2738 } 2739 2740 return 0; 2741 } 2742 2743 case Intrinsic::eh_return: { 2744 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2745 2746 if (MMI && ExceptionHandling) { 2747 MMI->setCallsEHReturn(true); 2748 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, 2749 MVT::Other, 2750 getRoot(), 2751 getValue(I.getOperand(1)), 2752 getValue(I.getOperand(2)))); 2753 } else { 2754 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2755 } 2756 2757 return 0; 2758 } 2759 2760 case Intrinsic::eh_unwind_init: { 2761 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { 2762 MMI->setCallsUnwindInit(true); 2763 } 2764 2765 return 0; 2766 } 2767 2768 case Intrinsic::eh_dwarf_cfa: { 2769 if (ExceptionHandling) { 2770 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); 2771 SDOperand CfaArg; 2772 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) 2773 CfaArg = DAG.getNode(ISD::TRUNCATE, 2774 TLI.getPointerTy(), getValue(I.getOperand(1))); 2775 else 2776 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, 2777 TLI.getPointerTy(), getValue(I.getOperand(1))); 2778 2779 SDOperand Offset = DAG.getNode(ISD::ADD, 2780 TLI.getPointerTy(), 2781 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, 2782 TLI.getPointerTy()), 2783 CfaArg); 2784 setValue(&I, DAG.getNode(ISD::ADD, 2785 TLI.getPointerTy(), 2786 DAG.getNode(ISD::FRAMEADDR, 2787 TLI.getPointerTy(), 2788 DAG.getConstant(0, 2789 TLI.getPointerTy())), 2790 Offset)); 2791 } else { 2792 setValue(&I, DAG.getConstant(0, TLI.getPointerTy())); 2793 } 2794 2795 return 0; 2796 } 2797 2798 case Intrinsic::sqrt: 2799 setValue(&I, DAG.getNode(ISD::FSQRT, 2800 getValue(I.getOperand(1)).getValueType(), 2801 getValue(I.getOperand(1)))); 2802 return 0; 2803 case Intrinsic::powi: 2804 setValue(&I, DAG.getNode(ISD::FPOWI, 2805 getValue(I.getOperand(1)).getValueType(), 2806 getValue(I.getOperand(1)), 2807 getValue(I.getOperand(2)))); 2808 return 0; 2809 case Intrinsic::sin: 2810 setValue(&I, DAG.getNode(ISD::FSIN, 2811 getValue(I.getOperand(1)).getValueType(), 2812 getValue(I.getOperand(1)))); 2813 return 0; 2814 case Intrinsic::cos: 2815 setValue(&I, DAG.getNode(ISD::FCOS, 2816 getValue(I.getOperand(1)).getValueType(), 2817 getValue(I.getOperand(1)))); 2818 return 0; 2819 case Intrinsic::pow: 2820 setValue(&I, DAG.getNode(ISD::FPOW, 2821 getValue(I.getOperand(1)).getValueType(), 2822 getValue(I.getOperand(1)), 2823 getValue(I.getOperand(2)))); 2824 return 0; 2825 case Intrinsic::pcmarker: { 2826 SDOperand Tmp = getValue(I.getOperand(1)); 2827 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2828 return 0; 2829 } 2830 case Intrinsic::readcyclecounter: { 2831 SDOperand Op = getRoot(); 2832 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2833 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2834 &Op, 1); 2835 setValue(&I, Tmp); 2836 DAG.setRoot(Tmp.getValue(1)); 2837 return 0; 2838 } 2839 case Intrinsic::part_select: { 2840 // Currently not implemented: just abort 2841 assert(0 && "part_select intrinsic not implemented"); 2842 abort(); 2843 } 2844 case Intrinsic::part_set: { 2845 // Currently not implemented: just abort 2846 assert(0 && "part_set intrinsic not implemented"); 2847 abort(); 2848 } 2849 case Intrinsic::bswap: 2850 setValue(&I, DAG.getNode(ISD::BSWAP, 2851 getValue(I.getOperand(1)).getValueType(), 2852 getValue(I.getOperand(1)))); 2853 return 0; 2854 case Intrinsic::cttz: { 2855 SDOperand Arg = getValue(I.getOperand(1)); 2856 MVT::ValueType Ty = Arg.getValueType(); 2857 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); 2858 setValue(&I, result); 2859 return 0; 2860 } 2861 case Intrinsic::ctlz: { 2862 SDOperand Arg = getValue(I.getOperand(1)); 2863 MVT::ValueType Ty = Arg.getValueType(); 2864 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); 2865 setValue(&I, result); 2866 return 0; 2867 } 2868 case Intrinsic::ctpop: { 2869 SDOperand Arg = getValue(I.getOperand(1)); 2870 MVT::ValueType Ty = Arg.getValueType(); 2871 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); 2872 setValue(&I, result); 2873 return 0; 2874 } 2875 case Intrinsic::stacksave: { 2876 SDOperand Op = getRoot(); 2877 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2878 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2879 setValue(&I, Tmp); 2880 DAG.setRoot(Tmp.getValue(1)); 2881 return 0; 2882 } 2883 case Intrinsic::stackrestore: { 2884 SDOperand Tmp = getValue(I.getOperand(1)); 2885 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2886 return 0; 2887 } 2888 case Intrinsic::prefetch: 2889 // FIXME: Currently discarding prefetches. 2890 return 0; 2891 2892 case Intrinsic::var_annotation: 2893 // Discard annotate attributes 2894 return 0; 2895 2896 case Intrinsic::init_trampoline: { 2897 const Function *F = 2898 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2))); 2899 2900 SDOperand Ops[6]; 2901 Ops[0] = getRoot(); 2902 Ops[1] = getValue(I.getOperand(1)); 2903 Ops[2] = getValue(I.getOperand(2)); 2904 Ops[3] = getValue(I.getOperand(3)); 2905 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 2906 Ops[5] = DAG.getSrcValue(F); 2907 2908 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE, 2909 DAG.getNodeValueTypes(TLI.getPointerTy(), 2910 MVT::Other), 2, 2911 Ops, 6); 2912 2913 setValue(&I, Tmp); 2914 DAG.setRoot(Tmp.getValue(1)); 2915 return 0; 2916 } 2917 case Intrinsic::flt_rounds: { 2918 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32)); 2919 return 0; 2920 } 2921 } 2922} 2923 2924 2925void SelectionDAGLowering::LowerCallTo(Instruction &I, 2926 const Type *CalledValueTy, 2927 const ParamAttrsList *Attrs, 2928 unsigned CallingConv, 2929 bool IsTailCall, 2930 SDOperand Callee, unsigned OpIdx, 2931 MachineBasicBlock *LandingPad) { 2932 const PointerType *PT = cast<PointerType>(CalledValueTy); 2933 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2934 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 2935 unsigned BeginLabel = 0, EndLabel = 0; 2936 2937 TargetLowering::ArgListTy Args; 2938 TargetLowering::ArgListEntry Entry; 2939 Args.reserve(I.getNumOperands()); 2940 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) { 2941 Value *Arg = I.getOperand(i); 2942 SDOperand ArgNode = getValue(Arg); 2943 Entry.Node = ArgNode; Entry.Ty = Arg->getType(); 2944 2945 unsigned attrInd = i - OpIdx + 1; 2946 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); 2947 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); 2948 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); 2949 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); 2950 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest); 2951 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal); 2952 Args.push_back(Entry); 2953 } 2954 2955 if (ExceptionHandling && MMI && LandingPad) { 2956 // Insert a label before the invoke call to mark the try range. This can be 2957 // used to detect deletion of the invoke via the MachineModuleInfo. 2958 BeginLabel = MMI->NextLabelID(); 2959 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2960 DAG.getConstant(BeginLabel, MVT::i32))); 2961 } 2962 2963 std::pair<SDOperand,SDOperand> Result = 2964 TLI.LowerCallTo(getRoot(), I.getType(), 2965 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt), 2966 FTy->isVarArg(), CallingConv, IsTailCall, 2967 Callee, Args, DAG); 2968 if (I.getType() != Type::VoidTy) 2969 setValue(&I, Result.first); 2970 DAG.setRoot(Result.second); 2971 2972 if (ExceptionHandling && MMI && LandingPad) { 2973 // Insert a label at the end of the invoke call to mark the try range. This 2974 // can be used to detect deletion of the invoke via the MachineModuleInfo. 2975 EndLabel = MMI->NextLabelID(); 2976 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), 2977 DAG.getConstant(EndLabel, MVT::i32))); 2978 2979 // Inform MachineModuleInfo of range. 2980 MMI->addInvoke(LandingPad, BeginLabel, EndLabel); 2981 } 2982} 2983 2984 2985void SelectionDAGLowering::visitCall(CallInst &I) { 2986 const char *RenameFn = 0; 2987 if (Function *F = I.getCalledFunction()) { 2988 if (F->isDeclaration()) { 2989 if (unsigned IID = F->getIntrinsicID()) { 2990 RenameFn = visitIntrinsicCall(I, IID); 2991 if (!RenameFn) 2992 return; 2993 } 2994 } 2995 2996 // Check for well-known libc/libm calls. If the function is internal, it 2997 // can't be a library call. 2998 unsigned NameLen = F->getNameLen(); 2999 if (!F->hasInternalLinkage() && NameLen) { 3000 const char *NameStr = F->getNameStart(); 3001 if (NameStr[0] == 'c' && 3002 ((NameLen == 8 && !strcmp(NameStr, "copysign")) || 3003 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) { 3004 if (I.getNumOperands() == 3 && // Basic sanity checks. 3005 I.getOperand(1)->getType()->isFloatingPoint() && 3006 I.getType() == I.getOperand(1)->getType() && 3007 I.getType() == I.getOperand(2)->getType()) { 3008 SDOperand LHS = getValue(I.getOperand(1)); 3009 SDOperand RHS = getValue(I.getOperand(2)); 3010 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 3011 LHS, RHS)); 3012 return; 3013 } 3014 } else if (NameStr[0] == 'f' && 3015 ((NameLen == 4 && !strcmp(NameStr, "fabs")) || 3016 (NameLen == 5 && !strcmp(NameStr, "fabsf")) || 3017 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) { 3018 if (I.getNumOperands() == 2 && // Basic sanity checks. 3019 I.getOperand(1)->getType()->isFloatingPoint() && 3020 I.getType() == I.getOperand(1)->getType()) { 3021 SDOperand Tmp = getValue(I.getOperand(1)); 3022 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 3023 return; 3024 } 3025 } else if (NameStr[0] == 's' && 3026 ((NameLen == 3 && !strcmp(NameStr, "sin")) || 3027 (NameLen == 4 && !strcmp(NameStr, "sinf")) || 3028 (NameLen == 4 && !strcmp(NameStr, "sinl")))) { 3029 if (I.getNumOperands() == 2 && // Basic sanity checks. 3030 I.getOperand(1)->getType()->isFloatingPoint() && 3031 I.getType() == I.getOperand(1)->getType()) { 3032 SDOperand Tmp = getValue(I.getOperand(1)); 3033 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 3034 return; 3035 } 3036 } else if (NameStr[0] == 'c' && 3037 ((NameLen == 3 && !strcmp(NameStr, "cos")) || 3038 (NameLen == 4 && !strcmp(NameStr, "cosf")) || 3039 (NameLen == 4 && !strcmp(NameStr, "cosl")))) { 3040 if (I.getNumOperands() == 2 && // Basic sanity checks. 3041 I.getOperand(1)->getType()->isFloatingPoint() && 3042 I.getType() == I.getOperand(1)->getType()) { 3043 SDOperand Tmp = getValue(I.getOperand(1)); 3044 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 3045 return; 3046 } 3047 } 3048 } 3049 } else if (isa<InlineAsm>(I.getOperand(0))) { 3050 visitInlineAsm(&I); 3051 return; 3052 } 3053 3054 SDOperand Callee; 3055 if (!RenameFn) 3056 Callee = getValue(I.getOperand(0)); 3057 else 3058 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 3059 3060 LowerCallTo(I, I.getCalledValue()->getType(), I.getParamAttrs(), 3061 I.getCallingConv(), 3062 I.isTailCall(), 3063 Callee, 3064 1); 3065} 3066 3067 3068/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 3069/// this value and returns the result as a ValueVT value. This uses 3070/// Chain/Flag as the input and updates them for the output Chain/Flag. 3071/// If the Flag pointer is NULL, no flag is used. 3072SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 3073 SDOperand &Chain, SDOperand *Flag)const{ 3074 // Copy the legal parts from the registers. 3075 unsigned NumParts = Regs.size(); 3076 SmallVector<SDOperand, 8> Parts(NumParts); 3077 for (unsigned i = 0; i != NumParts; ++i) { 3078 SDOperand Part = Flag ? 3079 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : 3080 DAG.getCopyFromReg(Chain, Regs[i], RegVT); 3081 Chain = Part.getValue(1); 3082 if (Flag) 3083 *Flag = Part.getValue(2); 3084 Parts[i] = Part; 3085 } 3086 3087 // Assemble the legal parts into the final value. 3088 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); 3089} 3090 3091/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 3092/// specified value into the registers specified by this object. This uses 3093/// Chain/Flag as the input and updates them for the output Chain/Flag. 3094/// If the Flag pointer is NULL, no flag is used. 3095void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 3096 SDOperand &Chain, SDOperand *Flag) const { 3097 // Get the list of the values's legal parts. 3098 unsigned NumParts = Regs.size(); 3099 SmallVector<SDOperand, 8> Parts(NumParts); 3100 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); 3101 3102 // Copy the parts into the registers. 3103 for (unsigned i = 0; i != NumParts; ++i) { 3104 SDOperand Part = Flag ? 3105 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : 3106 DAG.getCopyToReg(Chain, Regs[i], Parts[i]); 3107 Chain = Part.getValue(0); 3108 if (Flag) 3109 *Flag = Part.getValue(1); 3110 } 3111} 3112 3113/// AddInlineAsmOperands - Add this value to the specified inlineasm node 3114/// operand list. This adds the code marker and includes the number of 3115/// values added into it. 3116void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 3117 std::vector<SDOperand> &Ops) const { 3118 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 3119 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); 3120 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 3121 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 3122} 3123 3124/// isAllocatableRegister - If the specified register is safe to allocate, 3125/// i.e. it isn't a stack pointer or some other special register, return the 3126/// register class for the register. Otherwise, return null. 3127static const TargetRegisterClass * 3128isAllocatableRegister(unsigned Reg, MachineFunction &MF, 3129 const TargetLowering &TLI, const MRegisterInfo *MRI) { 3130 MVT::ValueType FoundVT = MVT::Other; 3131 const TargetRegisterClass *FoundRC = 0; 3132 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 3133 E = MRI->regclass_end(); RCI != E; ++RCI) { 3134 MVT::ValueType ThisVT = MVT::Other; 3135 3136 const TargetRegisterClass *RC = *RCI; 3137 // If none of the the value types for this register class are valid, we 3138 // can't use it. For example, 64-bit reg classes on 32-bit targets. 3139 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 3140 I != E; ++I) { 3141 if (TLI.isTypeLegal(*I)) { 3142 // If we have already found this register in a different register class, 3143 // choose the one with the largest VT specified. For example, on 3144 // PowerPC, we favor f64 register classes over f32. 3145 if (FoundVT == MVT::Other || 3146 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 3147 ThisVT = *I; 3148 break; 3149 } 3150 } 3151 } 3152 3153 if (ThisVT == MVT::Other) continue; 3154 3155 // NOTE: This isn't ideal. In particular, this might allocate the 3156 // frame pointer in functions that need it (due to them not being taken 3157 // out of allocation, because a variable sized allocation hasn't been seen 3158 // yet). This is a slight code pessimization, but should still work. 3159 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 3160 E = RC->allocation_order_end(MF); I != E; ++I) 3161 if (*I == Reg) { 3162 // We found a matching register class. Keep looking at others in case 3163 // we find one with larger registers that this physreg is also in. 3164 FoundRC = RC; 3165 FoundVT = ThisVT; 3166 break; 3167 } 3168 } 3169 return FoundRC; 3170} 3171 3172 3173namespace { 3174/// AsmOperandInfo - This contains information for each constraint that we are 3175/// lowering. 3176struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 3177 /// ConstraintCode - This contains the actual string for the code, like "m". 3178 std::string ConstraintCode; 3179 3180 /// ConstraintType - Information about the constraint code, e.g. Register, 3181 /// RegisterClass, Memory, Other, Unknown. 3182 TargetLowering::ConstraintType ConstraintType; 3183 3184 /// CallOperand/CallOperandval - If this is the result output operand or a 3185 /// clobber, this is null, otherwise it is the incoming operand to the 3186 /// CallInst. This gets modified as the asm is processed. 3187 SDOperand CallOperand; 3188 Value *CallOperandVal; 3189 3190 /// ConstraintVT - The ValueType for the operand value. 3191 MVT::ValueType ConstraintVT; 3192 3193 /// AssignedRegs - If this is a register or register class operand, this 3194 /// contains the set of register corresponding to the operand. 3195 RegsForValue AssignedRegs; 3196 3197 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 3198 : InlineAsm::ConstraintInfo(info), 3199 ConstraintType(TargetLowering::C_Unknown), 3200 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) { 3201 } 3202 3203 void ComputeConstraintToUse(const TargetLowering &TLI); 3204 3205 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 3206 /// busy in OutputRegs/InputRegs. 3207 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 3208 std::set<unsigned> &OutputRegs, 3209 std::set<unsigned> &InputRegs) const { 3210 if (isOutReg) 3211 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3212 if (isInReg) 3213 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end()); 3214 } 3215}; 3216} // end anon namespace. 3217 3218/// getConstraintGenerality - Return an integer indicating how general CT is. 3219static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3220 switch (CT) { 3221 default: assert(0 && "Unknown constraint type!"); 3222 case TargetLowering::C_Other: 3223 case TargetLowering::C_Unknown: 3224 return 0; 3225 case TargetLowering::C_Register: 3226 return 1; 3227 case TargetLowering::C_RegisterClass: 3228 return 2; 3229 case TargetLowering::C_Memory: 3230 return 3; 3231 } 3232} 3233 3234void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) { 3235 assert(!Codes.empty() && "Must have at least one constraint"); 3236 3237 std::string *Current = &Codes[0]; 3238 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current); 3239 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common. 3240 ConstraintCode = *Current; 3241 ConstraintType = CurType; 3242 return; 3243 } 3244 3245 unsigned CurGenerality = getConstraintGenerality(CurType); 3246 3247 // If we have multiple constraints, try to pick the most general one ahead 3248 // of time. This isn't a wonderful solution, but handles common cases. 3249 for (unsigned j = 1, e = Codes.size(); j != e; ++j) { 3250 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]); 3251 unsigned ThisGenerality = getConstraintGenerality(ThisType); 3252 if (ThisGenerality > CurGenerality) { 3253 // This constraint letter is more general than the previous one, 3254 // use it. 3255 CurType = ThisType; 3256 Current = &Codes[j]; 3257 CurGenerality = ThisGenerality; 3258 } 3259 } 3260 3261 ConstraintCode = *Current; 3262 ConstraintType = CurType; 3263} 3264 3265 3266void SelectionDAGLowering:: 3267GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, 3268 std::set<unsigned> &OutputRegs, 3269 std::set<unsigned> &InputRegs) { 3270 // Compute whether this value requires an input register, an output register, 3271 // or both. 3272 bool isOutReg = false; 3273 bool isInReg = false; 3274 switch (OpInfo.Type) { 3275 case InlineAsm::isOutput: 3276 isOutReg = true; 3277 3278 // If this is an early-clobber output, or if there is an input 3279 // constraint that matches this, we need to reserve the input register 3280 // so no other inputs allocate to it. 3281 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput; 3282 break; 3283 case InlineAsm::isInput: 3284 isInReg = true; 3285 isOutReg = false; 3286 break; 3287 case InlineAsm::isClobber: 3288 isOutReg = true; 3289 isInReg = true; 3290 break; 3291 } 3292 3293 3294 MachineFunction &MF = DAG.getMachineFunction(); 3295 std::vector<unsigned> Regs; 3296 3297 // If this is a constraint for a single physreg, or a constraint for a 3298 // register class, find it. 3299 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 3300 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3301 OpInfo.ConstraintVT); 3302 3303 unsigned NumRegs = 1; 3304 if (OpInfo.ConstraintVT != MVT::Other) 3305 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); 3306 MVT::ValueType RegVT; 3307 MVT::ValueType ValueVT = OpInfo.ConstraintVT; 3308 3309 3310 // If this is a constraint for a specific physical register, like {r17}, 3311 // assign it now. 3312 if (PhysReg.first) { 3313 if (OpInfo.ConstraintVT == MVT::Other) 3314 ValueVT = *PhysReg.second->vt_begin(); 3315 3316 // Get the actual register value type. This is important, because the user 3317 // may have asked for (e.g.) the AX register in i32 type. We need to 3318 // remember that AX is actually i16 to get the right extension. 3319 RegVT = *PhysReg.second->vt_begin(); 3320 3321 // This is a explicit reference to a physical register. 3322 Regs.push_back(PhysReg.first); 3323 3324 // If this is an expanded reference, add the rest of the regs to Regs. 3325 if (NumRegs != 1) { 3326 TargetRegisterClass::iterator I = PhysReg.second->begin(); 3327 TargetRegisterClass::iterator E = PhysReg.second->end(); 3328 for (; *I != PhysReg.first; ++I) 3329 assert(I != E && "Didn't find reg!"); 3330 3331 // Already added the first reg. 3332 --NumRegs; ++I; 3333 for (; NumRegs; --NumRegs, ++I) { 3334 assert(I != E && "Ran out of registers to allocate!"); 3335 Regs.push_back(*I); 3336 } 3337 } 3338 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3339 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3340 return; 3341 } 3342 3343 // Otherwise, if this was a reference to an LLVM register class, create vregs 3344 // for this reference. 3345 std::vector<unsigned> RegClassRegs; 3346 const TargetRegisterClass *RC = PhysReg.second; 3347 if (RC) { 3348 // If this is an early clobber or tied register, our regalloc doesn't know 3349 // how to maintain the constraint. If it isn't, go ahead and create vreg 3350 // and let the regalloc do the right thing. 3351 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber && 3352 // If there is some other early clobber and this is an input register, 3353 // then we are forced to pre-allocate the input reg so it doesn't 3354 // conflict with the earlyclobber. 3355 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) { 3356 RegVT = *PhysReg.second->vt_begin(); 3357 3358 if (OpInfo.ConstraintVT == MVT::Other) 3359 ValueVT = RegVT; 3360 3361 // Create the appropriate number of virtual registers. 3362 SSARegMap *RegMap = MF.getSSARegMap(); 3363 for (; NumRegs; --NumRegs) 3364 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 3365 3366 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 3367 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3368 return; 3369 } 3370 3371 // Otherwise, we can't allocate it. Let the code below figure out how to 3372 // maintain these constraints. 3373 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 3374 3375 } else { 3376 // This is a reference to a register class that doesn't directly correspond 3377 // to an LLVM register class. Allocate NumRegs consecutive, available, 3378 // registers from the class. 3379 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3380 OpInfo.ConstraintVT); 3381 } 3382 3383 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 3384 unsigned NumAllocated = 0; 3385 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 3386 unsigned Reg = RegClassRegs[i]; 3387 // See if this register is available. 3388 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 3389 (isInReg && InputRegs.count(Reg))) { // Already used. 3390 // Make sure we find consecutive registers. 3391 NumAllocated = 0; 3392 continue; 3393 } 3394 3395 // Check to see if this register is allocatable (i.e. don't give out the 3396 // stack pointer). 3397 if (RC == 0) { 3398 RC = isAllocatableRegister(Reg, MF, TLI, MRI); 3399 if (!RC) { // Couldn't allocate this register. 3400 // Reset NumAllocated to make sure we return consecutive registers. 3401 NumAllocated = 0; 3402 continue; 3403 } 3404 } 3405 3406 // Okay, this register is good, we can use it. 3407 ++NumAllocated; 3408 3409 // If we allocated enough consecutive registers, succeed. 3410 if (NumAllocated == NumRegs) { 3411 unsigned RegStart = (i-NumAllocated)+1; 3412 unsigned RegEnd = i+1; 3413 // Mark all of the allocated registers used. 3414 for (unsigned i = RegStart; i != RegEnd; ++i) 3415 Regs.push_back(RegClassRegs[i]); 3416 3417 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 3418 OpInfo.ConstraintVT); 3419 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); 3420 return; 3421 } 3422 } 3423 3424 // Otherwise, we couldn't allocate enough registers for this. 3425 return; 3426} 3427 3428 3429/// visitInlineAsm - Handle a call to an InlineAsm object. 3430/// 3431void SelectionDAGLowering::visitInlineAsm(CallSite CS) { 3432 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3433 3434 /// ConstraintOperands - Information about all of the constraints. 3435 std::vector<AsmOperandInfo> ConstraintOperands; 3436 3437 SDOperand Chain = getRoot(); 3438 SDOperand Flag; 3439 3440 std::set<unsigned> OutputRegs, InputRegs; 3441 3442 // Do a prepass over the constraints, canonicalizing them, and building up the 3443 // ConstraintOperands list. 3444 std::vector<InlineAsm::ConstraintInfo> 3445 ConstraintInfos = IA->ParseConstraints(); 3446 3447 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output 3448 // constraint. If so, we can't let the register allocator allocate any input 3449 // registers, because it will not know to avoid the earlyclobbered output reg. 3450 bool SawEarlyClobber = false; 3451 3452 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3453 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3454 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3455 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3456 3457 MVT::ValueType OpVT = MVT::Other; 3458 3459 // Compute the value type for each operand. 3460 switch (OpInfo.Type) { 3461 case InlineAsm::isOutput: 3462 if (!OpInfo.isIndirect) { 3463 // The return value of the call is this value. As such, there is no 3464 // corresponding argument. 3465 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3466 OpVT = TLI.getValueType(CS.getType()); 3467 } else { 3468 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3469 } 3470 break; 3471 case InlineAsm::isInput: 3472 OpInfo.CallOperandVal = CS.getArgument(ArgNo++); 3473 break; 3474 case InlineAsm::isClobber: 3475 // Nothing to do. 3476 break; 3477 } 3478 3479 // If this is an input or an indirect output, process the call argument. 3480 // BasicBlocks are labels, currently appearing only in asm's. 3481 if (OpInfo.CallOperandVal) { 3482 if (isa<BasicBlock>(OpInfo.CallOperandVal)) 3483 OpInfo.CallOperand = 3484 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]); 3485 else { 3486 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 3487 const Type *OpTy = OpInfo.CallOperandVal->getType(); 3488 // If this is an indirect operand, the operand is a pointer to the 3489 // accessed type. 3490 if (OpInfo.isIndirect) 3491 OpTy = cast<PointerType>(OpTy)->getElementType(); 3492 3493 // If OpTy is not a first-class value, it may be a struct/union that we 3494 // can tile with integers. 3495 if (!OpTy->isFirstClassType() && OpTy->isSized()) { 3496 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3497 switch (BitSize) { 3498 default: break; 3499 case 1: 3500 case 8: 3501 case 16: 3502 case 32: 3503 case 64: 3504 OpTy = IntegerType::get(BitSize); 3505 break; 3506 } 3507 } 3508 3509 OpVT = TLI.getValueType(OpTy, true); 3510 } 3511 } 3512 3513 OpInfo.ConstraintVT = OpVT; 3514 3515 // Compute the constraint code and ConstraintType to use. 3516 OpInfo.ComputeConstraintToUse(TLI); 3517 3518 // Keep track of whether we see an earlyclobber. 3519 SawEarlyClobber |= OpInfo.isEarlyClobber; 3520 3521 // If this is a memory input, and if the operand is not indirect, do what we 3522 // need to to provide an address for the memory input. 3523 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 3524 !OpInfo.isIndirect) { 3525 assert(OpInfo.Type == InlineAsm::isInput && 3526 "Can only indirectify direct input operands!"); 3527 3528 // Memory operands really want the address of the value. If we don't have 3529 // an indirect input, put it in the constpool if we can, otherwise spill 3530 // it to a stack slot. 3531 3532 // If the operand is a float, integer, or vector constant, spill to a 3533 // constant pool entry to get its address. 3534 Value *OpVal = OpInfo.CallOperandVal; 3535 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 3536 isa<ConstantVector>(OpVal)) { 3537 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 3538 TLI.getPointerTy()); 3539 } else { 3540 // Otherwise, create a stack slot and emit a store to it before the 3541 // asm. 3542 const Type *Ty = OpVal->getType(); 3543 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3544 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3545 MachineFunction &MF = DAG.getMachineFunction(); 3546 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3547 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3548 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); 3549 OpInfo.CallOperand = StackSlot; 3550 } 3551 3552 // There is no longer a Value* corresponding to this operand. 3553 OpInfo.CallOperandVal = 0; 3554 // It is now an indirect operand. 3555 OpInfo.isIndirect = true; 3556 } 3557 3558 // If this constraint is for a specific register, allocate it before 3559 // anything else. 3560 if (OpInfo.ConstraintType == TargetLowering::C_Register) 3561 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3562 } 3563 ConstraintInfos.clear(); 3564 3565 3566 // Second pass - Loop over all of the operands, assigning virtual or physregs 3567 // to registerclass operands. 3568 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3569 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3570 3571 // C_Register operands have already been allocated, Other/Memory don't need 3572 // to be. 3573 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 3574 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); 3575 } 3576 3577 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 3578 std::vector<SDOperand> AsmNodeOperands; 3579 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 3580 AsmNodeOperands.push_back( 3581 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); 3582 3583 3584 // Loop over all of the inputs, copying the operand values into the 3585 // appropriate registers and processing the output regs. 3586 RegsForValue RetValRegs; 3587 3588 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 3589 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 3590 3591 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 3592 AsmOperandInfo &OpInfo = ConstraintOperands[i]; 3593 3594 switch (OpInfo.Type) { 3595 case InlineAsm::isOutput: { 3596 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 3597 OpInfo.ConstraintType != TargetLowering::C_Register) { 3598 // Memory output, or 'other' output (e.g. 'X' constraint). 3599 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 3600 3601 // Add information to the INLINEASM node to know about this output. 3602 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3603 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3604 TLI.getPointerTy())); 3605 AsmNodeOperands.push_back(OpInfo.CallOperand); 3606 break; 3607 } 3608 3609 // Otherwise, this is a register or register class output. 3610 3611 // Copy the output from the appropriate register. Find a register that 3612 // we can use. 3613 if (OpInfo.AssignedRegs.Regs.empty()) { 3614 cerr << "Couldn't allocate output reg for contraint '" 3615 << OpInfo.ConstraintCode << "'!\n"; 3616 exit(1); 3617 } 3618 3619 if (!OpInfo.isIndirect) { 3620 // This is the result value of the call. 3621 assert(RetValRegs.Regs.empty() && 3622 "Cannot have multiple output constraints yet!"); 3623 assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); 3624 RetValRegs = OpInfo.AssignedRegs; 3625 } else { 3626 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 3627 OpInfo.CallOperandVal)); 3628 } 3629 3630 // Add information to the INLINEASM node to know that this register is 3631 // set. 3632 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, 3633 AsmNodeOperands); 3634 break; 3635 } 3636 case InlineAsm::isInput: { 3637 SDOperand InOperandVal = OpInfo.CallOperand; 3638 3639 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint? 3640 // If this is required to match an output register we have already set, 3641 // just use its register. 3642 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str()); 3643 3644 // Scan until we find the definition we already emitted of this operand. 3645 // When we find it, create a RegsForValue operand. 3646 unsigned CurOp = 2; // The first operand. 3647 for (; OperandNo; --OperandNo) { 3648 // Advance to the next operand. 3649 unsigned NumOps = 3650 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3651 assert(((NumOps & 7) == 2 /*REGDEF*/ || 3652 (NumOps & 7) == 4 /*MEM*/) && 3653 "Skipped past definitions?"); 3654 CurOp += (NumOps>>3)+1; 3655 } 3656 3657 unsigned NumOps = 3658 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 3659 if ((NumOps & 7) == 2 /*REGDEF*/) { 3660 // Add NumOps>>3 registers to MatchedRegs. 3661 RegsForValue MatchedRegs; 3662 MatchedRegs.ValueVT = InOperandVal.getValueType(); 3663 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 3664 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 3665 unsigned Reg = 3666 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 3667 MatchedRegs.Regs.push_back(Reg); 3668 } 3669 3670 // Use the produced MatchedRegs object to 3671 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3672 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 3673 break; 3674 } else { 3675 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!"); 3676 assert(0 && "matching constraints for memory operands unimp"); 3677 } 3678 } 3679 3680 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 3681 assert(!OpInfo.isIndirect && 3682 "Don't know how to handle indirect other inputs yet!"); 3683 3684 std::vector<SDOperand> Ops; 3685 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 3686 Ops, DAG); 3687 if (Ops.empty()) { 3688 cerr << "Invalid operand for inline asm constraint '" 3689 << OpInfo.ConstraintCode << "'!\n"; 3690 exit(1); 3691 } 3692 3693 // Add information to the INLINEASM node to know about this input. 3694 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); 3695 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3696 TLI.getPointerTy())); 3697 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 3698 break; 3699 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 3700 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 3701 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 3702 "Memory operands expect pointer values"); 3703 3704 // Add information to the INLINEASM node to know about this input. 3705 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 3706 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 3707 TLI.getPointerTy())); 3708 AsmNodeOperands.push_back(InOperandVal); 3709 break; 3710 } 3711 3712 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 3713 OpInfo.ConstraintType == TargetLowering::C_Register) && 3714 "Unknown constraint type!"); 3715 assert(!OpInfo.isIndirect && 3716 "Don't know how to handle indirect register inputs yet!"); 3717 3718 // Copy the input into the appropriate registers. 3719 assert(!OpInfo.AssignedRegs.Regs.empty() && 3720 "Couldn't allocate input reg!"); 3721 3722 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); 3723 3724 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, 3725 AsmNodeOperands); 3726 break; 3727 } 3728 case InlineAsm::isClobber: { 3729 // Add the clobbered value to the operand list, so that the register 3730 // allocator is aware that the physreg got clobbered. 3731 if (!OpInfo.AssignedRegs.Regs.empty()) 3732 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, 3733 AsmNodeOperands); 3734 break; 3735 } 3736 } 3737 } 3738 3739 // Finish up input operands. 3740 AsmNodeOperands[0] = Chain; 3741 if (Flag.Val) AsmNodeOperands.push_back(Flag); 3742 3743 Chain = DAG.getNode(ISD::INLINEASM, 3744 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 3745 &AsmNodeOperands[0], AsmNodeOperands.size()); 3746 Flag = Chain.getValue(1); 3747 3748 // If this asm returns a register value, copy the result from that register 3749 // and set it as the value of the call. 3750 if (!RetValRegs.Regs.empty()) { 3751 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); 3752 3753 // If the result of the inline asm is a vector, it may have the wrong 3754 // width/num elts. Make sure to convert it to the right type with 3755 // bit_convert. 3756 if (MVT::isVector(Val.getValueType())) { 3757 const VectorType *VTy = cast<VectorType>(CS.getType()); 3758 MVT::ValueType DesiredVT = TLI.getValueType(VTy); 3759 3760 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val); 3761 } 3762 3763 setValue(CS.getInstruction(), Val); 3764 } 3765 3766 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 3767 3768 // Process indirect outputs, first output all of the flagged copies out of 3769 // physregs. 3770 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 3771 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 3772 Value *Ptr = IndirectStoresToEmit[i].second; 3773 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); 3774 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 3775 } 3776 3777 // Emit the non-flagged stores from the physregs. 3778 SmallVector<SDOperand, 8> OutChains; 3779 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 3780 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 3781 getValue(StoresToEmit[i].second), 3782 StoresToEmit[i].second, 0)); 3783 if (!OutChains.empty()) 3784 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3785 &OutChains[0], OutChains.size()); 3786 DAG.setRoot(Chain); 3787} 3788 3789 3790void SelectionDAGLowering::visitMalloc(MallocInst &I) { 3791 SDOperand Src = getValue(I.getOperand(0)); 3792 3793 MVT::ValueType IntPtr = TLI.getPointerTy(); 3794 3795 if (IntPtr < Src.getValueType()) 3796 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 3797 else if (IntPtr > Src.getValueType()) 3798 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 3799 3800 // Scale the source by the type size. 3801 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); 3802 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 3803 Src, getIntPtrConstant(ElementSize)); 3804 3805 TargetLowering::ArgListTy Args; 3806 TargetLowering::ArgListEntry Entry; 3807 Entry.Node = Src; 3808 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3809 Args.push_back(Entry); 3810 3811 std::pair<SDOperand,SDOperand> Result = 3812 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true, 3813 DAG.getExternalSymbol("malloc", IntPtr), 3814 Args, DAG); 3815 setValue(&I, Result.first); // Pointers always fit in registers 3816 DAG.setRoot(Result.second); 3817} 3818 3819void SelectionDAGLowering::visitFree(FreeInst &I) { 3820 TargetLowering::ArgListTy Args; 3821 TargetLowering::ArgListEntry Entry; 3822 Entry.Node = getValue(I.getOperand(0)); 3823 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3824 Args.push_back(Entry); 3825 MVT::ValueType IntPtr = TLI.getPointerTy(); 3826 std::pair<SDOperand,SDOperand> Result = 3827 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true, 3828 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 3829 DAG.setRoot(Result.second); 3830} 3831 3832// InsertAtEndOfBasicBlock - This method should be implemented by targets that 3833// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 3834// instructions are special in various ways, which require special support to 3835// insert. The specified MachineInstr is created but not inserted into any 3836// basic blocks, and the scheduler passes ownership of it to this method. 3837MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 3838 MachineBasicBlock *MBB) { 3839 cerr << "If a target marks an instruction with " 3840 << "'usesCustomDAGSchedInserter', it must implement " 3841 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 3842 abort(); 3843 return 0; 3844} 3845 3846void SelectionDAGLowering::visitVAStart(CallInst &I) { 3847 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 3848 getValue(I.getOperand(1)), 3849 DAG.getSrcValue(I.getOperand(1)))); 3850} 3851 3852void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 3853 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 3854 getValue(I.getOperand(0)), 3855 DAG.getSrcValue(I.getOperand(0))); 3856 setValue(&I, V); 3857 DAG.setRoot(V.getValue(1)); 3858} 3859 3860void SelectionDAGLowering::visitVAEnd(CallInst &I) { 3861 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 3862 getValue(I.getOperand(1)), 3863 DAG.getSrcValue(I.getOperand(1)))); 3864} 3865 3866void SelectionDAGLowering::visitVACopy(CallInst &I) { 3867 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 3868 getValue(I.getOperand(1)), 3869 getValue(I.getOperand(2)), 3870 DAG.getSrcValue(I.getOperand(1)), 3871 DAG.getSrcValue(I.getOperand(2)))); 3872} 3873 3874/// TargetLowering::LowerArguments - This is the default LowerArguments 3875/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 3876/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 3877/// integrated into SDISel. 3878std::vector<SDOperand> 3879TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 3880 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 3881 std::vector<SDOperand> Ops; 3882 Ops.push_back(DAG.getRoot()); 3883 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 3884 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 3885 3886 // Add one result value for each formal argument. 3887 std::vector<MVT::ValueType> RetVals; 3888 unsigned j = 1; 3889 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); 3890 I != E; ++I, ++j) { 3891 MVT::ValueType VT = getValueType(I->getType()); 3892 unsigned Flags = ISD::ParamFlags::NoFlagSet; 3893 unsigned OriginalAlignment = 3894 getTargetData()->getABITypeAlignment(I->getType()); 3895 3896 // FIXME: Distinguish between a formal with no [sz]ext attribute from one 3897 // that is zero extended! 3898 if (F.paramHasAttr(j, ParamAttr::ZExt)) 3899 Flags &= ~(ISD::ParamFlags::SExt); 3900 if (F.paramHasAttr(j, ParamAttr::SExt)) 3901 Flags |= ISD::ParamFlags::SExt; 3902 if (F.paramHasAttr(j, ParamAttr::InReg)) 3903 Flags |= ISD::ParamFlags::InReg; 3904 if (F.paramHasAttr(j, ParamAttr::StructRet)) 3905 Flags |= ISD::ParamFlags::StructReturn; 3906 if (F.paramHasAttr(j, ParamAttr::ByVal)) { 3907 Flags |= ISD::ParamFlags::ByVal; 3908 const PointerType *Ty = cast<PointerType>(I->getType()); 3909 const StructType *STy = cast<StructType>(Ty->getElementType()); 3910 unsigned StructAlign = 3911 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 3912 unsigned StructSize = getTargetData()->getABITypeSize(STy); 3913 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 3914 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 3915 } 3916 if (F.paramHasAttr(j, ParamAttr::Nest)) 3917 Flags |= ISD::ParamFlags::Nest; 3918 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs); 3919 3920 switch (getTypeAction(VT)) { 3921 default: assert(0 && "Unknown type action!"); 3922 case Legal: 3923 RetVals.push_back(VT); 3924 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3925 break; 3926 case Promote: 3927 RetVals.push_back(getTypeToTransformTo(VT)); 3928 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3929 break; 3930 case Expand: { 3931 // If this is an illegal type, it needs to be broken up to fit into 3932 // registers. 3933 MVT::ValueType RegisterVT = getRegisterType(VT); 3934 unsigned NumRegs = getNumRegisters(VT); 3935 for (unsigned i = 0; i != NumRegs; ++i) { 3936 RetVals.push_back(RegisterVT); 3937 // if it isn't first piece, alignment must be 1 3938 if (i > 0) 3939 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | 3940 (1 << ISD::ParamFlags::OrigAlignmentOffs); 3941 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 3942 } 3943 break; 3944 } 3945 } 3946 } 3947 3948 RetVals.push_back(MVT::Other); 3949 3950 // Create the node. 3951 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 3952 DAG.getNodeValueTypes(RetVals), RetVals.size(), 3953 &Ops[0], Ops.size()).Val; 3954 unsigned NumArgRegs = Result->getNumValues() - 1; 3955 DAG.setRoot(SDOperand(Result, NumArgRegs)); 3956 3957 // Set up the return result vector. 3958 Ops.clear(); 3959 unsigned i = 0; 3960 unsigned Idx = 1; 3961 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 3962 ++I, ++Idx) { 3963 MVT::ValueType VT = getValueType(I->getType()); 3964 3965 switch (getTypeAction(VT)) { 3966 default: assert(0 && "Unknown type action!"); 3967 case Legal: 3968 Ops.push_back(SDOperand(Result, i++)); 3969 break; 3970 case Promote: { 3971 SDOperand Op(Result, i++); 3972 if (MVT::isInteger(VT)) { 3973 if (F.paramHasAttr(Idx, ParamAttr::SExt)) 3974 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, 3975 DAG.getValueType(VT)); 3976 else if (F.paramHasAttr(Idx, ParamAttr::ZExt)) 3977 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, 3978 DAG.getValueType(VT)); 3979 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3980 } else { 3981 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3982 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 3983 } 3984 Ops.push_back(Op); 3985 break; 3986 } 3987 case Expand: { 3988 MVT::ValueType PartVT = getRegisterType(VT); 3989 unsigned NumParts = getNumRegisters(VT); 3990 SmallVector<SDOperand, 4> Parts(NumParts); 3991 for (unsigned j = 0; j != NumParts; ++j) 3992 Parts[j] = SDOperand(Result, i++); 3993 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); 3994 break; 3995 } 3996 } 3997 } 3998 assert(i == NumArgRegs && "Argument register count mismatch!"); 3999 return Ops; 4000} 4001 4002 4003/// TargetLowering::LowerCallTo - This is the default LowerCallTo 4004/// implementation, which just inserts an ISD::CALL node, which is later custom 4005/// lowered by the target to something concrete. FIXME: When all targets are 4006/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 4007std::pair<SDOperand, SDOperand> 4008TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 4009 bool RetTyIsSigned, bool isVarArg, 4010 unsigned CallingConv, bool isTailCall, 4011 SDOperand Callee, 4012 ArgListTy &Args, SelectionDAG &DAG) { 4013 SmallVector<SDOperand, 32> Ops; 4014 Ops.push_back(Chain); // Op#0 - Chain 4015 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 4016 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 4017 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 4018 Ops.push_back(Callee); 4019 4020 // Handle all of the outgoing arguments. 4021 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 4022 MVT::ValueType VT = getValueType(Args[i].Ty); 4023 SDOperand Op = Args[i].Node; 4024 unsigned Flags = ISD::ParamFlags::NoFlagSet; 4025 unsigned OriginalAlignment = 4026 getTargetData()->getABITypeAlignment(Args[i].Ty); 4027 4028 if (Args[i].isSExt) 4029 Flags |= ISD::ParamFlags::SExt; 4030 if (Args[i].isZExt) 4031 Flags |= ISD::ParamFlags::ZExt; 4032 if (Args[i].isInReg) 4033 Flags |= ISD::ParamFlags::InReg; 4034 if (Args[i].isSRet) 4035 Flags |= ISD::ParamFlags::StructReturn; 4036 if (Args[i].isByVal) { 4037 Flags |= ISD::ParamFlags::ByVal; 4038 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 4039 const StructType *STy = cast<StructType>(Ty->getElementType()); 4040 unsigned StructAlign = 4041 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy)); 4042 unsigned StructSize = getTargetData()->getABITypeSize(STy); 4043 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs); 4044 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs); 4045 } 4046 if (Args[i].isNest) 4047 Flags |= ISD::ParamFlags::Nest; 4048 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs; 4049 4050 switch (getTypeAction(VT)) { 4051 default: assert(0 && "Unknown type action!"); 4052 case Legal: 4053 Ops.push_back(Op); 4054 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4055 break; 4056 case Promote: 4057 if (MVT::isInteger(VT)) { 4058 unsigned ExtOp; 4059 if (Args[i].isSExt) 4060 ExtOp = ISD::SIGN_EXTEND; 4061 else if (Args[i].isZExt) 4062 ExtOp = ISD::ZERO_EXTEND; 4063 else 4064 ExtOp = ISD::ANY_EXTEND; 4065 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 4066 } else { 4067 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 4068 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 4069 } 4070 Ops.push_back(Op); 4071 Ops.push_back(DAG.getConstant(Flags, MVT::i32)); 4072 break; 4073 case Expand: { 4074 MVT::ValueType PartVT = getRegisterType(VT); 4075 unsigned NumParts = getNumRegisters(VT); 4076 SmallVector<SDOperand, 4> Parts(NumParts); 4077 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); 4078 for (unsigned i = 0; i != NumParts; ++i) { 4079 // if it isn't first piece, alignment must be 1 4080 unsigned MyFlags = Flags; 4081 if (i != 0) 4082 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | 4083 (1 << ISD::ParamFlags::OrigAlignmentOffs); 4084 4085 Ops.push_back(Parts[i]); 4086 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); 4087 } 4088 break; 4089 } 4090 } 4091 } 4092 4093 // Figure out the result value types. 4094 MVT::ValueType VT = getValueType(RetTy); 4095 MVT::ValueType RegisterVT = getRegisterType(VT); 4096 unsigned NumRegs = getNumRegisters(VT); 4097 SmallVector<MVT::ValueType, 4> RetTys(NumRegs); 4098 for (unsigned i = 0; i != NumRegs; ++i) 4099 RetTys[i] = RegisterVT; 4100 4101 RetTys.push_back(MVT::Other); // Always has a chain. 4102 4103 // Create the CALL node. 4104 SDOperand Res = DAG.getNode(ISD::CALL, 4105 DAG.getVTList(&RetTys[0], NumRegs + 1), 4106 &Ops[0], Ops.size()); 4107 Chain = Res.getValue(NumRegs); 4108 4109 // Gather up the call result into a single value. 4110 if (RetTy != Type::VoidTy) { 4111 ISD::NodeType AssertOp = ISD::AssertSext; 4112 if (!RetTyIsSigned) 4113 AssertOp = ISD::AssertZext; 4114 SmallVector<SDOperand, 4> Results(NumRegs); 4115 for (unsigned i = 0; i != NumRegs; ++i) 4116 Results[i] = Res.getValue(i); 4117 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); 4118 } 4119 4120 return std::make_pair(Res, Chain); 4121} 4122 4123SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4124 assert(0 && "LowerOperation not implemented for this target!"); 4125 abort(); 4126 return SDOperand(); 4127} 4128 4129SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 4130 SelectionDAG &DAG) { 4131 assert(0 && "CustomPromoteOperation not implemented for this target!"); 4132 abort(); 4133 return SDOperand(); 4134} 4135 4136/// getMemsetValue - Vectorized representation of the memset value 4137/// operand. 4138static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 4139 SelectionDAG &DAG) { 4140 MVT::ValueType CurVT = VT; 4141 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 4142 uint64_t Val = C->getValue() & 255; 4143 unsigned Shift = 8; 4144 while (CurVT != MVT::i8) { 4145 Val = (Val << Shift) | Val; 4146 Shift <<= 1; 4147 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4148 } 4149 return DAG.getConstant(Val, VT); 4150 } else { 4151 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 4152 unsigned Shift = 8; 4153 while (CurVT != MVT::i8) { 4154 Value = 4155 DAG.getNode(ISD::OR, VT, 4156 DAG.getNode(ISD::SHL, VT, Value, 4157 DAG.getConstant(Shift, MVT::i8)), Value); 4158 Shift <<= 1; 4159 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 4160 } 4161 4162 return Value; 4163 } 4164} 4165 4166/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 4167/// used when a memcpy is turned into a memset when the source is a constant 4168/// string ptr. 4169static SDOperand getMemsetStringVal(MVT::ValueType VT, 4170 SelectionDAG &DAG, TargetLowering &TLI, 4171 std::string &Str, unsigned Offset) { 4172 uint64_t Val = 0; 4173 unsigned MSB = MVT::getSizeInBits(VT) / 8; 4174 if (TLI.isLittleEndian()) 4175 Offset = Offset + MSB - 1; 4176 for (unsigned i = 0; i != MSB; ++i) { 4177 Val = (Val << 8) | (unsigned char)Str[Offset]; 4178 Offset += TLI.isLittleEndian() ? -1 : 1; 4179 } 4180 return DAG.getConstant(Val, VT); 4181} 4182 4183/// getMemBasePlusOffset - Returns base and offset node for the 4184static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 4185 SelectionDAG &DAG, TargetLowering &TLI) { 4186 MVT::ValueType VT = Base.getValueType(); 4187 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 4188} 4189 4190/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 4191/// to replace the memset / memcpy is below the threshold. It also returns the 4192/// types of the sequence of memory ops to perform memset / memcpy. 4193static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 4194 unsigned Limit, uint64_t Size, 4195 unsigned Align, TargetLowering &TLI) { 4196 MVT::ValueType VT; 4197 4198 if (TLI.allowsUnalignedMemoryAccesses()) { 4199 VT = MVT::i64; 4200 } else { 4201 switch (Align & 7) { 4202 case 0: 4203 VT = MVT::i64; 4204 break; 4205 case 4: 4206 VT = MVT::i32; 4207 break; 4208 case 2: 4209 VT = MVT::i16; 4210 break; 4211 default: 4212 VT = MVT::i8; 4213 break; 4214 } 4215 } 4216 4217 MVT::ValueType LVT = MVT::i64; 4218 while (!TLI.isTypeLegal(LVT)) 4219 LVT = (MVT::ValueType)((unsigned)LVT - 1); 4220 assert(MVT::isInteger(LVT)); 4221 4222 if (VT > LVT) 4223 VT = LVT; 4224 4225 unsigned NumMemOps = 0; 4226 while (Size != 0) { 4227 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4228 while (VTSize > Size) { 4229 VT = (MVT::ValueType)((unsigned)VT - 1); 4230 VTSize >>= 1; 4231 } 4232 assert(MVT::isInteger(VT)); 4233 4234 if (++NumMemOps > Limit) 4235 return false; 4236 MemOps.push_back(VT); 4237 Size -= VTSize; 4238 } 4239 4240 return true; 4241} 4242 4243void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 4244 SDOperand Op1 = getValue(I.getOperand(1)); 4245 SDOperand Op2 = getValue(I.getOperand(2)); 4246 SDOperand Op3 = getValue(I.getOperand(3)); 4247 SDOperand Op4 = getValue(I.getOperand(4)); 4248 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 4249 if (Align == 0) Align = 1; 4250 4251 // If the source and destination are known to not be aliases, we can 4252 // lower memmove as memcpy. 4253 if (Op == ISD::MEMMOVE) { 4254 uint64_t Size = -1ULL; 4255 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4256 Size = C->getValue(); 4257 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) == 4258 AliasAnalysis::NoAlias) 4259 Op = ISD::MEMCPY; 4260 } 4261 4262 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 4263 std::vector<MVT::ValueType> MemOps; 4264 4265 // Expand memset / memcpy to a series of load / store ops 4266 // if the size operand falls below a certain threshold. 4267 SmallVector<SDOperand, 8> OutChains; 4268 switch (Op) { 4269 default: break; // Do nothing for now. 4270 case ISD::MEMSET: { 4271 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 4272 Size->getValue(), Align, TLI)) { 4273 unsigned NumMemOps = MemOps.size(); 4274 unsigned Offset = 0; 4275 for (unsigned i = 0; i < NumMemOps; i++) { 4276 MVT::ValueType VT = MemOps[i]; 4277 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4278 SDOperand Value = getMemsetValue(Op2, VT, DAG); 4279 SDOperand Store = DAG.getStore(getRoot(), Value, 4280 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 4281 I.getOperand(1), Offset); 4282 OutChains.push_back(Store); 4283 Offset += VTSize; 4284 } 4285 } 4286 break; 4287 } 4288 case ISD::MEMCPY: { 4289 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 4290 Size->getValue(), Align, TLI)) { 4291 unsigned NumMemOps = MemOps.size(); 4292 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 4293 GlobalAddressSDNode *G = NULL; 4294 std::string Str; 4295 bool CopyFromStr = false; 4296 4297 if (Op2.getOpcode() == ISD::GlobalAddress) 4298 G = cast<GlobalAddressSDNode>(Op2); 4299 else if (Op2.getOpcode() == ISD::ADD && 4300 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 4301 Op2.getOperand(1).getOpcode() == ISD::Constant) { 4302 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 4303 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 4304 } 4305 if (G) { 4306 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 4307 if (GV && GV->isConstant()) { 4308 Str = GV->getStringValue(false); 4309 if (!Str.empty()) { 4310 CopyFromStr = true; 4311 SrcOff += SrcDelta; 4312 } 4313 } 4314 } 4315 4316 for (unsigned i = 0; i < NumMemOps; i++) { 4317 MVT::ValueType VT = MemOps[i]; 4318 unsigned VTSize = MVT::getSizeInBits(VT) / 8; 4319 SDOperand Value, Chain, Store; 4320 4321 if (CopyFromStr) { 4322 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 4323 Chain = getRoot(); 4324 Store = 4325 DAG.getStore(Chain, Value, 4326 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4327 I.getOperand(1), DstOff); 4328 } else { 4329 Value = DAG.getLoad(VT, getRoot(), 4330 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 4331 I.getOperand(2), SrcOff, false, Align); 4332 Chain = Value.getValue(1); 4333 Store = 4334 DAG.getStore(Chain, Value, 4335 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 4336 I.getOperand(1), DstOff, false, Align); 4337 } 4338 OutChains.push_back(Store); 4339 SrcOff += VTSize; 4340 DstOff += VTSize; 4341 } 4342 } 4343 break; 4344 } 4345 } 4346 4347 if (!OutChains.empty()) { 4348 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4349 &OutChains[0], OutChains.size())); 4350 return; 4351 } 4352 } 4353 4354 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1); 4355 SDOperand Node; 4356 switch(Op) { 4357 default: 4358 assert(0 && "Unknown Op"); 4359 case ISD::MEMCPY: 4360 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4361 break; 4362 case ISD::MEMMOVE: 4363 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4364 break; 4365 case ISD::MEMSET: 4366 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline); 4367 break; 4368 } 4369 DAG.setRoot(Node); 4370} 4371 4372//===----------------------------------------------------------------------===// 4373// SelectionDAGISel code 4374//===----------------------------------------------------------------------===// 4375 4376unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 4377 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 4378} 4379 4380void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 4381 AU.addRequired<AliasAnalysis>(); 4382 AU.setPreservesAll(); 4383} 4384 4385 4386 4387bool SelectionDAGISel::runOnFunction(Function &Fn) { 4388 // Get alias analysis for load/store combining. 4389 AA = &getAnalysis<AliasAnalysis>(); 4390 4391 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 4392 RegMap = MF.getSSARegMap(); 4393 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 4394 4395 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 4396 4397 if (ExceptionHandling) 4398 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4399 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 4400 // Mark landing pad. 4401 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 4402 4403 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 4404 SelectBasicBlock(I, MF, FuncInfo); 4405 4406 // Add function live-ins to entry block live-in set. 4407 BasicBlock *EntryBB = &Fn.getEntryBlock(); 4408 BB = FuncInfo.MBBMap[EntryBB]; 4409 if (!MF.livein_empty()) 4410 for (MachineFunction::livein_iterator I = MF.livein_begin(), 4411 E = MF.livein_end(); I != E; ++I) 4412 BB->addLiveIn(I->first); 4413 4414#ifndef NDEBUG 4415 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() && 4416 "Not all catch info was assigned to a landing pad!"); 4417#endif 4418 4419 return true; 4420} 4421 4422SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 4423 unsigned Reg) { 4424 SDOperand Op = getValue(V); 4425 assert((Op.getOpcode() != ISD::CopyFromReg || 4426 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 4427 "Copy from a reg to the same reg!"); 4428 4429 MVT::ValueType SrcVT = Op.getValueType(); 4430 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT); 4431 unsigned NumRegs = TLI.getNumRegisters(SrcVT); 4432 SmallVector<SDOperand, 8> Regs(NumRegs); 4433 SmallVector<SDOperand, 8> Chains(NumRegs); 4434 4435 // Copy the value by legal parts into sequential virtual registers. 4436 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); 4437 for (unsigned i = 0; i != NumRegs; ++i) 4438 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); 4439 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); 4440} 4441 4442void SelectionDAGISel:: 4443LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL, 4444 std::vector<SDOperand> &UnorderedChains) { 4445 // If this is the entry block, emit arguments. 4446 Function &F = *LLVMBB->getParent(); 4447 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 4448 SDOperand OldRoot = SDL.DAG.getRoot(); 4449 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 4450 4451 unsigned a = 0; 4452 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 4453 AI != E; ++AI, ++a) 4454 if (!AI->use_empty()) { 4455 SDL.setValue(AI, Args[a]); 4456 4457 // If this argument is live outside of the entry block, insert a copy from 4458 // whereever we got it to the vreg that other BB's will reference it as. 4459 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI); 4460 if (VMI != FuncInfo.ValueMap.end()) { 4461 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second); 4462 UnorderedChains.push_back(Copy); 4463 } 4464 } 4465 4466 // Finally, if the target has anything special to do, allow it to do so. 4467 // FIXME: this should insert code into the DAG! 4468 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 4469} 4470 4471static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, 4472 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 4473 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) 4474 if (isSelector(I)) { 4475 // Apply the catch info to DestBB. 4476 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]); 4477#ifndef NDEBUG 4478 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 4479 FLI.CatchInfoFound.insert(I); 4480#endif 4481 } 4482} 4483 4484/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the 4485/// DAG and fixes their tailcall attribute operand. 4486static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 4487 TargetLowering& TLI) { 4488 SDNode * Ret = NULL; 4489 SDOperand Terminator = DAG.getRoot(); 4490 4491 // Find RET node. 4492 if (Terminator.getOpcode() == ISD::RET) { 4493 Ret = Terminator.Val; 4494 } 4495 4496 // Fix tail call attribute of CALL nodes. 4497 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), 4498 BI = prior(DAG.allnodes_end()); BI != BE; --BI) { 4499 if (BI->getOpcode() == ISD::CALL) { 4500 SDOperand OpRet(Ret, 0); 4501 SDOperand OpCall(static_cast<SDNode*>(BI), 0); 4502 bool isMarkedTailCall = 4503 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0; 4504 // If CALL node has tail call attribute set to true and the call is not 4505 // eligible (no RET or the target rejects) the attribute is fixed to 4506 // false. The TargetLowering::IsEligibleForTailCallOptimization function 4507 // must correctly identify tail call optimizable calls. 4508 if (isMarkedTailCall && 4509 (Ret==NULL || 4510 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) { 4511 SmallVector<SDOperand, 32> Ops; 4512 unsigned idx=0; 4513 for(SDNode::op_iterator I =OpCall.Val->op_begin(), 4514 E=OpCall.Val->op_end(); I!=E; I++, idx++) { 4515 if (idx!=3) 4516 Ops.push_back(*I); 4517 else 4518 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy())); 4519 } 4520 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size()); 4521 } 4522 } 4523 } 4524} 4525 4526void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 4527 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 4528 FunctionLoweringInfo &FuncInfo) { 4529 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo); 4530 4531 std::vector<SDOperand> UnorderedChains; 4532 4533 // Lower any arguments needed in this block if this is the entry block. 4534 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) 4535 LowerArguments(LLVMBB, SDL, UnorderedChains); 4536 4537 BB = FuncInfo.MBBMap[LLVMBB]; 4538 SDL.setCurrentBasicBlock(BB); 4539 4540 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 4541 4542 if (ExceptionHandling && MMI && BB->isLandingPad()) { 4543 // Add a label to mark the beginning of the landing pad. Deletion of the 4544 // landing pad can thus be detected via the MachineModuleInfo. 4545 unsigned LabelID = MMI->addLandingPad(BB); 4546 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), 4547 DAG.getConstant(LabelID, MVT::i32))); 4548 4549 // Mark exception register as live in. 4550 unsigned Reg = TLI.getExceptionAddressRegister(); 4551 if (Reg) BB->addLiveIn(Reg); 4552 4553 // Mark exception selector register as live in. 4554 Reg = TLI.getExceptionSelectorRegister(); 4555 if (Reg) BB->addLiveIn(Reg); 4556 4557 // FIXME: Hack around an exception handling flaw (PR1508): the personality 4558 // function and list of typeids logically belong to the invoke (or, if you 4559 // like, the basic block containing the invoke), and need to be associated 4560 // with it in the dwarf exception handling tables. Currently however the 4561 // information is provided by an intrinsic (eh.selector) that can be moved 4562 // to unexpected places by the optimizers: if the unwind edge is critical, 4563 // then breaking it can result in the intrinsics being in the successor of 4564 // the landing pad, not the landing pad itself. This results in exceptions 4565 // not being caught because no typeids are associated with the invoke. 4566 // This may not be the only way things can go wrong, but it is the only way 4567 // we try to work around for the moment. 4568 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 4569 4570 if (Br && Br->isUnconditional()) { // Critical edge? 4571 BasicBlock::iterator I, E; 4572 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 4573 if (isSelector(I)) 4574 break; 4575 4576 if (I == E) 4577 // No catch info found - try to extract some from the successor. 4578 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo); 4579 } 4580 } 4581 4582 // Lower all of the non-terminator instructions. 4583 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4584 I != E; ++I) 4585 SDL.visit(*I); 4586 4587 // Ensure that all instructions which are used outside of their defining 4588 // blocks are available as virtual registers. Invoke is handled elsewhere. 4589 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4590 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) { 4591 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4592 if (VMI != FuncInfo.ValueMap.end()) 4593 UnorderedChains.push_back( 4594 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4595 } 4596 4597 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4598 // ensure constants are generated when needed. Remember the virtual registers 4599 // that need to be added to the Machine PHI nodes as input. We cannot just 4600 // directly add them, because expansion might result in multiple MBB's for one 4601 // BB. As such, the start of the BB might correspond to a different MBB than 4602 // the end. 4603 // 4604 TerminatorInst *TI = LLVMBB->getTerminator(); 4605 4606 // Emit constants only once even if used by multiple PHI nodes. 4607 std::map<Constant*, unsigned> ConstantsOut; 4608 4609 // Vector bool would be better, but vector<bool> is really slow. 4610 std::vector<unsigned char> SuccsHandled; 4611 if (TI->getNumSuccessors()) 4612 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4613 4614 // Check successor nodes' PHI nodes that expect a constant to be available 4615 // from this block. 4616 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4617 BasicBlock *SuccBB = TI->getSuccessor(succ); 4618 if (!isa<PHINode>(SuccBB->begin())) continue; 4619 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4620 4621 // If this terminator has multiple identical successors (common for 4622 // switches), only handle each succ once. 4623 unsigned SuccMBBNo = SuccMBB->getNumber(); 4624 if (SuccsHandled[SuccMBBNo]) continue; 4625 SuccsHandled[SuccMBBNo] = true; 4626 4627 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4628 PHINode *PN; 4629 4630 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4631 // nodes and Machine PHI nodes, but the incoming operands have not been 4632 // emitted yet. 4633 for (BasicBlock::iterator I = SuccBB->begin(); 4634 (PN = dyn_cast<PHINode>(I)); ++I) { 4635 // Ignore dead phi's. 4636 if (PN->use_empty()) continue; 4637 4638 unsigned Reg; 4639 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4640 4641 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4642 unsigned &RegOut = ConstantsOut[C]; 4643 if (RegOut == 0) { 4644 RegOut = FuncInfo.CreateRegForValue(C); 4645 UnorderedChains.push_back( 4646 SDL.CopyValueToVirtualRegister(C, RegOut)); 4647 } 4648 Reg = RegOut; 4649 } else { 4650 Reg = FuncInfo.ValueMap[PHIOp]; 4651 if (Reg == 0) { 4652 assert(isa<AllocaInst>(PHIOp) && 4653 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4654 "Didn't codegen value into a register!??"); 4655 Reg = FuncInfo.CreateRegForValue(PHIOp); 4656 UnorderedChains.push_back( 4657 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4658 } 4659 } 4660 4661 // Remember that this register needs to added to the machine PHI node as 4662 // the input for this MBB. 4663 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4664 unsigned NumRegisters = TLI.getNumRegisters(VT); 4665 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 4666 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4667 } 4668 } 4669 ConstantsOut.clear(); 4670 4671 // Turn all of the unordered chains into one factored node. 4672 if (!UnorderedChains.empty()) { 4673 SDOperand Root = SDL.getRoot(); 4674 if (Root.getOpcode() != ISD::EntryToken) { 4675 unsigned i = 0, e = UnorderedChains.size(); 4676 for (; i != e; ++i) { 4677 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4678 if (UnorderedChains[i].Val->getOperand(0) == Root) 4679 break; // Don't add the root if we already indirectly depend on it. 4680 } 4681 4682 if (i == e) 4683 UnorderedChains.push_back(Root); 4684 } 4685 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4686 &UnorderedChains[0], UnorderedChains.size())); 4687 } 4688 4689 // Lower the terminator after the copies are emitted. 4690 SDL.visit(*LLVMBB->getTerminator()); 4691 4692 // Copy over any CaseBlock records that may now exist due to SwitchInst 4693 // lowering, as well as any jump table information. 4694 SwitchCases.clear(); 4695 SwitchCases = SDL.SwitchCases; 4696 JTCases.clear(); 4697 JTCases = SDL.JTCases; 4698 BitTestCases.clear(); 4699 BitTestCases = SDL.BitTestCases; 4700 4701 // Make sure the root of the DAG is up-to-date. 4702 DAG.setRoot(SDL.getRoot()); 4703 4704 // Check whether calls in this block are real tail calls. Fix up CALL nodes 4705 // with correct tailcall attribute so that the target can rely on the tailcall 4706 // attribute indicating whether the call is really eligible for tail call 4707 // optimization. 4708 CheckDAGForTailCallsAndFixThem(DAG, TLI); 4709} 4710 4711void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4712 DOUT << "Lowered selection DAG:\n"; 4713 DEBUG(DAG.dump()); 4714 4715 // Run the DAG combiner in pre-legalize mode. 4716 DAG.Combine(false, *AA); 4717 4718 DOUT << "Optimized lowered selection DAG:\n"; 4719 DEBUG(DAG.dump()); 4720 4721 // Second step, hack on the DAG until it only uses operations and types that 4722 // the target supports. 4723#if 0 // Enable this some day. 4724 DAG.LegalizeTypes(); 4725 // Someday even later, enable a dag combine pass here. 4726#endif 4727 DAG.Legalize(); 4728 4729 DOUT << "Legalized selection DAG:\n"; 4730 DEBUG(DAG.dump()); 4731 4732 // Run the DAG combiner in post-legalize mode. 4733 DAG.Combine(true, *AA); 4734 4735 DOUT << "Optimized legalized selection DAG:\n"; 4736 DEBUG(DAG.dump()); 4737 4738 if (ViewISelDAGs) DAG.viewGraph(); 4739 4740 // Third, instruction select all of the operations to machine code, adding the 4741 // code to the MachineBasicBlock. 4742 InstructionSelectBasicBlock(DAG); 4743 4744 DOUT << "Selected machine code:\n"; 4745 DEBUG(BB->dump()); 4746} 4747 4748void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4749 FunctionLoweringInfo &FuncInfo) { 4750 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4751 { 4752 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4753 CurDAG = &DAG; 4754 4755 // First step, lower LLVM code to some DAG. This DAG may use operations and 4756 // types that are not supported by the target. 4757 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4758 4759 // Second step, emit the lowered DAG as machine code. 4760 CodeGenAndEmitDAG(DAG); 4761 } 4762 4763 DOUT << "Total amount of phi nodes to update: " 4764 << PHINodesToUpdate.size() << "\n"; 4765 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) 4766 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first 4767 << ", " << PHINodesToUpdate[i].second << ")\n";); 4768 4769 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4770 // PHI nodes in successors. 4771 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) { 4772 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4773 MachineInstr *PHI = PHINodesToUpdate[i].first; 4774 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4775 "This is not a machine PHI node that we are updating!"); 4776 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4777 PHI->addMachineBasicBlockOperand(BB); 4778 } 4779 return; 4780 } 4781 4782 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) { 4783 // Lower header first, if it wasn't already lowered 4784 if (!BitTestCases[i].Emitted) { 4785 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4786 CurDAG = &HSDAG; 4787 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4788 // Set the current basic block to the mbb we wish to insert the code into 4789 BB = BitTestCases[i].Parent; 4790 HSDL.setCurrentBasicBlock(BB); 4791 // Emit the code 4792 HSDL.visitBitTestHeader(BitTestCases[i]); 4793 HSDAG.setRoot(HSDL.getRoot()); 4794 CodeGenAndEmitDAG(HSDAG); 4795 } 4796 4797 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4798 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4799 CurDAG = &BSDAG; 4800 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo); 4801 // Set the current basic block to the mbb we wish to insert the code into 4802 BB = BitTestCases[i].Cases[j].ThisBB; 4803 BSDL.setCurrentBasicBlock(BB); 4804 // Emit the code 4805 if (j+1 != ej) 4806 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB, 4807 BitTestCases[i].Reg, 4808 BitTestCases[i].Cases[j]); 4809 else 4810 BSDL.visitBitTestCase(BitTestCases[i].Default, 4811 BitTestCases[i].Reg, 4812 BitTestCases[i].Cases[j]); 4813 4814 4815 BSDAG.setRoot(BSDL.getRoot()); 4816 CodeGenAndEmitDAG(BSDAG); 4817 } 4818 4819 // Update PHI Nodes 4820 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4821 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4822 MachineBasicBlock *PHIBB = PHI->getParent(); 4823 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4824 "This is not a machine PHI node that we are updating!"); 4825 // This is "default" BB. We have two jumps to it. From "header" BB and 4826 // from last "case" BB. 4827 if (PHIBB == BitTestCases[i].Default) { 4828 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4829 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent); 4830 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4831 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB); 4832 } 4833 // One of "cases" BB. 4834 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { 4835 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB; 4836 if (cBB->succ_end() != 4837 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) { 4838 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4839 PHI->addMachineBasicBlockOperand(cBB); 4840 } 4841 } 4842 } 4843 } 4844 4845 // If the JumpTable record is filled in, then we need to emit a jump table. 4846 // Updating the PHI nodes is tricky in this case, since we need to determine 4847 // whether the PHI is a successor of the range check MBB or the jump table MBB 4848 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) { 4849 // Lower header first, if it wasn't already lowered 4850 if (!JTCases[i].first.Emitted) { 4851 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4852 CurDAG = &HSDAG; 4853 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo); 4854 // Set the current basic block to the mbb we wish to insert the code into 4855 BB = JTCases[i].first.HeaderBB; 4856 HSDL.setCurrentBasicBlock(BB); 4857 // Emit the code 4858 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first); 4859 HSDAG.setRoot(HSDL.getRoot()); 4860 CodeGenAndEmitDAG(HSDAG); 4861 } 4862 4863 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4864 CurDAG = &JSDAG; 4865 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo); 4866 // Set the current basic block to the mbb we wish to insert the code into 4867 BB = JTCases[i].second.MBB; 4868 JSDL.setCurrentBasicBlock(BB); 4869 // Emit the code 4870 JSDL.visitJumpTable(JTCases[i].second); 4871 JSDAG.setRoot(JSDL.getRoot()); 4872 CodeGenAndEmitDAG(JSDAG); 4873 4874 // Update PHI Nodes 4875 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4876 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4877 MachineBasicBlock *PHIBB = PHI->getParent(); 4878 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4879 "This is not a machine PHI node that we are updating!"); 4880 // "default" BB. We can go there only from header BB. 4881 if (PHIBB == JTCases[i].second.Default) { 4882 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4883 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB); 4884 } 4885 // JT BB. Just iterate over successors here 4886 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4887 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4888 PHI->addMachineBasicBlockOperand(BB); 4889 } 4890 } 4891 } 4892 4893 // If the switch block involved a branch to one of the actual successors, we 4894 // need to update PHI nodes in that block. 4895 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4896 MachineInstr *PHI = PHINodesToUpdate[i].first; 4897 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4898 "This is not a machine PHI node that we are updating!"); 4899 if (BB->isSuccessor(PHI->getParent())) { 4900 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4901 PHI->addMachineBasicBlockOperand(BB); 4902 } 4903 } 4904 4905 // If we generated any switch lowering information, build and codegen any 4906 // additional DAGs necessary. 4907 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4908 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>()); 4909 CurDAG = &SDAG; 4910 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo); 4911 4912 // Set the current basic block to the mbb we wish to insert the code into 4913 BB = SwitchCases[i].ThisBB; 4914 SDL.setCurrentBasicBlock(BB); 4915 4916 // Emit the code 4917 SDL.visitSwitchCase(SwitchCases[i]); 4918 SDAG.setRoot(SDL.getRoot()); 4919 CodeGenAndEmitDAG(SDAG); 4920 4921 // Handle any PHI nodes in successors of this chunk, as if we were coming 4922 // from the original BB before switch expansion. Note that PHI nodes can 4923 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4924 // handle them the right number of times. 4925 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4926 for (MachineBasicBlock::iterator Phi = BB->begin(); 4927 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4928 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4929 for (unsigned pn = 0; ; ++pn) { 4930 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4931 if (PHINodesToUpdate[pn].first == Phi) { 4932 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4933 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4934 break; 4935 } 4936 } 4937 } 4938 4939 // Don't process RHS if same block as LHS. 4940 if (BB == SwitchCases[i].FalseBB) 4941 SwitchCases[i].FalseBB = 0; 4942 4943 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4944 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4945 SwitchCases[i].FalseBB = 0; 4946 } 4947 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4948 } 4949} 4950 4951 4952//===----------------------------------------------------------------------===// 4953/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4954/// target node in the graph. 4955void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4956 if (ViewSchedDAGs) DAG.viewGraph(); 4957 4958 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4959 4960 if (!Ctor) { 4961 Ctor = ISHeuristic; 4962 RegisterScheduler::setDefault(Ctor); 4963 } 4964 4965 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4966 BB = SL->Run(); 4967 4968 if (ViewSUnitDAGs) SL->viewGraph(); 4969 4970 delete SL; 4971} 4972 4973 4974HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4975 return new HazardRecognizer(); 4976} 4977 4978//===----------------------------------------------------------------------===// 4979// Helper functions used by the generated instruction selector. 4980//===----------------------------------------------------------------------===// 4981// Calls to these methods are generated by tblgen. 4982 4983/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4984/// the dag combiner simplified the 255, we still want to match. RHS is the 4985/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4986/// specified in the .td file (e.g. 255). 4987bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4988 int64_t DesiredMaskS) const { 4989 uint64_t ActualMask = RHS->getValue(); 4990 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4991 4992 // If the actual mask exactly matches, success! 4993 if (ActualMask == DesiredMask) 4994 return true; 4995 4996 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4997 if (ActualMask & ~DesiredMask) 4998 return false; 4999 5000 // Otherwise, the DAG Combiner may have proven that the value coming in is 5001 // either already zero or is not demanded. Check for known zero input bits. 5002 uint64_t NeededMask = DesiredMask & ~ActualMask; 5003 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 5004 return true; 5005 5006 // TODO: check to see if missing bits are just not demanded. 5007 5008 // Otherwise, this pattern doesn't match. 5009 return false; 5010} 5011 5012/// CheckOrMask - The isel is trying to match something like (or X, 255). If 5013/// the dag combiner simplified the 255, we still want to match. RHS is the 5014/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 5015/// specified in the .td file (e.g. 255). 5016bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 5017 int64_t DesiredMaskS) const { 5018 uint64_t ActualMask = RHS->getValue(); 5019 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 5020 5021 // If the actual mask exactly matches, success! 5022 if (ActualMask == DesiredMask) 5023 return true; 5024 5025 // If the actual AND mask is allowing unallowed bits, this doesn't match. 5026 if (ActualMask & ~DesiredMask) 5027 return false; 5028 5029 // Otherwise, the DAG Combiner may have proven that the value coming in is 5030 // either already zero or is not demanded. Check for known zero input bits. 5031 uint64_t NeededMask = DesiredMask & ~ActualMask; 5032 5033 uint64_t KnownZero, KnownOne; 5034 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 5035 5036 // If all the missing bits in the or are already known to be set, match! 5037 if ((NeededMask & KnownOne) == NeededMask) 5038 return true; 5039 5040 // TODO: check to see if missing bits are just not demanded. 5041 5042 // Otherwise, this pattern doesn't match. 5043 return false; 5044} 5045 5046 5047/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 5048/// by tblgen. Others should not call it. 5049void SelectionDAGISel:: 5050SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 5051 std::vector<SDOperand> InOps; 5052 std::swap(InOps, Ops); 5053 5054 Ops.push_back(InOps[0]); // input chain. 5055 Ops.push_back(InOps[1]); // input asm string. 5056 5057 unsigned i = 2, e = InOps.size(); 5058 if (InOps[e-1].getValueType() == MVT::Flag) 5059 --e; // Don't process a flag operand if it is here. 5060 5061 while (i != e) { 5062 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 5063 if ((Flags & 7) != 4 /*MEM*/) { 5064 // Just skip over this operand, copying the operands verbatim. 5065 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 5066 i += (Flags >> 3) + 1; 5067 } else { 5068 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 5069 // Otherwise, this is a memory operand. Ask the target to select it. 5070 std::vector<SDOperand> SelOps; 5071 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 5072 cerr << "Could not match memory address. Inline asm failure!\n"; 5073 exit(1); 5074 } 5075 5076 // Add this to the output node. 5077 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); 5078 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), 5079 IntPtrTy)); 5080 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 5081 i += 2; 5082 } 5083 } 5084 5085 // Add the flag input back if present. 5086 if (e != InOps.size()) 5087 Ops.push_back(InOps.back()); 5088} 5089 5090char SelectionDAGISel::ID = 0; 5091