TargetSchedule.cpp revision 3918cade8f7c0a9ff4e3c5799a55846d8f6e3fd4 
1//===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements a wrapper around MCSchedModel that allows the interface
11// to benefit from information currently only available in TargetInstrInfo.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetSchedule.h"
16#include "llvm/Target/TargetInstrInfo.h"
17#include "llvm/Target/TargetRegisterInfo.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
24static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
25  cl::desc("Use TargetSchedModel for latency lookup"));
26
27static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
28  cl::desc("Use InstrItineraryData for latency lookup"));
29
30void TargetSchedModel::init(const MCSchedModel &sm,
31                            const TargetSubtargetInfo *sti,
32                            const TargetInstrInfo *tii) {
33  SchedModel = sm;
34  STI = sti;
35  TII = tii;
36  STI->initInstrItins(InstrItins);
37}
38
39/// If we can determine the operand latency from the def only, without machine
40/// model or itinerary lookup, do so. Otherwise return -1.
41int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
42                                    bool FindMin) const {
43
44  // Return a latency based on the itinerary properties and defining instruction
45  // if possible. Some common subtargets don't require per-operand latency,
46  // especially for minimum latencies.
47  if (FindMin) {
48    // If MinLatency is invalid, then use the itinerary for MinLatency. If no
49    // itinerary exists either, then use single cycle latency.
50    if (SchedModel.MinLatency < 0
51        && !(EnableSchedItins && hasInstrItineraries())) {
52      return 1;
53    }
54    return SchedModel.MinLatency;
55  }
56  else if (!(EnableSchedModel && hasInstrSchedModel())
57           && !(EnableSchedItins && hasInstrItineraries())) {
58    return TII->defaultDefLatency(&SchedModel, DefMI);
59  }
60  // ...operand lookup required
61  return -1;
62}
63
64/// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
65/// evaluation of predicates that depend on instruction operands or flags.
66const MCSchedClassDesc *TargetSchedModel::
67resolveSchedClass(const MachineInstr *MI) const {
68
69  // Get the definition's scheduling class descriptor from this machine model.
70  unsigned SchedClass = MI->getDesc().getSchedClass();
71  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
72
73#ifndef NDEBUG
74  unsigned NIter = 0;
75#endif
76  while (SCDesc->isVariant()) {
77    assert(++NIter < 6 && "Variants are nested deeper than the magic number");
78
79    SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
80    SCDesc = SchedModel.getSchedClassDesc(SchedClass);
81  }
82  return SCDesc;
83}
84
85/// Find the def index of this operand. This index maps to the machine model and
86/// is independent of use operands. Def operands may be reordered with uses or
87/// merged with uses without affecting the def index (e.g. before/after
88/// regalloc). However, an instruction's def operands must never be reordered
89/// with respect to each other.
90static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
91  unsigned DefIdx = 0;
92  for (unsigned i = 0; i != DefOperIdx; ++i) {
93    const MachineOperand &MO = MI->getOperand(i);
94    if (MO.isReg() && MO.isDef())
95      ++DefIdx;
96  }
97  return DefIdx;
98}
99
100/// Find the use index of this operand. This is independent of the instruction's
101/// def operands.
102///
103/// Note that uses are not determined by the operand's isUse property, which
104/// is simply the inverse of isDef. Here we consider any readsReg operand to be
105/// a "use". The machine model allows an operand to be both a Def and Use.
106static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
107  unsigned UseIdx = 0;
108  for (unsigned i = 0; i != UseOperIdx; ++i) {
109    const MachineOperand &MO = MI->getOperand(i);
110    if (MO.isReg() && MO.readsReg())
111      ++UseIdx;
112  }
113  return UseIdx;
114}
115
116// Top-level API for clients that know the operand indices.
117unsigned TargetSchedModel::computeOperandLatency(
118  const MachineInstr *DefMI, unsigned DefOperIdx,
119  const MachineInstr *UseMI, unsigned UseOperIdx,
120  bool FindMin) const {
121
122  int DefLatency = getDefLatency(DefMI, FindMin);
123  if (DefLatency >= 0)
124    return DefLatency;
125
126  if (!FindMin && EnableSchedModel && hasInstrSchedModel()) {
127    const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
128    unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
129    if (DefIdx < SCDesc->NumWriteLatencyEntries) {
130      // Lookup the definition's write latency in SubtargetInfo.
131      const MCWriteLatencyEntry *WLEntry =
132        STI->getWriteLatencyEntry(SCDesc, DefIdx);
133      unsigned WriteID = WLEntry->WriteResourceID;
134      unsigned Latency = WLEntry->Cycles;
135      if (!UseMI)
136        return Latency;
137
138      // Lookup the use's latency adjustment in SubtargetInfo.
139      const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
140      if (UseDesc->NumReadAdvanceEntries == 0)
141        return Latency;
142      unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
143      return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
144    }
145    // If DefIdx does not exist in the model (e.g. implicit defs), then return
146    // unit latency (defaultDefLatency may be too conservative).
147#ifndef NDEBUG
148    if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
149        && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
150      std::string Err;
151      raw_string_ostream ss(Err);
152      ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
153         << *DefMI;
154      report_fatal_error(ss.str());
155    }
156#endif
157    return 1;
158  }
159  assert(EnableSchedItins && hasInstrItineraries() &&
160         "operand latency requires itinerary");
161
162  int OperLatency = 0;
163  if (UseMI) {
164    OperLatency =
165      TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
166  }
167  else {
168    unsigned DefClass = DefMI->getDesc().getSchedClass();
169    OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
170  }
171  if (OperLatency >= 0)
172    return OperLatency;
173
174  // No operand latency was found.
175  unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
176
177  // Expected latency is the max of the stage latency and itinerary props.
178  if (!FindMin)
179    InstrLatency = std::max(InstrLatency,
180                            TII->defaultDefLatency(&SchedModel, DefMI));
181  return InstrLatency;
182}
183