| d42730dc712026cbfb1322a979e0ac72cd31a19e |
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30-Sep-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
IfConverter: Use TargetSchedule for instruction latencies
For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).
Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.
ATTENTION: Out of tree targets!
(I will also send out an email later to LLVMDev)
This means, if your target implements
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost);
and returns a value for "PredCost", you now also need to implement
unsigned getPredictationCost(const MachineInstr *MI);
(if your target uses the IfConversion.cpp pass)
radar://15077010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 070156437752179833b1e5fddd50caa03fd7c12f |
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25-Sep-2013 |
Andrew Trick <atrick@apple.com> |
Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.
Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 71b9d94d6ba2933df0f7936c44cdb344336d46ef |
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17-Jun-2013 |
Andrew Trick <atrick@apple.com> |
MI-Sched: handle ReadAdvance latencies as used by Swift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| b86a0cdb674549d8493043331cecd9cbf53b80da |
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15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 6a22dba4854a8b3d7427f8493f663c1b52df4477 |
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13-Apr-2013 |
Andrew Trick <atrick@apple.com> |
MI-Sched cleanup. If an instruction has no valid sched class, do not attempt to check for a variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 51f6747b23bf7c85e90f816bf9bfae3a1d4fd058 |
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16-Mar-2013 |
Andrew Trick <atrick@apple.com> |
Change the default latency for implicit defs.
Implicit defs are not currently positional and not modeled by the
per-operand machine model. Unfortunately, we treat defs that are part
of the architectural instruction description, like flags, the same as
other implicit defs. Really, they should have a fixed MachineInstr
layout and probably shouldn't be "implicit" at all.
For now, we'll change the default latency to be the max operand
latency. That will give flag setting operands full latency for x86
folded loads. Other kinds of "fake" implicit defs don't occur prior to
regalloc anyway, and we would like them to go away postRegAlloc as
well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
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03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 8d4abb2446f80986ad5136bbec30c5da18cd6f4b |
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06-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: TargetSchedule interface for machine resources.
Expose the processor resources defined by the machine model to the
scheduler and other clients through the TargetSchedule interface.
Normalize each resource count with respect to other kinds of
resources. This allows scheduling heuristics to balance resources
against other kinds of resources and latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| fdd6fa89b960088b368231ec08e56a0c0b1e6930 |
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17-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Better handling of invalid latencies in the machine model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 4903c15b7d92802a4f0f28928a89bb4c0d5e212f |
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11-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Handle "transient" non-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 82d46aec62f127856f4bfeb30f80aa12dd74bae0 |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: fall-back to a target hook for instr bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 412cd2f81374865dfa708bef6d5b896ca10dece0 |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.
Allows the HazardRecognizer to be disabled along with itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| c0dfffa448ad7ab647779bc3e7f2aee5c76cb31b |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Add computeInstrLatency to TargetSchedModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 42bb106118db51393c2524c8b0c7f7ba6674cfd7 |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 72fd0a9448a9d9eced8f475741e4a1ee543253e0 |
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04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
Enable -schedmodel, but prefer itineraries until we have more benchmark data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 3918cade8f7c0a9ff4e3c5799a55846d8f6e3fd4 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedule: cleanup computeOperandLatency logic & diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 34301ceca8913f3126339f332d3dc6f2d7ac0d78 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| e1b53287179b4b9b5c3c549586f688d3fa2ae8ef |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 12886db4a7af74f17281695320c40248cb263f55 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
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| 99ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7b |
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14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel interface. To be implemented...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetSchedule.cpp
|