MipsSEInstrInfo.h revision 8589010e3d1d5a902992a5039cffa9d4116982c5 
11320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
21320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//
31320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//                     The LLVM Compiler Infrastructure
41320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//
51320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci// This file is distributed under the University of Illinois Open Source
61320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci// License. See LICENSE.TXT for details.
71320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//
81320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//===----------------------------------------------------------------------===//
91320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//
101320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
111320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//
121320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//===----------------------------------------------------------------------===//
131320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci
141320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci#ifndef MIPSSEINSTRUCTIONINFO_H
151320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci#define MIPSSEINSTRUCTIONINFO_H
16
17#include "MipsInstrInfo.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsSERegisterInfo.h"
20
21namespace llvm {
22
23class MipsSEInstrInfo : public MipsInstrInfo {
24  const MipsSERegisterInfo RI;
25  bool IsN64;
26
27public:
28  explicit MipsSEInstrInfo(MipsTargetMachine &TM);
29
30  virtual const MipsRegisterInfo &getRegisterInfo() const;
31
32  /// isLoadFromStackSlot - If the specified machine instruction is a direct
33  /// load from a stack slot, return the virtual or physical register number of
34  /// the destination along with the FrameIndex of the loaded stack slot.  If
35  /// not, return 0.  This predicate must return 0 if the instruction has
36  /// any side effects other than loading from the stack slot.
37  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
38                                       int &FrameIndex) const;
39
40  /// isStoreToStackSlot - If the specified machine instruction is a direct
41  /// store to a stack slot, return the virtual or physical register number of
42  /// the source reg along with the FrameIndex of the loaded stack slot.  If
43  /// not, return 0.  This predicate must return 0 if the instruction has
44  /// any side effects other than storing to the stack slot.
45  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
46                                      int &FrameIndex) const;
47
48  virtual void copyPhysReg(MachineBasicBlock &MBB,
49                           MachineBasicBlock::iterator MI, DebugLoc DL,
50                           unsigned DestReg, unsigned SrcReg,
51                           bool KillSrc) const;
52
53  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
54                                   MachineBasicBlock::iterator MBBI,
55                                   unsigned SrcReg, bool isKill, int FrameIndex,
56                                   const TargetRegisterClass *RC,
57                                   const TargetRegisterInfo *TRI) const;
58
59  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
60                                    MachineBasicBlock::iterator MBBI,
61                                    unsigned DestReg, int FrameIndex,
62                                    const TargetRegisterClass *RC,
63                                    const TargetRegisterInfo *TRI) const;
64
65  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
66
67  virtual unsigned GetOppositeBranchOpc(unsigned Opc) const;
68
69private:
70  virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const;
71
72  void ExpandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
73                   unsigned Opc) const;
74  void ExpandExtractElementF64(MachineBasicBlock &MBB,
75                               MachineBasicBlock::iterator I) const;
76  void ExpandBuildPairF64(MachineBasicBlock &MBB,
77                          MachineBasicBlock::iterator I) const;
78};
79
80}
81
82#endif
83