1//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that NVPTX uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef NVPTXISELLOWERING_H
16#define NVPTXISELLOWERING_H
17
18#include "NVPTX.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23namespace NVPTXISD {
24enum NodeType {
25  // Start the numbering from where ISD NodeType finishes.
26  FIRST_NUMBER = ISD::BUILTIN_OP_END,
27  Wrapper,
28  CALL,
29  RET_FLAG,
30  LOAD_PARAM,
31  DeclareParam,
32  DeclareScalarParam,
33  DeclareRetParam,
34  DeclareRet,
35  DeclareScalarRet,
36  PrintCall,
37  PrintCallUni,
38  CallArgBegin,
39  CallArg,
40  LastCallArg,
41  CallArgEnd,
42  CallVoid,
43  CallVal,
44  CallSymbol,
45  Prototype,
46  MoveParam,
47  PseudoUseParam,
48  RETURN,
49  CallSeqBegin,
50  CallSeqEnd,
51  CallPrototype,
52  FUN_SHFL_CLAMP,
53  FUN_SHFR_CLAMP,
54  MUL_WIDE_SIGNED,
55  MUL_WIDE_UNSIGNED,
56  IMAD,
57  Dummy,
58
59  LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
60  LoadV4,
61  LDGV2, // LDG.v2
62  LDGV4, // LDG.v4
63  LDUV2, // LDU.v2
64  LDUV4, // LDU.v4
65  StoreV2,
66  StoreV4,
67  LoadParam,
68  LoadParamV2,
69  LoadParamV4,
70  StoreParam,
71  StoreParamV2,
72  StoreParamV4,
73  StoreParamS32, // to sext and store a <32bit value, not used currently
74  StoreParamU32, // to zext and store a <32bit value, not used currently
75  StoreRetval,
76  StoreRetvalV2,
77  StoreRetvalV4,
78
79  // Texture intrinsics
80  Tex1DFloatI32,
81  Tex1DFloatFloat,
82  Tex1DFloatFloatLevel,
83  Tex1DFloatFloatGrad,
84  Tex1DI32I32,
85  Tex1DI32Float,
86  Tex1DI32FloatLevel,
87  Tex1DI32FloatGrad,
88  Tex1DArrayFloatI32,
89  Tex1DArrayFloatFloat,
90  Tex1DArrayFloatFloatLevel,
91  Tex1DArrayFloatFloatGrad,
92  Tex1DArrayI32I32,
93  Tex1DArrayI32Float,
94  Tex1DArrayI32FloatLevel,
95  Tex1DArrayI32FloatGrad,
96  Tex2DFloatI32,
97  Tex2DFloatFloat,
98  Tex2DFloatFloatLevel,
99  Tex2DFloatFloatGrad,
100  Tex2DI32I32,
101  Tex2DI32Float,
102  Tex2DI32FloatLevel,
103  Tex2DI32FloatGrad,
104  Tex2DArrayFloatI32,
105  Tex2DArrayFloatFloat,
106  Tex2DArrayFloatFloatLevel,
107  Tex2DArrayFloatFloatGrad,
108  Tex2DArrayI32I32,
109  Tex2DArrayI32Float,
110  Tex2DArrayI32FloatLevel,
111  Tex2DArrayI32FloatGrad,
112  Tex3DFloatI32,
113  Tex3DFloatFloat,
114  Tex3DFloatFloatLevel,
115  Tex3DFloatFloatGrad,
116  Tex3DI32I32,
117  Tex3DI32Float,
118  Tex3DI32FloatLevel,
119  Tex3DI32FloatGrad,
120
121  // Surface intrinsics
122  Suld1DI8Trap,
123  Suld1DI16Trap,
124  Suld1DI32Trap,
125  Suld1DV2I8Trap,
126  Suld1DV2I16Trap,
127  Suld1DV2I32Trap,
128  Suld1DV4I8Trap,
129  Suld1DV4I16Trap,
130  Suld1DV4I32Trap,
131
132  Suld1DArrayI8Trap,
133  Suld1DArrayI16Trap,
134  Suld1DArrayI32Trap,
135  Suld1DArrayV2I8Trap,
136  Suld1DArrayV2I16Trap,
137  Suld1DArrayV2I32Trap,
138  Suld1DArrayV4I8Trap,
139  Suld1DArrayV4I16Trap,
140  Suld1DArrayV4I32Trap,
141
142  Suld2DI8Trap,
143  Suld2DI16Trap,
144  Suld2DI32Trap,
145  Suld2DV2I8Trap,
146  Suld2DV2I16Trap,
147  Suld2DV2I32Trap,
148  Suld2DV4I8Trap,
149  Suld2DV4I16Trap,
150  Suld2DV4I32Trap,
151
152  Suld2DArrayI8Trap,
153  Suld2DArrayI16Trap,
154  Suld2DArrayI32Trap,
155  Suld2DArrayV2I8Trap,
156  Suld2DArrayV2I16Trap,
157  Suld2DArrayV2I32Trap,
158  Suld2DArrayV4I8Trap,
159  Suld2DArrayV4I16Trap,
160  Suld2DArrayV4I32Trap,
161
162  Suld3DI8Trap,
163  Suld3DI16Trap,
164  Suld3DI32Trap,
165  Suld3DV2I8Trap,
166  Suld3DV2I16Trap,
167  Suld3DV2I32Trap,
168  Suld3DV4I8Trap,
169  Suld3DV4I16Trap,
170  Suld3DV4I32Trap
171};
172}
173
174class NVPTXSubtarget;
175
176//===--------------------------------------------------------------------===//
177// TargetLowering Implementation
178//===--------------------------------------------------------------------===//
179class NVPTXTargetLowering : public TargetLowering {
180public:
181  explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
182  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
183
184  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
185  SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
186                             SelectionDAG &DAG) const;
187
188  const char *getTargetNodeName(unsigned Opcode) const override;
189
190  bool isTypeSupportedInIntrinsic(MVT VT) const;
191
192  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
193                          unsigned Intrinsic) const override;
194
195  /// isLegalAddressingMode - Return true if the addressing mode represented
196  /// by AM is legal for this target, for a load/store of the specified type
197  /// Used to guide target specific optimizations, like loop strength
198  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
199  /// address mode (CodeGenPrepare.cpp)
200  bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
201
202  /// getFunctionAlignment - Return the Log2 alignment of this function.
203  unsigned getFunctionAlignment(const Function *F) const;
204
205  EVT getSetCCResultType(LLVMContext &Ctx, EVT VT) const override {
206    if (VT.isVector())
207      return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
208    return MVT::i1;
209  }
210
211  ConstraintType
212  getConstraintType(const std::string &Constraint) const override;
213  std::pair<unsigned, const TargetRegisterClass *>
214  getRegForInlineAsmConstraint(const std::string &Constraint,
215                               MVT VT) const override;
216
217  SDValue LowerFormalArguments(
218      SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
219      const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
220      SmallVectorImpl<SDValue> &InVals) const override;
221
222  SDValue LowerCall(CallLoweringInfo &CLI,
223                    SmallVectorImpl<SDValue> &InVals) const override;
224
225  std::string getPrototype(Type *, const ArgListTy &,
226                           const SmallVectorImpl<ISD::OutputArg> &,
227                           unsigned retAlignment,
228                           const ImmutableCallSite *CS) const;
229
230  SDValue
231  LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
232              const SmallVectorImpl<ISD::OutputArg> &Outs,
233              const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
234              SelectionDAG &DAG) const override;
235
236  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
237                                    std::vector<SDValue> &Ops,
238                                    SelectionDAG &DAG) const override;
239
240  NVPTXTargetMachine *nvTM;
241
242  // PTX always uses 32-bit shift amounts
243  MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
244
245  TargetLoweringBase::LegalizeTypeAction
246  getPreferredVectorAction(EVT VT) const override;
247
248private:
249  const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
250
251  SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
252                     EVT = MVT::i32) const;
253  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
254  SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
255
256  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
257
258  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
259  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
260
261  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
262  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
263  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
264
265  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
266  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
267
268  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
269                          SelectionDAG &DAG) const override;
270  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
271
272  unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
273                                Type *Ty, unsigned Idx) const;
274};
275} // namespace llvm
276
277#endif // NVPTXISELLOWERING_H
278