| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 4d748eb0e4b55262619305c96a89c55c30bffe6c |
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15-Nov-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Fix handling of indirect calls
Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 1fd09172bba8539e198db0360ac66f4694b4a3e0 |
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01-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] We dont use NVBuiltin anymore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| ef0ccc93203e99077632cec7a0a15b8e1b704aee |
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28-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns
Test case is no breakage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 1c07dae9fcd04469779edf7b86fef37fecc9466c |
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28-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 00df1252286eb71b093d8e45eb4c9cee4ca5761d |
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28-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Add infrastructure for vector loads/stores of parameters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 5df8c1bbb66a6b7386c9d7866592ecbb646da66c |
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25-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Default pointer type doesn't make sense for getParamSymbol()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
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22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
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25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
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18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 3639ce2575660a0e6938d2e84e8bd9a738fd7051 |
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30-Mar-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
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01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 7eacad03efda36e09ebd96e95d7891cadaaa9087 |
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12-Feb-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend. Instead,
let the target-independent code do all of the work. The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 3d200255d5b93344c1ab0a5ba4b47a52cfa5893e |
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29-Nov-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Allow targets to prefer TypeSplitVector over TypePromoteInteger when computing the legalization method for vectors
For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| a20067b5d4ea718a3f0e47adae8b231e4a2db9f6 |
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14-Nov-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Implement custom lowering of loads/stores for i1
Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8
Fixes PR13291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
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25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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| 49683f3c961379fbc088871a5d6304950f1f1cbc |
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04-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:
nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX
The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
|