NVPTXISelLowering.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that NVPTX uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef NVPTXISELLOWERING_H
16#define NVPTXISELLOWERING_H
17
18#include "NVPTX.h"
19#include "NVPTXSubtarget.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24namespace NVPTXISD {
25enum NodeType {
26  // Start the numbering from where ISD NodeType finishes.
27  FIRST_NUMBER = ISD::BUILTIN_OP_END,
28  Wrapper,
29  CALL,
30  RET_FLAG,
31  LOAD_PARAM,
32  DeclareParam,
33  DeclareScalarParam,
34  DeclareRetParam,
35  DeclareRet,
36  DeclareScalarRet,
37  PrintCall,
38  PrintCallUni,
39  CallArgBegin,
40  CallArg,
41  LastCallArg,
42  CallArgEnd,
43  CallVoid,
44  CallVal,
45  CallSymbol,
46  Prototype,
47  MoveParam,
48  PseudoUseParam,
49  RETURN,
50  CallSeqBegin,
51  CallSeqEnd,
52  CallPrototype,
53  Dummy,
54
55  LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
56  LoadV4,
57  LDGV2, // LDG.v2
58  LDGV4, // LDG.v4
59  LDUV2, // LDU.v2
60  LDUV4, // LDU.v4
61  StoreV2,
62  StoreV4,
63  LoadParam,
64  LoadParamV2,
65  LoadParamV4,
66  StoreParam,
67  StoreParamV2,
68  StoreParamV4,
69  StoreParamS32, // to sext and store a <32bit value, not used currently
70  StoreParamU32, // to zext and store a <32bit value, not used currently
71  StoreRetval,
72  StoreRetvalV2,
73  StoreRetvalV4,
74
75  // Texture intrinsics
76  Tex1DFloatI32,
77  Tex1DFloatFloat,
78  Tex1DFloatFloatLevel,
79  Tex1DFloatFloatGrad,
80  Tex1DI32I32,
81  Tex1DI32Float,
82  Tex1DI32FloatLevel,
83  Tex1DI32FloatGrad,
84  Tex1DArrayFloatI32,
85  Tex1DArrayFloatFloat,
86  Tex1DArrayFloatFloatLevel,
87  Tex1DArrayFloatFloatGrad,
88  Tex1DArrayI32I32,
89  Tex1DArrayI32Float,
90  Tex1DArrayI32FloatLevel,
91  Tex1DArrayI32FloatGrad,
92  Tex2DFloatI32,
93  Tex2DFloatFloat,
94  Tex2DFloatFloatLevel,
95  Tex2DFloatFloatGrad,
96  Tex2DI32I32,
97  Tex2DI32Float,
98  Tex2DI32FloatLevel,
99  Tex2DI32FloatGrad,
100  Tex2DArrayFloatI32,
101  Tex2DArrayFloatFloat,
102  Tex2DArrayFloatFloatLevel,
103  Tex2DArrayFloatFloatGrad,
104  Tex2DArrayI32I32,
105  Tex2DArrayI32Float,
106  Tex2DArrayI32FloatLevel,
107  Tex2DArrayI32FloatGrad,
108  Tex3DFloatI32,
109  Tex3DFloatFloat,
110  Tex3DFloatFloatLevel,
111  Tex3DFloatFloatGrad,
112  Tex3DI32I32,
113  Tex3DI32Float,
114  Tex3DI32FloatLevel,
115  Tex3DI32FloatGrad,
116
117  // Surface intrinsics
118  Suld1DI8Trap,
119  Suld1DI16Trap,
120  Suld1DI32Trap,
121  Suld1DV2I8Trap,
122  Suld1DV2I16Trap,
123  Suld1DV2I32Trap,
124  Suld1DV4I8Trap,
125  Suld1DV4I16Trap,
126  Suld1DV4I32Trap,
127
128  Suld1DArrayI8Trap,
129  Suld1DArrayI16Trap,
130  Suld1DArrayI32Trap,
131  Suld1DArrayV2I8Trap,
132  Suld1DArrayV2I16Trap,
133  Suld1DArrayV2I32Trap,
134  Suld1DArrayV4I8Trap,
135  Suld1DArrayV4I16Trap,
136  Suld1DArrayV4I32Trap,
137
138  Suld2DI8Trap,
139  Suld2DI16Trap,
140  Suld2DI32Trap,
141  Suld2DV2I8Trap,
142  Suld2DV2I16Trap,
143  Suld2DV2I32Trap,
144  Suld2DV4I8Trap,
145  Suld2DV4I16Trap,
146  Suld2DV4I32Trap,
147
148  Suld2DArrayI8Trap,
149  Suld2DArrayI16Trap,
150  Suld2DArrayI32Trap,
151  Suld2DArrayV2I8Trap,
152  Suld2DArrayV2I16Trap,
153  Suld2DArrayV2I32Trap,
154  Suld2DArrayV4I8Trap,
155  Suld2DArrayV4I16Trap,
156  Suld2DArrayV4I32Trap,
157
158  Suld3DI8Trap,
159  Suld3DI16Trap,
160  Suld3DI32Trap,
161  Suld3DV2I8Trap,
162  Suld3DV2I16Trap,
163  Suld3DV2I32Trap,
164  Suld3DV4I8Trap,
165  Suld3DV4I16Trap,
166  Suld3DV4I32Trap
167};
168}
169
170//===--------------------------------------------------------------------===//
171// TargetLowering Implementation
172//===--------------------------------------------------------------------===//
173class NVPTXTargetLowering : public TargetLowering {
174public:
175  explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
176  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
177
178  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
179  SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
180                             SelectionDAG &DAG) const;
181
182  const char *getTargetNodeName(unsigned Opcode) const override;
183
184  bool isTypeSupportedInIntrinsic(MVT VT) const;
185
186  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
187                          unsigned Intrinsic) const override;
188
189  /// isLegalAddressingMode - Return true if the addressing mode represented
190  /// by AM is legal for this target, for a load/store of the specified type
191  /// Used to guide target specific optimizations, like loop strength
192  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
193  /// address mode (CodeGenPrepare.cpp)
194  bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
195
196  /// getFunctionAlignment - Return the Log2 alignment of this function.
197  unsigned getFunctionAlignment(const Function *F) const;
198
199  EVT getSetCCResultType(LLVMContext &, EVT VT) const override {
200    if (VT.isVector())
201      return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
202    return MVT::i1;
203  }
204
205  ConstraintType
206  getConstraintType(const std::string &Constraint) const override;
207  std::pair<unsigned, const TargetRegisterClass *>
208  getRegForInlineAsmConstraint(const std::string &Constraint,
209                               MVT VT) const override;
210
211  SDValue LowerFormalArguments(
212      SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
213      const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
214      SmallVectorImpl<SDValue> &InVals) const override;
215
216  SDValue LowerCall(CallLoweringInfo &CLI,
217                    SmallVectorImpl<SDValue> &InVals) const override;
218
219  std::string getPrototype(Type *, const ArgListTy &,
220                           const SmallVectorImpl<ISD::OutputArg> &,
221                           unsigned retAlignment,
222                           const ImmutableCallSite *CS) const;
223
224  SDValue
225  LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
226              const SmallVectorImpl<ISD::OutputArg> &Outs,
227              const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
228              SelectionDAG &DAG) const override;
229
230  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
231                                    std::vector<SDValue> &Ops,
232                                    SelectionDAG &DAG) const override;
233
234  NVPTXTargetMachine *nvTM;
235
236  // PTX always uses 32-bit shift amounts
237  MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
238
239  bool shouldSplitVectorType(EVT VT) const override;
240
241private:
242  const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
243
244  SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
245                     EVT = MVT::i32) const;
246  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
247  SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
248
249  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
250
251  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
252  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
253
254  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
255  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
256  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
257
258  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
259                          SelectionDAG &DAG) const override;
260
261  unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
262                                Type *Ty, unsigned Idx) const;
263};
264} // namespace llvm
265
266#endif // NVPTXISELLOWERING_H
267