PPCRegisterInfo.cpp revision 0e6a052331f674dd70e28af41f654a7874405eab 
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "reginfo"
16#include "PPC.h"
17#include "PPCInstrBuilder.h"
18#include "PPCMachineFunctionInfo.h"
19#include "PPCRegisterInfo.h"
20#include "PPCFrameLowering.h"
21#include "PPCSubtarget.h"
22#include "llvm/CallingConv.h"
23#include "llvm/Constants.h"
24#include "llvm/Function.h"
25#include "llvm/Type.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineLocation.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/RegisterScavenging.h"
34#include "llvm/Target/TargetFrameLowering.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/MathExtras.h"
42#include "llvm/Support/raw_ostream.h"
43#include "llvm/ADT/BitVector.h"
44#include "llvm/ADT/STLExtras.h"
45#include <cstdlib>
46
47#define GET_REGINFO_TARGET_DESC
48#include "PPCGenRegisterInfo.inc"
49
50// FIXME (64-bit): Eventually enable by default.
51namespace llvm {
52cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
53                                   cl::init(false),
54                                   cl::desc("Enable PPC32 register scavenger"),
55                                   cl::Hidden);
56cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
57                                   cl::init(false),
58                                   cl::desc("Enable PPC64 register scavenger"),
59                                   cl::Hidden);
60}
61
62using namespace llvm;
63
64// FIXME (64-bit): Should be inlined.
65bool
66PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
67  return ((EnablePPC32RS && !Subtarget.isPPC64()) ||
68          (EnablePPC64RS && Subtarget.isPPC64()));
69}
70
71/// getRegisterNumbering - Given the enum value for some register, e.g.
72/// PPC::F14, return the number that it corresponds to (e.g. 14).
73unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
74  using namespace PPC;
75  switch (RegEnum) {
76  case 0: return 0;
77  case R0 :  case X0 :  case F0 :  case V0 : case CR0:  case CR0LT: return  0;
78  case R1 :  case X1 :  case F1 :  case V1 : case CR1:  case CR0GT: return  1;
79  case R2 :  case X2 :  case F2 :  case V2 : case CR2:  case CR0EQ: return  2;
80  case R3 :  case X3 :  case F3 :  case V3 : case CR3:  case CR0UN: return  3;
81  case R4 :  case X4 :  case F4 :  case V4 : case CR4:  case CR1LT: return  4;
82  case R5 :  case X5 :  case F5 :  case V5 : case CR5:  case CR1GT: return  5;
83  case R6 :  case X6 :  case F6 :  case V6 : case CR6:  case CR1EQ: return  6;
84  case R7 :  case X7 :  case F7 :  case V7 : case CR7:  case CR1UN: return  7;
85  case R8 :  case X8 :  case F8 :  case V8 : case CR2LT: return  8;
86  case R9 :  case X9 :  case F9 :  case V9 : case CR2GT: return  9;
87  case R10:  case X10:  case F10:  case V10: case CR2EQ: return 10;
88  case R11:  case X11:  case F11:  case V11: case CR2UN: return 11;
89  case R12:  case X12:  case F12:  case V12: case CR3LT: return 12;
90  case R13:  case X13:  case F13:  case V13: case CR3GT: return 13;
91  case R14:  case X14:  case F14:  case V14: case CR3EQ: return 14;
92  case R15:  case X15:  case F15:  case V15: case CR3UN: return 15;
93  case R16:  case X16:  case F16:  case V16: case CR4LT: return 16;
94  case R17:  case X17:  case F17:  case V17: case CR4GT: return 17;
95  case R18:  case X18:  case F18:  case V18: case CR4EQ: return 18;
96  case R19:  case X19:  case F19:  case V19: case CR4UN: return 19;
97  case R20:  case X20:  case F20:  case V20: case CR5LT: return 20;
98  case R21:  case X21:  case F21:  case V21: case CR5GT: return 21;
99  case R22:  case X22:  case F22:  case V22: case CR5EQ: return 22;
100  case R23:  case X23:  case F23:  case V23: case CR5UN: return 23;
101  case R24:  case X24:  case F24:  case V24: case CR6LT: return 24;
102  case R25:  case X25:  case F25:  case V25: case CR6GT: return 25;
103  case R26:  case X26:  case F26:  case V26: case CR6EQ: return 26;
104  case R27:  case X27:  case F27:  case V27: case CR6UN: return 27;
105  case R28:  case X28:  case F28:  case V28: case CR7LT: return 28;
106  case R29:  case X29:  case F29:  case V29: case CR7GT: return 29;
107  case R30:  case X30:  case F30:  case V30: case CR7EQ: return 30;
108  case R31:  case X31:  case F31:  case V31: case CR7UN: return 31;
109  default:
110    llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
111  }
112}
113
114PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
115                                 const TargetInstrInfo &tii)
116  : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
117                       ST.isPPC64() ? 0 : 1,
118                       ST.isPPC64() ? 0 : 1),
119    Subtarget(ST), TII(tii) {
120  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
121  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
122  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
123  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
124  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
125  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
126  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
127  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
128
129  // 64-bit
130  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
131  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
132  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
133  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
134  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
135}
136
137/// getPointerRegClass - Return the register class to use to hold pointers.
138/// This is used for addressing modes.
139const TargetRegisterClass *
140PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
141  if (Subtarget.isPPC64())
142    return &PPC::G8RCRegClass;
143  return &PPC::GPRCRegClass;
144}
145
146const unsigned*
147PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148  // 32-bit Darwin calling convention.
149  static const unsigned Darwin32_CalleeSavedRegs[] = {
150              PPC::R13, PPC::R14, PPC::R15,
151    PPC::R16, PPC::R17, PPC::R18, PPC::R19,
152    PPC::R20, PPC::R21, PPC::R22, PPC::R23,
153    PPC::R24, PPC::R25, PPC::R26, PPC::R27,
154    PPC::R28, PPC::R29, PPC::R30, PPC::R31,
155
156    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
157    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
158    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
159    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
160    PPC::F30, PPC::F31,
161
162    PPC::CR2, PPC::CR3, PPC::CR4,
163    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
164    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
165    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
166
167    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
168    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
169    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
170
171    PPC::LR,  0
172  };
173
174  // 32-bit SVR4 calling convention.
175  static const unsigned SVR4_CalleeSavedRegs[] = {
176                        PPC::R14, PPC::R15,
177    PPC::R16, PPC::R17, PPC::R18, PPC::R19,
178    PPC::R20, PPC::R21, PPC::R22, PPC::R23,
179    PPC::R24, PPC::R25, PPC::R26, PPC::R27,
180    PPC::R28, PPC::R29, PPC::R30, PPC::R31,
181
182    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
183    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
184    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
185    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
186    PPC::F30, PPC::F31,
187
188    PPC::CR2, PPC::CR3, PPC::CR4,
189
190    PPC::VRSAVE,
191
192    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
193    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
194    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
195
196    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
197    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
198    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
199
200    0
201  };
202  // 64-bit Darwin calling convention.
203  static const unsigned Darwin64_CalleeSavedRegs[] = {
204    PPC::X14, PPC::X15,
205    PPC::X16, PPC::X17, PPC::X18, PPC::X19,
206    PPC::X20, PPC::X21, PPC::X22, PPC::X23,
207    PPC::X24, PPC::X25, PPC::X26, PPC::X27,
208    PPC::X28, PPC::X29, PPC::X30, PPC::X31,
209
210    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
211    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
212    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
213    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
214    PPC::F30, PPC::F31,
215
216    PPC::CR2, PPC::CR3, PPC::CR4,
217    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
218    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
219    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
220
221    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
222    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
223    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
224
225    PPC::LR8,  0
226  };
227
228  // 64-bit SVR4 calling convention.
229  static const unsigned SVR4_64_CalleeSavedRegs[] = {
230    PPC::X14, PPC::X15,
231    PPC::X16, PPC::X17, PPC::X18, PPC::X19,
232    PPC::X20, PPC::X21, PPC::X22, PPC::X23,
233    PPC::X24, PPC::X25, PPC::X26, PPC::X27,
234    PPC::X28, PPC::X29, PPC::X30, PPC::X31,
235
236    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
237    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
238    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
239    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
240    PPC::F30, PPC::F31,
241
242    PPC::CR2, PPC::CR3, PPC::CR4,
243
244    PPC::VRSAVE,
245
246    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
247    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
248    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
249
250    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
251    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
252    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
253
254    0
255  };
256
257  if (Subtarget.isDarwinABI())
258    return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
259                                 Darwin32_CalleeSavedRegs;
260
261  return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
262}
263
264BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
265  BitVector Reserved(getNumRegs());
266  const PPCFrameLowering *PPCFI =
267    static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
268
269  Reserved.set(PPC::R0);
270  Reserved.set(PPC::R1);
271  Reserved.set(PPC::LR);
272  Reserved.set(PPC::LR8);
273  Reserved.set(PPC::RM);
274
275  // The SVR4 ABI reserves r2 and r13
276  if (Subtarget.isSVR4ABI()) {
277    Reserved.set(PPC::R2);  // System-reserved register
278    Reserved.set(PPC::R13); // Small Data Area pointer register
279  }
280  // Reserve R2 on Darwin to hack around the problem of save/restore of CR
281  // when the stack frame is too big to address directly; we need two regs.
282  // This is a hack.
283  if (Subtarget.isDarwinABI()) {
284    Reserved.set(PPC::R2);
285  }
286
287  // On PPC64, r13 is the thread pointer. Never allocate this register.
288  // Note that this is over conservative, as it also prevents allocation of R31
289  // when the FP is not needed.
290  if (Subtarget.isPPC64()) {
291    Reserved.set(PPC::R13);
292    Reserved.set(PPC::R31);
293
294    if (!requiresRegisterScavenging(MF))
295      Reserved.set(PPC::R0);    // FIXME (64-bit): Remove
296
297    Reserved.set(PPC::X0);
298    Reserved.set(PPC::X1);
299    Reserved.set(PPC::X13);
300    Reserved.set(PPC::X31);
301
302    // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
303    if (Subtarget.isSVR4ABI()) {
304      Reserved.set(PPC::X2);
305    }
306    // Reserve R2 on Darwin to hack around the problem of save/restore of CR
307    // when the stack frame is too big to address directly; we need two regs.
308    // This is a hack.
309    if (Subtarget.isDarwinABI()) {
310      Reserved.set(PPC::X2);
311    }
312  }
313
314  if (PPCFI->needsFP(MF))
315    Reserved.set(PPC::R31);
316
317  return Reserved;
318}
319
320//===----------------------------------------------------------------------===//
321// Stack Frame Processing methods
322//===----------------------------------------------------------------------===//
323
324void PPCRegisterInfo::
325eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
326                              MachineBasicBlock::iterator I) const {
327  if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
328    // Add (actually subtract) back the amount the callee popped on return.
329    if (int CalleeAmt =  I->getOperand(1).getImm()) {
330      bool is64Bit = Subtarget.isPPC64();
331      CalleeAmt *= -1;
332      unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
333      unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
334      unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
335      unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
336      unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
337      unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
338      MachineInstr *MI = I;
339      DebugLoc dl = MI->getDebugLoc();
340
341      if (isInt<16>(CalleeAmt)) {
342        BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
343          addImm(CalleeAmt);
344      } else {
345        MachineBasicBlock::iterator MBBI = I;
346        BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
347          .addImm(CalleeAmt >> 16);
348        BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
349          .addReg(TmpReg, RegState::Kill)
350          .addImm(CalleeAmt & 0xFFFF);
351        BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
352          .addReg(StackReg)
353          .addReg(StackReg)
354          .addReg(TmpReg);
355      }
356    }
357  }
358  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
359  MBB.erase(I);
360}
361
362/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
363/// register first and then a spilled callee-saved register if that fails.
364static
365unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
366                             const TargetRegisterClass *RC, int SPAdj) {
367  assert(RS && "Register scavenging must be on");
368  unsigned Reg = RS->FindUnusedReg(RC);
369  // FIXME: move ARM callee-saved reg scan to target independent code, then
370  // search for already spilled CS register here.
371  if (Reg == 0)
372    Reg = RS->scavengeRegister(RC, II, SPAdj);
373  return Reg;
374}
375
376/// lowerDynamicAlloc - Generate the code for allocating an object in the
377/// current frame.  The sequence of code with be in the general form
378///
379///   addi   R0, SP, \#frameSize ; get the address of the previous frame
380///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
381///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
382///
383void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
384                                        int SPAdj, RegScavenger *RS) const {
385  // Get the instruction.
386  MachineInstr &MI = *II;
387  // Get the instruction's basic block.
388  MachineBasicBlock &MBB = *MI.getParent();
389  // Get the basic block's function.
390  MachineFunction &MF = *MBB.getParent();
391  // Get the frame info.
392  MachineFrameInfo *MFI = MF.getFrameInfo();
393  // Determine whether 64-bit pointers are used.
394  bool LP64 = Subtarget.isPPC64();
395  DebugLoc dl = MI.getDebugLoc();
396
397  // Get the maximum call stack size.
398  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
399  // Get the total frame size.
400  unsigned FrameSize = MFI->getStackSize();
401
402  // Get stack alignments.
403  unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
404  unsigned MaxAlign = MFI->getMaxAlignment();
405  if (MaxAlign > TargetAlign)
406    report_fatal_error("Dynamic alloca with large aligns not supported");
407
408  // Determine the previous frame's address.  If FrameSize can't be
409  // represented as 16 bits or we need special alignment, then we load the
410  // previous frame's address from 0(SP).  Why not do an addis of the hi?
411  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
412  // Constructing the constant and adding would take 3 instructions.
413  // Fortunately, a frame greater than 32K is rare.
414  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
415  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
416  const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
417
418  // FIXME (64-bit): Use "findScratchRegister"
419  unsigned Reg;
420  if (requiresRegisterScavenging(MF))
421    Reg = findScratchRegister(II, RS, RC, SPAdj);
422  else
423    Reg = PPC::R0;
424
425  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
426    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
427      .addReg(PPC::R31)
428      .addImm(FrameSize);
429  } else if (LP64) {
430    if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
431      BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
432        .addImm(0)
433        .addReg(PPC::X1);
434    else
435      BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
436        .addImm(0)
437        .addReg(PPC::X1);
438  } else {
439    BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
440      .addImm(0)
441      .addReg(PPC::R1);
442  }
443
444  // Grow the stack and update the stack pointer link, then determine the
445  // address of new allocated space.
446  if (LP64) {
447    if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
448      BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
449        .addReg(Reg, RegState::Kill)
450        .addReg(PPC::X1)
451        .addReg(MI.getOperand(1).getReg());
452    else
453      BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
454        .addReg(PPC::X0, RegState::Kill)
455        .addReg(PPC::X1)
456        .addReg(MI.getOperand(1).getReg());
457
458    if (!MI.getOperand(1).isKill())
459      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
460        .addReg(PPC::X1)
461        .addImm(maxCallFrameSize);
462    else
463      // Implicitly kill the register.
464      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
465        .addReg(PPC::X1)
466        .addImm(maxCallFrameSize)
467        .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
468  } else {
469    BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
470      .addReg(Reg, RegState::Kill)
471      .addReg(PPC::R1)
472      .addReg(MI.getOperand(1).getReg());
473
474    if (!MI.getOperand(1).isKill())
475      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
476        .addReg(PPC::R1)
477        .addImm(maxCallFrameSize);
478    else
479      // Implicitly kill the register.
480      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
481        .addReg(PPC::R1)
482        .addImm(maxCallFrameSize)
483        .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
484  }
485
486  // Discard the DYNALLOC instruction.
487  MBB.erase(II);
488}
489
490/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
491/// reserving a whole register (R0), we scrounge for one here. This generates
492/// code like this:
493///
494///   mfcr rA                  ; Move the conditional register into GPR rA.
495///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
496///   stw rA, FI               ; Store rA to the frame.
497///
498void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
499                                      unsigned FrameIndex, int SPAdj,
500                                      RegScavenger *RS) const {
501  // Get the instruction.
502  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>, <FI>
503  // Get the instruction's basic block.
504  MachineBasicBlock &MBB = *MI.getParent();
505  DebugLoc dl = MI.getDebugLoc();
506
507  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
508  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
509  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
510  unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
511  unsigned SrcReg = MI.getOperand(0).getReg();
512  bool LP64 = Subtarget.isPPC64();
513
514  // We need to store the CR in the low 4-bits of the saved value. First, issue
515  // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
516  BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg)
517          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
518
519  // If the saved register wasn't CR0, shift the bits left so that they are in
520  // CR0's slot.
521  if (SrcReg != PPC::CR0)
522    // rlwinm rA, rA, ShiftBits, 0, 31.
523    BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
524      .addReg(Reg, RegState::Kill)
525      .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
526      .addImm(0)
527      .addImm(31);
528
529  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
530                    .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
531                    FrameIndex);
532
533  // Discard the pseudo instruction.
534  MBB.erase(II);
535}
536
537void
538PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
539                                     int SPAdj, RegScavenger *RS) const {
540  assert(SPAdj == 0 && "Unexpected");
541
542  // Get the instruction.
543  MachineInstr &MI = *II;
544  // Get the instruction's basic block.
545  MachineBasicBlock &MBB = *MI.getParent();
546  // Get the basic block's function.
547  MachineFunction &MF = *MBB.getParent();
548  // Get the frame info.
549  MachineFrameInfo *MFI = MF.getFrameInfo();
550  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
551  DebugLoc dl = MI.getDebugLoc();
552
553  // Find out which operand is the frame index.
554  unsigned FIOperandNo = 0;
555  while (!MI.getOperand(FIOperandNo).isFI()) {
556    ++FIOperandNo;
557    assert(FIOperandNo != MI.getNumOperands() &&
558           "Instr doesn't have FrameIndex operand!");
559  }
560  // Take into account whether it's an add or mem instruction
561  unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
562  if (MI.isInlineAsm())
563    OffsetOperandNo = FIOperandNo-1;
564
565  // Get the frame index.
566  int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
567
568  // Get the frame pointer save index.  Users of this index are primarily
569  // DYNALLOC instructions.
570  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
571  int FPSI = FI->getFramePointerSaveIndex();
572  // Get the instruction opcode.
573  unsigned OpC = MI.getOpcode();
574
575  // Special case for dynamic alloca.
576  if (FPSI && FrameIndex == FPSI &&
577      (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
578    lowerDynamicAlloc(II, SPAdj, RS);
579    return;
580  }
581
582  // Special case for pseudo-op SPILL_CR.
583  if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default.
584    if (OpC == PPC::SPILL_CR) {
585      lowerCRSpilling(II, FrameIndex, SPAdj, RS);
586      return;
587    }
588
589  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
590  MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
591                                              PPC::R31 : PPC::R1,
592                                              false);
593
594  // Figure out if the offset in the instruction is shifted right two bits. This
595  // is true for instructions like "STD", which the machine implicitly adds two
596  // low zeros to.
597  bool isIXAddr = false;
598  switch (OpC) {
599  case PPC::LWA:
600  case PPC::LD:
601  case PPC::STD:
602  case PPC::STD_32:
603    isIXAddr = true;
604    break;
605  }
606
607  // Now add the frame object offset to the offset from r1.
608  int Offset = MFI->getObjectOffset(FrameIndex);
609  if (!isIXAddr)
610    Offset += MI.getOperand(OffsetOperandNo).getImm();
611  else
612    Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
613
614  // If we're not using a Frame Pointer that has been set to the value of the
615  // SP before having the stack size subtracted from it, then add the stack size
616  // to Offset to get the correct offset.
617  // Naked functions have stack size 0, although getStackSize may not reflect that
618  // because we didn't call all the pieces that compute it for naked functions.
619  if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
620    Offset += MFI->getStackSize();
621
622  // If we can, encode the offset directly into the instruction.  If this is a
623  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
624  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
625  // clear can be encoded.  This is extremely uncommon, because normally you
626  // only "std" to a stack slot that is at least 4-byte aligned, but it can
627  // happen in invalid code.
628  if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
629    if (isIXAddr)
630      Offset >>= 2;    // The actual encoded value has the low two bits zero.
631    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
632    return;
633  }
634
635  // The offset doesn't fit into a single register, scavenge one to build the
636  // offset in.
637  // FIXME: figure out what SPAdj is doing here.
638
639  // FIXME (64-bit): Use "findScratchRegister".
640  unsigned SReg;
641  if (requiresRegisterScavenging(MF))
642    SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
643  else
644    SReg = PPC::R0;
645
646  // Insert a set of rA with the full offset value before the ld, st, or add
647  BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
648    .addImm(Offset >> 16);
649  BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
650    .addReg(SReg, RegState::Kill)
651    .addImm(Offset);
652
653  // Convert into indexed form of the instruction:
654  //
655  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
656  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
657  unsigned OperandBase;
658
659  if (OpC != TargetOpcode::INLINEASM) {
660    assert(ImmToIdxMap.count(OpC) &&
661           "No indexed form of load or store available!");
662    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
663    MI.setDesc(TII.get(NewOpcode));
664    OperandBase = 1;
665  } else {
666    OperandBase = OffsetOperandNo;
667  }
668
669  unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
670  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
671  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
672}
673
674unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
675  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
676
677  if (!Subtarget.isPPC64())
678    return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
679  else
680    return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
681}
682
683unsigned PPCRegisterInfo::getEHExceptionRegister() const {
684  return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
685}
686
687unsigned PPCRegisterInfo::getEHHandlerRegister() const {
688  return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
689}
690