PPCRegisterInfo.cpp revision 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "reginfo"
15#include "PPC.h"
16#include "PPCInstrBuilder.h"
17#include "PPCRegisterInfo.h"
18#include "llvm/Constants.h"
19#include "llvm/Type.h"
20#include "llvm/CodeGen/ValueTypes.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/Target/TargetFrameInfo.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/ADT/STLExtras.h"
30#include <cstdlib>
31#include <iostream>
32using namespace llvm;
33
34PPCRegisterInfo::PPCRegisterInfo()
35  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
36  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
37  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
38  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
39  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
40  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
41  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
42  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
43  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
44}
45
46void
47PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
48                                     MachineBasicBlock::iterator MI,
49                                     unsigned SrcReg, int FrameIdx,
50                                     const TargetRegisterClass *RC) const {
51  if (SrcReg == PPC::LR) {
52    BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
53    addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
54  } else if (RC == PPC::CRRCRegisterClass) {
55    BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
56    addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
57  } else if (RC == PPC::GPRCRegisterClass) {
58    addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
59  } else if (RC == PPC::G8RCRegisterClass) {
60    addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
61  } else if (RC == PPC::F8RCRegisterClass) {
62    addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
63  } else if (RC == PPC::F4RCRegisterClass) {
64    addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
65  } else {
66    assert(0 && "Unknown regclass!");
67    abort();
68  }
69}
70
71void
72PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
73                                        MachineBasicBlock::iterator MI,
74                                        unsigned DestReg, int FrameIdx,
75                                        const TargetRegisterClass *RC) const {
76  if (DestReg == PPC::LR) {
77    addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
78    BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
79  } else if (RC == PPC::CRRCRegisterClass) {
80    addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
81    BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
82  } else if (RC == PPC::GPRCRegisterClass) {
83    addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
84  } else if (RC == PPC::G8RCRegisterClass) {
85    addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
86  } else if (RC == PPC::F8RCRegisterClass) {
87    addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
88  } else if (RC == PPC::F4RCRegisterClass) {
89    addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
90  } else {
91    assert(0 && "Unknown regclass!");
92    abort();
93  }
94}
95
96void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
97                                   MachineBasicBlock::iterator MI,
98                                   unsigned DestReg, unsigned SrcReg,
99                                   const TargetRegisterClass *RC) const {
100  MachineInstr *I;
101
102  if (RC == PPC::GPRCRegisterClass) {
103    BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
104  } else if (RC == PPC::G8RCRegisterClass) {
105    BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
106  } else if (RC == PPC::F4RCRegisterClass) {
107    BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
108  } else if (RC == PPC::F8RCRegisterClass) {
109    BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
110  } else if (RC == PPC::CRRCRegisterClass) {
111    BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
112  } else {
113    std::cerr << "Attempt to copy register that is not GPR or FPR";
114    abort();
115  }
116}
117
118unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
119                                              int &FrameIndex) const {
120  switch (MI->getOpcode()) {
121  default: break;
122  case PPC::LD:
123  case PPC::LWZ:
124  case PPC::LFS:
125  case PPC::LFD:
126    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
127        MI->getOperand(2).isFrameIndex()) {
128      FrameIndex = MI->getOperand(2).getFrameIndex();
129      return MI->getOperand(0).getReg();
130    }
131    break;
132  }
133  return 0;
134}
135
136/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
137/// copy instructions, turning them into load/store instructions.
138MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
139                                                 unsigned OpNum,
140                                                 int FrameIndex) const {
141  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
142  // it takes more than one instruction to store it.
143  unsigned Opc = MI->getOpcode();
144
145  if ((Opc == PPC::OR4 &&
146       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
147    if (OpNum == 0) {  // move -> store
148      unsigned InReg = MI->getOperand(1).getReg();
149      return addFrameReference(BuildMI(PPC::STW,
150                                       3).addReg(InReg), FrameIndex);
151    } else {           // move -> load
152      unsigned OutReg = MI->getOperand(0).getReg();
153      return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
154    }
155  } else if ((Opc == PPC::OR8 &&
156              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
157    if (OpNum == 0) {  // move -> store
158      unsigned InReg = MI->getOperand(1).getReg();
159      return addFrameReference(BuildMI(PPC::STD,
160                                       3).addReg(InReg), FrameIndex);
161    } else {           // move -> load
162      unsigned OutReg = MI->getOperand(0).getReg();
163      return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
164    }
165  } else if (Opc == PPC::FMRD) {
166    if (OpNum == 0) {  // move -> store
167      unsigned InReg = MI->getOperand(1).getReg();
168      return addFrameReference(BuildMI(PPC::STFD,
169                                       3).addReg(InReg), FrameIndex);
170    } else {           // move -> load
171      unsigned OutReg = MI->getOperand(0).getReg();
172      return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
173    }
174  } else if (Opc == PPC::FMRS) {
175    if (OpNum == 0) {  // move -> store
176      unsigned InReg = MI->getOperand(1).getReg();
177      return addFrameReference(BuildMI(PPC::STFS,
178                                       3).addReg(InReg), FrameIndex);
179    } else {           // move -> load
180      unsigned OutReg = MI->getOperand(0).getReg();
181      return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
182    }
183  }
184  return 0;
185}
186
187//===----------------------------------------------------------------------===//
188// Stack Frame Processing methods
189//===----------------------------------------------------------------------===//
190
191// hasFP - Return true if the specified function should have a dedicated frame
192// pointer register.  This is true if the function has variable sized allocas or
193// if frame pointer elimination is disabled.
194//
195static bool hasFP(MachineFunction &MF) {
196  return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
197}
198
199void PPCRegisterInfo::
200eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
201                              MachineBasicBlock::iterator I) const {
202  if (hasFP(MF)) {
203    // If we have a frame pointer, convert as follows:
204    // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
205    // ADJCALLSTACKUP   -> addi, r1, r1, amount
206    MachineInstr *Old = I;
207    unsigned Amount = Old->getOperand(0).getImmedValue();
208    if (Amount != 0) {
209      // We need to keep the stack aligned properly.  To do this, we round the
210      // amount of space needed for the outgoing arguments up to the next
211      // alignment boundary.
212      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
213      Amount = (Amount+Align-1)/Align*Align;
214
215      // Replace the pseudo instruction with a new instruction...
216      if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
217        MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
218                .addSImm(-Amount));
219      } else {
220        assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
221        MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
222                .addSImm(Amount));
223      }
224    }
225  }
226  MBB.erase(I);
227}
228
229void
230PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
231  unsigned i = 0;
232  MachineInstr &MI = *II;
233  MachineBasicBlock &MBB = *MI.getParent();
234  MachineFunction &MF = *MBB.getParent();
235
236  while (!MI.getOperand(i).isFrameIndex()) {
237    ++i;
238    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
239  }
240
241  int FrameIndex = MI.getOperand(i).getFrameIndex();
242
243  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
244  MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
245
246  // Take into account whether it's an add or mem instruction
247  unsigned OffIdx = (i == 2) ? 1 : 2;
248
249  // Now add the frame object offset to the offset from r1.
250  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
251               MI.getOperand(OffIdx).getImmedValue();
252
253  // If we're not using a Frame Pointer that has been set to the value of the
254  // SP before having the stack size subtracted from it, then add the stack size
255  // to Offset to get the correct offset.
256  Offset += MF.getFrameInfo()->getStackSize();
257
258  if (Offset > 32767 || Offset < -32768) {
259    // Insert a set of r0 with the full offset value before the ld, st, or add
260    MachineBasicBlock *MBB = MI.getParent();
261    MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
262    MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
263      .addImm(Offset));
264    // convert into indexed form of the instruction
265    // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
266    // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
267    assert(ImmToIdxMap.count(MI.getOpcode()) &&
268           "No indexed form of load or store available!");
269    unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
270    MI.setOpcode(NewOpcode);
271    MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
272    MI.SetMachineOperandReg(2, PPC::R0);
273  } else {
274    MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
275                              Offset);
276  }
277}
278
279
280void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
281  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
282  MachineBasicBlock::iterator MBBI = MBB.begin();
283  MachineFrameInfo *MFI = MF.getFrameInfo();
284  MachineInstr *MI;
285
286  // Get the number of bytes to allocate from the FrameInfo
287  unsigned NumBytes = MFI->getStackSize();
288
289  // If we have calls, we cannot use the red zone to store callee save registers
290  // and we must set up a stack frame, so calculate the necessary size here.
291  if (MFI->hasCalls()) {
292    // We reserve argument space for call sites in the function immediately on
293    // entry to the current function.  This eliminates the need for add/sub
294    // brackets around call sites.
295    NumBytes += MFI->getMaxCallFrameSize();
296  }
297
298  // If we are a leaf function, and use up to 224 bytes of stack space,
299  // and don't have a frame pointer, then we do not need to adjust the stack
300  // pointer (we fit in the Red Zone).
301  if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) {
302    MFI->setStackSize(0);
303    return;
304  }
305
306  // Add the size of R1 to  NumBytes size for the store of R1 to the bottom
307  // of the stack and round the size to a multiple of the alignment.
308  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
309  unsigned GPRSize = 4;
310  unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
311  NumBytes = (NumBytes+Size+Align-1)/Align*Align;
312
313  // Update frame info to pretend that this is part of the stack...
314  MFI->setStackSize(NumBytes);
315
316  // Adjust stack pointer: r1 -= numbytes.
317  if (NumBytes <= 32768) {
318    MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
319    MBB.insert(MBBI, MI);
320  } else {
321    int NegNumbytes = -NumBytes;
322    MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
323    MBB.insert(MBBI, MI);
324    MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
325      .addImm(NegNumbytes & 0xFFFF);
326    MBB.insert(MBBI, MI);
327    MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
328    MBB.insert(MBBI, MI);
329  }
330
331  if (hasFP(MF)) {
332    MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
333    MBB.insert(MBBI, MI);
334    MI = BuildMI(PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
335    MBB.insert(MBBI, MI);
336  }
337}
338
339void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
340                                   MachineBasicBlock &MBB) const {
341  const MachineFrameInfo *MFI = MF.getFrameInfo();
342  MachineBasicBlock::iterator MBBI = prior(MBB.end());
343  MachineInstr *MI;
344  assert(MBBI->getOpcode() == PPC::BLR &&
345         "Can only insert epilog into returning blocks");
346
347  // Get the number of bytes allocated from the FrameInfo...
348  unsigned NumBytes = MFI->getStackSize();
349  unsigned GPRSize = 4;
350
351  if (NumBytes != 0) {
352    if (hasFP(MF)) {
353      MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
354      MBB.insert(MBBI, MI);
355    }
356    MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
357    MBB.insert(MBBI, MI);
358  }
359}
360
361#include "PPCGenRegisterInfo.inc"
362
363