PPCRegisterInfo.cpp revision 7194aaf738a1b89441635340403f1c5b06ae18ef 
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "reginfo"
16#include "PPC.h"
17#include "PPCInstrBuilder.h"
18#include "PPCMachineFunctionInfo.h"
19#include "PPCRegisterInfo.h"
20#include "PPCFrameInfo.h"
21#include "PPCSubtarget.h"
22#include "llvm/Constants.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/CodeGen/SelectionDAGNodes.h"
33#include "llvm/Target/TargetFrameInfo.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/ADT/BitVector.h"
41#include "llvm/ADT/STLExtras.h"
42#include <cstdlib>
43using namespace llvm;
44
45// FIXME (64-bit): Should be inlined.
46bool
47PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
48  return !Subtarget.isPPC64();
49}
50
51/// getRegisterNumbering - Given the enum value for some register, e.g.
52/// PPC::F14, return the number that it corresponds to (e.g. 14).
53unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
54  using namespace PPC;
55  switch (RegEnum) {
56  case 0: return 0;
57  case R0 :  case X0 :  case F0 :  case V0 : case CR0:  return  0;
58  case R1 :  case X1 :  case F1 :  case V1 : case CR1:  return  1;
59  case R2 :  case X2 :  case F2 :  case V2 : case CR2:  return  2;
60  case R3 :  case X3 :  case F3 :  case V3 : case CR3:  return  3;
61  case R4 :  case X4 :  case F4 :  case V4 : case CR4:  return  4;
62  case R5 :  case X5 :  case F5 :  case V5 : case CR5:  return  5;
63  case R6 :  case X6 :  case F6 :  case V6 : case CR6:  return  6;
64  case R7 :  case X7 :  case F7 :  case V7 : case CR7:  return  7;
65  case R8 :  case X8 :  case F8 :  case V8 : return  8;
66  case R9 :  case X9 :  case F9 :  case V9 : return  9;
67  case R10:  case X10:  case F10:  case V10: return 10;
68  case R11:  case X11:  case F11:  case V11: return 11;
69  case R12:  case X12:  case F12:  case V12: return 12;
70  case R13:  case X13:  case F13:  case V13: return 13;
71  case R14:  case X14:  case F14:  case V14: return 14;
72  case R15:  case X15:  case F15:  case V15: return 15;
73  case R16:  case X16:  case F16:  case V16: return 16;
74  case R17:  case X17:  case F17:  case V17: return 17;
75  case R18:  case X18:  case F18:  case V18: return 18;
76  case R19:  case X19:  case F19:  case V19: return 19;
77  case R20:  case X20:  case F20:  case V20: return 20;
78  case R21:  case X21:  case F21:  case V21: return 21;
79  case R22:  case X22:  case F22:  case V22: return 22;
80  case R23:  case X23:  case F23:  case V23: return 23;
81  case R24:  case X24:  case F24:  case V24: return 24;
82  case R25:  case X25:  case F25:  case V25: return 25;
83  case R26:  case X26:  case F26:  case V26: return 26;
84  case R27:  case X27:  case F27:  case V27: return 27;
85  case R28:  case X28:  case F28:  case V28: return 28;
86  case R29:  case X29:  case F29:  case V29: return 29;
87  case R30:  case X30:  case F30:  case V30: return 30;
88  case R31:  case X31:  case F31:  case V31: return 31;
89  default:
90    cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
91    abort();
92  }
93}
94
95PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
96                                 const TargetInstrInfo &tii)
97  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
98    Subtarget(ST), TII(tii) {
99  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
100  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
101  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
102  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
103  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
104  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
105  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
106  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
107
108  // 64-bit
109  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
110  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
111  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
112  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
113  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
114}
115
116void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
117                                    MachineBasicBlock::iterator I,
118                                    unsigned DestReg,
119                                    const MachineInstr *Orig) const {
120  MachineInstr *MI = Orig->clone();
121  MI->getOperand(0).setReg(DestReg);
122  MBB.insert(I, MI);
123}
124
125const unsigned*
126PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
127  // 32-bit Darwin calling convention.
128  static const unsigned Macho32_CalleeSavedRegs[] = {
129              PPC::R13, PPC::R14, PPC::R15,
130    PPC::R16, PPC::R17, PPC::R18, PPC::R19,
131    PPC::R20, PPC::R21, PPC::R22, PPC::R23,
132    PPC::R24, PPC::R25, PPC::R26, PPC::R27,
133    PPC::R28, PPC::R29, PPC::R30, PPC::R31,
134
135    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
136    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
137    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
138    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
139    PPC::F30, PPC::F31,
140
141    PPC::CR2, PPC::CR3, PPC::CR4,
142    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
143    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
144    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
145
146    PPC::LR,  0
147  };
148
149  static const unsigned ELF32_CalleeSavedRegs[] = {
150              PPC::R13, PPC::R14, PPC::R15,
151    PPC::R16, PPC::R17, PPC::R18, PPC::R19,
152    PPC::R20, PPC::R21, PPC::R22, PPC::R23,
153    PPC::R24, PPC::R25, PPC::R26, PPC::R27,
154    PPC::R28, PPC::R29, PPC::R30, PPC::R31,
155
156                                  PPC::F9,
157    PPC::F10, PPC::F11, PPC::F12, PPC::F13,
158    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
159    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
160    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
161    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
162    PPC::F30, PPC::F31,
163
164    PPC::CR2, PPC::CR3, PPC::CR4,
165    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
166    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
167    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
168
169    PPC::LR,  0
170  };
171  // 64-bit Darwin calling convention.
172  static const unsigned Macho64_CalleeSavedRegs[] = {
173    PPC::X14, PPC::X15,
174    PPC::X16, PPC::X17, PPC::X18, PPC::X19,
175    PPC::X20, PPC::X21, PPC::X22, PPC::X23,
176    PPC::X24, PPC::X25, PPC::X26, PPC::X27,
177    PPC::X28, PPC::X29, PPC::X30, PPC::X31,
178
179    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
180    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
181    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
182    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
183    PPC::F30, PPC::F31,
184
185    PPC::CR2, PPC::CR3, PPC::CR4,
186    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
187    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
188    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
189
190    PPC::LR8,  0
191  };
192
193  if (Subtarget.isMachoABI())
194    return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
195                                 Macho32_CalleeSavedRegs;
196
197  // ELF 32.
198  return ELF32_CalleeSavedRegs;
199}
200
201const TargetRegisterClass* const*
202PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
203  // 32-bit Macho calling convention.
204  static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
205                       &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
206    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
207    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
208    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
209    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
210
211    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
212    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
213    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
214    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
215    &PPC::F8RCRegClass,&PPC::F8RCRegClass,
216
217    &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
218
219    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
220    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
221    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
222
223    &PPC::GPRCRegClass, 0
224  };
225
226  static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
227                       &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
228    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
229    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
230    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
231    &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
232
233                                                             &PPC::F8RCRegClass,
234    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
235    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
236    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
237    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
238    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
239    &PPC::F8RCRegClass,&PPC::F8RCRegClass,
240
241    &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
242
243    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
244    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
245    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
246
247    &PPC::GPRCRegClass, 0
248  };
249
250  // 64-bit Macho calling convention.
251  static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
252    &PPC::G8RCRegClass,&PPC::G8RCRegClass,
253    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
254    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
255    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
256    &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
257
258    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
259    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
260    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
261    &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
262    &PPC::F8RCRegClass,&PPC::F8RCRegClass,
263
264    &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
265
266    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
267    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
268    &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
269
270    &PPC::G8RCRegClass, 0
271  };
272
273  if (Subtarget.isMachoABI())
274    return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
275                                 Macho32_CalleeSavedRegClasses;
276
277  // ELF 32.
278  return ELF32_CalleeSavedRegClasses;
279}
280
281// needsFP - Return true if the specified function should have a dedicated frame
282// pointer register.  This is true if the function has variable sized allocas or
283// if frame pointer elimination is disabled.
284//
285static bool needsFP(const MachineFunction &MF) {
286  const MachineFrameInfo *MFI = MF.getFrameInfo();
287  return NoFramePointerElim || MFI->hasVarSizedObjects();
288}
289
290static bool spillsCR(const MachineFunction &MF) {
291  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
292  return FuncInfo->isCRSpilled();
293}
294
295BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
296  BitVector Reserved(getNumRegs());
297  Reserved.set(PPC::R0);
298  Reserved.set(PPC::R1);
299  Reserved.set(PPC::LR);
300  Reserved.set(PPC::LR8);
301
302  // In Linux, r2 is reserved for the OS.
303  if (!Subtarget.isDarwin())
304    Reserved.set(PPC::R2);
305
306  // On PPC64, r13 is the thread pointer. Never allocate this register. Note
307  // that this is over conservative, as it also prevents allocation of R31 when
308  // the FP is not needed.
309  if (Subtarget.isPPC64()) {
310    Reserved.set(PPC::R13);
311    Reserved.set(PPC::R31);
312
313    Reserved.set(PPC::R0);      // FIXME (64-bit): Remove
314
315    Reserved.set(PPC::X0);
316    Reserved.set(PPC::X1);
317    Reserved.set(PPC::X13);
318    Reserved.set(PPC::X31);
319  }
320
321  if (needsFP(MF))
322    Reserved.set(PPC::R31);
323
324  return Reserved;
325}
326
327//===----------------------------------------------------------------------===//
328// Stack Frame Processing methods
329//===----------------------------------------------------------------------===//
330
331// hasFP - Return true if the specified function actually has a dedicated frame
332// pointer register.  This is true if the function needs a frame pointer and has
333// a non-zero stack size.
334bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
335  const MachineFrameInfo *MFI = MF.getFrameInfo();
336  return MFI->getStackSize() && needsFP(MF);
337}
338
339/// MustSaveLR - Return true if this function requires that we save the LR
340/// register onto the stack in the prolog and restore it in the epilog of the
341/// function.
342static bool MustSaveLR(const MachineFunction &MF) {
343  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
344
345  // We need an save/restore of LR if there is any use/def of LR explicitly, or
346  // if there is some use of the LR stack slot (e.g. for builtin_return_address.
347  return MFI->usesLR() || MFI->isLRStoreRequired() ||
348         // FIXME: Anything that has a call should clobber the LR register,
349         // isn't this redundant??
350         MF.getFrameInfo()->hasCalls();
351}
352
353void PPCRegisterInfo::
354eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
355                              MachineBasicBlock::iterator I) const {
356  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
357  MBB.erase(I);
358}
359
360/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
361/// register first and then a spilled callee-saved register if that fails.
362static
363unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
364                             const TargetRegisterClass *RC, int SPAdj) {
365  assert(RS && "Register scavenging must be on");
366  unsigned Reg = RS->FindUnusedReg(RC, true);
367  // FIXME: move ARM callee-saved reg scan to target independent code, then
368  // search for already spilled CS register here.
369  if (Reg == 0)
370    Reg = RS->scavengeRegister(RC, II, SPAdj);
371  return Reg;
372}
373
374/// lowerDynamicAlloc - Generate the code for allocating an object in the
375/// current frame.  The sequence of code with be in the general form
376///
377///   addi   R0, SP, #frameSize ; get the address of the previous frame
378///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
379///   addi   Rnew, SP, #maxCalFrameSize ; get the top of the allocation
380///
381void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
382                                        int SPAdj, RegScavenger *RS) const {
383  // Get the instruction.
384  MachineInstr &MI = *II;
385  // Get the instruction's basic block.
386  MachineBasicBlock &MBB = *MI.getParent();
387  // Get the basic block's function.
388  MachineFunction &MF = *MBB.getParent();
389  // Get the frame info.
390  MachineFrameInfo *MFI = MF.getFrameInfo();
391  // Determine whether 64-bit pointers are used.
392  bool LP64 = Subtarget.isPPC64();
393
394  // Get the maximum call stack size.
395  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
396  // Get the total frame size.
397  unsigned FrameSize = MFI->getStackSize();
398
399  // Get stack alignments.
400  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
401  unsigned MaxAlign = MFI->getMaxAlignment();
402  assert(MaxAlign <= TargetAlign &&
403         "Dynamic alloca with large aligns not supported");
404
405  // Determine the previous frame's address.  If FrameSize can't be
406  // represented as 16 bits or we need special alignment, then we load the
407  // previous frame's address from 0(SP).  Why not do an addis of the hi?
408  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
409  // Constructing the constant and adding would take 3 instructions.
410  // Fortunately, a frame greater than 32K is rare.
411  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
412  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
413  const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
414
415  // FIXME (64-bit): Use "findScratchRegister"
416  unsigned Reg;
417  if (!LP64)
418    Reg = findScratchRegister(II, RS, RC, SPAdj);
419  else
420    Reg = PPC::R0;
421
422  if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
423    BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
424      .addReg(PPC::R31)
425      .addImm(FrameSize);
426  } else if (LP64) {
427    Reg = PPC::X0;              // FIXME (64-bit): Remove.
428    BuildMI(MBB, II, TII.get(PPC::LD), Reg)
429      .addImm(0)
430      .addReg(PPC::X1);
431  } else {
432    BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
433      .addImm(0)
434      .addReg(PPC::R1);
435  }
436
437  // Grow the stack and update the stack pointer link, then determine the
438  // address of new allocated space.
439  if (LP64) {
440#if 0                           // FIXME (64-bit): Enable
441    BuildMI(MBB, II, TII.get(PPC::STDUX))
442      .addReg(Reg, false, false, true)
443      .addReg(PPC::X1)
444      .addReg(MI.getOperand(1).getReg());
445#else
446    BuildMI(MBB, II, TII.get(PPC::STDUX))
447      .addReg(PPC::X0, false, false, true)
448      .addReg(PPC::X1)
449      .addReg(MI.getOperand(1).getReg());
450#endif
451
452    if (!MI.getOperand(1).isKill())
453      BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
454	.addReg(PPC::X1)
455	.addImm(maxCallFrameSize);
456    else
457      // Implicitly kill the register.
458      BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
459	.addReg(PPC::X1)
460	.addImm(maxCallFrameSize)
461	.addReg(MI.getOperand(1).getReg(), false, true, true);
462  } else {
463    BuildMI(MBB, II, TII.get(PPC::STWUX))
464      .addReg(Reg, false, false, true)
465      .addReg(PPC::R1)
466      .addReg(MI.getOperand(1).getReg());
467
468    if (!MI.getOperand(1).isKill())
469      BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
470	.addReg(PPC::R1)
471	.addImm(maxCallFrameSize);
472    else
473      // Implicitly kill the register.
474      BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
475	.addReg(PPC::R1)
476	.addImm(maxCallFrameSize)
477	.addReg(MI.getOperand(1).getReg(), false, true, true);
478  }
479
480  // Discard the DYNALLOC instruction.
481  MBB.erase(II);
482}
483
484/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
485/// reserving a whole register (R0), we scrounge for one here. This generates
486/// code like this:
487///
488///   mfcr rA                  ; Move the conditional register into GPR rA.
489///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
490///   stw rA, FI               ; Store rA to the frame.
491///
492void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
493                                      unsigned FrameIndex, int SPAdj,
494                                      RegScavenger *RS) const {
495  // Get the instruction.
496  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>, <FI>
497  // Get the instruction's basic block.
498  MachineBasicBlock &MBB = *MI.getParent();
499
500  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
501  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
502  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
503  unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
504
505  // We need to store the CR in the low 4-bits of the saved value.  First, issue
506  // an MFCR to save all of the CRBits.
507  if (!MI.getOperand(0).isKill())
508    BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
509  else
510    // Implicitly kill the CR register.
511    BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
512      .addReg(MI.getOperand(0).getReg(), false, true, true);
513
514  // If the saved register wasn't CR0, shift the bits left so that they are in
515  // CR0's slot.
516  unsigned SrcReg = MI.getOperand(0).getReg();
517  if (SrcReg != PPC::CR0)
518    // rlwinm rA, rA, ShiftBits, 0, 31.
519    BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
520      .addReg(Reg, false, false, true)
521      .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
522      .addImm(0)
523      .addImm(31);
524
525  addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
526                    .addReg(Reg, false, false, MI.getOperand(1).getImm()),
527                    FrameIndex);
528
529  // Discard the pseudo instruction.
530  MBB.erase(II);
531}
532
533void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
534                                          int SPAdj, RegScavenger *RS) const {
535  assert(SPAdj == 0 && "Unexpected");
536
537  // Get the instruction.
538  MachineInstr &MI = *II;
539  // Get the instruction's basic block.
540  MachineBasicBlock &MBB = *MI.getParent();
541  // Get the basic block's function.
542  MachineFunction &MF = *MBB.getParent();
543  // Get the frame info.
544  MachineFrameInfo *MFI = MF.getFrameInfo();
545
546  // Find out which operand is the frame index.
547  unsigned FIOperandNo = 0;
548  while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
549    ++FIOperandNo;
550    assert(FIOperandNo != MI.getNumOperands() &&
551           "Instr doesn't have FrameIndex operand!");
552  }
553  // Take into account whether it's an add or mem instruction
554  unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
555  if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
556    OffsetOperandNo = FIOperandNo-1;
557
558  // Get the frame index.
559  int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
560
561  // Get the frame pointer save index.  Users of this index are primarily
562  // DYNALLOC instructions.
563  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
564  int FPSI = FI->getFramePointerSaveIndex();
565  // Get the instruction opcode.
566  unsigned OpC = MI.getOpcode();
567
568  // Special case for dynamic alloca.
569  if (FPSI && FrameIndex == FPSI &&
570      (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
571    lowerDynamicAlloc(II, SPAdj, RS);
572    return;
573  }
574
575  // Special case for pseudo-op SPILL_CR.
576  if (!Subtarget.isPPC64())     // FIXME (64-bit): Remove.
577  if (OpC == PPC::SPILL_CR) {
578    lowerCRSpilling(II, FrameIndex, SPAdj, RS);
579    return;
580  }
581
582  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
583  MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
584                                              false);
585
586  // Figure out if the offset in the instruction is shifted right two bits. This
587  // is true for instructions like "STD", which the machine implicitly adds two
588  // low zeros to.
589  bool isIXAddr = false;
590  switch (OpC) {
591  case PPC::LWA:
592  case PPC::LD:
593  case PPC::STD:
594  case PPC::STD_32:
595    isIXAddr = true;
596    break;
597  }
598
599  // Now add the frame object offset to the offset from r1.
600  int Offset = MFI->getObjectOffset(FrameIndex);
601  if (!isIXAddr)
602    Offset += MI.getOperand(OffsetOperandNo).getImm();
603  else
604    Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
605
606  // If we're not using a Frame Pointer that has been set to the value of the
607  // SP before having the stack size subtracted from it, then add the stack size
608  // to Offset to get the correct offset.
609  Offset += MFI->getStackSize();
610
611  // If we can, encode the offset directly into the instruction.  If this is a
612  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
613  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
614  // clear can be encoded.  This is extremely uncommon, because normally you
615  // only "std" to a stack slot that is at least 4-byte aligned, but it can
616  // happen in invalid code.
617  if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
618    if (isIXAddr)
619      Offset >>= 2;    // The actual encoded value has the low two bits zero.
620    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
621    return;
622  }
623
624  // The offset doesn't fit into a single register, scavenge one to build the
625  // offset in.
626  // FIXME: figure out what SPAdj is doing here.
627
628  // FIXME (64-bit): Use "findScratchRegister".
629  unsigned SReg;
630  if (!Subtarget.isPPC64())
631    SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
632  else
633    SReg = PPC::R0;
634
635  // Insert a set of rA with the full offset value before the ld, st, or add
636  BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
637    .addImm(Offset >> 16);
638  BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
639    .addReg(SReg, false, false, true)
640    .addImm(Offset);
641
642  // Convert into indexed form of the instruction:
643  //
644  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
645  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
646  unsigned OperandBase;
647
648  if (OpC != TargetInstrInfo::INLINEASM) {
649    assert(ImmToIdxMap.count(OpC) &&
650           "No indexed form of load or store available!");
651    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
652    MI.setDesc(TII.get(NewOpcode));
653    OperandBase = 1;
654  } else {
655    OperandBase = OffsetOperandNo;
656  }
657
658  unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
659  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
660  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
661}
662
663/// VRRegNo - Map from a numbered VR register to its enum value.
664///
665static const unsigned short VRRegNo[] = {
666 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
667 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
668 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
669 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
670};
671
672/// RemoveVRSaveCode - We have found that this function does not need any code
673/// to manipulate the VRSAVE register, even though it uses vector registers.
674/// This can happen when the only registers used are known to be live in or out
675/// of the function.  Remove all of the VRSAVE related code from the function.
676static void RemoveVRSaveCode(MachineInstr *MI) {
677  MachineBasicBlock *Entry = MI->getParent();
678  MachineFunction *MF = Entry->getParent();
679
680  // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
681  MachineBasicBlock::iterator MBBI = MI;
682  ++MBBI;
683  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
684  MBBI->eraseFromParent();
685
686  bool RemovedAllMTVRSAVEs = true;
687  // See if we can find and remove the MTVRSAVE instruction from all of the
688  // epilog blocks.
689  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
690    // If last instruction is a return instruction, add an epilogue
691    if (!I->empty() && I->back().getDesc().isReturn()) {
692      bool FoundIt = false;
693      for (MBBI = I->end(); MBBI != I->begin(); ) {
694        --MBBI;
695        if (MBBI->getOpcode() == PPC::MTVRSAVE) {
696          MBBI->eraseFromParent();  // remove it.
697          FoundIt = true;
698          break;
699        }
700      }
701      RemovedAllMTVRSAVEs &= FoundIt;
702    }
703  }
704
705  // If we found and removed all MTVRSAVE instructions, remove the read of
706  // VRSAVE as well.
707  if (RemovedAllMTVRSAVEs) {
708    MBBI = MI;
709    assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
710    --MBBI;
711    assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
712    MBBI->eraseFromParent();
713  }
714
715  // Finally, nuke the UPDATE_VRSAVE.
716  MI->eraseFromParent();
717}
718
719// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
720// instruction selector.  Based on the vector registers that have been used,
721// transform this into the appropriate ORI instruction.
722static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
723  MachineFunction *MF = MI->getParent()->getParent();
724
725  unsigned UsedRegMask = 0;
726  for (unsigned i = 0; i != 32; ++i)
727    if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
728      UsedRegMask |= 1 << (31-i);
729
730  // Live in and live out values already must be in the mask, so don't bother
731  // marking them.
732  for (MachineRegisterInfo::livein_iterator
733       I = MF->getRegInfo().livein_begin(),
734       E = MF->getRegInfo().livein_end(); I != E; ++I) {
735    unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
736    if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
737      UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
738  }
739  for (MachineRegisterInfo::liveout_iterator
740       I = MF->getRegInfo().liveout_begin(),
741       E = MF->getRegInfo().liveout_end(); I != E; ++I) {
742    unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
743    if (VRRegNo[RegNo] == *I)              // If this really is a vector reg.
744      UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
745  }
746
747  // If no registers are used, turn this into a copy.
748  if (UsedRegMask == 0) {
749    // Remove all VRSAVE code.
750    RemoveVRSaveCode(MI);
751    return;
752  }
753
754  unsigned SrcReg = MI->getOperand(1).getReg();
755  unsigned DstReg = MI->getOperand(0).getReg();
756
757  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
758    if (DstReg != SrcReg)
759      BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
760        .addReg(SrcReg)
761        .addImm(UsedRegMask);
762    else
763      BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
764        .addReg(SrcReg, false, false, true)
765        .addImm(UsedRegMask);
766  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
767    if (DstReg != SrcReg)
768      BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
769        .addReg(SrcReg)
770        .addImm(UsedRegMask >> 16);
771    else
772      BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
773        .addReg(SrcReg, false, false, true)
774        .addImm(UsedRegMask >> 16);
775  } else {
776    if (DstReg != SrcReg)
777      BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
778        .addReg(SrcReg)
779        .addImm(UsedRegMask >> 16);
780    else
781      BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
782        .addReg(SrcReg, false, false, true)
783        .addImm(UsedRegMask >> 16);
784
785    BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
786      .addReg(DstReg, false, false, true)
787      .addImm(UsedRegMask & 0xFFFF);
788  }
789
790  // Remove the old UPDATE_VRSAVE instruction.
791  MI->eraseFromParent();
792}
793
794/// determineFrameLayout - Determine the size of the frame and maximum call
795/// frame size.
796void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
797  MachineFrameInfo *MFI = MF.getFrameInfo();
798
799  // Get the number of bytes to allocate from the FrameInfo
800  unsigned FrameSize = MFI->getStackSize();
801
802  // Get the alignments provided by the target, and the maximum alignment
803  // (if any) of the fixed frame objects.
804  unsigned MaxAlign = MFI->getMaxAlignment();
805  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
806  unsigned AlignMask = TargetAlign - 1;  //
807
808  // If we are a leaf function, and use up to 224 bytes of stack space,
809  // don't have a frame pointer, calls, or dynamic alloca then we do not need
810  // to adjust the stack pointer (we fit in the Red Zone).
811  if (FrameSize <= 224 &&             // Fits in red zone.
812      !MFI->hasVarSizedObjects() &&   // No dynamic alloca.
813      !MFI->hasCalls() &&             // No calls.
814      MaxAlign <= TargetAlign) {      // No special alignment.
815    // No need for frame
816    MFI->setStackSize(0);
817    return;
818  }
819
820  // Get the maximum call frame size of all the calls.
821  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
822
823  // Maximum call frame needs to be at least big enough for linkage and 8 args.
824  unsigned minCallFrameSize =
825    PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
826                                      Subtarget.isMachoABI());
827  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
828
829  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
830  // that allocations will be aligned.
831  if (MFI->hasVarSizedObjects())
832    maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
833
834  // Update maximum call frame size.
835  MFI->setMaxCallFrameSize(maxCallFrameSize);
836
837  // Include call frame size in total.
838  FrameSize += maxCallFrameSize;
839
840  // Make sure the frame is aligned.
841  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
842
843  // Update frame info.
844  MFI->setStackSize(FrameSize);
845}
846
847void
848PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
849                                                      RegScavenger *RS) const {
850  //  Save and clear the LR state.
851  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
852  unsigned LR = getRARegister();
853  FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
854  MF.getRegInfo().setPhysRegUnused(LR);
855
856  //  Save R31 if necessary
857  int FPSI = FI->getFramePointerSaveIndex();
858  bool IsPPC64 = Subtarget.isPPC64();
859  bool IsELF32_ABI = Subtarget.isELF32_ABI();
860  bool IsMachoABI  = Subtarget.isMachoABI();
861  MachineFrameInfo *MFI = MF.getFrameInfo();
862
863  // If the frame pointer save index hasn't been defined yet.
864  if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
865      IsELF32_ABI) {
866    // Find out what the fix offset of the frame pointer save area.
867    int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
868                                                           IsMachoABI);
869    // Allocate the frame index for frame pointer save area.
870    FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
871    // Save the result.
872    FI->setFramePointerSaveIndex(FPSI);
873  }
874
875  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
876  // a large stack, which will require scavenging a register to materialize a
877  // large offset.
878  // FIXME: this doesn't actually check stack size, so is a bit pessimistic
879  // FIXME: doesn't detect whether or not we need to spill vXX, which requires
880  //        r0 for now.
881
882  if (!IsPPC64)                 // FIXME (64-bit): Enable.
883  if (needsFP(MF) || spillsCR(MF)) {
884    const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
885    const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
886    const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
887    RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
888                                                       RC->getAlignment()));
889  }
890}
891
892void
893PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
894  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
895  MachineBasicBlock::iterator MBBI = MBB.begin();
896  MachineFrameInfo *MFI = MF.getFrameInfo();
897  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
898
899  // Prepare for frame info.
900  unsigned FrameLabelId = 0;
901
902  // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
903  // process it.
904  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
905    if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
906      HandleVRSaveUpdate(MBBI, TII);
907      break;
908    }
909  }
910
911  // Move MBBI back to the beginning of the function.
912  MBBI = MBB.begin();
913
914  // Work out frame sizes.
915  determineFrameLayout(MF);
916  unsigned FrameSize = MFI->getStackSize();
917
918  int NegFrameSize = -FrameSize;
919
920  // Get processor type.
921  bool IsPPC64 = Subtarget.isPPC64();
922  // Get operating system
923  bool IsMachoABI = Subtarget.isMachoABI();
924  // Check if the link register (LR) has been used.
925  bool UsesLR = MustSaveLR(MF);
926  // Do we have a frame pointer for this function?
927  bool HasFP = hasFP(MF) && FrameSize;
928
929  int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
930  int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
931
932  if (IsPPC64) {
933    if (UsesLR)
934      BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
935
936    if (HasFP)
937      BuildMI(MBB, MBBI, TII.get(PPC::STD))
938        .addReg(PPC::X31)
939        .addImm(FPOffset/4)
940        .addReg(PPC::X1);
941
942    if (UsesLR)
943      BuildMI(MBB, MBBI, TII.get(PPC::STD))
944        .addReg(PPC::X0)
945        .addImm(LROffset / 4)
946        .addReg(PPC::X1);
947  } else {
948    if (UsesLR)
949      BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
950
951    if (HasFP)
952      BuildMI(MBB, MBBI, TII.get(PPC::STW))
953        .addReg(PPC::R31)
954        .addImm(FPOffset)
955        .addReg(PPC::R1);
956
957    if (UsesLR)
958      BuildMI(MBB, MBBI, TII.get(PPC::STW))
959        .addReg(PPC::R0)
960        .addImm(LROffset)
961        .addReg(PPC::R1);
962  }
963
964  // Skip if a leaf routine.
965  if (!FrameSize) return;
966
967  // Get stack alignments.
968  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
969  unsigned MaxAlign = MFI->getMaxAlignment();
970
971  if (MMI && MMI->needsFrameInfo()) {
972    // Mark effective beginning of when frame pointer becomes valid.
973    FrameLabelId = MMI->NextLabelID();
974    BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
975  }
976
977  // Adjust stack pointer: r1 += NegFrameSize.
978  // If there is a preferred stack alignment, align R1 now
979  if (!IsPPC64) {
980    // PPC32.
981    if (MaxAlign > TargetAlign) {
982      assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
983      assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
984
985      BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
986        .addReg(PPC::R1)
987        .addImm(0)
988        .addImm(32 - Log2_32(MaxAlign))
989        .addImm(31);
990      BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
991        .addReg(PPC::R0, false, false, true)
992        .addImm(NegFrameSize);
993      BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
994        .addReg(PPC::R1)
995        .addReg(PPC::R1)
996        .addReg(PPC::R0);
997    } else if (isInt16(NegFrameSize)) {
998      BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
999        .addReg(PPC::R1)
1000        .addImm(NegFrameSize)
1001        .addReg(PPC::R1);
1002    } else {
1003      BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1004        .addImm(NegFrameSize >> 16);
1005      BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1006        .addReg(PPC::R0, false, false, true)
1007        .addImm(NegFrameSize & 0xFFFF);
1008      BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1009        .addReg(PPC::R1)
1010        .addReg(PPC::R1)
1011        .addReg(PPC::R0);
1012    }
1013  } else {    // PPC64.
1014    if (MaxAlign > TargetAlign) {
1015      assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1016      assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1017
1018      BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1019        .addReg(PPC::X1)
1020        .addImm(0)
1021        .addImm(64 - Log2_32(MaxAlign));
1022      BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1023        .addReg(PPC::X0)
1024        .addImm(NegFrameSize);
1025      BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1026        .addReg(PPC::X1)
1027        .addReg(PPC::X1)
1028        .addReg(PPC::X0);
1029    } else if (isInt16(NegFrameSize)) {
1030      BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1031        .addReg(PPC::X1)
1032        .addImm(NegFrameSize / 4)
1033        .addReg(PPC::X1);
1034    } else {
1035      BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1036        .addImm(NegFrameSize >> 16);
1037      BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1038        .addReg(PPC::X0, false, false, true)
1039        .addImm(NegFrameSize & 0xFFFF);
1040      BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1041        .addReg(PPC::X1)
1042        .addReg(PPC::X1)
1043        .addReg(PPC::X0);
1044    }
1045  }
1046
1047  if (MMI && MMI->needsFrameInfo()) {
1048    std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1049
1050    if (NegFrameSize) {
1051      // Show update of SP.
1052      MachineLocation SPDst(MachineLocation::VirtualFP);
1053      MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1054      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1055    } else {
1056      MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1057      Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1058    }
1059
1060    if (HasFP) {
1061      MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1062      MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1063      Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1064    }
1065
1066    // Add callee saved registers to move list.
1067    const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1068    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1069      int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1070      unsigned Reg = CSI[I].getReg();
1071      if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1072      MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1073      MachineLocation CSSrc(Reg);
1074      Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1075    }
1076
1077    MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1078    MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1079    Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1080
1081    // Mark effective beginning of when frame pointer is ready.
1082    unsigned ReadyLabelId = MMI->NextLabelID();
1083    BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1084
1085    MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1086                                  (IsPPC64 ? PPC::X1 : PPC::R1));
1087    MachineLocation FPSrc(MachineLocation::VirtualFP);
1088    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1089  }
1090
1091  // If there is a frame pointer, copy R1 into R31
1092  if (HasFP) {
1093    if (!IsPPC64) {
1094      BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1095        .addReg(PPC::R1)
1096        .addReg(PPC::R1);
1097    } else {
1098      BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1099        .addReg(PPC::X1)
1100        .addReg(PPC::X1);
1101    }
1102  }
1103}
1104
1105void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1106                                   MachineBasicBlock &MBB) const {
1107  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1108  assert(MBBI->getOpcode() == PPC::BLR &&
1109         "Can only insert epilog into returning blocks");
1110
1111  // Get alignment info so we know how to restore r1
1112  const MachineFrameInfo *MFI = MF.getFrameInfo();
1113  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1114  unsigned MaxAlign = MFI->getMaxAlignment();
1115
1116  // Get the number of bytes allocated from the FrameInfo.
1117  unsigned FrameSize = MFI->getStackSize();
1118
1119  // Get processor type.
1120  bool IsPPC64 = Subtarget.isPPC64();
1121  // Get operating system
1122  bool IsMachoABI = Subtarget.isMachoABI();
1123  // Check if the link register (LR) has been used.
1124  bool UsesLR = MustSaveLR(MF);
1125  // Do we have a frame pointer for this function?
1126  bool HasFP = hasFP(MF) && FrameSize;
1127
1128  int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1129  int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1130
1131  if (FrameSize) {
1132    // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1133    // on entry to the function.  Add this offset back now.
1134    if (!Subtarget.isPPC64()) {
1135      if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1136            !MFI->hasVarSizedObjects()) {
1137          BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1138              .addReg(PPC::R1).addImm(FrameSize);
1139      } else {
1140        BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1141      }
1142    } else {
1143      if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1144            !MFI->hasVarSizedObjects()) {
1145        BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1146           .addReg(PPC::X1).addImm(FrameSize);
1147      } else {
1148        BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1149      }
1150    }
1151  }
1152
1153  if (IsPPC64) {
1154    if (UsesLR)
1155      BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1156        .addImm(LROffset/4).addReg(PPC::X1);
1157
1158    if (HasFP)
1159      BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1160        .addImm(FPOffset/4).addReg(PPC::X1);
1161
1162    if (UsesLR)
1163      BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1164  } else {
1165    if (UsesLR)
1166      BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1167          .addImm(LROffset).addReg(PPC::R1);
1168
1169    if (HasFP)
1170      BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1171          .addImm(FPOffset).addReg(PPC::R1);
1172
1173    if (UsesLR)
1174      BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1175  }
1176}
1177
1178unsigned PPCRegisterInfo::getRARegister() const {
1179  return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1180}
1181
1182unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1183  if (!Subtarget.isPPC64())
1184    return hasFP(MF) ? PPC::R31 : PPC::R1;
1185  else
1186    return hasFP(MF) ? PPC::X31 : PPC::X1;
1187}
1188
1189void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1190                                                                         const {
1191  // Initial state of the frame pointer is R1.
1192  MachineLocation Dst(MachineLocation::VirtualFP);
1193  MachineLocation Src(PPC::R1, 0);
1194  Moves.push_back(MachineMove(0, Dst, Src));
1195}
1196
1197unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1198  return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1199}
1200
1201unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1202  return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1203}
1204
1205int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1206  // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1207  return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1208}
1209
1210#include "PPCGenRegisterInfo.inc"
1211
1212