PPCRegisterInfo.cpp revision b92187a4103dca24c3767c380f63593d1f6161a7
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetRegisterInfo 11// class. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "reginfo" 16#include "PPC.h" 17#include "PPCInstrBuilder.h" 18#include "PPCMachineFunctionInfo.h" 19#include "PPCRegisterInfo.h" 20#include "PPCFrameInfo.h" 21#include "PPCSubtarget.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/Function.h" 25#include "llvm/Type.h" 26#include "llvm/CodeGen/ValueTypes.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineLocation.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/RegisterScavenging.h" 34#include "llvm/Target/TargetFrameInfo.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/Support/CommandLine.h" 39#include "llvm/Support/Debug.h" 40#include "llvm/Support/ErrorHandling.h" 41#include "llvm/Support/MathExtras.h" 42#include "llvm/Support/raw_ostream.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/STLExtras.h" 45#include <cstdlib> 46 47// FIXME This disables some code that aligns the stack to a boundary 48// bigger than the default (16 bytes on Darwin) when there is a stack local 49// of greater alignment. This does not currently work, because the delta 50// between old and new stack pointers is added to offsets that reference 51// incoming parameters after the prolog is generated, and the code that 52// does that doesn't handle a variable delta. You don't want to do that 53// anyway; a better approach is to reserve another register that retains 54// to the incoming stack pointer, and reference parameters relative to that. 55#define ALIGN_STACK 0 56 57// FIXME (64-bit): Eventually enable by default. 58namespace llvm { 59cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 60 cl::init(false), 61 cl::desc("Enable PPC32 register scavenger"), 62 cl::Hidden); 63cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 64 cl::init(false), 65 cl::desc("Enable PPC64 register scavenger"), 66 cl::Hidden); 67} 68 69using namespace llvm; 70 71#define EnableRegisterScavenging \ 72 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 73 (EnablePPC64RS && Subtarget.isPPC64())) 74 75// FIXME (64-bit): Should be inlined. 76bool 77PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 78 return EnableRegisterScavenging; 79} 80 81/// getRegisterNumbering - Given the enum value for some register, e.g. 82/// PPC::F14, return the number that it corresponds to (e.g. 14). 83unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 84 using namespace PPC; 85 switch (RegEnum) { 86 case 0: return 0; 87 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 88 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 89 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 90 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 91 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 92 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 93 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 94 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 95 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 96 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 97 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 98 case R11: case X11: case F11: case V11: case CR2UN: return 11; 99 case R12: case X12: case F12: case V12: case CR3LT: return 12; 100 case R13: case X13: case F13: case V13: case CR3GT: return 13; 101 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 102 case R15: case X15: case F15: case V15: case CR3UN: return 15; 103 case R16: case X16: case F16: case V16: case CR4LT: return 16; 104 case R17: case X17: case F17: case V17: case CR4GT: return 17; 105 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 106 case R19: case X19: case F19: case V19: case CR4UN: return 19; 107 case R20: case X20: case F20: case V20: case CR5LT: return 20; 108 case R21: case X21: case F21: case V21: case CR5GT: return 21; 109 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 110 case R23: case X23: case F23: case V23: case CR5UN: return 23; 111 case R24: case X24: case F24: case V24: case CR6LT: return 24; 112 case R25: case X25: case F25: case V25: case CR6GT: return 25; 113 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 114 case R27: case X27: case F27: case V27: case CR6UN: return 27; 115 case R28: case X28: case F28: case V28: case CR7LT: return 28; 116 case R29: case X29: case F29: case V29: case CR7GT: return 29; 117 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 118 case R31: case X31: case F31: case V31: case CR7UN: return 31; 119 default: 120 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 121 } 122} 123 124PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 125 const TargetInstrInfo &tii) 126 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 127 Subtarget(ST), TII(tii) { 128 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 129 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 130 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 131 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 132 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 133 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 134 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 135 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 136 137 // 64-bit 138 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 139 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 140 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 141 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 142 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 143} 144 145/// getPointerRegClass - Return the register class to use to hold pointers. 146/// This is used for addressing modes. 147const TargetRegisterClass * 148PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 149 if (Subtarget.isPPC64()) 150 return &PPC::G8RCRegClass; 151 return &PPC::GPRCRegClass; 152} 153 154const unsigned* 155PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 156 // 32-bit Darwin calling convention. 157 static const unsigned Darwin32_CalleeSavedRegs[] = { 158 PPC::R13, PPC::R14, PPC::R15, 159 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 160 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 161 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 162 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 163 164 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 165 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 166 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 167 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 168 PPC::F30, PPC::F31, 169 170 PPC::CR2, PPC::CR3, PPC::CR4, 171 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 172 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 173 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 174 175 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 176 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 177 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 178 179 PPC::LR, 0 180 }; 181 182 // 32-bit SVR4 calling convention. 183 static const unsigned SVR4_CalleeSavedRegs[] = { 184 PPC::R14, PPC::R15, 185 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 186 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 187 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 188 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 189 190 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 191 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 192 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 193 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 194 PPC::F30, PPC::F31, 195 196 PPC::CR2, PPC::CR3, PPC::CR4, 197 198 PPC::VRSAVE, 199 200 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 201 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 202 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 203 204 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 205 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 206 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 207 208 0 209 }; 210 // 64-bit Darwin calling convention. 211 static const unsigned Darwin64_CalleeSavedRegs[] = { 212 PPC::X14, PPC::X15, 213 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 214 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 215 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 216 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 217 218 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 219 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 220 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 221 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 222 PPC::F30, PPC::F31, 223 224 PPC::CR2, PPC::CR3, PPC::CR4, 225 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 226 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 227 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 228 229 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 230 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 231 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 232 233 PPC::LR8, 0 234 }; 235 236 // 64-bit SVR4 calling convention. 237 static const unsigned SVR4_64_CalleeSavedRegs[] = { 238 PPC::X14, PPC::X15, 239 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 240 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 241 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 242 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 243 244 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 245 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 246 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 247 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 248 PPC::F30, PPC::F31, 249 250 PPC::CR2, PPC::CR3, PPC::CR4, 251 252 PPC::VRSAVE, 253 254 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 255 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 256 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 257 258 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 259 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 260 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 261 262 0 263 }; 264 265 if (Subtarget.isDarwinABI()) 266 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 267 Darwin32_CalleeSavedRegs; 268 269 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 270} 271 272const TargetRegisterClass* const* 273PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 274 // 32-bit Darwin calling convention. 275 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 276 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 277 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 278 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 279 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 280 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 281 282 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 283 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 284 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 285 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 286 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 287 288 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 289 290 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 291 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 292 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 293 294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 295 &PPC::CRBITRCRegClass, 296 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 297 &PPC::CRBITRCRegClass, 298 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 299 &PPC::CRBITRCRegClass, 300 301 &PPC::GPRCRegClass, 0 302 }; 303 304 // 32-bit SVR4 calling convention. 305 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = { 306 &PPC::GPRCRegClass,&PPC::GPRCRegClass, 307 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 308 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 309 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 310 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 311 312 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 313 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 314 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 315 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 316 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 317 318 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 319 320 &PPC::VRSAVERCRegClass, 321 322 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 323 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 324 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 325 326 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 327 &PPC::CRBITRCRegClass, 328 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 329 &PPC::CRBITRCRegClass, 330 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 331 &PPC::CRBITRCRegClass, 332 333 0 334 }; 335 336 // 64-bit Darwin calling convention. 337 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 338 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 339 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 340 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 341 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 342 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 343 344 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 345 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 346 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 347 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 348 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 349 350 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 351 352 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 353 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 354 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 355 356 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 357 &PPC::CRBITRCRegClass, 358 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 359 &PPC::CRBITRCRegClass, 360 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 361 &PPC::CRBITRCRegClass, 362 363 &PPC::G8RCRegClass, 0 364 }; 365 366 // 64-bit SVR4 calling convention. 367 static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = { 368 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 369 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 370 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 371 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 372 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 373 374 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 375 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 376 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 377 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 378 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 379 380 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 381 382 &PPC::VRSAVERCRegClass, 383 384 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 385 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 386 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 387 388 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 389 &PPC::CRBITRCRegClass, 390 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 391 &PPC::CRBITRCRegClass, 392 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 393 &PPC::CRBITRCRegClass, 394 395 0 396 }; 397 398 if (Subtarget.isDarwinABI()) 399 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 400 Darwin32_CalleeSavedRegClasses; 401 402 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses 403 : SVR4_CalleeSavedRegClasses; 404} 405 406// needsFP - Return true if the specified function should have a dedicated frame 407// pointer register. This is true if the function has variable sized allocas or 408// if frame pointer elimination is disabled. 409// 410static bool needsFP(const MachineFunction &MF) { 411 const MachineFrameInfo *MFI = MF.getFrameInfo(); 412 // Naked functions have no stack frame pushed, so we don't have a frame pointer. 413 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 414 return false; 415 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || 416 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 417} 418 419static bool spillsCR(const MachineFunction &MF) { 420 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 421 return FuncInfo->isCRSpilled(); 422} 423 424BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 425 BitVector Reserved(getNumRegs()); 426 Reserved.set(PPC::R0); 427 Reserved.set(PPC::R1); 428 Reserved.set(PPC::LR); 429 Reserved.set(PPC::LR8); 430 Reserved.set(PPC::RM); 431 432 // The SVR4 ABI reserves r2 and r13 433 if (Subtarget.isSVR4ABI()) { 434 Reserved.set(PPC::R2); // System-reserved register 435 Reserved.set(PPC::R13); // Small Data Area pointer register 436 } 437 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 438 // when the stack frame is too big to address directly; we need two regs. 439 // This is a hack. 440 if (Subtarget.isDarwinABI()) { 441 Reserved.set(PPC::R2); 442 } 443 444 // On PPC64, r13 is the thread pointer. Never allocate this register. 445 // Note that this is over conservative, as it also prevents allocation of R31 446 // when the FP is not needed. 447 if (Subtarget.isPPC64()) { 448 Reserved.set(PPC::R13); 449 Reserved.set(PPC::R31); 450 451 if (!EnableRegisterScavenging) 452 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 453 454 Reserved.set(PPC::X0); 455 Reserved.set(PPC::X1); 456 Reserved.set(PPC::X13); 457 Reserved.set(PPC::X31); 458 459 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 460 if (Subtarget.isSVR4ABI()) { 461 Reserved.set(PPC::X2); 462 } 463 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 464 // when the stack frame is too big to address directly; we need two regs. 465 // This is a hack. 466 if (Subtarget.isDarwinABI()) { 467 Reserved.set(PPC::X2); 468 } 469 } 470 471 if (needsFP(MF)) 472 Reserved.set(PPC::R31); 473 474 return Reserved; 475} 476 477//===----------------------------------------------------------------------===// 478// Stack Frame Processing methods 479//===----------------------------------------------------------------------===// 480 481// hasFP - Return true if the specified function actually has a dedicated frame 482// pointer register. This is true if the function needs a frame pointer and has 483// a non-zero stack size. 484bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 485 const MachineFrameInfo *MFI = MF.getFrameInfo(); 486 return MFI->getStackSize() && needsFP(MF); 487} 488 489/// MustSaveLR - Return true if this function requires that we save the LR 490/// register onto the stack in the prolog and restore it in the epilog of the 491/// function. 492static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 493 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 494 495 // We need a save/restore of LR if there is any def of LR (which is 496 // defined by calls, including the PIC setup sequence), or if there is 497 // some use of the LR stack slot (e.g. for builtin_return_address). 498 // (LR comes in 32 and 64 bit versions.) 499 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 500 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 501} 502 503 504 505void PPCRegisterInfo:: 506eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 507 MachineBasicBlock::iterator I) const { 508 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 509 // Add (actually subtract) back the amount the callee popped on return. 510 if (int CalleeAmt = I->getOperand(1).getImm()) { 511 bool is64Bit = Subtarget.isPPC64(); 512 CalleeAmt *= -1; 513 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 514 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 515 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 516 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 517 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 518 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 519 MachineInstr *MI = I; 520 DebugLoc dl = MI->getDebugLoc(); 521 522 if (isInt<16>(CalleeAmt)) { 523 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 524 addImm(CalleeAmt); 525 } else { 526 MachineBasicBlock::iterator MBBI = I; 527 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 528 .addImm(CalleeAmt >> 16); 529 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 530 .addReg(TmpReg, RegState::Kill) 531 .addImm(CalleeAmt & 0xFFFF); 532 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 533 .addReg(StackReg) 534 .addReg(StackReg) 535 .addReg(TmpReg); 536 } 537 } 538 } 539 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 540 MBB.erase(I); 541} 542 543/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 544/// register first and then a spilled callee-saved register if that fails. 545static 546unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 547 const TargetRegisterClass *RC, int SPAdj) { 548 assert(RS && "Register scavenging must be on"); 549 unsigned Reg = RS->FindUnusedReg(RC); 550 // FIXME: move ARM callee-saved reg scan to target independent code, then 551 // search for already spilled CS register here. 552 if (Reg == 0) 553 Reg = RS->scavengeRegister(RC, II, SPAdj); 554 return Reg; 555} 556 557/// lowerDynamicAlloc - Generate the code for allocating an object in the 558/// current frame. The sequence of code with be in the general form 559/// 560/// addi R0, SP, \#frameSize ; get the address of the previous frame 561/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 562/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 563/// 564void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 565 int SPAdj, RegScavenger *RS) const { 566 // Get the instruction. 567 MachineInstr &MI = *II; 568 // Get the instruction's basic block. 569 MachineBasicBlock &MBB = *MI.getParent(); 570 // Get the basic block's function. 571 MachineFunction &MF = *MBB.getParent(); 572 // Get the frame info. 573 MachineFrameInfo *MFI = MF.getFrameInfo(); 574 // Determine whether 64-bit pointers are used. 575 bool LP64 = Subtarget.isPPC64(); 576 DebugLoc dl = MI.getDebugLoc(); 577 578 // Get the maximum call stack size. 579 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 580 // Get the total frame size. 581 unsigned FrameSize = MFI->getStackSize(); 582 583 // Get stack alignments. 584 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 585 unsigned MaxAlign = MFI->getMaxAlignment(); 586 assert(MaxAlign <= TargetAlign && 587 "Dynamic alloca with large aligns not supported"); 588 589 // Determine the previous frame's address. If FrameSize can't be 590 // represented as 16 bits or we need special alignment, then we load the 591 // previous frame's address from 0(SP). Why not do an addis of the hi? 592 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 593 // Constructing the constant and adding would take 3 instructions. 594 // Fortunately, a frame greater than 32K is rare. 595 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 596 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 597 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 598 599 // FIXME (64-bit): Use "findScratchRegister" 600 unsigned Reg; 601 if (EnableRegisterScavenging) 602 Reg = findScratchRegister(II, RS, RC, SPAdj); 603 else 604 Reg = PPC::R0; 605 606 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 607 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 608 .addReg(PPC::R31) 609 .addImm(FrameSize); 610 } else if (LP64) { 611 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 612 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 613 .addImm(0) 614 .addReg(PPC::X1); 615 else 616 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 617 .addImm(0) 618 .addReg(PPC::X1); 619 } else { 620 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 621 .addImm(0) 622 .addReg(PPC::R1); 623 } 624 625 // Grow the stack and update the stack pointer link, then determine the 626 // address of new allocated space. 627 if (LP64) { 628 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 629 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 630 .addReg(Reg, RegState::Kill) 631 .addReg(PPC::X1) 632 .addReg(MI.getOperand(1).getReg()); 633 else 634 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 635 .addReg(PPC::X0, RegState::Kill) 636 .addReg(PPC::X1) 637 .addReg(MI.getOperand(1).getReg()); 638 639 if (!MI.getOperand(1).isKill()) 640 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 641 .addReg(PPC::X1) 642 .addImm(maxCallFrameSize); 643 else 644 // Implicitly kill the register. 645 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 646 .addReg(PPC::X1) 647 .addImm(maxCallFrameSize) 648 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 649 } else { 650 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 651 .addReg(Reg, RegState::Kill) 652 .addReg(PPC::R1) 653 .addReg(MI.getOperand(1).getReg()); 654 655 if (!MI.getOperand(1).isKill()) 656 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 657 .addReg(PPC::R1) 658 .addImm(maxCallFrameSize); 659 else 660 // Implicitly kill the register. 661 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 662 .addReg(PPC::R1) 663 .addImm(maxCallFrameSize) 664 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 665 } 666 667 // Discard the DYNALLOC instruction. 668 MBB.erase(II); 669} 670 671/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 672/// reserving a whole register (R0), we scrounge for one here. This generates 673/// code like this: 674/// 675/// mfcr rA ; Move the conditional register into GPR rA. 676/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 677/// stw rA, FI ; Store rA to the frame. 678/// 679void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 680 unsigned FrameIndex, int SPAdj, 681 RegScavenger *RS) const { 682 // Get the instruction. 683 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 684 // Get the instruction's basic block. 685 MachineBasicBlock &MBB = *MI.getParent(); 686 DebugLoc dl = MI.getDebugLoc(); 687 688 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 689 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 690 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 691 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 692 693 // We need to store the CR in the low 4-bits of the saved value. First, issue 694 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 695 if (!MI.getOperand(0).isKill()) 696 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg); 697 else 698 // Implicitly kill the CR register. 699 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) 700 .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill); 701 702 // If the saved register wasn't CR0, shift the bits left so that they are in 703 // CR0's slot. 704 unsigned SrcReg = MI.getOperand(0).getReg(); 705 if (SrcReg != PPC::CR0) 706 // rlwinm rA, rA, ShiftBits, 0, 31. 707 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 708 .addReg(Reg, RegState::Kill) 709 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 710 .addImm(0) 711 .addImm(31); 712 713 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 714 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 715 FrameIndex); 716 717 // Discard the pseudo instruction. 718 MBB.erase(II); 719} 720 721unsigned 722PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 723 int SPAdj, FrameIndexValue *Value, 724 RegScavenger *RS) const { 725 assert(SPAdj == 0 && "Unexpected"); 726 727 // Get the instruction. 728 MachineInstr &MI = *II; 729 // Get the instruction's basic block. 730 MachineBasicBlock &MBB = *MI.getParent(); 731 // Get the basic block's function. 732 MachineFunction &MF = *MBB.getParent(); 733 // Get the frame info. 734 MachineFrameInfo *MFI = MF.getFrameInfo(); 735 DebugLoc dl = MI.getDebugLoc(); 736 737 // Find out which operand is the frame index. 738 unsigned FIOperandNo = 0; 739 while (!MI.getOperand(FIOperandNo).isFI()) { 740 ++FIOperandNo; 741 assert(FIOperandNo != MI.getNumOperands() && 742 "Instr doesn't have FrameIndex operand!"); 743 } 744 // Take into account whether it's an add or mem instruction 745 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 746 if (MI.isInlineAsm()) 747 OffsetOperandNo = FIOperandNo-1; 748 749 // Get the frame index. 750 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 751 752 // Get the frame pointer save index. Users of this index are primarily 753 // DYNALLOC instructions. 754 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 755 int FPSI = FI->getFramePointerSaveIndex(); 756 // Get the instruction opcode. 757 unsigned OpC = MI.getOpcode(); 758 759 // Special case for dynamic alloca. 760 if (FPSI && FrameIndex == FPSI && 761 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 762 lowerDynamicAlloc(II, SPAdj, RS); 763 return 0; 764 } 765 766 // Special case for pseudo-op SPILL_CR. 767 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 768 if (OpC == PPC::SPILL_CR) { 769 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 770 return 0; 771 } 772 773 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 774 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 775 false); 776 777 // Figure out if the offset in the instruction is shifted right two bits. This 778 // is true for instructions like "STD", which the machine implicitly adds two 779 // low zeros to. 780 bool isIXAddr = false; 781 switch (OpC) { 782 case PPC::LWA: 783 case PPC::LD: 784 case PPC::STD: 785 case PPC::STD_32: 786 isIXAddr = true; 787 break; 788 } 789 790 // Now add the frame object offset to the offset from r1. 791 int Offset = MFI->getObjectOffset(FrameIndex); 792 if (!isIXAddr) 793 Offset += MI.getOperand(OffsetOperandNo).getImm(); 794 else 795 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 796 797 // If we're not using a Frame Pointer that has been set to the value of the 798 // SP before having the stack size subtracted from it, then add the stack size 799 // to Offset to get the correct offset. 800 // Naked functions have stack size 0, although getStackSize may not reflect that 801 // because we didn't call all the pieces that compute it for naked functions. 802 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 803 Offset += MFI->getStackSize(); 804 805 // If we can, encode the offset directly into the instruction. If this is a 806 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 807 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 808 // clear can be encoded. This is extremely uncommon, because normally you 809 // only "std" to a stack slot that is at least 4-byte aligned, but it can 810 // happen in invalid code. 811 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 812 if (isIXAddr) 813 Offset >>= 2; // The actual encoded value has the low two bits zero. 814 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 815 return 0; 816 } 817 818 // The offset doesn't fit into a single register, scavenge one to build the 819 // offset in. 820 // FIXME: figure out what SPAdj is doing here. 821 822 // FIXME (64-bit): Use "findScratchRegister". 823 unsigned SReg; 824 if (EnableRegisterScavenging) 825 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 826 else 827 SReg = PPC::R0; 828 829 // Insert a set of rA with the full offset value before the ld, st, or add 830 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 831 .addImm(Offset >> 16); 832 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 833 .addReg(SReg, RegState::Kill) 834 .addImm(Offset); 835 836 // Convert into indexed form of the instruction: 837 // 838 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 839 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 840 unsigned OperandBase; 841 842 if (OpC != TargetOpcode::INLINEASM) { 843 assert(ImmToIdxMap.count(OpC) && 844 "No indexed form of load or store available!"); 845 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 846 MI.setDesc(TII.get(NewOpcode)); 847 OperandBase = 1; 848 } else { 849 OperandBase = OffsetOperandNo; 850 } 851 852 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 853 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 854 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 855 return 0; 856} 857 858/// VRRegNo - Map from a numbered VR register to its enum value. 859/// 860static const unsigned short VRRegNo[] = { 861 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 862 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 863 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 864 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 865}; 866 867/// RemoveVRSaveCode - We have found that this function does not need any code 868/// to manipulate the VRSAVE register, even though it uses vector registers. 869/// This can happen when the only registers used are known to be live in or out 870/// of the function. Remove all of the VRSAVE related code from the function. 871static void RemoveVRSaveCode(MachineInstr *MI) { 872 MachineBasicBlock *Entry = MI->getParent(); 873 MachineFunction *MF = Entry->getParent(); 874 875 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 876 MachineBasicBlock::iterator MBBI = MI; 877 ++MBBI; 878 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 879 MBBI->eraseFromParent(); 880 881 bool RemovedAllMTVRSAVEs = true; 882 // See if we can find and remove the MTVRSAVE instruction from all of the 883 // epilog blocks. 884 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 885 // If last instruction is a return instruction, add an epilogue 886 if (!I->empty() && I->back().getDesc().isReturn()) { 887 bool FoundIt = false; 888 for (MBBI = I->end(); MBBI != I->begin(); ) { 889 --MBBI; 890 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 891 MBBI->eraseFromParent(); // remove it. 892 FoundIt = true; 893 break; 894 } 895 } 896 RemovedAllMTVRSAVEs &= FoundIt; 897 } 898 } 899 900 // If we found and removed all MTVRSAVE instructions, remove the read of 901 // VRSAVE as well. 902 if (RemovedAllMTVRSAVEs) { 903 MBBI = MI; 904 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 905 --MBBI; 906 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 907 MBBI->eraseFromParent(); 908 } 909 910 // Finally, nuke the UPDATE_VRSAVE. 911 MI->eraseFromParent(); 912} 913 914// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 915// instruction selector. Based on the vector registers that have been used, 916// transform this into the appropriate ORI instruction. 917static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 918 MachineFunction *MF = MI->getParent()->getParent(); 919 DebugLoc dl = MI->getDebugLoc(); 920 921 unsigned UsedRegMask = 0; 922 for (unsigned i = 0; i != 32; ++i) 923 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 924 UsedRegMask |= 1 << (31-i); 925 926 // Live in and live out values already must be in the mask, so don't bother 927 // marking them. 928 for (MachineRegisterInfo::livein_iterator 929 I = MF->getRegInfo().livein_begin(), 930 E = MF->getRegInfo().livein_end(); I != E; ++I) { 931 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 932 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 933 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 934 } 935 for (MachineRegisterInfo::liveout_iterator 936 I = MF->getRegInfo().liveout_begin(), 937 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 938 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 939 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 940 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 941 } 942 943 // If no registers are used, turn this into a copy. 944 if (UsedRegMask == 0) { 945 // Remove all VRSAVE code. 946 RemoveVRSaveCode(MI); 947 return; 948 } 949 950 unsigned SrcReg = MI->getOperand(1).getReg(); 951 unsigned DstReg = MI->getOperand(0).getReg(); 952 953 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 954 if (DstReg != SrcReg) 955 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 956 .addReg(SrcReg) 957 .addImm(UsedRegMask); 958 else 959 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 960 .addReg(SrcReg, RegState::Kill) 961 .addImm(UsedRegMask); 962 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 963 if (DstReg != SrcReg) 964 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 965 .addReg(SrcReg) 966 .addImm(UsedRegMask >> 16); 967 else 968 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 969 .addReg(SrcReg, RegState::Kill) 970 .addImm(UsedRegMask >> 16); 971 } else { 972 if (DstReg != SrcReg) 973 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 974 .addReg(SrcReg) 975 .addImm(UsedRegMask >> 16); 976 else 977 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 978 .addReg(SrcReg, RegState::Kill) 979 .addImm(UsedRegMask >> 16); 980 981 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 982 .addReg(DstReg, RegState::Kill) 983 .addImm(UsedRegMask & 0xFFFF); 984 } 985 986 // Remove the old UPDATE_VRSAVE instruction. 987 MI->eraseFromParent(); 988} 989 990/// determineFrameLayout - Determine the size of the frame and maximum call 991/// frame size. 992void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 993 MachineFrameInfo *MFI = MF.getFrameInfo(); 994 995 // Get the number of bytes to allocate from the FrameInfo 996 unsigned FrameSize = MFI->getStackSize(); 997 998 // Get the alignments provided by the target, and the maximum alignment 999 // (if any) of the fixed frame objects. 1000 unsigned MaxAlign = MFI->getMaxAlignment(); 1001 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1002 unsigned AlignMask = TargetAlign - 1; // 1003 1004 // If we are a leaf function, and use up to 224 bytes of stack space, 1005 // don't have a frame pointer, calls, or dynamic alloca then we do not need 1006 // to adjust the stack pointer (we fit in the Red Zone). 1007 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 1008 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 1009 if (!DisableRedZone && 1010 FrameSize <= 224 && // Fits in red zone. 1011 !MFI->hasVarSizedObjects() && // No dynamic alloca. 1012 !MFI->adjustsStack() && // No calls. 1013 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 1014 // No need for frame 1015 MFI->setStackSize(0); 1016 return; 1017 } 1018 1019 // Get the maximum call frame size of all the calls. 1020 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 1021 1022 // Maximum call frame needs to be at least big enough for linkage and 8 args. 1023 unsigned minCallFrameSize = 1024 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 1025 Subtarget.isDarwinABI()); 1026 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 1027 1028 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 1029 // that allocations will be aligned. 1030 if (MFI->hasVarSizedObjects()) 1031 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 1032 1033 // Update maximum call frame size. 1034 MFI->setMaxCallFrameSize(maxCallFrameSize); 1035 1036 // Include call frame size in total. 1037 FrameSize += maxCallFrameSize; 1038 1039 // Make sure the frame is aligned. 1040 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 1041 1042 // Update frame info. 1043 MFI->setStackSize(FrameSize); 1044} 1045 1046void 1047PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1048 RegScavenger *RS) const { 1049 // Save and clear the LR state. 1050 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1051 unsigned LR = getRARegister(); 1052 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1053 MF.getRegInfo().setPhysRegUnused(LR); 1054 1055 // Save R31 if necessary 1056 int FPSI = FI->getFramePointerSaveIndex(); 1057 bool isPPC64 = Subtarget.isPPC64(); 1058 bool isDarwinABI = Subtarget.isDarwinABI(); 1059 MachineFrameInfo *MFI = MF.getFrameInfo(); 1060 1061 // If the frame pointer save index hasn't been defined yet. 1062 if (!FPSI && needsFP(MF)) { 1063 // Find out what the fix offset of the frame pointer save area. 1064 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 1065 isDarwinABI); 1066 // Allocate the frame index for frame pointer save area. 1067 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, 1068 true, false); 1069 // Save the result. 1070 FI->setFramePointerSaveIndex(FPSI); 1071 } 1072 1073 // Reserve stack space to move the linkage area to in case of a tail call. 1074 int TCSPDelta = 0; 1075 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1076 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, 1077 true, false); 1078 } 1079 1080 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1081 // a large stack, which will require scavenging a register to materialize a 1082 // large offset. 1083 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 1084 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 1085 // r0 for now. 1086 1087 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 1088 if (needsFP(MF) || spillsCR(MF)) { 1089 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1090 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1091 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 1092 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1093 RC->getAlignment(), 1094 false)); 1095 } 1096} 1097 1098void 1099PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 1100 const { 1101 // Early exit if not using the SVR4 ABI. 1102 if (!Subtarget.isSVR4ABI()) { 1103 return; 1104 } 1105 1106 // Get callee saved register information. 1107 MachineFrameInfo *FFI = MF.getFrameInfo(); 1108 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1109 1110 // Early exit if no callee saved registers are modified! 1111 if (CSI.empty() && !needsFP(MF)) { 1112 return; 1113 } 1114 1115 unsigned MinGPR = PPC::R31; 1116 unsigned MinG8R = PPC::X31; 1117 unsigned MinFPR = PPC::F31; 1118 unsigned MinVR = PPC::V31; 1119 1120 bool HasGPSaveArea = false; 1121 bool HasG8SaveArea = false; 1122 bool HasFPSaveArea = false; 1123 bool HasCRSaveArea = false; 1124 bool HasVRSAVESaveArea = false; 1125 bool HasVRSaveArea = false; 1126 1127 SmallVector<CalleeSavedInfo, 18> GPRegs; 1128 SmallVector<CalleeSavedInfo, 18> G8Regs; 1129 SmallVector<CalleeSavedInfo, 18> FPRegs; 1130 SmallVector<CalleeSavedInfo, 18> VRegs; 1131 1132 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1133 unsigned Reg = CSI[i].getReg(); 1134 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1135 1136 if (RC == PPC::GPRCRegisterClass) { 1137 HasGPSaveArea = true; 1138 1139 GPRegs.push_back(CSI[i]); 1140 1141 if (Reg < MinGPR) { 1142 MinGPR = Reg; 1143 } 1144 } else if (RC == PPC::G8RCRegisterClass) { 1145 HasG8SaveArea = true; 1146 1147 G8Regs.push_back(CSI[i]); 1148 1149 if (Reg < MinG8R) { 1150 MinG8R = Reg; 1151 } 1152 } else if (RC == PPC::F8RCRegisterClass) { 1153 HasFPSaveArea = true; 1154 1155 FPRegs.push_back(CSI[i]); 1156 1157 if (Reg < MinFPR) { 1158 MinFPR = Reg; 1159 } 1160// FIXME SVR4: Disable CR save area for now. 1161 } else if ( RC == PPC::CRBITRCRegisterClass 1162 || RC == PPC::CRRCRegisterClass) { 1163// HasCRSaveArea = true; 1164 } else if (RC == PPC::VRSAVERCRegisterClass) { 1165 HasVRSAVESaveArea = true; 1166 } else if (RC == PPC::VRRCRegisterClass) { 1167 HasVRSaveArea = true; 1168 1169 VRegs.push_back(CSI[i]); 1170 1171 if (Reg < MinVR) { 1172 MinVR = Reg; 1173 } 1174 } else { 1175 llvm_unreachable("Unknown RegisterClass!"); 1176 } 1177 } 1178 1179 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1180 1181 int64_t LowerBound = 0; 1182 1183 // Take into account stack space reserved for tail calls. 1184 int TCSPDelta = 0; 1185 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1186 LowerBound = TCSPDelta; 1187 } 1188 1189 // The Floating-point register save area is right below the back chain word 1190 // of the previous stack frame. 1191 if (HasFPSaveArea) { 1192 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1193 int FI = FPRegs[i].getFrameIdx(); 1194 1195 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1196 } 1197 1198 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; 1199 } 1200 1201 // Check whether the frame pointer register is allocated. If so, make sure it 1202 // is spilled to the correct offset. 1203 if (needsFP(MF)) { 1204 HasGPSaveArea = true; 1205 1206 int FI = PFI->getFramePointerSaveIndex(); 1207 assert(FI && "No Frame Pointer Save Slot!"); 1208 1209 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1210 } 1211 1212 // General register save area starts right below the Floating-point 1213 // register save area. 1214 if (HasGPSaveArea || HasG8SaveArea) { 1215 // Move general register save area spill slots down, taking into account 1216 // the size of the Floating-point register save area. 1217 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1218 int FI = GPRegs[i].getFrameIdx(); 1219 1220 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1221 } 1222 1223 // Move general register save area spill slots down, taking into account 1224 // the size of the Floating-point register save area. 1225 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1226 int FI = G8Regs[i].getFrameIdx(); 1227 1228 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1229 } 1230 1231 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR), 1232 getRegisterNumbering(MinG8R)); 1233 1234 if (Subtarget.isPPC64()) { 1235 LowerBound -= (31 - MinReg + 1) * 8; 1236 } else { 1237 LowerBound -= (31 - MinReg + 1) * 4; 1238 } 1239 } 1240 1241 // The CR save area is below the general register save area. 1242 if (HasCRSaveArea) { 1243 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1244 // which have the CR/CRBIT register class? 1245 // Adjust the frame index of the CR spill slot. 1246 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1247 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1248 1249 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) { 1250 int FI = CSI[i].getFrameIdx(); 1251 1252 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1253 } 1254 } 1255 1256 LowerBound -= 4; // The CR save area is always 4 bytes long. 1257 } 1258 1259 if (HasVRSAVESaveArea) { 1260 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1261 // which have the VRSAVE register class? 1262 // Adjust the frame index of the VRSAVE spill slot. 1263 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1264 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1265 1266 if (RC == PPC::VRSAVERCRegisterClass) { 1267 int FI = CSI[i].getFrameIdx(); 1268 1269 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1270 } 1271 } 1272 1273 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1274 } 1275 1276 if (HasVRSaveArea) { 1277 // Insert alignment padding, we need 16-byte alignment. 1278 LowerBound = (LowerBound - 15) & ~(15); 1279 1280 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1281 int FI = VRegs[i].getFrameIdx(); 1282 1283 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1284 } 1285 } 1286} 1287 1288void 1289PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 1290 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 1291 MachineBasicBlock::iterator MBBI = MBB.begin(); 1292 MachineFrameInfo *MFI = MF.getFrameInfo(); 1293 MachineModuleInfo &MMI = MF.getMMI(); 1294 DebugLoc dl; 1295 bool needsFrameMoves = MMI.hasDebugInfo() || 1296 !MF.getFunction()->doesNotThrow() || 1297 UnwindTablesMandatory; 1298 1299 // Prepare for frame info. 1300 MCSymbol *FrameLabel = 0; 1301 1302 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1303 // process it. 1304 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1305 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1306 HandleVRSaveUpdate(MBBI, TII); 1307 break; 1308 } 1309 } 1310 1311 // Move MBBI back to the beginning of the function. 1312 MBBI = MBB.begin(); 1313 1314 // Work out frame sizes. 1315 determineFrameLayout(MF); 1316 unsigned FrameSize = MFI->getStackSize(); 1317 1318 int NegFrameSize = -FrameSize; 1319 1320 // Get processor type. 1321 bool isPPC64 = Subtarget.isPPC64(); 1322 // Get operating system 1323 bool isDarwinABI = Subtarget.isDarwinABI(); 1324 // Check if the link register (LR) must be saved. 1325 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1326 bool MustSaveLR = FI->mustSaveLR(); 1327 // Do we have a frame pointer for this function? 1328 bool HasFP = hasFP(MF) && FrameSize; 1329 1330 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1331 1332 int FPOffset = 0; 1333 if (HasFP) { 1334 if (Subtarget.isSVR4ABI()) { 1335 MachineFrameInfo *FFI = MF.getFrameInfo(); 1336 int FPIndex = FI->getFramePointerSaveIndex(); 1337 assert(FPIndex && "No Frame Pointer Save Slot!"); 1338 FPOffset = FFI->getObjectOffset(FPIndex); 1339 } else { 1340 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1341 } 1342 } 1343 1344 if (isPPC64) { 1345 if (MustSaveLR) 1346 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 1347 1348 if (HasFP) 1349 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1350 .addReg(PPC::X31) 1351 .addImm(FPOffset/4) 1352 .addReg(PPC::X1); 1353 1354 if (MustSaveLR) 1355 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1356 .addReg(PPC::X0) 1357 .addImm(LROffset / 4) 1358 .addReg(PPC::X1); 1359 } else { 1360 if (MustSaveLR) 1361 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 1362 1363 if (HasFP) 1364 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1365 .addReg(PPC::R31) 1366 .addImm(FPOffset) 1367 .addReg(PPC::R1); 1368 1369 if (MustSaveLR) 1370 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1371 .addReg(PPC::R0) 1372 .addImm(LROffset) 1373 .addReg(PPC::R1); 1374 } 1375 1376 // Skip if a leaf routine. 1377 if (!FrameSize) return; 1378 1379 // Get stack alignments. 1380 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1381 unsigned MaxAlign = MFI->getMaxAlignment(); 1382 1383 // Adjust stack pointer: r1 += NegFrameSize. 1384 // If there is a preferred stack alignment, align R1 now 1385 if (!isPPC64) { 1386 // PPC32. 1387 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1388 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 1389 "Invalid alignment!"); 1390 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 1391 1392 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 1393 .addReg(PPC::R1) 1394 .addImm(0) 1395 .addImm(32 - Log2_32(MaxAlign)) 1396 .addImm(31); 1397 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 1398 .addReg(PPC::R0, RegState::Kill) 1399 .addImm(NegFrameSize); 1400 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1401 .addReg(PPC::R1) 1402 .addReg(PPC::R1) 1403 .addReg(PPC::R0); 1404 } else if (isInt<16>(NegFrameSize)) { 1405 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 1406 .addReg(PPC::R1) 1407 .addImm(NegFrameSize) 1408 .addReg(PPC::R1); 1409 } else { 1410 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1411 .addImm(NegFrameSize >> 16); 1412 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1413 .addReg(PPC::R0, RegState::Kill) 1414 .addImm(NegFrameSize & 0xFFFF); 1415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1416 .addReg(PPC::R1) 1417 .addReg(PPC::R1) 1418 .addReg(PPC::R0); 1419 } 1420 } else { // PPC64. 1421 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1422 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 1423 "Invalid alignment!"); 1424 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 1425 1426 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 1427 .addReg(PPC::X1) 1428 .addImm(0) 1429 .addImm(64 - Log2_32(MaxAlign)); 1430 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 1431 .addReg(PPC::X0) 1432 .addImm(NegFrameSize); 1433 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1434 .addReg(PPC::X1) 1435 .addReg(PPC::X1) 1436 .addReg(PPC::X0); 1437 } else if (isInt<16>(NegFrameSize)) { 1438 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 1439 .addReg(PPC::X1) 1440 .addImm(NegFrameSize / 4) 1441 .addReg(PPC::X1); 1442 } else { 1443 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1444 .addImm(NegFrameSize >> 16); 1445 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1446 .addReg(PPC::X0, RegState::Kill) 1447 .addImm(NegFrameSize & 0xFFFF); 1448 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1449 .addReg(PPC::X1) 1450 .addReg(PPC::X1) 1451 .addReg(PPC::X0); 1452 } 1453 } 1454 1455 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 1456 1457 // Add the "machine moves" for the instructions we generated above, but in 1458 // reverse order. 1459 if (needsFrameMoves) { 1460 // Mark effective beginning of when frame pointer becomes valid. 1461 FrameLabel = MMI.getContext().CreateTempSymbol(); 1462 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(FrameLabel); 1463 1464 // Show update of SP. 1465 if (NegFrameSize) { 1466 MachineLocation SPDst(MachineLocation::VirtualFP); 1467 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1468 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 1469 } else { 1470 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 1471 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 1472 } 1473 1474 if (HasFP) { 1475 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1476 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 1477 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 1478 } 1479 1480 if (MustSaveLR) { 1481 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1482 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 1483 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 1484 } 1485 } 1486 1487 MCSymbol *ReadyLabel = 0; 1488 1489 // If there is a frame pointer, copy R1 into R31 1490 if (HasFP) { 1491 if (!isPPC64) { 1492 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 1493 .addReg(PPC::R1) 1494 .addReg(PPC::R1); 1495 } else { 1496 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 1497 .addReg(PPC::X1) 1498 .addReg(PPC::X1); 1499 } 1500 1501 if (needsFrameMoves) { 1502 ReadyLabel = MMI.getContext().CreateTempSymbol(); 1503 1504 // Mark effective beginning of when frame pointer is ready. 1505 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(ReadyLabel); 1506 1507 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 1508 (isPPC64 ? PPC::X1 : PPC::R1)); 1509 MachineLocation FPSrc(MachineLocation::VirtualFP); 1510 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 1511 } 1512 } 1513 1514 if (needsFrameMoves) { 1515 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 1516 1517 // Add callee saved registers to move list. 1518 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1519 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1520 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1521 unsigned Reg = CSI[I].getReg(); 1522 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1523 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1524 MachineLocation CSSrc(Reg); 1525 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 1526 } 1527 } 1528} 1529 1530void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1531 MachineBasicBlock &MBB) const { 1532 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1533 unsigned RetOpcode = MBBI->getOpcode(); 1534 DebugLoc dl; 1535 1536 assert( (RetOpcode == PPC::BLR || 1537 RetOpcode == PPC::TCRETURNri || 1538 RetOpcode == PPC::TCRETURNdi || 1539 RetOpcode == PPC::TCRETURNai || 1540 RetOpcode == PPC::TCRETURNri8 || 1541 RetOpcode == PPC::TCRETURNdi8 || 1542 RetOpcode == PPC::TCRETURNai8) && 1543 "Can only insert epilog into returning blocks"); 1544 1545 // Get alignment info so we know how to restore r1 1546 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1547 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1548 unsigned MaxAlign = MFI->getMaxAlignment(); 1549 1550 // Get the number of bytes allocated from the FrameInfo. 1551 int FrameSize = MFI->getStackSize(); 1552 1553 // Get processor type. 1554 bool isPPC64 = Subtarget.isPPC64(); 1555 // Get operating system 1556 bool isDarwinABI = Subtarget.isDarwinABI(); 1557 // Check if the link register (LR) has been saved. 1558 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1559 bool MustSaveLR = FI->mustSaveLR(); 1560 // Do we have a frame pointer for this function? 1561 bool HasFP = hasFP(MF) && FrameSize; 1562 1563 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1564 1565 int FPOffset = 0; 1566 if (HasFP) { 1567 if (Subtarget.isSVR4ABI()) { 1568 MachineFrameInfo *FFI = MF.getFrameInfo(); 1569 int FPIndex = FI->getFramePointerSaveIndex(); 1570 assert(FPIndex && "No Frame Pointer Save Slot!"); 1571 FPOffset = FFI->getObjectOffset(FPIndex); 1572 } else { 1573 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1574 } 1575 } 1576 1577 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1578 RetOpcode == PPC::TCRETURNdi || 1579 RetOpcode == PPC::TCRETURNai || 1580 RetOpcode == PPC::TCRETURNri8 || 1581 RetOpcode == PPC::TCRETURNdi8 || 1582 RetOpcode == PPC::TCRETURNai8; 1583 1584 if (UsesTCRet) { 1585 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1586 MachineOperand &StackAdjust = MBBI->getOperand(1); 1587 assert(StackAdjust.isImm() && "Expecting immediate value."); 1588 // Adjust stack pointer. 1589 int StackAdj = StackAdjust.getImm(); 1590 int Delta = StackAdj - MaxTCRetDelta; 1591 assert((Delta >= 0) && "Delta must be positive"); 1592 if (MaxTCRetDelta>0) 1593 FrameSize += (StackAdj +Delta); 1594 else 1595 FrameSize += StackAdj; 1596 } 1597 1598 if (FrameSize) { 1599 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1600 // on entry to the function. Add this offset back now. 1601 if (!isPPC64) { 1602 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1603 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1604 // call which invalidates the stack pointer value in SP(0). So we use the 1605 // value of R31 in this case. 1606 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 1607 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1608 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1609 .addReg(PPC::R31).addImm(FrameSize); 1610 } else if(FI->hasFastCall()) { 1611 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1612 .addImm(FrameSize >> 16); 1613 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1614 .addReg(PPC::R0, RegState::Kill) 1615 .addImm(FrameSize & 0xFFFF); 1616 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 1617 .addReg(PPC::R1) 1618 .addReg(PPC::R31) 1619 .addReg(PPC::R0); 1620 } else if (isInt<16>(FrameSize) && 1621 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1622 !MFI->hasVarSizedObjects()) { 1623 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1624 .addReg(PPC::R1).addImm(FrameSize); 1625 } else { 1626 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 1627 .addImm(0).addReg(PPC::R1); 1628 } 1629 } else { 1630 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 1631 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1632 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1633 .addReg(PPC::X31).addImm(FrameSize); 1634 } else if(FI->hasFastCall()) { 1635 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1636 .addImm(FrameSize >> 16); 1637 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1638 .addReg(PPC::X0, RegState::Kill) 1639 .addImm(FrameSize & 0xFFFF); 1640 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 1641 .addReg(PPC::X1) 1642 .addReg(PPC::X31) 1643 .addReg(PPC::X0); 1644 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 1645 !MFI->hasVarSizedObjects()) { 1646 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1647 .addReg(PPC::X1).addImm(FrameSize); 1648 } else { 1649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 1650 .addImm(0).addReg(PPC::X1); 1651 } 1652 } 1653 } 1654 1655 if (isPPC64) { 1656 if (MustSaveLR) 1657 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 1658 .addImm(LROffset/4).addReg(PPC::X1); 1659 1660 if (HasFP) 1661 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 1662 .addImm(FPOffset/4).addReg(PPC::X1); 1663 1664 if (MustSaveLR) 1665 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1666 } else { 1667 if (MustSaveLR) 1668 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 1669 .addImm(LROffset).addReg(PPC::R1); 1670 1671 if (HasFP) 1672 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 1673 .addImm(FPOffset).addReg(PPC::R1); 1674 1675 if (MustSaveLR) 1676 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 1677 } 1678 1679 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1680 // call optimization 1681 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 1682 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1683 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1684 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1685 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 1686 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1687 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 1688 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 1689 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 1690 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 1691 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 1692 1693 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1694 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 1695 .addReg(StackReg).addImm(CallerAllocatedAmt); 1696 } else { 1697 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1698 .addImm(CallerAllocatedAmt >> 16); 1699 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1700 .addReg(TmpReg, RegState::Kill) 1701 .addImm(CallerAllocatedAmt & 0xFFFF); 1702 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 1703 .addReg(StackReg) 1704 .addReg(FPReg) 1705 .addReg(TmpReg); 1706 } 1707 } else if (RetOpcode == PPC::TCRETURNdi) { 1708 MBBI = prior(MBB.end()); 1709 MachineOperand &JumpTarget = MBBI->getOperand(0); 1710 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1711 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1712 } else if (RetOpcode == PPC::TCRETURNri) { 1713 MBBI = prior(MBB.end()); 1714 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1715 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1716 } else if (RetOpcode == PPC::TCRETURNai) { 1717 MBBI = prior(MBB.end()); 1718 MachineOperand &JumpTarget = MBBI->getOperand(0); 1719 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1720 } else if (RetOpcode == PPC::TCRETURNdi8) { 1721 MBBI = prior(MBB.end()); 1722 MachineOperand &JumpTarget = MBBI->getOperand(0); 1723 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1724 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1725 } else if (RetOpcode == PPC::TCRETURNri8) { 1726 MBBI = prior(MBB.end()); 1727 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1728 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1729 } else if (RetOpcode == PPC::TCRETURNai8) { 1730 MBBI = prior(MBB.end()); 1731 MachineOperand &JumpTarget = MBBI->getOperand(0); 1732 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1733 } 1734} 1735 1736unsigned PPCRegisterInfo::getRARegister() const { 1737 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1738} 1739 1740unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 1741 if (!Subtarget.isPPC64()) 1742 return hasFP(MF) ? PPC::R31 : PPC::R1; 1743 else 1744 return hasFP(MF) ? PPC::X31 : PPC::X1; 1745} 1746 1747void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1748 const { 1749 // Initial state of the frame pointer is R1. 1750 MachineLocation Dst(MachineLocation::VirtualFP); 1751 MachineLocation Src(PPC::R1, 0); 1752 Moves.push_back(MachineMove(0, Dst, Src)); 1753} 1754 1755unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1756 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1757} 1758 1759unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1760 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1761} 1762 1763int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1764 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1765 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1766} 1767 1768#include "PPCGenRegisterInfo.inc" 1769 1770